6651 %}
6652
6653 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6655 ins_cost(150);
6656 size(4);
6657 format %{ "MOV$cmp $icc,$src,$dst" %}
6658 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6659 ins_pipe(ialu_reg);
6660 %}
6661
6662 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6664 ins_cost(140);
6665 size(4);
6666 format %{ "MOV$cmp $icc,$src,$dst" %}
6667 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6668 ins_pipe(ialu_imm);
6669 %}
6670
6671 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6673 ins_cost(150);
6674 size(4);
6675 format %{ "MOV$cmp $icc,$src,$dst" %}
6676 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6677 ins_pipe(ialu_reg);
6678 %}
6679
6680 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6681 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6682 ins_cost(140);
6683 size(4);
6684 format %{ "MOV$cmp $icc,$src,$dst" %}
6685 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6686 ins_pipe(ialu_imm);
6687 %}
6688
6689 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6691 ins_cost(150);
6692 size(4);
6693 format %{ "MOV$cmp $fcc,$src,$dst" %}
6694 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6695 ins_pipe(ialu_reg);
6696 %}
6697
6698 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6699 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6700 ins_cost(140);
6706
6707 // Conditional move for RegN. Only cmov(reg,reg).
6708 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6709 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6710 ins_cost(150);
6711 format %{ "MOV$cmp $pcc,$src,$dst" %}
6712 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6713 ins_pipe(ialu_reg);
6714 %}
6715
6716 // This instruction also works with CmpN so we don't need cmovNN_reg.
6717 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6718 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6719 ins_cost(150);
6720 size(4);
6721 format %{ "MOV$cmp $icc,$src,$dst" %}
6722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6723 ins_pipe(ialu_reg);
6724 %}
6725
6726 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6727 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6728 ins_cost(150);
6729 size(4);
6730 format %{ "MOV$cmp $fcc,$src,$dst" %}
6731 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6732 ins_pipe(ialu_reg);
6733 %}
6734
6735 // Conditional move
6736 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6737 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6738 ins_cost(150);
6739 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6740 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6741 ins_pipe(ialu_reg);
6742 %}
6743
6744 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6745 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6746 ins_cost(140);
6747 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6748 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6749 ins_pipe(ialu_imm);
6750 %}
6751
6752 // This instruction also works with CmpN so we don't need cmovPN_reg.
6753 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6754 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6755 ins_cost(150);
6756
6757 size(4);
6758 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6759 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6760 ins_pipe(ialu_reg);
6761 %}
6762
6763 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6764 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6765 ins_cost(140);
6766
6767 size(4);
6768 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6769 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6770 ins_pipe(ialu_imm);
6771 %}
6772
6773 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6774 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6775 ins_cost(150);
6776 size(4);
6777 format %{ "MOV$cmp $fcc,$src,$dst" %}
6778 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6779 ins_pipe(ialu_imm);
6780 %}
6781
6782 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6783 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6784 ins_cost(140);
6785 size(4);
6786 format %{ "MOV$cmp $fcc,$src,$dst" %}
6787 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6788 ins_pipe(ialu_imm);
6789 %}
6790
6791 // Conditional move
6792 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6793 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6794 ins_cost(150);
6795 opcode(0x101);
6796 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6797 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6798 ins_pipe(int_conditional_float_move);
6799 %}
6800
6801 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6802 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6803 ins_cost(150);
6804
6805 size(4);
6806 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6807 opcode(0x101);
6808 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6809 ins_pipe(int_conditional_float_move);
6810 %}
6811
6812 // Conditional move,
6813 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6814 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6815 ins_cost(150);
6816 size(4);
6817 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6818 opcode(0x1);
6819 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6820 ins_pipe(int_conditional_double_move);
6821 %}
6822
6823 // Conditional move
6824 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6825 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6826 ins_cost(150);
6827 size(4);
6828 opcode(0x102);
6829 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6830 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6831 ins_pipe(int_conditional_double_move);
6832 %}
6833
6834 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6835 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6836 ins_cost(150);
6837
6838 size(4);
6839 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6840 opcode(0x102);
6841 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6842 ins_pipe(int_conditional_double_move);
6843 %}
6844
6845 // Conditional move,
6846 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6847 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6848 ins_cost(150);
6849 size(4);
6850 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6851 opcode(0x2);
6852 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6853 ins_pipe(int_conditional_double_move);
6854 %}
6855
6856 // Conditional move
6857 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6858 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6859 ins_cost(150);
6860 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6861 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6862 ins_pipe(ialu_reg);
6863 %}
6864
6865 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6866 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6867 ins_cost(140);
6868 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6869 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6870 ins_pipe(ialu_imm);
6871 %}
6872
6873 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6874 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6875 ins_cost(150);
6876
6877 size(4);
6878 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6880 ins_pipe(ialu_reg);
6881 %}
6882
6883
6884 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6885 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6886 ins_cost(150);
6887
6888 size(4);
6889 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6890 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6891 ins_pipe(ialu_reg);
6892 %}
6893
6894
6895
|
6651 %}
6652
6653 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6655 ins_cost(150);
6656 size(4);
6657 format %{ "MOV$cmp $icc,$src,$dst" %}
6658 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6659 ins_pipe(ialu_reg);
6660 %}
6661
6662 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6664 ins_cost(140);
6665 size(4);
6666 format %{ "MOV$cmp $icc,$src,$dst" %}
6667 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6668 ins_pipe(ialu_imm);
6669 %}
6670
6671 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6673 ins_cost(150);
6674 size(4);
6675 format %{ "MOV$cmp $icc,$src,$dst" %}
6676 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6677 ins_pipe(ialu_reg);
6678 %}
6679
6680 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6681 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6682 ins_cost(140);
6683 size(4);
6684 format %{ "MOV$cmp $icc,$src,$dst" %}
6685 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6686 ins_pipe(ialu_imm);
6687 %}
6688
6689 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6691 ins_cost(150);
6692 size(4);
6693 format %{ "MOV$cmp $fcc,$src,$dst" %}
6694 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6695 ins_pipe(ialu_reg);
6696 %}
6697
6698 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6699 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6700 ins_cost(140);
6706
6707 // Conditional move for RegN. Only cmov(reg,reg).
6708 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6709 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6710 ins_cost(150);
6711 format %{ "MOV$cmp $pcc,$src,$dst" %}
6712 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6713 ins_pipe(ialu_reg);
6714 %}
6715
6716 // This instruction also works with CmpN so we don't need cmovNN_reg.
6717 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6718 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6719 ins_cost(150);
6720 size(4);
6721 format %{ "MOV$cmp $icc,$src,$dst" %}
6722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6723 ins_pipe(ialu_reg);
6724 %}
6725
6726 // This instruction also works with CmpN so we don't need cmovNN_reg.
6727 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6728 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6729 ins_cost(150);
6730 size(4);
6731 format %{ "MOV$cmp $icc,$src,$dst" %}
6732 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6733 ins_pipe(ialu_reg);
6734 %}
6735
6736 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6737 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6738 ins_cost(150);
6739 size(4);
6740 format %{ "MOV$cmp $fcc,$src,$dst" %}
6741 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6742 ins_pipe(ialu_reg);
6743 %}
6744
6745 // Conditional move
6746 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6747 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6748 ins_cost(150);
6749 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6750 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6755 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6756 ins_cost(140);
6757 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6758 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6759 ins_pipe(ialu_imm);
6760 %}
6761
6762 // This instruction also works with CmpN so we don't need cmovPN_reg.
6763 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6764 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6765 ins_cost(150);
6766
6767 size(4);
6768 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6769 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6770 ins_pipe(ialu_reg);
6771 %}
6772
6773 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6774 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6775 ins_cost(150);
6776
6777 size(4);
6778 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6779 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6780 ins_pipe(ialu_reg);
6781 %}
6782
6783 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6784 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6785 ins_cost(140);
6786
6787 size(4);
6788 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6789 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6790 ins_pipe(ialu_imm);
6791 %}
6792
6793 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6794 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6795 ins_cost(140);
6796
6797 size(4);
6798 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6799 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6800 ins_pipe(ialu_imm);
6801 %}
6802
6803 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6804 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6805 ins_cost(150);
6806 size(4);
6807 format %{ "MOV$cmp $fcc,$src,$dst" %}
6808 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6809 ins_pipe(ialu_imm);
6810 %}
6811
6812 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6813 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6814 ins_cost(140);
6815 size(4);
6816 format %{ "MOV$cmp $fcc,$src,$dst" %}
6817 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6818 ins_pipe(ialu_imm);
6819 %}
6820
6821 // Conditional move
6822 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6823 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6824 ins_cost(150);
6825 opcode(0x101);
6826 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6827 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6828 ins_pipe(int_conditional_float_move);
6829 %}
6830
6831 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6832 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6833 ins_cost(150);
6834
6835 size(4);
6836 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6837 opcode(0x101);
6838 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6839 ins_pipe(int_conditional_float_move);
6840 %}
6841
6842 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6843 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6844 ins_cost(150);
6845
6846 size(4);
6847 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6848 opcode(0x101);
6849 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6850 ins_pipe(int_conditional_float_move);
6851 %}
6852
6853 // Conditional move,
6854 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6855 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6856 ins_cost(150);
6857 size(4);
6858 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6859 opcode(0x1);
6860 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6861 ins_pipe(int_conditional_double_move);
6862 %}
6863
6864 // Conditional move
6865 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6866 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6867 ins_cost(150);
6868 size(4);
6869 opcode(0x102);
6870 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6871 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6872 ins_pipe(int_conditional_double_move);
6873 %}
6874
6875 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6876 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6877 ins_cost(150);
6878
6879 size(4);
6880 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6881 opcode(0x102);
6882 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6883 ins_pipe(int_conditional_double_move);
6884 %}
6885
6886 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6887 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6888 ins_cost(150);
6889
6890 size(4);
6891 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6892 opcode(0x102);
6893 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6894 ins_pipe(int_conditional_double_move);
6895 %}
6896
6897 // Conditional move,
6898 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6899 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6900 ins_cost(150);
6901 size(4);
6902 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6903 opcode(0x2);
6904 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6905 ins_pipe(int_conditional_double_move);
6906 %}
6907
6908 // Conditional move
6909 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6910 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6911 ins_cost(150);
6912 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6914 ins_pipe(ialu_reg);
6915 %}
6916
6917 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6918 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6919 ins_cost(140);
6920 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6921 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6922 ins_pipe(ialu_imm);
6923 %}
6924
6925 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6926 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6927 ins_cost(150);
6928
6929 size(4);
6930 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6931 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6932 ins_pipe(ialu_reg);
6933 %}
6934
6935
6936 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6937 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6938 ins_cost(150);
6939
6940 size(4);
6941 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6942 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(ialu_reg);
6944 %}
6945
6946
6947 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6948 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6949 ins_cost(150);
6950
6951 size(4);
6952 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6953 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6954 ins_pipe(ialu_reg);
6955 %}
6956
6957
6958
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