702 pc = (address) uc->uc_mcontext.gregs[REG_PC]; 703 } 704 705 // unmask current signal 706 sigset_t newset; 707 sigemptyset(&newset); 708 sigaddset(&newset, sig); 709 sigprocmask(SIG_UNBLOCK, &newset, NULL); 710 711 VMError err(t, sig, pc, info, ucVoid); 712 err.report_and_die(); 713 714 ShouldNotReachHere(); 715 } 716 717 void os::print_context(outputStream *st, void *context) { 718 if (context == NULL) return; 719 720 ucontext_t *uc = (ucontext_t*)context; 721 st->print_cr("Registers:"); 722 723 // this is horrendously verbose but the layout of the registers in the 724 // context does not match how we defined our abstract Register set, so 725 // we can't just iterate through the gregs area 726 727 #ifdef AMD64 728 st->print( "RAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RAX]); 729 st->print(", RBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBX]); 730 st->print(", RCX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RCX]); 731 st->print(", RDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDX]); 732 st->cr(); 733 st->print( "RSP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSP]); 734 st->print(", RBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBP]); 735 st->print(", RSI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSI]); 736 st->print(", RDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDI]); 737 st->cr(); 738 st->print( "R8=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R8]); 739 st->print(", R9=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R9]); 740 st->print(", R10=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R10]); 741 st->print(", R11=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R11]); 742 st->cr(); 743 st->print( "R12=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R12]); 744 st->print(", R13=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R13]); 745 st->print(", R14=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R14]); 746 st->print(", R15=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R15]); 747 st->cr(); 748 st->print( "RIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RIP]); 749 st->print(", RFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RFL]); 750 751 st->cr(); 752 st->cr(); 753 754 st->print_cr("Register to memory mapping:"); 755 st->cr(); 756 757 // this is only for the "general purpose" registers 758 759 st->print_cr("RAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RAX]); 760 print_location(st, uc->uc_mcontext.gregs[REG_RAX]); 761 st->cr(); 762 st->print_cr("RBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBX]); 763 print_location(st, uc->uc_mcontext.gregs[REG_RBX]); 764 st->cr(); 765 st->print_cr("RCX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RCX]); 766 print_location(st, uc->uc_mcontext.gregs[REG_RCX]); 767 st->cr(); 768 st->print_cr("RDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDX]); 769 print_location(st, uc->uc_mcontext.gregs[REG_RDX]); 770 st->cr(); 771 st->print_cr("RSP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSP]); 772 print_location(st, uc->uc_mcontext.gregs[REG_RSP]); 773 st->cr(); 774 st->print_cr("RBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBP]); 775 print_location(st, uc->uc_mcontext.gregs[REG_RSP]); 776 st->cr(); 777 st->print_cr("RSI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSI]); 778 print_location(st, uc->uc_mcontext.gregs[REG_RSI]); 779 st->cr(); 780 st->print_cr("RDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDI]); 781 print_location(st, uc->uc_mcontext.gregs[REG_RDI]); 782 st->cr(); 783 st->print_cr("R8 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R8]); 784 print_location(st, uc->uc_mcontext.gregs[REG_R8]); 785 st->cr(); 786 st->print_cr("R9 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R9]); 787 print_location(st, uc->uc_mcontext.gregs[REG_R9]); 788 st->cr(); 789 st->print_cr("R10=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R10]); 790 print_location(st, uc->uc_mcontext.gregs[REG_R10]); 791 st->cr(); 792 st->print_cr("R11=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R11]); 793 print_location(st, uc->uc_mcontext.gregs[REG_R11]); 794 st->cr(); 795 st->print_cr("R12=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R12]); 796 print_location(st, uc->uc_mcontext.gregs[REG_R12]); 797 st->cr(); 798 st->print_cr("R13=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R13]); 799 print_location(st, uc->uc_mcontext.gregs[REG_R13]); 800 st->cr(); 801 st->print_cr("R14=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R14]); 802 print_location(st, uc->uc_mcontext.gregs[REG_R14]); 803 st->cr(); 804 st->print_cr("R15=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R15]); 805 print_location(st, uc->uc_mcontext.gregs[REG_R15]); 806 807 #else 808 st->print( "EAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EAX]); 809 st->print(", EBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBX]); 810 st->print(", ECX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ECX]); 811 st->print(", EDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDX]); 812 st->cr(); 813 st->print( "ESP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[UESP]); 814 st->print(", EBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBP]); 815 st->print(", ESI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ESI]); 816 st->print(", EDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDI]); 817 st->cr(); 818 st->print( "EIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EIP]); 819 st->print(", EFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EFL]); 820 821 st->cr(); 822 st->cr(); 823 824 st->print_cr("Register to memory mapping:"); 825 st->cr(); 826 827 // this is only for the "general purpose" registers 828 829 st->print_cr("EAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EAX]); 830 print_location(st, uc->uc_mcontext.gregs[EAX]); 831 st->cr(); 832 st->print_cr("EBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBX]); 833 print_location(st, uc->uc_mcontext.gregs[EBX]); 834 st->cr(); 835 st->print_cr("ECX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ECX]); 836 print_location(st, uc->uc_mcontext.gregs[ECX]); 837 st->cr(); 838 st->print_cr("EDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDX]); 839 print_location(st, uc->uc_mcontext.gregs[EDX]); 840 st->cr(); 841 st->print_cr("ESP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[UESP]); 842 print_location(st, uc->uc_mcontext.gregs[UESP]); 843 st->cr(); 844 st->print_cr("EBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBP]); 845 print_location(st, uc->uc_mcontext.gregs[EBP]); 846 st->cr(); 847 st->print_cr("ESI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ESI]); 848 print_location(st, uc->uc_mcontext.gregs[ESI]); 849 st->cr(); 850 st->print_cr("EDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDI]); 851 print_location(st, uc->uc_mcontext.gregs[EDI]); 852 853 #endif // AMD64 854 st->cr(); 855 st->cr(); 856 857 intptr_t *sp = (intptr_t *)os::Solaris::ucontext_get_sp(uc); 858 st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", sp); 859 print_hex_dump(st, (address)sp, (address)(sp + 8*sizeof(intptr_t)), sizeof(intptr_t)); 860 st->cr(); 861 862 // Note: it may be unsafe to inspect memory near pc. For example, pc may 863 // point to garbage if entry point in an nmethod is corrupted. Leave 864 // this at the end, and hope for the best. 865 ExtendedPC epc = os::Solaris::ucontext_get_ExtendedPC(uc); 866 address pc = epc.pc(); 867 st->print_cr("Instructions: (pc=" PTR_FORMAT ")", pc); 868 print_hex_dump(st, pc - 16, pc + 16, sizeof(char)); 869 } 870 871 872 #ifdef AMD64 873 void os::Solaris::init_thread_fpu_state(void) { 874 // Nothing to do 875 } 876 #else 877 // From solaris_i486.s 878 extern "C" void fixcw(); 879 880 void os::Solaris::init_thread_fpu_state(void) { 881 // Set fpu to 53 bit precision. This happens too early to use a stub. 882 fixcw(); 883 } 884 885 // These routines are the initial value of atomic_xchg_entry(), 886 // atomic_cmpxchg_entry(), atomic_inc_entry() and fence_entry() 887 // until initialization is complete. 888 // TODO - replace with .il implementation when compiler supports it. 889 890 typedef jint xchg_func_t (jint, volatile jint*); | 702 pc = (address) uc->uc_mcontext.gregs[REG_PC]; 703 } 704 705 // unmask current signal 706 sigset_t newset; 707 sigemptyset(&newset); 708 sigaddset(&newset, sig); 709 sigprocmask(SIG_UNBLOCK, &newset, NULL); 710 711 VMError err(t, sig, pc, info, ucVoid); 712 err.report_and_die(); 713 714 ShouldNotReachHere(); 715 } 716 717 void os::print_context(outputStream *st, void *context) { 718 if (context == NULL) return; 719 720 ucontext_t *uc = (ucontext_t*)context; 721 st->print_cr("Registers:"); 722 #ifdef AMD64 723 st->print( "RAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RAX]); 724 st->print(", RBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBX]); 725 st->print(", RCX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RCX]); 726 st->print(", RDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDX]); 727 st->cr(); 728 st->print( "RSP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSP]); 729 st->print(", RBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBP]); 730 st->print(", RSI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSI]); 731 st->print(", RDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDI]); 732 st->cr(); 733 st->print( "R8 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R8]); 734 st->print(", R9 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R9]); 735 st->print(", R10=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R10]); 736 st->print(", R11=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R11]); 737 st->cr(); 738 st->print( "R12=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R12]); 739 st->print(", R13=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R13]); 740 st->print(", R14=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R14]); 741 st->print(", R15=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R15]); 742 st->cr(); 743 st->print( "RIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RIP]); 744 st->print(", RFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RFL]); 745 #else 746 st->print( "EAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EAX]); 747 st->print(", EBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBX]); 748 st->print(", ECX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ECX]); 749 st->print(", EDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDX]); 750 st->cr(); 751 st->print( "ESP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[UESP]); 752 st->print(", EBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBP]); 753 st->print(", ESI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ESI]); 754 st->print(", EDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDI]); 755 st->cr(); 756 st->print( "EIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EIP]); 757 st->print(", EFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EFL]); 758 #endif // AMD64 759 st->cr(); 760 st->cr(); 761 762 intptr_t *sp = (intptr_t *)os::Solaris::ucontext_get_sp(uc); 763 st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", sp); 764 print_hex_dump(st, (address)sp, (address)(sp + 8*sizeof(intptr_t)), sizeof(intptr_t)); 765 st->cr(); 766 767 // Note: it may be unsafe to inspect memory near pc. For example, pc may 768 // point to garbage if entry point in an nmethod is corrupted. Leave 769 // this at the end, and hope for the best. 770 ExtendedPC epc = os::Solaris::ucontext_get_ExtendedPC(uc); 771 address pc = epc.pc(); 772 st->print_cr("Instructions: (pc=" PTR_FORMAT ")", pc); 773 print_hex_dump(st, pc - 32, pc + 32, sizeof(char)); 774 } 775 776 void os::print_register_info(outputStream *st, void *context) { 777 if (context == NULL) return; 778 779 ucontext_t *uc = (ucontext_t*)context; 780 781 st->print_cr("Register to memory mapping:"); 782 st->cr(); 783 784 // this is horrendously verbose but the layout of the registers in the 785 // context does not match how we defined our abstract Register set, so 786 // we can't just iterate through the gregs area 787 788 // this is only for the "general purpose" registers 789 790 #ifdef AMD64 791 st->print("RAX="); print_location(st, uc->uc_mcontext.gregs[REG_RAX]); 792 st->print("RBX="); print_location(st, uc->uc_mcontext.gregs[REG_RBX]); 793 st->print("RCX="); print_location(st, uc->uc_mcontext.gregs[REG_RCX]); 794 st->print("RDX="); print_location(st, uc->uc_mcontext.gregs[REG_RDX]); 795 st->print("RSP="); print_location(st, uc->uc_mcontext.gregs[REG_RSP]); 796 st->print("RBP="); print_location(st, uc->uc_mcontext.gregs[REG_RBP]); 797 st->print("RSI="); print_location(st, uc->uc_mcontext.gregs[REG_RSI]); 798 st->print("RDI="); print_location(st, uc->uc_mcontext.gregs[REG_RDI]); 799 st->print("R8 ="); print_location(st, uc->uc_mcontext.gregs[REG_R8]); 800 st->print("R9 ="); print_location(st, uc->uc_mcontext.gregs[REG_R9]); 801 st->print("R10="); print_location(st, uc->uc_mcontext.gregs[REG_R10]); 802 st->print("R11="); print_location(st, uc->uc_mcontext.gregs[REG_R11]); 803 st->print("R12="); print_location(st, uc->uc_mcontext.gregs[REG_R12]); 804 st->print("R13="); print_location(st, uc->uc_mcontext.gregs[REG_R13]); 805 st->print("R14="); print_location(st, uc->uc_mcontext.gregs[REG_R14]); 806 st->print("R15="); print_location(st, uc->uc_mcontext.gregs[REG_R15]); 807 #else 808 st->print("EAX="); print_location(st, uc->uc_mcontext.gregs[EAX]); 809 st->print("EBX="); print_location(st, uc->uc_mcontext.gregs[EBX]); 810 st->print("ECX="); print_location(st, uc->uc_mcontext.gregs[ECX]); 811 st->print("EDX="); print_location(st, uc->uc_mcontext.gregs[EDX]); 812 st->print("ESP="); print_location(st, uc->uc_mcontext.gregs[UESP]); 813 st->print("EBP="); print_location(st, uc->uc_mcontext.gregs[EBP]); 814 st->print("ESI="); print_location(st, uc->uc_mcontext.gregs[ESI]); 815 st->print("EDI="); print_location(st, uc->uc_mcontext.gregs[EDI]); 816 #endif 817 818 st->cr(); 819 } 820 821 822 #ifdef AMD64 823 void os::Solaris::init_thread_fpu_state(void) { 824 // Nothing to do 825 } 826 #else 827 // From solaris_i486.s 828 extern "C" void fixcw(); 829 830 void os::Solaris::init_thread_fpu_state(void) { 831 // Set fpu to 53 bit precision. This happens too early to use a stub. 832 fixcw(); 833 } 834 835 // These routines are the initial value of atomic_xchg_entry(), 836 // atomic_cmpxchg_entry(), atomic_inc_entry() and fence_entry() 837 // until initialization is complete. 838 // TODO - replace with .il implementation when compiler supports it. 839 840 typedef jint xchg_func_t (jint, volatile jint*); |