1 /*
2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #ifdef ARM
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case objectTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::oopConst(NULL);
92 } else {
93 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
94 }
95 }
96 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
97 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
98 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
99 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
100 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
101 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
102 }
103 }
104
105
106 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
107 switch (type->tag()) {
108 case objectTag: return LIR_OprFact::oopConst(NULL);
109 case addressTag:return LIR_OprFact::addressConst(0);
110 case intTag: return LIR_OprFact::intConst(0);
111 case floatTag: return LIR_OprFact::floatConst(0.0);
112 case longTag: return LIR_OprFact::longConst(0);
113 case doubleTag: return LIR_OprFact::doubleConst(0.0);
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 return illegalOpr;
117 }
118
119
120
121 //---------------------------------------------------
122
123
124 LIR_Address::Scale LIR_Address::scale(BasicType type) {
125 int elem_size = type2aelembytes(type);
126 switch (elem_size) {
127 case 1: return LIR_Address::times_1;
128 case 2: return LIR_Address::times_2;
129 case 4: return LIR_Address::times_4;
130 case 8: return LIR_Address::times_8;
131 }
132 ShouldNotReachHere();
133 return LIR_Address::times_1;
134 }
135
136
137 #ifndef PRODUCT
138 void LIR_Address::verify() const {
139 #if defined(SPARC) || defined(PPC)
140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
141 assert(disp() == 0 || index()->is_illegal(), "can't have both");
142 #endif
143 #ifdef ARM
144 assert(disp() == 0 || index()->is_illegal(), "can't have both");
145 assert(-4096 < disp() && disp() < 4096, "architecture constraint");
146 #endif
147 #ifdef _LP64
148 assert(base()->is_cpu_register(), "wrong base operand");
149 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
150 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
151 "wrong type for addresses");
152 #else
153 assert(base()->is_single_cpu(), "wrong base operand");
154 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
155 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
156 "wrong type for addresses");
157 #endif
158 }
159 #endif
160
161
162 //---------------------------------------------------
163
164 char LIR_OprDesc::type_char(BasicType t) {
165 switch (t) {
166 case T_ARRAY:
167 t = T_OBJECT;
168 case T_BOOLEAN:
169 case T_CHAR:
170 case T_FLOAT:
171 case T_DOUBLE:
172 case T_BYTE:
173 case T_SHORT:
174 case T_INT:
175 case T_LONG:
176 case T_OBJECT:
177 case T_ADDRESS:
178 case T_VOID:
179 return ::type2char(t);
180
181 case T_ILLEGAL:
182 return '?';
183
184 default:
185 ShouldNotReachHere();
186 return '?';
187 }
188 }
189
190 #ifndef PRODUCT
191 void LIR_OprDesc::validate_type() const {
192
193 #ifdef ASSERT
194 if (!is_pointer() && !is_illegal()) {
195 switch (as_BasicType(type_field())) {
196 case T_LONG:
197 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
198 size_field() == double_size, "must match");
199 break;
200 case T_FLOAT:
201 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
202 assert((kind_field() == fpu_register || kind_field() == stack_value
203 ARM_ONLY(|| kind_field() == cpu_register)
204 PPC_ONLY(|| kind_field() == cpu_register) ) &&
205 size_field() == single_size, "must match");
206 break;
207 case T_DOUBLE:
208 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
209 assert((kind_field() == fpu_register || kind_field() == stack_value
210 ARM_ONLY(|| kind_field() == cpu_register)
211 PPC_ONLY(|| kind_field() == cpu_register) ) &&
212 size_field() == double_size, "must match");
213 break;
214 case T_BOOLEAN:
215 case T_CHAR:
216 case T_BYTE:
217 case T_SHORT:
218 case T_INT:
219 case T_ADDRESS:
220 case T_OBJECT:
221 case T_ARRAY:
222 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
223 size_field() == single_size, "must match");
224 break;
225
226 case T_ILLEGAL:
227 // XXX TKR also means unknown right now
228 // assert(is_illegal(), "must match");
229 break;
230
231 default:
232 ShouldNotReachHere();
233 }
234 }
235 #endif
236
237 }
238 #endif // PRODUCT
239
240
241 bool LIR_OprDesc::is_oop() const {
242 if (is_pointer()) {
243 return pointer()->is_oop_pointer();
244 } else {
245 OprType t= type_field();
246 assert(t != unknown_type, "not set");
247 return t == object_type;
248 }
249 }
250
251
252
253 void LIR_Op2::verify() const {
254 #ifdef ASSERT
255 switch (code()) {
256 case lir_cmove:
257 break;
258
259 default:
260 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
261 "can't produce oops from arith");
262 }
263
264 if (TwoOperandLIRForm) {
265 switch (code()) {
266 case lir_add:
267 case lir_sub:
268 case lir_mul:
269 case lir_mul_strictfp:
270 case lir_div:
271 case lir_div_strictfp:
272 case lir_rem:
273 case lir_logic_and:
274 case lir_logic_or:
275 case lir_logic_xor:
276 case lir_shl:
277 case lir_shr:
278 assert(in_opr1() == result_opr(), "opr1 and result must match");
279 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
280 break;
281
282 // special handling for lir_ushr because of write barriers
283 case lir_ushr:
284 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
285 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
286 break;
287
288 }
289 }
290 #endif
291 }
292
293
294 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
295 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
296 , _cond(cond)
297 , _type(type)
298 , _label(block->label())
299 , _block(block)
300 , _ublock(NULL)
301 , _stub(NULL) {
302 }
303
304 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
305 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
306 , _cond(cond)
307 , _type(type)
308 , _label(stub->entry())
309 , _block(NULL)
310 , _ublock(NULL)
311 , _stub(stub) {
312 }
313
314 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
315 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
316 , _cond(cond)
317 , _type(type)
318 , _label(block->label())
319 , _block(block)
320 , _ublock(ublock)
321 , _stub(NULL)
322 {
323 }
324
325 void LIR_OpBranch::change_block(BlockBegin* b) {
326 assert(_block != NULL, "must have old block");
327 assert(_block->label() == label(), "must be equal");
328
329 _block = b;
330 _label = b->label();
331 }
332
333 void LIR_OpBranch::change_ublock(BlockBegin* b) {
334 assert(_ublock != NULL, "must have old block");
335 _ublock = b;
336 }
337
338 void LIR_OpBranch::negate_cond() {
339 switch (_cond) {
340 case lir_cond_equal: _cond = lir_cond_notEqual; break;
341 case lir_cond_notEqual: _cond = lir_cond_equal; break;
342 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
343 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
344 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
345 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
346 default: ShouldNotReachHere();
347 }
348 }
349
350
351 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
352 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
353 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
354 CodeStub* stub)
355
356 : LIR_Op(code, result, NULL)
357 , _object(object)
358 , _array(LIR_OprFact::illegalOpr)
359 , _klass(klass)
360 , _tmp1(tmp1)
361 , _tmp2(tmp2)
362 , _tmp3(tmp3)
363 , _fast_check(fast_check)
364 , _stub(stub)
365 , _info_for_patch(info_for_patch)
366 , _info_for_exception(info_for_exception)
367 , _profiled_method(NULL)
368 , _profiled_bci(-1)
369 , _should_profile(false)
370 {
371 if (code == lir_checkcast) {
372 assert(info_for_exception != NULL, "checkcast throws exceptions");
373 } else if (code == lir_instanceof) {
374 assert(info_for_exception == NULL, "instanceof throws no exceptions");
375 } else {
376 ShouldNotReachHere();
377 }
378 }
379
380
381
382 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
383 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
384 , _object(object)
385 , _array(array)
386 , _klass(NULL)
387 , _tmp1(tmp1)
388 , _tmp2(tmp2)
389 , _tmp3(tmp3)
390 , _fast_check(false)
391 , _stub(NULL)
392 , _info_for_patch(NULL)
393 , _info_for_exception(info_for_exception)
394 , _profiled_method(NULL)
395 , _profiled_bci(-1)
396 , _should_profile(false)
397 {
398 if (code == lir_store_check) {
399 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
400 assert(info_for_exception != NULL, "store_check throws exceptions");
401 } else {
402 ShouldNotReachHere();
403 }
404 }
405
406
407 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
408 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
409 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
410 , _tmp(tmp)
411 , _src(src)
412 , _src_pos(src_pos)
413 , _dst(dst)
414 , _dst_pos(dst_pos)
415 , _flags(flags)
416 , _expected_type(expected_type)
417 , _length(length) {
418 _stub = new ArrayCopyStub(this);
419 }
420
421
422 //-------------------verify--------------------------
423
424 void LIR_Op1::verify() const {
425 switch(code()) {
426 case lir_move:
427 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
428 break;
429 case lir_null_check:
430 assert(in_opr()->is_register(), "must be");
431 break;
432 case lir_return:
433 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
434 break;
435 }
436 }
437
438 void LIR_OpRTCall::verify() const {
439 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
440 }
441
442 //-------------------visits--------------------------
443
444 // complete rework of LIR instruction visitor.
445 // The virtual calls for each instruction type is replaced by a big
446 // switch that adds the operands for each instruction
447
448 void LIR_OpVisitState::visit(LIR_Op* op) {
449 // copy information from the LIR_Op
450 reset();
451 set_op(op);
452
453 switch (op->code()) {
454
455 // LIR_Op0
456 case lir_word_align: // result and info always invalid
457 case lir_backwardbranch_target: // result and info always invalid
458 case lir_build_frame: // result and info always invalid
459 case lir_fpop_raw: // result and info always invalid
460 case lir_24bit_FPU: // result and info always invalid
461 case lir_reset_FPU: // result and info always invalid
462 case lir_breakpoint: // result and info always invalid
463 case lir_membar: // result and info always invalid
464 case lir_membar_acquire: // result and info always invalid
465 case lir_membar_release: // result and info always invalid
466 {
467 assert(op->as_Op0() != NULL, "must be");
468 assert(op->_info == NULL, "info not used by this instruction");
469 assert(op->_result->is_illegal(), "not used");
470 break;
471 }
472
473 case lir_nop: // may have info, result always invalid
474 case lir_std_entry: // may have result, info always invalid
475 case lir_osr_entry: // may have result, info always invalid
476 case lir_get_thread: // may have result, info always invalid
477 {
478 assert(op->as_Op0() != NULL, "must be");
479 if (op->_info != NULL) do_info(op->_info);
480 if (op->_result->is_valid()) do_output(op->_result);
481 break;
482 }
483
484
485 // LIR_OpLabel
486 case lir_label: // result and info always invalid
487 {
488 assert(op->as_OpLabel() != NULL, "must be");
489 assert(op->_info == NULL, "info not used by this instruction");
490 assert(op->_result->is_illegal(), "not used");
491 break;
492 }
493
494
495 // LIR_Op1
496 case lir_fxch: // input always valid, result and info always invalid
497 case lir_fld: // input always valid, result and info always invalid
498 case lir_ffree: // input always valid, result and info always invalid
499 case lir_push: // input always valid, result and info always invalid
500 case lir_pop: // input always valid, result and info always invalid
501 case lir_return: // input always valid, result and info always invalid
502 case lir_leal: // input and result always valid, info always invalid
503 case lir_neg: // input and result always valid, info always invalid
504 case lir_monaddr: // input and result always valid, info always invalid
505 case lir_null_check: // input and info always valid, result always invalid
506 case lir_move: // input and result always valid, may have info
507 case lir_pack64: // input and result always valid
508 case lir_unpack64: // input and result always valid
509 case lir_prefetchr: // input always valid, result and info always invalid
510 case lir_prefetchw: // input always valid, result and info always invalid
511 {
512 assert(op->as_Op1() != NULL, "must be");
513 LIR_Op1* op1 = (LIR_Op1*)op;
514
515 if (op1->_info) do_info(op1->_info);
516 if (op1->_opr->is_valid()) do_input(op1->_opr);
517 if (op1->_result->is_valid()) do_output(op1->_result);
518
519 break;
520 }
521
522 case lir_safepoint:
523 {
524 assert(op->as_Op1() != NULL, "must be");
525 LIR_Op1* op1 = (LIR_Op1*)op;
526
527 assert(op1->_info != NULL, ""); do_info(op1->_info);
528 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
529 assert(op1->_result->is_illegal(), "safepoint does not produce value");
530
531 break;
532 }
533
534 // LIR_OpConvert;
535 case lir_convert: // input and result always valid, info always invalid
536 {
537 assert(op->as_OpConvert() != NULL, "must be");
538 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
539
540 assert(opConvert->_info == NULL, "must be");
541 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
542 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
543 #ifdef PPC
544 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
545 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
546 #endif
547 do_stub(opConvert->_stub);
548
549 break;
550 }
551
552 // LIR_OpBranch;
553 case lir_branch: // may have info, input and result register always invalid
554 case lir_cond_float_branch: // may have info, input and result register always invalid
555 {
556 assert(op->as_OpBranch() != NULL, "must be");
557 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
558
559 if (opBranch->_info != NULL) do_info(opBranch->_info);
560 assert(opBranch->_result->is_illegal(), "not used");
561 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
562
563 break;
564 }
565
566
567 // LIR_OpAllocObj
568 case lir_alloc_object:
569 {
570 assert(op->as_OpAllocObj() != NULL, "must be");
571 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
572
573 if (opAllocObj->_info) do_info(opAllocObj->_info);
574 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
575 do_temp(opAllocObj->_opr);
576 }
577 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
578 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
579 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
580 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
581 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
582 do_stub(opAllocObj->_stub);
583 break;
584 }
585
586
587 // LIR_OpRoundFP;
588 case lir_roundfp: {
589 assert(op->as_OpRoundFP() != NULL, "must be");
590 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
591
592 assert(op->_info == NULL, "info not used by this instruction");
593 assert(opRoundFP->_tmp->is_illegal(), "not used");
594 do_input(opRoundFP->_opr);
595 do_output(opRoundFP->_result);
596
597 break;
598 }
599
600
601 // LIR_Op2
602 case lir_cmp:
603 case lir_cmp_l2i:
604 case lir_ucmp_fd2i:
605 case lir_cmp_fd2i:
606 case lir_add:
607 case lir_sub:
608 case lir_mul:
609 case lir_div:
610 case lir_rem:
611 case lir_sqrt:
612 case lir_abs:
613 case lir_logic_and:
614 case lir_logic_or:
615 case lir_logic_xor:
616 case lir_shl:
617 case lir_shr:
618 case lir_ushr:
619 {
620 assert(op->as_Op2() != NULL, "must be");
621 LIR_Op2* op2 = (LIR_Op2*)op;
622
623 if (op2->_info) do_info(op2->_info);
624 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
625 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
626 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
627 if (op2->_result->is_valid()) do_output(op2->_result);
628
629 break;
630 }
631
632 // special handling for cmove: right input operand must not be equal
633 // to the result operand, otherwise the backend fails
634 case lir_cmove:
635 {
636 assert(op->as_Op2() != NULL, "must be");
637 LIR_Op2* op2 = (LIR_Op2*)op;
638
639 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
640 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
641
642 do_input(op2->_opr1);
643 do_input(op2->_opr2);
644 do_temp(op2->_opr2);
645 do_output(op2->_result);
646
647 break;
648 }
649
650 // vspecial handling for strict operations: register input operands
651 // as temp to guarantee that they do not overlap with other
652 // registers
653 case lir_mul_strictfp:
654 case lir_div_strictfp:
655 {
656 assert(op->as_Op2() != NULL, "must be");
657 LIR_Op2* op2 = (LIR_Op2*)op;
658
659 assert(op2->_info == NULL, "not used");
660 assert(op2->_opr1->is_valid(), "used");
661 assert(op2->_opr2->is_valid(), "used");
662 assert(op2->_result->is_valid(), "used");
663
664 do_input(op2->_opr1); do_temp(op2->_opr1);
665 do_input(op2->_opr2); do_temp(op2->_opr2);
666 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
667 do_output(op2->_result);
668
669 break;
670 }
671
672 case lir_throw: {
673 assert(op->as_Op2() != NULL, "must be");
674 LIR_Op2* op2 = (LIR_Op2*)op;
675
676 if (op2->_info) do_info(op2->_info);
677 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
678 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
679 assert(op2->_result->is_illegal(), "no result");
680
681 break;
682 }
683
684 case lir_unwind: {
685 assert(op->as_Op1() != NULL, "must be");
686 LIR_Op1* op1 = (LIR_Op1*)op;
687
688 assert(op1->_info == NULL, "no info");
689 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
690 assert(op1->_result->is_illegal(), "no result");
691
692 break;
693 }
694
695
696 case lir_tan:
697 case lir_sin:
698 case lir_cos:
699 case lir_log:
700 case lir_log10: {
701 assert(op->as_Op2() != NULL, "must be");
702 LIR_Op2* op2 = (LIR_Op2*)op;
703
704 // On x86 tan/sin/cos need two temporary fpu stack slots and
705 // log/log10 need one so handle opr2 and tmp as temp inputs.
706 // Register input operand as temp to guarantee that it doesn't
707 // overlap with the input.
708 assert(op2->_info == NULL, "not used");
709 assert(op2->_opr1->is_valid(), "used");
710 do_input(op2->_opr1); do_temp(op2->_opr1);
711
712 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
713 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
714 if (op2->_result->is_valid()) do_output(op2->_result);
715
716 break;
717 }
718
719
720 // LIR_Op3
721 case lir_idiv:
722 case lir_irem: {
723 assert(op->as_Op3() != NULL, "must be");
724 LIR_Op3* op3= (LIR_Op3*)op;
725
726 if (op3->_info) do_info(op3->_info);
727 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
728
729 // second operand is input and temp, so ensure that second operand
730 // and third operand get not the same register
731 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
732 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
733 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
734
735 if (op3->_result->is_valid()) do_output(op3->_result);
736
737 break;
738 }
739
740
741 // LIR_OpJavaCall
742 case lir_static_call:
743 case lir_optvirtual_call:
744 case lir_icvirtual_call:
745 case lir_virtual_call:
746 case lir_dynamic_call: {
747 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
748 assert(opJavaCall != NULL, "must be");
749
750 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
751
752 // only visit register parameters
753 int n = opJavaCall->_arguments->length();
754 for (int i = 0; i < n; i++) {
755 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
756 do_input(*opJavaCall->_arguments->adr_at(i));
757 }
758 }
759
760 if (opJavaCall->_info) do_info(opJavaCall->_info);
761 if (opJavaCall->is_method_handle_invoke()) {
762 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
763 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
764 }
765 do_call();
766 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
767
768 break;
769 }
770
771
772 // LIR_OpRTCall
773 case lir_rtcall: {
774 assert(op->as_OpRTCall() != NULL, "must be");
775 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
776
777 // only visit register parameters
778 int n = opRTCall->_arguments->length();
779 for (int i = 0; i < n; i++) {
780 if (!opRTCall->_arguments->at(i)->is_pointer()) {
781 do_input(*opRTCall->_arguments->adr_at(i));
782 }
783 }
784 if (opRTCall->_info) do_info(opRTCall->_info);
785 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
786 do_call();
787 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
788
789 break;
790 }
791
792
793 // LIR_OpArrayCopy
794 case lir_arraycopy: {
795 assert(op->as_OpArrayCopy() != NULL, "must be");
796 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
797
798 assert(opArrayCopy->_result->is_illegal(), "unused");
799 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
800 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
801 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
802 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
803 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
804 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
805 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
806
807 // the implementation of arraycopy always has a call into the runtime
808 do_call();
809
810 break;
811 }
812
813
814 // LIR_OpLock
815 case lir_lock:
816 case lir_unlock: {
817 assert(op->as_OpLock() != NULL, "must be");
818 LIR_OpLock* opLock = (LIR_OpLock*)op;
819
820 if (opLock->_info) do_info(opLock->_info);
821
822 // TODO: check if these operands really have to be temp
823 // (or if input is sufficient). This may have influence on the oop map!
824 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
825 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
826 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
827
828 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
829 assert(opLock->_result->is_illegal(), "unused");
830
831 do_stub(opLock->_stub);
832
833 break;
834 }
835
836
837 // LIR_OpDelay
838 case lir_delay_slot: {
839 assert(op->as_OpDelay() != NULL, "must be");
840 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
841
842 visit(opDelay->delay_op());
843 break;
844 }
845
846 // LIR_OpTypeCheck
847 case lir_instanceof:
848 case lir_checkcast:
849 case lir_store_check: {
850 assert(op->as_OpTypeCheck() != NULL, "must be");
851 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
852
853 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
854 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
855 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
856 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
857 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
858 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
859 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
860 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
861 do_stub(opTypeCheck->_stub);
862 break;
863 }
864
865 // LIR_OpCompareAndSwap
866 case lir_cas_long:
867 case lir_cas_obj:
868 case lir_cas_int: {
869 assert(op->as_OpCompareAndSwap() != NULL, "must be");
870 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
871
872 assert(opCompareAndSwap->_addr->is_valid(), "used");
873 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
874 assert(opCompareAndSwap->_new_value->is_valid(), "used");
875 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
876 do_input(opCompareAndSwap->_addr);
877 do_temp(opCompareAndSwap->_addr);
878 do_input(opCompareAndSwap->_cmp_value);
879 do_temp(opCompareAndSwap->_cmp_value);
880 do_input(opCompareAndSwap->_new_value);
881 do_temp(opCompareAndSwap->_new_value);
882 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
883 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
884 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
885
886 break;
887 }
888
889
890 // LIR_OpAllocArray;
891 case lir_alloc_array: {
892 assert(op->as_OpAllocArray() != NULL, "must be");
893 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
894
895 if (opAllocArray->_info) do_info(opAllocArray->_info);
896 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
897 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
898 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
899 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
900 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
901 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
902 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
903 do_stub(opAllocArray->_stub);
904 break;
905 }
906
907 // LIR_OpProfileCall:
908 case lir_profile_call: {
909 assert(op->as_OpProfileCall() != NULL, "must be");
910 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
911
912 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
913 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
914 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
915 break;
916 }
917 default:
918 ShouldNotReachHere();
919 }
920 }
921
922
923 void LIR_OpVisitState::do_stub(CodeStub* stub) {
924 if (stub != NULL) {
925 stub->visit(this);
926 }
927 }
928
929 XHandlers* LIR_OpVisitState::all_xhandler() {
930 XHandlers* result = NULL;
931
932 int i;
933 for (i = 0; i < info_count(); i++) {
934 if (info_at(i)->exception_handlers() != NULL) {
935 result = info_at(i)->exception_handlers();
936 break;
937 }
938 }
939
940 #ifdef ASSERT
941 for (i = 0; i < info_count(); i++) {
942 assert(info_at(i)->exception_handlers() == NULL ||
943 info_at(i)->exception_handlers() == result,
944 "only one xhandler list allowed per LIR-operation");
945 }
946 #endif
947
948 if (result != NULL) {
949 return result;
950 } else {
951 return new XHandlers();
952 }
953
954 return result;
955 }
956
957
958 #ifdef ASSERT
959 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
960 visit(op);
961
962 return opr_count(inputMode) == 0 &&
963 opr_count(outputMode) == 0 &&
964 opr_count(tempMode) == 0 &&
965 info_count() == 0 &&
966 !has_call() &&
967 !has_slow_case();
968 }
969 #endif
970
971 //---------------------------------------------------
972
973
974 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
975 masm->emit_call(this);
976 }
977
978 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
979 masm->emit_rtcall(this);
980 }
981
982 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
983 masm->emit_opLabel(this);
984 }
985
986 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
987 masm->emit_arraycopy(this);
988 masm->emit_code_stub(stub());
989 }
990
991 void LIR_Op0::emit_code(LIR_Assembler* masm) {
992 masm->emit_op0(this);
993 }
994
995 void LIR_Op1::emit_code(LIR_Assembler* masm) {
996 masm->emit_op1(this);
997 }
998
999 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1000 masm->emit_alloc_obj(this);
1001 masm->emit_code_stub(stub());
1002 }
1003
1004 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1005 masm->emit_opBranch(this);
1006 if (stub()) {
1007 masm->emit_code_stub(stub());
1008 }
1009 }
1010
1011 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1012 masm->emit_opConvert(this);
1013 if (stub() != NULL) {
1014 masm->emit_code_stub(stub());
1015 }
1016 }
1017
1018 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1019 masm->emit_op2(this);
1020 }
1021
1022 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1023 masm->emit_alloc_array(this);
1024 masm->emit_code_stub(stub());
1025 }
1026
1027 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1028 masm->emit_opTypeCheck(this);
1029 if (stub()) {
1030 masm->emit_code_stub(stub());
1031 }
1032 }
1033
1034 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1035 masm->emit_compare_and_swap(this);
1036 }
1037
1038 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1039 masm->emit_op3(this);
1040 }
1041
1042 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1043 masm->emit_lock(this);
1044 if (stub()) {
1045 masm->emit_code_stub(stub());
1046 }
1047 }
1048
1049
1050 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1051 masm->emit_delay(this);
1052 }
1053
1054 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1055 masm->emit_profile_call(this);
1056 }
1057
1058 // LIR_List
1059 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1060 : _operations(8)
1061 , _compilation(compilation)
1062 #ifndef PRODUCT
1063 , _block(block)
1064 #endif
1065 #ifdef ASSERT
1066 , _file(NULL)
1067 , _line(0)
1068 #endif
1069 { }
1070
1071
1072 #ifdef ASSERT
1073 void LIR_List::set_file_and_line(const char * file, int line) {
1074 const char * f = strrchr(file, '/');
1075 if (f == NULL) f = strrchr(file, '\\');
1076 if (f == NULL) {
1077 f = file;
1078 } else {
1079 f++;
1080 }
1081 _file = f;
1082 _line = line;
1083 }
1084 #endif
1085
1086
1087 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1088 assert(this == buffer->lir_list(), "wrong lir list");
1089 const int n = _operations.length();
1090
1091 if (buffer->number_of_ops() > 0) {
1092 // increase size of instructions list
1093 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1094 // insert ops from buffer into instructions list
1095 int op_index = buffer->number_of_ops() - 1;
1096 int ip_index = buffer->number_of_insertion_points() - 1;
1097 int from_index = n - 1;
1098 int to_index = _operations.length() - 1;
1099 for (; ip_index >= 0; ip_index --) {
1100 int index = buffer->index_at(ip_index);
1101 // make room after insertion point
1102 while (index < from_index) {
1103 _operations.at_put(to_index --, _operations.at(from_index --));
1104 }
1105 // insert ops from buffer
1106 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1107 _operations.at_put(to_index --, buffer->op_at(op_index --));
1108 }
1109 }
1110 }
1111
1112 buffer->finish();
1113 }
1114
1115
1116 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1117 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1118 }
1119
1120
1121 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1122 append(new LIR_Op1(
1123 lir_move,
1124 LIR_OprFact::address(addr),
1125 src,
1126 addr->type(),
1127 patch_code,
1128 info));
1129 }
1130
1131
1132 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1133 append(new LIR_Op1(
1134 lir_move,
1135 LIR_OprFact::address(address),
1136 dst,
1137 address->type(),
1138 patch_code,
1139 info, lir_move_volatile));
1140 }
1141
1142 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1143 append(new LIR_Op1(
1144 lir_move,
1145 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1146 dst,
1147 type,
1148 patch_code,
1149 info, lir_move_volatile));
1150 }
1151
1152
1153 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1154 append(new LIR_Op1(
1155 is_store ? lir_prefetchw : lir_prefetchr,
1156 LIR_OprFact::address(addr)));
1157 }
1158
1159
1160 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1161 append(new LIR_Op1(
1162 lir_move,
1163 LIR_OprFact::intConst(v),
1164 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1165 type,
1166 patch_code,
1167 info));
1168 }
1169
1170
1171 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1172 append(new LIR_Op1(
1173 lir_move,
1174 LIR_OprFact::oopConst(o),
1175 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1176 type,
1177 patch_code,
1178 info));
1179 }
1180
1181
1182 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1183 append(new LIR_Op1(
1184 lir_move,
1185 src,
1186 LIR_OprFact::address(addr),
1187 addr->type(),
1188 patch_code,
1189 info));
1190 }
1191
1192
1193 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1194 append(new LIR_Op1(
1195 lir_move,
1196 src,
1197 LIR_OprFact::address(addr),
1198 addr->type(),
1199 patch_code,
1200 info,
1201 lir_move_volatile));
1202 }
1203
1204 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1205 append(new LIR_Op1(
1206 lir_move,
1207 src,
1208 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1209 type,
1210 patch_code,
1211 info, lir_move_volatile));
1212 }
1213
1214
1215 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1216 append(new LIR_Op3(
1217 lir_idiv,
1218 left,
1219 right,
1220 tmp,
1221 res,
1222 info));
1223 }
1224
1225
1226 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1227 append(new LIR_Op3(
1228 lir_idiv,
1229 left,
1230 LIR_OprFact::intConst(right),
1231 tmp,
1232 res,
1233 info));
1234 }
1235
1236
1237 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1238 append(new LIR_Op3(
1239 lir_irem,
1240 left,
1241 right,
1242 tmp,
1243 res,
1244 info));
1245 }
1246
1247
1248 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1249 append(new LIR_Op3(
1250 lir_irem,
1251 left,
1252 LIR_OprFact::intConst(right),
1253 tmp,
1254 res,
1255 info));
1256 }
1257
1258
1259 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1260 append(new LIR_Op2(
1261 lir_cmp,
1262 condition,
1263 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1264 LIR_OprFact::intConst(c),
1265 info));
1266 }
1267
1268
1269 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1270 append(new LIR_Op2(
1271 lir_cmp,
1272 condition,
1273 reg,
1274 LIR_OprFact::address(addr),
1275 info));
1276 }
1277
1278 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1279 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1280 append(new LIR_OpAllocObj(
1281 klass,
1282 dst,
1283 t1,
1284 t2,
1285 t3,
1286 t4,
1287 header_size,
1288 object_size,
1289 init_check,
1290 stub));
1291 }
1292
1293 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1294 append(new LIR_OpAllocArray(
1295 klass,
1296 len,
1297 dst,
1298 t1,
1299 t2,
1300 t3,
1301 t4,
1302 type,
1303 stub));
1304 }
1305
1306 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1307 append(new LIR_Op2(
1308 lir_shl,
1309 value,
1310 count,
1311 dst,
1312 tmp));
1313 }
1314
1315 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1316 append(new LIR_Op2(
1317 lir_shr,
1318 value,
1319 count,
1320 dst,
1321 tmp));
1322 }
1323
1324
1325 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1326 append(new LIR_Op2(
1327 lir_ushr,
1328 value,
1329 count,
1330 dst,
1331 tmp));
1332 }
1333
1334 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1335 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1336 left,
1337 right,
1338 dst));
1339 }
1340
1341 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1342 append(new LIR_OpLock(
1343 lir_lock,
1344 hdr,
1345 obj,
1346 lock,
1347 scratch,
1348 stub,
1349 info));
1350 }
1351
1352 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1353 append(new LIR_OpLock(
1354 lir_unlock,
1355 hdr,
1356 obj,
1357 lock,
1358 scratch,
1359 stub,
1360 NULL));
1361 }
1362
1363
1364 void check_LIR() {
1365 // cannot do the proper checking as PRODUCT and other modes return different results
1366 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1367 }
1368
1369
1370
1371 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1372 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1373 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1374 ciMethod* profiled_method, int profiled_bci) {
1375 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1376 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1377 if (profiled_method != NULL) {
1378 c->set_profiled_method(profiled_method);
1379 c->set_profiled_bci(profiled_bci);
1380 c->set_should_profile(true);
1381 }
1382 append(c);
1383 }
1384
1385 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1386 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1387 if (profiled_method != NULL) {
1388 c->set_profiled_method(profiled_method);
1389 c->set_profiled_bci(profiled_bci);
1390 c->set_should_profile(true);
1391 }
1392 append(c);
1393 }
1394
1395
1396 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1397 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception));
1398 }
1399
1400
1401 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1402 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1403 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1404 }
1405
1406 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1407 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1408 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1409 }
1410
1411 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1412 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1413 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1414 }
1415
1416
1417 #ifdef PRODUCT
1418
1419 void print_LIR(BlockList* blocks) {
1420 }
1421
1422 #else
1423 // LIR_OprDesc
1424 void LIR_OprDesc::print() const {
1425 print(tty);
1426 }
1427
1428 void LIR_OprDesc::print(outputStream* out) const {
1429 if (is_illegal()) {
1430 return;
1431 }
1432
1433 out->print("[");
1434 if (is_pointer()) {
1435 pointer()->print_value_on(out);
1436 } else if (is_single_stack()) {
1437 out->print("stack:%d", single_stack_ix());
1438 } else if (is_double_stack()) {
1439 out->print("dbl_stack:%d",double_stack_ix());
1440 } else if (is_virtual()) {
1441 out->print("R%d", vreg_number());
1442 } else if (is_single_cpu()) {
1443 out->print(as_register()->name());
1444 } else if (is_double_cpu()) {
1445 out->print(as_register_hi()->name());
1446 out->print(as_register_lo()->name());
1447 #if defined(X86)
1448 } else if (is_single_xmm()) {
1449 out->print(as_xmm_float_reg()->name());
1450 } else if (is_double_xmm()) {
1451 out->print(as_xmm_double_reg()->name());
1452 } else if (is_single_fpu()) {
1453 out->print("fpu%d", fpu_regnr());
1454 } else if (is_double_fpu()) {
1455 out->print("fpu%d", fpu_regnrLo());
1456 #elif defined(ARM)
1457 } else if (is_single_fpu()) {
1458 out->print("s%d", fpu_regnr());
1459 } else if (is_double_fpu()) {
1460 out->print("d%d", fpu_regnrLo() >> 1);
1461 #else
1462 } else if (is_single_fpu()) {
1463 out->print(as_float_reg()->name());
1464 } else if (is_double_fpu()) {
1465 out->print(as_double_reg()->name());
1466 #endif
1467
1468 } else if (is_illegal()) {
1469 out->print("-");
1470 } else {
1471 out->print("Unknown Operand");
1472 }
1473 if (!is_illegal()) {
1474 out->print("|%c", type_char());
1475 }
1476 if (is_register() && is_last_use()) {
1477 out->print("(last_use)");
1478 }
1479 out->print("]");
1480 }
1481
1482
1483 // LIR_Address
1484 void LIR_Const::print_value_on(outputStream* out) const {
1485 switch (type()) {
1486 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1487 case T_INT: out->print("int:%d", as_jint()); break;
1488 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1489 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1490 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1491 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1492 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1493 }
1494 }
1495
1496 // LIR_Address
1497 void LIR_Address::print_value_on(outputStream* out) const {
1498 out->print("Base:"); _base->print(out);
1499 if (!_index->is_illegal()) {
1500 out->print(" Index:"); _index->print(out);
1501 switch (scale()) {
1502 case times_1: break;
1503 case times_2: out->print(" * 2"); break;
1504 case times_4: out->print(" * 4"); break;
1505 case times_8: out->print(" * 8"); break;
1506 }
1507 }
1508 out->print(" Disp: %d", _disp);
1509 }
1510
1511 // debug output of block header without InstructionPrinter
1512 // (because phi functions are not necessary for LIR)
1513 static void print_block(BlockBegin* x) {
1514 // print block id
1515 BlockEnd* end = x->end();
1516 tty->print("B%d ", x->block_id());
1517
1518 // print flags
1519 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1520 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1521 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1522 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1523 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1524 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1525 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1526
1527 // print block bci range
1528 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1529
1530 // print predecessors and successors
1531 if (x->number_of_preds() > 0) {
1532 tty->print("preds: ");
1533 for (int i = 0; i < x->number_of_preds(); i ++) {
1534 tty->print("B%d ", x->pred_at(i)->block_id());
1535 }
1536 }
1537
1538 if (x->number_of_sux() > 0) {
1539 tty->print("sux: ");
1540 for (int i = 0; i < x->number_of_sux(); i ++) {
1541 tty->print("B%d ", x->sux_at(i)->block_id());
1542 }
1543 }
1544
1545 // print exception handlers
1546 if (x->number_of_exception_handlers() > 0) {
1547 tty->print("xhandler: ");
1548 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1549 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1550 }
1551 }
1552
1553 tty->cr();
1554 }
1555
1556 void print_LIR(BlockList* blocks) {
1557 tty->print_cr("LIR:");
1558 int i;
1559 for (i = 0; i < blocks->length(); i++) {
1560 BlockBegin* bb = blocks->at(i);
1561 print_block(bb);
1562 tty->print("__id_Instruction___________________________________________"); tty->cr();
1563 bb->lir()->print_instructions();
1564 }
1565 }
1566
1567 void LIR_List::print_instructions() {
1568 for (int i = 0; i < _operations.length(); i++) {
1569 _operations.at(i)->print(); tty->cr();
1570 }
1571 tty->cr();
1572 }
1573
1574 // LIR_Ops printing routines
1575 // LIR_Op
1576 void LIR_Op::print_on(outputStream* out) const {
1577 if (id() != -1 || PrintCFGToFile) {
1578 out->print("%4d ", id());
1579 } else {
1580 out->print(" ");
1581 }
1582 out->print(name()); out->print(" ");
1583 print_instr(out);
1584 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1585 #ifdef ASSERT
1586 if (Verbose && _file != NULL) {
1587 out->print(" (%s:%d)", _file, _line);
1588 }
1589 #endif
1590 }
1591
1592 const char * LIR_Op::name() const {
1593 const char* s = NULL;
1594 switch(code()) {
1595 // LIR_Op0
1596 case lir_membar: s = "membar"; break;
1597 case lir_membar_acquire: s = "membar_acquire"; break;
1598 case lir_membar_release: s = "membar_release"; break;
1599 case lir_word_align: s = "word_align"; break;
1600 case lir_label: s = "label"; break;
1601 case lir_nop: s = "nop"; break;
1602 case lir_backwardbranch_target: s = "backbranch"; break;
1603 case lir_std_entry: s = "std_entry"; break;
1604 case lir_osr_entry: s = "osr_entry"; break;
1605 case lir_build_frame: s = "build_frm"; break;
1606 case lir_fpop_raw: s = "fpop_raw"; break;
1607 case lir_24bit_FPU: s = "24bit_FPU"; break;
1608 case lir_reset_FPU: s = "reset_FPU"; break;
1609 case lir_breakpoint: s = "breakpoint"; break;
1610 case lir_get_thread: s = "get_thread"; break;
1611 // LIR_Op1
1612 case lir_fxch: s = "fxch"; break;
1613 case lir_fld: s = "fld"; break;
1614 case lir_ffree: s = "ffree"; break;
1615 case lir_push: s = "push"; break;
1616 case lir_pop: s = "pop"; break;
1617 case lir_null_check: s = "null_check"; break;
1618 case lir_return: s = "return"; break;
1619 case lir_safepoint: s = "safepoint"; break;
1620 case lir_neg: s = "neg"; break;
1621 case lir_leal: s = "leal"; break;
1622 case lir_branch: s = "branch"; break;
1623 case lir_cond_float_branch: s = "flt_cond_br"; break;
1624 case lir_move: s = "move"; break;
1625 case lir_roundfp: s = "roundfp"; break;
1626 case lir_rtcall: s = "rtcall"; break;
1627 case lir_throw: s = "throw"; break;
1628 case lir_unwind: s = "unwind"; break;
1629 case lir_convert: s = "convert"; break;
1630 case lir_alloc_object: s = "alloc_obj"; break;
1631 case lir_monaddr: s = "mon_addr"; break;
1632 case lir_pack64: s = "pack64"; break;
1633 case lir_unpack64: s = "unpack64"; break;
1634 // LIR_Op2
1635 case lir_cmp: s = "cmp"; break;
1636 case lir_cmp_l2i: s = "cmp_l2i"; break;
1637 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1638 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1639 case lir_cmove: s = "cmove"; break;
1640 case lir_add: s = "add"; break;
1641 case lir_sub: s = "sub"; break;
1642 case lir_mul: s = "mul"; break;
1643 case lir_mul_strictfp: s = "mul_strictfp"; break;
1644 case lir_div: s = "div"; break;
1645 case lir_div_strictfp: s = "div_strictfp"; break;
1646 case lir_rem: s = "rem"; break;
1647 case lir_abs: s = "abs"; break;
1648 case lir_sqrt: s = "sqrt"; break;
1649 case lir_sin: s = "sin"; break;
1650 case lir_cos: s = "cos"; break;
1651 case lir_tan: s = "tan"; break;
1652 case lir_log: s = "log"; break;
1653 case lir_log10: s = "log10"; break;
1654 case lir_logic_and: s = "logic_and"; break;
1655 case lir_logic_or: s = "logic_or"; break;
1656 case lir_logic_xor: s = "logic_xor"; break;
1657 case lir_shl: s = "shift_left"; break;
1658 case lir_shr: s = "shift_right"; break;
1659 case lir_ushr: s = "ushift_right"; break;
1660 case lir_alloc_array: s = "alloc_array"; break;
1661 // LIR_Op3
1662 case lir_idiv: s = "idiv"; break;
1663 case lir_irem: s = "irem"; break;
1664 // LIR_OpJavaCall
1665 case lir_static_call: s = "static"; break;
1666 case lir_optvirtual_call: s = "optvirtual"; break;
1667 case lir_icvirtual_call: s = "icvirtual"; break;
1668 case lir_virtual_call: s = "virtual"; break;
1669 case lir_dynamic_call: s = "dynamic"; break;
1670 // LIR_OpArrayCopy
1671 case lir_arraycopy: s = "arraycopy"; break;
1672 // LIR_OpLock
1673 case lir_lock: s = "lock"; break;
1674 case lir_unlock: s = "unlock"; break;
1675 // LIR_OpDelay
1676 case lir_delay_slot: s = "delay"; break;
1677 // LIR_OpTypeCheck
1678 case lir_instanceof: s = "instanceof"; break;
1679 case lir_checkcast: s = "checkcast"; break;
1680 case lir_store_check: s = "store_check"; break;
1681 // LIR_OpCompareAndSwap
1682 case lir_cas_long: s = "cas_long"; break;
1683 case lir_cas_obj: s = "cas_obj"; break;
1684 case lir_cas_int: s = "cas_int"; break;
1685 // LIR_OpProfileCall
1686 case lir_profile_call: s = "profile_call"; break;
1687 case lir_none: ShouldNotReachHere();break;
1688 default: s = "illegal_op"; break;
1689 }
1690 return s;
1691 }
1692
1693 // LIR_OpJavaCall
1694 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1695 out->print("call: ");
1696 out->print("[addr: 0x%x]", address());
1697 if (receiver()->is_valid()) {
1698 out->print(" [recv: "); receiver()->print(out); out->print("]");
1699 }
1700 if (result_opr()->is_valid()) {
1701 out->print(" [result: "); result_opr()->print(out); out->print("]");
1702 }
1703 }
1704
1705 // LIR_OpLabel
1706 void LIR_OpLabel::print_instr(outputStream* out) const {
1707 out->print("[label:0x%x]", _label);
1708 }
1709
1710 // LIR_OpArrayCopy
1711 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1712 src()->print(out); out->print(" ");
1713 src_pos()->print(out); out->print(" ");
1714 dst()->print(out); out->print(" ");
1715 dst_pos()->print(out); out->print(" ");
1716 length()->print(out); out->print(" ");
1717 tmp()->print(out); out->print(" ");
1718 }
1719
1720 // LIR_OpCompareAndSwap
1721 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1722 addr()->print(out); out->print(" ");
1723 cmp_value()->print(out); out->print(" ");
1724 new_value()->print(out); out->print(" ");
1725 tmp1()->print(out); out->print(" ");
1726 tmp2()->print(out); out->print(" ");
1727
1728 }
1729
1730 // LIR_Op0
1731 void LIR_Op0::print_instr(outputStream* out) const {
1732 result_opr()->print(out);
1733 }
1734
1735 // LIR_Op1
1736 const char * LIR_Op1::name() const {
1737 if (code() == lir_move) {
1738 switch (move_kind()) {
1739 case lir_move_normal:
1740 return "move";
1741 case lir_move_unaligned:
1742 return "unaligned move";
1743 case lir_move_volatile:
1744 return "volatile_move";
1745 case lir_move_wide:
1746 return "wide_move";
1747 default:
1748 ShouldNotReachHere();
1749 return "illegal_op";
1750 }
1751 } else {
1752 return LIR_Op::name();
1753 }
1754 }
1755
1756
1757 void LIR_Op1::print_instr(outputStream* out) const {
1758 _opr->print(out); out->print(" ");
1759 result_opr()->print(out); out->print(" ");
1760 print_patch_code(out, patch_code());
1761 }
1762
1763
1764 // LIR_Op1
1765 void LIR_OpRTCall::print_instr(outputStream* out) const {
1766 intx a = (intx)addr();
1767 out->print(Runtime1::name_for_address(addr()));
1768 out->print(" ");
1769 tmp()->print(out);
1770 }
1771
1772 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1773 switch(code) {
1774 case lir_patch_none: break;
1775 case lir_patch_low: out->print("[patch_low]"); break;
1776 case lir_patch_high: out->print("[patch_high]"); break;
1777 case lir_patch_normal: out->print("[patch_normal]"); break;
1778 default: ShouldNotReachHere();
1779 }
1780 }
1781
1782 // LIR_OpBranch
1783 void LIR_OpBranch::print_instr(outputStream* out) const {
1784 print_condition(out, cond()); out->print(" ");
1785 if (block() != NULL) {
1786 out->print("[B%d] ", block()->block_id());
1787 } else if (stub() != NULL) {
1788 out->print("[");
1789 stub()->print_name(out);
1790 out->print(": 0x%x]", stub());
1791 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1792 } else {
1793 out->print("[label:0x%x] ", label());
1794 }
1795 if (ublock() != NULL) {
1796 out->print("unordered: [B%d] ", ublock()->block_id());
1797 }
1798 }
1799
1800 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1801 switch(cond) {
1802 case lir_cond_equal: out->print("[EQ]"); break;
1803 case lir_cond_notEqual: out->print("[NE]"); break;
1804 case lir_cond_less: out->print("[LT]"); break;
1805 case lir_cond_lessEqual: out->print("[LE]"); break;
1806 case lir_cond_greaterEqual: out->print("[GE]"); break;
1807 case lir_cond_greater: out->print("[GT]"); break;
1808 case lir_cond_belowEqual: out->print("[BE]"); break;
1809 case lir_cond_aboveEqual: out->print("[AE]"); break;
1810 case lir_cond_always: out->print("[AL]"); break;
1811 default: out->print("[%d]",cond); break;
1812 }
1813 }
1814
1815 // LIR_OpConvert
1816 void LIR_OpConvert::print_instr(outputStream* out) const {
1817 print_bytecode(out, bytecode());
1818 in_opr()->print(out); out->print(" ");
1819 result_opr()->print(out); out->print(" ");
1820 #ifdef PPC
1821 if(tmp1()->is_valid()) {
1822 tmp1()->print(out); out->print(" ");
1823 tmp2()->print(out); out->print(" ");
1824 }
1825 #endif
1826 }
1827
1828 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1829 switch(code) {
1830 case Bytecodes::_d2f: out->print("[d2f] "); break;
1831 case Bytecodes::_d2i: out->print("[d2i] "); break;
1832 case Bytecodes::_d2l: out->print("[d2l] "); break;
1833 case Bytecodes::_f2d: out->print("[f2d] "); break;
1834 case Bytecodes::_f2i: out->print("[f2i] "); break;
1835 case Bytecodes::_f2l: out->print("[f2l] "); break;
1836 case Bytecodes::_i2b: out->print("[i2b] "); break;
1837 case Bytecodes::_i2c: out->print("[i2c] "); break;
1838 case Bytecodes::_i2d: out->print("[i2d] "); break;
1839 case Bytecodes::_i2f: out->print("[i2f] "); break;
1840 case Bytecodes::_i2l: out->print("[i2l] "); break;
1841 case Bytecodes::_i2s: out->print("[i2s] "); break;
1842 case Bytecodes::_l2i: out->print("[l2i] "); break;
1843 case Bytecodes::_l2f: out->print("[l2f] "); break;
1844 case Bytecodes::_l2d: out->print("[l2d] "); break;
1845 default:
1846 out->print("[?%d]",code);
1847 break;
1848 }
1849 }
1850
1851 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1852 klass()->print(out); out->print(" ");
1853 obj()->print(out); out->print(" ");
1854 tmp1()->print(out); out->print(" ");
1855 tmp2()->print(out); out->print(" ");
1856 tmp3()->print(out); out->print(" ");
1857 tmp4()->print(out); out->print(" ");
1858 out->print("[hdr:%d]", header_size()); out->print(" ");
1859 out->print("[obj:%d]", object_size()); out->print(" ");
1860 out->print("[lbl:0x%x]", stub()->entry());
1861 }
1862
1863 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1864 _opr->print(out); out->print(" ");
1865 tmp()->print(out); out->print(" ");
1866 result_opr()->print(out); out->print(" ");
1867 }
1868
1869 // LIR_Op2
1870 void LIR_Op2::print_instr(outputStream* out) const {
1871 if (code() == lir_cmove) {
1872 print_condition(out, condition()); out->print(" ");
1873 }
1874 in_opr1()->print(out); out->print(" ");
1875 in_opr2()->print(out); out->print(" ");
1876 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
1877 result_opr()->print(out);
1878 }
1879
1880 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1881 klass()->print(out); out->print(" ");
1882 len()->print(out); out->print(" ");
1883 obj()->print(out); out->print(" ");
1884 tmp1()->print(out); out->print(" ");
1885 tmp2()->print(out); out->print(" ");
1886 tmp3()->print(out); out->print(" ");
1887 tmp4()->print(out); out->print(" ");
1888 out->print("[type:0x%x]", type()); out->print(" ");
1889 out->print("[label:0x%x]", stub()->entry());
1890 }
1891
1892
1893 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1894 object()->print(out); out->print(" ");
1895 if (code() == lir_store_check) {
1896 array()->print(out); out->print(" ");
1897 }
1898 if (code() != lir_store_check) {
1899 klass()->print_name_on(out); out->print(" ");
1900 if (fast_check()) out->print("fast_check ");
1901 }
1902 tmp1()->print(out); out->print(" ");
1903 tmp2()->print(out); out->print(" ");
1904 tmp3()->print(out); out->print(" ");
1905 result_opr()->print(out); out->print(" ");
1906 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1907 }
1908
1909
1910 // LIR_Op3
1911 void LIR_Op3::print_instr(outputStream* out) const {
1912 in_opr1()->print(out); out->print(" ");
1913 in_opr2()->print(out); out->print(" ");
1914 in_opr3()->print(out); out->print(" ");
1915 result_opr()->print(out);
1916 }
1917
1918
1919 void LIR_OpLock::print_instr(outputStream* out) const {
1920 hdr_opr()->print(out); out->print(" ");
1921 obj_opr()->print(out); out->print(" ");
1922 lock_opr()->print(out); out->print(" ");
1923 if (_scratch->is_valid()) {
1924 _scratch->print(out); out->print(" ");
1925 }
1926 out->print("[lbl:0x%x]", stub()->entry());
1927 }
1928
1929
1930 void LIR_OpDelay::print_instr(outputStream* out) const {
1931 _op->print_on(out);
1932 }
1933
1934
1935 // LIR_OpProfileCall
1936 void LIR_OpProfileCall::print_instr(outputStream* out) const {
1937 profiled_method()->name()->print_symbol_on(out);
1938 out->print(".");
1939 profiled_method()->holder()->name()->print_symbol_on(out);
1940 out->print(" @ %d ", profiled_bci());
1941 mdo()->print(out); out->print(" ");
1942 recv()->print(out); out->print(" ");
1943 tmp1()->print(out); out->print(" ");
1944 }
1945
1946 #endif // PRODUCT
1947
1948 // Implementation of LIR_InsertionBuffer
1949
1950 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
1951 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
1952
1953 int i = number_of_insertion_points() - 1;
1954 if (i < 0 || index_at(i) < index) {
1955 append_new(index, 1);
1956 } else {
1957 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
1958 assert(count_at(i) > 0, "check");
1959 set_count_at(i, count_at(i) + 1);
1960 }
1961 _ops.push(op);
1962
1963 DEBUG_ONLY(verify());
1964 }
1965
1966 #ifdef ASSERT
1967 void LIR_InsertionBuffer::verify() {
1968 int sum = 0;
1969 int prev_idx = -1;
1970
1971 for (int i = 0; i < number_of_insertion_points(); i++) {
1972 assert(prev_idx < index_at(i), "index must be ordered ascending");
1973 sum += count_at(i);
1974 }
1975 assert(sum == number_of_ops(), "wrong total sum");
1976 }
1977 #endif