1 /*
2 * Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "assembler_x86.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolderOop.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class RegisterSaver {
49 enum { FPU_regs_live = 8 /*for the FPU stack*/+8/*eight more for XMM registers*/ };
50 // Capture info about frame layout
51 enum layout {
52 fpu_state_off = 0,
53 fpu_state_end = fpu_state_off+FPUStateSizeInWords-1,
54 st0_off, st0H_off,
55 st1_off, st1H_off,
56 st2_off, st2H_off,
57 st3_off, st3H_off,
58 st4_off, st4H_off,
59 st5_off, st5H_off,
60 st6_off, st6H_off,
61 st7_off, st7H_off,
62
63 xmm0_off, xmm0H_off,
64 xmm1_off, xmm1H_off,
65 xmm2_off, xmm2H_off,
66 xmm3_off, xmm3H_off,
67 xmm4_off, xmm4H_off,
68 xmm5_off, xmm5H_off,
69 xmm6_off, xmm6H_off,
70 xmm7_off, xmm7H_off,
71 flags_off,
72 rdi_off,
73 rsi_off,
74 ignore_off, // extra copy of rbp,
75 rsp_off,
76 rbx_off,
77 rdx_off,
78 rcx_off,
79 rax_off,
80 // The frame sender code expects that rbp will be in the "natural" place and
81 // will override any oopMap setting for it. We must therefore force the layout
82 // so that it agrees with the frame sender code.
83 rbp_off,
84 return_off, // slot for return address
85 reg_save_size };
86
87
88 public:
89
90 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words,
91 int* total_frame_words, bool verify_fpu = true);
92 static void restore_live_registers(MacroAssembler* masm);
93
94 static int rax_offset() { return rax_off; }
95 static int rbx_offset() { return rbx_off; }
96
97 // Offsets into the register save area
98 // Used by deoptimization when it is managing result register
99 // values on its own
100
101 static int raxOffset(void) { return rax_off; }
102 static int rdxOffset(void) { return rdx_off; }
103 static int rbxOffset(void) { return rbx_off; }
104 static int xmm0Offset(void) { return xmm0_off; }
105 // This really returns a slot in the fp save area, which one is not important
106 static int fpResultOffset(void) { return st0_off; }
107
108 // During deoptimization only the result register need to be restored
109 // all the other values have already been extracted.
110
111 static void restore_result_registers(MacroAssembler* masm);
112
113 };
114
115 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words,
116 int* total_frame_words, bool verify_fpu) {
117
118 int frame_size_in_bytes = (reg_save_size + additional_frame_words) * wordSize;
119 int frame_words = frame_size_in_bytes / wordSize;
120 *total_frame_words = frame_words;
121
122 assert(FPUStateSizeInWords == 27, "update stack layout");
123
124 // save registers, fpu state, and flags
125 // We assume caller has already has return address slot on the stack
126 // We push epb twice in this sequence because we want the real rbp,
127 // to be under the return like a normal enter and we want to use pusha
128 // We push by hand instead of pusing push
129 __ enter();
130 __ pusha();
131 __ pushf();
132 __ subptr(rsp,FPU_regs_live*sizeof(jdouble)); // Push FPU registers space
133 __ push_FPU_state(); // Save FPU state & init
134
135 if (verify_fpu) {
136 // Some stubs may have non standard FPU control word settings so
137 // only check and reset the value when it required to be the
138 // standard value. The safepoint blob in particular can be used
139 // in methods which are using the 24 bit control word for
140 // optimized float math.
141
142 #ifdef ASSERT
143 // Make sure the control word has the expected value
144 Label ok;
145 __ cmpw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
146 __ jccb(Assembler::equal, ok);
147 __ stop("corrupted control word detected");
148 __ bind(ok);
149 #endif
150
151 // Reset the control word to guard against exceptions being unmasked
152 // since fstp_d can cause FPU stack underflow exceptions. Write it
153 // into the on stack copy and then reload that to make sure that the
154 // current and future values are correct.
155 __ movw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
156 }
157
158 __ frstor(Address(rsp, 0));
159 if (!verify_fpu) {
160 // Set the control word so that exceptions are masked for the
161 // following code.
162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
163 }
164
165 // Save the FPU registers in de-opt-able form
166
167 __ fstp_d(Address(rsp, st0_off*wordSize)); // st(0)
168 __ fstp_d(Address(rsp, st1_off*wordSize)); // st(1)
169 __ fstp_d(Address(rsp, st2_off*wordSize)); // st(2)
170 __ fstp_d(Address(rsp, st3_off*wordSize)); // st(3)
171 __ fstp_d(Address(rsp, st4_off*wordSize)); // st(4)
172 __ fstp_d(Address(rsp, st5_off*wordSize)); // st(5)
173 __ fstp_d(Address(rsp, st6_off*wordSize)); // st(6)
174 __ fstp_d(Address(rsp, st7_off*wordSize)); // st(7)
175
176 if( UseSSE == 1 ) { // Save the XMM state
177 __ movflt(Address(rsp,xmm0_off*wordSize),xmm0);
178 __ movflt(Address(rsp,xmm1_off*wordSize),xmm1);
179 __ movflt(Address(rsp,xmm2_off*wordSize),xmm2);
180 __ movflt(Address(rsp,xmm3_off*wordSize),xmm3);
181 __ movflt(Address(rsp,xmm4_off*wordSize),xmm4);
182 __ movflt(Address(rsp,xmm5_off*wordSize),xmm5);
183 __ movflt(Address(rsp,xmm6_off*wordSize),xmm6);
184 __ movflt(Address(rsp,xmm7_off*wordSize),xmm7);
185 } else if( UseSSE >= 2 ) {
186 __ movdbl(Address(rsp,xmm0_off*wordSize),xmm0);
187 __ movdbl(Address(rsp,xmm1_off*wordSize),xmm1);
188 __ movdbl(Address(rsp,xmm2_off*wordSize),xmm2);
189 __ movdbl(Address(rsp,xmm3_off*wordSize),xmm3);
190 __ movdbl(Address(rsp,xmm4_off*wordSize),xmm4);
191 __ movdbl(Address(rsp,xmm5_off*wordSize),xmm5);
192 __ movdbl(Address(rsp,xmm6_off*wordSize),xmm6);
193 __ movdbl(Address(rsp,xmm7_off*wordSize),xmm7);
194 }
195
196 // Set an oopmap for the call site. This oopmap will map all
197 // oop-registers and debug-info registers as callee-saved. This
198 // will allow deoptimization at this safepoint to find all possible
199 // debug-info recordings, as well as let GC find all oops.
200
201 OopMapSet *oop_maps = new OopMapSet();
202 OopMap* map = new OopMap( frame_words, 0 );
203
204 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_words)
205
206 map->set_callee_saved(STACK_OFFSET( rax_off), rax->as_VMReg());
207 map->set_callee_saved(STACK_OFFSET( rcx_off), rcx->as_VMReg());
208 map->set_callee_saved(STACK_OFFSET( rdx_off), rdx->as_VMReg());
209 map->set_callee_saved(STACK_OFFSET( rbx_off), rbx->as_VMReg());
210 // rbp, location is known implicitly, no oopMap
211 map->set_callee_saved(STACK_OFFSET( rsi_off), rsi->as_VMReg());
212 map->set_callee_saved(STACK_OFFSET( rdi_off), rdi->as_VMReg());
213 map->set_callee_saved(STACK_OFFSET(st0_off), as_FloatRegister(0)->as_VMReg());
214 map->set_callee_saved(STACK_OFFSET(st1_off), as_FloatRegister(1)->as_VMReg());
215 map->set_callee_saved(STACK_OFFSET(st2_off), as_FloatRegister(2)->as_VMReg());
216 map->set_callee_saved(STACK_OFFSET(st3_off), as_FloatRegister(3)->as_VMReg());
217 map->set_callee_saved(STACK_OFFSET(st4_off), as_FloatRegister(4)->as_VMReg());
218 map->set_callee_saved(STACK_OFFSET(st5_off), as_FloatRegister(5)->as_VMReg());
219 map->set_callee_saved(STACK_OFFSET(st6_off), as_FloatRegister(6)->as_VMReg());
220 map->set_callee_saved(STACK_OFFSET(st7_off), as_FloatRegister(7)->as_VMReg());
221 map->set_callee_saved(STACK_OFFSET(xmm0_off), xmm0->as_VMReg());
222 map->set_callee_saved(STACK_OFFSET(xmm1_off), xmm1->as_VMReg());
223 map->set_callee_saved(STACK_OFFSET(xmm2_off), xmm2->as_VMReg());
224 map->set_callee_saved(STACK_OFFSET(xmm3_off), xmm3->as_VMReg());
225 map->set_callee_saved(STACK_OFFSET(xmm4_off), xmm4->as_VMReg());
226 map->set_callee_saved(STACK_OFFSET(xmm5_off), xmm5->as_VMReg());
227 map->set_callee_saved(STACK_OFFSET(xmm6_off), xmm6->as_VMReg());
228 map->set_callee_saved(STACK_OFFSET(xmm7_off), xmm7->as_VMReg());
229 // %%% This is really a waste but we'll keep things as they were for now
230 if (true) {
231 #define NEXTREG(x) (x)->as_VMReg()->next()
232 map->set_callee_saved(STACK_OFFSET(st0H_off), NEXTREG(as_FloatRegister(0)));
233 map->set_callee_saved(STACK_OFFSET(st1H_off), NEXTREG(as_FloatRegister(1)));
234 map->set_callee_saved(STACK_OFFSET(st2H_off), NEXTREG(as_FloatRegister(2)));
235 map->set_callee_saved(STACK_OFFSET(st3H_off), NEXTREG(as_FloatRegister(3)));
236 map->set_callee_saved(STACK_OFFSET(st4H_off), NEXTREG(as_FloatRegister(4)));
237 map->set_callee_saved(STACK_OFFSET(st5H_off), NEXTREG(as_FloatRegister(5)));
238 map->set_callee_saved(STACK_OFFSET(st6H_off), NEXTREG(as_FloatRegister(6)));
239 map->set_callee_saved(STACK_OFFSET(st7H_off), NEXTREG(as_FloatRegister(7)));
240 map->set_callee_saved(STACK_OFFSET(xmm0H_off), NEXTREG(xmm0));
241 map->set_callee_saved(STACK_OFFSET(xmm1H_off), NEXTREG(xmm1));
242 map->set_callee_saved(STACK_OFFSET(xmm2H_off), NEXTREG(xmm2));
243 map->set_callee_saved(STACK_OFFSET(xmm3H_off), NEXTREG(xmm3));
244 map->set_callee_saved(STACK_OFFSET(xmm4H_off), NEXTREG(xmm4));
245 map->set_callee_saved(STACK_OFFSET(xmm5H_off), NEXTREG(xmm5));
246 map->set_callee_saved(STACK_OFFSET(xmm6H_off), NEXTREG(xmm6));
247 map->set_callee_saved(STACK_OFFSET(xmm7H_off), NEXTREG(xmm7));
248 #undef NEXTREG
249 #undef STACK_OFFSET
250 }
251
252 return map;
253
254 }
255
256 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
257
258 // Recover XMM & FPU state
259 if( UseSSE == 1 ) {
260 __ movflt(xmm0,Address(rsp,xmm0_off*wordSize));
261 __ movflt(xmm1,Address(rsp,xmm1_off*wordSize));
262 __ movflt(xmm2,Address(rsp,xmm2_off*wordSize));
263 __ movflt(xmm3,Address(rsp,xmm3_off*wordSize));
264 __ movflt(xmm4,Address(rsp,xmm4_off*wordSize));
265 __ movflt(xmm5,Address(rsp,xmm5_off*wordSize));
266 __ movflt(xmm6,Address(rsp,xmm6_off*wordSize));
267 __ movflt(xmm7,Address(rsp,xmm7_off*wordSize));
268 } else if( UseSSE >= 2 ) {
269 __ movdbl(xmm0,Address(rsp,xmm0_off*wordSize));
270 __ movdbl(xmm1,Address(rsp,xmm1_off*wordSize));
271 __ movdbl(xmm2,Address(rsp,xmm2_off*wordSize));
272 __ movdbl(xmm3,Address(rsp,xmm3_off*wordSize));
273 __ movdbl(xmm4,Address(rsp,xmm4_off*wordSize));
274 __ movdbl(xmm5,Address(rsp,xmm5_off*wordSize));
275 __ movdbl(xmm6,Address(rsp,xmm6_off*wordSize));
276 __ movdbl(xmm7,Address(rsp,xmm7_off*wordSize));
277 }
278 __ pop_FPU_state();
279 __ addptr(rsp, FPU_regs_live*sizeof(jdouble)); // Pop FPU registers
280
281 __ popf();
282 __ popa();
283 // Get the rbp, described implicitly by the frame sender code (no oopMap)
284 __ pop(rbp);
285
286 }
287
288 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
289
290 // Just restore result register. Only used by deoptimization. By
291 // now any callee save register that needs to be restore to a c2
292 // caller of the deoptee has been extracted into the vframeArray
293 // and will be stuffed into the c2i adapter we create for later
294 // restoration so only result registers need to be restored here.
295 //
296
297 __ frstor(Address(rsp, 0)); // Restore fpu state
298
299 // Recover XMM & FPU state
300 if( UseSSE == 1 ) {
301 __ movflt(xmm0, Address(rsp, xmm0_off*wordSize));
302 } else if( UseSSE >= 2 ) {
303 __ movdbl(xmm0, Address(rsp, xmm0_off*wordSize));
304 }
305 __ movptr(rax, Address(rsp, rax_off*wordSize));
306 __ movptr(rdx, Address(rsp, rdx_off*wordSize));
307 // Pop all of the register save are off the stack except the return address
308 __ addptr(rsp, return_off * wordSize);
309 }
310
311 // The java_calling_convention describes stack locations as ideal slots on
312 // a frame with no abi restrictions. Since we must observe abi restrictions
313 // (like the placement of the register window) the slots must be biased by
314 // the following value.
315 static int reg2offset_in(VMReg r) {
316 // Account for saved rbp, and return address
317 // This should really be in_preserve_stack_slots
318 return (r->reg2stack() + 2) * VMRegImpl::stack_slot_size;
319 }
320
321 static int reg2offset_out(VMReg r) {
322 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
323 }
324
325 // ---------------------------------------------------------------------------
326 // Read the array of BasicTypes from a signature, and compute where the
327 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
328 // quantities. Values less than SharedInfo::stack0 are registers, those above
329 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
330 // as framesizes are fixed.
331 // VMRegImpl::stack0 refers to the first slot 0(sp).
332 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
333 // up to RegisterImpl::number_of_registers) are the 32-bit
334 // integer registers.
335
336 // Pass first two oop/int args in registers ECX and EDX.
337 // Pass first two float/double args in registers XMM0 and XMM1.
338 // Doubles have precedence, so if you pass a mix of floats and doubles
339 // the doubles will grab the registers before the floats will.
340
341 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
342 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
343 // units regardless of build. Of course for i486 there is no 64 bit build
344
345
346 // ---------------------------------------------------------------------------
347 // The compiled Java calling convention.
348 // Pass first two oop/int args in registers ECX and EDX.
349 // Pass first two float/double args in registers XMM0 and XMM1.
350 // Doubles have precedence, so if you pass a mix of floats and doubles
351 // the doubles will grab the registers before the floats will.
352 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
353 VMRegPair *regs,
354 int total_args_passed,
355 int is_outgoing) {
356 uint stack = 0; // Starting stack position for args on stack
357
358
359 // Pass first two oop/int args in registers ECX and EDX.
360 uint reg_arg0 = 9999;
361 uint reg_arg1 = 9999;
362
363 // Pass first two float/double args in registers XMM0 and XMM1.
364 // Doubles have precedence, so if you pass a mix of floats and doubles
365 // the doubles will grab the registers before the floats will.
366 // CNC - TURNED OFF FOR non-SSE.
367 // On Intel we have to round all doubles (and most floats) at
368 // call sites by storing to the stack in any case.
369 // UseSSE=0 ==> Don't Use ==> 9999+0
370 // UseSSE=1 ==> Floats only ==> 9999+1
371 // UseSSE>=2 ==> Floats or doubles ==> 9999+2
372 enum { fltarg_dontuse = 9999+0, fltarg_float_only = 9999+1, fltarg_flt_dbl = 9999+2 };
373 uint fargs = (UseSSE>=2) ? 2 : UseSSE;
374 uint freg_arg0 = 9999+fargs;
375 uint freg_arg1 = 9999+fargs;
376
377 // Pass doubles & longs aligned on the stack. First count stack slots for doubles
378 int i;
379 for( i = 0; i < total_args_passed; i++) {
380 if( sig_bt[i] == T_DOUBLE ) {
381 // first 2 doubles go in registers
382 if( freg_arg0 == fltarg_flt_dbl ) freg_arg0 = i;
383 else if( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i;
384 else // Else double is passed low on the stack to be aligned.
385 stack += 2;
386 } else if( sig_bt[i] == T_LONG ) {
387 stack += 2;
388 }
389 }
390 int dstack = 0; // Separate counter for placing doubles
391
392 // Now pick where all else goes.
393 for( i = 0; i < total_args_passed; i++) {
394 // From the type and the argument number (count) compute the location
395 switch( sig_bt[i] ) {
396 case T_SHORT:
397 case T_CHAR:
398 case T_BYTE:
399 case T_BOOLEAN:
400 case T_INT:
401 case T_ARRAY:
402 case T_OBJECT:
403 case T_ADDRESS:
404 if( reg_arg0 == 9999 ) {
405 reg_arg0 = i;
406 regs[i].set1(rcx->as_VMReg());
407 } else if( reg_arg1 == 9999 ) {
408 reg_arg1 = i;
409 regs[i].set1(rdx->as_VMReg());
410 } else {
411 regs[i].set1(VMRegImpl::stack2reg(stack++));
412 }
413 break;
414 case T_FLOAT:
415 if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
416 freg_arg0 = i;
417 regs[i].set1(xmm0->as_VMReg());
418 } else if( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
419 freg_arg1 = i;
420 regs[i].set1(xmm1->as_VMReg());
421 } else {
422 regs[i].set1(VMRegImpl::stack2reg(stack++));
423 }
424 break;
425 case T_LONG:
426 assert(sig_bt[i+1] == T_VOID, "missing Half" );
427 regs[i].set2(VMRegImpl::stack2reg(dstack));
428 dstack += 2;
429 break;
430 case T_DOUBLE:
431 assert(sig_bt[i+1] == T_VOID, "missing Half" );
432 if( freg_arg0 == (uint)i ) {
433 regs[i].set2(xmm0->as_VMReg());
434 } else if( freg_arg1 == (uint)i ) {
435 regs[i].set2(xmm1->as_VMReg());
436 } else {
437 regs[i].set2(VMRegImpl::stack2reg(dstack));
438 dstack += 2;
439 }
440 break;
441 case T_VOID: regs[i].set_bad(); break;
442 break;
443 default:
444 ShouldNotReachHere();
445 break;
446 }
447 }
448
449 // return value can be odd number of VMRegImpl stack slots make multiple of 2
450 return round_to(stack, 2);
451 }
452
453 // Patch the callers callsite with entry to compiled code if it exists.
454 static void patch_callers_callsite(MacroAssembler *masm) {
455 Label L;
456 __ verify_oop(rbx);
457 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
458 __ jcc(Assembler::equal, L);
459 // Schedule the branch target address early.
460 // Call into the VM to patch the caller, then jump to compiled callee
461 // rax, isn't live so capture return address while we easily can
462 __ movptr(rax, Address(rsp, 0));
463 __ pusha();
464 __ pushf();
465
466 if (UseSSE == 1) {
467 __ subptr(rsp, 2*wordSize);
468 __ movflt(Address(rsp, 0), xmm0);
469 __ movflt(Address(rsp, wordSize), xmm1);
470 }
471 if (UseSSE >= 2) {
472 __ subptr(rsp, 4*wordSize);
473 __ movdbl(Address(rsp, 0), xmm0);
474 __ movdbl(Address(rsp, 2*wordSize), xmm1);
475 }
476 #ifdef COMPILER2
477 // C2 may leave the stack dirty if not in SSE2+ mode
478 if (UseSSE >= 2) {
479 __ verify_FPU(0, "c2i transition should have clean FPU stack");
480 } else {
481 __ empty_FPU_stack();
482 }
483 #endif /* COMPILER2 */
484
485 // VM needs caller's callsite
486 __ push(rax);
487 // VM needs target method
488 __ push(rbx);
489 __ verify_oop(rbx);
490 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
491 __ addptr(rsp, 2*wordSize);
492
493 if (UseSSE == 1) {
494 __ movflt(xmm0, Address(rsp, 0));
495 __ movflt(xmm1, Address(rsp, wordSize));
496 __ addptr(rsp, 2*wordSize);
497 }
498 if (UseSSE >= 2) {
499 __ movdbl(xmm0, Address(rsp, 0));
500 __ movdbl(xmm1, Address(rsp, 2*wordSize));
501 __ addptr(rsp, 4*wordSize);
502 }
503
504 __ popf();
505 __ popa();
506 __ bind(L);
507 }
508
509
510 static void move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) {
511 int next_off = st_off - Interpreter::stackElementSize;
512 __ movdbl(Address(rsp, next_off), r);
513 }
514
515 static void gen_c2i_adapter(MacroAssembler *masm,
516 int total_args_passed,
517 int comp_args_on_stack,
518 const BasicType *sig_bt,
519 const VMRegPair *regs,
520 Label& skip_fixup) {
521 // Before we get into the guts of the C2I adapter, see if we should be here
522 // at all. We've come from compiled code and are attempting to jump to the
523 // interpreter, which means the caller made a static call to get here
524 // (vcalls always get a compiled target if there is one). Check for a
525 // compiled target. If there is one, we need to patch the caller's call.
526 patch_callers_callsite(masm);
527
528 __ bind(skip_fixup);
529
530 #ifdef COMPILER2
531 // C2 may leave the stack dirty if not in SSE2+ mode
532 if (UseSSE >= 2) {
533 __ verify_FPU(0, "c2i transition should have clean FPU stack");
534 } else {
535 __ empty_FPU_stack();
536 }
537 #endif /* COMPILER2 */
538
539 // Since all args are passed on the stack, total_args_passed * interpreter_
540 // stack_element_size is the
541 // space we need.
542 int extraspace = total_args_passed * Interpreter::stackElementSize;
543
544 // Get return address
545 __ pop(rax);
546
547 // set senderSP value
548 __ movptr(rsi, rsp);
549
550 __ subptr(rsp, extraspace);
551
552 // Now write the args into the outgoing interpreter space
553 for (int i = 0; i < total_args_passed; i++) {
554 if (sig_bt[i] == T_VOID) {
555 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
556 continue;
557 }
558
559 // st_off points to lowest address on stack.
560 int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize;
561 int next_off = st_off - Interpreter::stackElementSize;
562
563 // Say 4 args:
564 // i st_off
565 // 0 12 T_LONG
566 // 1 8 T_VOID
567 // 2 4 T_OBJECT
568 // 3 0 T_BOOL
569 VMReg r_1 = regs[i].first();
570 VMReg r_2 = regs[i].second();
571 if (!r_1->is_valid()) {
572 assert(!r_2->is_valid(), "");
573 continue;
574 }
575
576 if (r_1->is_stack()) {
577 // memory to memory use fpu stack top
578 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
579
580 if (!r_2->is_valid()) {
581 __ movl(rdi, Address(rsp, ld_off));
582 __ movptr(Address(rsp, st_off), rdi);
583 } else {
584
585 // ld_off == LSW, ld_off+VMRegImpl::stack_slot_size == MSW
586 // st_off == MSW, st_off-wordSize == LSW
587
588 __ movptr(rdi, Address(rsp, ld_off));
589 __ movptr(Address(rsp, next_off), rdi);
590 #ifndef _LP64
591 __ movptr(rdi, Address(rsp, ld_off + wordSize));
592 __ movptr(Address(rsp, st_off), rdi);
593 #else
594 #ifdef ASSERT
595 // Overwrite the unused slot with known junk
596 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
597 __ movptr(Address(rsp, st_off), rax);
598 #endif /* ASSERT */
599 #endif // _LP64
600 }
601 } else if (r_1->is_Register()) {
602 Register r = r_1->as_Register();
603 if (!r_2->is_valid()) {
604 __ movl(Address(rsp, st_off), r);
605 } else {
606 // long/double in gpr
607 NOT_LP64(ShouldNotReachHere());
608 // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
609 // T_DOUBLE and T_LONG use two slots in the interpreter
610 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
611 // long/double in gpr
612 #ifdef ASSERT
613 // Overwrite the unused slot with known junk
614 LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
615 __ movptr(Address(rsp, st_off), rax);
616 #endif /* ASSERT */
617 __ movptr(Address(rsp, next_off), r);
618 } else {
619 __ movptr(Address(rsp, st_off), r);
620 }
621 }
622 } else {
623 assert(r_1->is_XMMRegister(), "");
624 if (!r_2->is_valid()) {
625 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
626 } else {
627 assert(sig_bt[i] == T_DOUBLE || sig_bt[i] == T_LONG, "wrong type");
628 move_c2i_double(masm, r_1->as_XMMRegister(), st_off);
629 }
630 }
631 }
632
633 // Schedule the branch target address early.
634 __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
635 // And repush original return address
636 __ push(rax);
637 __ jmp(rcx);
638 }
639
640
641 static void move_i2c_double(MacroAssembler *masm, XMMRegister r, Register saved_sp, int ld_off) {
642 int next_val_off = ld_off - Interpreter::stackElementSize;
643 __ movdbl(r, Address(saved_sp, next_val_off));
644 }
645
646 static void gen_i2c_adapter(MacroAssembler *masm,
647 int total_args_passed,
648 int comp_args_on_stack,
649 const BasicType *sig_bt,
650 const VMRegPair *regs) {
651
652 // Note: rsi contains the senderSP on entry. We must preserve it since
653 // we may do a i2c -> c2i transition if we lose a race where compiled
654 // code goes non-entrant while we get args ready.
655
656 // Pick up the return address
657 __ movptr(rax, Address(rsp, 0));
658
659 // Must preserve original SP for loading incoming arguments because
660 // we need to align the outgoing SP for compiled code.
661 __ movptr(rdi, rsp);
662
663 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
664 // in registers, we will occasionally have no stack args.
665 int comp_words_on_stack = 0;
666 if (comp_args_on_stack) {
667 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
668 // registers are below. By subtracting stack0, we either get a negative
669 // number (all values in registers) or the maximum stack slot accessed.
670 // int comp_args_on_stack = VMRegImpl::reg2stack(max_arg);
671 // Convert 4-byte stack slots to words.
672 comp_words_on_stack = round_to(comp_args_on_stack*4, wordSize)>>LogBytesPerWord;
673 // Round up to miminum stack alignment, in wordSize
674 comp_words_on_stack = round_to(comp_words_on_stack, 2);
675 __ subptr(rsp, comp_words_on_stack * wordSize);
676 }
677
678 // Align the outgoing SP
679 __ andptr(rsp, -(StackAlignmentInBytes));
680
681 // push the return address on the stack (note that pushing, rather
682 // than storing it, yields the correct frame alignment for the callee)
683 __ push(rax);
684
685 // Put saved SP in another register
686 const Register saved_sp = rax;
687 __ movptr(saved_sp, rdi);
688
689
690 // Will jump to the compiled code just as if compiled code was doing it.
691 // Pre-load the register-jump target early, to schedule it better.
692 __ movptr(rdi, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
693
694 // Now generate the shuffle code. Pick up all register args and move the
695 // rest through the floating point stack top.
696 for (int i = 0; i < total_args_passed; i++) {
697 if (sig_bt[i] == T_VOID) {
698 // Longs and doubles are passed in native word order, but misaligned
699 // in the 32-bit build.
700 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
701 continue;
702 }
703
704 // Pick up 0, 1 or 2 words from SP+offset.
705
706 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
707 "scrambled load targets?");
708 // Load in argument order going down.
709 int ld_off = (total_args_passed - i) * Interpreter::stackElementSize;
710 // Point to interpreter value (vs. tag)
711 int next_off = ld_off - Interpreter::stackElementSize;
712 //
713 //
714 //
715 VMReg r_1 = regs[i].first();
716 VMReg r_2 = regs[i].second();
717 if (!r_1->is_valid()) {
718 assert(!r_2->is_valid(), "");
719 continue;
720 }
721 if (r_1->is_stack()) {
722 // Convert stack slot to an SP offset (+ wordSize to account for return address )
723 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
724
725 // We can use rsi as a temp here because compiled code doesn't need rsi as an input
726 // and if we end up going thru a c2i because of a miss a reasonable value of rsi
727 // we be generated.
728 if (!r_2->is_valid()) {
729 // __ fld_s(Address(saved_sp, ld_off));
730 // __ fstp_s(Address(rsp, st_off));
731 __ movl(rsi, Address(saved_sp, ld_off));
732 __ movptr(Address(rsp, st_off), rsi);
733 } else {
734 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
735 // are accessed as negative so LSW is at LOW address
736
737 // ld_off is MSW so get LSW
738 // st_off is LSW (i.e. reg.first())
739 // __ fld_d(Address(saved_sp, next_off));
740 // __ fstp_d(Address(rsp, st_off));
741 //
742 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
743 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
744 // So we must adjust where to pick up the data to match the interpreter.
745 //
746 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
747 // are accessed as negative so LSW is at LOW address
748
749 // ld_off is MSW so get LSW
750 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
751 next_off : ld_off;
752 __ movptr(rsi, Address(saved_sp, offset));
753 __ movptr(Address(rsp, st_off), rsi);
754 #ifndef _LP64
755 __ movptr(rsi, Address(saved_sp, ld_off));
756 __ movptr(Address(rsp, st_off + wordSize), rsi);
757 #endif // _LP64
758 }
759 } else if (r_1->is_Register()) { // Register argument
760 Register r = r_1->as_Register();
761 assert(r != rax, "must be different");
762 if (r_2->is_valid()) {
763 //
764 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
765 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
766 // So we must adjust where to pick up the data to match the interpreter.
767
768 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
769 next_off : ld_off;
770
771 // this can be a misaligned move
772 __ movptr(r, Address(saved_sp, offset));
773 #ifndef _LP64
774 assert(r_2->as_Register() != rax, "need another temporary register");
775 // Remember r_1 is low address (and LSB on x86)
776 // So r_2 gets loaded from high address regardless of the platform
777 __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
778 #endif // _LP64
779 } else {
780 __ movl(r, Address(saved_sp, ld_off));
781 }
782 } else {
783 assert(r_1->is_XMMRegister(), "");
784 if (!r_2->is_valid()) {
785 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
786 } else {
787 move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
788 }
789 }
790 }
791
792 // 6243940 We might end up in handle_wrong_method if
793 // the callee is deoptimized as we race thru here. If that
794 // happens we don't want to take a safepoint because the
795 // caller frame will look interpreted and arguments are now
796 // "compiled" so it is much better to make this transition
797 // invisible to the stack walking code. Unfortunately if
798 // we try and find the callee by normal means a safepoint
799 // is possible. So we stash the desired callee in the thread
800 // and the vm will find there should this case occur.
801
802 __ get_thread(rax);
803 __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
804
805 // move methodOop to rax, in case we end up in an c2i adapter.
806 // the c2i adapters expect methodOop in rax, (c2) because c2's
807 // resolve stubs return the result (the method) in rax,.
808 // I'd love to fix this.
809 __ mov(rax, rbx);
810
811 __ jmp(rdi);
812 }
813
814 // ---------------------------------------------------------------
815 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
816 int total_args_passed,
817 int comp_args_on_stack,
818 const BasicType *sig_bt,
819 const VMRegPair *regs,
820 AdapterFingerPrint* fingerprint) {
821 address i2c_entry = __ pc();
822
823 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
824
825 // -------------------------------------------------------------------------
826 // Generate a C2I adapter. On entry we know rbx, holds the methodOop during calls
827 // to the interpreter. The args start out packed in the compiled layout. They
828 // need to be unpacked into the interpreter layout. This will almost always
829 // require some stack space. We grow the current (compiled) stack, then repack
830 // the args. We finally end in a jump to the generic interpreter entry point.
831 // On exit from the interpreter, the interpreter will restore our SP (lest the
832 // compiled code, which relys solely on SP and not EBP, get sick).
833
834 address c2i_unverified_entry = __ pc();
835 Label skip_fixup;
836
837 Register holder = rax;
838 Register receiver = rcx;
839 Register temp = rbx;
840
841 {
842
843 Label missed;
844
845 __ verify_oop(holder);
846 __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
847 __ verify_oop(temp);
848
849 __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
850 __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
851 __ jcc(Assembler::notEqual, missed);
852 // Method might have been compiled since the call site was patched to
853 // interpreted if that is the case treat it as a miss so we can get
854 // the call site corrected.
855 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
856 __ jcc(Assembler::equal, skip_fixup);
857
858 __ bind(missed);
859 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
860 }
861
862 address c2i_entry = __ pc();
863
864 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
865
866 __ flush();
867 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
868 }
869
870 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
871 VMRegPair *regs,
872 int total_args_passed) {
873 // We return the amount of VMRegImpl stack slots we need to reserve for all
874 // the arguments NOT counting out_preserve_stack_slots.
875
876 uint stack = 0; // All arguments on stack
877
878 for( int i = 0; i < total_args_passed; i++) {
879 // From the type and the argument number (count) compute the location
880 switch( sig_bt[i] ) {
881 case T_BOOLEAN:
882 case T_CHAR:
883 case T_FLOAT:
884 case T_BYTE:
885 case T_SHORT:
886 case T_INT:
887 case T_OBJECT:
888 case T_ARRAY:
889 case T_ADDRESS:
890 regs[i].set1(VMRegImpl::stack2reg(stack++));
891 break;
892 case T_LONG:
893 case T_DOUBLE: // The stack numbering is reversed from Java
894 // Since C arguments do not get reversed, the ordering for
895 // doubles on the stack must be opposite the Java convention
896 assert(sig_bt[i+1] == T_VOID, "missing Half" );
897 regs[i].set2(VMRegImpl::stack2reg(stack));
898 stack += 2;
899 break;
900 case T_VOID: regs[i].set_bad(); break;
901 default:
902 ShouldNotReachHere();
903 break;
904 }
905 }
906 return stack;
907 }
908
909 // A simple move of integer like type
910 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
911 if (src.first()->is_stack()) {
912 if (dst.first()->is_stack()) {
913 // stack to stack
914 // __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
915 // __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
916 __ movl2ptr(rax, Address(rbp, reg2offset_in(src.first())));
917 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
918 } else {
919 // stack to reg
920 __ movl2ptr(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
921 }
922 } else if (dst.first()->is_stack()) {
923 // reg to stack
924 // no need to sign extend on 64bit
925 __ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
926 } else {
927 if (dst.first() != src.first()) {
928 __ mov(dst.first()->as_Register(), src.first()->as_Register());
929 }
930 }
931 }
932
933 // An oop arg. Must pass a handle not the oop itself
934 static void object_move(MacroAssembler* masm,
935 OopMap* map,
936 int oop_handle_offset,
937 int framesize_in_slots,
938 VMRegPair src,
939 VMRegPair dst,
940 bool is_receiver,
941 int* receiver_offset) {
942
943 // Because of the calling conventions we know that src can be a
944 // register or a stack location. dst can only be a stack location.
945
946 assert(dst.first()->is_stack(), "must be stack");
947 // must pass a handle. First figure out the location we use as a handle
948
949 if (src.first()->is_stack()) {
950 // Oop is already on the stack as an argument
951 Register rHandle = rax;
952 Label nil;
953 __ xorptr(rHandle, rHandle);
954 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
955 __ jcc(Assembler::equal, nil);
956 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
957 __ bind(nil);
958 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
959
960 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
961 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
962 if (is_receiver) {
963 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
964 }
965 } else {
966 // Oop is in an a register we must store it to the space we reserve
967 // on the stack for oop_handles
968 const Register rOop = src.first()->as_Register();
969 const Register rHandle = rax;
970 int oop_slot = (rOop == rcx ? 0 : 1) * VMRegImpl::slots_per_word + oop_handle_offset;
971 int offset = oop_slot*VMRegImpl::stack_slot_size;
972 Label skip;
973 __ movptr(Address(rsp, offset), rOop);
974 map->set_oop(VMRegImpl::stack2reg(oop_slot));
975 __ xorptr(rHandle, rHandle);
976 __ cmpptr(rOop, (int32_t)NULL_WORD);
977 __ jcc(Assembler::equal, skip);
978 __ lea(rHandle, Address(rsp, offset));
979 __ bind(skip);
980 // Store the handle parameter
981 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
982 if (is_receiver) {
983 *receiver_offset = offset;
984 }
985 }
986 }
987
988 // A float arg may have to do float reg int reg conversion
989 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
990 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
991
992 // Because of the calling convention we know that src is either a stack location
993 // or an xmm register. dst can only be a stack location.
994
995 assert(dst.first()->is_stack() && ( src.first()->is_stack() || src.first()->is_XMMRegister()), "bad parameters");
996
997 if (src.first()->is_stack()) {
998 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
999 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1000 } else {
1001 // reg to stack
1002 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1003 }
1004 }
1005
1006 // A long move
1007 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1008
1009 // The only legal possibility for a long_move VMRegPair is:
1010 // 1: two stack slots (possibly unaligned)
1011 // as neither the java or C calling convention will use registers
1012 // for longs.
1013
1014 if (src.first()->is_stack() && dst.first()->is_stack()) {
1015 assert(src.second()->is_stack() && dst.second()->is_stack(), "must be all stack");
1016 __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
1017 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
1018 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1019 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
1020 } else {
1021 ShouldNotReachHere();
1022 }
1023 }
1024
1025 // A double move
1026 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1027
1028 // The only legal possibilities for a double_move VMRegPair are:
1029 // The painful thing here is that like long_move a VMRegPair might be
1030
1031 // Because of the calling convention we know that src is either
1032 // 1: a single physical register (xmm registers only)
1033 // 2: two stack slots (possibly unaligned)
1034 // dst can only be a pair of stack slots.
1035
1036 assert(dst.first()->is_stack() && (src.first()->is_XMMRegister() || src.first()->is_stack()), "bad args");
1037
1038 if (src.first()->is_stack()) {
1039 // source is all stack
1040 __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
1041 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
1042 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1043 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
1044 } else {
1045 // reg to stack
1046 // No worries about stack alignment
1047 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1048 }
1049 }
1050
1051
1052 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1053 // We always ignore the frame_slots arg and just use the space just below frame pointer
1054 // which by this time is free to use
1055 switch (ret_type) {
1056 case T_FLOAT:
1057 __ fstp_s(Address(rbp, -wordSize));
1058 break;
1059 case T_DOUBLE:
1060 __ fstp_d(Address(rbp, -2*wordSize));
1061 break;
1062 case T_VOID: break;
1063 case T_LONG:
1064 __ movptr(Address(rbp, -wordSize), rax);
1065 NOT_LP64(__ movptr(Address(rbp, -2*wordSize), rdx));
1066 break;
1067 default: {
1068 __ movptr(Address(rbp, -wordSize), rax);
1069 }
1070 }
1071 }
1072
1073 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1074 // We always ignore the frame_slots arg and just use the space just below frame pointer
1075 // which by this time is free to use
1076 switch (ret_type) {
1077 case T_FLOAT:
1078 __ fld_s(Address(rbp, -wordSize));
1079 break;
1080 case T_DOUBLE:
1081 __ fld_d(Address(rbp, -2*wordSize));
1082 break;
1083 case T_LONG:
1084 __ movptr(rax, Address(rbp, -wordSize));
1085 NOT_LP64(__ movptr(rdx, Address(rbp, -2*wordSize)));
1086 break;
1087 case T_VOID: break;
1088 default: {
1089 __ movptr(rax, Address(rbp, -wordSize));
1090 }
1091 }
1092 }
1093
1094 // ---------------------------------------------------------------------------
1095 // Generate a native wrapper for a given method. The method takes arguments
1096 // in the Java compiled code convention, marshals them to the native
1097 // convention (handlizes oops, etc), transitions to native, makes the call,
1098 // returns to java state (possibly blocking), unhandlizes any result and
1099 // returns.
1100 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
1101 methodHandle method,
1102 int compile_id,
1103 int total_in_args,
1104 int comp_args_on_stack,
1105 BasicType *in_sig_bt,
1106 VMRegPair *in_regs,
1107 BasicType ret_type) {
1108
1109 // An OopMap for lock (and class if static)
1110 OopMapSet *oop_maps = new OopMapSet();
1111
1112 // We have received a description of where all the java arg are located
1113 // on entry to the wrapper. We need to convert these args to where
1114 // the jni function will expect them. To figure out where they go
1115 // we convert the java signature to a C signature by inserting
1116 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1117
1118 int total_c_args = total_in_args + 1;
1119 if (method->is_static()) {
1120 total_c_args++;
1121 }
1122
1123 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1124 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1125
1126 int argc = 0;
1127 out_sig_bt[argc++] = T_ADDRESS;
1128 if (method->is_static()) {
1129 out_sig_bt[argc++] = T_OBJECT;
1130 }
1131
1132 int i;
1133 for (i = 0; i < total_in_args ; i++ ) {
1134 out_sig_bt[argc++] = in_sig_bt[i];
1135 }
1136
1137
1138 // Now figure out where the args must be stored and how much stack space
1139 // they require (neglecting out_preserve_stack_slots but space for storing
1140 // the 1st six register arguments). It's weird see int_stk_helper.
1141 //
1142 int out_arg_slots;
1143 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1144
1145 // Compute framesize for the wrapper. We need to handlize all oops in
1146 // registers a max of 2 on x86.
1147
1148 // Calculate the total number of stack slots we will need.
1149
1150 // First count the abi requirement plus all of the outgoing args
1151 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1152
1153 // Now the space for the inbound oop handle area
1154
1155 int oop_handle_offset = stack_slots;
1156 stack_slots += 2*VMRegImpl::slots_per_word;
1157
1158 // Now any space we need for handlizing a klass if static method
1159
1160 int klass_slot_offset = 0;
1161 int klass_offset = -1;
1162 int lock_slot_offset = 0;
1163 bool is_static = false;
1164 int oop_temp_slot_offset = 0;
1165
1166 if (method->is_static()) {
1167 klass_slot_offset = stack_slots;
1168 stack_slots += VMRegImpl::slots_per_word;
1169 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1170 is_static = true;
1171 }
1172
1173 // Plus a lock if needed
1174
1175 if (method->is_synchronized()) {
1176 lock_slot_offset = stack_slots;
1177 stack_slots += VMRegImpl::slots_per_word;
1178 }
1179
1180 // Now a place (+2) to save return values or temp during shuffling
1181 // + 2 for return address (which we own) and saved rbp,
1182 stack_slots += 4;
1183
1184 // Ok The space we have allocated will look like:
1185 //
1186 //
1187 // FP-> | |
1188 // |---------------------|
1189 // | 2 slots for moves |
1190 // |---------------------|
1191 // | lock box (if sync) |
1192 // |---------------------| <- lock_slot_offset (-lock_slot_rbp_offset)
1193 // | klass (if static) |
1194 // |---------------------| <- klass_slot_offset
1195 // | oopHandle area |
1196 // |---------------------| <- oop_handle_offset (a max of 2 registers)
1197 // | outbound memory |
1198 // | based arguments |
1199 // | |
1200 // |---------------------|
1201 // | |
1202 // SP-> | out_preserved_slots |
1203 //
1204 //
1205 // ****************************************************************************
1206 // WARNING - on Windows Java Natives use pascal calling convention and pop the
1207 // arguments off of the stack after the jni call. Before the call we can use
1208 // instructions that are SP relative. After the jni call we switch to FP
1209 // relative instructions instead of re-adjusting the stack on windows.
1210 // ****************************************************************************
1211
1212
1213 // Now compute actual number of stack words we need rounding to make
1214 // stack properly aligned.
1215 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1216
1217 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1218
1219 intptr_t start = (intptr_t)__ pc();
1220
1221 // First thing make an ic check to see if we should even be here
1222
1223 // We are free to use all registers as temps without saving them and
1224 // restoring them except rbp,. rbp, is the only callee save register
1225 // as far as the interpreter and the compiler(s) are concerned.
1226
1227
1228 const Register ic_reg = rax;
1229 const Register receiver = rcx;
1230 Label hit;
1231 Label exception_pending;
1232
1233
1234 __ verify_oop(receiver);
1235 __ cmpptr(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
1236 __ jcc(Assembler::equal, hit);
1237
1238 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1239
1240 // verified entry must be aligned for code patching.
1241 // and the first 5 bytes must be in the same cache line
1242 // if we align at 8 then we will be sure 5 bytes are in the same line
1243 __ align(8);
1244
1245 __ bind(hit);
1246
1247 int vep_offset = ((intptr_t)__ pc()) - start;
1248
1249 #ifdef COMPILER1
1250 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1251 // Object.hashCode can pull the hashCode from the header word
1252 // instead of doing a full VM transition once it's been computed.
1253 // Since hashCode is usually polymorphic at call sites we can't do
1254 // this optimization at the call site without a lot of work.
1255 Label slowCase;
1256 Register receiver = rcx;
1257 Register result = rax;
1258 __ movptr(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
1259
1260 // check if locked
1261 __ testptr(result, markOopDesc::unlocked_value);
1262 __ jcc (Assembler::zero, slowCase);
1263
1264 if (UseBiasedLocking) {
1265 // Check if biased and fall through to runtime if so
1266 __ testptr(result, markOopDesc::biased_lock_bit_in_place);
1267 __ jcc (Assembler::notZero, slowCase);
1268 }
1269
1270 // get hash
1271 __ andptr(result, markOopDesc::hash_mask_in_place);
1272 // test if hashCode exists
1273 __ jcc (Assembler::zero, slowCase);
1274 __ shrptr(result, markOopDesc::hash_shift);
1275 __ ret(0);
1276 __ bind (slowCase);
1277 }
1278 #endif // COMPILER1
1279
1280 // The instruction at the verified entry point must be 5 bytes or longer
1281 // because it can be patched on the fly by make_non_entrant. The stack bang
1282 // instruction fits that requirement.
1283
1284 // Generate stack overflow check
1285
1286 if (UseStackBanging) {
1287 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1288 } else {
1289 // need a 5 byte instruction to allow MT safe patching to non-entrant
1290 __ fat_nop();
1291 }
1292
1293 // Generate a new frame for the wrapper.
1294 __ enter();
1295 // -2 because return address is already present and so is saved rbp,
1296 __ subptr(rsp, stack_size - 2*wordSize);
1297
1298 // Frame is now completed as far a size and linkage.
1299
1300 int frame_complete = ((intptr_t)__ pc()) - start;
1301
1302 // Calculate the difference between rsp and rbp,. We need to know it
1303 // after the native call because on windows Java Natives will pop
1304 // the arguments and it is painful to do rsp relative addressing
1305 // in a platform independent way. So after the call we switch to
1306 // rbp, relative addressing.
1307
1308 int fp_adjustment = stack_size - 2*wordSize;
1309
1310 #ifdef COMPILER2
1311 // C2 may leave the stack dirty if not in SSE2+ mode
1312 if (UseSSE >= 2) {
1313 __ verify_FPU(0, "c2i transition should have clean FPU stack");
1314 } else {
1315 __ empty_FPU_stack();
1316 }
1317 #endif /* COMPILER2 */
1318
1319 // Compute the rbp, offset for any slots used after the jni call
1320
1321 int lock_slot_rbp_offset = (lock_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment;
1322 int oop_temp_slot_rbp_offset = (oop_temp_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment;
1323
1324 // We use rdi as a thread pointer because it is callee save and
1325 // if we load it once it is usable thru the entire wrapper
1326 const Register thread = rdi;
1327
1328 // We use rsi as the oop handle for the receiver/klass
1329 // It is callee save so it survives the call to native
1330
1331 const Register oop_handle_reg = rsi;
1332
1333 __ get_thread(thread);
1334
1335
1336 //
1337 // We immediately shuffle the arguments so that any vm call we have to
1338 // make from here on out (sync slow path, jvmti, etc.) we will have
1339 // captured the oops from our caller and have a valid oopMap for
1340 // them.
1341
1342 // -----------------
1343 // The Grand Shuffle
1344 //
1345 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
1346 // and, if static, the class mirror instead of a receiver. This pretty much
1347 // guarantees that register layout will not match (and x86 doesn't use reg
1348 // parms though amd does). Since the native abi doesn't use register args
1349 // and the java conventions does we don't have to worry about collisions.
1350 // All of our moved are reg->stack or stack->stack.
1351 // We ignore the extra arguments during the shuffle and handle them at the
1352 // last moment. The shuffle is described by the two calling convention
1353 // vectors we have in our possession. We simply walk the java vector to
1354 // get the source locations and the c vector to get the destinations.
1355
1356 int c_arg = method->is_static() ? 2 : 1 ;
1357
1358 // Record rsp-based slot for receiver on stack for non-static methods
1359 int receiver_offset = -1;
1360
1361 // This is a trick. We double the stack slots so we can claim
1362 // the oops in the caller's frame. Since we are sure to have
1363 // more args than the caller doubling is enough to make
1364 // sure we can capture all the incoming oop args from the
1365 // caller.
1366 //
1367 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1368
1369 // Mark location of rbp,
1370 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
1371
1372 // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
1373 // Are free to temporaries if we have to do stack to steck moves.
1374 // All inbound args are referenced based on rbp, and all outbound args via rsp.
1375
1376 for (i = 0; i < total_in_args ; i++, c_arg++ ) {
1377 switch (in_sig_bt[i]) {
1378 case T_ARRAY:
1379 case T_OBJECT:
1380 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1381 ((i == 0) && (!is_static)),
1382 &receiver_offset);
1383 break;
1384 case T_VOID:
1385 break;
1386
1387 case T_FLOAT:
1388 float_move(masm, in_regs[i], out_regs[c_arg]);
1389 break;
1390
1391 case T_DOUBLE:
1392 assert( i + 1 < total_in_args &&
1393 in_sig_bt[i + 1] == T_VOID &&
1394 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1395 double_move(masm, in_regs[i], out_regs[c_arg]);
1396 break;
1397
1398 case T_LONG :
1399 long_move(masm, in_regs[i], out_regs[c_arg]);
1400 break;
1401
1402 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
1403
1404 default:
1405 simple_move32(masm, in_regs[i], out_regs[c_arg]);
1406 }
1407 }
1408
1409 // Pre-load a static method's oop into rsi. Used both by locking code and
1410 // the normal JNI call code.
1411 if (method->is_static()) {
1412
1413 // load opp into a register
1414 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
1415
1416 // Now handlize the static class mirror it's known not-null.
1417 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
1418 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
1419
1420 // Now get the handle
1421 __ lea(oop_handle_reg, Address(rsp, klass_offset));
1422 // store the klass handle as second argument
1423 __ movptr(Address(rsp, wordSize), oop_handle_reg);
1424 }
1425
1426 // Change state to native (we save the return address in the thread, since it might not
1427 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
1428 // points into the right code segment. It does not have to be the correct return pc.
1429 // We use the same pc/oopMap repeatedly when we call out
1430
1431 intptr_t the_pc = (intptr_t) __ pc();
1432 oop_maps->add_gc_map(the_pc - start, map);
1433
1434 __ set_last_Java_frame(thread, rsp, noreg, (address)the_pc);
1435
1436
1437 // We have all of the arguments setup at this point. We must not touch any register
1438 // argument registers at this point (what if we save/restore them there are no oop?
1439
1440 {
1441 SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
1442 __ movoop(rax, JNIHandles::make_local(method()));
1443 __ call_VM_leaf(
1444 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
1445 thread, rax);
1446 }
1447
1448 // RedefineClasses() tracing support for obsolete method entry
1449 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
1450 __ movoop(rax, JNIHandles::make_local(method()));
1451 __ call_VM_leaf(
1452 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
1453 thread, rax);
1454 }
1455
1456 // These are register definitions we need for locking/unlocking
1457 const Register swap_reg = rax; // Must use rax, for cmpxchg instruction
1458 const Register obj_reg = rcx; // Will contain the oop
1459 const Register lock_reg = rdx; // Address of compiler lock object (BasicLock)
1460
1461 Label slow_path_lock;
1462 Label lock_done;
1463
1464 // Lock a synchronized method
1465 if (method->is_synchronized()) {
1466
1467
1468 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
1469
1470 // Get the handle (the 2nd argument)
1471 __ movptr(oop_handle_reg, Address(rsp, wordSize));
1472
1473 // Get address of the box
1474
1475 __ lea(lock_reg, Address(rbp, lock_slot_rbp_offset));
1476
1477 // Load the oop from the handle
1478 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1479
1480 if (UseBiasedLocking) {
1481 // Note that oop_handle_reg is trashed during this call
1482 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, oop_handle_reg, false, lock_done, &slow_path_lock);
1483 }
1484
1485 // Load immediate 1 into swap_reg %rax,
1486 __ movptr(swap_reg, 1);
1487
1488 // Load (object->mark() | 1) into swap_reg %rax,
1489 __ orptr(swap_reg, Address(obj_reg, 0));
1490
1491 // Save (object->mark() | 1) into BasicLock's displaced header
1492 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1493
1494 if (os::is_MP()) {
1495 __ lock();
1496 }
1497
1498 // src -> dest iff dest == rax, else rax, <- dest
1499 // *obj_reg = lock_reg iff *obj_reg == rax, else rax, = *(obj_reg)
1500 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
1501 __ jcc(Assembler::equal, lock_done);
1502
1503 // Test if the oopMark is an obvious stack pointer, i.e.,
1504 // 1) (mark & 3) == 0, and
1505 // 2) rsp <= mark < mark + os::pagesize()
1506 // These 3 tests can be done by evaluating the following
1507 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
1508 // assuming both stack pointer and pagesize have their
1509 // least significant 2 bits clear.
1510 // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
1511
1512 __ subptr(swap_reg, rsp);
1513 __ andptr(swap_reg, 3 - os::vm_page_size());
1514
1515 // Save the test result, for recursive case, the result is zero
1516 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1517 __ jcc(Assembler::notEqual, slow_path_lock);
1518 // Slow path will re-enter here
1519 __ bind(lock_done);
1520
1521 if (UseBiasedLocking) {
1522 // Re-fetch oop_handle_reg as we trashed it above
1523 __ movptr(oop_handle_reg, Address(rsp, wordSize));
1524 }
1525 }
1526
1527
1528 // Finally just about ready to make the JNI call
1529
1530
1531 // get JNIEnv* which is first argument to native
1532
1533 __ lea(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
1534 __ movptr(Address(rsp, 0), rdx);
1535
1536 // Now set thread in native
1537 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native);
1538
1539 __ call(RuntimeAddress(method->native_function()));
1540
1541 // WARNING - on Windows Java Natives use pascal calling convention and pop the
1542 // arguments off of the stack. We could just re-adjust the stack pointer here
1543 // and continue to do SP relative addressing but we instead switch to FP
1544 // relative addressing.
1545
1546 // Unpack native results.
1547 switch (ret_type) {
1548 case T_BOOLEAN: __ c2bool(rax); break;
1549 case T_CHAR : __ andptr(rax, 0xFFFF); break;
1550 case T_BYTE : __ sign_extend_byte (rax); break;
1551 case T_SHORT : __ sign_extend_short(rax); break;
1552 case T_INT : /* nothing to do */ break;
1553 case T_DOUBLE :
1554 case T_FLOAT :
1555 // Result is in st0 we'll save as needed
1556 break;
1557 case T_ARRAY: // Really a handle
1558 case T_OBJECT: // Really a handle
1559 break; // can't de-handlize until after safepoint check
1560 case T_VOID: break;
1561 case T_LONG: break;
1562 default : ShouldNotReachHere();
1563 }
1564
1565 // Switch thread to "native transition" state before reading the synchronization state.
1566 // This additional state is necessary because reading and testing the synchronization
1567 // state is not atomic w.r.t. GC, as this scenario demonstrates:
1568 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
1569 // VM thread changes sync state to synchronizing and suspends threads for GC.
1570 // Thread A is resumed to finish this native method, but doesn't block here since it
1571 // didn't see any synchronization is progress, and escapes.
1572 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
1573
1574 if(os::is_MP()) {
1575 if (UseMembar) {
1576 // Force this write out before the read below
1577 __ membar(Assembler::Membar_mask_bits(
1578 Assembler::LoadLoad | Assembler::LoadStore |
1579 Assembler::StoreLoad | Assembler::StoreStore));
1580 } else {
1581 // Write serialization page so VM thread can do a pseudo remote membar.
1582 // We use the current thread pointer to calculate a thread specific
1583 // offset to write to within the page. This minimizes bus traffic
1584 // due to cache line collision.
1585 __ serialize_memory(thread, rcx);
1586 }
1587 }
1588
1589 if (AlwaysRestoreFPU) {
1590 // Make sure the control word is correct.
1591 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1592 }
1593
1594 // check for safepoint operation in progress and/or pending suspend requests
1595 { Label Continue;
1596
1597 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
1598 SafepointSynchronize::_not_synchronized);
1599
1600 Label L;
1601 __ jcc(Assembler::notEqual, L);
1602 __ cmpl(Address(thread, JavaThread::suspend_flags_offset()), 0);
1603 __ jcc(Assembler::equal, Continue);
1604 __ bind(L);
1605
1606 // Don't use call_VM as it will see a possible pending exception and forward it
1607 // and never return here preventing us from clearing _last_native_pc down below.
1608 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
1609 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
1610 // by hand.
1611 //
1612 save_native_result(masm, ret_type, stack_slots);
1613 __ push(thread);
1614 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
1615 JavaThread::check_special_condition_for_native_trans)));
1616 __ increment(rsp, wordSize);
1617 // Restore any method result value
1618 restore_native_result(masm, ret_type, stack_slots);
1619
1620 __ bind(Continue);
1621 }
1622
1623 // change thread state
1624 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_Java);
1625
1626 Label reguard;
1627 Label reguard_done;
1628 __ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
1629 __ jcc(Assembler::equal, reguard);
1630
1631 // slow path reguard re-enters here
1632 __ bind(reguard_done);
1633
1634 // Handle possible exception (will unlock if necessary)
1635
1636 // native result if any is live
1637
1638 // Unlock
1639 Label slow_path_unlock;
1640 Label unlock_done;
1641 if (method->is_synchronized()) {
1642
1643 Label done;
1644
1645 // Get locked oop from the handle we passed to jni
1646 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1647
1648 if (UseBiasedLocking) {
1649 __ biased_locking_exit(obj_reg, rbx, done);
1650 }
1651
1652 // Simple recursive lock?
1653
1654 __ cmpptr(Address(rbp, lock_slot_rbp_offset), (int32_t)NULL_WORD);
1655 __ jcc(Assembler::equal, done);
1656
1657 // Must save rax, if if it is live now because cmpxchg must use it
1658 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1659 save_native_result(masm, ret_type, stack_slots);
1660 }
1661
1662 // get old displaced header
1663 __ movptr(rbx, Address(rbp, lock_slot_rbp_offset));
1664
1665 // get address of the stack lock
1666 __ lea(rax, Address(rbp, lock_slot_rbp_offset));
1667
1668 // Atomic swap old header if oop still contains the stack lock
1669 if (os::is_MP()) {
1670 __ lock();
1671 }
1672
1673 // src -> dest iff dest == rax, else rax, <- dest
1674 // *obj_reg = rbx, iff *obj_reg == rax, else rax, = *(obj_reg)
1675 __ cmpxchgptr(rbx, Address(obj_reg, 0));
1676 __ jcc(Assembler::notEqual, slow_path_unlock);
1677
1678 // slow path re-enters here
1679 __ bind(unlock_done);
1680 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1681 restore_native_result(masm, ret_type, stack_slots);
1682 }
1683
1684 __ bind(done);
1685
1686 }
1687
1688 {
1689 SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
1690 // Tell dtrace about this method exit
1691 save_native_result(masm, ret_type, stack_slots);
1692 __ movoop(rax, JNIHandles::make_local(method()));
1693 __ call_VM_leaf(
1694 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
1695 thread, rax);
1696 restore_native_result(masm, ret_type, stack_slots);
1697 }
1698
1699 // We can finally stop using that last_Java_frame we setup ages ago
1700
1701 __ reset_last_Java_frame(thread, false, true);
1702
1703 // Unpack oop result
1704 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
1705 Label L;
1706 __ cmpptr(rax, (int32_t)NULL_WORD);
1707 __ jcc(Assembler::equal, L);
1708 __ movptr(rax, Address(rax, 0));
1709 __ bind(L);
1710 __ verify_oop(rax);
1711 }
1712
1713 // reset handle block
1714 __ movptr(rcx, Address(thread, JavaThread::active_handles_offset()));
1715
1716 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
1717
1718 // Any exception pending?
1719 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1720 __ jcc(Assembler::notEqual, exception_pending);
1721
1722
1723 // no exception, we're almost done
1724
1725 // check that only result value is on FPU stack
1726 __ verify_FPU(ret_type == T_FLOAT || ret_type == T_DOUBLE ? 1 : 0, "native_wrapper normal exit");
1727
1728 // Fixup floating pointer results so that result looks like a return from a compiled method
1729 if (ret_type == T_FLOAT) {
1730 if (UseSSE >= 1) {
1731 // Pop st0 and store as float and reload into xmm register
1732 __ fstp_s(Address(rbp, -4));
1733 __ movflt(xmm0, Address(rbp, -4));
1734 }
1735 } else if (ret_type == T_DOUBLE) {
1736 if (UseSSE >= 2) {
1737 // Pop st0 and store as double and reload into xmm register
1738 __ fstp_d(Address(rbp, -8));
1739 __ movdbl(xmm0, Address(rbp, -8));
1740 }
1741 }
1742
1743 // Return
1744
1745 __ leave();
1746 __ ret(0);
1747
1748 // Unexpected paths are out of line and go here
1749
1750 // Slow path locking & unlocking
1751 if (method->is_synchronized()) {
1752
1753 // BEGIN Slow path lock
1754
1755 __ bind(slow_path_lock);
1756
1757 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
1758 // args are (oop obj, BasicLock* lock, JavaThread* thread)
1759 __ push(thread);
1760 __ push(lock_reg);
1761 __ push(obj_reg);
1762 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C)));
1763 __ addptr(rsp, 3*wordSize);
1764
1765 #ifdef ASSERT
1766 { Label L;
1767 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
1768 __ jcc(Assembler::equal, L);
1769 __ stop("no pending exception allowed on exit from monitorenter");
1770 __ bind(L);
1771 }
1772 #endif
1773 __ jmp(lock_done);
1774
1775 // END Slow path lock
1776
1777 // BEGIN Slow path unlock
1778 __ bind(slow_path_unlock);
1779
1780 // Slow path unlock
1781
1782 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1783 save_native_result(masm, ret_type, stack_slots);
1784 }
1785 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
1786
1787 __ pushptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
1788 __ movptr(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
1789
1790
1791 // should be a peal
1792 // +wordSize because of the push above
1793 __ lea(rax, Address(rbp, lock_slot_rbp_offset));
1794 __ push(rax);
1795
1796 __ push(obj_reg);
1797 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
1798 __ addptr(rsp, 2*wordSize);
1799 #ifdef ASSERT
1800 {
1801 Label L;
1802 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1803 __ jcc(Assembler::equal, L);
1804 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
1805 __ bind(L);
1806 }
1807 #endif /* ASSERT */
1808
1809 __ popptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
1810
1811 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1812 restore_native_result(masm, ret_type, stack_slots);
1813 }
1814 __ jmp(unlock_done);
1815 // END Slow path unlock
1816
1817 }
1818
1819 // SLOW PATH Reguard the stack if needed
1820
1821 __ bind(reguard);
1822 save_native_result(masm, ret_type, stack_slots);
1823 {
1824 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
1825 }
1826 restore_native_result(masm, ret_type, stack_slots);
1827 __ jmp(reguard_done);
1828
1829
1830 // BEGIN EXCEPTION PROCESSING
1831
1832 // Forward the exception
1833 __ bind(exception_pending);
1834
1835 // remove possible return value from FPU register stack
1836 __ empty_FPU_stack();
1837
1838 // pop our frame
1839 __ leave();
1840 // and forward the exception
1841 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1842
1843 __ flush();
1844
1845 nmethod *nm = nmethod::new_native_nmethod(method,
1846 compile_id,
1847 masm->code(),
1848 vep_offset,
1849 frame_complete,
1850 stack_slots / VMRegImpl::slots_per_word,
1851 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
1852 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
1853 oop_maps);
1854 return nm;
1855
1856 }
1857
1858 #ifdef HAVE_DTRACE_H
1859 // ---------------------------------------------------------------------------
1860 // Generate a dtrace nmethod for a given signature. The method takes arguments
1861 // in the Java compiled code convention, marshals them to the native
1862 // abi and then leaves nops at the position you would expect to call a native
1863 // function. When the probe is enabled the nops are replaced with a trap
1864 // instruction that dtrace inserts and the trace will cause a notification
1865 // to dtrace.
1866 //
1867 // The probes are only able to take primitive types and java/lang/String as
1868 // arguments. No other java types are allowed. Strings are converted to utf8
1869 // strings so that from dtrace point of view java strings are converted to C
1870 // strings. There is an arbitrary fixed limit on the total space that a method
1871 // can use for converting the strings. (256 chars per string in the signature).
1872 // So any java string larger then this is truncated.
1873
1874 nmethod *SharedRuntime::generate_dtrace_nmethod(
1875 MacroAssembler *masm, methodHandle method) {
1876
1877 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
1878 // be single threaded in this method.
1879 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
1880
1881 // Fill in the signature array, for the calling-convention call.
1882 int total_args_passed = method->size_of_parameters();
1883
1884 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
1885 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
1886
1887 // The signature we are going to use for the trap that dtrace will see
1888 // java/lang/String is converted. We drop "this" and any other object
1889 // is converted to NULL. (A one-slot java/lang/Long object reference
1890 // is converted to a two-slot long, which is why we double the allocation).
1891 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
1892 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
1893
1894 int i=0;
1895 int total_strings = 0;
1896 int first_arg_to_pass = 0;
1897 int total_c_args = 0;
1898
1899 if( !method->is_static() ) { // Pass in receiver first
1900 in_sig_bt[i++] = T_OBJECT;
1901 first_arg_to_pass = 1;
1902 }
1903
1904 // We need to convert the java args to where a native (non-jni) function
1905 // would expect them. To figure out where they go we convert the java
1906 // signature to a C signature.
1907
1908 SignatureStream ss(method->signature());
1909 for ( ; !ss.at_return_type(); ss.next()) {
1910 BasicType bt = ss.type();
1911 in_sig_bt[i++] = bt; // Collect remaining bits of signature
1912 out_sig_bt[total_c_args++] = bt;
1913 if( bt == T_OBJECT) {
1914 Symbol* s = ss.as_symbol_or_null(); // symbol is created
1915 if (s == vmSymbols::java_lang_String()) {
1916 total_strings++;
1917 out_sig_bt[total_c_args-1] = T_ADDRESS;
1918 } else if (s == vmSymbols::java_lang_Boolean() ||
1919 s == vmSymbols::java_lang_Character() ||
1920 s == vmSymbols::java_lang_Byte() ||
1921 s == vmSymbols::java_lang_Short() ||
1922 s == vmSymbols::java_lang_Integer() ||
1923 s == vmSymbols::java_lang_Float()) {
1924 out_sig_bt[total_c_args-1] = T_INT;
1925 } else if (s == vmSymbols::java_lang_Long() ||
1926 s == vmSymbols::java_lang_Double()) {
1927 out_sig_bt[total_c_args-1] = T_LONG;
1928 out_sig_bt[total_c_args++] = T_VOID;
1929 }
1930 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
1931 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
1932 out_sig_bt[total_c_args++] = T_VOID;
1933 }
1934 }
1935
1936 assert(i==total_args_passed, "validly parsed signature");
1937
1938 // Now get the compiled-Java layout as input arguments
1939 int comp_args_on_stack;
1940 comp_args_on_stack = SharedRuntime::java_calling_convention(
1941 in_sig_bt, in_regs, total_args_passed, false);
1942
1943 // Now figure out where the args must be stored and how much stack space
1944 // they require (neglecting out_preserve_stack_slots).
1945
1946 int out_arg_slots;
1947 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1948
1949 // Calculate the total number of stack slots we will need.
1950
1951 // First count the abi requirement plus all of the outgoing args
1952 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1953
1954 // Now space for the string(s) we must convert
1955
1956 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
1957 for (i = 0; i < total_strings ; i++) {
1958 string_locs[i] = stack_slots;
1959 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
1960 }
1961
1962 // + 2 for return address (which we own) and saved rbp,
1963
1964 stack_slots += 2;
1965
1966 // Ok The space we have allocated will look like:
1967 //
1968 //
1969 // FP-> | |
1970 // |---------------------|
1971 // | string[n] |
1972 // |---------------------| <- string_locs[n]
1973 // | string[n-1] |
1974 // |---------------------| <- string_locs[n-1]
1975 // | ... |
1976 // | ... |
1977 // |---------------------| <- string_locs[1]
1978 // | string[0] |
1979 // |---------------------| <- string_locs[0]
1980 // | outbound memory |
1981 // | based arguments |
1982 // | |
1983 // |---------------------|
1984 // | |
1985 // SP-> | out_preserved_slots |
1986 //
1987 //
1988
1989 // Now compute actual number of stack words we need rounding to make
1990 // stack properly aligned.
1991 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
1992
1993 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1994
1995 intptr_t start = (intptr_t)__ pc();
1996
1997 // First thing make an ic check to see if we should even be here
1998
1999 // We are free to use all registers as temps without saving them and
2000 // restoring them except rbp. rbp, is the only callee save register
2001 // as far as the interpreter and the compiler(s) are concerned.
2002
2003 const Register ic_reg = rax;
2004 const Register receiver = rcx;
2005 Label hit;
2006 Label exception_pending;
2007
2008
2009 __ verify_oop(receiver);
2010 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2011 __ jcc(Assembler::equal, hit);
2012
2013 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2014
2015 // verified entry must be aligned for code patching.
2016 // and the first 5 bytes must be in the same cache line
2017 // if we align at 8 then we will be sure 5 bytes are in the same line
2018 __ align(8);
2019
2020 __ bind(hit);
2021
2022 int vep_offset = ((intptr_t)__ pc()) - start;
2023
2024
2025 // The instruction at the verified entry point must be 5 bytes or longer
2026 // because it can be patched on the fly by make_non_entrant. The stack bang
2027 // instruction fits that requirement.
2028
2029 // Generate stack overflow check
2030
2031
2032 if (UseStackBanging) {
2033 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2034 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2035 } else {
2036 __ movl(rax, stack_size);
2037 __ bang_stack_size(rax, rbx);
2038 }
2039 } else {
2040 // need a 5 byte instruction to allow MT safe patching to non-entrant
2041 __ fat_nop();
2042 }
2043
2044 assert(((int)__ pc() - start - vep_offset) >= 5,
2045 "valid size for make_non_entrant");
2046
2047 // Generate a new frame for the wrapper.
2048 __ enter();
2049
2050 // -2 because return address is already present and so is saved rbp,
2051 if (stack_size - 2*wordSize != 0) {
2052 __ subl(rsp, stack_size - 2*wordSize);
2053 }
2054
2055 // Frame is now completed as far a size and linkage.
2056
2057 int frame_complete = ((intptr_t)__ pc()) - start;
2058
2059 // First thing we do store all the args as if we are doing the call.
2060 // Since the C calling convention is stack based that ensures that
2061 // all the Java register args are stored before we need to convert any
2062 // string we might have.
2063
2064 int sid = 0;
2065 int c_arg, j_arg;
2066 int string_reg = 0;
2067
2068 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2069 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2070
2071 VMRegPair src = in_regs[j_arg];
2072 VMRegPair dst = out_regs[c_arg];
2073 assert(dst.first()->is_stack() || in_sig_bt[j_arg] == T_VOID,
2074 "stack based abi assumed");
2075
2076 switch (in_sig_bt[j_arg]) {
2077
2078 case T_ARRAY:
2079 case T_OBJECT:
2080 if (out_sig_bt[c_arg] == T_ADDRESS) {
2081 // Any register based arg for a java string after the first
2082 // will be destroyed by the call to get_utf so we store
2083 // the original value in the location the utf string address
2084 // will eventually be stored.
2085 if (src.first()->is_reg()) {
2086 if (string_reg++ != 0) {
2087 simple_move32(masm, src, dst);
2088 }
2089 }
2090 } else if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2091 // need to unbox a one-word value
2092 Register in_reg = rax;
2093 if ( src.first()->is_reg() ) {
2094 in_reg = src.first()->as_Register();
2095 } else {
2096 simple_move32(masm, src, in_reg->as_VMReg());
2097 }
2098 Label skipUnbox;
2099 __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
2100 if ( out_sig_bt[c_arg] == T_LONG ) {
2101 __ movl(Address(rsp, reg2offset_out(dst.second())), NULL_WORD);
2102 }
2103 __ testl(in_reg, in_reg);
2104 __ jcc(Assembler::zero, skipUnbox);
2105 assert(dst.first()->is_stack() &&
2106 (!dst.second()->is_valid() || dst.second()->is_stack()),
2107 "value(s) must go into stack slots");
2108
2109 BasicType bt = out_sig_bt[c_arg];
2110 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2111 if ( bt == T_LONG ) {
2112 __ movl(rbx, Address(in_reg,
2113 box_offset + VMRegImpl::stack_slot_size));
2114 __ movl(Address(rsp, reg2offset_out(dst.second())), rbx);
2115 }
2116 __ movl(in_reg, Address(in_reg, box_offset));
2117 __ movl(Address(rsp, reg2offset_out(dst.first())), in_reg);
2118 __ bind(skipUnbox);
2119 } else {
2120 // Convert the arg to NULL
2121 __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
2122 }
2123 if (out_sig_bt[c_arg] == T_LONG) {
2124 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2125 ++c_arg; // Move over the T_VOID To keep the loop indices in sync
2126 }
2127 break;
2128
2129 case T_VOID:
2130 break;
2131
2132 case T_FLOAT:
2133 float_move(masm, src, dst);
2134 break;
2135
2136 case T_DOUBLE:
2137 assert( j_arg + 1 < total_args_passed &&
2138 in_sig_bt[j_arg + 1] == T_VOID, "bad arg list");
2139 double_move(masm, src, dst);
2140 break;
2141
2142 case T_LONG :
2143 long_move(masm, src, dst);
2144 break;
2145
2146 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2147
2148 default:
2149 simple_move32(masm, src, dst);
2150 }
2151 }
2152
2153 // Now we must convert any string we have to utf8
2154 //
2155
2156 for (sid = 0, j_arg = first_arg_to_pass, c_arg = 0 ;
2157 sid < total_strings ; j_arg++, c_arg++ ) {
2158
2159 if (out_sig_bt[c_arg] == T_ADDRESS) {
2160
2161 Address utf8_addr = Address(
2162 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2163 __ leal(rax, utf8_addr);
2164
2165 // The first string we find might still be in the original java arg
2166 // register
2167 VMReg orig_loc = in_regs[j_arg].first();
2168 Register string_oop;
2169
2170 // This is where the argument will eventually reside
2171 Address dest = Address(rsp, reg2offset_out(out_regs[c_arg].first()));
2172
2173 if (sid == 1 && orig_loc->is_reg()) {
2174 string_oop = orig_loc->as_Register();
2175 assert(string_oop != rax, "smashed arg");
2176 } else {
2177
2178 if (orig_loc->is_reg()) {
2179 // Get the copy of the jls object
2180 __ movl(rcx, dest);
2181 } else {
2182 // arg is still in the original location
2183 __ movl(rcx, Address(rbp, reg2offset_in(orig_loc)));
2184 }
2185 string_oop = rcx;
2186
2187 }
2188 Label nullString;
2189 __ movl(dest, NULL_WORD);
2190 __ testl(string_oop, string_oop);
2191 __ jcc(Assembler::zero, nullString);
2192
2193 // Now we can store the address of the utf string as the argument
2194 __ movl(dest, rax);
2195
2196 // And do the conversion
2197 __ call_VM_leaf(CAST_FROM_FN_PTR(
2198 address, SharedRuntime::get_utf), string_oop, rax);
2199 __ bind(nullString);
2200 }
2201
2202 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2203 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2204 ++c_arg; // Move over the T_VOID To keep the loop indices in sync
2205 }
2206 }
2207
2208
2209 // Ok now we are done. Need to place the nop that dtrace wants in order to
2210 // patch in the trap
2211
2212 int patch_offset = ((intptr_t)__ pc()) - start;
2213
2214 __ nop();
2215
2216
2217 // Return
2218
2219 __ leave();
2220 __ ret(0);
2221
2222 __ flush();
2223
2224 nmethod *nm = nmethod::new_dtrace_nmethod(
2225 method, masm->code(), vep_offset, patch_offset, frame_complete,
2226 stack_slots / VMRegImpl::slots_per_word);
2227 return nm;
2228
2229 }
2230
2231 #endif // HAVE_DTRACE_H
2232
2233 // this function returns the adjust size (in number of words) to a c2i adapter
2234 // activation for use during deoptimization
2235 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2236 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
2237 }
2238
2239
2240 uint SharedRuntime::out_preserve_stack_slots() {
2241 return 0;
2242 }
2243
2244
2245 //------------------------------generate_deopt_blob----------------------------
2246 void SharedRuntime::generate_deopt_blob() {
2247 // allocate space for the code
2248 ResourceMark rm;
2249 // setup code generation tools
2250 CodeBuffer buffer("deopt_blob", 1024, 1024);
2251 MacroAssembler* masm = new MacroAssembler(&buffer);
2252 int frame_size_in_words;
2253 OopMap* map = NULL;
2254 // Account for the extra args we place on the stack
2255 // by the time we call fetch_unroll_info
2256 const int additional_words = 2; // deopt kind, thread
2257
2258 OopMapSet *oop_maps = new OopMapSet();
2259
2260 // -------------
2261 // This code enters when returning to a de-optimized nmethod. A return
2262 // address has been pushed on the the stack, and return values are in
2263 // registers.
2264 // If we are doing a normal deopt then we were called from the patched
2265 // nmethod from the point we returned to the nmethod. So the return
2266 // address on the stack is wrong by NativeCall::instruction_size
2267 // We will adjust the value to it looks like we have the original return
2268 // address on the stack (like when we eagerly deoptimized).
2269 // In the case of an exception pending with deoptimized then we enter
2270 // with a return address on the stack that points after the call we patched
2271 // into the exception handler. We have the following register state:
2272 // rax,: exception
2273 // rbx,: exception handler
2274 // rdx: throwing pc
2275 // So in this case we simply jam rdx into the useless return address and
2276 // the stack looks just like we want.
2277 //
2278 // At this point we need to de-opt. We save the argument return
2279 // registers. We call the first C routine, fetch_unroll_info(). This
2280 // routine captures the return values and returns a structure which
2281 // describes the current frame size and the sizes of all replacement frames.
2282 // The current frame is compiled code and may contain many inlined
2283 // functions, each with their own JVM state. We pop the current frame, then
2284 // push all the new frames. Then we call the C routine unpack_frames() to
2285 // populate these frames. Finally unpack_frames() returns us the new target
2286 // address. Notice that callee-save registers are BLOWN here; they have
2287 // already been captured in the vframeArray at the time the return PC was
2288 // patched.
2289 address start = __ pc();
2290 Label cont;
2291
2292 // Prolog for non exception case!
2293
2294 // Save everything in sight.
2295
2296 map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
2297 // Normal deoptimization
2298 __ push(Deoptimization::Unpack_deopt);
2299 __ jmp(cont);
2300
2301 int reexecute_offset = __ pc() - start;
2302
2303 // Reexecute case
2304 // return address is the pc describes what bci to do re-execute at
2305
2306 // No need to update map as each call to save_live_registers will produce identical oopmap
2307 (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
2308
2309 __ push(Deoptimization::Unpack_reexecute);
2310 __ jmp(cont);
2311
2312 int exception_offset = __ pc() - start;
2313
2314 // Prolog for exception case
2315
2316 // all registers are dead at this entry point, except for rax, and
2317 // rdx which contain the exception oop and exception pc
2318 // respectively. Set them in TLS and fall thru to the
2319 // unpack_with_exception_in_tls entry point.
2320
2321 __ get_thread(rdi);
2322 __ movptr(Address(rdi, JavaThread::exception_pc_offset()), rdx);
2323 __ movptr(Address(rdi, JavaThread::exception_oop_offset()), rax);
2324
2325 int exception_in_tls_offset = __ pc() - start;
2326
2327 // new implementation because exception oop is now passed in JavaThread
2328
2329 // Prolog for exception case
2330 // All registers must be preserved because they might be used by LinearScan
2331 // Exceptiop oop and throwing PC are passed in JavaThread
2332 // tos: stack at point of call to method that threw the exception (i.e. only
2333 // args are on the stack, no return address)
2334
2335 // make room on stack for the return address
2336 // It will be patched later with the throwing pc. The correct value is not
2337 // available now because loading it from memory would destroy registers.
2338 __ push(0);
2339
2340 // Save everything in sight.
2341
2342 // No need to update map as each call to save_live_registers will produce identical oopmap
2343 (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
2344
2345 // Now it is safe to overwrite any register
2346
2347 // store the correct deoptimization type
2348 __ push(Deoptimization::Unpack_exception);
2349
2350 // load throwing pc from JavaThread and patch it as the return address
2351 // of the current frame. Then clear the field in JavaThread
2352 __ get_thread(rdi);
2353 __ movptr(rdx, Address(rdi, JavaThread::exception_pc_offset()));
2354 __ movptr(Address(rbp, wordSize), rdx);
2355 __ movptr(Address(rdi, JavaThread::exception_pc_offset()), NULL_WORD);
2356
2357 #ifdef ASSERT
2358 // verify that there is really an exception oop in JavaThread
2359 __ movptr(rax, Address(rdi, JavaThread::exception_oop_offset()));
2360 __ verify_oop(rax);
2361
2362 // verify that there is no pending exception
2363 Label no_pending_exception;
2364 __ movptr(rax, Address(rdi, Thread::pending_exception_offset()));
2365 __ testptr(rax, rax);
2366 __ jcc(Assembler::zero, no_pending_exception);
2367 __ stop("must not have pending exception here");
2368 __ bind(no_pending_exception);
2369 #endif
2370
2371 __ bind(cont);
2372
2373 // Compiled code leaves the floating point stack dirty, empty it.
2374 __ empty_FPU_stack();
2375
2376
2377 // Call C code. Need thread and this frame, but NOT official VM entry
2378 // crud. We cannot block on this call, no GC can happen.
2379 __ get_thread(rcx);
2380 __ push(rcx);
2381 // fetch_unroll_info needs to call last_java_frame()
2382 __ set_last_Java_frame(rcx, noreg, noreg, NULL);
2383
2384 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
2385
2386 // Need to have an oopmap that tells fetch_unroll_info where to
2387 // find any register it might need.
2388
2389 oop_maps->add_gc_map( __ pc()-start, map);
2390
2391 // Discard arg to fetch_unroll_info
2392 __ pop(rcx);
2393
2394 __ get_thread(rcx);
2395 __ reset_last_Java_frame(rcx, false, false);
2396
2397 // Load UnrollBlock into EDI
2398 __ mov(rdi, rax);
2399
2400 // Move the unpack kind to a safe place in the UnrollBlock because
2401 // we are very short of registers
2402
2403 Address unpack_kind(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes());
2404 // retrieve the deopt kind from where we left it.
2405 __ pop(rax);
2406 __ movl(unpack_kind, rax); // save the unpack_kind value
2407
2408 Label noException;
2409 __ cmpl(rax, Deoptimization::Unpack_exception); // Was exception pending?
2410 __ jcc(Assembler::notEqual, noException);
2411 __ movptr(rax, Address(rcx, JavaThread::exception_oop_offset()));
2412 __ movptr(rdx, Address(rcx, JavaThread::exception_pc_offset()));
2413 __ movptr(Address(rcx, JavaThread::exception_oop_offset()), NULL_WORD);
2414 __ movptr(Address(rcx, JavaThread::exception_pc_offset()), NULL_WORD);
2415
2416 __ verify_oop(rax);
2417
2418 // Overwrite the result registers with the exception results.
2419 __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
2420 __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
2421
2422 __ bind(noException);
2423
2424 // Stack is back to only having register save data on the stack.
2425 // Now restore the result registers. Everything else is either dead or captured
2426 // in the vframeArray.
2427
2428 RegisterSaver::restore_result_registers(masm);
2429
2430 // Non standard control word may be leaked out through a safepoint blob, and we can
2431 // deopt at a poll point with the non standard control word. However, we should make
2432 // sure the control word is correct after restore_result_registers.
2433 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
2434
2435 // All of the register save area has been popped of the stack. Only the
2436 // return address remains.
2437
2438 // Pop all the frames we must move/replace.
2439 //
2440 // Frame picture (youngest to oldest)
2441 // 1: self-frame (no frame link)
2442 // 2: deopting frame (no frame link)
2443 // 3: caller of deopting frame (could be compiled/interpreted).
2444 //
2445 // Note: by leaving the return address of self-frame on the stack
2446 // and using the size of frame 2 to adjust the stack
2447 // when we are done the return to frame 3 will still be on the stack.
2448
2449 // Pop deoptimized frame
2450 __ addptr(rsp, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
2451
2452 // sp should be pointing at the return address to the caller (3)
2453
2454 // Stack bang to make sure there's enough room for these interpreter frames.
2455 if (UseStackBanging) {
2456 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2457 __ bang_stack_size(rbx, rcx);
2458 }
2459
2460 // Load array of frame pcs into ECX
2461 __ movptr(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2462
2463 __ pop(rsi); // trash the old pc
2464
2465 // Load array of frame sizes into ESI
2466 __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
2467
2468 Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
2469
2470 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
2471 __ movl(counter, rbx);
2472
2473 // Pick up the initial fp we should save
2474 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2475
2476 // Now adjust the caller's stack to make up for the extra locals
2477 // but record the original sp so that we can save it in the skeletal interpreter
2478 // frame and the stack walking of interpreter_sender will get the unextended sp
2479 // value and not the "real" sp value.
2480
2481 Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
2482 __ movptr(sp_temp, rsp);
2483 __ movl2ptr(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
2484 __ subptr(rsp, rbx);
2485
2486 // Push interpreter frames in a loop
2487 Label loop;
2488 __ bind(loop);
2489 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2490 #ifdef CC_INTERP
2491 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
2492 #ifdef ASSERT
2493 __ push(0xDEADDEAD); // Make a recognizable pattern
2494 __ push(0xDEADDEAD);
2495 #else /* ASSERT */
2496 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
2497 #endif /* ASSERT */
2498 #else /* CC_INTERP */
2499 __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
2500 #endif /* CC_INTERP */
2501 __ pushptr(Address(rcx, 0)); // save return address
2502 __ enter(); // save old & set new rbp,
2503 __ subptr(rsp, rbx); // Prolog!
2504 __ movptr(rbx, sp_temp); // sender's sp
2505 #ifdef CC_INTERP
2506 __ movptr(Address(rbp,
2507 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2508 rbx); // Make it walkable
2509 #else /* CC_INTERP */
2510 // This value is corrected by layout_activation_impl
2511 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
2512 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
2513 #endif /* CC_INTERP */
2514 __ movptr(sp_temp, rsp); // pass to next frame
2515 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2516 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2517 __ decrementl(counter); // decrement counter
2518 __ jcc(Assembler::notZero, loop);
2519 __ pushptr(Address(rcx, 0)); // save final return address
2520
2521 // Re-push self-frame
2522 __ enter(); // save old & set new rbp,
2523
2524 // Return address and rbp, are in place
2525 // We'll push additional args later. Just allocate a full sized
2526 // register save area
2527 __ subptr(rsp, (frame_size_in_words-additional_words - 2) * wordSize);
2528
2529 // Restore frame locals after moving the frame
2530 __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
2531 __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
2532 __ fstp_d(Address(rsp, RegisterSaver::fpResultOffset()*wordSize)); // Pop float stack and store in local
2533 if( UseSSE>=2 ) __ movdbl(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
2534 if( UseSSE==1 ) __ movflt(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
2535
2536 // Set up the args to unpack_frame
2537
2538 __ pushl(unpack_kind); // get the unpack_kind value
2539 __ get_thread(rcx);
2540 __ push(rcx);
2541
2542 // set last_Java_sp, last_Java_fp
2543 __ set_last_Java_frame(rcx, noreg, rbp, NULL);
2544
2545 // Call C code. Need thread but NOT official VM entry
2546 // crud. We cannot block on this call, no GC can happen. Call should
2547 // restore return values to their stack-slots with the new SP.
2548 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
2549 // Set an oopmap for the call site
2550 oop_maps->add_gc_map( __ pc()-start, new OopMap( frame_size_in_words, 0 ));
2551
2552 // rax, contains the return result type
2553 __ push(rax);
2554
2555 __ get_thread(rcx);
2556 __ reset_last_Java_frame(rcx, false, false);
2557
2558 // Collect return values
2559 __ movptr(rax,Address(rsp, (RegisterSaver::raxOffset() + additional_words + 1)*wordSize));
2560 __ movptr(rdx,Address(rsp, (RegisterSaver::rdxOffset() + additional_words + 1)*wordSize));
2561
2562 // Clear floating point stack before returning to interpreter
2563 __ empty_FPU_stack();
2564
2565 // Check if we should push the float or double return value.
2566 Label results_done, yes_double_value;
2567 __ cmpl(Address(rsp, 0), T_DOUBLE);
2568 __ jcc (Assembler::zero, yes_double_value);
2569 __ cmpl(Address(rsp, 0), T_FLOAT);
2570 __ jcc (Assembler::notZero, results_done);
2571
2572 // return float value as expected by interpreter
2573 if( UseSSE>=1 ) __ movflt(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
2574 else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
2575 __ jmp(results_done);
2576
2577 // return double value as expected by interpreter
2578 __ bind(yes_double_value);
2579 if( UseSSE>=2 ) __ movdbl(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
2580 else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
2581
2582 __ bind(results_done);
2583
2584 // Pop self-frame.
2585 __ leave(); // Epilog!
2586
2587 // Jump to interpreter
2588 __ ret(0);
2589
2590 // -------------
2591 // make sure all code is generated
2592 masm->flush();
2593
2594 _deopt_blob = DeoptimizationBlob::create( &buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
2595 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
2596 }
2597
2598
2599 #ifdef COMPILER2
2600 //------------------------------generate_uncommon_trap_blob--------------------
2601 void SharedRuntime::generate_uncommon_trap_blob() {
2602 // allocate space for the code
2603 ResourceMark rm;
2604 // setup code generation tools
2605 CodeBuffer buffer("uncommon_trap_blob", 512, 512);
2606 MacroAssembler* masm = new MacroAssembler(&buffer);
2607
2608 enum frame_layout {
2609 arg0_off, // thread sp + 0 // Arg location for
2610 arg1_off, // unloaded_class_index sp + 1 // calling C
2611 // The frame sender code expects that rbp will be in the "natural" place and
2612 // will override any oopMap setting for it. We must therefore force the layout
2613 // so that it agrees with the frame sender code.
2614 rbp_off, // callee saved register sp + 2
2615 return_off, // slot for return address sp + 3
2616 framesize
2617 };
2618
2619 address start = __ pc();
2620 // Push self-frame.
2621 __ subptr(rsp, return_off*wordSize); // Epilog!
2622
2623 // rbp, is an implicitly saved callee saved register (i.e. the calling
2624 // convention will save restore it in prolog/epilog) Other than that
2625 // there are no callee save registers no that adapter frames are gone.
2626 __ movptr(Address(rsp, rbp_off*wordSize), rbp);
2627
2628 // Clear the floating point exception stack
2629 __ empty_FPU_stack();
2630
2631 // set last_Java_sp
2632 __ get_thread(rdx);
2633 __ set_last_Java_frame(rdx, noreg, noreg, NULL);
2634
2635 // Call C code. Need thread but NOT official VM entry
2636 // crud. We cannot block on this call, no GC can happen. Call should
2637 // capture callee-saved registers as well as return values.
2638 __ movptr(Address(rsp, arg0_off*wordSize), rdx);
2639 // argument already in ECX
2640 __ movl(Address(rsp, arg1_off*wordSize),rcx);
2641 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
2642
2643 // Set an oopmap for the call site
2644 OopMapSet *oop_maps = new OopMapSet();
2645 OopMap* map = new OopMap( framesize, 0 );
2646 // No oopMap for rbp, it is known implicitly
2647
2648 oop_maps->add_gc_map( __ pc()-start, map);
2649
2650 __ get_thread(rcx);
2651
2652 __ reset_last_Java_frame(rcx, false, false);
2653
2654 // Load UnrollBlock into EDI
2655 __ movptr(rdi, rax);
2656
2657 // Pop all the frames we must move/replace.
2658 //
2659 // Frame picture (youngest to oldest)
2660 // 1: self-frame (no frame link)
2661 // 2: deopting frame (no frame link)
2662 // 3: caller of deopting frame (could be compiled/interpreted).
2663
2664 // Pop self-frame. We have no frame, and must rely only on EAX and ESP.
2665 __ addptr(rsp,(framesize-1)*wordSize); // Epilog!
2666
2667 // Pop deoptimized frame
2668 __ movl2ptr(rcx, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
2669 __ addptr(rsp, rcx);
2670
2671 // sp should be pointing at the return address to the caller (3)
2672
2673 // Stack bang to make sure there's enough room for these interpreter frames.
2674 if (UseStackBanging) {
2675 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2676 __ bang_stack_size(rbx, rcx);
2677 }
2678
2679
2680 // Load array of frame pcs into ECX
2681 __ movl(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2682
2683 __ pop(rsi); // trash the pc
2684
2685 // Load array of frame sizes into ESI
2686 __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
2687
2688 Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
2689
2690 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
2691 __ movl(counter, rbx);
2692
2693 // Pick up the initial fp we should save
2694 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2695
2696 // Now adjust the caller's stack to make up for the extra locals
2697 // but record the original sp so that we can save it in the skeletal interpreter
2698 // frame and the stack walking of interpreter_sender will get the unextended sp
2699 // value and not the "real" sp value.
2700
2701 Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
2702 __ movptr(sp_temp, rsp);
2703 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
2704 __ subptr(rsp, rbx);
2705
2706 // Push interpreter frames in a loop
2707 Label loop;
2708 __ bind(loop);
2709 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2710 #ifdef CC_INTERP
2711 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
2712 #ifdef ASSERT
2713 __ push(0xDEADDEAD); // Make a recognizable pattern
2714 __ push(0xDEADDEAD); // (parm to RecursiveInterpreter...)
2715 #else /* ASSERT */
2716 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
2717 #endif /* ASSERT */
2718 #else /* CC_INTERP */
2719 __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
2720 #endif /* CC_INTERP */
2721 __ pushptr(Address(rcx, 0)); // save return address
2722 __ enter(); // save old & set new rbp,
2723 __ subptr(rsp, rbx); // Prolog!
2724 __ movptr(rbx, sp_temp); // sender's sp
2725 #ifdef CC_INTERP
2726 __ movptr(Address(rbp,
2727 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2728 rbx); // Make it walkable
2729 #else /* CC_INTERP */
2730 // This value is corrected by layout_activation_impl
2731 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD );
2732 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
2733 #endif /* CC_INTERP */
2734 __ movptr(sp_temp, rsp); // pass to next frame
2735 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2736 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2737 __ decrementl(counter); // decrement counter
2738 __ jcc(Assembler::notZero, loop);
2739 __ pushptr(Address(rcx, 0)); // save final return address
2740
2741 // Re-push self-frame
2742 __ enter(); // save old & set new rbp,
2743 __ subptr(rsp, (framesize-2) * wordSize); // Prolog!
2744
2745
2746 // set last_Java_sp, last_Java_fp
2747 __ get_thread(rdi);
2748 __ set_last_Java_frame(rdi, noreg, rbp, NULL);
2749
2750 // Call C code. Need thread but NOT official VM entry
2751 // crud. We cannot block on this call, no GC can happen. Call should
2752 // restore return values to their stack-slots with the new SP.
2753 __ movptr(Address(rsp,arg0_off*wordSize),rdi);
2754 __ movl(Address(rsp,arg1_off*wordSize), Deoptimization::Unpack_uncommon_trap);
2755 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
2756 // Set an oopmap for the call site
2757 oop_maps->add_gc_map( __ pc()-start, new OopMap( framesize, 0 ) );
2758
2759 __ get_thread(rdi);
2760 __ reset_last_Java_frame(rdi, true, false);
2761
2762 // Pop self-frame.
2763 __ leave(); // Epilog!
2764
2765 // Jump to interpreter
2766 __ ret(0);
2767
2768 // -------------
2769 // make sure all code is generated
2770 masm->flush();
2771
2772 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize);
2773 }
2774 #endif // COMPILER2
2775
2776 //------------------------------generate_handler_blob------
2777 //
2778 // Generate a special Compile2Runtime blob that saves all registers,
2779 // setup oopmap, and calls safepoint code to stop the compiled code for
2780 // a safepoint.
2781 //
2782 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
2783
2784 // Account for thread arg in our frame
2785 const int additional_words = 1;
2786 int frame_size_in_words;
2787
2788 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
2789
2790 ResourceMark rm;
2791 OopMapSet *oop_maps = new OopMapSet();
2792 OopMap* map;
2793
2794 // allocate space for the code
2795 // setup code generation tools
2796 CodeBuffer buffer("handler_blob", 1024, 512);
2797 MacroAssembler* masm = new MacroAssembler(&buffer);
2798
2799 const Register java_thread = rdi; // callee-saved for VC++
2800 address start = __ pc();
2801 address call_pc = NULL;
2802
2803 // If cause_return is true we are at a poll_return and there is
2804 // the return address on the stack to the caller on the nmethod
2805 // that is safepoint. We can leave this return on the stack and
2806 // effectively complete the return and safepoint in the caller.
2807 // Otherwise we push space for a return address that the safepoint
2808 // handler will install later to make the stack walking sensible.
2809 if( !cause_return )
2810 __ push(rbx); // Make room for return address (or push it again)
2811
2812 map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
2813
2814 // The following is basically a call_VM. However, we need the precise
2815 // address of the call in order to generate an oopmap. Hence, we do all the
2816 // work ourselves.
2817
2818 // Push thread argument and setup last_Java_sp
2819 __ get_thread(java_thread);
2820 __ push(java_thread);
2821 __ set_last_Java_frame(java_thread, noreg, noreg, NULL);
2822
2823 // if this was not a poll_return then we need to correct the return address now.
2824 if( !cause_return ) {
2825 __ movptr(rax, Address(java_thread, JavaThread::saved_exception_pc_offset()));
2826 __ movptr(Address(rbp, wordSize), rax);
2827 }
2828
2829 // do the call
2830 __ call(RuntimeAddress(call_ptr));
2831
2832 // Set an oopmap for the call site. This oopmap will map all
2833 // oop-registers and debug-info registers as callee-saved. This
2834 // will allow deoptimization at this safepoint to find all possible
2835 // debug-info recordings, as well as let GC find all oops.
2836
2837 oop_maps->add_gc_map( __ pc() - start, map);
2838
2839 // Discard arg
2840 __ pop(rcx);
2841
2842 Label noException;
2843
2844 // Clear last_Java_sp again
2845 __ get_thread(java_thread);
2846 __ reset_last_Java_frame(java_thread, false, false);
2847
2848 __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
2849 __ jcc(Assembler::equal, noException);
2850
2851 // Exception pending
2852
2853 RegisterSaver::restore_live_registers(masm);
2854
2855 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2856
2857 __ bind(noException);
2858
2859 // Normal exit, register restoring and exit
2860 RegisterSaver::restore_live_registers(masm);
2861
2862 __ ret(0);
2863
2864 // make sure all code is generated
2865 masm->flush();
2866
2867 // Fill-out other meta info
2868 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
2869 }
2870
2871 //
2872 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
2873 //
2874 // Generate a stub that calls into vm to find out the proper destination
2875 // of a java call. All the argument registers are live at this point
2876 // but since this is generic code we don't know what they are and the caller
2877 // must do any gc of the args.
2878 //
2879 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
2880 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
2881
2882 // allocate space for the code
2883 ResourceMark rm;
2884
2885 CodeBuffer buffer(name, 1000, 512);
2886 MacroAssembler* masm = new MacroAssembler(&buffer);
2887
2888 int frame_size_words;
2889 enum frame_layout {
2890 thread_off,
2891 extra_words };
2892
2893 OopMapSet *oop_maps = new OopMapSet();
2894 OopMap* map = NULL;
2895
2896 int start = __ offset();
2897
2898 map = RegisterSaver::save_live_registers(masm, extra_words, &frame_size_words);
2899
2900 int frame_complete = __ offset();
2901
2902 const Register thread = rdi;
2903 __ get_thread(rdi);
2904
2905 __ push(thread);
2906 __ set_last_Java_frame(thread, noreg, rbp, NULL);
2907
2908 __ call(RuntimeAddress(destination));
2909
2910
2911 // Set an oopmap for the call site.
2912 // We need this not only for callee-saved registers, but also for volatile
2913 // registers that the compiler might be keeping live across a safepoint.
2914
2915 oop_maps->add_gc_map( __ offset() - start, map);
2916
2917 // rax, contains the address we are going to jump to assuming no exception got installed
2918
2919 __ addptr(rsp, wordSize);
2920
2921 // clear last_Java_sp
2922 __ reset_last_Java_frame(thread, true, false);
2923 // check for pending exceptions
2924 Label pending;
2925 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
2926 __ jcc(Assembler::notEqual, pending);
2927
2928 // get the returned methodOop
2929 __ movptr(rbx, Address(thread, JavaThread::vm_result_offset()));
2930 __ movptr(Address(rsp, RegisterSaver::rbx_offset() * wordSize), rbx);
2931
2932 __ movptr(Address(rsp, RegisterSaver::rax_offset() * wordSize), rax);
2933
2934 RegisterSaver::restore_live_registers(masm);
2935
2936 // We are back the the original state on entry and ready to go.
2937
2938 __ jmp(rax);
2939
2940 // Pending exception after the safepoint
2941
2942 __ bind(pending);
2943
2944 RegisterSaver::restore_live_registers(masm);
2945
2946 // exception pending => remove activation and forward to exception handler
2947
2948 __ get_thread(thread);
2949 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
2950 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
2951 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2952
2953 // -------------
2954 // make sure all code is generated
2955 masm->flush();
2956
2957 // return the blob
2958 // frame_size_words or bytes??
2959 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
2960 }