src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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 125           ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
 126            (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
 127         return true;
 128       }
 129 
 130       return false;
 131     }
 132 
 133     default:
 134       return false;
 135   }
 136   ShouldNotReachHere();
 137 }
 138 
 139 
 140 LIR_Opr LIR_Assembler::receiverOpr() {
 141   return FrameMap::O0_oop_opr;
 142 }
 143 
 144 
 145 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
 146   return FrameMap::I0_oop_opr;
 147 }
 148 
 149 
 150 LIR_Opr LIR_Assembler::osrBufferPointer() {
 151   return FrameMap::I0_opr;
 152 }
 153 
 154 
 155 int LIR_Assembler::initial_frame_size_in_bytes() {
 156   return in_bytes(frame_map()->framesize_in_bytes());
 157 }
 158 
 159 
 160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
 161 // we fetch the class of the receiver (O0) and compare it with the cached class.
 162 // If they do not match we jump to slow case.
 163 int LIR_Assembler::check_icache() {
 164   int offset = __ offset();
 165   __ inline_cache_check(O0, G5_inline_cache_reg);
 166   return offset;
 167 }
 168 
 169 




 125           ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
 126            (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
 127         return true;
 128       }
 129 
 130       return false;
 131     }
 132 
 133     default:
 134       return false;
 135   }
 136   ShouldNotReachHere();
 137 }
 138 
 139 
 140 LIR_Opr LIR_Assembler::receiverOpr() {
 141   return FrameMap::O0_oop_opr;
 142 }
 143 
 144 





 145 LIR_Opr LIR_Assembler::osrBufferPointer() {
 146   return FrameMap::I0_opr;
 147 }
 148 
 149 
 150 int LIR_Assembler::initial_frame_size_in_bytes() {
 151   return in_bytes(frame_map()->framesize_in_bytes());
 152 }
 153 
 154 
 155 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
 156 // we fetch the class of the receiver (O0) and compare it with the cached class.
 157 // If they do not match we jump to slow case.
 158 int LIR_Assembler::check_icache() {
 159   int offset = __ offset();
 160   __ inline_cache_check(O0, G5_inline_cache_reg);
 161   return offset;
 162 }
 163 
 164 


src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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