1 /*
2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "assembler_x86.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolderOop.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class SimpleRuntimeFrame {
49
50 public:
51
52 // Most of the runtime stubs have this simple frame layout.
53 // This class exists to make the layout shared in one place.
54 // Offsets are for compiler stack slots, which are jints.
55 enum layout {
56 // The frame sender code expects that rbp will be in the "natural" place and
57 // will override any oopMap setting for it. We must therefore force the layout
58 // so that it agrees with the frame sender code.
59 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
60 rbp_off2,
61 return_off, return_off2,
62 framesize
63 };
64 };
65
66 class RegisterSaver {
67 // Capture info about frame layout. Layout offsets are in jint
68 // units because compiler frame slots are jints.
69 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
70 enum layout {
71 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
72 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
73 DEF_XMM_OFFS(0),
74 DEF_XMM_OFFS(1),
75 DEF_XMM_OFFS(2),
76 DEF_XMM_OFFS(3),
77 DEF_XMM_OFFS(4),
78 DEF_XMM_OFFS(5),
79 DEF_XMM_OFFS(6),
80 DEF_XMM_OFFS(7),
81 DEF_XMM_OFFS(8),
82 DEF_XMM_OFFS(9),
83 DEF_XMM_OFFS(10),
84 DEF_XMM_OFFS(11),
85 DEF_XMM_OFFS(12),
86 DEF_XMM_OFFS(13),
87 DEF_XMM_OFFS(14),
88 DEF_XMM_OFFS(15),
89 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
90 fpu_stateH_end,
91 r15_off, r15H_off,
92 r14_off, r14H_off,
93 r13_off, r13H_off,
94 r12_off, r12H_off,
95 r11_off, r11H_off,
96 r10_off, r10H_off,
97 r9_off, r9H_off,
98 r8_off, r8H_off,
99 rdi_off, rdiH_off,
100 rsi_off, rsiH_off,
101 ignore_off, ignoreH_off, // extra copy of rbp
102 rsp_off, rspH_off,
103 rbx_off, rbxH_off,
104 rdx_off, rdxH_off,
105 rcx_off, rcxH_off,
106 rax_off, raxH_off,
107 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
108 align_off, alignH_off,
109 flags_off, flagsH_off,
110 // The frame sender code expects that rbp will be in the "natural" place and
111 // will override any oopMap setting for it. We must therefore force the layout
112 // so that it agrees with the frame sender code.
113 rbp_off, rbpH_off, // copy of rbp we will restore
114 return_off, returnH_off, // slot for return address
115 reg_save_size // size in compiler stack slots
116 };
117
118 public:
119 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
120 static void restore_live_registers(MacroAssembler* masm);
121
122 // Offsets into the register save area
123 // Used by deoptimization when it is managing result register
124 // values on its own
125
126 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
127 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
128 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
129 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
130 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
131
132 // During deoptimization only the result registers need to be restored,
133 // all the other values have already been extracted.
134 static void restore_result_registers(MacroAssembler* masm);
135 };
136
137 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
138
139 // Always make the frame size 16-byte aligned
140 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
141 reg_save_size*BytesPerInt, 16);
142 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
143 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
144 // The caller will allocate additional_frame_words
145 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
146 // CodeBlob frame size is in words.
147 int frame_size_in_words = frame_size_in_bytes / wordSize;
148 *total_frame_words = frame_size_in_words;
149
150 // Save registers, fpu state, and flags.
151 // We assume caller has already pushed the return address onto the
152 // stack, so rsp is 8-byte aligned here.
153 // We push rpb twice in this sequence because we want the real rbp
154 // to be under the return like a normal enter.
155
156 __ enter(); // rsp becomes 16-byte aligned here
157 __ push_CPU_state(); // Push a multiple of 16 bytes
158 if (frame::arg_reg_save_area_bytes != 0) {
159 // Allocate argument register save area
160 __ subptr(rsp, frame::arg_reg_save_area_bytes);
161 }
162
163 // Set an oopmap for the call site. This oopmap will map all
164 // oop-registers and debug-info registers as callee-saved. This
165 // will allow deoptimization at this safepoint to find all possible
166 // debug-info recordings, as well as let GC find all oops.
167
168 OopMapSet *oop_maps = new OopMapSet();
169 OopMap* map = new OopMap(frame_size_in_slots, 0);
170 map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg());
171 map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg());
172 map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg());
173 map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg());
174 // rbp location is known implicitly by the frame sender code, needs no oopmap
175 // and the location where rbp was saved by is ignored
176 map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg());
177 map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg());
178 map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg());
179 map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg());
180 map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg());
181 map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg());
182 map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg());
183 map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg());
184 map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg());
185 map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg());
186 map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg());
187 map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg());
188 map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg());
189 map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg());
190 map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg());
191 map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg());
192 map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg());
193 map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg());
194 map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg());
195 map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg());
196 map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg());
197 map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg());
198 map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg());
199 map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg());
200 map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg());
201 map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg());
202
203 // %%% These should all be a waste but we'll keep things as they were for now
204 if (true) {
205 map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots),
206 rax->as_VMReg()->next());
207 map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots),
208 rcx->as_VMReg()->next());
209 map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots),
210 rdx->as_VMReg()->next());
211 map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots),
212 rbx->as_VMReg()->next());
213 // rbp location is known implicitly by the frame sender code, needs no oopmap
214 map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots),
215 rsi->as_VMReg()->next());
216 map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots),
217 rdi->as_VMReg()->next());
218 map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots),
219 r8->as_VMReg()->next());
220 map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots),
221 r9->as_VMReg()->next());
222 map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots),
223 r10->as_VMReg()->next());
224 map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots),
225 r11->as_VMReg()->next());
226 map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots),
227 r12->as_VMReg()->next());
228 map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots),
229 r13->as_VMReg()->next());
230 map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots),
231 r14->as_VMReg()->next());
232 map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots),
233 r15->as_VMReg()->next());
234 map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots),
235 xmm0->as_VMReg()->next());
236 map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots),
237 xmm1->as_VMReg()->next());
238 map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots),
239 xmm2->as_VMReg()->next());
240 map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots),
241 xmm3->as_VMReg()->next());
242 map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots),
243 xmm4->as_VMReg()->next());
244 map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots),
245 xmm5->as_VMReg()->next());
246 map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots),
247 xmm6->as_VMReg()->next());
248 map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots),
249 xmm7->as_VMReg()->next());
250 map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots),
251 xmm8->as_VMReg()->next());
252 map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots),
253 xmm9->as_VMReg()->next());
254 map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots),
255 xmm10->as_VMReg()->next());
256 map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots),
257 xmm11->as_VMReg()->next());
258 map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots),
259 xmm12->as_VMReg()->next());
260 map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots),
261 xmm13->as_VMReg()->next());
262 map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots),
263 xmm14->as_VMReg()->next());
264 map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots),
265 xmm15->as_VMReg()->next());
266 }
267
268 return map;
269 }
270
271 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
272 if (frame::arg_reg_save_area_bytes != 0) {
273 // Pop arg register save area
274 __ addptr(rsp, frame::arg_reg_save_area_bytes);
275 }
276 // Recover CPU state
277 __ pop_CPU_state();
278 // Get the rbp described implicitly by the calling convention (no oopMap)
279 __ pop(rbp);
280 }
281
282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
283
284 // Just restore result register. Only used by deoptimization. By
285 // now any callee save register that needs to be restored to a c2
286 // caller of the deoptee has been extracted into the vframeArray
287 // and will be stuffed into the c2i adapter we create for later
288 // restoration so only result registers need to be restored here.
289
290 // Restore fp result register
291 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
292 // Restore integer result register
293 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
294 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
295
296 // Pop all of the register save are off the stack except the return address
297 __ addptr(rsp, return_offset_in_bytes());
298 }
299
300 // The java_calling_convention describes stack locations as ideal slots on
301 // a frame with no abi restrictions. Since we must observe abi restrictions
302 // (like the placement of the register window) the slots must be biased by
303 // the following value.
304 static int reg2offset_in(VMReg r) {
305 // Account for saved rbp and return address
306 // This should really be in_preserve_stack_slots
307 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
308 }
309
310 static int reg2offset_out(VMReg r) {
311 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
312 }
313
314 // ---------------------------------------------------------------------------
315 // Read the array of BasicTypes from a signature, and compute where the
316 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
317 // quantities. Values less than VMRegImpl::stack0 are registers, those above
318 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
319 // as framesizes are fixed.
320 // VMRegImpl::stack0 refers to the first slot 0(sp).
321 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
322 // up to RegisterImpl::number_of_registers) are the 64-bit
323 // integer registers.
324
325 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
326 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
327 // units regardless of build. Of course for i486 there is no 64 bit build
328
329 // The Java calling convention is a "shifted" version of the C ABI.
330 // By skipping the first C ABI register we can call non-static jni methods
331 // with small numbers of arguments without having to shuffle the arguments
332 // at all. Since we control the java ABI we ought to at least get some
333 // advantage out of it.
334
335 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
336 VMRegPair *regs,
337 int total_args_passed,
338 int is_outgoing) {
339
340 // Create the mapping between argument positions and
341 // registers.
342 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
343 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
344 };
345 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
346 j_farg0, j_farg1, j_farg2, j_farg3,
347 j_farg4, j_farg5, j_farg6, j_farg7
348 };
349
350
351 uint int_args = 0;
352 uint fp_args = 0;
353 uint stk_args = 0; // inc by 2 each time
354
355 for (int i = 0; i < total_args_passed; i++) {
356 switch (sig_bt[i]) {
357 case T_BOOLEAN:
358 case T_CHAR:
359 case T_BYTE:
360 case T_SHORT:
361 case T_INT:
362 if (int_args < Argument::n_int_register_parameters_j) {
363 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
364 } else {
365 regs[i].set1(VMRegImpl::stack2reg(stk_args));
366 stk_args += 2;
367 }
368 break;
369 case T_VOID:
370 // halves of T_LONG or T_DOUBLE
371 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
372 regs[i].set_bad();
373 break;
374 case T_LONG:
375 assert(sig_bt[i + 1] == T_VOID, "expecting half");
376 // fall through
377 case T_OBJECT:
378 case T_ARRAY:
379 case T_ADDRESS:
380 if (int_args < Argument::n_int_register_parameters_j) {
381 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
382 } else {
383 regs[i].set2(VMRegImpl::stack2reg(stk_args));
384 stk_args += 2;
385 }
386 break;
387 case T_FLOAT:
388 if (fp_args < Argument::n_float_register_parameters_j) {
389 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
390 } else {
391 regs[i].set1(VMRegImpl::stack2reg(stk_args));
392 stk_args += 2;
393 }
394 break;
395 case T_DOUBLE:
396 assert(sig_bt[i + 1] == T_VOID, "expecting half");
397 if (fp_args < Argument::n_float_register_parameters_j) {
398 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
399 } else {
400 regs[i].set2(VMRegImpl::stack2reg(stk_args));
401 stk_args += 2;
402 }
403 break;
404 default:
405 ShouldNotReachHere();
406 break;
407 }
408 }
409
410 return round_to(stk_args, 2);
411 }
412
413 // Patch the callers callsite with entry to compiled code if it exists.
414 static void patch_callers_callsite(MacroAssembler *masm) {
415 Label L;
416 __ verify_oop(rbx);
417 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
418 __ jcc(Assembler::equal, L);
419
420 // Save the current stack pointer
421 __ mov(r13, rsp);
422 // Schedule the branch target address early.
423 // Call into the VM to patch the caller, then jump to compiled callee
424 // rax isn't live so capture return address while we easily can
425 __ movptr(rax, Address(rsp, 0));
426
427 // align stack so push_CPU_state doesn't fault
428 __ andptr(rsp, -(StackAlignmentInBytes));
429 __ push_CPU_state();
430
431
432 __ verify_oop(rbx);
433 // VM needs caller's callsite
434 // VM needs target method
435 // This needs to be a long call since we will relocate this adapter to
436 // the codeBuffer and it may not reach
437
438 // Allocate argument register save area
439 if (frame::arg_reg_save_area_bytes != 0) {
440 __ subptr(rsp, frame::arg_reg_save_area_bytes);
441 }
442 __ mov(c_rarg0, rbx);
443 __ mov(c_rarg1, rax);
444 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
445
446 // De-allocate argument register save area
447 if (frame::arg_reg_save_area_bytes != 0) {
448 __ addptr(rsp, frame::arg_reg_save_area_bytes);
449 }
450
451 __ pop_CPU_state();
452 // restore sp
453 __ mov(rsp, r13);
454 __ bind(L);
455 }
456
457
458 static void gen_c2i_adapter(MacroAssembler *masm,
459 int total_args_passed,
460 int comp_args_on_stack,
461 const BasicType *sig_bt,
462 const VMRegPair *regs,
463 Label& skip_fixup) {
464 // Before we get into the guts of the C2I adapter, see if we should be here
465 // at all. We've come from compiled code and are attempting to jump to the
466 // interpreter, which means the caller made a static call to get here
467 // (vcalls always get a compiled target if there is one). Check for a
468 // compiled target. If there is one, we need to patch the caller's call.
469 patch_callers_callsite(masm);
470
471 __ bind(skip_fixup);
472
473 // Since all args are passed on the stack, total_args_passed *
474 // Interpreter::stackElementSize is the space we need. Plus 1 because
475 // we also account for the return address location since
476 // we store it first rather than hold it in rax across all the shuffling
477
478 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
479
480 // stack is aligned, keep it that way
481 extraspace = round_to(extraspace, 2*wordSize);
482
483 // Get return address
484 __ pop(rax);
485
486 // set senderSP value
487 __ mov(r13, rsp);
488
489 __ subptr(rsp, extraspace);
490
491 // Store the return address in the expected location
492 __ movptr(Address(rsp, 0), rax);
493
494 // Now write the args into the outgoing interpreter space
495 for (int i = 0; i < total_args_passed; i++) {
496 if (sig_bt[i] == T_VOID) {
497 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
498 continue;
499 }
500
501 // offset to start parameters
502 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
503 int next_off = st_off - Interpreter::stackElementSize;
504
505 // Say 4 args:
506 // i st_off
507 // 0 32 T_LONG
508 // 1 24 T_VOID
509 // 2 16 T_OBJECT
510 // 3 8 T_BOOL
511 // - 0 return address
512 //
513 // However to make thing extra confusing. Because we can fit a long/double in
514 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
515 // leaves one slot empty and only stores to a single slot. In this case the
516 // slot that is occupied is the T_VOID slot. See I said it was confusing.
517
518 VMReg r_1 = regs[i].first();
519 VMReg r_2 = regs[i].second();
520 if (!r_1->is_valid()) {
521 assert(!r_2->is_valid(), "");
522 continue;
523 }
524 if (r_1->is_stack()) {
525 // memory to memory use rax
526 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
527 if (!r_2->is_valid()) {
528 // sign extend??
529 __ movl(rax, Address(rsp, ld_off));
530 __ movptr(Address(rsp, st_off), rax);
531
532 } else {
533
534 __ movq(rax, Address(rsp, ld_off));
535
536 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
537 // T_DOUBLE and T_LONG use two slots in the interpreter
538 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
539 // ld_off == LSW, ld_off+wordSize == MSW
540 // st_off == MSW, next_off == LSW
541 __ movq(Address(rsp, next_off), rax);
542 #ifdef ASSERT
543 // Overwrite the unused slot with known junk
544 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
545 __ movptr(Address(rsp, st_off), rax);
546 #endif /* ASSERT */
547 } else {
548 __ movq(Address(rsp, st_off), rax);
549 }
550 }
551 } else if (r_1->is_Register()) {
552 Register r = r_1->as_Register();
553 if (!r_2->is_valid()) {
554 // must be only an int (or less ) so move only 32bits to slot
555 // why not sign extend??
556 __ movl(Address(rsp, st_off), r);
557 } else {
558 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
559 // T_DOUBLE and T_LONG use two slots in the interpreter
560 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
561 // long/double in gpr
562 #ifdef ASSERT
563 // Overwrite the unused slot with known junk
564 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
565 __ movptr(Address(rsp, st_off), rax);
566 #endif /* ASSERT */
567 __ movq(Address(rsp, next_off), r);
568 } else {
569 __ movptr(Address(rsp, st_off), r);
570 }
571 }
572 } else {
573 assert(r_1->is_XMMRegister(), "");
574 if (!r_2->is_valid()) {
575 // only a float use just part of the slot
576 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
577 } else {
578 #ifdef ASSERT
579 // Overwrite the unused slot with known junk
580 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
581 __ movptr(Address(rsp, st_off), rax);
582 #endif /* ASSERT */
583 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
584 }
585 }
586 }
587
588 // Schedule the branch target address early.
589 __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
590 __ jmp(rcx);
591 }
592
593 static void gen_i2c_adapter(MacroAssembler *masm,
594 int total_args_passed,
595 int comp_args_on_stack,
596 const BasicType *sig_bt,
597 const VMRegPair *regs) {
598
599 // Note: r13 contains the senderSP on entry. We must preserve it since
600 // we may do a i2c -> c2i transition if we lose a race where compiled
601 // code goes non-entrant while we get args ready.
602 // In addition we use r13 to locate all the interpreter args as
603 // we must align the stack to 16 bytes on an i2c entry else we
604 // lose alignment we expect in all compiled code and register
605 // save code can segv when fxsave instructions find improperly
606 // aligned stack pointer.
607
608 // Pick up the return address
609 __ movptr(rax, Address(rsp, 0));
610
611 // Must preserve original SP for loading incoming arguments because
612 // we need to align the outgoing SP for compiled code.
613 __ movptr(r11, rsp);
614
615 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
616 // in registers, we will occasionally have no stack args.
617 int comp_words_on_stack = 0;
618 if (comp_args_on_stack) {
619 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
620 // registers are below. By subtracting stack0, we either get a negative
621 // number (all values in registers) or the maximum stack slot accessed.
622
623 // Convert 4-byte c2 stack slots to words.
624 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
625 // Round up to miminum stack alignment, in wordSize
626 comp_words_on_stack = round_to(comp_words_on_stack, 2);
627 __ subptr(rsp, comp_words_on_stack * wordSize);
628 }
629
630
631 // Ensure compiled code always sees stack at proper alignment
632 __ andptr(rsp, -16);
633
634 // push the return address and misalign the stack that youngest frame always sees
635 // as far as the placement of the call instruction
636 __ push(rax);
637
638 // Put saved SP in another register
639 const Register saved_sp = rax;
640 __ movptr(saved_sp, r11);
641
642 // Will jump to the compiled code just as if compiled code was doing it.
643 // Pre-load the register-jump target early, to schedule it better.
644 __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
645
646 // Now generate the shuffle code. Pick up all register args and move the
647 // rest through the floating point stack top.
648 for (int i = 0; i < total_args_passed; i++) {
649 if (sig_bt[i] == T_VOID) {
650 // Longs and doubles are passed in native word order, but misaligned
651 // in the 32-bit build.
652 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
653 continue;
654 }
655
656 // Pick up 0, 1 or 2 words from SP+offset.
657
658 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
659 "scrambled load targets?");
660 // Load in argument order going down.
661 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
662 // Point to interpreter value (vs. tag)
663 int next_off = ld_off - Interpreter::stackElementSize;
664 //
665 //
666 //
667 VMReg r_1 = regs[i].first();
668 VMReg r_2 = regs[i].second();
669 if (!r_1->is_valid()) {
670 assert(!r_2->is_valid(), "");
671 continue;
672 }
673 if (r_1->is_stack()) {
674 // Convert stack slot to an SP offset (+ wordSize to account for return address )
675 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
676
677 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
678 // and if we end up going thru a c2i because of a miss a reasonable value of r13
679 // will be generated.
680 if (!r_2->is_valid()) {
681 // sign extend???
682 __ movl(r13, Address(saved_sp, ld_off));
683 __ movptr(Address(rsp, st_off), r13);
684 } else {
685 //
686 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
687 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
688 // So we must adjust where to pick up the data to match the interpreter.
689 //
690 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
691 // are accessed as negative so LSW is at LOW address
692
693 // ld_off is MSW so get LSW
694 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
695 next_off : ld_off;
696 __ movq(r13, Address(saved_sp, offset));
697 // st_off is LSW (i.e. reg.first())
698 __ movq(Address(rsp, st_off), r13);
699 }
700 } else if (r_1->is_Register()) { // Register argument
701 Register r = r_1->as_Register();
702 assert(r != rax, "must be different");
703 if (r_2->is_valid()) {
704 //
705 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
706 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
707 // So we must adjust where to pick up the data to match the interpreter.
708
709 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
710 next_off : ld_off;
711
712 // this can be a misaligned move
713 __ movq(r, Address(saved_sp, offset));
714 } else {
715 // sign extend and use a full word?
716 __ movl(r, Address(saved_sp, ld_off));
717 }
718 } else {
719 if (!r_2->is_valid()) {
720 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
721 } else {
722 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
723 }
724 }
725 }
726
727 // 6243940 We might end up in handle_wrong_method if
728 // the callee is deoptimized as we race thru here. If that
729 // happens we don't want to take a safepoint because the
730 // caller frame will look interpreted and arguments are now
731 // "compiled" so it is much better to make this transition
732 // invisible to the stack walking code. Unfortunately if
733 // we try and find the callee by normal means a safepoint
734 // is possible. So we stash the desired callee in the thread
735 // and the vm will find there should this case occur.
736
737 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
738
739 // put methodOop where a c2i would expect should we end up there
740 // only needed becaus eof c2 resolve stubs return methodOop as a result in
741 // rax
742 __ mov(rax, rbx);
743 __ jmp(r11);
744 }
745
746 // ---------------------------------------------------------------
747 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
748 int total_args_passed,
749 int comp_args_on_stack,
750 const BasicType *sig_bt,
751 const VMRegPair *regs,
752 AdapterFingerPrint* fingerprint) {
753 address i2c_entry = __ pc();
754
755 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
756
757 // -------------------------------------------------------------------------
758 // Generate a C2I adapter. On entry we know rbx holds the methodOop during calls
759 // to the interpreter. The args start out packed in the compiled layout. They
760 // need to be unpacked into the interpreter layout. This will almost always
761 // require some stack space. We grow the current (compiled) stack, then repack
762 // the args. We finally end in a jump to the generic interpreter entry point.
763 // On exit from the interpreter, the interpreter will restore our SP (lest the
764 // compiled code, which relys solely on SP and not RBP, get sick).
765
766 address c2i_unverified_entry = __ pc();
767 Label skip_fixup;
768 Label ok;
769
770 Register holder = rax;
771 Register receiver = j_rarg0;
772 Register temp = rbx;
773
774 {
775 __ verify_oop(holder);
776 __ load_klass(temp, receiver);
777 __ verify_oop(temp);
778
779 __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
780 __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
781 __ jcc(Assembler::equal, ok);
782 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
783
784 __ bind(ok);
785 // Method might have been compiled since the call site was patched to
786 // interpreted if that is the case treat it as a miss so we can get
787 // the call site corrected.
788 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
789 __ jcc(Assembler::equal, skip_fixup);
790 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
791 }
792
793 address c2i_entry = __ pc();
794
795 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
796
797 __ flush();
798 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
799 }
800
801 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
802 VMRegPair *regs,
803 int total_args_passed) {
804 // We return the amount of VMRegImpl stack slots we need to reserve for all
805 // the arguments NOT counting out_preserve_stack_slots.
806
807 // NOTE: These arrays will have to change when c1 is ported
808 #ifdef _WIN64
809 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
810 c_rarg0, c_rarg1, c_rarg2, c_rarg3
811 };
812 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
813 c_farg0, c_farg1, c_farg2, c_farg3
814 };
815 #else
816 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
817 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
818 };
819 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
820 c_farg0, c_farg1, c_farg2, c_farg3,
821 c_farg4, c_farg5, c_farg6, c_farg7
822 };
823 #endif // _WIN64
824
825
826 uint int_args = 0;
827 uint fp_args = 0;
828 uint stk_args = 0; // inc by 2 each time
829
830 for (int i = 0; i < total_args_passed; i++) {
831 switch (sig_bt[i]) {
832 case T_BOOLEAN:
833 case T_CHAR:
834 case T_BYTE:
835 case T_SHORT:
836 case T_INT:
837 if (int_args < Argument::n_int_register_parameters_c) {
838 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
839 #ifdef _WIN64
840 fp_args++;
841 // Allocate slots for callee to stuff register args the stack.
842 stk_args += 2;
843 #endif
844 } else {
845 regs[i].set1(VMRegImpl::stack2reg(stk_args));
846 stk_args += 2;
847 }
848 break;
849 case T_LONG:
850 assert(sig_bt[i + 1] == T_VOID, "expecting half");
851 // fall through
852 case T_OBJECT:
853 case T_ARRAY:
854 case T_ADDRESS:
855 if (int_args < Argument::n_int_register_parameters_c) {
856 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
857 #ifdef _WIN64
858 fp_args++;
859 stk_args += 2;
860 #endif
861 } else {
862 regs[i].set2(VMRegImpl::stack2reg(stk_args));
863 stk_args += 2;
864 }
865 break;
866 case T_FLOAT:
867 if (fp_args < Argument::n_float_register_parameters_c) {
868 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
869 #ifdef _WIN64
870 int_args++;
871 // Allocate slots for callee to stuff register args the stack.
872 stk_args += 2;
873 #endif
874 } else {
875 regs[i].set1(VMRegImpl::stack2reg(stk_args));
876 stk_args += 2;
877 }
878 break;
879 case T_DOUBLE:
880 assert(sig_bt[i + 1] == T_VOID, "expecting half");
881 if (fp_args < Argument::n_float_register_parameters_c) {
882 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
883 #ifdef _WIN64
884 int_args++;
885 // Allocate slots for callee to stuff register args the stack.
886 stk_args += 2;
887 #endif
888 } else {
889 regs[i].set2(VMRegImpl::stack2reg(stk_args));
890 stk_args += 2;
891 }
892 break;
893 case T_VOID: // Halves of longs and doubles
894 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
895 regs[i].set_bad();
896 break;
897 default:
898 ShouldNotReachHere();
899 break;
900 }
901 }
902 #ifdef _WIN64
903 // windows abi requires that we always allocate enough stack space
904 // for 4 64bit registers to be stored down.
905 if (stk_args < 8) {
906 stk_args = 8;
907 }
908 #endif // _WIN64
909
910 return stk_args;
911 }
912
913 // On 64 bit we will store integer like items to the stack as
914 // 64 bits items (sparc abi) even though java would only store
915 // 32bits for a parameter. On 32bit it will simply be 32 bits
916 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
917 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
918 if (src.first()->is_stack()) {
919 if (dst.first()->is_stack()) {
920 // stack to stack
921 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
922 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
923 } else {
924 // stack to reg
925 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
926 }
927 } else if (dst.first()->is_stack()) {
928 // reg to stack
929 // Do we really have to sign extend???
930 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
931 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
932 } else {
933 // Do we really have to sign extend???
934 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
935 if (dst.first() != src.first()) {
936 __ movq(dst.first()->as_Register(), src.first()->as_Register());
937 }
938 }
939 }
940
941 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
942 if (src.first()->is_stack()) {
943 if (dst.first()->is_stack()) {
944 // stack to stack
945 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
946 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
947 } else {
948 // stack to reg
949 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
950 }
951 } else if (dst.first()->is_stack()) {
952 // reg to stack
953 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
954 } else {
955 if (dst.first() != src.first()) {
956 __ movq(dst.first()->as_Register(), src.first()->as_Register());
957 }
958 }
959 }
960
961 // An oop arg. Must pass a handle not the oop itself
962 static void object_move(MacroAssembler* masm,
963 OopMap* map,
964 int oop_handle_offset,
965 int framesize_in_slots,
966 VMRegPair src,
967 VMRegPair dst,
968 bool is_receiver,
969 int* receiver_offset) {
970
971 // must pass a handle. First figure out the location we use as a handle
972
973 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
974
975 // See if oop is NULL if it is we need no handle
976
977 if (src.first()->is_stack()) {
978
979 // Oop is already on the stack as an argument
980 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
981 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
982 if (is_receiver) {
983 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
984 }
985
986 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
987 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
988 // conditionally move a NULL
989 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
990 } else {
991
992 // Oop is in an a register we must store it to the space we reserve
993 // on the stack for oop_handles and pass a handle if oop is non-NULL
994
995 const Register rOop = src.first()->as_Register();
996 int oop_slot;
997 if (rOop == j_rarg0)
998 oop_slot = 0;
999 else if (rOop == j_rarg1)
1000 oop_slot = 1;
1001 else if (rOop == j_rarg2)
1002 oop_slot = 2;
1003 else if (rOop == j_rarg3)
1004 oop_slot = 3;
1005 else if (rOop == j_rarg4)
1006 oop_slot = 4;
1007 else {
1008 assert(rOop == j_rarg5, "wrong register");
1009 oop_slot = 5;
1010 }
1011
1012 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1013 int offset = oop_slot*VMRegImpl::stack_slot_size;
1014
1015 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1016 // Store oop in handle area, may be NULL
1017 __ movptr(Address(rsp, offset), rOop);
1018 if (is_receiver) {
1019 *receiver_offset = offset;
1020 }
1021
1022 __ cmpptr(rOop, (int32_t)NULL_WORD);
1023 __ lea(rHandle, Address(rsp, offset));
1024 // conditionally move a NULL from the handle area where it was just stored
1025 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1026 }
1027
1028 // If arg is on the stack then place it otherwise it is already in correct reg.
1029 if (dst.first()->is_stack()) {
1030 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1031 }
1032 }
1033
1034 // A float arg may have to do float reg int reg conversion
1035 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1036 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1037
1038 // The calling conventions assures us that each VMregpair is either
1039 // all really one physical register or adjacent stack slots.
1040 // This greatly simplifies the cases here compared to sparc.
1041
1042 if (src.first()->is_stack()) {
1043 if (dst.first()->is_stack()) {
1044 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1045 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1046 } else {
1047 // stack to reg
1048 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1049 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1050 }
1051 } else if (dst.first()->is_stack()) {
1052 // reg to stack
1053 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1054 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1055 } else {
1056 // reg to reg
1057 // In theory these overlap but the ordering is such that this is likely a nop
1058 if ( src.first() != dst.first()) {
1059 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1060 }
1061 }
1062 }
1063
1064 // A long move
1065 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1066
1067 // The calling conventions assures us that each VMregpair is either
1068 // all really one physical register or adjacent stack slots.
1069 // This greatly simplifies the cases here compared to sparc.
1070
1071 if (src.is_single_phys_reg() ) {
1072 if (dst.is_single_phys_reg()) {
1073 if (dst.first() != src.first()) {
1074 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1075 }
1076 } else {
1077 assert(dst.is_single_reg(), "not a stack pair");
1078 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1079 }
1080 } else if (dst.is_single_phys_reg()) {
1081 assert(src.is_single_reg(), "not a stack pair");
1082 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1083 } else {
1084 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1085 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1086 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1087 }
1088 }
1089
1090 // A double move
1091 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1092
1093 // The calling conventions assures us that each VMregpair is either
1094 // all really one physical register or adjacent stack slots.
1095 // This greatly simplifies the cases here compared to sparc.
1096
1097 if (src.is_single_phys_reg() ) {
1098 if (dst.is_single_phys_reg()) {
1099 // In theory these overlap but the ordering is such that this is likely a nop
1100 if ( src.first() != dst.first()) {
1101 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1102 }
1103 } else {
1104 assert(dst.is_single_reg(), "not a stack pair");
1105 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1106 }
1107 } else if (dst.is_single_phys_reg()) {
1108 assert(src.is_single_reg(), "not a stack pair");
1109 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1110 } else {
1111 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1112 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1113 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1114 }
1115 }
1116
1117
1118 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1119 // We always ignore the frame_slots arg and just use the space just below frame pointer
1120 // which by this time is free to use
1121 switch (ret_type) {
1122 case T_FLOAT:
1123 __ movflt(Address(rbp, -wordSize), xmm0);
1124 break;
1125 case T_DOUBLE:
1126 __ movdbl(Address(rbp, -wordSize), xmm0);
1127 break;
1128 case T_VOID: break;
1129 default: {
1130 __ movptr(Address(rbp, -wordSize), rax);
1131 }
1132 }
1133 }
1134
1135 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1136 // We always ignore the frame_slots arg and just use the space just below frame pointer
1137 // which by this time is free to use
1138 switch (ret_type) {
1139 case T_FLOAT:
1140 __ movflt(xmm0, Address(rbp, -wordSize));
1141 break;
1142 case T_DOUBLE:
1143 __ movdbl(xmm0, Address(rbp, -wordSize));
1144 break;
1145 case T_VOID: break;
1146 default: {
1147 __ movptr(rax, Address(rbp, -wordSize));
1148 }
1149 }
1150 }
1151
1152 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1153 for ( int i = first_arg ; i < arg_count ; i++ ) {
1154 if (args[i].first()->is_Register()) {
1155 __ push(args[i].first()->as_Register());
1156 } else if (args[i].first()->is_XMMRegister()) {
1157 __ subptr(rsp, 2*wordSize);
1158 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1159 }
1160 }
1161 }
1162
1163 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1164 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1165 if (args[i].first()->is_Register()) {
1166 __ pop(args[i].first()->as_Register());
1167 } else if (args[i].first()->is_XMMRegister()) {
1168 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1169 __ addptr(rsp, 2*wordSize);
1170 }
1171 }
1172 }
1173
1174
1175 static void save_or_restore_arguments(MacroAssembler* masm,
1176 const int stack_slots,
1177 const int total_in_args,
1178 const int arg_save_area,
1179 OopMap* map,
1180 VMRegPair* in_regs,
1181 BasicType* in_sig_bt) {
1182 // if map is non-NULL then the code should store the values,
1183 // otherwise it should load them.
1184 int handle_index = 0;
1185 // Save down double word first
1186 for ( int i = 0; i < total_in_args; i++) {
1187 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1188 int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
1189 int offset = slot * VMRegImpl::stack_slot_size;
1190 handle_index += 2;
1191 assert(handle_index <= stack_slots, "overflow");
1192 if (map != NULL) {
1193 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1194 } else {
1195 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1196 }
1197 }
1198 if (in_regs[i].first()->is_Register() &&
1199 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1200 int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
1201 int offset = slot * VMRegImpl::stack_slot_size;
1202 handle_index += 2;
1203 assert(handle_index <= stack_slots, "overflow");
1204 if (map != NULL) {
1205 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1206 if (in_sig_bt[i] == T_ARRAY) {
1207 map->set_oop(VMRegImpl::stack2reg(slot));;
1208 }
1209 } else {
1210 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1211 }
1212 }
1213 }
1214 // Save or restore single word registers
1215 for ( int i = 0; i < total_in_args; i++) {
1216 if (in_regs[i].first()->is_Register()) {
1217 int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
1218 int offset = slot * VMRegImpl::stack_slot_size;
1219 assert(handle_index <= stack_slots, "overflow");
1220
1221 // Value is in an input register pass we must flush it to the stack
1222 const Register reg = in_regs[i].first()->as_Register();
1223 switch (in_sig_bt[i]) {
1224 case T_BOOLEAN:
1225 case T_CHAR:
1226 case T_BYTE:
1227 case T_SHORT:
1228 case T_INT:
1229 if (map != NULL) {
1230 __ movl(Address(rsp, offset), reg);
1231 } else {
1232 __ movl(reg, Address(rsp, offset));
1233 }
1234 break;
1235 case T_ARRAY:
1236 case T_LONG:
1237 // handled above
1238 break;
1239 case T_OBJECT:
1240 default: ShouldNotReachHere();
1241 }
1242 } else if (in_regs[i].first()->is_XMMRegister()) {
1243 if (in_sig_bt[i] == T_FLOAT) {
1244 int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
1245 int offset = slot * VMRegImpl::stack_slot_size;
1246 assert(handle_index <= stack_slots, "overflow");
1247 if (map != NULL) {
1248 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1249 } else {
1250 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1251 }
1252 }
1253 } else if (in_regs[i].first()->is_stack()) {
1254 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1255 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1256 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1257 }
1258 }
1259 }
1260 }
1261
1262
1263 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1264 // keeps a new JNI critical region from starting until a GC has been
1265 // forced. Save down any oops in registers and describe them in an
1266 // OopMap.
1267 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1268 int stack_slots,
1269 int total_c_args,
1270 int total_in_args,
1271 int arg_save_area,
1272 OopMapSet* oop_maps,
1273 VMRegPair* in_regs,
1274 BasicType* in_sig_bt) {
1275 __ block_comment("check GC_locker::needs_gc");
1276 Label cont;
1277 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
1278 __ jcc(Assembler::equal, cont);
1279
1280 // Save down any incoming oops and call into the runtime to halt for a GC
1281
1282 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1283 save_or_restore_arguments(masm, stack_slots, total_in_args,
1284 arg_save_area, map, in_regs, in_sig_bt);
1285
1286 address the_pc = __ pc();
1287 oop_maps->add_gc_map( __ offset(), map);
1288 __ set_last_Java_frame(rsp, noreg, the_pc);
1289
1290 __ block_comment("block_for_jni_critical");
1291 __ movptr(c_rarg0, r15_thread);
1292 __ mov(r12, rsp); // remember sp
1293 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1294 __ andptr(rsp, -16); // align stack as required by ABI
1295 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1296 __ mov(rsp, r12); // restore sp
1297 __ reinit_heapbase();
1298
1299 __ reset_last_Java_frame(false, true);
1300
1301 save_or_restore_arguments(masm, stack_slots, total_in_args,
1302 arg_save_area, NULL, in_regs, in_sig_bt);
1303
1304 __ bind(cont);
1305 #ifdef ASSERT
1306 if (StressCriticalJNINatives) {
1307 // Stress register saving
1308 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1309 save_or_restore_arguments(masm, stack_slots, total_in_args,
1310 arg_save_area, map, in_regs, in_sig_bt);
1311 // Destroy argument registers
1312 for (int i = 0; i < total_in_args - 1; i++) {
1313 if (in_regs[i].first()->is_Register()) {
1314 const Register reg = in_regs[i].first()->as_Register();
1315 __ xorptr(reg, reg);
1316 } else if (in_regs[i].first()->is_XMMRegister()) {
1317 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1318 } else if (in_regs[i].first()->is_FloatRegister()) {
1319 ShouldNotReachHere();
1320 } else if (in_regs[i].first()->is_stack()) {
1321 // Nothing to do
1322 } else {
1323 ShouldNotReachHere();
1324 }
1325 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1326 i++;
1327 }
1328 }
1329
1330 save_or_restore_arguments(masm, stack_slots, total_in_args,
1331 arg_save_area, NULL, in_regs, in_sig_bt);
1332 }
1333 #endif
1334 }
1335
1336 // Unpack an array argument into a pointer to the body and the length
1337 // if the array is non-null, otherwise pass 0 for both.
1338 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1339 Register tmp_reg = rax;
1340 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1341 "possible collision");
1342 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1343 "possible collision");
1344
1345 // Pass the length, ptr pair
1346 Label is_null, done;
1347 VMRegPair tmp;
1348 tmp.set_ptr(tmp_reg->as_VMReg());
1349 if (reg.first()->is_stack()) {
1350 // Load the arg up from the stack
1351 move_ptr(masm, reg, tmp);
1352 reg = tmp;
1353 }
1354 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1355 __ jccb(Assembler::equal, is_null);
1356 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1357 move_ptr(masm, tmp, body_arg);
1358 // load the length relative to the body.
1359 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1360 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1361 move32_64(masm, tmp, length_arg);
1362 __ jmpb(done);
1363 __ bind(is_null);
1364 // Pass zeros
1365 __ xorptr(tmp_reg, tmp_reg);
1366 move_ptr(masm, tmp, body_arg);
1367 move32_64(masm, tmp, length_arg);
1368 __ bind(done);
1369 }
1370
1371 // ---------------------------------------------------------------------------
1372 // Generate a native wrapper for a given method. The method takes arguments
1373 // in the Java compiled code convention, marshals them to the native
1374 // convention (handlizes oops, etc), transitions to native, makes the call,
1375 // returns to java state (possibly blocking), unhandlizes any result and
1376 // returns.
1377 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
1378 methodHandle method,
1379 int compile_id,
1380 int total_in_args,
1381 int comp_args_on_stack,
1382 BasicType *in_sig_bt,
1383 VMRegPair *in_regs,
1384 BasicType ret_type) {
1385 bool is_critical_native = true;
1386 address native_func = method->critical_native_function();
1387 if (native_func == NULL) {
1388 native_func = method->native_function();
1389 is_critical_native = false;
1390 }
1391 assert(native_func != NULL, "must have function");
1392
1393 // An OopMap for lock (and class if static)
1394 OopMapSet *oop_maps = new OopMapSet();
1395 intptr_t start = (intptr_t)__ pc();
1396
1397 // We have received a description of where all the java arg are located
1398 // on entry to the wrapper. We need to convert these args to where
1399 // the jni function will expect them. To figure out where they go
1400 // we convert the java signature to a C signature by inserting
1401 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1402
1403 int total_c_args = total_in_args;
1404 if (!is_critical_native) {
1405 total_c_args += 1;
1406 if (method->is_static()) {
1407 total_c_args++;
1408 }
1409 } else {
1410 for (int i = 0; i < total_in_args; i++) {
1411 if (in_sig_bt[i] == T_ARRAY) {
1412 total_c_args++;
1413 }
1414 }
1415 }
1416
1417 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1418 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1419 BasicType* in_elem_bt = NULL;
1420
1421 int argc = 0;
1422 if (!is_critical_native) {
1423 out_sig_bt[argc++] = T_ADDRESS;
1424 if (method->is_static()) {
1425 out_sig_bt[argc++] = T_OBJECT;
1426 }
1427
1428 for (int i = 0; i < total_in_args ; i++ ) {
1429 out_sig_bt[argc++] = in_sig_bt[i];
1430 }
1431 } else {
1432 Thread* THREAD = Thread::current();
1433 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1434 SignatureStream ss(method->signature());
1435 for (int i = 0; i < total_in_args ; i++ ) {
1436 if (in_sig_bt[i] == T_ARRAY) {
1437 // Arrays are passed as int, elem* pair
1438 out_sig_bt[argc++] = T_INT;
1439 out_sig_bt[argc++] = T_ADDRESS;
1440 Symbol* atype = ss.as_symbol(CHECK_NULL);
1441 const char* at = atype->as_C_string();
1442 if (strlen(at) == 2) {
1443 assert(at[0] == '[', "must be");
1444 switch (at[1]) {
1445 case 'B': in_elem_bt[i] = T_BYTE; break;
1446 case 'C': in_elem_bt[i] = T_CHAR; break;
1447 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1448 case 'F': in_elem_bt[i] = T_FLOAT; break;
1449 case 'I': in_elem_bt[i] = T_INT; break;
1450 case 'J': in_elem_bt[i] = T_LONG; break;
1451 case 'S': in_elem_bt[i] = T_SHORT; break;
1452 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1453 default: ShouldNotReachHere();
1454 }
1455 }
1456 } else {
1457 out_sig_bt[argc++] = in_sig_bt[i];
1458 in_elem_bt[i] = T_VOID;
1459 }
1460 if (in_sig_bt[i] != T_VOID) {
1461 assert(in_sig_bt[i] == ss.type(), "must match");
1462 ss.next();
1463 }
1464 }
1465 }
1466
1467 // Now figure out where the args must be stored and how much stack space
1468 // they require.
1469 int out_arg_slots;
1470 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1471
1472 // Compute framesize for the wrapper. We need to handlize all oops in
1473 // incoming registers
1474
1475 // Calculate the total number of stack slots we will need.
1476
1477 // First count the abi requirement plus all of the outgoing args
1478 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1479
1480 // Now the space for the inbound oop handle area
1481 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
1482 if (is_critical_native) {
1483 // Critical natives may have to call out so they need a save area
1484 // for register arguments.
1485 int double_slots = 0;
1486 int single_slots = 0;
1487 for ( int i = 0; i < total_in_args; i++) {
1488 if (in_regs[i].first()->is_Register()) {
1489 const Register reg = in_regs[i].first()->as_Register();
1490 switch (in_sig_bt[i]) {
1491 case T_ARRAY:
1492 case T_BOOLEAN:
1493 case T_BYTE:
1494 case T_SHORT:
1495 case T_CHAR:
1496 case T_INT: single_slots++; break;
1497 case T_LONG: double_slots++; break;
1498 default: ShouldNotReachHere();
1499 }
1500 } else if (in_regs[i].first()->is_XMMRegister()) {
1501 switch (in_sig_bt[i]) {
1502 case T_FLOAT: single_slots++; break;
1503 case T_DOUBLE: double_slots++; break;
1504 default: ShouldNotReachHere();
1505 }
1506 } else if (in_regs[i].first()->is_FloatRegister()) {
1507 ShouldNotReachHere();
1508 }
1509 }
1510 total_save_slots = double_slots * 2 + single_slots;
1511 // align the save area
1512 if (double_slots != 0) {
1513 stack_slots = round_to(stack_slots, 2);
1514 }
1515 }
1516
1517 int oop_handle_offset = stack_slots;
1518 stack_slots += total_save_slots;
1519
1520 // Now any space we need for handlizing a klass if static method
1521
1522 int klass_slot_offset = 0;
1523 int klass_offset = -1;
1524 int lock_slot_offset = 0;
1525 bool is_static = false;
1526
1527 if (method->is_static()) {
1528 klass_slot_offset = stack_slots;
1529 stack_slots += VMRegImpl::slots_per_word;
1530 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1531 is_static = true;
1532 }
1533
1534 // Plus a lock if needed
1535
1536 if (method->is_synchronized()) {
1537 lock_slot_offset = stack_slots;
1538 stack_slots += VMRegImpl::slots_per_word;
1539 }
1540
1541 // Now a place (+2) to save return values or temp during shuffling
1542 // + 4 for return address (which we own) and saved rbp
1543 stack_slots += 6;
1544
1545 // Ok The space we have allocated will look like:
1546 //
1547 //
1548 // FP-> | |
1549 // |---------------------|
1550 // | 2 slots for moves |
1551 // |---------------------|
1552 // | lock box (if sync) |
1553 // |---------------------| <- lock_slot_offset
1554 // | klass (if static) |
1555 // |---------------------| <- klass_slot_offset
1556 // | oopHandle area |
1557 // |---------------------| <- oop_handle_offset (6 java arg registers)
1558 // | outbound memory |
1559 // | based arguments |
1560 // | |
1561 // |---------------------|
1562 // | |
1563 // SP-> | out_preserved_slots |
1564 //
1565 //
1566
1567
1568 // Now compute actual number of stack words we need rounding to make
1569 // stack properly aligned.
1570 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1571
1572 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1573
1574 // First thing make an ic check to see if we should even be here
1575
1576 // We are free to use all registers as temps without saving them and
1577 // restoring them except rbp. rbp is the only callee save register
1578 // as far as the interpreter and the compiler(s) are concerned.
1579
1580
1581 const Register ic_reg = rax;
1582 const Register receiver = j_rarg0;
1583
1584 Label hit;
1585 Label exception_pending;
1586
1587 assert_different_registers(ic_reg, receiver, rscratch1);
1588 __ verify_oop(receiver);
1589 __ load_klass(rscratch1, receiver);
1590 __ cmpq(ic_reg, rscratch1);
1591 __ jcc(Assembler::equal, hit);
1592
1593 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1594
1595 // Verified entry point must be aligned
1596 __ align(8);
1597
1598 __ bind(hit);
1599
1600 int vep_offset = ((intptr_t)__ pc()) - start;
1601
1602 // The instruction at the verified entry point must be 5 bytes or longer
1603 // because it can be patched on the fly by make_non_entrant. The stack bang
1604 // instruction fits that requirement.
1605
1606 // Generate stack overflow check
1607
1608 if (UseStackBanging) {
1609 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1610 } else {
1611 // need a 5 byte instruction to allow MT safe patching to non-entrant
1612 __ fat_nop();
1613 }
1614
1615 // Generate a new frame for the wrapper.
1616 __ enter();
1617 // -2 because return address is already present and so is saved rbp
1618 __ subptr(rsp, stack_size - 2*wordSize);
1619
1620 // Frame is now completed as far as size and linkage.
1621 int frame_complete = ((intptr_t)__ pc()) - start;
1622
1623 #ifdef ASSERT
1624 {
1625 Label L;
1626 __ mov(rax, rsp);
1627 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
1628 __ cmpptr(rax, rsp);
1629 __ jcc(Assembler::equal, L);
1630 __ stop("improperly aligned stack");
1631 __ bind(L);
1632 }
1633 #endif /* ASSERT */
1634
1635
1636 // We use r14 as the oop handle for the receiver/klass
1637 // It is callee save so it survives the call to native
1638
1639 const Register oop_handle_reg = r14;
1640
1641 if (is_critical_native) {
1642 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
1643 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
1644 }
1645
1646 //
1647 // We immediately shuffle the arguments so that any vm call we have to
1648 // make from here on out (sync slow path, jvmti, etc.) we will have
1649 // captured the oops from our caller and have a valid oopMap for
1650 // them.
1651
1652 // -----------------
1653 // The Grand Shuffle
1654
1655 // The Java calling convention is either equal (linux) or denser (win64) than the
1656 // c calling convention. However the because of the jni_env argument the c calling
1657 // convention always has at least one more (and two for static) arguments than Java.
1658 // Therefore if we move the args from java -> c backwards then we will never have
1659 // a register->register conflict and we don't have to build a dependency graph
1660 // and figure out how to break any cycles.
1661 //
1662
1663 // Record esp-based slot for receiver on stack for non-static methods
1664 int receiver_offset = -1;
1665
1666 // This is a trick. We double the stack slots so we can claim
1667 // the oops in the caller's frame. Since we are sure to have
1668 // more args than the caller doubling is enough to make
1669 // sure we can capture all the incoming oop args from the
1670 // caller.
1671 //
1672 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1673
1674 // Mark location of rbp (someday)
1675 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
1676
1677 // Use eax, ebx as temporaries during any memory-memory moves we have to do
1678 // All inbound args are referenced based on rbp and all outbound args via rsp.
1679
1680
1681 #ifdef ASSERT
1682 bool reg_destroyed[RegisterImpl::number_of_registers];
1683 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
1684 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
1685 reg_destroyed[r] = false;
1686 }
1687 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
1688 freg_destroyed[f] = false;
1689 }
1690
1691 #endif /* ASSERT */
1692
1693 if (is_critical_native) {
1694 // The mapping of Java and C arguments passed in registers are
1695 // rotated by one, which helps when passing arguments to regular
1696 // Java method but for critical natives that creates a cycle which
1697 // can cause arguments to be killed before they are used. Break
1698 // the cycle by moving the first argument into a temporary
1699 // register.
1700 for (int i = 0; i < total_c_args; i++) {
1701 if (in_regs[i].first()->is_Register() &&
1702 in_regs[i].first()->as_Register() == rdi) {
1703 __ mov(rbx, rdi);
1704 in_regs[i].set1(rbx->as_VMReg());
1705 }
1706 }
1707 }
1708
1709 // This may iterate in two different directions depending on the
1710 // kind of native it is. The reason is that for regular JNI natives
1711 // the incoming and outgoing registers are offset upwards and for
1712 // critical natives they are offset down.
1713 int c_arg = total_c_args - 1;
1714 int stride = -1;
1715 int init = total_in_args - 1;
1716 if (is_critical_native) {
1717 // stride forwards
1718 c_arg = 0;
1719 stride = 1;
1720 init = 0;
1721 }
1722 for (int i = init, count = 0; count < total_in_args; i += stride, c_arg += stride, count++ ) {
1723 #ifdef ASSERT
1724 if (in_regs[i].first()->is_Register()) {
1725 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
1726 } else if (in_regs[i].first()->is_XMMRegister()) {
1727 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
1728 }
1729 if (out_regs[c_arg].first()->is_Register()) {
1730 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1731 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1732 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1733 }
1734 #endif /* ASSERT */
1735 switch (in_sig_bt[i]) {
1736 case T_ARRAY:
1737 if (is_critical_native) {
1738 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
1739 c_arg++;
1740 #ifdef ASSERT
1741 if (out_regs[c_arg].first()->is_Register()) {
1742 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1743 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1744 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1745 }
1746 #endif
1747 break;
1748 }
1749 case T_OBJECT:
1750 assert(!is_critical_native, "no oop arguments");
1751 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1752 ((i == 0) && (!is_static)),
1753 &receiver_offset);
1754 break;
1755 case T_VOID:
1756 break;
1757
1758 case T_FLOAT:
1759 float_move(masm, in_regs[i], out_regs[c_arg]);
1760 break;
1761
1762 case T_DOUBLE:
1763 assert( i + 1 < total_in_args &&
1764 in_sig_bt[i + 1] == T_VOID &&
1765 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1766 double_move(masm, in_regs[i], out_regs[c_arg]);
1767 break;
1768
1769 case T_LONG :
1770 long_move(masm, in_regs[i], out_regs[c_arg]);
1771 break;
1772
1773 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
1774
1775 default:
1776 move32_64(masm, in_regs[i], out_regs[c_arg]);
1777 }
1778 }
1779
1780 // point c_arg at the first arg that is already loaded in case we
1781 // need to spill before we call out
1782 c_arg++;
1783
1784 // Pre-load a static method's oop into r14. Used both by locking code and
1785 // the normal JNI call code.
1786 if (method->is_static() && !is_critical_native) {
1787
1788 // load oop into a register
1789 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
1790
1791 // Now handlize the static class mirror it's known not-null.
1792 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
1793 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
1794
1795 // Now get the handle
1796 __ lea(oop_handle_reg, Address(rsp, klass_offset));
1797 // store the klass handle as second argument
1798 __ movptr(c_rarg1, oop_handle_reg);
1799 // and protect the arg if we must spill
1800 c_arg--;
1801 }
1802
1803 // Change state to native (we save the return address in the thread, since it might not
1804 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
1805 // points into the right code segment. It does not have to be the correct return pc.
1806 // We use the same pc/oopMap repeatedly when we call out
1807
1808 intptr_t the_pc = (intptr_t) __ pc();
1809 oop_maps->add_gc_map(the_pc - start, map);
1810
1811 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
1812
1813
1814 // We have all of the arguments setup at this point. We must not touch any register
1815 // argument registers at this point (what if we save/restore them there are no oop?
1816
1817 {
1818 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1819 // protect the args we've loaded
1820 save_args(masm, total_c_args, c_arg, out_regs);
1821 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1822 __ call_VM_leaf(
1823 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
1824 r15_thread, c_rarg1);
1825 restore_args(masm, total_c_args, c_arg, out_regs);
1826 }
1827
1828 // RedefineClasses() tracing support for obsolete method entry
1829 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
1830 // protect the args we've loaded
1831 save_args(masm, total_c_args, c_arg, out_regs);
1832 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1833 __ call_VM_leaf(
1834 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
1835 r15_thread, c_rarg1);
1836 restore_args(masm, total_c_args, c_arg, out_regs);
1837 }
1838
1839 // Lock a synchronized method
1840
1841 // Register definitions used by locking and unlocking
1842
1843 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
1844 const Register obj_reg = rbx; // Will contain the oop
1845 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
1846 const Register old_hdr = r13; // value of old header at unlock time
1847
1848 Label slow_path_lock;
1849 Label lock_done;
1850
1851 if (method->is_synchronized()) {
1852 assert(!is_critical_native, "unhandled");
1853
1854
1855 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
1856
1857 // Get the handle (the 2nd argument)
1858 __ mov(oop_handle_reg, c_rarg1);
1859
1860 // Get address of the box
1861
1862 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1863
1864 // Load the oop from the handle
1865 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1866
1867 if (UseBiasedLocking) {
1868 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
1869 }
1870
1871 // Load immediate 1 into swap_reg %rax
1872 __ movl(swap_reg, 1);
1873
1874 // Load (object->mark() | 1) into swap_reg %rax
1875 __ orptr(swap_reg, Address(obj_reg, 0));
1876
1877 // Save (object->mark() | 1) into BasicLock's displaced header
1878 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1879
1880 if (os::is_MP()) {
1881 __ lock();
1882 }
1883
1884 // src -> dest iff dest == rax else rax <- dest
1885 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
1886 __ jcc(Assembler::equal, lock_done);
1887
1888 // Hmm should this move to the slow path code area???
1889
1890 // Test if the oopMark is an obvious stack pointer, i.e.,
1891 // 1) (mark & 3) == 0, and
1892 // 2) rsp <= mark < mark + os::pagesize()
1893 // These 3 tests can be done by evaluating the following
1894 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
1895 // assuming both stack pointer and pagesize have their
1896 // least significant 2 bits clear.
1897 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
1898
1899 __ subptr(swap_reg, rsp);
1900 __ andptr(swap_reg, 3 - os::vm_page_size());
1901
1902 // Save the test result, for recursive case, the result is zero
1903 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1904 __ jcc(Assembler::notEqual, slow_path_lock);
1905
1906 // Slow path will re-enter here
1907
1908 __ bind(lock_done);
1909 }
1910
1911
1912 // Finally just about ready to make the JNI call
1913
1914
1915 // get JNIEnv* which is first argument to native
1916 if (!is_critical_native) {
1917 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
1918 }
1919
1920 // Now set thread in native
1921 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
1922
1923 __ call(RuntimeAddress(native_func));
1924
1925 // Either restore the MXCSR register after returning from the JNI Call
1926 // or verify that it wasn't changed.
1927 if (RestoreMXCSROnJNICalls) {
1928 __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
1929
1930 }
1931 else if (CheckJNICalls ) {
1932 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
1933 }
1934
1935
1936 // Unpack native results.
1937 switch (ret_type) {
1938 case T_BOOLEAN: __ c2bool(rax); break;
1939 case T_CHAR : __ movzwl(rax, rax); break;
1940 case T_BYTE : __ sign_extend_byte (rax); break;
1941 case T_SHORT : __ sign_extend_short(rax); break;
1942 case T_INT : /* nothing to do */ break;
1943 case T_DOUBLE :
1944 case T_FLOAT :
1945 // Result is in xmm0 we'll save as needed
1946 break;
1947 case T_ARRAY: // Really a handle
1948 case T_OBJECT: // Really a handle
1949 break; // can't de-handlize until after safepoint check
1950 case T_VOID: break;
1951 case T_LONG: break;
1952 default : ShouldNotReachHere();
1953 }
1954
1955 // Switch thread to "native transition" state before reading the synchronization state.
1956 // This additional state is necessary because reading and testing the synchronization
1957 // state is not atomic w.r.t. GC, as this scenario demonstrates:
1958 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
1959 // VM thread changes sync state to synchronizing and suspends threads for GC.
1960 // Thread A is resumed to finish this native method, but doesn't block here since it
1961 // didn't see any synchronization is progress, and escapes.
1962 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
1963
1964 if(os::is_MP()) {
1965 if (UseMembar) {
1966 // Force this write out before the read below
1967 __ membar(Assembler::Membar_mask_bits(
1968 Assembler::LoadLoad | Assembler::LoadStore |
1969 Assembler::StoreLoad | Assembler::StoreStore));
1970 } else {
1971 // Write serialization page so VM thread can do a pseudo remote membar.
1972 // We use the current thread pointer to calculate a thread specific
1973 // offset to write to within the page. This minimizes bus traffic
1974 // due to cache line collision.
1975 __ serialize_memory(r15_thread, rcx);
1976 }
1977 }
1978
1979 Label after_transition;
1980
1981 // check for safepoint operation in progress and/or pending suspend requests
1982 {
1983 Label Continue;
1984
1985 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
1986 SafepointSynchronize::_not_synchronized);
1987
1988 Label L;
1989 __ jcc(Assembler::notEqual, L);
1990 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
1991 __ jcc(Assembler::equal, Continue);
1992 __ bind(L);
1993
1994 // Don't use call_VM as it will see a possible pending exception and forward it
1995 // and never return here preventing us from clearing _last_native_pc down below.
1996 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
1997 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
1998 // by hand.
1999 //
2000 save_native_result(masm, ret_type, stack_slots);
2001 __ mov(c_rarg0, r15_thread);
2002 __ mov(r12, rsp); // remember sp
2003 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2004 __ andptr(rsp, -16); // align stack as required by ABI
2005 if (!is_critical_native) {
2006 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2007 } else {
2008 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2009 }
2010 __ mov(rsp, r12); // restore sp
2011 __ reinit_heapbase();
2012 // Restore any method result value
2013 restore_native_result(masm, ret_type, stack_slots);
2014
2015 if (is_critical_native) {
2016 // The call above performed the transition to thread_in_Java so
2017 // skip the transition logic below.
2018 __ jmpb(after_transition);
2019 }
2020
2021 __ bind(Continue);
2022 }
2023
2024 // change thread state
2025 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2026 __ bind(after_transition);
2027
2028 Label reguard;
2029 Label reguard_done;
2030 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
2031 __ jcc(Assembler::equal, reguard);
2032 __ bind(reguard_done);
2033
2034 // native result if any is live
2035
2036 // Unlock
2037 Label unlock_done;
2038 Label slow_path_unlock;
2039 if (method->is_synchronized()) {
2040
2041 // Get locked oop from the handle we passed to jni
2042 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2043
2044 Label done;
2045
2046 if (UseBiasedLocking) {
2047 __ biased_locking_exit(obj_reg, old_hdr, done);
2048 }
2049
2050 // Simple recursive lock?
2051
2052 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2053 __ jcc(Assembler::equal, done);
2054
2055 // Must save rax if if it is live now because cmpxchg must use it
2056 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2057 save_native_result(masm, ret_type, stack_slots);
2058 }
2059
2060
2061 // get address of the stack lock
2062 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2063 // get old displaced header
2064 __ movptr(old_hdr, Address(rax, 0));
2065
2066 // Atomic swap old header if oop still contains the stack lock
2067 if (os::is_MP()) {
2068 __ lock();
2069 }
2070 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
2071 __ jcc(Assembler::notEqual, slow_path_unlock);
2072
2073 // slow path re-enters here
2074 __ bind(unlock_done);
2075 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2076 restore_native_result(masm, ret_type, stack_slots);
2077 }
2078
2079 __ bind(done);
2080
2081 }
2082 {
2083 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2084 save_native_result(masm, ret_type, stack_slots);
2085 __ movoop(c_rarg1, JNIHandles::make_local(method()));
2086 __ call_VM_leaf(
2087 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2088 r15_thread, c_rarg1);
2089 restore_native_result(masm, ret_type, stack_slots);
2090 }
2091
2092 __ reset_last_Java_frame(false, true);
2093
2094 // Unpack oop result
2095 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2096 Label L;
2097 __ testptr(rax, rax);
2098 __ jcc(Assembler::zero, L);
2099 __ movptr(rax, Address(rax, 0));
2100 __ bind(L);
2101 __ verify_oop(rax);
2102 }
2103
2104 if (!is_critical_native) {
2105 // reset handle block
2106 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2107 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2108 }
2109
2110 // pop our frame
2111
2112 __ leave();
2113
2114 if (!is_critical_native) {
2115 // Any exception pending?
2116 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2117 __ jcc(Assembler::notEqual, exception_pending);
2118 }
2119
2120 // Return
2121
2122 __ ret(0);
2123
2124 // Unexpected paths are out of line and go here
2125
2126 if (!is_critical_native) {
2127 // forward the exception
2128 __ bind(exception_pending);
2129
2130 // and forward the exception
2131 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2132 }
2133
2134 // Slow path locking & unlocking
2135 if (method->is_synchronized()) {
2136
2137 // BEGIN Slow path lock
2138 __ bind(slow_path_lock);
2139
2140 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2141 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2142
2143 // protect the args we've loaded
2144 save_args(masm, total_c_args, c_arg, out_regs);
2145
2146 __ mov(c_rarg0, obj_reg);
2147 __ mov(c_rarg1, lock_reg);
2148 __ mov(c_rarg2, r15_thread);
2149
2150 // Not a leaf but we have last_Java_frame setup as we want
2151 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2152 restore_args(masm, total_c_args, c_arg, out_regs);
2153
2154 #ifdef ASSERT
2155 { Label L;
2156 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2157 __ jcc(Assembler::equal, L);
2158 __ stop("no pending exception allowed on exit from monitorenter");
2159 __ bind(L);
2160 }
2161 #endif
2162 __ jmp(lock_done);
2163
2164 // END Slow path lock
2165
2166 // BEGIN Slow path unlock
2167 __ bind(slow_path_unlock);
2168
2169 // If we haven't already saved the native result we must save it now as xmm registers
2170 // are still exposed.
2171
2172 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2173 save_native_result(masm, ret_type, stack_slots);
2174 }
2175
2176 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2177
2178 __ mov(c_rarg0, obj_reg);
2179 __ mov(r12, rsp); // remember sp
2180 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2181 __ andptr(rsp, -16); // align stack as required by ABI
2182
2183 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2184 // NOTE that obj_reg == rbx currently
2185 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2186 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2187
2188 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2189 __ mov(rsp, r12); // restore sp
2190 __ reinit_heapbase();
2191 #ifdef ASSERT
2192 {
2193 Label L;
2194 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2195 __ jcc(Assembler::equal, L);
2196 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2197 __ bind(L);
2198 }
2199 #endif /* ASSERT */
2200
2201 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2202
2203 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2204 restore_native_result(masm, ret_type, stack_slots);
2205 }
2206 __ jmp(unlock_done);
2207
2208 // END Slow path unlock
2209
2210 } // synchronized
2211
2212 // SLOW PATH Reguard the stack if needed
2213
2214 __ bind(reguard);
2215 save_native_result(masm, ret_type, stack_slots);
2216 __ mov(r12, rsp); // remember sp
2217 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2218 __ andptr(rsp, -16); // align stack as required by ABI
2219 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2220 __ mov(rsp, r12); // restore sp
2221 __ reinit_heapbase();
2222 restore_native_result(masm, ret_type, stack_slots);
2223 // and continue
2224 __ jmp(reguard_done);
2225
2226
2227
2228 __ flush();
2229
2230 nmethod *nm = nmethod::new_native_nmethod(method,
2231 compile_id,
2232 masm->code(),
2233 vep_offset,
2234 frame_complete,
2235 stack_slots / VMRegImpl::slots_per_word,
2236 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2237 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2238 oop_maps);
2239
2240 if (is_critical_native) {
2241 nm->set_lazy_critical_native(true);
2242 }
2243
2244 return nm;
2245
2246 }
2247
2248 #ifdef HAVE_DTRACE_H
2249 // ---------------------------------------------------------------------------
2250 // Generate a dtrace nmethod for a given signature. The method takes arguments
2251 // in the Java compiled code convention, marshals them to the native
2252 // abi and then leaves nops at the position you would expect to call a native
2253 // function. When the probe is enabled the nops are replaced with a trap
2254 // instruction that dtrace inserts and the trace will cause a notification
2255 // to dtrace.
2256 //
2257 // The probes are only able to take primitive types and java/lang/String as
2258 // arguments. No other java types are allowed. Strings are converted to utf8
2259 // strings so that from dtrace point of view java strings are converted to C
2260 // strings. There is an arbitrary fixed limit on the total space that a method
2261 // can use for converting the strings. (256 chars per string in the signature).
2262 // So any java string larger then this is truncated.
2263
2264 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2265 static bool offsets_initialized = false;
2266
2267
2268 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
2269 methodHandle method) {
2270
2271
2272 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2273 // be single threaded in this method.
2274 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2275
2276 if (!offsets_initialized) {
2277 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
2278 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
2279 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
2280 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
2281 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
2282 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
2283
2284 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
2285 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
2286 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
2287 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
2288 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
2289 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
2290 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
2291 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
2292
2293 offsets_initialized = true;
2294 }
2295 // Fill in the signature array, for the calling-convention call.
2296 int total_args_passed = method->size_of_parameters();
2297
2298 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2299 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2300
2301 // The signature we are going to use for the trap that dtrace will see
2302 // java/lang/String is converted. We drop "this" and any other object
2303 // is converted to NULL. (A one-slot java/lang/Long object reference
2304 // is converted to a two-slot long, which is why we double the allocation).
2305 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2306 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2307
2308 int i=0;
2309 int total_strings = 0;
2310 int first_arg_to_pass = 0;
2311 int total_c_args = 0;
2312
2313 // Skip the receiver as dtrace doesn't want to see it
2314 if( !method->is_static() ) {
2315 in_sig_bt[i++] = T_OBJECT;
2316 first_arg_to_pass = 1;
2317 }
2318
2319 // We need to convert the java args to where a native (non-jni) function
2320 // would expect them. To figure out where they go we convert the java
2321 // signature to a C signature.
2322
2323 SignatureStream ss(method->signature());
2324 for ( ; !ss.at_return_type(); ss.next()) {
2325 BasicType bt = ss.type();
2326 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2327 out_sig_bt[total_c_args++] = bt;
2328 if( bt == T_OBJECT) {
2329 Symbol* s = ss.as_symbol_or_null(); // symbol is created
2330 if (s == vmSymbols::java_lang_String()) {
2331 total_strings++;
2332 out_sig_bt[total_c_args-1] = T_ADDRESS;
2333 } else if (s == vmSymbols::java_lang_Boolean() ||
2334 s == vmSymbols::java_lang_Character() ||
2335 s == vmSymbols::java_lang_Byte() ||
2336 s == vmSymbols::java_lang_Short() ||
2337 s == vmSymbols::java_lang_Integer() ||
2338 s == vmSymbols::java_lang_Float()) {
2339 out_sig_bt[total_c_args-1] = T_INT;
2340 } else if (s == vmSymbols::java_lang_Long() ||
2341 s == vmSymbols::java_lang_Double()) {
2342 out_sig_bt[total_c_args-1] = T_LONG;
2343 out_sig_bt[total_c_args++] = T_VOID;
2344 }
2345 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2346 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2347 // We convert double to long
2348 out_sig_bt[total_c_args-1] = T_LONG;
2349 out_sig_bt[total_c_args++] = T_VOID;
2350 } else if ( bt == T_FLOAT) {
2351 // We convert float to int
2352 out_sig_bt[total_c_args-1] = T_INT;
2353 }
2354 }
2355
2356 assert(i==total_args_passed, "validly parsed signature");
2357
2358 // Now get the compiled-Java layout as input arguments
2359 int comp_args_on_stack;
2360 comp_args_on_stack = SharedRuntime::java_calling_convention(
2361 in_sig_bt, in_regs, total_args_passed, false);
2362
2363 // Now figure out where the args must be stored and how much stack space
2364 // they require (neglecting out_preserve_stack_slots but space for storing
2365 // the 1st six register arguments). It's weird see int_stk_helper.
2366
2367 int out_arg_slots;
2368 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2369
2370 // Calculate the total number of stack slots we will need.
2371
2372 // First count the abi requirement plus all of the outgoing args
2373 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2374
2375 // Now space for the string(s) we must convert
2376 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2377 for (i = 0; i < total_strings ; i++) {
2378 string_locs[i] = stack_slots;
2379 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2380 }
2381
2382 // Plus the temps we might need to juggle register args
2383 // regs take two slots each
2384 stack_slots += (Argument::n_int_register_parameters_c +
2385 Argument::n_float_register_parameters_c) * 2;
2386
2387
2388 // + 4 for return address (which we own) and saved rbp,
2389
2390 stack_slots += 4;
2391
2392 // Ok The space we have allocated will look like:
2393 //
2394 //
2395 // FP-> | |
2396 // |---------------------|
2397 // | string[n] |
2398 // |---------------------| <- string_locs[n]
2399 // | string[n-1] |
2400 // |---------------------| <- string_locs[n-1]
2401 // | ... |
2402 // | ... |
2403 // |---------------------| <- string_locs[1]
2404 // | string[0] |
2405 // |---------------------| <- string_locs[0]
2406 // | outbound memory |
2407 // | based arguments |
2408 // | |
2409 // |---------------------|
2410 // | |
2411 // SP-> | out_preserved_slots |
2412 //
2413 //
2414
2415 // Now compute actual number of stack words we need rounding to make
2416 // stack properly aligned.
2417 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2418
2419 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2420
2421 intptr_t start = (intptr_t)__ pc();
2422
2423 // First thing make an ic check to see if we should even be here
2424
2425 // We are free to use all registers as temps without saving them and
2426 // restoring them except rbp. rbp, is the only callee save register
2427 // as far as the interpreter and the compiler(s) are concerned.
2428
2429 const Register ic_reg = rax;
2430 const Register receiver = rcx;
2431 Label hit;
2432 Label exception_pending;
2433
2434
2435 __ verify_oop(receiver);
2436 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2437 __ jcc(Assembler::equal, hit);
2438
2439 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2440
2441 // verified entry must be aligned for code patching.
2442 // and the first 5 bytes must be in the same cache line
2443 // if we align at 8 then we will be sure 5 bytes are in the same line
2444 __ align(8);
2445
2446 __ bind(hit);
2447
2448 int vep_offset = ((intptr_t)__ pc()) - start;
2449
2450
2451 // The instruction at the verified entry point must be 5 bytes or longer
2452 // because it can be patched on the fly by make_non_entrant. The stack bang
2453 // instruction fits that requirement.
2454
2455 // Generate stack overflow check
2456
2457 if (UseStackBanging) {
2458 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2459 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2460 } else {
2461 __ movl(rax, stack_size);
2462 __ bang_stack_size(rax, rbx);
2463 }
2464 } else {
2465 // need a 5 byte instruction to allow MT safe patching to non-entrant
2466 __ fat_nop();
2467 }
2468
2469 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2470 "valid size for make_non_entrant");
2471
2472 // Generate a new frame for the wrapper.
2473 __ enter();
2474
2475 // -4 because return address is already present and so is saved rbp,
2476 if (stack_size - 2*wordSize != 0) {
2477 __ subq(rsp, stack_size - 2*wordSize);
2478 }
2479
2480 // Frame is now completed as far a size and linkage.
2481
2482 int frame_complete = ((intptr_t)__ pc()) - start;
2483
2484 int c_arg, j_arg;
2485
2486 // State of input register args
2487
2488 bool live[ConcreteRegisterImpl::number_of_registers];
2489
2490 live[j_rarg0->as_VMReg()->value()] = false;
2491 live[j_rarg1->as_VMReg()->value()] = false;
2492 live[j_rarg2->as_VMReg()->value()] = false;
2493 live[j_rarg3->as_VMReg()->value()] = false;
2494 live[j_rarg4->as_VMReg()->value()] = false;
2495 live[j_rarg5->as_VMReg()->value()] = false;
2496
2497 live[j_farg0->as_VMReg()->value()] = false;
2498 live[j_farg1->as_VMReg()->value()] = false;
2499 live[j_farg2->as_VMReg()->value()] = false;
2500 live[j_farg3->as_VMReg()->value()] = false;
2501 live[j_farg4->as_VMReg()->value()] = false;
2502 live[j_farg5->as_VMReg()->value()] = false;
2503 live[j_farg6->as_VMReg()->value()] = false;
2504 live[j_farg7->as_VMReg()->value()] = false;
2505
2506
2507 bool rax_is_zero = false;
2508
2509 // All args (except strings) destined for the stack are moved first
2510 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2511 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2512 VMRegPair src = in_regs[j_arg];
2513 VMRegPair dst = out_regs[c_arg];
2514
2515 // Get the real reg value or a dummy (rsp)
2516
2517 int src_reg = src.first()->is_reg() ?
2518 src.first()->value() :
2519 rsp->as_VMReg()->value();
2520
2521 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2522 (in_sig_bt[j_arg] == T_OBJECT &&
2523 out_sig_bt[c_arg] != T_INT &&
2524 out_sig_bt[c_arg] != T_ADDRESS &&
2525 out_sig_bt[c_arg] != T_LONG);
2526
2527 live[src_reg] = !useless;
2528
2529 if (dst.first()->is_stack()) {
2530
2531 // Even though a string arg in a register is still live after this loop
2532 // after the string conversion loop (next) it will be dead so we take
2533 // advantage of that now for simpler code to manage live.
2534
2535 live[src_reg] = false;
2536 switch (in_sig_bt[j_arg]) {
2537
2538 case T_ARRAY:
2539 case T_OBJECT:
2540 {
2541 Address stack_dst(rsp, reg2offset_out(dst.first()));
2542
2543 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2544 // need to unbox a one-word value
2545 Register in_reg = rax;
2546 if ( src.first()->is_reg() ) {
2547 in_reg = src.first()->as_Register();
2548 } else {
2549 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2550 rax_is_zero = false;
2551 }
2552 Label skipUnbox;
2553 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2554 (int32_t)NULL_WORD);
2555 __ testq(in_reg, in_reg);
2556 __ jcc(Assembler::zero, skipUnbox);
2557
2558 BasicType bt = out_sig_bt[c_arg];
2559 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2560 Address src1(in_reg, box_offset);
2561 if ( bt == T_LONG ) {
2562 __ movq(in_reg, src1);
2563 __ movq(stack_dst, in_reg);
2564 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2565 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2566 } else {
2567 __ movl(in_reg, src1);
2568 __ movl(stack_dst, in_reg);
2569 }
2570
2571 __ bind(skipUnbox);
2572 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2573 // Convert the arg to NULL
2574 if (!rax_is_zero) {
2575 __ xorq(rax, rax);
2576 rax_is_zero = true;
2577 }
2578 __ movq(stack_dst, rax);
2579 }
2580 }
2581 break;
2582
2583 case T_VOID:
2584 break;
2585
2586 case T_FLOAT:
2587 // This does the right thing since we know it is destined for the
2588 // stack
2589 float_move(masm, src, dst);
2590 break;
2591
2592 case T_DOUBLE:
2593 // This does the right thing since we know it is destined for the
2594 // stack
2595 double_move(masm, src, dst);
2596 break;
2597
2598 case T_LONG :
2599 long_move(masm, src, dst);
2600 break;
2601
2602 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2603
2604 default:
2605 move32_64(masm, src, dst);
2606 }
2607 }
2608
2609 }
2610
2611 // If we have any strings we must store any register based arg to the stack
2612 // This includes any still live xmm registers too.
2613
2614 int sid = 0;
2615
2616 if (total_strings > 0 ) {
2617 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2618 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2619 VMRegPair src = in_regs[j_arg];
2620 VMRegPair dst = out_regs[c_arg];
2621
2622 if (src.first()->is_reg()) {
2623 Address src_tmp(rbp, fp_offset[src.first()->value()]);
2624
2625 // string oops were left untouched by the previous loop even if the
2626 // eventual (converted) arg is destined for the stack so park them
2627 // away now (except for first)
2628
2629 if (out_sig_bt[c_arg] == T_ADDRESS) {
2630 Address utf8_addr = Address(
2631 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2632 if (sid != 1) {
2633 // The first string arg won't be killed until after the utf8
2634 // conversion
2635 __ movq(utf8_addr, src.first()->as_Register());
2636 }
2637 } else if (dst.first()->is_reg()) {
2638 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
2639
2640 // Convert the xmm register to an int and store it in the reserved
2641 // location for the eventual c register arg
2642 XMMRegister f = src.first()->as_XMMRegister();
2643 if (in_sig_bt[j_arg] == T_FLOAT) {
2644 __ movflt(src_tmp, f);
2645 } else {
2646 __ movdbl(src_tmp, f);
2647 }
2648 } else {
2649 // If the arg is an oop type we don't support don't bother to store
2650 // it remember string was handled above.
2651 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2652 (in_sig_bt[j_arg] == T_OBJECT &&
2653 out_sig_bt[c_arg] != T_INT &&
2654 out_sig_bt[c_arg] != T_LONG);
2655
2656 if (!useless) {
2657 __ movq(src_tmp, src.first()->as_Register());
2658 }
2659 }
2660 }
2661 }
2662 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2663 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2664 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2665 }
2666 }
2667
2668 // Now that the volatile registers are safe, convert all the strings
2669 sid = 0;
2670
2671 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2672 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2673 if (out_sig_bt[c_arg] == T_ADDRESS) {
2674 // It's a string
2675 Address utf8_addr = Address(
2676 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2677 // The first string we find might still be in the original java arg
2678 // register
2679
2680 VMReg src = in_regs[j_arg].first();
2681
2682 // We will need to eventually save the final argument to the trap
2683 // in the von-volatile location dedicated to src. This is the offset
2684 // from fp we will use.
2685 int src_off = src->is_reg() ?
2686 fp_offset[src->value()] : reg2offset_in(src);
2687
2688 // This is where the argument will eventually reside
2689 VMRegPair dst = out_regs[c_arg];
2690
2691 if (src->is_reg()) {
2692 if (sid == 1) {
2693 __ movq(c_rarg0, src->as_Register());
2694 } else {
2695 __ movq(c_rarg0, utf8_addr);
2696 }
2697 } else {
2698 // arg is still in the original location
2699 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
2700 }
2701 Label done, convert;
2702
2703 // see if the oop is NULL
2704 __ testq(c_rarg0, c_rarg0);
2705 __ jcc(Assembler::notEqual, convert);
2706
2707 if (dst.first()->is_reg()) {
2708 // Save the ptr to utf string in the origina src loc or the tmp
2709 // dedicated to it
2710 __ movq(Address(rbp, src_off), c_rarg0);
2711 } else {
2712 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
2713 }
2714 __ jmp(done);
2715
2716 __ bind(convert);
2717
2718 __ lea(c_rarg1, utf8_addr);
2719 if (dst.first()->is_reg()) {
2720 __ movq(Address(rbp, src_off), c_rarg1);
2721 } else {
2722 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
2723 }
2724 // And do the conversion
2725 __ call(RuntimeAddress(
2726 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
2727
2728 __ bind(done);
2729 }
2730 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2731 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2732 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2733 }
2734 }
2735 // The get_utf call killed all the c_arg registers
2736 live[c_rarg0->as_VMReg()->value()] = false;
2737 live[c_rarg1->as_VMReg()->value()] = false;
2738 live[c_rarg2->as_VMReg()->value()] = false;
2739 live[c_rarg3->as_VMReg()->value()] = false;
2740 live[c_rarg4->as_VMReg()->value()] = false;
2741 live[c_rarg5->as_VMReg()->value()] = false;
2742
2743 live[c_farg0->as_VMReg()->value()] = false;
2744 live[c_farg1->as_VMReg()->value()] = false;
2745 live[c_farg2->as_VMReg()->value()] = false;
2746 live[c_farg3->as_VMReg()->value()] = false;
2747 live[c_farg4->as_VMReg()->value()] = false;
2748 live[c_farg5->as_VMReg()->value()] = false;
2749 live[c_farg6->as_VMReg()->value()] = false;
2750 live[c_farg7->as_VMReg()->value()] = false;
2751 }
2752
2753 // Now we can finally move the register args to their desired locations
2754
2755 rax_is_zero = false;
2756
2757 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2758 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2759
2760 VMRegPair src = in_regs[j_arg];
2761 VMRegPair dst = out_regs[c_arg];
2762
2763 // Only need to look for args destined for the interger registers (since we
2764 // convert float/double args to look like int/long outbound)
2765 if (dst.first()->is_reg()) {
2766 Register r = dst.first()->as_Register();
2767
2768 // Check if the java arg is unsupported and thereofre useless
2769 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2770 (in_sig_bt[j_arg] == T_OBJECT &&
2771 out_sig_bt[c_arg] != T_INT &&
2772 out_sig_bt[c_arg] != T_ADDRESS &&
2773 out_sig_bt[c_arg] != T_LONG);
2774
2775
2776 // If we're going to kill an existing arg save it first
2777 if (live[dst.first()->value()]) {
2778 // you can't kill yourself
2779 if (src.first() != dst.first()) {
2780 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
2781 }
2782 }
2783 if (src.first()->is_reg()) {
2784 if (live[src.first()->value()] ) {
2785 if (in_sig_bt[j_arg] == T_FLOAT) {
2786 __ movdl(r, src.first()->as_XMMRegister());
2787 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
2788 __ movdq(r, src.first()->as_XMMRegister());
2789 } else if (r != src.first()->as_Register()) {
2790 if (!useless) {
2791 __ movq(r, src.first()->as_Register());
2792 }
2793 }
2794 } else {
2795 // If the arg is an oop type we don't support don't bother to store
2796 // it
2797 if (!useless) {
2798 if (in_sig_bt[j_arg] == T_DOUBLE ||
2799 in_sig_bt[j_arg] == T_LONG ||
2800 in_sig_bt[j_arg] == T_OBJECT ) {
2801 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
2802 } else {
2803 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
2804 }
2805 }
2806 }
2807 live[src.first()->value()] = false;
2808 } else if (!useless) {
2809 // full sized move even for int should be ok
2810 __ movq(r, Address(rbp, reg2offset_in(src.first())));
2811 }
2812
2813 // At this point r has the original java arg in the final location
2814 // (assuming it wasn't useless). If the java arg was an oop
2815 // we have a bit more to do
2816
2817 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
2818 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2819 // need to unbox a one-word value
2820 Label skip;
2821 __ testq(r, r);
2822 __ jcc(Assembler::equal, skip);
2823 BasicType bt = out_sig_bt[c_arg];
2824 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2825 Address src1(r, box_offset);
2826 if ( bt == T_LONG ) {
2827 __ movq(r, src1);
2828 } else {
2829 __ movl(r, src1);
2830 }
2831 __ bind(skip);
2832
2833 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2834 // Convert the arg to NULL
2835 __ xorq(r, r);
2836 }
2837 }
2838
2839 // dst can longer be holding an input value
2840 live[dst.first()->value()] = false;
2841 }
2842 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2843 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2844 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2845 }
2846 }
2847
2848
2849 // Ok now we are done. Need to place the nop that dtrace wants in order to
2850 // patch in the trap
2851 int patch_offset = ((intptr_t)__ pc()) - start;
2852
2853 __ nop();
2854
2855
2856 // Return
2857
2858 __ leave();
2859 __ ret(0);
2860
2861 __ flush();
2862
2863 nmethod *nm = nmethod::new_dtrace_nmethod(
2864 method, masm->code(), vep_offset, patch_offset, frame_complete,
2865 stack_slots / VMRegImpl::slots_per_word);
2866 return nm;
2867
2868 }
2869
2870 #endif // HAVE_DTRACE_H
2871
2872 // this function returns the adjust size (in number of words) to a c2i adapter
2873 // activation for use during deoptimization
2874 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2875 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
2876 }
2877
2878
2879 uint SharedRuntime::out_preserve_stack_slots() {
2880 return 0;
2881 }
2882
2883
2884 //------------------------------generate_deopt_blob----------------------------
2885 void SharedRuntime::generate_deopt_blob() {
2886 // Allocate space for the code
2887 ResourceMark rm;
2888 // Setup code generation tools
2889 CodeBuffer buffer("deopt_blob", 2048, 1024);
2890 MacroAssembler* masm = new MacroAssembler(&buffer);
2891 int frame_size_in_words;
2892 OopMap* map = NULL;
2893 OopMapSet *oop_maps = new OopMapSet();
2894
2895 // -------------
2896 // This code enters when returning to a de-optimized nmethod. A return
2897 // address has been pushed on the the stack, and return values are in
2898 // registers.
2899 // If we are doing a normal deopt then we were called from the patched
2900 // nmethod from the point we returned to the nmethod. So the return
2901 // address on the stack is wrong by NativeCall::instruction_size
2902 // We will adjust the value so it looks like we have the original return
2903 // address on the stack (like when we eagerly deoptimized).
2904 // In the case of an exception pending when deoptimizing, we enter
2905 // with a return address on the stack that points after the call we patched
2906 // into the exception handler. We have the following register state from,
2907 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
2908 // rax: exception oop
2909 // rbx: exception handler
2910 // rdx: throwing pc
2911 // So in this case we simply jam rdx into the useless return address and
2912 // the stack looks just like we want.
2913 //
2914 // At this point we need to de-opt. We save the argument return
2915 // registers. We call the first C routine, fetch_unroll_info(). This
2916 // routine captures the return values and returns a structure which
2917 // describes the current frame size and the sizes of all replacement frames.
2918 // The current frame is compiled code and may contain many inlined
2919 // functions, each with their own JVM state. We pop the current frame, then
2920 // push all the new frames. Then we call the C routine unpack_frames() to
2921 // populate these frames. Finally unpack_frames() returns us the new target
2922 // address. Notice that callee-save registers are BLOWN here; they have
2923 // already been captured in the vframeArray at the time the return PC was
2924 // patched.
2925 address start = __ pc();
2926 Label cont;
2927
2928 // Prolog for non exception case!
2929
2930 // Save everything in sight.
2931 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2932
2933 // Normal deoptimization. Save exec mode for unpack_frames.
2934 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
2935 __ jmp(cont);
2936
2937 int reexecute_offset = __ pc() - start;
2938
2939 // Reexecute case
2940 // return address is the pc describes what bci to do re-execute at
2941
2942 // No need to update map as each call to save_live_registers will produce identical oopmap
2943 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2944
2945 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
2946 __ jmp(cont);
2947
2948 int exception_offset = __ pc() - start;
2949
2950 // Prolog for exception case
2951
2952 // all registers are dead at this entry point, except for rax, and
2953 // rdx which contain the exception oop and exception pc
2954 // respectively. Set them in TLS and fall thru to the
2955 // unpack_with_exception_in_tls entry point.
2956
2957 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
2958 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
2959
2960 int exception_in_tls_offset = __ pc() - start;
2961
2962 // new implementation because exception oop is now passed in JavaThread
2963
2964 // Prolog for exception case
2965 // All registers must be preserved because they might be used by LinearScan
2966 // Exceptiop oop and throwing PC are passed in JavaThread
2967 // tos: stack at point of call to method that threw the exception (i.e. only
2968 // args are on the stack, no return address)
2969
2970 // make room on stack for the return address
2971 // It will be patched later with the throwing pc. The correct value is not
2972 // available now because loading it from memory would destroy registers.
2973 __ push(0);
2974
2975 // Save everything in sight.
2976 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2977
2978 // Now it is safe to overwrite any register
2979
2980 // Deopt during an exception. Save exec mode for unpack_frames.
2981 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
2982
2983 // load throwing pc from JavaThread and patch it as the return address
2984 // of the current frame. Then clear the field in JavaThread
2985
2986 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
2987 __ movptr(Address(rbp, wordSize), rdx);
2988 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
2989
2990 #ifdef ASSERT
2991 // verify that there is really an exception oop in JavaThread
2992 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
2993 __ verify_oop(rax);
2994
2995 // verify that there is no pending exception
2996 Label no_pending_exception;
2997 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
2998 __ testptr(rax, rax);
2999 __ jcc(Assembler::zero, no_pending_exception);
3000 __ stop("must not have pending exception here");
3001 __ bind(no_pending_exception);
3002 #endif
3003
3004 __ bind(cont);
3005
3006 // Call C code. Need thread and this frame, but NOT official VM entry
3007 // crud. We cannot block on this call, no GC can happen.
3008 //
3009 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3010
3011 // fetch_unroll_info needs to call last_java_frame().
3012
3013 __ set_last_Java_frame(noreg, noreg, NULL);
3014 #ifdef ASSERT
3015 { Label L;
3016 __ cmpptr(Address(r15_thread,
3017 JavaThread::last_Java_fp_offset()),
3018 (int32_t)0);
3019 __ jcc(Assembler::equal, L);
3020 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3021 __ bind(L);
3022 }
3023 #endif // ASSERT
3024 __ mov(c_rarg0, r15_thread);
3025 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3026
3027 // Need to have an oopmap that tells fetch_unroll_info where to
3028 // find any register it might need.
3029 oop_maps->add_gc_map(__ pc() - start, map);
3030
3031 __ reset_last_Java_frame(false, false);
3032
3033 // Load UnrollBlock* into rdi
3034 __ mov(rdi, rax);
3035
3036 Label noException;
3037 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3038 __ jcc(Assembler::notEqual, noException);
3039 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3040 // QQQ this is useless it was NULL above
3041 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3042 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3043 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3044
3045 __ verify_oop(rax);
3046
3047 // Overwrite the result registers with the exception results.
3048 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3049 // I think this is useless
3050 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3051
3052 __ bind(noException);
3053
3054 // Only register save data is on the stack.
3055 // Now restore the result registers. Everything else is either dead
3056 // or captured in the vframeArray.
3057 RegisterSaver::restore_result_registers(masm);
3058
3059 // All of the register save area has been popped of the stack. Only the
3060 // return address remains.
3061
3062 // Pop all the frames we must move/replace.
3063 //
3064 // Frame picture (youngest to oldest)
3065 // 1: self-frame (no frame link)
3066 // 2: deopting frame (no frame link)
3067 // 3: caller of deopting frame (could be compiled/interpreted).
3068 //
3069 // Note: by leaving the return address of self-frame on the stack
3070 // and using the size of frame 2 to adjust the stack
3071 // when we are done the return to frame 3 will still be on the stack.
3072
3073 // Pop deoptimized frame
3074 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3075 __ addptr(rsp, rcx);
3076
3077 // rsp should be pointing at the return address to the caller (3)
3078
3079 // Stack bang to make sure there's enough room for these interpreter frames.
3080 if (UseStackBanging) {
3081 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3082 __ bang_stack_size(rbx, rcx);
3083 }
3084
3085 // Load address of array of frame pcs into rcx
3086 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3087
3088 // Trash the old pc
3089 __ addptr(rsp, wordSize);
3090
3091 // Load address of array of frame sizes into rsi
3092 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3093
3094 // Load counter into rdx
3095 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3096
3097 // Pick up the initial fp we should save
3098 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3099
3100 // Now adjust the caller's stack to make up for the extra locals
3101 // but record the original sp so that we can save it in the skeletal interpreter
3102 // frame and the stack walking of interpreter_sender will get the unextended sp
3103 // value and not the "real" sp value.
3104
3105 const Register sender_sp = r8;
3106
3107 __ mov(sender_sp, rsp);
3108 __ movl(rbx, Address(rdi,
3109 Deoptimization::UnrollBlock::
3110 caller_adjustment_offset_in_bytes()));
3111 __ subptr(rsp, rbx);
3112
3113 // Push interpreter frames in a loop
3114 Label loop;
3115 __ bind(loop);
3116 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3117 #ifdef CC_INTERP
3118 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3119 #ifdef ASSERT
3120 __ push(0xDEADDEAD); // Make a recognizable pattern
3121 __ push(0xDEADDEAD);
3122 #else /* ASSERT */
3123 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3124 #endif /* ASSERT */
3125 #else
3126 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3127 #endif // CC_INTERP
3128 __ pushptr(Address(rcx, 0)); // Save return address
3129 __ enter(); // Save old & set new ebp
3130 __ subptr(rsp, rbx); // Prolog
3131 #ifdef CC_INTERP
3132 __ movptr(Address(rbp,
3133 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3134 sender_sp); // Make it walkable
3135 #else /* CC_INTERP */
3136 // This value is corrected by layout_activation_impl
3137 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3138 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3139 #endif /* CC_INTERP */
3140 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3141 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3142 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3143 __ decrementl(rdx); // Decrement counter
3144 __ jcc(Assembler::notZero, loop);
3145 __ pushptr(Address(rcx, 0)); // Save final return address
3146
3147 // Re-push self-frame
3148 __ enter(); // Save old & set new ebp
3149
3150 // Allocate a full sized register save area.
3151 // Return address and rbp are in place, so we allocate two less words.
3152 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3153
3154 // Restore frame locals after moving the frame
3155 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3156 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3157
3158 // Call C code. Need thread but NOT official VM entry
3159 // crud. We cannot block on this call, no GC can happen. Call should
3160 // restore return values to their stack-slots with the new SP.
3161 //
3162 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3163
3164 // Use rbp because the frames look interpreted now
3165 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3166 // Don't need the precise return PC here, just precise enough to point into this code blob.
3167 address the_pc = __ pc();
3168 __ set_last_Java_frame(noreg, rbp, the_pc);
3169
3170 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3171 __ mov(c_rarg0, r15_thread);
3172 __ movl(c_rarg1, r14); // second arg: exec_mode
3173 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3174 // Revert SP alignment after call since we're going to do some SP relative addressing below
3175 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3176
3177 // Set an oopmap for the call site
3178 // Use the same PC we used for the last java frame
3179 oop_maps->add_gc_map(the_pc - start,
3180 new OopMap( frame_size_in_words, 0 ));
3181
3182 // Clear fp AND pc
3183 __ reset_last_Java_frame(true, true);
3184
3185 // Collect return values
3186 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3187 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3188 // I think this is useless (throwing pc?)
3189 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3190
3191 // Pop self-frame.
3192 __ leave(); // Epilog
3193
3194 // Jump to interpreter
3195 __ ret(0);
3196
3197 // Make sure all code is generated
3198 masm->flush();
3199
3200 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3201 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3202 }
3203
3204 #ifdef COMPILER2
3205 //------------------------------generate_uncommon_trap_blob--------------------
3206 void SharedRuntime::generate_uncommon_trap_blob() {
3207 // Allocate space for the code
3208 ResourceMark rm;
3209 // Setup code generation tools
3210 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3211 MacroAssembler* masm = new MacroAssembler(&buffer);
3212
3213 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3214
3215 address start = __ pc();
3216
3217 // Push self-frame. We get here with a return address on the
3218 // stack, so rsp is 8-byte aligned until we allocate our frame.
3219 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3220
3221 // No callee saved registers. rbp is assumed implicitly saved
3222 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3223
3224 // compiler left unloaded_class_index in j_rarg0 move to where the
3225 // runtime expects it.
3226 __ movl(c_rarg1, j_rarg0);
3227
3228 __ set_last_Java_frame(noreg, noreg, NULL);
3229
3230 // Call C code. Need thread but NOT official VM entry
3231 // crud. We cannot block on this call, no GC can happen. Call should
3232 // capture callee-saved registers as well as return values.
3233 // Thread is in rdi already.
3234 //
3235 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3236
3237 __ mov(c_rarg0, r15_thread);
3238 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3239
3240 // Set an oopmap for the call site
3241 OopMapSet* oop_maps = new OopMapSet();
3242 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3243
3244 // location of rbp is known implicitly by the frame sender code
3245
3246 oop_maps->add_gc_map(__ pc() - start, map);
3247
3248 __ reset_last_Java_frame(false, false);
3249
3250 // Load UnrollBlock* into rdi
3251 __ mov(rdi, rax);
3252
3253 // Pop all the frames we must move/replace.
3254 //
3255 // Frame picture (youngest to oldest)
3256 // 1: self-frame (no frame link)
3257 // 2: deopting frame (no frame link)
3258 // 3: caller of deopting frame (could be compiled/interpreted).
3259
3260 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3261 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3262
3263 // Pop deoptimized frame (int)
3264 __ movl(rcx, Address(rdi,
3265 Deoptimization::UnrollBlock::
3266 size_of_deoptimized_frame_offset_in_bytes()));
3267 __ addptr(rsp, rcx);
3268
3269 // rsp should be pointing at the return address to the caller (3)
3270
3271 // Stack bang to make sure there's enough room for these interpreter frames.
3272 if (UseStackBanging) {
3273 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3274 __ bang_stack_size(rbx, rcx);
3275 }
3276
3277 // Load address of array of frame pcs into rcx (address*)
3278 __ movptr(rcx,
3279 Address(rdi,
3280 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3281
3282 // Trash the return pc
3283 __ addptr(rsp, wordSize);
3284
3285 // Load address of array of frame sizes into rsi (intptr_t*)
3286 __ movptr(rsi, Address(rdi,
3287 Deoptimization::UnrollBlock::
3288 frame_sizes_offset_in_bytes()));
3289
3290 // Counter
3291 __ movl(rdx, Address(rdi,
3292 Deoptimization::UnrollBlock::
3293 number_of_frames_offset_in_bytes())); // (int)
3294
3295 // Pick up the initial fp we should save
3296 __ movptr(rbp,
3297 Address(rdi,
3298 Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3299
3300 // Now adjust the caller's stack to make up for the extra locals but
3301 // record the original sp so that we can save it in the skeletal
3302 // interpreter frame and the stack walking of interpreter_sender
3303 // will get the unextended sp value and not the "real" sp value.
3304
3305 const Register sender_sp = r8;
3306
3307 __ mov(sender_sp, rsp);
3308 __ movl(rbx, Address(rdi,
3309 Deoptimization::UnrollBlock::
3310 caller_adjustment_offset_in_bytes())); // (int)
3311 __ subptr(rsp, rbx);
3312
3313 // Push interpreter frames in a loop
3314 Label loop;
3315 __ bind(loop);
3316 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3317 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3318 __ pushptr(Address(rcx, 0)); // Save return address
3319 __ enter(); // Save old & set new rbp
3320 __ subptr(rsp, rbx); // Prolog
3321 #ifdef CC_INTERP
3322 __ movptr(Address(rbp,
3323 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3324 sender_sp); // Make it walkable
3325 #else // CC_INTERP
3326 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3327 sender_sp); // Make it walkable
3328 // This value is corrected by layout_activation_impl
3329 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3330 #endif // CC_INTERP
3331 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3332 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3333 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3334 __ decrementl(rdx); // Decrement counter
3335 __ jcc(Assembler::notZero, loop);
3336 __ pushptr(Address(rcx, 0)); // Save final return address
3337
3338 // Re-push self-frame
3339 __ enter(); // Save old & set new rbp
3340 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3341 // Prolog
3342
3343 // Use rbp because the frames look interpreted now
3344 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3345 // Don't need the precise return PC here, just precise enough to point into this code blob.
3346 address the_pc = __ pc();
3347 __ set_last_Java_frame(noreg, rbp, the_pc);
3348
3349 // Call C code. Need thread but NOT official VM entry
3350 // crud. We cannot block on this call, no GC can happen. Call should
3351 // restore return values to their stack-slots with the new SP.
3352 // Thread is in rdi already.
3353 //
3354 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3355
3356 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3357 __ mov(c_rarg0, r15_thread);
3358 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3359 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3360
3361 // Set an oopmap for the call site
3362 // Use the same PC we used for the last java frame
3363 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3364
3365 // Clear fp AND pc
3366 __ reset_last_Java_frame(true, true);
3367
3368 // Pop self-frame.
3369 __ leave(); // Epilog
3370
3371 // Jump to interpreter
3372 __ ret(0);
3373
3374 // Make sure all code is generated
3375 masm->flush();
3376
3377 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3378 SimpleRuntimeFrame::framesize >> 1);
3379 }
3380 #endif // COMPILER2
3381
3382
3383 //------------------------------generate_handler_blob------
3384 //
3385 // Generate a special Compile2Runtime blob that saves all registers,
3386 // and setup oopmap.
3387 //
3388 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
3389 assert(StubRoutines::forward_exception_entry() != NULL,
3390 "must be generated before");
3391
3392 ResourceMark rm;
3393 OopMapSet *oop_maps = new OopMapSet();
3394 OopMap* map;
3395
3396 // Allocate space for the code. Setup code generation tools.
3397 CodeBuffer buffer("handler_blob", 2048, 1024);
3398 MacroAssembler* masm = new MacroAssembler(&buffer);
3399
3400 address start = __ pc();
3401 address call_pc = NULL;
3402 int frame_size_in_words;
3403
3404 // Make room for return address (or push it again)
3405 if (!cause_return) {
3406 __ push(rbx);
3407 }
3408
3409 // Save registers, fpu state, and flags
3410 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3411
3412 // The following is basically a call_VM. However, we need the precise
3413 // address of the call in order to generate an oopmap. Hence, we do all the
3414 // work outselves.
3415
3416 __ set_last_Java_frame(noreg, noreg, NULL);
3417
3418 // The return address must always be correct so that frame constructor never
3419 // sees an invalid pc.
3420
3421 if (!cause_return) {
3422 // overwrite the dummy value we pushed on entry
3423 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3424 __ movptr(Address(rbp, wordSize), c_rarg0);
3425 }
3426
3427 // Do the call
3428 __ mov(c_rarg0, r15_thread);
3429 __ call(RuntimeAddress(call_ptr));
3430
3431 // Set an oopmap for the call site. This oopmap will map all
3432 // oop-registers and debug-info registers as callee-saved. This
3433 // will allow deoptimization at this safepoint to find all possible
3434 // debug-info recordings, as well as let GC find all oops.
3435
3436 oop_maps->add_gc_map( __ pc() - start, map);
3437
3438 Label noException;
3439
3440 __ reset_last_Java_frame(false, false);
3441
3442 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3443 __ jcc(Assembler::equal, noException);
3444
3445 // Exception pending
3446
3447 RegisterSaver::restore_live_registers(masm);
3448
3449 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3450
3451 // No exception case
3452 __ bind(noException);
3453
3454 // Normal exit, restore registers and exit.
3455 RegisterSaver::restore_live_registers(masm);
3456
3457 __ ret(0);
3458
3459 // Make sure all code is generated
3460 masm->flush();
3461
3462 // Fill-out other meta info
3463 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3464 }
3465
3466 //
3467 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3468 //
3469 // Generate a stub that calls into vm to find out the proper destination
3470 // of a java call. All the argument registers are live at this point
3471 // but since this is generic code we don't know what they are and the caller
3472 // must do any gc of the args.
3473 //
3474 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3475 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3476
3477 // allocate space for the code
3478 ResourceMark rm;
3479
3480 CodeBuffer buffer(name, 1000, 512);
3481 MacroAssembler* masm = new MacroAssembler(&buffer);
3482
3483 int frame_size_in_words;
3484
3485 OopMapSet *oop_maps = new OopMapSet();
3486 OopMap* map = NULL;
3487
3488 int start = __ offset();
3489
3490 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3491
3492 int frame_complete = __ offset();
3493
3494 __ set_last_Java_frame(noreg, noreg, NULL);
3495
3496 __ mov(c_rarg0, r15_thread);
3497
3498 __ call(RuntimeAddress(destination));
3499
3500
3501 // Set an oopmap for the call site.
3502 // We need this not only for callee-saved registers, but also for volatile
3503 // registers that the compiler might be keeping live across a safepoint.
3504
3505 oop_maps->add_gc_map( __ offset() - start, map);
3506
3507 // rax contains the address we are going to jump to assuming no exception got installed
3508
3509 // clear last_Java_sp
3510 __ reset_last_Java_frame(false, false);
3511 // check for pending exceptions
3512 Label pending;
3513 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3514 __ jcc(Assembler::notEqual, pending);
3515
3516 // get the returned methodOop
3517 __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
3518 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3519
3520 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3521
3522 RegisterSaver::restore_live_registers(masm);
3523
3524 // We are back the the original state on entry and ready to go.
3525
3526 __ jmp(rax);
3527
3528 // Pending exception after the safepoint
3529
3530 __ bind(pending);
3531
3532 RegisterSaver::restore_live_registers(masm);
3533
3534 // exception pending => remove activation and forward to exception handler
3535
3536 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3537
3538 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3539 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3540
3541 // -------------
3542 // make sure all code is generated
3543 masm->flush();
3544
3545 // return the blob
3546 // frame_size_words or bytes??
3547 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3548 }
3549
3550
3551 #ifdef COMPILER2
3552 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3553 //
3554 //------------------------------generate_exception_blob---------------------------
3555 // creates exception blob at the end
3556 // Using exception blob, this code is jumped from a compiled method.
3557 // (see emit_exception_handler in x86_64.ad file)
3558 //
3559 // Given an exception pc at a call we call into the runtime for the
3560 // handler in this method. This handler might merely restore state
3561 // (i.e. callee save registers) unwind the frame and jump to the
3562 // exception handler for the nmethod if there is no Java level handler
3563 // for the nmethod.
3564 //
3565 // This code is entered with a jmp.
3566 //
3567 // Arguments:
3568 // rax: exception oop
3569 // rdx: exception pc
3570 //
3571 // Results:
3572 // rax: exception oop
3573 // rdx: exception pc in caller or ???
3574 // destination: exception handler of caller
3575 //
3576 // Note: the exception pc MUST be at a call (precise debug information)
3577 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3578 //
3579
3580 void OptoRuntime::generate_exception_blob() {
3581 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3582 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3583 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3584
3585 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3586
3587 // Allocate space for the code
3588 ResourceMark rm;
3589 // Setup code generation tools
3590 CodeBuffer buffer("exception_blob", 2048, 1024);
3591 MacroAssembler* masm = new MacroAssembler(&buffer);
3592
3593
3594 address start = __ pc();
3595
3596 // Exception pc is 'return address' for stack walker
3597 __ push(rdx);
3598 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3599
3600 // Save callee-saved registers. See x86_64.ad.
3601
3602 // rbp is an implicitly saved callee saved register (i.e. the calling
3603 // convention will save restore it in prolog/epilog) Other than that
3604 // there are no callee save registers now that adapter frames are gone.
3605
3606 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3607
3608 // Store exception in Thread object. We cannot pass any arguments to the
3609 // handle_exception call, since we do not want to make any assumption
3610 // about the size of the frame where the exception happened in.
3611 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3612 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3613 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3614
3615 // This call does all the hard work. It checks if an exception handler
3616 // exists in the method.
3617 // If so, it returns the handler address.
3618 // If not, it prepares for stack-unwinding, restoring the callee-save
3619 // registers of the frame being removed.
3620 //
3621 // address OptoRuntime::handle_exception_C(JavaThread* thread)
3622
3623 __ set_last_Java_frame(noreg, noreg, NULL);
3624 __ mov(c_rarg0, r15_thread);
3625 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
3626
3627 // Set an oopmap for the call site. This oopmap will only be used if we
3628 // are unwinding the stack. Hence, all locations will be dead.
3629 // Callee-saved registers will be the same as the frame above (i.e.,
3630 // handle_exception_stub), since they were restored when we got the
3631 // exception.
3632
3633 OopMapSet* oop_maps = new OopMapSet();
3634
3635 oop_maps->add_gc_map( __ pc()-start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3636
3637 __ reset_last_Java_frame(false, false);
3638
3639 // Restore callee-saved registers
3640
3641 // rbp is an implicitly saved callee saved register (i.e. the calling
3642 // convention will save restore it in prolog/epilog) Other than that
3643 // there are no callee save registers no that adapter frames are gone.
3644
3645 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
3646
3647 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
3648 __ pop(rdx); // No need for exception pc anymore
3649
3650 // rax: exception handler
3651
3652 // Restore SP from BP if the exception PC is a MethodHandle call site.
3653 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0);
3654 __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
3655
3656 // We have a handler in rax (could be deopt blob).
3657 __ mov(r8, rax);
3658
3659 // Get the exception oop
3660 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3661 // Get the exception pc in case we are deoptimized
3662 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3663 #ifdef ASSERT
3664 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
3665 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
3666 #endif
3667 // Clear the exception oop so GC no longer processes it as a root.
3668 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
3669
3670 // rax: exception oop
3671 // r8: exception handler
3672 // rdx: exception pc
3673 // Jump to handler
3674
3675 __ jmp(r8);
3676
3677 // Make sure all code is generated
3678 masm->flush();
3679
3680 // Set exception blob
3681 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3682 }
3683 #endif // COMPILER2