1 /*
2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "assembler_x86.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolderOop.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class SimpleRuntimeFrame {
49
50 public:
51
52 // Most of the runtime stubs have this simple frame layout.
53 // This class exists to make the layout shared in one place.
54 // Offsets are for compiler stack slots, which are jints.
55 enum layout {
56 // The frame sender code expects that rbp will be in the "natural" place and
57 // will override any oopMap setting for it. We must therefore force the layout
58 // so that it agrees with the frame sender code.
59 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
60 rbp_off2,
61 return_off, return_off2,
62 framesize
63 };
64 };
65
66 class RegisterSaver {
67 // Capture info about frame layout. Layout offsets are in jint
68 // units because compiler frame slots are jints.
69 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
70 enum layout {
71 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
72 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
73 DEF_XMM_OFFS(0),
74 DEF_XMM_OFFS(1),
75 DEF_XMM_OFFS(2),
76 DEF_XMM_OFFS(3),
77 DEF_XMM_OFFS(4),
78 DEF_XMM_OFFS(5),
79 DEF_XMM_OFFS(6),
80 DEF_XMM_OFFS(7),
81 DEF_XMM_OFFS(8),
82 DEF_XMM_OFFS(9),
83 DEF_XMM_OFFS(10),
84 DEF_XMM_OFFS(11),
85 DEF_XMM_OFFS(12),
86 DEF_XMM_OFFS(13),
87 DEF_XMM_OFFS(14),
88 DEF_XMM_OFFS(15),
89 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
90 fpu_stateH_end,
91 r15_off, r15H_off,
92 r14_off, r14H_off,
93 r13_off, r13H_off,
94 r12_off, r12H_off,
95 r11_off, r11H_off,
96 r10_off, r10H_off,
97 r9_off, r9H_off,
98 r8_off, r8H_off,
99 rdi_off, rdiH_off,
100 rsi_off, rsiH_off,
101 ignore_off, ignoreH_off, // extra copy of rbp
102 rsp_off, rspH_off,
103 rbx_off, rbxH_off,
104 rdx_off, rdxH_off,
105 rcx_off, rcxH_off,
106 rax_off, raxH_off,
107 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
108 align_off, alignH_off,
109 flags_off, flagsH_off,
110 // The frame sender code expects that rbp will be in the "natural" place and
111 // will override any oopMap setting for it. We must therefore force the layout
112 // so that it agrees with the frame sender code.
113 rbp_off, rbpH_off, // copy of rbp we will restore
114 return_off, returnH_off, // slot for return address
115 reg_save_size // size in compiler stack slots
116 };
117
118 public:
119 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
120 static void restore_live_registers(MacroAssembler* masm);
121
122 // Offsets into the register save area
123 // Used by deoptimization when it is managing result register
124 // values on its own
125
126 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
127 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
128 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
129 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
130 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
131
132 // During deoptimization only the result registers need to be restored,
133 // all the other values have already been extracted.
134 static void restore_result_registers(MacroAssembler* masm);
135 };
136
137 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
138
139 // Always make the frame size 16-byte aligned
140 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
141 reg_save_size*BytesPerInt, 16);
142 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
143 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
144 // The caller will allocate additional_frame_words
145 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
146 // CodeBlob frame size is in words.
147 int frame_size_in_words = frame_size_in_bytes / wordSize;
148 *total_frame_words = frame_size_in_words;
149
150 // Save registers, fpu state, and flags.
151 // We assume caller has already pushed the return address onto the
152 // stack, so rsp is 8-byte aligned here.
153 // We push rpb twice in this sequence because we want the real rbp
154 // to be under the return like a normal enter.
155
156 __ enter(); // rsp becomes 16-byte aligned here
157 __ push_CPU_state(); // Push a multiple of 16 bytes
158 if (frame::arg_reg_save_area_bytes != 0) {
159 // Allocate argument register save area
160 __ subptr(rsp, frame::arg_reg_save_area_bytes);
161 }
162
163 // Set an oopmap for the call site. This oopmap will map all
164 // oop-registers and debug-info registers as callee-saved. This
165 // will allow deoptimization at this safepoint to find all possible
166 // debug-info recordings, as well as let GC find all oops.
167
168 OopMapSet *oop_maps = new OopMapSet();
169 OopMap* map = new OopMap(frame_size_in_slots, 0);
170 map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg());
171 map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg());
172 map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg());
173 map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg());
174 // rbp location is known implicitly by the frame sender code, needs no oopmap
175 // and the location where rbp was saved by is ignored
176 map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg());
177 map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg());
178 map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg());
179 map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg());
180 map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg());
181 map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg());
182 map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg());
183 map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg());
184 map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg());
185 map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg());
186 map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg());
187 map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg());
188 map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg());
189 map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg());
190 map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg());
191 map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg());
192 map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg());
193 map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg());
194 map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg());
195 map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg());
196 map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg());
197 map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg());
198 map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg());
199 map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg());
200 map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg());
201 map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg());
202
203 // %%% These should all be a waste but we'll keep things as they were for now
204 if (true) {
205 map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots),
206 rax->as_VMReg()->next());
207 map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots),
208 rcx->as_VMReg()->next());
209 map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots),
210 rdx->as_VMReg()->next());
211 map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots),
212 rbx->as_VMReg()->next());
213 // rbp location is known implicitly by the frame sender code, needs no oopmap
214 map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots),
215 rsi->as_VMReg()->next());
216 map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots),
217 rdi->as_VMReg()->next());
218 map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots),
219 r8->as_VMReg()->next());
220 map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots),
221 r9->as_VMReg()->next());
222 map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots),
223 r10->as_VMReg()->next());
224 map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots),
225 r11->as_VMReg()->next());
226 map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots),
227 r12->as_VMReg()->next());
228 map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots),
229 r13->as_VMReg()->next());
230 map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots),
231 r14->as_VMReg()->next());
232 map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots),
233 r15->as_VMReg()->next());
234 map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots),
235 xmm0->as_VMReg()->next());
236 map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots),
237 xmm1->as_VMReg()->next());
238 map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots),
239 xmm2->as_VMReg()->next());
240 map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots),
241 xmm3->as_VMReg()->next());
242 map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots),
243 xmm4->as_VMReg()->next());
244 map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots),
245 xmm5->as_VMReg()->next());
246 map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots),
247 xmm6->as_VMReg()->next());
248 map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots),
249 xmm7->as_VMReg()->next());
250 map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots),
251 xmm8->as_VMReg()->next());
252 map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots),
253 xmm9->as_VMReg()->next());
254 map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots),
255 xmm10->as_VMReg()->next());
256 map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots),
257 xmm11->as_VMReg()->next());
258 map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots),
259 xmm12->as_VMReg()->next());
260 map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots),
261 xmm13->as_VMReg()->next());
262 map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots),
263 xmm14->as_VMReg()->next());
264 map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots),
265 xmm15->as_VMReg()->next());
266 }
267
268 return map;
269 }
270
271 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
272 if (frame::arg_reg_save_area_bytes != 0) {
273 // Pop arg register save area
274 __ addptr(rsp, frame::arg_reg_save_area_bytes);
275 }
276 // Recover CPU state
277 __ pop_CPU_state();
278 // Get the rbp described implicitly by the calling convention (no oopMap)
279 __ pop(rbp);
280 }
281
282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
283
284 // Just restore result register. Only used by deoptimization. By
285 // now any callee save register that needs to be restored to a c2
286 // caller of the deoptee has been extracted into the vframeArray
287 // and will be stuffed into the c2i adapter we create for later
288 // restoration so only result registers need to be restored here.
289
290 // Restore fp result register
291 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
292 // Restore integer result register
293 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
294 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
295
296 // Pop all of the register save are off the stack except the return address
297 __ addptr(rsp, return_offset_in_bytes());
298 }
299
300 // The java_calling_convention describes stack locations as ideal slots on
301 // a frame with no abi restrictions. Since we must observe abi restrictions
302 // (like the placement of the register window) the slots must be biased by
303 // the following value.
304 static int reg2offset_in(VMReg r) {
305 // Account for saved rbp and return address
306 // This should really be in_preserve_stack_slots
307 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
308 }
309
310 static int reg2offset_out(VMReg r) {
311 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
312 }
313
314 // ---------------------------------------------------------------------------
315 // Read the array of BasicTypes from a signature, and compute where the
316 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
317 // quantities. Values less than VMRegImpl::stack0 are registers, those above
318 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
319 // as framesizes are fixed.
320 // VMRegImpl::stack0 refers to the first slot 0(sp).
321 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
322 // up to RegisterImpl::number_of_registers) are the 64-bit
323 // integer registers.
324
325 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
326 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
327 // units regardless of build. Of course for i486 there is no 64 bit build
328
329 // The Java calling convention is a "shifted" version of the C ABI.
330 // By skipping the first C ABI register we can call non-static jni methods
331 // with small numbers of arguments without having to shuffle the arguments
332 // at all. Since we control the java ABI we ought to at least get some
333 // advantage out of it.
334
335 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
336 VMRegPair *regs,
337 int total_args_passed,
338 int is_outgoing) {
339
340 // Create the mapping between argument positions and
341 // registers.
342 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
343 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
344 };
345 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
346 j_farg0, j_farg1, j_farg2, j_farg3,
347 j_farg4, j_farg5, j_farg6, j_farg7
348 };
349
350
351 uint int_args = 0;
352 uint fp_args = 0;
353 uint stk_args = 0; // inc by 2 each time
354
355 for (int i = 0; i < total_args_passed; i++) {
356 switch (sig_bt[i]) {
357 case T_BOOLEAN:
358 case T_CHAR:
359 case T_BYTE:
360 case T_SHORT:
361 case T_INT:
362 if (int_args < Argument::n_int_register_parameters_j) {
363 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
364 } else {
365 regs[i].set1(VMRegImpl::stack2reg(stk_args));
366 stk_args += 2;
367 }
368 break;
369 case T_VOID:
370 // halves of T_LONG or T_DOUBLE
371 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
372 regs[i].set_bad();
373 break;
374 case T_LONG:
375 assert(sig_bt[i + 1] == T_VOID, "expecting half");
376 // fall through
377 case T_OBJECT:
378 case T_ARRAY:
379 case T_ADDRESS:
380 if (int_args < Argument::n_int_register_parameters_j) {
381 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
382 } else {
383 regs[i].set2(VMRegImpl::stack2reg(stk_args));
384 stk_args += 2;
385 }
386 break;
387 case T_FLOAT:
388 if (fp_args < Argument::n_float_register_parameters_j) {
389 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
390 } else {
391 regs[i].set1(VMRegImpl::stack2reg(stk_args));
392 stk_args += 2;
393 }
394 break;
395 case T_DOUBLE:
396 assert(sig_bt[i + 1] == T_VOID, "expecting half");
397 if (fp_args < Argument::n_float_register_parameters_j) {
398 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
399 } else {
400 regs[i].set2(VMRegImpl::stack2reg(stk_args));
401 stk_args += 2;
402 }
403 break;
404 default:
405 ShouldNotReachHere();
406 break;
407 }
408 }
409
410 return round_to(stk_args, 2);
411 }
412
413 // Patch the callers callsite with entry to compiled code if it exists.
414 static void patch_callers_callsite(MacroAssembler *masm) {
415 Label L;
416 __ verify_oop(rbx);
417 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
418 __ jcc(Assembler::equal, L);
419
420 // Save the current stack pointer
421 __ mov(r13, rsp);
422 // Schedule the branch target address early.
423 // Call into the VM to patch the caller, then jump to compiled callee
424 // rax isn't live so capture return address while we easily can
425 __ movptr(rax, Address(rsp, 0));
426
427 // align stack so push_CPU_state doesn't fault
428 __ andptr(rsp, -(StackAlignmentInBytes));
429 __ push_CPU_state();
430
431
432 __ verify_oop(rbx);
433 // VM needs caller's callsite
434 // VM needs target method
435 // This needs to be a long call since we will relocate this adapter to
436 // the codeBuffer and it may not reach
437
438 // Allocate argument register save area
439 if (frame::arg_reg_save_area_bytes != 0) {
440 __ subptr(rsp, frame::arg_reg_save_area_bytes);
441 }
442 __ mov(c_rarg0, rbx);
443 __ mov(c_rarg1, rax);
444 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
445
446 // De-allocate argument register save area
447 if (frame::arg_reg_save_area_bytes != 0) {
448 __ addptr(rsp, frame::arg_reg_save_area_bytes);
449 }
450
451 __ pop_CPU_state();
452 // restore sp
453 __ mov(rsp, r13);
454 __ bind(L);
455 }
456
457
458 static void gen_c2i_adapter(MacroAssembler *masm,
459 int total_args_passed,
460 int comp_args_on_stack,
461 const BasicType *sig_bt,
462 const VMRegPair *regs,
463 Label& skip_fixup) {
464 // Before we get into the guts of the C2I adapter, see if we should be here
465 // at all. We've come from compiled code and are attempting to jump to the
466 // interpreter, which means the caller made a static call to get here
467 // (vcalls always get a compiled target if there is one). Check for a
468 // compiled target. If there is one, we need to patch the caller's call.
469 patch_callers_callsite(masm);
470
471 __ bind(skip_fixup);
472
473 // Since all args are passed on the stack, total_args_passed *
474 // Interpreter::stackElementSize is the space we need. Plus 1 because
475 // we also account for the return address location since
476 // we store it first rather than hold it in rax across all the shuffling
477
478 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
479
480 // stack is aligned, keep it that way
481 extraspace = round_to(extraspace, 2*wordSize);
482
483 // Get return address
484 __ pop(rax);
485
486 // set senderSP value
487 __ mov(r13, rsp);
488
489 __ subptr(rsp, extraspace);
490
491 // Store the return address in the expected location
492 __ movptr(Address(rsp, 0), rax);
493
494 // Now write the args into the outgoing interpreter space
495 for (int i = 0; i < total_args_passed; i++) {
496 if (sig_bt[i] == T_VOID) {
497 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
498 continue;
499 }
500
501 // offset to start parameters
502 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
503 int next_off = st_off - Interpreter::stackElementSize;
504
505 // Say 4 args:
506 // i st_off
507 // 0 32 T_LONG
508 // 1 24 T_VOID
509 // 2 16 T_OBJECT
510 // 3 8 T_BOOL
511 // - 0 return address
512 //
513 // However to make thing extra confusing. Because we can fit a long/double in
514 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
515 // leaves one slot empty and only stores to a single slot. In this case the
516 // slot that is occupied is the T_VOID slot. See I said it was confusing.
517
518 VMReg r_1 = regs[i].first();
519 VMReg r_2 = regs[i].second();
520 if (!r_1->is_valid()) {
521 assert(!r_2->is_valid(), "");
522 continue;
523 }
524 if (r_1->is_stack()) {
525 // memory to memory use rax
526 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
527 if (!r_2->is_valid()) {
528 // sign extend??
529 __ movl(rax, Address(rsp, ld_off));
530 __ movptr(Address(rsp, st_off), rax);
531
532 } else {
533
534 __ movq(rax, Address(rsp, ld_off));
535
536 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
537 // T_DOUBLE and T_LONG use two slots in the interpreter
538 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
539 // ld_off == LSW, ld_off+wordSize == MSW
540 // st_off == MSW, next_off == LSW
541 __ movq(Address(rsp, next_off), rax);
542 #ifdef ASSERT
543 // Overwrite the unused slot with known junk
544 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
545 __ movptr(Address(rsp, st_off), rax);
546 #endif /* ASSERT */
547 } else {
548 __ movq(Address(rsp, st_off), rax);
549 }
550 }
551 } else if (r_1->is_Register()) {
552 Register r = r_1->as_Register();
553 if (!r_2->is_valid()) {
554 // must be only an int (or less ) so move only 32bits to slot
555 // why not sign extend??
556 __ movl(Address(rsp, st_off), r);
557 } else {
558 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
559 // T_DOUBLE and T_LONG use two slots in the interpreter
560 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
561 // long/double in gpr
562 #ifdef ASSERT
563 // Overwrite the unused slot with known junk
564 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
565 __ movptr(Address(rsp, st_off), rax);
566 #endif /* ASSERT */
567 __ movq(Address(rsp, next_off), r);
568 } else {
569 __ movptr(Address(rsp, st_off), r);
570 }
571 }
572 } else {
573 assert(r_1->is_XMMRegister(), "");
574 if (!r_2->is_valid()) {
575 // only a float use just part of the slot
576 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
577 } else {
578 #ifdef ASSERT
579 // Overwrite the unused slot with known junk
580 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
581 __ movptr(Address(rsp, st_off), rax);
582 #endif /* ASSERT */
583 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
584 }
585 }
586 }
587
588 // Schedule the branch target address early.
589 __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
590 __ jmp(rcx);
591 }
592
593 static void gen_i2c_adapter(MacroAssembler *masm,
594 int total_args_passed,
595 int comp_args_on_stack,
596 const BasicType *sig_bt,
597 const VMRegPair *regs) {
598
599 // Note: r13 contains the senderSP on entry. We must preserve it since
600 // we may do a i2c -> c2i transition if we lose a race where compiled
601 // code goes non-entrant while we get args ready.
602 // In addition we use r13 to locate all the interpreter args as
603 // we must align the stack to 16 bytes on an i2c entry else we
604 // lose alignment we expect in all compiled code and register
605 // save code can segv when fxsave instructions find improperly
606 // aligned stack pointer.
607
608 // Pick up the return address
609 __ movptr(rax, Address(rsp, 0));
610
611 // Must preserve original SP for loading incoming arguments because
612 // we need to align the outgoing SP for compiled code.
613 __ movptr(r11, rsp);
614
615 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
616 // in registers, we will occasionally have no stack args.
617 int comp_words_on_stack = 0;
618 if (comp_args_on_stack) {
619 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
620 // registers are below. By subtracting stack0, we either get a negative
621 // number (all values in registers) or the maximum stack slot accessed.
622
623 // Convert 4-byte c2 stack slots to words.
624 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
625 // Round up to miminum stack alignment, in wordSize
626 comp_words_on_stack = round_to(comp_words_on_stack, 2);
627 __ subptr(rsp, comp_words_on_stack * wordSize);
628 }
629
630
631 // Ensure compiled code always sees stack at proper alignment
632 __ andptr(rsp, -16);
633
634 // push the return address and misalign the stack that youngest frame always sees
635 // as far as the placement of the call instruction
636 __ push(rax);
637
638 // Put saved SP in another register
639 const Register saved_sp = rax;
640 __ movptr(saved_sp, r11);
641
642 // Will jump to the compiled code just as if compiled code was doing it.
643 // Pre-load the register-jump target early, to schedule it better.
644 __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
645
646 // Now generate the shuffle code. Pick up all register args and move the
647 // rest through the floating point stack top.
648 for (int i = 0; i < total_args_passed; i++) {
649 if (sig_bt[i] == T_VOID) {
650 // Longs and doubles are passed in native word order, but misaligned
651 // in the 32-bit build.
652 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
653 continue;
654 }
655
656 // Pick up 0, 1 or 2 words from SP+offset.
657
658 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
659 "scrambled load targets?");
660 // Load in argument order going down.
661 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
662 // Point to interpreter value (vs. tag)
663 int next_off = ld_off - Interpreter::stackElementSize;
664 //
665 //
666 //
667 VMReg r_1 = regs[i].first();
668 VMReg r_2 = regs[i].second();
669 if (!r_1->is_valid()) {
670 assert(!r_2->is_valid(), "");
671 continue;
672 }
673 if (r_1->is_stack()) {
674 // Convert stack slot to an SP offset (+ wordSize to account for return address )
675 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
676
677 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
678 // and if we end up going thru a c2i because of a miss a reasonable value of r13
679 // will be generated.
680 if (!r_2->is_valid()) {
681 // sign extend???
682 __ movl(r13, Address(saved_sp, ld_off));
683 __ movptr(Address(rsp, st_off), r13);
684 } else {
685 //
686 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
687 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
688 // So we must adjust where to pick up the data to match the interpreter.
689 //
690 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
691 // are accessed as negative so LSW is at LOW address
692
693 // ld_off is MSW so get LSW
694 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
695 next_off : ld_off;
696 __ movq(r13, Address(saved_sp, offset));
697 // st_off is LSW (i.e. reg.first())
698 __ movq(Address(rsp, st_off), r13);
699 }
700 } else if (r_1->is_Register()) { // Register argument
701 Register r = r_1->as_Register();
702 assert(r != rax, "must be different");
703 if (r_2->is_valid()) {
704 //
705 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
706 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
707 // So we must adjust where to pick up the data to match the interpreter.
708
709 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
710 next_off : ld_off;
711
712 // this can be a misaligned move
713 __ movq(r, Address(saved_sp, offset));
714 } else {
715 // sign extend and use a full word?
716 __ movl(r, Address(saved_sp, ld_off));
717 }
718 } else {
719 if (!r_2->is_valid()) {
720 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
721 } else {
722 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
723 }
724 }
725 }
726
727 // 6243940 We might end up in handle_wrong_method if
728 // the callee is deoptimized as we race thru here. If that
729 // happens we don't want to take a safepoint because the
730 // caller frame will look interpreted and arguments are now
731 // "compiled" so it is much better to make this transition
732 // invisible to the stack walking code. Unfortunately if
733 // we try and find the callee by normal means a safepoint
734 // is possible. So we stash the desired callee in the thread
735 // and the vm will find there should this case occur.
736
737 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
738
739 // put methodOop where a c2i would expect should we end up there
740 // only needed becaus eof c2 resolve stubs return methodOop as a result in
741 // rax
742 __ mov(rax, rbx);
743 __ jmp(r11);
744 }
745
746 // ---------------------------------------------------------------
747 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
748 int total_args_passed,
749 int comp_args_on_stack,
750 const BasicType *sig_bt,
751 const VMRegPair *regs,
752 AdapterFingerPrint* fingerprint) {
753 address i2c_entry = __ pc();
754
755 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
756
757 // -------------------------------------------------------------------------
758 // Generate a C2I adapter. On entry we know rbx holds the methodOop during calls
759 // to the interpreter. The args start out packed in the compiled layout. They
760 // need to be unpacked into the interpreter layout. This will almost always
761 // require some stack space. We grow the current (compiled) stack, then repack
762 // the args. We finally end in a jump to the generic interpreter entry point.
763 // On exit from the interpreter, the interpreter will restore our SP (lest the
764 // compiled code, which relys solely on SP and not RBP, get sick).
765
766 address c2i_unverified_entry = __ pc();
767 Label skip_fixup;
768 Label ok;
769
770 Register holder = rax;
771 Register receiver = j_rarg0;
772 Register temp = rbx;
773
774 {
775 __ verify_oop(holder);
776 __ load_klass(temp, receiver);
777 __ verify_oop(temp);
778
779 __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
780 __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
781 __ jcc(Assembler::equal, ok);
782 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
783
784 __ bind(ok);
785 // Method might have been compiled since the call site was patched to
786 // interpreted if that is the case treat it as a miss so we can get
787 // the call site corrected.
788 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
789 __ jcc(Assembler::equal, skip_fixup);
790 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
791 }
792
793 address c2i_entry = __ pc();
794
795 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
796
797 __ flush();
798 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
799 }
800
801 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
802 VMRegPair *regs,
803 int total_args_passed) {
804 // We return the amount of VMRegImpl stack slots we need to reserve for all
805 // the arguments NOT counting out_preserve_stack_slots.
806
807 // NOTE: These arrays will have to change when c1 is ported
808 #ifdef _WIN64
809 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
810 c_rarg0, c_rarg1, c_rarg2, c_rarg3
811 };
812 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
813 c_farg0, c_farg1, c_farg2, c_farg3
814 };
815 #else
816 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
817 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
818 };
819 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
820 c_farg0, c_farg1, c_farg2, c_farg3,
821 c_farg4, c_farg5, c_farg6, c_farg7
822 };
823 #endif // _WIN64
824
825
826 uint int_args = 0;
827 uint fp_args = 0;
828 uint stk_args = 0; // inc by 2 each time
829
830 for (int i = 0; i < total_args_passed; i++) {
831 switch (sig_bt[i]) {
832 case T_BOOLEAN:
833 case T_CHAR:
834 case T_BYTE:
835 case T_SHORT:
836 case T_INT:
837 if (int_args < Argument::n_int_register_parameters_c) {
838 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
839 #ifdef _WIN64
840 fp_args++;
841 // Allocate slots for callee to stuff register args the stack.
842 stk_args += 2;
843 #endif
844 } else {
845 regs[i].set1(VMRegImpl::stack2reg(stk_args));
846 stk_args += 2;
847 }
848 break;
849 case T_LONG:
850 assert(sig_bt[i + 1] == T_VOID, "expecting half");
851 // fall through
852 case T_OBJECT:
853 case T_ARRAY:
854 case T_ADDRESS:
855 if (int_args < Argument::n_int_register_parameters_c) {
856 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
857 #ifdef _WIN64
858 fp_args++;
859 stk_args += 2;
860 #endif
861 } else {
862 regs[i].set2(VMRegImpl::stack2reg(stk_args));
863 stk_args += 2;
864 }
865 break;
866 case T_FLOAT:
867 if (fp_args < Argument::n_float_register_parameters_c) {
868 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
869 #ifdef _WIN64
870 int_args++;
871 // Allocate slots for callee to stuff register args the stack.
872 stk_args += 2;
873 #endif
874 } else {
875 regs[i].set1(VMRegImpl::stack2reg(stk_args));
876 stk_args += 2;
877 }
878 break;
879 case T_DOUBLE:
880 assert(sig_bt[i + 1] == T_VOID, "expecting half");
881 if (fp_args < Argument::n_float_register_parameters_c) {
882 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
883 #ifdef _WIN64
884 int_args++;
885 // Allocate slots for callee to stuff register args the stack.
886 stk_args += 2;
887 #endif
888 } else {
889 regs[i].set2(VMRegImpl::stack2reg(stk_args));
890 stk_args += 2;
891 }
892 break;
893 case T_VOID: // Halves of longs and doubles
894 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
895 regs[i].set_bad();
896 break;
897 default:
898 ShouldNotReachHere();
899 break;
900 }
901 }
902 #ifdef _WIN64
903 // windows abi requires that we always allocate enough stack space
904 // for 4 64bit registers to be stored down.
905 if (stk_args < 8) {
906 stk_args = 8;
907 }
908 #endif // _WIN64
909
910 return stk_args;
911 }
912
913 // On 64 bit we will store integer like items to the stack as
914 // 64 bits items (sparc abi) even though java would only store
915 // 32bits for a parameter. On 32bit it will simply be 32 bits
916 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
917 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
918 if (src.first()->is_stack()) {
919 if (dst.first()->is_stack()) {
920 // stack to stack
921 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
922 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
923 } else {
924 // stack to reg
925 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
926 }
927 } else if (dst.first()->is_stack()) {
928 // reg to stack
929 // Do we really have to sign extend???
930 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
931 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
932 } else {
933 // Do we really have to sign extend???
934 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
935 if (dst.first() != src.first()) {
936 __ movq(dst.first()->as_Register(), src.first()->as_Register());
937 }
938 }
939 }
940
941 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
942 if (src.first()->is_stack()) {
943 if (dst.first()->is_stack()) {
944 // stack to stack
945 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
946 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
947 } else {
948 // stack to reg
949 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
950 }
951 } else if (dst.first()->is_stack()) {
952 // reg to stack
953 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
954 } else {
955 if (dst.first() != src.first()) {
956 __ movq(dst.first()->as_Register(), src.first()->as_Register());
957 }
958 }
959 }
960
961 // An oop arg. Must pass a handle not the oop itself
962 static void object_move(MacroAssembler* masm,
963 OopMap* map,
964 int oop_handle_offset,
965 int framesize_in_slots,
966 VMRegPair src,
967 VMRegPair dst,
968 bool is_receiver,
969 int* receiver_offset) {
970
971 // must pass a handle. First figure out the location we use as a handle
972
973 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
974
975 // See if oop is NULL if it is we need no handle
976
977 if (src.first()->is_stack()) {
978
979 // Oop is already on the stack as an argument
980 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
981 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
982 if (is_receiver) {
983 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
984 }
985
986 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
987 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
988 // conditionally move a NULL
989 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
990 } else {
991
992 // Oop is in an a register we must store it to the space we reserve
993 // on the stack for oop_handles and pass a handle if oop is non-NULL
994
995 const Register rOop = src.first()->as_Register();
996 int oop_slot;
997 if (rOop == j_rarg0)
998 oop_slot = 0;
999 else if (rOop == j_rarg1)
1000 oop_slot = 1;
1001 else if (rOop == j_rarg2)
1002 oop_slot = 2;
1003 else if (rOop == j_rarg3)
1004 oop_slot = 3;
1005 else if (rOop == j_rarg4)
1006 oop_slot = 4;
1007 else {
1008 assert(rOop == j_rarg5, "wrong register");
1009 oop_slot = 5;
1010 }
1011
1012 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1013 int offset = oop_slot*VMRegImpl::stack_slot_size;
1014
1015 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1016 // Store oop in handle area, may be NULL
1017 __ movptr(Address(rsp, offset), rOop);
1018 if (is_receiver) {
1019 *receiver_offset = offset;
1020 }
1021
1022 __ cmpptr(rOop, (int32_t)NULL_WORD);
1023 __ lea(rHandle, Address(rsp, offset));
1024 // conditionally move a NULL from the handle area where it was just stored
1025 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1026 }
1027
1028 // If arg is on the stack then place it otherwise it is already in correct reg.
1029 if (dst.first()->is_stack()) {
1030 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1031 }
1032 }
1033
1034 // A float arg may have to do float reg int reg conversion
1035 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1036 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1037
1038 // The calling conventions assures us that each VMregpair is either
1039 // all really one physical register or adjacent stack slots.
1040 // This greatly simplifies the cases here compared to sparc.
1041
1042 if (src.first()->is_stack()) {
1043 if (dst.first()->is_stack()) {
1044 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1045 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1046 } else {
1047 // stack to reg
1048 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1049 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1050 }
1051 } else if (dst.first()->is_stack()) {
1052 // reg to stack
1053 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1054 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1055 } else {
1056 // reg to reg
1057 // In theory these overlap but the ordering is such that this is likely a nop
1058 if ( src.first() != dst.first()) {
1059 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1060 }
1061 }
1062 }
1063
1064 // A long move
1065 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1066
1067 // The calling conventions assures us that each VMregpair is either
1068 // all really one physical register or adjacent stack slots.
1069 // This greatly simplifies the cases here compared to sparc.
1070
1071 if (src.is_single_phys_reg() ) {
1072 if (dst.is_single_phys_reg()) {
1073 if (dst.first() != src.first()) {
1074 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1075 }
1076 } else {
1077 assert(dst.is_single_reg(), "not a stack pair");
1078 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1079 }
1080 } else if (dst.is_single_phys_reg()) {
1081 assert(src.is_single_reg(), "not a stack pair");
1082 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1083 } else {
1084 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1085 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1086 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1087 }
1088 }
1089
1090 // A double move
1091 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1092
1093 // The calling conventions assures us that each VMregpair is either
1094 // all really one physical register or adjacent stack slots.
1095 // This greatly simplifies the cases here compared to sparc.
1096
1097 if (src.is_single_phys_reg() ) {
1098 if (dst.is_single_phys_reg()) {
1099 // In theory these overlap but the ordering is such that this is likely a nop
1100 if ( src.first() != dst.first()) {
1101 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1102 }
1103 } else {
1104 assert(dst.is_single_reg(), "not a stack pair");
1105 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1106 }
1107 } else if (dst.is_single_phys_reg()) {
1108 assert(src.is_single_reg(), "not a stack pair");
1109 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1110 } else {
1111 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1112 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1113 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1114 }
1115 }
1116
1117
1118 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1119 // We always ignore the frame_slots arg and just use the space just below frame pointer
1120 // which by this time is free to use
1121 switch (ret_type) {
1122 case T_FLOAT:
1123 __ movflt(Address(rbp, -wordSize), xmm0);
1124 break;
1125 case T_DOUBLE:
1126 __ movdbl(Address(rbp, -wordSize), xmm0);
1127 break;
1128 case T_VOID: break;
1129 default: {
1130 __ movptr(Address(rbp, -wordSize), rax);
1131 }
1132 }
1133 }
1134
1135 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1136 // We always ignore the frame_slots arg and just use the space just below frame pointer
1137 // which by this time is free to use
1138 switch (ret_type) {
1139 case T_FLOAT:
1140 __ movflt(xmm0, Address(rbp, -wordSize));
1141 break;
1142 case T_DOUBLE:
1143 __ movdbl(xmm0, Address(rbp, -wordSize));
1144 break;
1145 case T_VOID: break;
1146 default: {
1147 __ movptr(rax, Address(rbp, -wordSize));
1148 }
1149 }
1150 }
1151
1152 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1153 for ( int i = first_arg ; i < arg_count ; i++ ) {
1154 if (args[i].first()->is_Register()) {
1155 __ push(args[i].first()->as_Register());
1156 } else if (args[i].first()->is_XMMRegister()) {
1157 __ subptr(rsp, 2*wordSize);
1158 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1159 }
1160 }
1161 }
1162
1163 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1164 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1165 if (args[i].first()->is_Register()) {
1166 __ pop(args[i].first()->as_Register());
1167 } else if (args[i].first()->is_XMMRegister()) {
1168 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1169 __ addptr(rsp, 2*wordSize);
1170 }
1171 }
1172 }
1173
1174
1175 static void save_or_restore_arguments(MacroAssembler* masm,
1176 const int stack_slots,
1177 const int total_in_args,
1178 const int arg_save_area,
1179 OopMap* map,
1180 VMRegPair* in_regs,
1181 BasicType* in_sig_bt) {
1182 // if map is non-NULL then the code should store the values,
1183 // otherwise it should load them.
1184 int slot = arg_save_area;
1185 // Save down double word first
1186 for ( int i = 0; i < total_in_args; i++) {
1187 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1188 int offset = slot * VMRegImpl::stack_slot_size;
1189 slot += VMRegImpl::slots_per_word;
1190 assert(slot <= stack_slots, "overflow");
1191 if (map != NULL) {
1192 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1193 } else {
1194 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1195 }
1196 }
1197 if (in_regs[i].first()->is_Register() &&
1198 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1199 int offset = slot * VMRegImpl::stack_slot_size;
1200 slot += VMRegImpl::slots_per_word;
1201 if (map != NULL) {
1202 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1203 if (in_sig_bt[i] == T_ARRAY) {
1204 map->set_oop(VMRegImpl::stack2reg(slot));;
1205 }
1206 } else {
1207 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1208 }
1209 }
1210 }
1211 // Save or restore single word registers
1212 for ( int i = 0; i < total_in_args; i++) {
1213 if (in_regs[i].first()->is_Register()) {
1214 int offset = slot * VMRegImpl::stack_slot_size;
1215 slot++;
1216 assert(slot <= stack_slots, "overflow");
1217
1218 // Value is in an input register pass we must flush it to the stack
1219 const Register reg = in_regs[i].first()->as_Register();
1220 switch (in_sig_bt[i]) {
1221 case T_BOOLEAN:
1222 case T_CHAR:
1223 case T_BYTE:
1224 case T_SHORT:
1225 case T_INT:
1226 if (map != NULL) {
1227 __ movl(Address(rsp, offset), reg);
1228 } else {
1229 __ movl(reg, Address(rsp, offset));
1230 }
1231 break;
1232 case T_ARRAY:
1233 case T_LONG:
1234 // handled above
1235 break;
1236 case T_OBJECT:
1237 default: ShouldNotReachHere();
1238 }
1239 } else if (in_regs[i].first()->is_XMMRegister()) {
1240 if (in_sig_bt[i] == T_FLOAT) {
1241 int offset = slot * VMRegImpl::stack_slot_size;
1242 slot++;
1243 assert(slot <= stack_slots, "overflow");
1244 if (map != NULL) {
1245 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1246 } else {
1247 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1248 }
1249 }
1250 } else if (in_regs[i].first()->is_stack()) {
1251 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1252 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1253 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1254 }
1255 }
1256 }
1257 }
1258
1259
1260 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1261 // keeps a new JNI critical region from starting until a GC has been
1262 // forced. Save down any oops in registers and describe them in an
1263 // OopMap.
1264 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1265 int stack_slots,
1266 int total_c_args,
1267 int total_in_args,
1268 int arg_save_area,
1269 OopMapSet* oop_maps,
1270 VMRegPair* in_regs,
1271 BasicType* in_sig_bt) {
1272 __ block_comment("check GC_locker::needs_gc");
1273 Label cont;
1274 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
1275 __ jcc(Assembler::equal, cont);
1276
1277 // Save down any incoming oops and call into the runtime to halt for a GC
1278
1279 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1280 save_or_restore_arguments(masm, stack_slots, total_in_args,
1281 arg_save_area, map, in_regs, in_sig_bt);
1282
1283 address the_pc = __ pc();
1284 oop_maps->add_gc_map( __ offset(), map);
1285 __ set_last_Java_frame(rsp, noreg, the_pc);
1286
1287 __ block_comment("block_for_jni_critical");
1288 __ movptr(c_rarg0, r15_thread);
1289 __ mov(r12, rsp); // remember sp
1290 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1291 __ andptr(rsp, -16); // align stack as required by ABI
1292 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1293 __ mov(rsp, r12); // restore sp
1294 __ reinit_heapbase();
1295
1296 __ reset_last_Java_frame(false, true);
1297
1298 save_or_restore_arguments(masm, stack_slots, total_in_args,
1299 arg_save_area, NULL, in_regs, in_sig_bt);
1300
1301 __ bind(cont);
1302 #ifdef ASSERT
1303 if (StressCriticalJNINatives) {
1304 // Stress register saving
1305 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1306 save_or_restore_arguments(masm, stack_slots, total_in_args,
1307 arg_save_area, map, in_regs, in_sig_bt);
1308 // Destroy argument registers
1309 for (int i = 0; i < total_in_args - 1; i++) {
1310 if (in_regs[i].first()->is_Register()) {
1311 const Register reg = in_regs[i].first()->as_Register();
1312 __ xorptr(reg, reg);
1313 } else if (in_regs[i].first()->is_XMMRegister()) {
1314 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1315 } else if (in_regs[i].first()->is_FloatRegister()) {
1316 ShouldNotReachHere();
1317 } else if (in_regs[i].first()->is_stack()) {
1318 // Nothing to do
1319 } else {
1320 ShouldNotReachHere();
1321 }
1322 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1323 i++;
1324 }
1325 }
1326
1327 save_or_restore_arguments(masm, stack_slots, total_in_args,
1328 arg_save_area, NULL, in_regs, in_sig_bt);
1329 }
1330 #endif
1331 }
1332
1333 // Unpack an array argument into a pointer to the body and the length
1334 // if the array is non-null, otherwise pass 0 for both.
1335 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1336 Register tmp_reg = rax;
1337 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1338 "possible collision");
1339 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1340 "possible collision");
1341
1342 // Pass the length, ptr pair
1343 Label is_null, done;
1344 VMRegPair tmp;
1345 tmp.set_ptr(tmp_reg->as_VMReg());
1346 if (reg.first()->is_stack()) {
1347 // Load the arg up from the stack
1348 move_ptr(masm, reg, tmp);
1349 reg = tmp;
1350 }
1351 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1352 __ jccb(Assembler::equal, is_null);
1353 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1354 move_ptr(masm, tmp, body_arg);
1355 // load the length relative to the body.
1356 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1357 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1358 move32_64(masm, tmp, length_arg);
1359 __ jmpb(done);
1360 __ bind(is_null);
1361 // Pass zeros
1362 __ xorptr(tmp_reg, tmp_reg);
1363 move_ptr(masm, tmp, body_arg);
1364 move32_64(masm, tmp, length_arg);
1365 __ bind(done);
1366 }
1367
1368
1369 class ComputeMoveOrder: public StackObj {
1370 class MoveOperation: public ResourceObj {
1371 friend class ComputeMoveOrder;
1372 private:
1373 VMRegPair _src;
1374 VMRegPair _dst;
1375 int _src_index;
1376 int _dst_index;
1377 bool _processed;
1378 MoveOperation* _next;
1379 MoveOperation* _prev;
1380
1381 static int get_id(VMRegPair r) {
1382 return r.first()->value();
1383 }
1384
1385 public:
1386 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst):
1387 _src(src)
1388 , _src_index(src_index)
1389 , _dst(dst)
1390 , _dst_index(dst_index)
1391 , _next(NULL)
1392 , _prev(NULL)
1393 , _processed(false) {
1394 }
1395
1396 VMRegPair src() const { return _src; }
1397 int src_id() const { return get_id(src()); }
1398 int src_index() const { return _src_index; }
1399 VMRegPair dst() const { return _dst; }
1400 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; }
1401 int dst_index() const { return _dst_index; }
1402 int dst_id() const { return get_id(dst()); }
1403 MoveOperation* next() const { return _next; }
1404 MoveOperation* prev() const { return _prev; }
1405 void set_processed() { _processed = true; }
1406 bool is_processed() const { return _processed; }
1407
1408 // insert
1409 void break_cycle(VMRegPair temp_register) {
1410 // create a new store following the last store
1411 // to move from the temp_register to the original
1412 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst());
1413
1414 // break the cycle of links and insert new_store at the end
1415 // break the reverse link.
1416 MoveOperation* p = prev();
1417 if (p->_next != NULL) {
1418 p->_next->_prev = NULL;
1419 }
1420 p->_next = new_store;
1421 new_store->_prev = p;
1422
1423 // change the original store to save it's value in the temp.
1424 set_dst(-1, temp_register);
1425 }
1426
1427 void link(GrowableArray<MoveOperation*>& killer) {
1428 // link this store in front the store that it depends on
1429 MoveOperation* n = killer.at_grow(src_id(), NULL);
1430 if (n != NULL) {
1431 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet");
1432 _next = n;
1433 n->_prev = this;
1434 }
1435 }
1436 };
1437
1438 private:
1439 GrowableArray<MoveOperation*> edges;
1440
1441 public:
1442 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs,
1443 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) {
1444 // Move operations where the dest is the stack can all be
1445 // scheduled first since they can't interfere with the other moves.
1446 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1447 if (in_sig_bt[i] == T_ARRAY) {
1448 c_arg--;
1449 if (out_regs[c_arg].first()->is_stack() &&
1450 out_regs[c_arg + 1].first()->is_stack()) {
1451 arg_order.push(i);
1452 arg_order.push(c_arg);
1453 } else {
1454 if (out_regs[c_arg].first()->is_stack() ||
1455 in_regs[i].first() == out_regs[c_arg].first()) {
1456 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]);
1457 } else {
1458 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1459 }
1460 }
1461 } else if (in_sig_bt[i] == T_VOID) {
1462 arg_order.push(i);
1463 arg_order.push(c_arg);
1464 } else {
1465 if (out_regs[c_arg].first()->is_stack() ||
1466 in_regs[i].first() == out_regs[c_arg].first()) {
1467 arg_order.push(i);
1468 arg_order.push(c_arg);
1469 } else {
1470 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1471 }
1472 }
1473 }
1474 // Break any cycles in the register moves and emit the in the
1475 // proper order.
1476 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg);
1477 for (int i = 0; i < stores->length(); i++) {
1478 arg_order.push(stores->at(i)->src_index());
1479 arg_order.push(stores->at(i)->dst_index());
1480 }
1481 }
1482
1483 // Collected all the move operations
1484 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) {
1485 if (src.first() == dst.first()) return;
1486 edges.append(new MoveOperation(src_index, src, dst_index, dst));
1487 }
1488
1489 // Walk the edges breaking cycles between moves. The result list
1490 // can be walked in order to produce the proper set of loads
1491 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) {
1492 // Record which moves kill which values
1493 GrowableArray<MoveOperation*> killer;
1494 for (int i = 0; i < edges.length(); i++) {
1495 MoveOperation* s = edges.at(i);
1496 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer");
1497 killer.at_put_grow(s->dst_id(), s, NULL);
1498 }
1499 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL,
1500 "make sure temp isn't in the registers that are killed");
1501
1502 // create links between loads and stores
1503 for (int i = 0; i < edges.length(); i++) {
1504 edges.at(i)->link(killer);
1505 }
1506
1507 // at this point, all the move operations are chained together
1508 // in a doubly linked list. Processing it backwards finds
1509 // the beginning of the chain, forwards finds the end. If there's
1510 // a cycle it can be broken at any point, so pick an edge and walk
1511 // backward until the list ends or we end where we started.
1512 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>();
1513 for (int e = 0; e < edges.length(); e++) {
1514 MoveOperation* s = edges.at(e);
1515 if (!s->is_processed()) {
1516 MoveOperation* start = s;
1517 // search for the beginning of the chain or cycle
1518 while (start->prev() != NULL && start->prev() != s) {
1519 start = start->prev();
1520 }
1521 if (start->prev() == s) {
1522 start->break_cycle(temp_register);
1523 }
1524 // walk the chain forward inserting to store list
1525 while (start != NULL) {
1526 stores->append(start);
1527 start->set_processed();
1528 start = start->next();
1529 }
1530 }
1531 }
1532 return stores;
1533 }
1534 };
1535
1536
1537 // ---------------------------------------------------------------------------
1538 // Generate a native wrapper for a given method. The method takes arguments
1539 // in the Java compiled code convention, marshals them to the native
1540 // convention (handlizes oops, etc), transitions to native, makes the call,
1541 // returns to java state (possibly blocking), unhandlizes any result and
1542 // returns.
1543 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
1544 methodHandle method,
1545 int compile_id,
1546 int total_in_args,
1547 int comp_args_on_stack,
1548 BasicType *in_sig_bt,
1549 VMRegPair *in_regs,
1550 BasicType ret_type) {
1551 bool is_critical_native = true;
1552 address native_func = method->critical_native_function();
1553 if (native_func == NULL) {
1554 native_func = method->native_function();
1555 is_critical_native = false;
1556 }
1557 assert(native_func != NULL, "must have function");
1558
1559 // An OopMap for lock (and class if static)
1560 OopMapSet *oop_maps = new OopMapSet();
1561 intptr_t start = (intptr_t)__ pc();
1562
1563 // We have received a description of where all the java arg are located
1564 // on entry to the wrapper. We need to convert these args to where
1565 // the jni function will expect them. To figure out where they go
1566 // we convert the java signature to a C signature by inserting
1567 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1568
1569 int total_c_args = total_in_args;
1570 if (!is_critical_native) {
1571 total_c_args += 1;
1572 if (method->is_static()) {
1573 total_c_args++;
1574 }
1575 } else {
1576 for (int i = 0; i < total_in_args; i++) {
1577 if (in_sig_bt[i] == T_ARRAY) {
1578 total_c_args++;
1579 }
1580 }
1581 }
1582
1583 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1584 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1585 BasicType* in_elem_bt = NULL;
1586
1587 int argc = 0;
1588 if (!is_critical_native) {
1589 out_sig_bt[argc++] = T_ADDRESS;
1590 if (method->is_static()) {
1591 out_sig_bt[argc++] = T_OBJECT;
1592 }
1593
1594 for (int i = 0; i < total_in_args ; i++ ) {
1595 out_sig_bt[argc++] = in_sig_bt[i];
1596 }
1597 } else {
1598 Thread* THREAD = Thread::current();
1599 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1600 SignatureStream ss(method->signature());
1601 for (int i = 0; i < total_in_args ; i++ ) {
1602 if (in_sig_bt[i] == T_ARRAY) {
1603 // Arrays are passed as int, elem* pair
1604 out_sig_bt[argc++] = T_INT;
1605 out_sig_bt[argc++] = T_ADDRESS;
1606 Symbol* atype = ss.as_symbol(CHECK_NULL);
1607 const char* at = atype->as_C_string();
1608 if (strlen(at) == 2) {
1609 assert(at[0] == '[', "must be");
1610 switch (at[1]) {
1611 case 'B': in_elem_bt[i] = T_BYTE; break;
1612 case 'C': in_elem_bt[i] = T_CHAR; break;
1613 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1614 case 'F': in_elem_bt[i] = T_FLOAT; break;
1615 case 'I': in_elem_bt[i] = T_INT; break;
1616 case 'J': in_elem_bt[i] = T_LONG; break;
1617 case 'S': in_elem_bt[i] = T_SHORT; break;
1618 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1619 default: ShouldNotReachHere();
1620 }
1621 }
1622 } else {
1623 out_sig_bt[argc++] = in_sig_bt[i];
1624 in_elem_bt[i] = T_VOID;
1625 }
1626 if (in_sig_bt[i] != T_VOID) {
1627 assert(in_sig_bt[i] == ss.type(), "must match");
1628 ss.next();
1629 }
1630 }
1631 }
1632
1633 // Now figure out where the args must be stored and how much stack space
1634 // they require.
1635 int out_arg_slots;
1636 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1637
1638 // Compute framesize for the wrapper. We need to handlize all oops in
1639 // incoming registers
1640
1641 // Calculate the total number of stack slots we will need.
1642
1643 // First count the abi requirement plus all of the outgoing args
1644 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1645
1646 // Now the space for the inbound oop handle area
1647 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
1648 if (is_critical_native) {
1649 // Critical natives may have to call out so they need a save area
1650 // for register arguments.
1651 int double_slots = 0;
1652 int single_slots = 0;
1653 for ( int i = 0; i < total_in_args; i++) {
1654 if (in_regs[i].first()->is_Register()) {
1655 const Register reg = in_regs[i].first()->as_Register();
1656 switch (in_sig_bt[i]) {
1657 case T_BOOLEAN:
1658 case T_BYTE:
1659 case T_SHORT:
1660 case T_CHAR:
1661 case T_INT: single_slots++; break;
1662 case T_ARRAY:
1663 case T_LONG: double_slots++; break;
1664 default: ShouldNotReachHere();
1665 }
1666 } else if (in_regs[i].first()->is_XMMRegister()) {
1667 switch (in_sig_bt[i]) {
1668 case T_FLOAT: single_slots++; break;
1669 case T_DOUBLE: double_slots++; break;
1670 default: ShouldNotReachHere();
1671 }
1672 } else if (in_regs[i].first()->is_FloatRegister()) {
1673 ShouldNotReachHere();
1674 }
1675 }
1676 total_save_slots = double_slots * 2 + single_slots;
1677 // align the save area
1678 if (double_slots != 0) {
1679 stack_slots = round_to(stack_slots, 2);
1680 }
1681 }
1682
1683 int oop_handle_offset = stack_slots;
1684 stack_slots += total_save_slots;
1685
1686 // Now any space we need for handlizing a klass if static method
1687
1688 int klass_slot_offset = 0;
1689 int klass_offset = -1;
1690 int lock_slot_offset = 0;
1691 bool is_static = false;
1692
1693 if (method->is_static()) {
1694 klass_slot_offset = stack_slots;
1695 stack_slots += VMRegImpl::slots_per_word;
1696 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1697 is_static = true;
1698 }
1699
1700 // Plus a lock if needed
1701
1702 if (method->is_synchronized()) {
1703 lock_slot_offset = stack_slots;
1704 stack_slots += VMRegImpl::slots_per_word;
1705 }
1706
1707 // Now a place (+2) to save return values or temp during shuffling
1708 // + 4 for return address (which we own) and saved rbp
1709 stack_slots += 6;
1710
1711 // Ok The space we have allocated will look like:
1712 //
1713 //
1714 // FP-> | |
1715 // |---------------------|
1716 // | 2 slots for moves |
1717 // |---------------------|
1718 // | lock box (if sync) |
1719 // |---------------------| <- lock_slot_offset
1720 // | klass (if static) |
1721 // |---------------------| <- klass_slot_offset
1722 // | oopHandle area |
1723 // |---------------------| <- oop_handle_offset (6 java arg registers)
1724 // | outbound memory |
1725 // | based arguments |
1726 // | |
1727 // |---------------------|
1728 // | |
1729 // SP-> | out_preserved_slots |
1730 //
1731 //
1732
1733
1734 // Now compute actual number of stack words we need rounding to make
1735 // stack properly aligned.
1736 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1737
1738 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1739
1740 // First thing make an ic check to see if we should even be here
1741
1742 // We are free to use all registers as temps without saving them and
1743 // restoring them except rbp. rbp is the only callee save register
1744 // as far as the interpreter and the compiler(s) are concerned.
1745
1746
1747 const Register ic_reg = rax;
1748 const Register receiver = j_rarg0;
1749
1750 Label hit;
1751 Label exception_pending;
1752
1753 assert_different_registers(ic_reg, receiver, rscratch1);
1754 __ verify_oop(receiver);
1755 __ load_klass(rscratch1, receiver);
1756 __ cmpq(ic_reg, rscratch1);
1757 __ jcc(Assembler::equal, hit);
1758
1759 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1760
1761 // Verified entry point must be aligned
1762 __ align(8);
1763
1764 __ bind(hit);
1765
1766 int vep_offset = ((intptr_t)__ pc()) - start;
1767
1768 // The instruction at the verified entry point must be 5 bytes or longer
1769 // because it can be patched on the fly by make_non_entrant. The stack bang
1770 // instruction fits that requirement.
1771
1772 // Generate stack overflow check
1773
1774 if (UseStackBanging) {
1775 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1776 } else {
1777 // need a 5 byte instruction to allow MT safe patching to non-entrant
1778 __ fat_nop();
1779 }
1780
1781 // Generate a new frame for the wrapper.
1782 __ enter();
1783 // -2 because return address is already present and so is saved rbp
1784 __ subptr(rsp, stack_size - 2*wordSize);
1785
1786 // Frame is now completed as far as size and linkage.
1787 int frame_complete = ((intptr_t)__ pc()) - start;
1788
1789 #ifdef ASSERT
1790 {
1791 Label L;
1792 __ mov(rax, rsp);
1793 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
1794 __ cmpptr(rax, rsp);
1795 __ jcc(Assembler::equal, L);
1796 __ stop("improperly aligned stack");
1797 __ bind(L);
1798 }
1799 #endif /* ASSERT */
1800
1801
1802 // We use r14 as the oop handle for the receiver/klass
1803 // It is callee save so it survives the call to native
1804
1805 const Register oop_handle_reg = r14;
1806
1807 if (is_critical_native) {
1808 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
1809 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
1810 }
1811
1812 //
1813 // We immediately shuffle the arguments so that any vm call we have to
1814 // make from here on out (sync slow path, jvmti, etc.) we will have
1815 // captured the oops from our caller and have a valid oopMap for
1816 // them.
1817
1818 // -----------------
1819 // The Grand Shuffle
1820
1821 // The Java calling convention is either equal (linux) or denser (win64) than the
1822 // c calling convention. However the because of the jni_env argument the c calling
1823 // convention always has at least one more (and two for static) arguments than Java.
1824 // Therefore if we move the args from java -> c backwards then we will never have
1825 // a register->register conflict and we don't have to build a dependency graph
1826 // and figure out how to break any cycles.
1827 //
1828
1829 // Record esp-based slot for receiver on stack for non-static methods
1830 int receiver_offset = -1;
1831
1832 // This is a trick. We double the stack slots so we can claim
1833 // the oops in the caller's frame. Since we are sure to have
1834 // more args than the caller doubling is enough to make
1835 // sure we can capture all the incoming oop args from the
1836 // caller.
1837 //
1838 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1839
1840 // Mark location of rbp (someday)
1841 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
1842
1843 // Use eax, ebx as temporaries during any memory-memory moves we have to do
1844 // All inbound args are referenced based on rbp and all outbound args via rsp.
1845
1846
1847 #ifdef ASSERT
1848 bool reg_destroyed[RegisterImpl::number_of_registers];
1849 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
1850 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
1851 reg_destroyed[r] = false;
1852 }
1853 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
1854 freg_destroyed[f] = false;
1855 }
1856
1857 #endif /* ASSERT */
1858
1859 // This may iterate in two different directions depending on the
1860 // kind of native it is. The reason is that for regular JNI natives
1861 // the incoming and outgoing registers are offset upwards and for
1862 // critical natives they are offset down.
1863 GrowableArray<int> arg_order(2 * total_in_args);
1864 VMRegPair tmp_vmreg;
1865 tmp_vmreg.set1(rbx->as_VMReg());
1866
1867 if (!is_critical_native) {
1868 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1869 arg_order.push(i);
1870 arg_order.push(c_arg);
1871 }
1872 } else {
1873 // Compute a valid move order, using tmp_vmreg to break any cycles
1874 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg);
1875 }
1876
1877 int temploc = -1;
1878 for (int ai = 0; ai < arg_order.length(); ai += 2) {
1879 int i = arg_order.at(ai);
1880 int c_arg = arg_order.at(ai + 1);
1881 __ block_comment(err_msg("move %d -> %d", i, c_arg));
1882 if (c_arg == -1) {
1883 assert(is_critical_native, "should only be required for critical natives");
1884 // This arg needs to be moved to a temporary
1885 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register());
1886 in_regs[i] = tmp_vmreg;
1887 temploc = i;
1888 continue;
1889 } else if (i == -1) {
1890 assert(is_critical_native, "should only be required for critical natives");
1891 // Read from the temporary location
1892 assert(temploc != -1, "must be valid");
1893 i = temploc;
1894 temploc = -1;
1895 }
1896 #ifdef ASSERT
1897 if (in_regs[i].first()->is_Register()) {
1898 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
1899 } else if (in_regs[i].first()->is_XMMRegister()) {
1900 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
1901 }
1902 if (out_regs[c_arg].first()->is_Register()) {
1903 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1904 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1905 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1906 }
1907 #endif /* ASSERT */
1908 switch (in_sig_bt[i]) {
1909 case T_ARRAY:
1910 if (is_critical_native) {
1911 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
1912 c_arg++;
1913 #ifdef ASSERT
1914 if (out_regs[c_arg].first()->is_Register()) {
1915 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1916 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1917 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1918 }
1919 #endif
1920 break;
1921 }
1922 case T_OBJECT:
1923 assert(!is_critical_native, "no oop arguments");
1924 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1925 ((i == 0) && (!is_static)),
1926 &receiver_offset);
1927 break;
1928 case T_VOID:
1929 break;
1930
1931 case T_FLOAT:
1932 float_move(masm, in_regs[i], out_regs[c_arg]);
1933 break;
1934
1935 case T_DOUBLE:
1936 assert( i + 1 < total_in_args &&
1937 in_sig_bt[i + 1] == T_VOID &&
1938 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1939 double_move(masm, in_regs[i], out_regs[c_arg]);
1940 break;
1941
1942 case T_LONG :
1943 long_move(masm, in_regs[i], out_regs[c_arg]);
1944 break;
1945
1946 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
1947
1948 default:
1949 move32_64(masm, in_regs[i], out_regs[c_arg]);
1950 }
1951 }
1952
1953 // point c_arg at the first arg that is already loaded in case we
1954 // need to spill before we call out
1955 int c_arg = total_c_args - total_in_args;
1956
1957 // Pre-load a static method's oop into r14. Used both by locking code and
1958 // the normal JNI call code.
1959 if (method->is_static() && !is_critical_native) {
1960
1961 // load oop into a register
1962 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
1963
1964 // Now handlize the static class mirror it's known not-null.
1965 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
1966 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
1967
1968 // Now get the handle
1969 __ lea(oop_handle_reg, Address(rsp, klass_offset));
1970 // store the klass handle as second argument
1971 __ movptr(c_rarg1, oop_handle_reg);
1972 // and protect the arg if we must spill
1973 c_arg--;
1974 }
1975
1976 // Change state to native (we save the return address in the thread, since it might not
1977 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
1978 // points into the right code segment. It does not have to be the correct return pc.
1979 // We use the same pc/oopMap repeatedly when we call out
1980
1981 intptr_t the_pc = (intptr_t) __ pc();
1982 oop_maps->add_gc_map(the_pc - start, map);
1983
1984 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
1985
1986
1987 // We have all of the arguments setup at this point. We must not touch any register
1988 // argument registers at this point (what if we save/restore them there are no oop?
1989
1990 {
1991 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1992 // protect the args we've loaded
1993 save_args(masm, total_c_args, c_arg, out_regs);
1994 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1995 __ call_VM_leaf(
1996 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
1997 r15_thread, c_rarg1);
1998 restore_args(masm, total_c_args, c_arg, out_regs);
1999 }
2000
2001 // RedefineClasses() tracing support for obsolete method entry
2002 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2003 // protect the args we've loaded
2004 save_args(masm, total_c_args, c_arg, out_regs);
2005 __ movoop(c_rarg1, JNIHandles::make_local(method()));
2006 __ call_VM_leaf(
2007 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2008 r15_thread, c_rarg1);
2009 restore_args(masm, total_c_args, c_arg, out_regs);
2010 }
2011
2012 // Lock a synchronized method
2013
2014 // Register definitions used by locking and unlocking
2015
2016 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
2017 const Register obj_reg = rbx; // Will contain the oop
2018 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
2019 const Register old_hdr = r13; // value of old header at unlock time
2020
2021 Label slow_path_lock;
2022 Label lock_done;
2023
2024 if (method->is_synchronized()) {
2025 assert(!is_critical_native, "unhandled");
2026
2027
2028 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2029
2030 // Get the handle (the 2nd argument)
2031 __ mov(oop_handle_reg, c_rarg1);
2032
2033 // Get address of the box
2034
2035 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2036
2037 // Load the oop from the handle
2038 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2039
2040 if (UseBiasedLocking) {
2041 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
2042 }
2043
2044 // Load immediate 1 into swap_reg %rax
2045 __ movl(swap_reg, 1);
2046
2047 // Load (object->mark() | 1) into swap_reg %rax
2048 __ orptr(swap_reg, Address(obj_reg, 0));
2049
2050 // Save (object->mark() | 1) into BasicLock's displaced header
2051 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2052
2053 if (os::is_MP()) {
2054 __ lock();
2055 }
2056
2057 // src -> dest iff dest == rax else rax <- dest
2058 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
2059 __ jcc(Assembler::equal, lock_done);
2060
2061 // Hmm should this move to the slow path code area???
2062
2063 // Test if the oopMark is an obvious stack pointer, i.e.,
2064 // 1) (mark & 3) == 0, and
2065 // 2) rsp <= mark < mark + os::pagesize()
2066 // These 3 tests can be done by evaluating the following
2067 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2068 // assuming both stack pointer and pagesize have their
2069 // least significant 2 bits clear.
2070 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2071
2072 __ subptr(swap_reg, rsp);
2073 __ andptr(swap_reg, 3 - os::vm_page_size());
2074
2075 // Save the test result, for recursive case, the result is zero
2076 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2077 __ jcc(Assembler::notEqual, slow_path_lock);
2078
2079 // Slow path will re-enter here
2080
2081 __ bind(lock_done);
2082 }
2083
2084
2085 // Finally just about ready to make the JNI call
2086
2087
2088 // get JNIEnv* which is first argument to native
2089 if (!is_critical_native) {
2090 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
2091 }
2092
2093 // Now set thread in native
2094 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2095
2096 __ call(RuntimeAddress(native_func));
2097
2098 // Either restore the MXCSR register after returning from the JNI Call
2099 // or verify that it wasn't changed.
2100 if (RestoreMXCSROnJNICalls) {
2101 __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
2102
2103 }
2104 else if (CheckJNICalls ) {
2105 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
2106 }
2107
2108
2109 // Unpack native results.
2110 switch (ret_type) {
2111 case T_BOOLEAN: __ c2bool(rax); break;
2112 case T_CHAR : __ movzwl(rax, rax); break;
2113 case T_BYTE : __ sign_extend_byte (rax); break;
2114 case T_SHORT : __ sign_extend_short(rax); break;
2115 case T_INT : /* nothing to do */ break;
2116 case T_DOUBLE :
2117 case T_FLOAT :
2118 // Result is in xmm0 we'll save as needed
2119 break;
2120 case T_ARRAY: // Really a handle
2121 case T_OBJECT: // Really a handle
2122 break; // can't de-handlize until after safepoint check
2123 case T_VOID: break;
2124 case T_LONG: break;
2125 default : ShouldNotReachHere();
2126 }
2127
2128 // Switch thread to "native transition" state before reading the synchronization state.
2129 // This additional state is necessary because reading and testing the synchronization
2130 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2131 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2132 // VM thread changes sync state to synchronizing and suspends threads for GC.
2133 // Thread A is resumed to finish this native method, but doesn't block here since it
2134 // didn't see any synchronization is progress, and escapes.
2135 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2136
2137 if(os::is_MP()) {
2138 if (UseMembar) {
2139 // Force this write out before the read below
2140 __ membar(Assembler::Membar_mask_bits(
2141 Assembler::LoadLoad | Assembler::LoadStore |
2142 Assembler::StoreLoad | Assembler::StoreStore));
2143 } else {
2144 // Write serialization page so VM thread can do a pseudo remote membar.
2145 // We use the current thread pointer to calculate a thread specific
2146 // offset to write to within the page. This minimizes bus traffic
2147 // due to cache line collision.
2148 __ serialize_memory(r15_thread, rcx);
2149 }
2150 }
2151
2152 Label after_transition;
2153
2154 // check for safepoint operation in progress and/or pending suspend requests
2155 {
2156 Label Continue;
2157
2158 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
2159 SafepointSynchronize::_not_synchronized);
2160
2161 Label L;
2162 __ jcc(Assembler::notEqual, L);
2163 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
2164 __ jcc(Assembler::equal, Continue);
2165 __ bind(L);
2166
2167 // Don't use call_VM as it will see a possible pending exception and forward it
2168 // and never return here preventing us from clearing _last_native_pc down below.
2169 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2170 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2171 // by hand.
2172 //
2173 save_native_result(masm, ret_type, stack_slots);
2174 __ mov(c_rarg0, r15_thread);
2175 __ mov(r12, rsp); // remember sp
2176 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2177 __ andptr(rsp, -16); // align stack as required by ABI
2178 if (!is_critical_native) {
2179 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2180 } else {
2181 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2182 }
2183 __ mov(rsp, r12); // restore sp
2184 __ reinit_heapbase();
2185 // Restore any method result value
2186 restore_native_result(masm, ret_type, stack_slots);
2187
2188 if (is_critical_native) {
2189 // The call above performed the transition to thread_in_Java so
2190 // skip the transition logic below.
2191 __ jmpb(after_transition);
2192 }
2193
2194 __ bind(Continue);
2195 }
2196
2197 // change thread state
2198 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2199 __ bind(after_transition);
2200
2201 Label reguard;
2202 Label reguard_done;
2203 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
2204 __ jcc(Assembler::equal, reguard);
2205 __ bind(reguard_done);
2206
2207 // native result if any is live
2208
2209 // Unlock
2210 Label unlock_done;
2211 Label slow_path_unlock;
2212 if (method->is_synchronized()) {
2213
2214 // Get locked oop from the handle we passed to jni
2215 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2216
2217 Label done;
2218
2219 if (UseBiasedLocking) {
2220 __ biased_locking_exit(obj_reg, old_hdr, done);
2221 }
2222
2223 // Simple recursive lock?
2224
2225 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2226 __ jcc(Assembler::equal, done);
2227
2228 // Must save rax if if it is live now because cmpxchg must use it
2229 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2230 save_native_result(masm, ret_type, stack_slots);
2231 }
2232
2233
2234 // get address of the stack lock
2235 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2236 // get old displaced header
2237 __ movptr(old_hdr, Address(rax, 0));
2238
2239 // Atomic swap old header if oop still contains the stack lock
2240 if (os::is_MP()) {
2241 __ lock();
2242 }
2243 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
2244 __ jcc(Assembler::notEqual, slow_path_unlock);
2245
2246 // slow path re-enters here
2247 __ bind(unlock_done);
2248 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2249 restore_native_result(masm, ret_type, stack_slots);
2250 }
2251
2252 __ bind(done);
2253
2254 }
2255 {
2256 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2257 save_native_result(masm, ret_type, stack_slots);
2258 __ movoop(c_rarg1, JNIHandles::make_local(method()));
2259 __ call_VM_leaf(
2260 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2261 r15_thread, c_rarg1);
2262 restore_native_result(masm, ret_type, stack_slots);
2263 }
2264
2265 __ reset_last_Java_frame(false, true);
2266
2267 // Unpack oop result
2268 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2269 Label L;
2270 __ testptr(rax, rax);
2271 __ jcc(Assembler::zero, L);
2272 __ movptr(rax, Address(rax, 0));
2273 __ bind(L);
2274 __ verify_oop(rax);
2275 }
2276
2277 if (!is_critical_native) {
2278 // reset handle block
2279 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2280 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2281 }
2282
2283 // pop our frame
2284
2285 __ leave();
2286
2287 if (!is_critical_native) {
2288 // Any exception pending?
2289 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2290 __ jcc(Assembler::notEqual, exception_pending);
2291 }
2292
2293 // Return
2294
2295 __ ret(0);
2296
2297 // Unexpected paths are out of line and go here
2298
2299 if (!is_critical_native) {
2300 // forward the exception
2301 __ bind(exception_pending);
2302
2303 // and forward the exception
2304 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2305 }
2306
2307 // Slow path locking & unlocking
2308 if (method->is_synchronized()) {
2309
2310 // BEGIN Slow path lock
2311 __ bind(slow_path_lock);
2312
2313 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2314 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2315
2316 // protect the args we've loaded
2317 save_args(masm, total_c_args, c_arg, out_regs);
2318
2319 __ mov(c_rarg0, obj_reg);
2320 __ mov(c_rarg1, lock_reg);
2321 __ mov(c_rarg2, r15_thread);
2322
2323 // Not a leaf but we have last_Java_frame setup as we want
2324 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2325 restore_args(masm, total_c_args, c_arg, out_regs);
2326
2327 #ifdef ASSERT
2328 { Label L;
2329 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2330 __ jcc(Assembler::equal, L);
2331 __ stop("no pending exception allowed on exit from monitorenter");
2332 __ bind(L);
2333 }
2334 #endif
2335 __ jmp(lock_done);
2336
2337 // END Slow path lock
2338
2339 // BEGIN Slow path unlock
2340 __ bind(slow_path_unlock);
2341
2342 // If we haven't already saved the native result we must save it now as xmm registers
2343 // are still exposed.
2344
2345 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2346 save_native_result(masm, ret_type, stack_slots);
2347 }
2348
2349 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2350
2351 __ mov(c_rarg0, obj_reg);
2352 __ mov(r12, rsp); // remember sp
2353 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2354 __ andptr(rsp, -16); // align stack as required by ABI
2355
2356 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2357 // NOTE that obj_reg == rbx currently
2358 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2359 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2360
2361 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2362 __ mov(rsp, r12); // restore sp
2363 __ reinit_heapbase();
2364 #ifdef ASSERT
2365 {
2366 Label L;
2367 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2368 __ jcc(Assembler::equal, L);
2369 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2370 __ bind(L);
2371 }
2372 #endif /* ASSERT */
2373
2374 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2375
2376 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2377 restore_native_result(masm, ret_type, stack_slots);
2378 }
2379 __ jmp(unlock_done);
2380
2381 // END Slow path unlock
2382
2383 } // synchronized
2384
2385 // SLOW PATH Reguard the stack if needed
2386
2387 __ bind(reguard);
2388 save_native_result(masm, ret_type, stack_slots);
2389 __ mov(r12, rsp); // remember sp
2390 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2391 __ andptr(rsp, -16); // align stack as required by ABI
2392 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2393 __ mov(rsp, r12); // restore sp
2394 __ reinit_heapbase();
2395 restore_native_result(masm, ret_type, stack_slots);
2396 // and continue
2397 __ jmp(reguard_done);
2398
2399
2400
2401 __ flush();
2402
2403 nmethod *nm = nmethod::new_native_nmethod(method,
2404 compile_id,
2405 masm->code(),
2406 vep_offset,
2407 frame_complete,
2408 stack_slots / VMRegImpl::slots_per_word,
2409 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2410 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2411 oop_maps);
2412
2413 if (is_critical_native) {
2414 nm->set_lazy_critical_native(true);
2415 }
2416
2417 return nm;
2418
2419 }
2420
2421 #ifdef HAVE_DTRACE_H
2422 // ---------------------------------------------------------------------------
2423 // Generate a dtrace nmethod for a given signature. The method takes arguments
2424 // in the Java compiled code convention, marshals them to the native
2425 // abi and then leaves nops at the position you would expect to call a native
2426 // function. When the probe is enabled the nops are replaced with a trap
2427 // instruction that dtrace inserts and the trace will cause a notification
2428 // to dtrace.
2429 //
2430 // The probes are only able to take primitive types and java/lang/String as
2431 // arguments. No other java types are allowed. Strings are converted to utf8
2432 // strings so that from dtrace point of view java strings are converted to C
2433 // strings. There is an arbitrary fixed limit on the total space that a method
2434 // can use for converting the strings. (256 chars per string in the signature).
2435 // So any java string larger then this is truncated.
2436
2437 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2438 static bool offsets_initialized = false;
2439
2440
2441 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
2442 methodHandle method) {
2443
2444
2445 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2446 // be single threaded in this method.
2447 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2448
2449 if (!offsets_initialized) {
2450 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
2451 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
2452 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
2453 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
2454 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
2455 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
2456
2457 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
2458 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
2459 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
2460 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
2461 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
2462 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
2463 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
2464 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
2465
2466 offsets_initialized = true;
2467 }
2468 // Fill in the signature array, for the calling-convention call.
2469 int total_args_passed = method->size_of_parameters();
2470
2471 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2472 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2473
2474 // The signature we are going to use for the trap that dtrace will see
2475 // java/lang/String is converted. We drop "this" and any other object
2476 // is converted to NULL. (A one-slot java/lang/Long object reference
2477 // is converted to a two-slot long, which is why we double the allocation).
2478 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2479 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2480
2481 int i=0;
2482 int total_strings = 0;
2483 int first_arg_to_pass = 0;
2484 int total_c_args = 0;
2485
2486 // Skip the receiver as dtrace doesn't want to see it
2487 if( !method->is_static() ) {
2488 in_sig_bt[i++] = T_OBJECT;
2489 first_arg_to_pass = 1;
2490 }
2491
2492 // We need to convert the java args to where a native (non-jni) function
2493 // would expect them. To figure out where they go we convert the java
2494 // signature to a C signature.
2495
2496 SignatureStream ss(method->signature());
2497 for ( ; !ss.at_return_type(); ss.next()) {
2498 BasicType bt = ss.type();
2499 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2500 out_sig_bt[total_c_args++] = bt;
2501 if( bt == T_OBJECT) {
2502 Symbol* s = ss.as_symbol_or_null(); // symbol is created
2503 if (s == vmSymbols::java_lang_String()) {
2504 total_strings++;
2505 out_sig_bt[total_c_args-1] = T_ADDRESS;
2506 } else if (s == vmSymbols::java_lang_Boolean() ||
2507 s == vmSymbols::java_lang_Character() ||
2508 s == vmSymbols::java_lang_Byte() ||
2509 s == vmSymbols::java_lang_Short() ||
2510 s == vmSymbols::java_lang_Integer() ||
2511 s == vmSymbols::java_lang_Float()) {
2512 out_sig_bt[total_c_args-1] = T_INT;
2513 } else if (s == vmSymbols::java_lang_Long() ||
2514 s == vmSymbols::java_lang_Double()) {
2515 out_sig_bt[total_c_args-1] = T_LONG;
2516 out_sig_bt[total_c_args++] = T_VOID;
2517 }
2518 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2519 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2520 // We convert double to long
2521 out_sig_bt[total_c_args-1] = T_LONG;
2522 out_sig_bt[total_c_args++] = T_VOID;
2523 } else if ( bt == T_FLOAT) {
2524 // We convert float to int
2525 out_sig_bt[total_c_args-1] = T_INT;
2526 }
2527 }
2528
2529 assert(i==total_args_passed, "validly parsed signature");
2530
2531 // Now get the compiled-Java layout as input arguments
2532 int comp_args_on_stack;
2533 comp_args_on_stack = SharedRuntime::java_calling_convention(
2534 in_sig_bt, in_regs, total_args_passed, false);
2535
2536 // Now figure out where the args must be stored and how much stack space
2537 // they require (neglecting out_preserve_stack_slots but space for storing
2538 // the 1st six register arguments). It's weird see int_stk_helper.
2539
2540 int out_arg_slots;
2541 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2542
2543 // Calculate the total number of stack slots we will need.
2544
2545 // First count the abi requirement plus all of the outgoing args
2546 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2547
2548 // Now space for the string(s) we must convert
2549 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2550 for (i = 0; i < total_strings ; i++) {
2551 string_locs[i] = stack_slots;
2552 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2553 }
2554
2555 // Plus the temps we might need to juggle register args
2556 // regs take two slots each
2557 stack_slots += (Argument::n_int_register_parameters_c +
2558 Argument::n_float_register_parameters_c) * 2;
2559
2560
2561 // + 4 for return address (which we own) and saved rbp,
2562
2563 stack_slots += 4;
2564
2565 // Ok The space we have allocated will look like:
2566 //
2567 //
2568 // FP-> | |
2569 // |---------------------|
2570 // | string[n] |
2571 // |---------------------| <- string_locs[n]
2572 // | string[n-1] |
2573 // |---------------------| <- string_locs[n-1]
2574 // | ... |
2575 // | ... |
2576 // |---------------------| <- string_locs[1]
2577 // | string[0] |
2578 // |---------------------| <- string_locs[0]
2579 // | outbound memory |
2580 // | based arguments |
2581 // | |
2582 // |---------------------|
2583 // | |
2584 // SP-> | out_preserved_slots |
2585 //
2586 //
2587
2588 // Now compute actual number of stack words we need rounding to make
2589 // stack properly aligned.
2590 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2591
2592 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2593
2594 intptr_t start = (intptr_t)__ pc();
2595
2596 // First thing make an ic check to see if we should even be here
2597
2598 // We are free to use all registers as temps without saving them and
2599 // restoring them except rbp. rbp, is the only callee save register
2600 // as far as the interpreter and the compiler(s) are concerned.
2601
2602 const Register ic_reg = rax;
2603 const Register receiver = rcx;
2604 Label hit;
2605 Label exception_pending;
2606
2607
2608 __ verify_oop(receiver);
2609 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2610 __ jcc(Assembler::equal, hit);
2611
2612 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2613
2614 // verified entry must be aligned for code patching.
2615 // and the first 5 bytes must be in the same cache line
2616 // if we align at 8 then we will be sure 5 bytes are in the same line
2617 __ align(8);
2618
2619 __ bind(hit);
2620
2621 int vep_offset = ((intptr_t)__ pc()) - start;
2622
2623
2624 // The instruction at the verified entry point must be 5 bytes or longer
2625 // because it can be patched on the fly by make_non_entrant. The stack bang
2626 // instruction fits that requirement.
2627
2628 // Generate stack overflow check
2629
2630 if (UseStackBanging) {
2631 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2632 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2633 } else {
2634 __ movl(rax, stack_size);
2635 __ bang_stack_size(rax, rbx);
2636 }
2637 } else {
2638 // need a 5 byte instruction to allow MT safe patching to non-entrant
2639 __ fat_nop();
2640 }
2641
2642 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2643 "valid size for make_non_entrant");
2644
2645 // Generate a new frame for the wrapper.
2646 __ enter();
2647
2648 // -4 because return address is already present and so is saved rbp,
2649 if (stack_size - 2*wordSize != 0) {
2650 __ subq(rsp, stack_size - 2*wordSize);
2651 }
2652
2653 // Frame is now completed as far a size and linkage.
2654
2655 int frame_complete = ((intptr_t)__ pc()) - start;
2656
2657 int c_arg, j_arg;
2658
2659 // State of input register args
2660
2661 bool live[ConcreteRegisterImpl::number_of_registers];
2662
2663 live[j_rarg0->as_VMReg()->value()] = false;
2664 live[j_rarg1->as_VMReg()->value()] = false;
2665 live[j_rarg2->as_VMReg()->value()] = false;
2666 live[j_rarg3->as_VMReg()->value()] = false;
2667 live[j_rarg4->as_VMReg()->value()] = false;
2668 live[j_rarg5->as_VMReg()->value()] = false;
2669
2670 live[j_farg0->as_VMReg()->value()] = false;
2671 live[j_farg1->as_VMReg()->value()] = false;
2672 live[j_farg2->as_VMReg()->value()] = false;
2673 live[j_farg3->as_VMReg()->value()] = false;
2674 live[j_farg4->as_VMReg()->value()] = false;
2675 live[j_farg5->as_VMReg()->value()] = false;
2676 live[j_farg6->as_VMReg()->value()] = false;
2677 live[j_farg7->as_VMReg()->value()] = false;
2678
2679
2680 bool rax_is_zero = false;
2681
2682 // All args (except strings) destined for the stack are moved first
2683 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2684 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2685 VMRegPair src = in_regs[j_arg];
2686 VMRegPair dst = out_regs[c_arg];
2687
2688 // Get the real reg value or a dummy (rsp)
2689
2690 int src_reg = src.first()->is_reg() ?
2691 src.first()->value() :
2692 rsp->as_VMReg()->value();
2693
2694 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2695 (in_sig_bt[j_arg] == T_OBJECT &&
2696 out_sig_bt[c_arg] != T_INT &&
2697 out_sig_bt[c_arg] != T_ADDRESS &&
2698 out_sig_bt[c_arg] != T_LONG);
2699
2700 live[src_reg] = !useless;
2701
2702 if (dst.first()->is_stack()) {
2703
2704 // Even though a string arg in a register is still live after this loop
2705 // after the string conversion loop (next) it will be dead so we take
2706 // advantage of that now for simpler code to manage live.
2707
2708 live[src_reg] = false;
2709 switch (in_sig_bt[j_arg]) {
2710
2711 case T_ARRAY:
2712 case T_OBJECT:
2713 {
2714 Address stack_dst(rsp, reg2offset_out(dst.first()));
2715
2716 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2717 // need to unbox a one-word value
2718 Register in_reg = rax;
2719 if ( src.first()->is_reg() ) {
2720 in_reg = src.first()->as_Register();
2721 } else {
2722 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2723 rax_is_zero = false;
2724 }
2725 Label skipUnbox;
2726 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2727 (int32_t)NULL_WORD);
2728 __ testq(in_reg, in_reg);
2729 __ jcc(Assembler::zero, skipUnbox);
2730
2731 BasicType bt = out_sig_bt[c_arg];
2732 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2733 Address src1(in_reg, box_offset);
2734 if ( bt == T_LONG ) {
2735 __ movq(in_reg, src1);
2736 __ movq(stack_dst, in_reg);
2737 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2738 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2739 } else {
2740 __ movl(in_reg, src1);
2741 __ movl(stack_dst, in_reg);
2742 }
2743
2744 __ bind(skipUnbox);
2745 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2746 // Convert the arg to NULL
2747 if (!rax_is_zero) {
2748 __ xorq(rax, rax);
2749 rax_is_zero = true;
2750 }
2751 __ movq(stack_dst, rax);
2752 }
2753 }
2754 break;
2755
2756 case T_VOID:
2757 break;
2758
2759 case T_FLOAT:
2760 // This does the right thing since we know it is destined for the
2761 // stack
2762 float_move(masm, src, dst);
2763 break;
2764
2765 case T_DOUBLE:
2766 // This does the right thing since we know it is destined for the
2767 // stack
2768 double_move(masm, src, dst);
2769 break;
2770
2771 case T_LONG :
2772 long_move(masm, src, dst);
2773 break;
2774
2775 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2776
2777 default:
2778 move32_64(masm, src, dst);
2779 }
2780 }
2781
2782 }
2783
2784 // If we have any strings we must store any register based arg to the stack
2785 // This includes any still live xmm registers too.
2786
2787 int sid = 0;
2788
2789 if (total_strings > 0 ) {
2790 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2791 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2792 VMRegPair src = in_regs[j_arg];
2793 VMRegPair dst = out_regs[c_arg];
2794
2795 if (src.first()->is_reg()) {
2796 Address src_tmp(rbp, fp_offset[src.first()->value()]);
2797
2798 // string oops were left untouched by the previous loop even if the
2799 // eventual (converted) arg is destined for the stack so park them
2800 // away now (except for first)
2801
2802 if (out_sig_bt[c_arg] == T_ADDRESS) {
2803 Address utf8_addr = Address(
2804 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2805 if (sid != 1) {
2806 // The first string arg won't be killed until after the utf8
2807 // conversion
2808 __ movq(utf8_addr, src.first()->as_Register());
2809 }
2810 } else if (dst.first()->is_reg()) {
2811 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
2812
2813 // Convert the xmm register to an int and store it in the reserved
2814 // location for the eventual c register arg
2815 XMMRegister f = src.first()->as_XMMRegister();
2816 if (in_sig_bt[j_arg] == T_FLOAT) {
2817 __ movflt(src_tmp, f);
2818 } else {
2819 __ movdbl(src_tmp, f);
2820 }
2821 } else {
2822 // If the arg is an oop type we don't support don't bother to store
2823 // it remember string was handled above.
2824 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2825 (in_sig_bt[j_arg] == T_OBJECT &&
2826 out_sig_bt[c_arg] != T_INT &&
2827 out_sig_bt[c_arg] != T_LONG);
2828
2829 if (!useless) {
2830 __ movq(src_tmp, src.first()->as_Register());
2831 }
2832 }
2833 }
2834 }
2835 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2836 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2837 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2838 }
2839 }
2840
2841 // Now that the volatile registers are safe, convert all the strings
2842 sid = 0;
2843
2844 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2845 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2846 if (out_sig_bt[c_arg] == T_ADDRESS) {
2847 // It's a string
2848 Address utf8_addr = Address(
2849 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2850 // The first string we find might still be in the original java arg
2851 // register
2852
2853 VMReg src = in_regs[j_arg].first();
2854
2855 // We will need to eventually save the final argument to the trap
2856 // in the von-volatile location dedicated to src. This is the offset
2857 // from fp we will use.
2858 int src_off = src->is_reg() ?
2859 fp_offset[src->value()] : reg2offset_in(src);
2860
2861 // This is where the argument will eventually reside
2862 VMRegPair dst = out_regs[c_arg];
2863
2864 if (src->is_reg()) {
2865 if (sid == 1) {
2866 __ movq(c_rarg0, src->as_Register());
2867 } else {
2868 __ movq(c_rarg0, utf8_addr);
2869 }
2870 } else {
2871 // arg is still in the original location
2872 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
2873 }
2874 Label done, convert;
2875
2876 // see if the oop is NULL
2877 __ testq(c_rarg0, c_rarg0);
2878 __ jcc(Assembler::notEqual, convert);
2879
2880 if (dst.first()->is_reg()) {
2881 // Save the ptr to utf string in the origina src loc or the tmp
2882 // dedicated to it
2883 __ movq(Address(rbp, src_off), c_rarg0);
2884 } else {
2885 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
2886 }
2887 __ jmp(done);
2888
2889 __ bind(convert);
2890
2891 __ lea(c_rarg1, utf8_addr);
2892 if (dst.first()->is_reg()) {
2893 __ movq(Address(rbp, src_off), c_rarg1);
2894 } else {
2895 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
2896 }
2897 // And do the conversion
2898 __ call(RuntimeAddress(
2899 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
2900
2901 __ bind(done);
2902 }
2903 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2904 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2905 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2906 }
2907 }
2908 // The get_utf call killed all the c_arg registers
2909 live[c_rarg0->as_VMReg()->value()] = false;
2910 live[c_rarg1->as_VMReg()->value()] = false;
2911 live[c_rarg2->as_VMReg()->value()] = false;
2912 live[c_rarg3->as_VMReg()->value()] = false;
2913 live[c_rarg4->as_VMReg()->value()] = false;
2914 live[c_rarg5->as_VMReg()->value()] = false;
2915
2916 live[c_farg0->as_VMReg()->value()] = false;
2917 live[c_farg1->as_VMReg()->value()] = false;
2918 live[c_farg2->as_VMReg()->value()] = false;
2919 live[c_farg3->as_VMReg()->value()] = false;
2920 live[c_farg4->as_VMReg()->value()] = false;
2921 live[c_farg5->as_VMReg()->value()] = false;
2922 live[c_farg6->as_VMReg()->value()] = false;
2923 live[c_farg7->as_VMReg()->value()] = false;
2924 }
2925
2926 // Now we can finally move the register args to their desired locations
2927
2928 rax_is_zero = false;
2929
2930 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2931 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2932
2933 VMRegPair src = in_regs[j_arg];
2934 VMRegPair dst = out_regs[c_arg];
2935
2936 // Only need to look for args destined for the interger registers (since we
2937 // convert float/double args to look like int/long outbound)
2938 if (dst.first()->is_reg()) {
2939 Register r = dst.first()->as_Register();
2940
2941 // Check if the java arg is unsupported and thereofre useless
2942 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2943 (in_sig_bt[j_arg] == T_OBJECT &&
2944 out_sig_bt[c_arg] != T_INT &&
2945 out_sig_bt[c_arg] != T_ADDRESS &&
2946 out_sig_bt[c_arg] != T_LONG);
2947
2948
2949 // If we're going to kill an existing arg save it first
2950 if (live[dst.first()->value()]) {
2951 // you can't kill yourself
2952 if (src.first() != dst.first()) {
2953 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
2954 }
2955 }
2956 if (src.first()->is_reg()) {
2957 if (live[src.first()->value()] ) {
2958 if (in_sig_bt[j_arg] == T_FLOAT) {
2959 __ movdl(r, src.first()->as_XMMRegister());
2960 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
2961 __ movdq(r, src.first()->as_XMMRegister());
2962 } else if (r != src.first()->as_Register()) {
2963 if (!useless) {
2964 __ movq(r, src.first()->as_Register());
2965 }
2966 }
2967 } else {
2968 // If the arg is an oop type we don't support don't bother to store
2969 // it
2970 if (!useless) {
2971 if (in_sig_bt[j_arg] == T_DOUBLE ||
2972 in_sig_bt[j_arg] == T_LONG ||
2973 in_sig_bt[j_arg] == T_OBJECT ) {
2974 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
2975 } else {
2976 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
2977 }
2978 }
2979 }
2980 live[src.first()->value()] = false;
2981 } else if (!useless) {
2982 // full sized move even for int should be ok
2983 __ movq(r, Address(rbp, reg2offset_in(src.first())));
2984 }
2985
2986 // At this point r has the original java arg in the final location
2987 // (assuming it wasn't useless). If the java arg was an oop
2988 // we have a bit more to do
2989
2990 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
2991 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2992 // need to unbox a one-word value
2993 Label skip;
2994 __ testq(r, r);
2995 __ jcc(Assembler::equal, skip);
2996 BasicType bt = out_sig_bt[c_arg];
2997 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2998 Address src1(r, box_offset);
2999 if ( bt == T_LONG ) {
3000 __ movq(r, src1);
3001 } else {
3002 __ movl(r, src1);
3003 }
3004 __ bind(skip);
3005
3006 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
3007 // Convert the arg to NULL
3008 __ xorq(r, r);
3009 }
3010 }
3011
3012 // dst can longer be holding an input value
3013 live[dst.first()->value()] = false;
3014 }
3015 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3016 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3017 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3018 }
3019 }
3020
3021
3022 // Ok now we are done. Need to place the nop that dtrace wants in order to
3023 // patch in the trap
3024 int patch_offset = ((intptr_t)__ pc()) - start;
3025
3026 __ nop();
3027
3028
3029 // Return
3030
3031 __ leave();
3032 __ ret(0);
3033
3034 __ flush();
3035
3036 nmethod *nm = nmethod::new_dtrace_nmethod(
3037 method, masm->code(), vep_offset, patch_offset, frame_complete,
3038 stack_slots / VMRegImpl::slots_per_word);
3039 return nm;
3040
3041 }
3042
3043 #endif // HAVE_DTRACE_H
3044
3045 // this function returns the adjust size (in number of words) to a c2i adapter
3046 // activation for use during deoptimization
3047 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
3048 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3049 }
3050
3051
3052 uint SharedRuntime::out_preserve_stack_slots() {
3053 return 0;
3054 }
3055
3056
3057 //------------------------------generate_deopt_blob----------------------------
3058 void SharedRuntime::generate_deopt_blob() {
3059 // Allocate space for the code
3060 ResourceMark rm;
3061 // Setup code generation tools
3062 CodeBuffer buffer("deopt_blob", 2048, 1024);
3063 MacroAssembler* masm = new MacroAssembler(&buffer);
3064 int frame_size_in_words;
3065 OopMap* map = NULL;
3066 OopMapSet *oop_maps = new OopMapSet();
3067
3068 // -------------
3069 // This code enters when returning to a de-optimized nmethod. A return
3070 // address has been pushed on the the stack, and return values are in
3071 // registers.
3072 // If we are doing a normal deopt then we were called from the patched
3073 // nmethod from the point we returned to the nmethod. So the return
3074 // address on the stack is wrong by NativeCall::instruction_size
3075 // We will adjust the value so it looks like we have the original return
3076 // address on the stack (like when we eagerly deoptimized).
3077 // In the case of an exception pending when deoptimizing, we enter
3078 // with a return address on the stack that points after the call we patched
3079 // into the exception handler. We have the following register state from,
3080 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
3081 // rax: exception oop
3082 // rbx: exception handler
3083 // rdx: throwing pc
3084 // So in this case we simply jam rdx into the useless return address and
3085 // the stack looks just like we want.
3086 //
3087 // At this point we need to de-opt. We save the argument return
3088 // registers. We call the first C routine, fetch_unroll_info(). This
3089 // routine captures the return values and returns a structure which
3090 // describes the current frame size and the sizes of all replacement frames.
3091 // The current frame is compiled code and may contain many inlined
3092 // functions, each with their own JVM state. We pop the current frame, then
3093 // push all the new frames. Then we call the C routine unpack_frames() to
3094 // populate these frames. Finally unpack_frames() returns us the new target
3095 // address. Notice that callee-save registers are BLOWN here; they have
3096 // already been captured in the vframeArray at the time the return PC was
3097 // patched.
3098 address start = __ pc();
3099 Label cont;
3100
3101 // Prolog for non exception case!
3102
3103 // Save everything in sight.
3104 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3105
3106 // Normal deoptimization. Save exec mode for unpack_frames.
3107 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
3108 __ jmp(cont);
3109
3110 int reexecute_offset = __ pc() - start;
3111
3112 // Reexecute case
3113 // return address is the pc describes what bci to do re-execute at
3114
3115 // No need to update map as each call to save_live_registers will produce identical oopmap
3116 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3117
3118 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
3119 __ jmp(cont);
3120
3121 int exception_offset = __ pc() - start;
3122
3123 // Prolog for exception case
3124
3125 // all registers are dead at this entry point, except for rax, and
3126 // rdx which contain the exception oop and exception pc
3127 // respectively. Set them in TLS and fall thru to the
3128 // unpack_with_exception_in_tls entry point.
3129
3130 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3131 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
3132
3133 int exception_in_tls_offset = __ pc() - start;
3134
3135 // new implementation because exception oop is now passed in JavaThread
3136
3137 // Prolog for exception case
3138 // All registers must be preserved because they might be used by LinearScan
3139 // Exceptiop oop and throwing PC are passed in JavaThread
3140 // tos: stack at point of call to method that threw the exception (i.e. only
3141 // args are on the stack, no return address)
3142
3143 // make room on stack for the return address
3144 // It will be patched later with the throwing pc. The correct value is not
3145 // available now because loading it from memory would destroy registers.
3146 __ push(0);
3147
3148 // Save everything in sight.
3149 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3150
3151 // Now it is safe to overwrite any register
3152
3153 // Deopt during an exception. Save exec mode for unpack_frames.
3154 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
3155
3156 // load throwing pc from JavaThread and patch it as the return address
3157 // of the current frame. Then clear the field in JavaThread
3158
3159 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3160 __ movptr(Address(rbp, wordSize), rdx);
3161 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3162
3163 #ifdef ASSERT
3164 // verify that there is really an exception oop in JavaThread
3165 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3166 __ verify_oop(rax);
3167
3168 // verify that there is no pending exception
3169 Label no_pending_exception;
3170 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3171 __ testptr(rax, rax);
3172 __ jcc(Assembler::zero, no_pending_exception);
3173 __ stop("must not have pending exception here");
3174 __ bind(no_pending_exception);
3175 #endif
3176
3177 __ bind(cont);
3178
3179 // Call C code. Need thread and this frame, but NOT official VM entry
3180 // crud. We cannot block on this call, no GC can happen.
3181 //
3182 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3183
3184 // fetch_unroll_info needs to call last_java_frame().
3185
3186 __ set_last_Java_frame(noreg, noreg, NULL);
3187 #ifdef ASSERT
3188 { Label L;
3189 __ cmpptr(Address(r15_thread,
3190 JavaThread::last_Java_fp_offset()),
3191 (int32_t)0);
3192 __ jcc(Assembler::equal, L);
3193 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3194 __ bind(L);
3195 }
3196 #endif // ASSERT
3197 __ mov(c_rarg0, r15_thread);
3198 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3199
3200 // Need to have an oopmap that tells fetch_unroll_info where to
3201 // find any register it might need.
3202 oop_maps->add_gc_map(__ pc() - start, map);
3203
3204 __ reset_last_Java_frame(false, false);
3205
3206 // Load UnrollBlock* into rdi
3207 __ mov(rdi, rax);
3208
3209 Label noException;
3210 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3211 __ jcc(Assembler::notEqual, noException);
3212 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3213 // QQQ this is useless it was NULL above
3214 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3215 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3216 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3217
3218 __ verify_oop(rax);
3219
3220 // Overwrite the result registers with the exception results.
3221 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3222 // I think this is useless
3223 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3224
3225 __ bind(noException);
3226
3227 // Only register save data is on the stack.
3228 // Now restore the result registers. Everything else is either dead
3229 // or captured in the vframeArray.
3230 RegisterSaver::restore_result_registers(masm);
3231
3232 // All of the register save area has been popped of the stack. Only the
3233 // return address remains.
3234
3235 // Pop all the frames we must move/replace.
3236 //
3237 // Frame picture (youngest to oldest)
3238 // 1: self-frame (no frame link)
3239 // 2: deopting frame (no frame link)
3240 // 3: caller of deopting frame (could be compiled/interpreted).
3241 //
3242 // Note: by leaving the return address of self-frame on the stack
3243 // and using the size of frame 2 to adjust the stack
3244 // when we are done the return to frame 3 will still be on the stack.
3245
3246 // Pop deoptimized frame
3247 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3248 __ addptr(rsp, rcx);
3249
3250 // rsp should be pointing at the return address to the caller (3)
3251
3252 // Stack bang to make sure there's enough room for these interpreter frames.
3253 if (UseStackBanging) {
3254 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3255 __ bang_stack_size(rbx, rcx);
3256 }
3257
3258 // Load address of array of frame pcs into rcx
3259 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3260
3261 // Trash the old pc
3262 __ addptr(rsp, wordSize);
3263
3264 // Load address of array of frame sizes into rsi
3265 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3266
3267 // Load counter into rdx
3268 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3269
3270 // Pick up the initial fp we should save
3271 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3272
3273 // Now adjust the caller's stack to make up for the extra locals
3274 // but record the original sp so that we can save it in the skeletal interpreter
3275 // frame and the stack walking of interpreter_sender will get the unextended sp
3276 // value and not the "real" sp value.
3277
3278 const Register sender_sp = r8;
3279
3280 __ mov(sender_sp, rsp);
3281 __ movl(rbx, Address(rdi,
3282 Deoptimization::UnrollBlock::
3283 caller_adjustment_offset_in_bytes()));
3284 __ subptr(rsp, rbx);
3285
3286 // Push interpreter frames in a loop
3287 Label loop;
3288 __ bind(loop);
3289 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3290 #ifdef CC_INTERP
3291 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3292 #ifdef ASSERT
3293 __ push(0xDEADDEAD); // Make a recognizable pattern
3294 __ push(0xDEADDEAD);
3295 #else /* ASSERT */
3296 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3297 #endif /* ASSERT */
3298 #else
3299 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3300 #endif // CC_INTERP
3301 __ pushptr(Address(rcx, 0)); // Save return address
3302 __ enter(); // Save old & set new ebp
3303 __ subptr(rsp, rbx); // Prolog
3304 #ifdef CC_INTERP
3305 __ movptr(Address(rbp,
3306 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3307 sender_sp); // Make it walkable
3308 #else /* CC_INTERP */
3309 // This value is corrected by layout_activation_impl
3310 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3311 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3312 #endif /* CC_INTERP */
3313 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3314 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3315 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3316 __ decrementl(rdx); // Decrement counter
3317 __ jcc(Assembler::notZero, loop);
3318 __ pushptr(Address(rcx, 0)); // Save final return address
3319
3320 // Re-push self-frame
3321 __ enter(); // Save old & set new ebp
3322
3323 // Allocate a full sized register save area.
3324 // Return address and rbp are in place, so we allocate two less words.
3325 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3326
3327 // Restore frame locals after moving the frame
3328 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3329 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3330
3331 // Call C code. Need thread but NOT official VM entry
3332 // crud. We cannot block on this call, no GC can happen. Call should
3333 // restore return values to their stack-slots with the new SP.
3334 //
3335 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3336
3337 // Use rbp because the frames look interpreted now
3338 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3339 // Don't need the precise return PC here, just precise enough to point into this code blob.
3340 address the_pc = __ pc();
3341 __ set_last_Java_frame(noreg, rbp, the_pc);
3342
3343 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3344 __ mov(c_rarg0, r15_thread);
3345 __ movl(c_rarg1, r14); // second arg: exec_mode
3346 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3347 // Revert SP alignment after call since we're going to do some SP relative addressing below
3348 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3349
3350 // Set an oopmap for the call site
3351 // Use the same PC we used for the last java frame
3352 oop_maps->add_gc_map(the_pc - start,
3353 new OopMap( frame_size_in_words, 0 ));
3354
3355 // Clear fp AND pc
3356 __ reset_last_Java_frame(true, true);
3357
3358 // Collect return values
3359 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3360 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3361 // I think this is useless (throwing pc?)
3362 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3363
3364 // Pop self-frame.
3365 __ leave(); // Epilog
3366
3367 // Jump to interpreter
3368 __ ret(0);
3369
3370 // Make sure all code is generated
3371 masm->flush();
3372
3373 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3374 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3375 }
3376
3377 #ifdef COMPILER2
3378 //------------------------------generate_uncommon_trap_blob--------------------
3379 void SharedRuntime::generate_uncommon_trap_blob() {
3380 // Allocate space for the code
3381 ResourceMark rm;
3382 // Setup code generation tools
3383 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3384 MacroAssembler* masm = new MacroAssembler(&buffer);
3385
3386 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3387
3388 address start = __ pc();
3389
3390 // Push self-frame. We get here with a return address on the
3391 // stack, so rsp is 8-byte aligned until we allocate our frame.
3392 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3393
3394 // No callee saved registers. rbp is assumed implicitly saved
3395 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3396
3397 // compiler left unloaded_class_index in j_rarg0 move to where the
3398 // runtime expects it.
3399 __ movl(c_rarg1, j_rarg0);
3400
3401 __ set_last_Java_frame(noreg, noreg, NULL);
3402
3403 // Call C code. Need thread but NOT official VM entry
3404 // crud. We cannot block on this call, no GC can happen. Call should
3405 // capture callee-saved registers as well as return values.
3406 // Thread is in rdi already.
3407 //
3408 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3409
3410 __ mov(c_rarg0, r15_thread);
3411 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3412
3413 // Set an oopmap for the call site
3414 OopMapSet* oop_maps = new OopMapSet();
3415 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3416
3417 // location of rbp is known implicitly by the frame sender code
3418
3419 oop_maps->add_gc_map(__ pc() - start, map);
3420
3421 __ reset_last_Java_frame(false, false);
3422
3423 // Load UnrollBlock* into rdi
3424 __ mov(rdi, rax);
3425
3426 // Pop all the frames we must move/replace.
3427 //
3428 // Frame picture (youngest to oldest)
3429 // 1: self-frame (no frame link)
3430 // 2: deopting frame (no frame link)
3431 // 3: caller of deopting frame (could be compiled/interpreted).
3432
3433 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3434 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3435
3436 // Pop deoptimized frame (int)
3437 __ movl(rcx, Address(rdi,
3438 Deoptimization::UnrollBlock::
3439 size_of_deoptimized_frame_offset_in_bytes()));
3440 __ addptr(rsp, rcx);
3441
3442 // rsp should be pointing at the return address to the caller (3)
3443
3444 // Stack bang to make sure there's enough room for these interpreter frames.
3445 if (UseStackBanging) {
3446 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3447 __ bang_stack_size(rbx, rcx);
3448 }
3449
3450 // Load address of array of frame pcs into rcx (address*)
3451 __ movptr(rcx,
3452 Address(rdi,
3453 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3454
3455 // Trash the return pc
3456 __ addptr(rsp, wordSize);
3457
3458 // Load address of array of frame sizes into rsi (intptr_t*)
3459 __ movptr(rsi, Address(rdi,
3460 Deoptimization::UnrollBlock::
3461 frame_sizes_offset_in_bytes()));
3462
3463 // Counter
3464 __ movl(rdx, Address(rdi,
3465 Deoptimization::UnrollBlock::
3466 number_of_frames_offset_in_bytes())); // (int)
3467
3468 // Pick up the initial fp we should save
3469 __ movptr(rbp,
3470 Address(rdi,
3471 Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3472
3473 // Now adjust the caller's stack to make up for the extra locals but
3474 // record the original sp so that we can save it in the skeletal
3475 // interpreter frame and the stack walking of interpreter_sender
3476 // will get the unextended sp value and not the "real" sp value.
3477
3478 const Register sender_sp = r8;
3479
3480 __ mov(sender_sp, rsp);
3481 __ movl(rbx, Address(rdi,
3482 Deoptimization::UnrollBlock::
3483 caller_adjustment_offset_in_bytes())); // (int)
3484 __ subptr(rsp, rbx);
3485
3486 // Push interpreter frames in a loop
3487 Label loop;
3488 __ bind(loop);
3489 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3490 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3491 __ pushptr(Address(rcx, 0)); // Save return address
3492 __ enter(); // Save old & set new rbp
3493 __ subptr(rsp, rbx); // Prolog
3494 #ifdef CC_INTERP
3495 __ movptr(Address(rbp,
3496 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3497 sender_sp); // Make it walkable
3498 #else // CC_INTERP
3499 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3500 sender_sp); // Make it walkable
3501 // This value is corrected by layout_activation_impl
3502 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3503 #endif // CC_INTERP
3504 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3505 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3506 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3507 __ decrementl(rdx); // Decrement counter
3508 __ jcc(Assembler::notZero, loop);
3509 __ pushptr(Address(rcx, 0)); // Save final return address
3510
3511 // Re-push self-frame
3512 __ enter(); // Save old & set new rbp
3513 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3514 // Prolog
3515
3516 // Use rbp because the frames look interpreted now
3517 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3518 // Don't need the precise return PC here, just precise enough to point into this code blob.
3519 address the_pc = __ pc();
3520 __ set_last_Java_frame(noreg, rbp, the_pc);
3521
3522 // Call C code. Need thread but NOT official VM entry
3523 // crud. We cannot block on this call, no GC can happen. Call should
3524 // restore return values to their stack-slots with the new SP.
3525 // Thread is in rdi already.
3526 //
3527 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3528
3529 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3530 __ mov(c_rarg0, r15_thread);
3531 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3532 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3533
3534 // Set an oopmap for the call site
3535 // Use the same PC we used for the last java frame
3536 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3537
3538 // Clear fp AND pc
3539 __ reset_last_Java_frame(true, true);
3540
3541 // Pop self-frame.
3542 __ leave(); // Epilog
3543
3544 // Jump to interpreter
3545 __ ret(0);
3546
3547 // Make sure all code is generated
3548 masm->flush();
3549
3550 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3551 SimpleRuntimeFrame::framesize >> 1);
3552 }
3553 #endif // COMPILER2
3554
3555
3556 //------------------------------generate_handler_blob------
3557 //
3558 // Generate a special Compile2Runtime blob that saves all registers,
3559 // and setup oopmap.
3560 //
3561 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
3562 assert(StubRoutines::forward_exception_entry() != NULL,
3563 "must be generated before");
3564
3565 ResourceMark rm;
3566 OopMapSet *oop_maps = new OopMapSet();
3567 OopMap* map;
3568
3569 // Allocate space for the code. Setup code generation tools.
3570 CodeBuffer buffer("handler_blob", 2048, 1024);
3571 MacroAssembler* masm = new MacroAssembler(&buffer);
3572
3573 address start = __ pc();
3574 address call_pc = NULL;
3575 int frame_size_in_words;
3576
3577 // Make room for return address (or push it again)
3578 if (!cause_return) {
3579 __ push(rbx);
3580 }
3581
3582 // Save registers, fpu state, and flags
3583 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3584
3585 // The following is basically a call_VM. However, we need the precise
3586 // address of the call in order to generate an oopmap. Hence, we do all the
3587 // work outselves.
3588
3589 __ set_last_Java_frame(noreg, noreg, NULL);
3590
3591 // The return address must always be correct so that frame constructor never
3592 // sees an invalid pc.
3593
3594 if (!cause_return) {
3595 // overwrite the dummy value we pushed on entry
3596 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3597 __ movptr(Address(rbp, wordSize), c_rarg0);
3598 }
3599
3600 // Do the call
3601 __ mov(c_rarg0, r15_thread);
3602 __ call(RuntimeAddress(call_ptr));
3603
3604 // Set an oopmap for the call site. This oopmap will map all
3605 // oop-registers and debug-info registers as callee-saved. This
3606 // will allow deoptimization at this safepoint to find all possible
3607 // debug-info recordings, as well as let GC find all oops.
3608
3609 oop_maps->add_gc_map( __ pc() - start, map);
3610
3611 Label noException;
3612
3613 __ reset_last_Java_frame(false, false);
3614
3615 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3616 __ jcc(Assembler::equal, noException);
3617
3618 // Exception pending
3619
3620 RegisterSaver::restore_live_registers(masm);
3621
3622 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3623
3624 // No exception case
3625 __ bind(noException);
3626
3627 // Normal exit, restore registers and exit.
3628 RegisterSaver::restore_live_registers(masm);
3629
3630 __ ret(0);
3631
3632 // Make sure all code is generated
3633 masm->flush();
3634
3635 // Fill-out other meta info
3636 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3637 }
3638
3639 //
3640 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3641 //
3642 // Generate a stub that calls into vm to find out the proper destination
3643 // of a java call. All the argument registers are live at this point
3644 // but since this is generic code we don't know what they are and the caller
3645 // must do any gc of the args.
3646 //
3647 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3648 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3649
3650 // allocate space for the code
3651 ResourceMark rm;
3652
3653 CodeBuffer buffer(name, 1000, 512);
3654 MacroAssembler* masm = new MacroAssembler(&buffer);
3655
3656 int frame_size_in_words;
3657
3658 OopMapSet *oop_maps = new OopMapSet();
3659 OopMap* map = NULL;
3660
3661 int start = __ offset();
3662
3663 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3664
3665 int frame_complete = __ offset();
3666
3667 __ set_last_Java_frame(noreg, noreg, NULL);
3668
3669 __ mov(c_rarg0, r15_thread);
3670
3671 __ call(RuntimeAddress(destination));
3672
3673
3674 // Set an oopmap for the call site.
3675 // We need this not only for callee-saved registers, but also for volatile
3676 // registers that the compiler might be keeping live across a safepoint.
3677
3678 oop_maps->add_gc_map( __ offset() - start, map);
3679
3680 // rax contains the address we are going to jump to assuming no exception got installed
3681
3682 // clear last_Java_sp
3683 __ reset_last_Java_frame(false, false);
3684 // check for pending exceptions
3685 Label pending;
3686 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3687 __ jcc(Assembler::notEqual, pending);
3688
3689 // get the returned methodOop
3690 __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
3691 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3692
3693 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3694
3695 RegisterSaver::restore_live_registers(masm);
3696
3697 // We are back the the original state on entry and ready to go.
3698
3699 __ jmp(rax);
3700
3701 // Pending exception after the safepoint
3702
3703 __ bind(pending);
3704
3705 RegisterSaver::restore_live_registers(masm);
3706
3707 // exception pending => remove activation and forward to exception handler
3708
3709 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3710
3711 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3712 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3713
3714 // -------------
3715 // make sure all code is generated
3716 masm->flush();
3717
3718 // return the blob
3719 // frame_size_words or bytes??
3720 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3721 }
3722
3723
3724 #ifdef COMPILER2
3725 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3726 //
3727 //------------------------------generate_exception_blob---------------------------
3728 // creates exception blob at the end
3729 // Using exception blob, this code is jumped from a compiled method.
3730 // (see emit_exception_handler in x86_64.ad file)
3731 //
3732 // Given an exception pc at a call we call into the runtime for the
3733 // handler in this method. This handler might merely restore state
3734 // (i.e. callee save registers) unwind the frame and jump to the
3735 // exception handler for the nmethod if there is no Java level handler
3736 // for the nmethod.
3737 //
3738 // This code is entered with a jmp.
3739 //
3740 // Arguments:
3741 // rax: exception oop
3742 // rdx: exception pc
3743 //
3744 // Results:
3745 // rax: exception oop
3746 // rdx: exception pc in caller or ???
3747 // destination: exception handler of caller
3748 //
3749 // Note: the exception pc MUST be at a call (precise debug information)
3750 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3751 //
3752
3753 void OptoRuntime::generate_exception_blob() {
3754 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3755 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3756 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3757
3758 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3759
3760 // Allocate space for the code
3761 ResourceMark rm;
3762 // Setup code generation tools
3763 CodeBuffer buffer("exception_blob", 2048, 1024);
3764 MacroAssembler* masm = new MacroAssembler(&buffer);
3765
3766
3767 address start = __ pc();
3768
3769 // Exception pc is 'return address' for stack walker
3770 __ push(rdx);
3771 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3772
3773 // Save callee-saved registers. See x86_64.ad.
3774
3775 // rbp is an implicitly saved callee saved register (i.e. the calling
3776 // convention will save restore it in prolog/epilog) Other than that
3777 // there are no callee save registers now that adapter frames are gone.
3778
3779 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3780
3781 // Store exception in Thread object. We cannot pass any arguments to the
3782 // handle_exception call, since we do not want to make any assumption
3783 // about the size of the frame where the exception happened in.
3784 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3785 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3786 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3787
3788 // This call does all the hard work. It checks if an exception handler
3789 // exists in the method.
3790 // If so, it returns the handler address.
3791 // If not, it prepares for stack-unwinding, restoring the callee-save
3792 // registers of the frame being removed.
3793 //
3794 // address OptoRuntime::handle_exception_C(JavaThread* thread)
3795
3796 __ set_last_Java_frame(noreg, noreg, NULL);
3797 __ mov(c_rarg0, r15_thread);
3798 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
3799
3800 // Set an oopmap for the call site. This oopmap will only be used if we
3801 // are unwinding the stack. Hence, all locations will be dead.
3802 // Callee-saved registers will be the same as the frame above (i.e.,
3803 // handle_exception_stub), since they were restored when we got the
3804 // exception.
3805
3806 OopMapSet* oop_maps = new OopMapSet();
3807
3808 oop_maps->add_gc_map( __ pc()-start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3809
3810 __ reset_last_Java_frame(false, false);
3811
3812 // Restore callee-saved registers
3813
3814 // rbp is an implicitly saved callee saved register (i.e. the calling
3815 // convention will save restore it in prolog/epilog) Other than that
3816 // there are no callee save registers no that adapter frames are gone.
3817
3818 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
3819
3820 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
3821 __ pop(rdx); // No need for exception pc anymore
3822
3823 // rax: exception handler
3824
3825 // Restore SP from BP if the exception PC is a MethodHandle call site.
3826 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0);
3827 __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
3828
3829 // We have a handler in rax (could be deopt blob).
3830 __ mov(r8, rax);
3831
3832 // Get the exception oop
3833 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3834 // Get the exception pc in case we are deoptimized
3835 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3836 #ifdef ASSERT
3837 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
3838 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
3839 #endif
3840 // Clear the exception oop so GC no longer processes it as a root.
3841 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
3842
3843 // rax: exception oop
3844 // r8: exception handler
3845 // rdx: exception pc
3846 // Jump to handler
3847
3848 __ jmp(r8);
3849
3850 // Make sure all code is generated
3851 masm->flush();
3852
3853 // Set exception blob
3854 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3855 }
3856 #endif // COMPILER2