src/cpu/x86/vm/x86_64.ad
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src/cpu/x86/vm/x86_64.ad

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3352 operand immP()
3353 %{
3354   match(ConP);
3355 
3356   op_cost(10);
3357   format %{ %}
3358   interface(CONST_INTER);
3359 %}
3360 
3361 // NULL Pointer Immediate
3362 operand immP0()
3363 %{
3364   predicate(n->get_ptr() == 0);
3365   match(ConP);
3366 
3367   op_cost(5);
3368   format %{ %}
3369   interface(CONST_INTER);
3370 %}
3371 
3372 operand immP_poll() %{
3373   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3374   match(ConP);
3375 
3376   // formats are generated automatically for constants and base registers
3377   format %{ %}
3378   interface(CONST_INTER);
3379 %}
3380 
3381 // Pointer Immediate
3382 operand immN() %{
3383   match(ConN);
3384 
3385   op_cost(10);
3386   format %{ %}
3387   interface(CONST_INTER);
3388 %}
3389 
3390 // NULL Pointer Immediate
3391 operand immN0() %{
3392   predicate(n->get_narrowcon() == 0);
3393   match(ConN);
3394 
3395   op_cost(5);
3396   format %{ %}
3397   interface(CONST_INTER);
3398 %}
3399 
3400 operand immP31()


5709 instruct loadConP(rRegP dst, immP con) %{
5710   match(Set dst con);
5711 
5712   format %{ "movq    $dst, $con\t# ptr" %}
5713   ins_encode(load_immP(dst, con));
5714   ins_pipe(ialu_reg_fat); // XXX
5715 %}
5716 
5717 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5718 %{
5719   match(Set dst src);
5720   effect(KILL cr);
5721 
5722   ins_cost(50);
5723   format %{ "xorl    $dst, $dst\t# ptr" %}
5724   opcode(0x33); /* + rd */
5725   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5726   ins_pipe(ialu_reg);
5727 %}
5728 
5729 instruct loadConP_poll(rRegP dst, immP_poll src) %{
5730   match(Set dst src);
5731   format %{ "movq    $dst, $src\t!ptr" %}
5732   ins_encode %{
5733     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
5734     __ lea($dst$$Register, polling_page);
5735   %}
5736   ins_pipe(ialu_reg_fat);
5737 %}
5738 
5739 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5740 %{
5741   match(Set dst src);
5742   effect(KILL cr);
5743 
5744   ins_cost(60);
5745   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
5746   ins_encode(load_immP31(dst, src));
5747   ins_pipe(ialu_reg);
5748 %}
5749 
5750 instruct loadConF(regF dst, immF con) %{
5751   match(Set dst con);
5752   ins_cost(125);
5753   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5754   ins_encode %{
5755     __ movflt($dst$$XMMRegister, $constantaddress($con));
5756   %}
5757   ins_pipe(pipe_slow);
5758 %}




3352 operand immP()
3353 %{
3354   match(ConP);
3355 
3356   op_cost(10);
3357   format %{ %}
3358   interface(CONST_INTER);
3359 %}
3360 
3361 // NULL Pointer Immediate
3362 operand immP0()
3363 %{
3364   predicate(n->get_ptr() == 0);
3365   match(ConP);
3366 
3367   op_cost(5);
3368   format %{ %}
3369   interface(CONST_INTER);
3370 %}
3371 









3372 // Pointer Immediate
3373 operand immN() %{
3374   match(ConN);
3375 
3376   op_cost(10);
3377   format %{ %}
3378   interface(CONST_INTER);
3379 %}
3380 
3381 // NULL Pointer Immediate
3382 operand immN0() %{
3383   predicate(n->get_narrowcon() == 0);
3384   match(ConN);
3385 
3386   op_cost(5);
3387   format %{ %}
3388   interface(CONST_INTER);
3389 %}
3390 
3391 operand immP31()


5700 instruct loadConP(rRegP dst, immP con) %{
5701   match(Set dst con);
5702 
5703   format %{ "movq    $dst, $con\t# ptr" %}
5704   ins_encode(load_immP(dst, con));
5705   ins_pipe(ialu_reg_fat); // XXX
5706 %}
5707 
5708 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5709 %{
5710   match(Set dst src);
5711   effect(KILL cr);
5712 
5713   ins_cost(50);
5714   format %{ "xorl    $dst, $dst\t# ptr" %}
5715   opcode(0x33); /* + rd */
5716   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5717   ins_pipe(ialu_reg);
5718 %}
5719 










5720 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5721 %{
5722   match(Set dst src);
5723   effect(KILL cr);
5724 
5725   ins_cost(60);
5726   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
5727   ins_encode(load_immP31(dst, src));
5728   ins_pipe(ialu_reg);
5729 %}
5730 
5731 instruct loadConF(regF dst, immF con) %{
5732   match(Set dst con);
5733   ins_cost(125);
5734   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5735   ins_encode %{
5736     __ movflt($dst$$XMMRegister, $constantaddress($con));
5737   %}
5738   ins_pipe(pipe_slow);
5739 %}


src/cpu/x86/vm/x86_64.ad
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