1 /*
   2  * Copyright 2002 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25 package sun.jvm.hotspot.asm.sparc;
  26 
  27 import sun.jvm.hotspot.asm.*;
  28 
  29 // Please refer to "The SPARC Architecture Manual - Version 9"
  30 
  31 public interface SPARCV9Opcodes extends SPARCOpcodes {
  32     // format 2, v9 specific "op2" values.
  33 
  34     // branch on integer condition codes with prediction
  35     public static final int OP_2_BPcc    = 1;
  36 
  37     // branch on integer register contents with prediction
  38     public static final int OP_2_BPr     = 3;
  39 
  40     // branch on float condition codes with prediction
  41     public static final int OP_2_FBPfcc  = 5;
  42 
  43     // "rcond" - branch on register condition
  44     public static final int BRANCH_RCOND_START_BIT  = 25;
  45 
  46     // rcond is 3 bits length
  47     public static final int BRANCH_RCOND_MASK = 7 << BRANCH_RCOND_START_BIT;
  48 
  49     // "rcond" - as used in conditional moves
  50     public static final int CMOVE_RCOND_START_BIT = 10;
  51     public static final int CMOVE_RCOND_MASK = 7 << CMOVE_RCOND_START_BIT;
  52 
  53     public static final int IMPDEP1 = CPop1;
  54     public static final int IMPDEP2 = CPop2;
  55 
  56     // various rcond values - used in BPr, MOVr and FMOVr
  57 
  58     // reserved register condition
  59     public static final int BRANCH_RCOND_RESERVED1 = 0; // 000
  60 
  61     public static final int BRZ     = 1;
  62     public static final int MOVRZ   = BRZ;
  63     public static final int FMOVZ   = BRZ;
  64 
  65     public static final int BRLEZ   = 2;
  66     public static final int MOVRLEZ = BRLEZ;
  67     public static final int FMOVLEZ = BRLEZ;
  68 
  69     public static final int BRLZ    = 3;
  70     public static final int MOVRLZ  = BRLZ;
  71     public static final int FMOVLZ  = BRLZ;
  72 
  73     // reserved register condition
  74     public static final int BRANCH_RCOND_RESERVED2 = 4; // 100
  75 
  76     public static final int BRNZ    = 5;
  77     public static final int MOVRNZ  = BRNZ;
  78     public static final int FMOVNZ  = BRNZ;
  79 
  80     public static final int BRGZ    = 6;
  81     public static final int MOVGZ   = BRGZ;
  82     public static final int FMOVGZ  = BRGZ;
  83 
  84     public static final int BRGEZ   = 7;
  85     public static final int MOVRGEZ = BRGEZ;
  86     public static final int FMOVGEZ = BRGEZ;
  87 
  88     // "p" - prediction bit - predict branch taken or not taken
  89     public static final int PREDICTION_START_BIT = 19;
  90     public static final int PREDICTION_MASK = 1 << PREDICTION_START_BIT;
  91 
  92     // branch pc relative displacement - hi 2 bits of disp16.
  93     public static final int DISP_16_HI_START_BIT = 20;
  94 
  95     // disp 16 hi is 2 bits length
  96     public static final int DISP_16_HI_MASK = 3 << DISP_16_HI_START_BIT;
  97 
  98     // disp 16 low 14 bits
  99     public static final int DISP_16_LO_START_BIT = 0; // just for completion.
 100     public static final int DISP_16_LO_MASK = 0x3FFF;
 101     public static final int DISP_16_LO_NUMBITS = 14;
 102 
 103     // disp 19 - integer branch with prediction - displacement
 104     public static final int DISP_19_MASK = 0x7FFFF;
 105 
 106     /*
 107      * condition code selected for integer branches - cc1 & cc0.
 108      * condition code selected for float branches - cc1 & cc0.
 109      * opf_cc field - floating conditional moves - 3 bits.
 110      * convert 2 bit codes as 3 bit codes always and use following codes
 111      * uniformly.
 112     */
 113 
 114     // opf_cc - 3 bits
 115     public static final int OPF_CC_START_BIT = 11;
 116     public static final int OPF_CC_MASK = 7 << OPF_CC_START_BIT;
 117 
 118     public static final int fcc0 = 0;  // 000
 119     public static final int fcc1 = 1;  // 001
 120     public static final int fcc2 = 2;  // 010
 121     public static final int fcc3 = 3;  // 011
 122     public static final int icc  = 4;  // 100
 123     public static final int CFLAG_RESERVED1 = 5; // 101
 124     public static final int xcc  = 6;  // 110
 125     public static final int CFLAG_RESERVED2 = 7; // 111
 126 
 127     // cc0, cc1 as in integer, float predicted branches
 128     public static final int BPcc_CC_START_BIT = 20;
 129     public static final int BPcc_CC_MASK = 3 << BPcc_CC_START_BIT;
 130     public static final int FBPfcc_CC_START_BIT = BPcc_CC_START_BIT;
 131     public static final int FBPfcc_CC_MASK = BPcc_CC_MASK;
 132 
 133     // condition codes for integer branches with prediction - BPcc
 134     public static final int CONDITION_BPN   = CONDITION_BN;
 135     public static final int CONDITION_BPE   = CONDITION_BE;
 136     public static final int CONDITION_BPLE  = CONDITION_BLE;
 137     public static final int CONDITION_BPL   = CONDITION_BL;
 138     public static final int CONDITION_BPLEU = CONDITION_BLEU;
 139     public static final int CONDITION_BPCS  = CONDITION_BCS;
 140     public static final int CONDITION_BPNEG = CONDITION_BNEG;
 141     public static final int CONDITION_BPVS  = CONDITION_BVS;
 142     public static final int CONDITION_BPA   = CONDITION_BA;
 143     public static final int CONDITION_BPNE  = CONDITION_BNE;
 144     public static final int CONDITION_BPG   = CONDITION_BG;
 145     public static final int CONDITION_BPGE  = CONDITION_BGE;
 146     public static final int CONDITION_BPGU  = CONDITION_BGU;
 147     public static final int CONDITION_BPCC  = CONDITION_BCC;
 148     public static final int CONDITION_BPPOS = CONDITION_BPOS;
 149     public static final int CONDITION_BPVC  = CONDITION_BVC;
 150 
 151     // condition codes for float branches with prediction
 152     public static final int CONDITION_FBPN  = CONDITION_BN;
 153     public static final int CONDITION_FBPNE = CONDITION_BE;
 154     public static final int CONDITION_FBPLG = CONDITION_BLE;
 155     public static final int CONDITION_FBPUL = CONDITION_BL;
 156     public static final int CONDITION_FBPL  = CONDITION_BLEU;
 157     public static final int CONDITION_FBPUG = CONDITION_BCS;
 158     public static final int CONDITION_FBPG  = CONDITION_BNEG;
 159     public static final int CONDITION_FBPU  = CONDITION_BVS;
 160     public static final int CONDITION_FBPA  = CONDITION_BA;
 161     public static final int CONDITION_FBPE  = CONDITION_BNE;
 162     public static final int CONDITION_FBPUE = CONDITION_BG;
 163     public static final int CONDITION_FBPGE = CONDITION_BGE;
 164     public static final int CONDITION_FBPUGE= CONDITION_BGU;
 165     public static final int CONDITION_FBPLE = CONDITION_BCC;
 166     public static final int CONDITION_FBPULE= CONDITION_BPOS;
 167     public static final int CONDITION_FBPO  = CONDITION_BVC;
 168 
 169     // "cmask" - 3 bit mask used in membar for completion constraints
 170     public static final int CMASK_START_BIT = 4;
 171     public static final int CMASK_MASK = 7 << CMASK_START_BIT;
 172 
 173     // "mmask" - 4 bit mask used in member for ordering instruction classes.
 174     public static final int MMASK_START_BIT = 0;
 175     public static final int MMASK_MASK = 0xF; // no need to shift
 176 
 177     // v9 specific load/store instruction opcodes
 178     // load/store instructions - op3 values - used with op=3 (FORMAT_3)
 179 
 180     public static final int LDUW   = LD;
 181     public static final int LDUWA  = LDA;
 182 
 183     public static final int LDXFSR = LDFSR;
 184 
 185     public static final int LDFA   = LDC;
 186     public static final int LDQF   = (2 << 4) | 2;
 187     public static final int LDQFA  = (3 << 4) | 2;
 188     public static final int LDDFA  = LDDC;
 189 
 190     public static final int STW    = ST;
 191     public static final int STWA   = STA;
 192     public static final int STFA   = STC;
 193 
 194     public static final int STXFSR = STFSR;
 195 
 196     public static final int STQF   = STDFQ;
 197     public static final int STQFA  = STDCQ;
 198     public static final int STDFA  = STDC;
 199 
 200     public static final int LDSW   = 8;
 201     public static final int LDSWA  = (1 << 4) | 8;
 202 
 203     public static final int LDX    = 0xB;
 204     public static final int LDXA   = (1 << 4) | 0xB;
 205 
 206     public static final int PREFETCH  = (2 << 4) | 0xD;
 207     public static final int PREFETCHA = (3 << 4) | 0xD;
 208 
 209     public static final int CASA   = (3 << 4) | 0xC;
 210 
 211     public static final int STX    = 0xE;
 212     public static final int STXA   = (1 << 4) | 0xE;
 213     public static final int CASXA  = (3 << 4) | 0xE;
 214 
 215     // 6 bit immediate shift count mask
 216     public static final int SHIFT_COUNT_6_MASK = 0x3F;
 217 
 218     // X bit mask - used to differentiate b/w 32 bit and 64 bit shifts
 219     public static final int X_MASK = 1 << 12;
 220 
 221     // E Opcode maps - Page 274 - Table 32 - op3 (op=2) table
 222     // v9 specific items
 223     public static final int ADDC   = ADDX;
 224     public static final int ADDCcc = ADDXcc;
 225 
 226     public static final int SUBC   = SUBX;
 227     public static final int SUBCcc = SUBXcc;
 228 
 229     public static final int MULX   = 9;
 230     public static final int UDIVX  = 0xD;
 231 
 232     public static final int SLLX   = SLL;
 233     public static final int SRLX   = SRL;
 234     public static final int SRAX   = SRA;
 235 
 236     // special register reads
 237     public static final int RDCCR  = RDY;
 238     public static final int RDASI  = RDY;
 239     public static final int RDTICK = RDY;
 240     public static final int RDPC   = RDY;
 241     public static final int RDFPRS = RDY;
 242     public static final int MEMBAR = RDY;
 243     public static final int STMBAR = RDY;
 244 
 245     public static final int RDPR   = (2 << 4) | 0xA;
 246 
 247     public static final int FLUSHW = (2 << 4) | 0xB;
 248 
 249     public static final int MOVcc  = (2 << 4) | 0xC;
 250 
 251     public static final int SDIVX  = (2 << 4) | 0xD;
 252 
 253     public static final int POPC   = (2 << 4) | 0xE;
 254 
 255     public static final int MOVr   = (2 << 4) | 0xF;
 256 
 257     // special regitser writes
 258     public static final int WRCCR  = WRY;
 259     public static final int WRASI  = WRY;
 260     public static final int WRFPRS = WRY;
 261     public static final int SIR    = WRY;
 262 
 263     public static final int SAVED  = (3 << 4) | 0x1;
 264     public static final int RESTORED = SAVED;
 265 
 266     public static final int WRPR   = (3 << 4) | 0x2;
 267 
 268     public static final int RETURN = RETT;
 269 
 270     public static final int DONE   = (3 << 4) | 0xE;
 271     public static final int RETRY  = DONE;
 272 
 273     // various integer condition code move instructions
 274     public static final int CONDITION_MOVN    = CONDITION_BN;
 275     public static final int CONDITION_MOVE    = CONDITION_BE;
 276     public static final int CONDITION_MOVLE   = CONDITION_BLE;
 277     public static final int CONDITION_MOVL    = CONDITION_BL;
 278     public static final int CONDITION_MOVLEU  = CONDITION_BLEU;
 279     public static final int CONDITION_MOVCS   = CONDITION_BCS;
 280     public static final int CONDITION_MOVNEG  = CONDITION_BNEG;
 281     public static final int CONDITION_MOVVS   = CONDITION_BVS;
 282     public static final int CONDITION_MOVA    = CONDITION_BA;
 283     public static final int CONDITION_MOVNE   = CONDITION_BNE;
 284     public static final int CONDITION_MOVG    = CONDITION_BG;
 285     public static final int CONDITION_MOVGE   = CONDITION_BGE;
 286     public static final int CONDITION_MOVGU   = CONDITION_BGU;
 287     public static final int CONDITION_MOVCC   = CONDITION_BCC;
 288     public static final int CONDITION_MOVPOS  = CONDITION_BPOS;
 289     public static final int CONDITION_MOVVC   = CONDITION_BVC;
 290 
 291     // cc0, cc1 & cc2 in conditional moves
 292     public static final int CMOVE_CC_START_BIT  = 11;
 293     public static final int CMOVE_CC0_CC1_MASK  = 3 << CMOVE_CC_START_BIT;
 294     public static final int CMOVE_CC2_START_BIT = 18;
 295     public static final int CMOVE_CC2_MASK      = 1 << CMOVE_CC2_START_BIT;
 296 
 297     public static final int CMOVE_COND_START_BIT = 14;
 298     // condition code is 4 bits
 299     public static final int CMOVE_COND_MASK = 0xF << CMOVE_COND_START_BIT;
 300 
 301     // opf[8:0] (op=2,op3=0x34=FPop1) - Table 34 - Page 276 - E Opcode Maps
 302     // v9 specific opcodes only - remaining are in SPARCOpcodes.
 303 
 304     public static final int FMOVd = 0x2;
 305     public static final int FMOVq = 0x3;
 306     public static final int FNEGd = 0x6;
 307     public static final int FNEGq = 0x7;
 308     public static final int FABSd = 0xA;
 309     public static final int FABSq = 0xB;
 310     public static final int FsTOx = (0x8 << 4) | 0x1;
 311     public static final int FdTOx = (0x8 << 4) | 0x2;
 312     public static final int FqTOx = (0x8 << 4) | 0x3;
 313     public static final int FxTOs = (0x8 << 4) | 0x4;
 314     public static final int FxTOd = (0x8 << 4) | 0x8;
 315     public static final int FxTOq = (0x8 << 4) | 0xC;
 316 
 317     // opf[8:0] (op=2, op3=0x35= FPop2) - Table 35 - Page 277 - E.2 Tables
 318     // v9 specific opcodes only 0 remanining are in SPARCOpcodes.
 319 
 320     // fp condition moves
 321 
 322     public static final int FMOVs_fcc0 = 1;
 323     public static final int FMOVs_fcc1 = 1 | (0x4 << 4);
 324     public static final int FMOVs_fcc2 = 1 | (0x8 << 4);
 325     public static final int FMOVs_fcc3 = 1 | (0xC << 4);
 326     public static final int FMOVs_icc  = 1 | (0x10 << 4);
 327     public static final int FMOVs_xcc  = 1 | (0x18 << 4);
 328 
 329     public static final int FMOVd_fcc0 = 2;
 330     public static final int FMOVd_fcc1 = 2 | (0x4 << 4);
 331     public static final int FMOVd_fcc2 = 2 | (0x8 << 4);
 332     public static final int FMOVd_fcc3 = 2 | (0xC << 4);
 333     public static final int FMOVd_icc  = 2 | (0x10 << 4);
 334     public static final int FMOVd_xcc  = 2 | (0x18 << 4);
 335 
 336     public static final int FMOVq_fcc0 = 3;
 337     public static final int FMOVq_fcc1 = 3 | (0x4 << 4);
 338     public static final int FMOVq_fcc2 = 3 | (0x8 << 4);
 339     public static final int FMOVq_fcc3 = 3 | (0xC << 4);
 340     public static final int FMOVq_icc  = 3 | (0x10 << 4);
 341     public static final int FMOVq_xcc  = 3 | (0x18 << 4);
 342 
 343     // fp register condition moves
 344 
 345     public static final int FMOVRsZ    = 5 | (0x2 << 4);
 346     public static final int FMOVRsLEZ  = 5 | (0x4 << 4);
 347     public static final int FMOVRsLZ   = 5 | (0x6 << 4);
 348     public static final int FMOVRsNZ   = 5 | (0xA << 4);
 349     public static final int FMOVRsGZ   = 5 | (0xC << 4);
 350     public static final int FMOVRsGEZ  = 5 | (0xE << 4);
 351 
 352     public static final int FMOVRdZ    = 6 | (0x2 << 4);
 353     public static final int FMOVRdLEZ  = 6 | (0x4 << 4);
 354     public static final int FMOVRdLZ   = 6 | (0x6 << 4);
 355     public static final int FMOVRdNZ   = 6 | (0xA << 4);
 356     public static final int FMOVRdGZ   = 6 | (0xC << 4);
 357     public static final int FMOVRdGEZ  = 6 | (0xE << 4);
 358 
 359     public static final int FMOVRqZ    = 7 | (0x2 << 4);
 360     public static final int FMOVRqLEZ  = 7 | (0x4 << 4);
 361     public static final int FMOVRqLZ   = 7 | (0x6 << 4);
 362     public static final int FMOVRqNZ   = 7 | (0xA << 4);
 363     public static final int FMOVRqGZ   = 7 | (0xC << 4);
 364     public static final int FMOVRqGEZ  = 7 | (0xE << 4);
 365 }