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src/cpu/aarch64/vm/aarch64.ad

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rev 13535 : 8187022: AArch64: UBFX instructions have wrong format string
Reviewed-by: duke
Contributed-by: daniel.stewart@linaro.org


12597   ins_cost(INSN_COST * 2);
12598   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12599   ins_encode %{
12600     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12601     int s = 31 - lshift;
12602     int r = (rshift - lshift) & 31;
12603     __ ubfmw(as_Register($dst$$reg),
12604             as_Register($src$$reg),
12605             r, s);
12606   %}
12607 
12608   ins_pipe(ialu_reg_shift);
12609 %}
12610 // Bitfield extract with shift & mask
12611 
12612 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12613 %{
12614   match(Set dst (AndI (URShiftI src rshift) mask));
12615 
12616   ins_cost(INSN_COST);
12617   format %{ "ubfxw $dst, $src, $mask" %}
12618   ins_encode %{
12619     int rshift = $rshift$$constant;
12620     long mask = $mask$$constant;
12621     int width = exact_log2(mask+1);
12622     __ ubfxw(as_Register($dst$$reg),
12623             as_Register($src$$reg), rshift, width);
12624   %}
12625   ins_pipe(ialu_reg_shift);
12626 %}
12627 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
12628 %{
12629   match(Set dst (AndL (URShiftL src rshift) mask));
12630 
12631   ins_cost(INSN_COST);
12632   format %{ "ubfx $dst, $src, $mask" %}
12633   ins_encode %{
12634     int rshift = $rshift$$constant;
12635     long mask = $mask$$constant;
12636     int width = exact_log2(mask+1);
12637     __ ubfx(as_Register($dst$$reg),
12638             as_Register($src$$reg), rshift, width);
12639   %}
12640   ins_pipe(ialu_reg_shift);
12641 %}
12642 
12643 // We can use ubfx when extending an And with a mask when we know mask
12644 // is positive.  We know that because immI_bitmask guarantees it.
12645 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12646 %{
12647   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
12648 
12649   ins_cost(INSN_COST * 2);
12650   format %{ "ubfx $dst, $src, $mask" %}
12651   ins_encode %{
12652     int rshift = $rshift$$constant;
12653     long mask = $mask$$constant;
12654     int width = exact_log2(mask+1);
12655     __ ubfx(as_Register($dst$$reg),
12656             as_Register($src$$reg), rshift, width);
12657   %}
12658   ins_pipe(ialu_reg_shift);
12659 %}
12660 
12661 // We can use ubfiz when masking by a positive number and then left shifting the result.
12662 // We know that the mask is positive because immI_bitmask guarantees it.
12663 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12664 %{
12665   match(Set dst (LShiftI (AndI src mask) lshift));
12666   predicate((unsigned int)n->in(2)->get_int() <= 31 &&
12667     (exact_log2(n->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= (31+1));
12668 
12669   ins_cost(INSN_COST);
12670   format %{ "ubfizw $dst, $src, $lshift, $mask" %}




12597   ins_cost(INSN_COST * 2);
12598   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12599   ins_encode %{
12600     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
12601     int s = 31 - lshift;
12602     int r = (rshift - lshift) & 31;
12603     __ ubfmw(as_Register($dst$$reg),
12604             as_Register($src$$reg),
12605             r, s);
12606   %}
12607 
12608   ins_pipe(ialu_reg_shift);
12609 %}
12610 // Bitfield extract with shift & mask
12611 
12612 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12613 %{
12614   match(Set dst (AndI (URShiftI src rshift) mask));
12615 
12616   ins_cost(INSN_COST);
12617   format %{ "ubfxw $dst, $src, $rshift, $mask" %}
12618   ins_encode %{
12619     int rshift = $rshift$$constant;
12620     long mask = $mask$$constant;
12621     int width = exact_log2(mask+1);
12622     __ ubfxw(as_Register($dst$$reg),
12623             as_Register($src$$reg), rshift, width);
12624   %}
12625   ins_pipe(ialu_reg_shift);
12626 %}
12627 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
12628 %{
12629   match(Set dst (AndL (URShiftL src rshift) mask));
12630 
12631   ins_cost(INSN_COST);
12632   format %{ "ubfx $dst, $src, $rshift, $mask" %}
12633   ins_encode %{
12634     int rshift = $rshift$$constant;
12635     long mask = $mask$$constant;
12636     int width = exact_log2(mask+1);
12637     __ ubfx(as_Register($dst$$reg),
12638             as_Register($src$$reg), rshift, width);
12639   %}
12640   ins_pipe(ialu_reg_shift);
12641 %}
12642 
12643 // We can use ubfx when extending an And with a mask when we know mask
12644 // is positive.  We know that because immI_bitmask guarantees it.
12645 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12646 %{
12647   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
12648 
12649   ins_cost(INSN_COST * 2);
12650   format %{ "ubfx $dst, $src, $rshift, $mask" %}
12651   ins_encode %{
12652     int rshift = $rshift$$constant;
12653     long mask = $mask$$constant;
12654     int width = exact_log2(mask+1);
12655     __ ubfx(as_Register($dst$$reg),
12656             as_Register($src$$reg), rshift, width);
12657   %}
12658   ins_pipe(ialu_reg_shift);
12659 %}
12660 
12661 // We can use ubfiz when masking by a positive number and then left shifting the result.
12662 // We know that the mask is positive because immI_bitmask guarantees it.
12663 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12664 %{
12665   match(Set dst (LShiftI (AndI src mask) lshift));
12666   predicate((unsigned int)n->in(2)->get_int() <= 31 &&
12667     (exact_log2(n->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= (31+1));
12668 
12669   ins_cost(INSN_COST);
12670   format %{ "ubfizw $dst, $src, $lshift, $mask" %}


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