1 /* 2 * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2018, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP 27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP 28 29 #include "asm/register.hpp" 30 31 // Address is an abstraction used to represent a memory location 32 // as used in assembler instructions. 33 // PPC instructions grok either baseReg + indexReg or baseReg + disp. 34 // So far we do not use this as simplification by this class is low 35 // on PPC with its simple addressing mode. Use RegisterOrConstant to 36 // represent an offset. 37 class Address VALUE_OBJ_CLASS_SPEC { 38 }; 39 40 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 41 private: 42 address _address; 43 RelocationHolder _rspec; 44 45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 46 switch (rtype) { 47 case relocInfo::external_word_type: 48 return external_word_Relocation::spec(addr); 49 case relocInfo::internal_word_type: 50 return internal_word_Relocation::spec(addr); 51 case relocInfo::opt_virtual_call_type: 52 return opt_virtual_call_Relocation::spec(); 53 case relocInfo::static_call_type: 54 return static_call_Relocation::spec(); 55 case relocInfo::runtime_call_type: 56 return runtime_call_Relocation::spec(); 57 case relocInfo::none: 58 return RelocationHolder(); 59 default: 60 ShouldNotReachHere(); 61 return RelocationHolder(); 62 } 63 } 64 65 protected: 66 // creation 67 AddressLiteral() : _address(NULL), _rspec(NULL) {} 68 69 public: 70 AddressLiteral(address addr, RelocationHolder const& rspec) 71 : _address(addr), 72 _rspec(rspec) {} 73 74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 75 : _address((address) addr), 76 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 77 78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 79 : _address((address) addr), 80 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 81 82 intptr_t value() const { return (intptr_t) _address; } 83 84 const RelocationHolder& rspec() const { return _rspec; } 85 }; 86 87 // Argument is an abstraction used to represent an outgoing 88 // actual argument or an incoming formal parameter, whether 89 // it resides in memory or in a register, in a manner consistent 90 // with the PPC Application Binary Interface, or ABI. This is 91 // often referred to as the native or C calling convention. 92 93 class Argument VALUE_OBJ_CLASS_SPEC { 94 private: 95 int _number; // The number of the argument. 96 public: 97 enum { 98 // Only 8 registers may contain integer parameters. 99 n_register_parameters = 8, 100 // Can have up to 8 floating registers. 101 n_float_register_parameters = 8, 102 103 // PPC C calling conventions. 104 // The first eight arguments are passed in int regs if they are int. 105 n_int_register_parameters_c = 8, 106 // The first thirteen float arguments are passed in float regs. 107 n_float_register_parameters_c = 13, 108 // Only the first 8 parameters are not placed on the stack. Aix disassembly 109 // shows that xlC places all float args after argument 8 on the stack AND 110 // in a register. This is not documented, but we follow this convention, too. 111 n_regs_not_on_stack_c = 8, 112 }; 113 // creation 114 Argument(int number) : _number(number) {} 115 116 int number() const { return _number; } 117 118 // Locating register-based arguments: 119 bool is_register() const { return _number < n_register_parameters; } 120 121 Register as_register() const { 122 assert(is_register(), "must be a register argument"); 123 return as_Register(number() + R3_ARG1->encoding()); 124 } 125 }; 126 127 #if !defined(ABI_ELFv2) 128 // A ppc64 function descriptor. 129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC { 130 private: 131 address _entry; 132 address _toc; 133 address _env; 134 135 public: 136 inline address entry() const { return _entry; } 137 inline address toc() const { return _toc; } 138 inline address env() const { return _env; } 139 140 inline void set_entry(address entry) { _entry = entry; } 141 inline void set_toc( address toc) { _toc = toc; } 142 inline void set_env( address env) { _env = env; } 143 144 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } 145 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } 146 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 147 148 // Friend functions can be called without loading toc and env. 149 enum { 150 friend_toc = 0xcafe, 151 friend_env = 0xc0de 152 }; 153 154 inline bool is_friend_function() const { 155 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 156 } 157 158 // Constructor for stack-allocated instances. 159 FunctionDescriptor() { 160 _entry = (address) 0xbad; 161 _toc = (address) 0xbad; 162 _env = (address) 0xbad; 163 } 164 }; 165 #endif 166 167 class Assembler : public AbstractAssembler { 168 protected: 169 // Displacement routines 170 static void print_instruction(int inst); 171 static int patched_branch(int dest_pos, int inst, int inst_pos); 172 static int branch_destination(int inst, int pos); 173 174 friend class AbstractAssembler; 175 176 // Code patchers need various routines like inv_wdisp() 177 friend class NativeInstruction; 178 friend class NativeGeneralJump; 179 friend class Relocation; 180 181 public: 182 183 enum shifts { 184 XO_21_29_SHIFT = 2, 185 XO_21_30_SHIFT = 1, 186 XO_27_29_SHIFT = 2, 187 XO_30_31_SHIFT = 0, 188 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 189 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 190 RS_SHIFT = 21u, // RS field in bits 21 -- 25 191 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 192 }; 193 194 enum opcdxos_masks { 195 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 196 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 197 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 198 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 199 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 200 // trap instructions 201 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 202 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 203 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 204 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 205 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 206 STD_OPCODE_MASK = LD_OPCODE_MASK, 207 STDU_OPCODE_MASK = STD_OPCODE_MASK, 208 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 209 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 210 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 211 STWU_OPCODE_MASK = STW_OPCODE_MASK, 212 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 213 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 214 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 215 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 216 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 217 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 218 }; 219 220 enum opcdxos { 221 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 222 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 223 ADDI_OPCODE = (14u << OPCODE_SHIFT), 224 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 225 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 226 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 227 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 228 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 229 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 230 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 231 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 232 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 233 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 234 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 235 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 236 MULLI_OPCODE = (7u << OPCODE_SHIFT), 237 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 238 ANDI_OPCODE = (28u << OPCODE_SHIFT), 239 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 240 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 241 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 242 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 243 ORI_OPCODE = (24u << OPCODE_SHIFT), 244 ORIS_OPCODE = (25u << OPCODE_SHIFT), 245 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 246 XORI_OPCODE = (26u << OPCODE_SHIFT), 247 XORIS_OPCODE = (27u << OPCODE_SHIFT), 248 249 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 250 251 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 252 CLRRWI_OPCODE = RLWINM_OPCODE, 253 CLRLWI_OPCODE = RLWINM_OPCODE, 254 255 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 256 257 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 258 SLWI_OPCODE = RLWINM_OPCODE, 259 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 260 SRWI_OPCODE = RLWINM_OPCODE, 261 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 262 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 263 264 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 265 CMPI_OPCODE = (11u << OPCODE_SHIFT), 266 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 267 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 268 269 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 270 271 // Special purpose registers 272 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 273 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 274 275 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 276 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 277 278 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 279 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 280 281 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 282 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 283 284 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 285 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 286 287 MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT), 288 MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT), 289 MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT), 290 MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT), 291 MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT), 292 MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT), 293 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT), 294 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT), 295 296 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT), 297 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT), 298 299 MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT), 300 301 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 302 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 303 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 304 305 // condition register logic instructions 306 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 307 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 308 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 309 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 310 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 311 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 312 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 313 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 314 315 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 316 BXX_OPCODE = (18u << OPCODE_SHIFT), 317 BCXX_OPCODE = (16u << OPCODE_SHIFT), 318 319 // CTR-related opcodes 320 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 321 322 LWZ_OPCODE = (32u << OPCODE_SHIFT), 323 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 324 LWZU_OPCODE = (33u << OPCODE_SHIFT), 325 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 326 327 LHA_OPCODE = (42u << OPCODE_SHIFT), 328 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 329 LHAU_OPCODE = (43u << OPCODE_SHIFT), 330 331 LHZ_OPCODE = (40u << OPCODE_SHIFT), 332 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 333 LHZU_OPCODE = (41u << OPCODE_SHIFT), 334 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 335 336 LBZ_OPCODE = (34u << OPCODE_SHIFT), 337 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 338 LBZU_OPCODE = (35u << OPCODE_SHIFT), 339 340 STW_OPCODE = (36u << OPCODE_SHIFT), 341 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 342 STWU_OPCODE = (37u << OPCODE_SHIFT), 343 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 344 345 STH_OPCODE = (44u << OPCODE_SHIFT), 346 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 347 STHU_OPCODE = (45u << OPCODE_SHIFT), 348 349 STB_OPCODE = (38u << OPCODE_SHIFT), 350 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 351 STBU_OPCODE = (39u << OPCODE_SHIFT), 352 353 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 354 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 355 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 356 357 // 32 bit opcode encodings 358 359 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 360 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 361 362 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 363 364 // 64 bit opcode encodings 365 366 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 367 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 368 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 369 370 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 371 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 372 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 373 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 374 375 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 376 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 377 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 378 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 379 380 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 381 382 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 383 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 384 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 385 386 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 387 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 388 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 389 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 390 391 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 392 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 393 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 394 395 396 // opcodes only used for floating arithmetic 397 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 398 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 399 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 400 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 401 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 402 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 403 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 404 // on Power7. Do not use. 405 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 406 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 407 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 408 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 409 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 410 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 411 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 412 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 413 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 414 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 415 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 416 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 417 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 418 419 // PPC64-internal FPU conversion opcodes 420 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 421 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 422 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 423 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 424 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 425 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 426 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 427 428 // WARNING: using fmadd results in a non-compliant vm. Some floating 429 // point tck tests will fail. 430 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 431 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 432 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 433 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 434 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 435 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 436 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 437 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 438 439 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 440 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 441 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 442 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 443 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 444 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 445 446 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 447 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 448 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 449 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 450 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 451 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 452 453 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 454 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 455 456 // Vector instruction support for >= Power6 457 // Vector Storage Access 458 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 459 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 460 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 461 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 462 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 463 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 464 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 465 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 466 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 467 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 468 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 469 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 470 471 // Vector-Scalar (VSX) instruction support. 472 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 473 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 474 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 475 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1), 476 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 477 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1), 478 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3), 479 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3), 480 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3), 481 482 // Vector Permute and Formatting 483 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 484 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 485 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 486 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 487 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 488 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 489 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 490 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 491 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 492 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 493 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 494 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 495 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 496 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 497 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 498 499 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 500 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 501 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 502 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 503 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 504 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 505 506 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 507 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 508 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 509 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 510 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 511 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 512 513 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 514 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 515 516 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 517 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 518 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 519 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 520 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 521 522 // Vector Integer 523 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 524 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 525 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 526 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 527 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 528 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 529 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 530 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ), 531 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 532 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 533 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 534 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 535 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 536 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 537 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 538 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 539 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 540 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 541 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 542 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 543 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 544 545 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 546 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 547 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 548 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 549 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 550 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 551 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 552 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 553 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 554 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 555 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 556 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 557 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 558 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 559 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 560 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 561 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 562 563 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 564 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 565 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 566 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 567 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 568 569 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 570 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 571 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 572 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 573 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 574 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 575 576 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 577 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 578 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 579 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 580 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 581 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 582 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 583 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 584 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 585 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 586 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 587 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 588 589 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 590 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 591 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 592 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 593 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 594 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 595 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 596 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 597 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 598 599 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 600 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 601 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 602 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 603 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 604 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ), 605 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 606 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 607 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 608 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 609 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 610 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 611 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 612 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 613 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 614 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 615 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 616 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 617 618 // Vector Floating-Point 619 // not implemented yet 620 621 // Vector Status and Control 622 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 623 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 624 625 // AES (introduced with Power 8) 626 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 627 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 628 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 629 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 630 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 631 632 // SHA (introduced with Power 8) 633 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 634 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 635 636 // Vector Binary Polynomial Multiplication (introduced with Power 8) 637 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 638 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 639 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 640 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 641 642 // Vector Permute and Xor (introduced with Power 8) 643 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 644 645 // Transactional Memory instructions (introduced with Power 8) 646 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 647 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 648 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 649 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 650 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 651 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 652 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 653 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 654 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 655 656 // Icache and dcache related instructions 657 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 658 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 659 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 660 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 661 662 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 663 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 664 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 665 666 // Instruction synchronization 667 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 668 // Memory barriers 669 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 670 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 671 672 // Trap instructions 673 TDI_OPCODE = (2u << OPCODE_SHIFT), 674 TWI_OPCODE = (3u << OPCODE_SHIFT), 675 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 676 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 677 678 // Atomics. 679 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 680 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 681 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 682 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 683 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 684 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 685 686 }; 687 688 // Trap instructions TO bits 689 enum trap_to_bits { 690 // single bits 691 traptoLessThanSigned = 1 << 4, // 0, left end 692 traptoGreaterThanSigned = 1 << 3, 693 traptoEqual = 1 << 2, 694 traptoLessThanUnsigned = 1 << 1, 695 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 696 697 // compound ones 698 traptoUnconditional = (traptoLessThanSigned | 699 traptoGreaterThanSigned | 700 traptoEqual | 701 traptoLessThanUnsigned | 702 traptoGreaterThanUnsigned) 703 }; 704 705 // Branch hints BH field 706 enum branch_hint_bh { 707 // bclr cases: 708 bhintbhBCLRisReturn = 0, 709 bhintbhBCLRisNotReturnButSame = 1, 710 bhintbhBCLRisNotPredictable = 3, 711 712 // bcctr cases: 713 bhintbhBCCTRisNotReturnButSame = 0, 714 bhintbhBCCTRisNotPredictable = 3 715 }; 716 717 // Branch prediction hints AT field 718 enum branch_hint_at { 719 bhintatNoHint = 0, // at=00 720 bhintatIsNotTaken = 2, // at=10 721 bhintatIsTaken = 3 // at=11 722 }; 723 724 // Branch prediction hints 725 enum branch_hint_concept { 726 // Use the same encoding as branch_hint_at to simply code. 727 bhintNoHint = bhintatNoHint, 728 bhintIsNotTaken = bhintatIsNotTaken, 729 bhintIsTaken = bhintatIsTaken 730 }; 731 732 // Used in BO field of branch instruction. 733 enum branch_condition { 734 bcondCRbiIs0 = 4, // bo=001at 735 bcondCRbiIs1 = 12, // bo=011at 736 bcondAlways = 20 // bo=10100 737 }; 738 739 // Branch condition with combined prediction hints. 740 enum branch_condition_with_hint { 741 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 742 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 743 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 744 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 745 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 746 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 747 }; 748 749 // Elemental Memory Barriers (>=Power 8) 750 enum Elemental_Membar_mask_bits { 751 StoreStore = 1 << 0, 752 StoreLoad = 1 << 1, 753 LoadStore = 1 << 2, 754 LoadLoad = 1 << 3 755 }; 756 757 // Branch prediction hints. 758 inline static int add_bhint_to_boint(const int bhint, const int boint) { 759 switch (boint) { 760 case bcondCRbiIs0: 761 case bcondCRbiIs1: 762 // branch_hint and branch_hint_at have same encodings 763 assert( (int)bhintNoHint == (int)bhintatNoHint 764 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 765 && (int)bhintIsTaken == (int)bhintatIsTaken, 766 "wrong encodings"); 767 assert((bhint & 0x03) == bhint, "wrong encodings"); 768 return (boint & ~0x03) | bhint; 769 case bcondAlways: 770 // no branch_hint 771 return boint; 772 default: 773 ShouldNotReachHere(); 774 return 0; 775 } 776 } 777 778 // Extract bcond from boint. 779 inline static int inv_boint_bcond(const int boint) { 780 int r_bcond = boint & ~0x03; 781 assert(r_bcond == bcondCRbiIs0 || 782 r_bcond == bcondCRbiIs1 || 783 r_bcond == bcondAlways, 784 "bad branch condition"); 785 return r_bcond; 786 } 787 788 // Extract bhint from boint. 789 inline static int inv_boint_bhint(const int boint) { 790 int r_bhint = boint & 0x03; 791 assert(r_bhint == bhintatNoHint || 792 r_bhint == bhintatIsNotTaken || 793 r_bhint == bhintatIsTaken, 794 "bad branch hint"); 795 return r_bhint; 796 } 797 798 // Calculate opposite of given bcond. 799 inline static int opposite_bcond(const int bcond) { 800 switch (bcond) { 801 case bcondCRbiIs0: 802 return bcondCRbiIs1; 803 case bcondCRbiIs1: 804 return bcondCRbiIs0; 805 default: 806 ShouldNotReachHere(); 807 return 0; 808 } 809 } 810 811 // Calculate opposite of given bhint. 812 inline static int opposite_bhint(const int bhint) { 813 switch (bhint) { 814 case bhintatNoHint: 815 return bhintatNoHint; 816 case bhintatIsNotTaken: 817 return bhintatIsTaken; 818 case bhintatIsTaken: 819 return bhintatIsNotTaken; 820 default: 821 ShouldNotReachHere(); 822 return 0; 823 } 824 } 825 826 // PPC branch instructions 827 enum ppcops { 828 b_op = 18, 829 bc_op = 16, 830 bcr_op = 19 831 }; 832 833 enum Condition { 834 negative = 0, 835 less = 0, 836 positive = 1, 837 greater = 1, 838 zero = 2, 839 equal = 2, 840 summary_overflow = 3, 841 }; 842 843 public: 844 // Helper functions for groups of instructions 845 846 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 847 848 // instruction must start at passed address 849 static int instr_len(unsigned char *instr) { return BytesPerInstWord; } 850 851 // instruction must be left-justified in argument 852 static int instr_len(unsigned long instr) { return BytesPerInstWord; } 853 854 // longest instructions 855 static int instr_maxlen() { return BytesPerInstWord; } 856 857 // Test if x is within signed immediate range for nbits. 858 static bool is_simm(int x, unsigned int nbits) { 859 assert(0 < nbits && nbits < 32, "out of bounds"); 860 const int min = -( ((int)1) << nbits-1 ); 861 const int maxplus1 = ( ((int)1) << nbits-1 ); 862 return min <= x && x < maxplus1; 863 } 864 865 static bool is_simm(jlong x, unsigned int nbits) { 866 assert(0 < nbits && nbits < 64, "out of bounds"); 867 const jlong min = -( ((jlong)1) << nbits-1 ); 868 const jlong maxplus1 = ( ((jlong)1) << nbits-1 ); 869 return min <= x && x < maxplus1; 870 } 871 872 // Test if x is within unsigned immediate range for nbits 873 static bool is_uimm(int x, unsigned int nbits) { 874 assert(0 < nbits && nbits < 32, "out of bounds"); 875 const int maxplus1 = ( ((int)1) << nbits ); 876 return 0 <= x && x < maxplus1; 877 } 878 879 static bool is_uimm(jlong x, unsigned int nbits) { 880 assert(0 < nbits && nbits < 64, "out of bounds"); 881 const jlong maxplus1 = ( ((jlong)1) << nbits ); 882 return 0 <= x && x < maxplus1; 883 } 884 885 protected: 886 // helpers 887 888 // X is supposed to fit in a field "nbits" wide 889 // and be sign-extended. Check the range. 890 static void assert_signed_range(intptr_t x, int nbits) { 891 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 892 "value out of range"); 893 } 894 895 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 896 assert((x & 3) == 0, "not word aligned"); 897 assert_signed_range(x, nbits + 2); 898 } 899 900 static void assert_unsigned_const(int x, int nbits) { 901 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 902 } 903 904 static int fmask(juint hi_bit, juint lo_bit) { 905 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 906 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 907 } 908 909 // inverse of u_field 910 static int inv_u_field(int x, int hi_bit, int lo_bit) { 911 juint r = juint(x) >> lo_bit; 912 r &= fmask(hi_bit, lo_bit); 913 return int(r); 914 } 915 916 // signed version: extract from field and sign-extend 917 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 918 x = x << (31-hi_bit); 919 x = x >> (31-hi_bit+lo_bit); 920 return x; 921 } 922 923 static int u_field(int x, int hi_bit, int lo_bit) { 924 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 925 int r = x << lo_bit; 926 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 927 return r; 928 } 929 930 // Same as u_field for signed values 931 static int s_field(int x, int hi_bit, int lo_bit) { 932 int nbits = hi_bit - lo_bit + 1; 933 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 934 "value out of range"); 935 x &= fmask(hi_bit, lo_bit); 936 int r = x << lo_bit; 937 return r; 938 } 939 940 // inv_op for ppc instructions 941 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 942 943 // Determine target address from li, bd field of branch instruction. 944 static intptr_t inv_li_field(int x) { 945 intptr_t r = inv_s_field_ppc(x, 25, 2); 946 r = (r << 2); 947 return r; 948 } 949 static intptr_t inv_bd_field(int x, intptr_t pos) { 950 intptr_t r = inv_s_field_ppc(x, 15, 2); 951 r = (r << 2) + pos; 952 return r; 953 } 954 955 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 956 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 957 // Extract instruction fields from instruction words. 958 public: 959 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } 960 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } 961 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } 962 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } 963 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 964 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 965 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. 966 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } 967 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } 968 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } 969 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } 970 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } 971 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } 972 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 973 974 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 975 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 976 977 // instruction fields 978 static int aa( int x) { return opp_u_field(x, 30, 30); } 979 static int ba( int x) { return opp_u_field(x, 15, 11); } 980 static int bb( int x) { return opp_u_field(x, 20, 16); } 981 static int bc( int x) { return opp_u_field(x, 25, 21); } 982 static int bd( int x) { return opp_s_field(x, 29, 16); } 983 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } 984 static int bf( int x) { return opp_u_field(x, 8, 6); } 985 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } 986 static int bfa( int x) { return opp_u_field(x, 13, 11); } 987 static int bh( int x) { return opp_u_field(x, 20, 19); } 988 static int bi( int x) { return opp_u_field(x, 15, 11); } 989 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } 990 static int bo( int x) { return opp_u_field(x, 10, 6); } 991 static int bt( int x) { return opp_u_field(x, 10, 6); } 992 static int d1( int x) { return opp_s_field(x, 31, 16); } 993 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } 994 static int eh( int x) { return opp_u_field(x, 31, 31); } 995 static int flm( int x) { return opp_u_field(x, 14, 7); } 996 static int fra( FloatRegister r) { return fra(r->encoding());} 997 static int frb( FloatRegister r) { return frb(r->encoding());} 998 static int frc( FloatRegister r) { return frc(r->encoding());} 999 static int frs( FloatRegister r) { return frs(r->encoding());} 1000 static int frt( FloatRegister r) { return frt(r->encoding());} 1001 static int fra( int x) { return opp_u_field(x, 15, 11); } 1002 static int frb( int x) { return opp_u_field(x, 20, 16); } 1003 static int frc( int x) { return opp_u_field(x, 25, 21); } 1004 static int frs( int x) { return opp_u_field(x, 10, 6); } 1005 static int frt( int x) { return opp_u_field(x, 10, 6); } 1006 static int fxm( int x) { return opp_u_field(x, 19, 12); } 1007 static int l10( int x) { return opp_u_field(x, 10, 10); } 1008 static int l15( int x) { return opp_u_field(x, 15, 15); } 1009 static int l910( int x) { return opp_u_field(x, 10, 9); } 1010 static int e1215( int x) { return opp_u_field(x, 15, 12); } 1011 static int lev( int x) { return opp_u_field(x, 26, 20); } 1012 static int li( int x) { return opp_s_field(x, 29, 6); } 1013 static int lk( int x) { return opp_u_field(x, 31, 31); } 1014 static int mb2125( int x) { return opp_u_field(x, 25, 21); } 1015 static int me2630( int x) { return opp_u_field(x, 30, 26); } 1016 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } 1017 static int me2126( int x) { return mb2126(x); } 1018 static int nb( int x) { return opp_u_field(x, 20, 16); } 1019 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes 1020 static int oe( int x) { return opp_u_field(x, 21, 21); } 1021 static int ra( Register r) { return ra(r->encoding()); } 1022 static int ra( int x) { return opp_u_field(x, 15, 11); } 1023 static int rb( Register r) { return rb(r->encoding()); } 1024 static int rb( int x) { return opp_u_field(x, 20, 16); } 1025 static int rc( int x) { return opp_u_field(x, 31, 31); } 1026 static int rs( Register r) { return rs(r->encoding()); } 1027 static int rs( int x) { return opp_u_field(x, 10, 6); } 1028 // we don't want to use R0 in memory accesses, because it has value `0' then 1029 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } 1030 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1031 1032 // register r is target 1033 static int rt( Register r) { return rs(r); } 1034 static int rt( int x) { return rs(x); } 1035 static int rta( Register r) { return ra(r); } 1036 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1037 1038 static int sh1620( int x) { return opp_u_field(x, 20, 16); } 1039 static int sh30( int x) { return opp_u_field(x, 30, 30); } 1040 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } 1041 static int si( int x) { return opp_s_field(x, 31, 16); } 1042 static int spr( int x) { return opp_u_field(x, 20, 11); } 1043 static int sr( int x) { return opp_u_field(x, 15, 12); } 1044 static int tbr( int x) { return opp_u_field(x, 20, 11); } 1045 static int th( int x) { return opp_u_field(x, 10, 7); } 1046 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } 1047 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } 1048 static int to( int x) { return opp_u_field(x, 10, 6); } 1049 static int u( int x) { return opp_u_field(x, 19, 16); } 1050 static int ui( int x) { return opp_u_field(x, 31, 16); } 1051 1052 // Support vector instructions for >= Power6. 1053 static int vra( int x) { return opp_u_field(x, 15, 11); } 1054 static int vrb( int x) { return opp_u_field(x, 20, 16); } 1055 static int vrc( int x) { return opp_u_field(x, 25, 21); } 1056 static int vrs( int x) { return opp_u_field(x, 10, 6); } 1057 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1058 1059 static int vra( VectorRegister r) { return vra(r->encoding());} 1060 static int vrb( VectorRegister r) { return vrb(r->encoding());} 1061 static int vrc( VectorRegister r) { return vrc(r->encoding());} 1062 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1063 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1064 1065 // Only used on SHA sigma instructions (VX-form) 1066 static int vst( int x) { return opp_u_field(x, 16, 16); } 1067 static int vsix( int x) { return opp_u_field(x, 20, 17); } 1068 1069 // Support Vector-Scalar (VSX) instructions. 1070 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); } 1071 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); } 1072 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); } 1073 static int vsrt( int x) { return vsrs(x); } 1074 static int vsdm( int x) { return opp_u_field(x, 23, 22); } 1075 1076 static int vsra( VectorSRegister r) { return vsra(r->encoding());} 1077 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} 1078 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} 1079 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1080 1081 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions 1082 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions 1083 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction 1084 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions 1085 1086 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1087 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1088 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1089 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1090 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1091 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1092 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1093 1094 protected: 1095 // Compute relative address for branch. 1096 static intptr_t disp(intptr_t x, intptr_t off) { 1097 int xx = x - off; 1098 xx = xx >> 2; 1099 return xx; 1100 } 1101 1102 public: 1103 // signed immediate, in low bits, nbits long 1104 static int simm(int x, int nbits) { 1105 assert_signed_range(x, nbits); 1106 return x & ((1 << nbits) - 1); 1107 } 1108 1109 // unsigned immediate, in low bits, nbits long 1110 static int uimm(int x, int nbits) { 1111 assert_unsigned_const(x, nbits); 1112 return x & ((1 << nbits) - 1); 1113 } 1114 1115 static void set_imm(int* instr, short s) { 1116 // imm is always in the lower 16 bits of the instruction, 1117 // so this is endian-neutral. Same for the get_imm below. 1118 uint32_t w = *(uint32_t *)instr; 1119 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1120 } 1121 1122 static int get_imm(address a, int instruction_number) { 1123 return (short)((int *)a)[instruction_number]; 1124 } 1125 1126 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } 1127 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1128 1129 protected: 1130 1131 // Extract the top 32 bits in a 64 bit word. 1132 static int32_t hi32(int64_t x) { 1133 int32_t r = int32_t((uint64_t)x >> 32); 1134 return r; 1135 } 1136 1137 public: 1138 1139 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1140 return ((addr + (a - 1)) & ~(a - 1)); 1141 } 1142 1143 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1144 return (0 == addr % a); 1145 } 1146 1147 void flush() { 1148 AbstractAssembler::flush(); 1149 } 1150 1151 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1152 inline void emit_data(int); 1153 inline void emit_data(int, RelocationHolder const&); 1154 inline void emit_data(int, relocInfo::relocType rtype); 1155 1156 // Emit an address. 1157 inline address emit_addr(const address addr = NULL); 1158 1159 #if !defined(ABI_ELFv2) 1160 // Emit a function descriptor with the specified entry point, TOC, 1161 // and ENV. If the entry point is NULL, the descriptor will point 1162 // just past the descriptor. 1163 // Use values from friend functions as defaults. 1164 inline address emit_fd(address entry = NULL, 1165 address toc = (address) FunctionDescriptor::friend_toc, 1166 address env = (address) FunctionDescriptor::friend_env); 1167 #endif 1168 1169 ///////////////////////////////////////////////////////////////////////////////////// 1170 // PPC instructions 1171 ///////////////////////////////////////////////////////////////////////////////////// 1172 1173 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1174 // immediates. The normal instruction encoders enforce that r0 is not 1175 // passed to them. Use either extended mnemonics encoders or the special ra0 1176 // versions. 1177 1178 // Issue an illegal instruction. 1179 inline void illtrap(); 1180 static inline bool is_illtrap(int x); 1181 1182 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1183 inline void addi( Register d, Register a, int si16); 1184 inline void addis(Register d, Register a, int si16); 1185 private: 1186 inline void addi_r0ok( Register d, Register a, int si16); 1187 inline void addis_r0ok(Register d, Register a, int si16); 1188 public: 1189 inline void addic_( Register d, Register a, int si16); 1190 inline void subfic( Register d, Register a, int si16); 1191 inline void add( Register d, Register a, Register b); 1192 inline void add_( Register d, Register a, Register b); 1193 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1194 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1195 inline void subf_( Register d, Register a, Register b); 1196 inline void addc( Register d, Register a, Register b); 1197 inline void addc_( Register d, Register a, Register b); 1198 inline void subfc( Register d, Register a, Register b); 1199 inline void subfc_( Register d, Register a, Register b); 1200 inline void adde( Register d, Register a, Register b); 1201 inline void adde_( Register d, Register a, Register b); 1202 inline void subfe( Register d, Register a, Register b); 1203 inline void subfe_( Register d, Register a, Register b); 1204 inline void neg( Register d, Register a); 1205 inline void neg_( Register d, Register a); 1206 inline void mulli( Register d, Register a, int si16); 1207 inline void mulld( Register d, Register a, Register b); 1208 inline void mulld_( Register d, Register a, Register b); 1209 inline void mullw( Register d, Register a, Register b); 1210 inline void mullw_( Register d, Register a, Register b); 1211 inline void mulhw( Register d, Register a, Register b); 1212 inline void mulhw_( Register d, Register a, Register b); 1213 inline void mulhwu( Register d, Register a, Register b); 1214 inline void mulhwu_(Register d, Register a, Register b); 1215 inline void mulhd( Register d, Register a, Register b); 1216 inline void mulhd_( Register d, Register a, Register b); 1217 inline void mulhdu( Register d, Register a, Register b); 1218 inline void mulhdu_(Register d, Register a, Register b); 1219 inline void divd( Register d, Register a, Register b); 1220 inline void divd_( Register d, Register a, Register b); 1221 inline void divw( Register d, Register a, Register b); 1222 inline void divw_( Register d, Register a, Register b); 1223 1224 // extended mnemonics 1225 inline void li( Register d, int si16); 1226 inline void lis( Register d, int si16); 1227 inline void addir(Register d, int si16, Register a); 1228 1229 static bool is_addi(int x) { 1230 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1231 } 1232 static bool is_addis(int x) { 1233 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1234 } 1235 static bool is_bxx(int x) { 1236 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1237 } 1238 static bool is_b(int x) { 1239 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1240 } 1241 static bool is_bl(int x) { 1242 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1243 } 1244 static bool is_bcxx(int x) { 1245 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1246 } 1247 static bool is_bxx_or_bcxx(int x) { 1248 return is_bxx(x) || is_bcxx(x); 1249 } 1250 static bool is_bctrl(int x) { 1251 return x == 0x4e800421; 1252 } 1253 static bool is_bctr(int x) { 1254 return x == 0x4e800420; 1255 } 1256 static bool is_bclr(int x) { 1257 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1258 } 1259 static bool is_li(int x) { 1260 return is_addi(x) && inv_ra_field(x)==0; 1261 } 1262 static bool is_lis(int x) { 1263 return is_addis(x) && inv_ra_field(x)==0; 1264 } 1265 static bool is_mtctr(int x) { 1266 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1267 } 1268 static bool is_ld(int x) { 1269 return LD_OPCODE == (x & LD_OPCODE_MASK); 1270 } 1271 static bool is_std(int x) { 1272 return STD_OPCODE == (x & STD_OPCODE_MASK); 1273 } 1274 static bool is_stdu(int x) { 1275 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1276 } 1277 static bool is_stdx(int x) { 1278 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1279 } 1280 static bool is_stdux(int x) { 1281 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1282 } 1283 static bool is_stwx(int x) { 1284 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1285 } 1286 static bool is_stwux(int x) { 1287 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1288 } 1289 static bool is_stw(int x) { 1290 return STW_OPCODE == (x & STW_OPCODE_MASK); 1291 } 1292 static bool is_stwu(int x) { 1293 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1294 } 1295 static bool is_ori(int x) { 1296 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1297 }; 1298 static bool is_oris(int x) { 1299 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1300 }; 1301 static bool is_rldicr(int x) { 1302 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1303 }; 1304 static bool is_nop(int x) { 1305 return x == 0x60000000; 1306 } 1307 // endgroup opcode for Power6 1308 static bool is_endgroup(int x) { 1309 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1310 } 1311 1312 1313 private: 1314 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1315 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1316 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1317 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1318 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1319 1320 public: 1321 // extended mnemonics of Compare Instructions 1322 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1323 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1324 inline void cmpw( ConditionRegister crx, Register a, Register b); 1325 inline void cmpd( ConditionRegister crx, Register a, Register b); 1326 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1327 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1328 inline void cmplw( ConditionRegister crx, Register a, Register b); 1329 inline void cmpld( ConditionRegister crx, Register a, Register b); 1330 1331 inline void isel( Register d, Register a, Register b, int bc); 1332 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1333 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1334 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1335 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1336 1337 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1338 void andi( Register a, Register s, int ui16); // optimized version 1339 inline void andi_( Register a, Register s, int ui16); 1340 inline void andis_( Register a, Register s, int ui16); 1341 inline void ori( Register a, Register s, int ui16); 1342 inline void oris( Register a, Register s, int ui16); 1343 inline void xori( Register a, Register s, int ui16); 1344 inline void xoris( Register a, Register s, int ui16); 1345 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1346 inline void and_( Register a, Register s, Register b); 1347 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a 1348 // SMT-priority change instruction (see SMT instructions below). 1349 inline void or_unchecked(Register a, Register s, Register b); 1350 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1351 inline void or_( Register a, Register s, Register b); 1352 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1353 inline void xor_( Register a, Register s, Register b); 1354 inline void nand( Register a, Register s, Register b); 1355 inline void nand_( Register a, Register s, Register b); 1356 inline void nor( Register a, Register s, Register b); 1357 inline void nor_( Register a, Register s, Register b); 1358 inline void andc( Register a, Register s, Register b); 1359 inline void andc_( Register a, Register s, Register b); 1360 inline void orc( Register a, Register s, Register b); 1361 inline void orc_( Register a, Register s, Register b); 1362 inline void extsb( Register a, Register s); 1363 inline void extsh( Register a, Register s); 1364 inline void extsw( Register a, Register s); 1365 1366 // extended mnemonics 1367 inline void nop(); 1368 // NOP for FP and BR units (different versions to allow them to be in one group) 1369 inline void fpnop0(); 1370 inline void fpnop1(); 1371 inline void brnop0(); 1372 inline void brnop1(); 1373 inline void brnop2(); 1374 1375 inline void mr( Register d, Register s); 1376 inline void ori_opt( Register d, int ui16); 1377 inline void oris_opt(Register d, int ui16); 1378 1379 // endgroup opcode for Power6 1380 inline void endgroup(); 1381 1382 // count instructions 1383 inline void cntlzw( Register a, Register s); 1384 inline void cntlzw_( Register a, Register s); 1385 inline void cntlzd( Register a, Register s); 1386 inline void cntlzd_( Register a, Register s); 1387 1388 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1389 inline void sld( Register a, Register s, Register b); 1390 inline void sld_( Register a, Register s, Register b); 1391 inline void slw( Register a, Register s, Register b); 1392 inline void slw_( Register a, Register s, Register b); 1393 inline void srd( Register a, Register s, Register b); 1394 inline void srd_( Register a, Register s, Register b); 1395 inline void srw( Register a, Register s, Register b); 1396 inline void srw_( Register a, Register s, Register b); 1397 inline void srad( Register a, Register s, Register b); 1398 inline void srad_( Register a, Register s, Register b); 1399 inline void sraw( Register a, Register s, Register b); 1400 inline void sraw_( Register a, Register s, Register b); 1401 inline void sradi( Register a, Register s, int sh6); 1402 inline void sradi_( Register a, Register s, int sh6); 1403 inline void srawi( Register a, Register s, int sh5); 1404 inline void srawi_( Register a, Register s, int sh5); 1405 1406 // extended mnemonics for Shift Instructions 1407 inline void sldi( Register a, Register s, int sh6); 1408 inline void sldi_( Register a, Register s, int sh6); 1409 inline void slwi( Register a, Register s, int sh5); 1410 inline void slwi_( Register a, Register s, int sh5); 1411 inline void srdi( Register a, Register s, int sh6); 1412 inline void srdi_( Register a, Register s, int sh6); 1413 inline void srwi( Register a, Register s, int sh5); 1414 inline void srwi_( Register a, Register s, int sh5); 1415 1416 inline void clrrdi( Register a, Register s, int ui6); 1417 inline void clrrdi_( Register a, Register s, int ui6); 1418 inline void clrldi( Register a, Register s, int ui6); 1419 inline void clrldi_( Register a, Register s, int ui6); 1420 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1421 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1422 inline void extrdi( Register a, Register s, int n, int b); 1423 // testbit with condition register 1424 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1425 1426 // rotate instructions 1427 inline void rotldi( Register a, Register s, int n); 1428 inline void rotrdi( Register a, Register s, int n); 1429 inline void rotlwi( Register a, Register s, int n); 1430 inline void rotrwi( Register a, Register s, int n); 1431 1432 // Rotate Instructions 1433 inline void rldic( Register a, Register s, int sh6, int mb6); 1434 inline void rldic_( Register a, Register s, int sh6, int mb6); 1435 inline void rldicr( Register a, Register s, int sh6, int mb6); 1436 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1437 inline void rldicl( Register a, Register s, int sh6, int mb6); 1438 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1439 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1440 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1441 inline void rldimi( Register a, Register s, int sh6, int mb6); 1442 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1443 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1444 inline void insrdi( Register a, Register s, int n, int b); 1445 inline void insrwi( Register a, Register s, int n, int b); 1446 1447 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1448 // 4 bytes 1449 inline void lwzx( Register d, Register s1, Register s2); 1450 inline void lwz( Register d, int si16, Register s1); 1451 inline void lwzu( Register d, int si16, Register s1); 1452 1453 // 4 bytes 1454 inline void lwax( Register d, Register s1, Register s2); 1455 inline void lwa( Register d, int si16, Register s1); 1456 1457 // 4 bytes reversed 1458 inline void lwbrx( Register d, Register s1, Register s2); 1459 1460 // 2 bytes 1461 inline void lhzx( Register d, Register s1, Register s2); 1462 inline void lhz( Register d, int si16, Register s1); 1463 inline void lhzu( Register d, int si16, Register s1); 1464 1465 // 2 bytes reversed 1466 inline void lhbrx( Register d, Register s1, Register s2); 1467 1468 // 2 bytes 1469 inline void lhax( Register d, Register s1, Register s2); 1470 inline void lha( Register d, int si16, Register s1); 1471 inline void lhau( Register d, int si16, Register s1); 1472 1473 // 1 byte 1474 inline void lbzx( Register d, Register s1, Register s2); 1475 inline void lbz( Register d, int si16, Register s1); 1476 inline void lbzu( Register d, int si16, Register s1); 1477 1478 // 8 bytes 1479 inline void ldx( Register d, Register s1, Register s2); 1480 inline void ld( Register d, int si16, Register s1); 1481 inline void ldu( Register d, int si16, Register s1); 1482 1483 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1484 inline void stwx( Register d, Register s1, Register s2); 1485 inline void stw( Register d, int si16, Register s1); 1486 inline void stwu( Register d, int si16, Register s1); 1487 1488 inline void sthx( Register d, Register s1, Register s2); 1489 inline void sth( Register d, int si16, Register s1); 1490 inline void sthu( Register d, int si16, Register s1); 1491 1492 inline void stbx( Register d, Register s1, Register s2); 1493 inline void stb( Register d, int si16, Register s1); 1494 inline void stbu( Register d, int si16, Register s1); 1495 1496 inline void stdx( Register d, Register s1, Register s2); 1497 inline void std( Register d, int si16, Register s1); 1498 inline void stdu( Register d, int si16, Register s1); 1499 inline void stdux(Register s, Register a, Register b); 1500 1501 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1502 inline void mtlr( Register s1); 1503 inline void mflr( Register d); 1504 inline void mtctr(Register s1); 1505 inline void mfctr(Register d); 1506 inline void mtcrf(int fxm, Register s); 1507 inline void mfcr( Register d); 1508 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1509 inline void mtcr( Register s); 1510 1511 // Special purpose registers 1512 // Exception Register 1513 inline void mtxer(Register s1); 1514 inline void mfxer(Register d); 1515 // Vector Register Save Register 1516 inline void mtvrsave(Register s1); 1517 inline void mfvrsave(Register d); 1518 // Timebase 1519 inline void mftb(Register d); 1520 // Introduced with Power 8: 1521 // Data Stream Control Register 1522 inline void mtdscr(Register s1); 1523 inline void mfdscr(Register d ); 1524 // Transactional Memory Registers 1525 inline void mftfhar(Register d); 1526 inline void mftfiar(Register d); 1527 inline void mftexasr(Register d); 1528 inline void mftexasru(Register d); 1529 1530 // PPC 1, section 2.4.1 Branch Instructions 1531 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1532 inline void b( Label& L); 1533 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1534 inline void bl( Label& L); 1535 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1536 inline void bc( int boint, int biint, Label& L); 1537 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1538 inline void bcl(int boint, int biint, Label& L); 1539 1540 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1541 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1542 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1543 relocInfo::relocType rt = relocInfo::none); 1544 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1545 relocInfo::relocType rt = relocInfo::none); 1546 1547 // helper function for b, bcxx 1548 inline bool is_within_range_of_b(address a, address pc); 1549 inline bool is_within_range_of_bcxx(address a, address pc); 1550 1551 // get the destination of a bxx branch (b, bl, ba, bla) 1552 static inline address bxx_destination(address baddr); 1553 static inline address bxx_destination(int instr, address pc); 1554 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1555 1556 // extended mnemonics for branch instructions 1557 inline void blt(ConditionRegister crx, Label& L); 1558 inline void bgt(ConditionRegister crx, Label& L); 1559 inline void beq(ConditionRegister crx, Label& L); 1560 inline void bso(ConditionRegister crx, Label& L); 1561 inline void bge(ConditionRegister crx, Label& L); 1562 inline void ble(ConditionRegister crx, Label& L); 1563 inline void bne(ConditionRegister crx, Label& L); 1564 inline void bns(ConditionRegister crx, Label& L); 1565 1566 // Branch instructions with static prediction hints. 1567 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1568 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1569 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1570 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1571 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1572 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1573 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1574 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1575 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1576 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1577 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1578 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1579 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1580 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1581 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1582 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1583 1584 // for use in conjunction with testbitdi: 1585 inline void btrue( ConditionRegister crx, Label& L); 1586 inline void bfalse(ConditionRegister crx, Label& L); 1587 1588 inline void bltl(ConditionRegister crx, Label& L); 1589 inline void bgtl(ConditionRegister crx, Label& L); 1590 inline void beql(ConditionRegister crx, Label& L); 1591 inline void bsol(ConditionRegister crx, Label& L); 1592 inline void bgel(ConditionRegister crx, Label& L); 1593 inline void blel(ConditionRegister crx, Label& L); 1594 inline void bnel(ConditionRegister crx, Label& L); 1595 inline void bnsl(ConditionRegister crx, Label& L); 1596 1597 // extended mnemonics for Branch Instructions via LR 1598 // We use `blr' for returns. 1599 inline void blr(relocInfo::relocType rt = relocInfo::none); 1600 1601 // extended mnemonics for Branch Instructions with CTR 1602 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1603 inline void bdnz(Label& L); 1604 // Decrement and branch if result is zero. 1605 inline void bdz(Label& L); 1606 // we use `bctr[l]' for jumps/calls in function descriptor glue 1607 // code, e.g. calls to runtime functions 1608 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1609 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1610 // conditional jumps/branches via CTR 1611 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1612 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1613 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1614 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1615 1616 // condition register logic instructions 1617 inline void crand( int d, int s1, int s2); 1618 inline void crnand(int d, int s1, int s2); 1619 inline void cror( int d, int s1, int s2); 1620 inline void crxor( int d, int s1, int s2); 1621 inline void crnor( int d, int s1, int s2); 1622 inline void creqv( int d, int s1, int s2); 1623 inline void crandc(int d, int s1, int s2); 1624 inline void crorc( int d, int s1, int s2); 1625 1626 // icache and dcache related instructions 1627 inline void icbi( Register s1, Register s2); 1628 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1629 inline void dcbz( Register s1, Register s2); 1630 inline void dcbst( Register s1, Register s2); 1631 inline void dcbf( Register s1, Register s2); 1632 1633 enum ct_cache_specification { 1634 ct_primary_cache = 0, 1635 ct_secondary_cache = 2 1636 }; 1637 // dcache read hint 1638 inline void dcbt( Register s1, Register s2); 1639 inline void dcbtct( Register s1, Register s2, int ct); 1640 inline void dcbtds( Register s1, Register s2, int ds); 1641 // dcache write hint 1642 inline void dcbtst( Register s1, Register s2); 1643 inline void dcbtstct(Register s1, Register s2, int ct); 1644 1645 // machine barrier instructions: 1646 // 1647 // - sync two-way memory barrier, aka fence 1648 // - lwsync orders Store|Store, 1649 // Load|Store, 1650 // Load|Load, 1651 // but not Store|Load 1652 // - eieio orders memory accesses for device memory (only) 1653 // - isync invalidates speculatively executed instructions 1654 // From the Power ISA 2.06 documentation: 1655 // "[...] an isync instruction prevents the execution of 1656 // instructions following the isync until instructions 1657 // preceding the isync have completed, [...]" 1658 // From IBM's AIX assembler reference: 1659 // "The isync [...] instructions causes the processor to 1660 // refetch any instructions that might have been fetched 1661 // prior to the isync instruction. The instruction isync 1662 // causes the processor to wait for all previous instructions 1663 // to complete. Then any instructions already fetched are 1664 // discarded and instruction processing continues in the 1665 // environment established by the previous instructions." 1666 // 1667 // semantic barrier instructions: 1668 // (as defined in orderAccess.hpp) 1669 // 1670 // - release orders Store|Store, (maps to lwsync) 1671 // Load|Store 1672 // - acquire orders Load|Store, (maps to lwsync) 1673 // Load|Load 1674 // - fence orders Store|Store, (maps to sync) 1675 // Load|Store, 1676 // Load|Load, 1677 // Store|Load 1678 // 1679 private: 1680 inline void sync(int l); 1681 public: 1682 inline void sync(); 1683 inline void lwsync(); 1684 inline void ptesync(); 1685 inline void eieio(); 1686 inline void isync(); 1687 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 1688 1689 // atomics 1690 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1691 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1692 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1693 inline bool lxarx_hint_exclusive_access(); 1694 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1695 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1696 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1697 inline void stwcx_( Register s, Register a, Register b); 1698 inline void stdcx_( Register s, Register a, Register b); 1699 inline void stqcx_( Register s, Register a, Register b); 1700 1701 // Instructions for adjusting thread priority for simultaneous 1702 // multithreading (SMT) on Power5. 1703 private: 1704 inline void smt_prio_very_low(); 1705 inline void smt_prio_medium_high(); 1706 inline void smt_prio_high(); 1707 1708 public: 1709 inline void smt_prio_low(); 1710 inline void smt_prio_medium_low(); 1711 inline void smt_prio_medium(); 1712 1713 // trap instructions 1714 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 1715 // NOT FOR DIRECT USE!! 1716 protected: 1717 inline void tdi_unchecked(int tobits, Register a, int si16); 1718 inline void twi_unchecked(int tobits, Register a, int si16); 1719 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1720 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1721 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 1722 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 1723 1724 static bool is_tdi(int x, int tobits, int ra, int si16) { 1725 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 1726 && (tobits == inv_to_field(x)) 1727 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1728 && (si16 == inv_si_field(x)); 1729 } 1730 1731 static bool is_twi(int x, int tobits, int ra, int si16) { 1732 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1733 && (tobits == inv_to_field(x)) 1734 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1735 && (si16 == inv_si_field(x)); 1736 } 1737 1738 static bool is_twi(int x, int tobits, int ra) { 1739 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1740 && (tobits == inv_to_field(x)) 1741 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 1742 } 1743 1744 static bool is_td(int x, int tobits, int ra, int rb) { 1745 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 1746 && (tobits == inv_to_field(x)) 1747 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1748 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1749 } 1750 1751 static bool is_tw(int x, int tobits, int ra, int rb) { 1752 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 1753 && (tobits == inv_to_field(x)) 1754 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1755 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1756 } 1757 1758 public: 1759 // PPC floating point instructions 1760 // PPC 1, section 4.6.2 Floating-Point Load Instructions 1761 inline void lfs( FloatRegister d, int si16, Register a); 1762 inline void lfsu( FloatRegister d, int si16, Register a); 1763 inline void lfsx( FloatRegister d, Register a, Register b); 1764 inline void lfd( FloatRegister d, int si16, Register a); 1765 inline void lfdu( FloatRegister d, int si16, Register a); 1766 inline void lfdx( FloatRegister d, Register a, Register b); 1767 1768 // PPC 1, section 4.6.3 Floating-Point Store Instructions 1769 inline void stfs( FloatRegister s, int si16, Register a); 1770 inline void stfsu( FloatRegister s, int si16, Register a); 1771 inline void stfsx( FloatRegister s, Register a, Register b); 1772 inline void stfd( FloatRegister s, int si16, Register a); 1773 inline void stfdu( FloatRegister s, int si16, Register a); 1774 inline void stfdx( FloatRegister s, Register a, Register b); 1775 1776 // PPC 1, section 4.6.4 Floating-Point Move Instructions 1777 inline void fmr( FloatRegister d, FloatRegister b); 1778 inline void fmr_( FloatRegister d, FloatRegister b); 1779 1780 // inline void mffgpr( FloatRegister d, Register b); 1781 // inline void mftgpr( Register d, FloatRegister b); 1782 inline void cmpb( Register a, Register s, Register b); 1783 inline void popcntb(Register a, Register s); 1784 inline void popcntw(Register a, Register s); 1785 inline void popcntd(Register a, Register s); 1786 1787 inline void fneg( FloatRegister d, FloatRegister b); 1788 inline void fneg_( FloatRegister d, FloatRegister b); 1789 inline void fabs( FloatRegister d, FloatRegister b); 1790 inline void fabs_( FloatRegister d, FloatRegister b); 1791 inline void fnabs( FloatRegister d, FloatRegister b); 1792 inline void fnabs_(FloatRegister d, FloatRegister b); 1793 1794 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 1795 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 1796 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 1797 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 1798 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 1799 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 1800 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 1801 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 1802 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 1803 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 1804 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 1805 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 1806 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 1807 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 1808 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 1809 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 1810 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 1811 1812 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 1813 inline void frsp( FloatRegister d, FloatRegister b); 1814 inline void fctid( FloatRegister d, FloatRegister b); 1815 inline void fctidz(FloatRegister d, FloatRegister b); 1816 inline void fctiw( FloatRegister d, FloatRegister b); 1817 inline void fctiwz(FloatRegister d, FloatRegister b); 1818 inline void fcfid( FloatRegister d, FloatRegister b); 1819 inline void fcfids(FloatRegister d, FloatRegister b); 1820 1821 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 1822 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 1823 1824 inline void fsqrt( FloatRegister d, FloatRegister b); 1825 inline void fsqrts(FloatRegister d, FloatRegister b); 1826 1827 // Vector instructions for >= Power6. 1828 inline void lvebx( VectorRegister d, Register s1, Register s2); 1829 inline void lvehx( VectorRegister d, Register s1, Register s2); 1830 inline void lvewx( VectorRegister d, Register s1, Register s2); 1831 inline void lvx( VectorRegister d, Register s1, Register s2); 1832 inline void lvxl( VectorRegister d, Register s1, Register s2); 1833 inline void stvebx( VectorRegister d, Register s1, Register s2); 1834 inline void stvehx( VectorRegister d, Register s1, Register s2); 1835 inline void stvewx( VectorRegister d, Register s1, Register s2); 1836 inline void stvx( VectorRegister d, Register s1, Register s2); 1837 inline void stvxl( VectorRegister d, Register s1, Register s2); 1838 inline void lvsl( VectorRegister d, Register s1, Register s2); 1839 inline void lvsr( VectorRegister d, Register s1, Register s2); 1840 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 1841 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 1842 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 1843 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 1844 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 1845 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 1846 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 1847 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 1848 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 1849 inline void vupkhpx( VectorRegister d, VectorRegister b); 1850 inline void vupkhsb( VectorRegister d, VectorRegister b); 1851 inline void vupkhsh( VectorRegister d, VectorRegister b); 1852 inline void vupklpx( VectorRegister d, VectorRegister b); 1853 inline void vupklsb( VectorRegister d, VectorRegister b); 1854 inline void vupklsh( VectorRegister d, VectorRegister b); 1855 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 1856 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 1857 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 1858 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 1859 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 1860 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 1861 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 1862 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 1863 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 1864 inline void vspltisb( VectorRegister d, int si5); 1865 inline void vspltish( VectorRegister d, int si5); 1866 inline void vspltisw( VectorRegister d, int si5); 1867 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1868 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1869 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 1870 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4); 1871 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 1872 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 1873 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 1874 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 1875 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 1876 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 1877 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 1878 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 1879 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 1880 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 1881 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b); 1882 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 1883 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 1884 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 1885 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 1886 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 1887 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 1888 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 1889 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 1890 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 1891 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 1892 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 1893 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 1894 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 1895 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 1896 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 1897 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 1898 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 1899 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 1900 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 1901 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 1902 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 1903 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1904 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 1905 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1906 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1907 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1908 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1909 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1910 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1911 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1912 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 1913 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 1914 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 1915 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 1916 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 1917 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 1918 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 1919 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 1920 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 1921 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 1922 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 1923 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 1924 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 1925 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 1926 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 1927 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 1928 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 1929 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 1930 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 1931 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 1932 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 1933 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 1934 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 1935 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 1936 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 1937 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 1938 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 1939 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 1940 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 1941 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 1942 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 1943 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 1944 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 1945 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 1946 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 1947 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 1948 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 1949 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 1950 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 1951 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 1952 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 1953 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 1954 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 1955 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 1956 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 1957 inline void vmr( VectorRegister d, VectorRegister a); 1958 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 1959 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 1960 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 1961 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 1962 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 1963 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 1964 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 1965 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 1966 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 1967 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 1968 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 1969 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 1970 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 1971 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 1972 // Vector Floating-Point not implemented yet 1973 inline void mtvscr( VectorRegister b); 1974 inline void mfvscr( VectorRegister d); 1975 1976 // Vector-Scalar (VSX) instructions. 1977 inline void lxvd2x( VectorSRegister d, Register a); 1978 inline void lxvd2x( VectorSRegister d, Register a, Register b); 1979 inline void stxvd2x( VectorSRegister d, Register a); 1980 inline void stxvd2x( VectorSRegister d, Register a, Register b); 1981 inline void mtvrwz( VectorRegister d, Register a); 1982 inline void mfvrwz( Register a, VectorRegister d); 1983 inline void mtvrd( VectorRegister d, Register a); 1984 inline void mfvrd( Register a, VectorRegister d); 1985 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm); 1986 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1987 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1988 1989 // VSX Extended Mnemonics 1990 inline void xxspltd( VectorSRegister d, VectorSRegister a, int x); 1991 inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1992 inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1993 inline void xxswapd( VectorSRegister d, VectorSRegister a); 1994 1995 // AES (introduced with Power 8) 1996 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 1997 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 1998 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 1999 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2000 inline void vsbox( VectorRegister d, VectorRegister a); 2001 2002 // SHA (introduced with Power 8) 2003 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); 2004 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); 2005 2006 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2007 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2008 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2009 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2010 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2011 2012 // Vector Permute and Xor (introduced with Power 8) 2013 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2014 2015 // Transactional Memory instructions (introduced with Power 8) 2016 inline void tbegin_(); // R=0 2017 inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2018 inline void tend_(); // A=0 2019 inline void tendall_(); // A=1 2020 inline void tabort_(Register a); 2021 inline void tabortwc_(int t, Register a, Register b); 2022 inline void tabortwci_(int t, Register a, int si); 2023 inline void tabortdc_(int t, Register a, Register b); 2024 inline void tabortdci_(int t, Register a, int si); 2025 inline void tsuspend_(); // tsr with L=0 2026 inline void tresume_(); // tsr with L=1 2027 inline void tcheck(int f); 2028 2029 // The following encoders use r0 as second operand. These instructions 2030 // read r0 as '0'. 2031 inline void lwzx( Register d, Register s2); 2032 inline void lwz( Register d, int si16); 2033 inline void lwax( Register d, Register s2); 2034 inline void lwa( Register d, int si16); 2035 inline void lwbrx(Register d, Register s2); 2036 inline void lhzx( Register d, Register s2); 2037 inline void lhz( Register d, int si16); 2038 inline void lhax( Register d, Register s2); 2039 inline void lha( Register d, int si16); 2040 inline void lhbrx(Register d, Register s2); 2041 inline void lbzx( Register d, Register s2); 2042 inline void lbz( Register d, int si16); 2043 inline void ldx( Register d, Register s2); 2044 inline void ld( Register d, int si16); 2045 inline void stwx( Register d, Register s2); 2046 inline void stw( Register d, int si16); 2047 inline void sthx( Register d, Register s2); 2048 inline void sth( Register d, int si16); 2049 inline void stbx( Register d, Register s2); 2050 inline void stb( Register d, int si16); 2051 inline void stdx( Register d, Register s2); 2052 inline void std( Register d, int si16); 2053 2054 // PPC 2, section 3.2.1 Instruction Cache Instructions 2055 inline void icbi( Register s2); 2056 // PPC 2, section 3.2.2 Data Cache Instructions 2057 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2058 inline void dcbz( Register s2); 2059 inline void dcbst( Register s2); 2060 inline void dcbf( Register s2); 2061 // dcache read hint 2062 inline void dcbt( Register s2); 2063 inline void dcbtct( Register s2, int ct); 2064 inline void dcbtds( Register s2, int ds); 2065 // dcache write hint 2066 inline void dcbtst( Register s2); 2067 inline void dcbtstct(Register s2, int ct); 2068 2069 // Atomics: use ra0mem to disallow R0 as base. 2070 inline void lwarx_unchecked(Register d, Register b, int eh1); 2071 inline void ldarx_unchecked(Register d, Register b, int eh1); 2072 inline void lqarx_unchecked(Register d, Register b, int eh1); 2073 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2074 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2075 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2076 inline void stwcx_(Register s, Register b); 2077 inline void stdcx_(Register s, Register b); 2078 inline void stqcx_(Register s, Register b); 2079 inline void lfs( FloatRegister d, int si16); 2080 inline void lfsx( FloatRegister d, Register b); 2081 inline void lfd( FloatRegister d, int si16); 2082 inline void lfdx( FloatRegister d, Register b); 2083 inline void stfs( FloatRegister s, int si16); 2084 inline void stfsx( FloatRegister s, Register b); 2085 inline void stfd( FloatRegister s, int si16); 2086 inline void stfdx( FloatRegister s, Register b); 2087 inline void lvebx( VectorRegister d, Register s2); 2088 inline void lvehx( VectorRegister d, Register s2); 2089 inline void lvewx( VectorRegister d, Register s2); 2090 inline void lvx( VectorRegister d, Register s2); 2091 inline void lvxl( VectorRegister d, Register s2); 2092 inline void stvebx(VectorRegister d, Register s2); 2093 inline void stvehx(VectorRegister d, Register s2); 2094 inline void stvewx(VectorRegister d, Register s2); 2095 inline void stvx( VectorRegister d, Register s2); 2096 inline void stvxl( VectorRegister d, Register s2); 2097 inline void lvsl( VectorRegister d, Register s2); 2098 inline void lvsr( VectorRegister d, Register s2); 2099 2100 // Endianess specific concatenation of 2 loaded vectors. 2101 inline void load_perm(VectorRegister perm, Register addr); 2102 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); 2103 2104 // RegisterOrConstant versions. 2105 // These emitters choose between the versions using two registers and 2106 // those with register and immediate, depending on the content of roc. 2107 // If the constant is not encodable as immediate, instructions to 2108 // load the constant are emitted beforehand. Store instructions need a 2109 // tmp reg if the constant is not encodable as immediate. 2110 // Size unpredictable. 2111 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2112 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2113 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2114 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2115 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2116 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2117 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2118 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2119 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2120 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2121 void add( Register d, RegisterOrConstant roc, Register s1); 2122 void subf(Register d, RegisterOrConstant roc, Register s1); 2123 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); 2124 2125 2126 // Emit several instructions to load a 64 bit constant. This issues a fixed 2127 // instruction pattern so that the constant can be patched later on. 2128 enum { 2129 load_const_size = 5 * BytesPerInstWord 2130 }; 2131 void load_const(Register d, long a, Register tmp = noreg); 2132 inline void load_const(Register d, void* a, Register tmp = noreg); 2133 inline void load_const(Register d, Label& L, Register tmp = noreg); 2134 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2135 2136 // Load a 64 bit constant, optimized, not identifyable. 2137 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2138 // 16 bit immediate offset. This is useful if the offset can be encoded in 2139 // a succeeding instruction. 2140 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); 2141 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2142 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2143 } 2144 2145 // Creation 2146 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2147 #ifdef CHECK_DELAY 2148 delay_state = no_delay; 2149 #endif 2150 } 2151 2152 // Testing 2153 #ifndef PRODUCT 2154 void test_asm(); 2155 #endif 2156 }; 2157 2158 2159 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP