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src/cpu/ppc/vm/assembler_ppc.hpp

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2083   inline void stfs(  FloatRegister s, int si16);
2084   inline void stfsx( FloatRegister s, Register b);
2085   inline void stfd(  FloatRegister s, int si16);
2086   inline void stfdx( FloatRegister s, Register b);
2087   inline void lvebx( VectorRegister d, Register s2);
2088   inline void lvehx( VectorRegister d, Register s2);
2089   inline void lvewx( VectorRegister d, Register s2);
2090   inline void lvx(   VectorRegister d, Register s2);
2091   inline void lvxl(  VectorRegister d, Register s2);
2092   inline void stvebx(VectorRegister d, Register s2);
2093   inline void stvehx(VectorRegister d, Register s2);
2094   inline void stvewx(VectorRegister d, Register s2);
2095   inline void stvx(  VectorRegister d, Register s2);
2096   inline void stvxl( VectorRegister d, Register s2);
2097   inline void lvsl(  VectorRegister d, Register s2);
2098   inline void lvsr(  VectorRegister d, Register s2);
2099 
2100   // Endianess specific concatenation of 2 loaded vectors.
2101   inline void load_perm(VectorRegister perm, Register addr);
2102   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);

2103 
2104   // RegisterOrConstant versions.
2105   // These emitters choose between the versions using two registers and
2106   // those with register and immediate, depending on the content of roc.
2107   // If the constant is not encodable as immediate, instructions to
2108   // load the constant are emitted beforehand. Store instructions need a
2109   // tmp reg if the constant is not encodable as immediate.
2110   // Size unpredictable.
2111   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2112   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2113   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2114   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2115   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2116   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2117   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2118   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2119   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2120   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2121   void add( Register d, RegisterOrConstant roc, Register s1);
2122   void subf(Register d, RegisterOrConstant roc, Register s1);




2083   inline void stfs(  FloatRegister s, int si16);
2084   inline void stfsx( FloatRegister s, Register b);
2085   inline void stfd(  FloatRegister s, int si16);
2086   inline void stfdx( FloatRegister s, Register b);
2087   inline void lvebx( VectorRegister d, Register s2);
2088   inline void lvehx( VectorRegister d, Register s2);
2089   inline void lvewx( VectorRegister d, Register s2);
2090   inline void lvx(   VectorRegister d, Register s2);
2091   inline void lvxl(  VectorRegister d, Register s2);
2092   inline void stvebx(VectorRegister d, Register s2);
2093   inline void stvehx(VectorRegister d, Register s2);
2094   inline void stvewx(VectorRegister d, Register s2);
2095   inline void stvx(  VectorRegister d, Register s2);
2096   inline void stvxl( VectorRegister d, Register s2);
2097   inline void lvsl(  VectorRegister d, Register s2);
2098   inline void lvsr(  VectorRegister d, Register s2);
2099 
2100   // Endianess specific concatenation of 2 loaded vectors.
2101   inline void load_perm(VectorRegister perm, Register addr);
2102   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
2103   inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
2104 
2105   // RegisterOrConstant versions.
2106   // These emitters choose between the versions using two registers and
2107   // those with register and immediate, depending on the content of roc.
2108   // If the constant is not encodable as immediate, instructions to
2109   // load the constant are emitted beforehand. Store instructions need a
2110   // tmp reg if the constant is not encodable as immediate.
2111   // Size unpredictable.
2112   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2113   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2114   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2115   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2116   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2117   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2118   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2119   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2120   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2121   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2122   void add( Register d, RegisterOrConstant roc, Register s1);
2123   void subf(Register d, RegisterOrConstant roc, Register s1);


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