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src/hotspot/cpu/sparc/sparc.ad

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2611 
2612 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2613     MacroAssembler _masm(&cbuf);
2614 
2615     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2616     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2617 
2618     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2619 %}
2620 
2621 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2622     MacroAssembler _masm(&cbuf);
2623 
2624     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2625     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2626 
2627     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2628 %}
2629 
2630 
2631 
2632 enc_class fmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2633     MacroAssembler _masm(&cbuf);
2634 
2635     FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2636     FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2637     FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2638     FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2639 
2640     __ fmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2641 %}
2642 
2643 enc_class fmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2644     MacroAssembler _masm(&cbuf);
2645 
2646     FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2647     FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2648     FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2649     FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2650 
2651     __ fmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2652 %}
2653 


2654 




2655 


2656 
























































2657 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2658     MacroAssembler _masm(&cbuf);
2659 
2660     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2661     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2662 
2663     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2664 %}
2665 
2666 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2667     MacroAssembler _masm(&cbuf);
2668 
2669     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2670     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2671 
2672     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2673 %}
2674 
2675 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2676     MacroAssembler _masm(&cbuf);


7580 //  Sqrt float double precision
7581 instruct sqrtF_reg_reg(regF dst, regF src) %{
7582   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7583 
7584   size(4);
7585   format %{ "FSQRTS $src,$dst" %}
7586   ins_encode(fsqrts(dst, src));
7587   ins_pipe(fdivF_reg_reg);
7588 %}
7589 
7590 //  Sqrt float double precision
7591 instruct sqrtD_reg_reg(regD dst, regD src) %{
7592   match(Set dst (SqrtD src));
7593 
7594   size(4);
7595   format %{ "FSQRTD $src,$dst" %}
7596   ins_encode(fsqrtd(dst, src));
7597   ins_pipe(fdivD_reg_reg);
7598 %}
7599 
7600 // Single precision fused floating-point multiply-add (d = a * b + c).
7601 instruct fmaF_regx4(regF dst, regF a, regF b, regF c) %{
7602   predicate(UseFMA);
7603   match(Set dst (FmaF c (Binary a b)));
7604   format %{ "fmadds $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7605   ins_encode(fmadds(dst, a, b, c));
7606   ins_pipe(fmaF_regx4);
7607 %}
7608 
7609 // Double precision fused floating-point multiply-add (d = a * b + c).
7610 instruct fmaD_regx4(regD dst, regD a, regD b, regD c) %{
7611   predicate(UseFMA);
7612   match(Set dst (FmaD c (Binary a b)));
7613   format %{ "fmaddd $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7614   ins_encode(fmaddd(dst, a, b, c));
7615   ins_pipe(fmaD_regx4);
7616 %}




























































7617 
7618 //----------Logical Instructions-----------------------------------------------
7619 // And Instructions
7620 // Register And
7621 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7622   match(Set dst (AndI src1 src2));
7623 
7624   size(4);
7625   format %{ "AND    $src1,$src2,$dst" %}
7626   opcode(Assembler::and_op3, Assembler::arith_op);
7627   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7628   ins_pipe(ialu_reg_reg);
7629 %}
7630 
7631 // Immediate And
7632 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7633   match(Set dst (AndI src1 src2));
7634 
7635   size(4);
7636   format %{ "AND    $src1,$src2,$dst" %}




2611 
2612 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2613     MacroAssembler _masm(&cbuf);
2614 
2615     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2616     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2617 
2618     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2619 %}
2620 
2621 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2622     MacroAssembler _masm(&cbuf);
2623 
2624     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2625     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2626 
2627     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2628 %}
2629 
2630 

2631 enc_class fmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2632     MacroAssembler _masm(&cbuf);
2633 
2634     FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2635     FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2636     FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2637     FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2638 
2639     __ fmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2640 %}
2641 
2642 enc_class fmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2643     MacroAssembler _masm(&cbuf);
2644 
2645     FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2646     FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2647     FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2648     FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2649 
2650     __ fmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2651 %}
2652 
2653 enc_class fmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2654     MacroAssembler _masm(&cbuf);
2655 
2656     FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2657     FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2658     FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2659     FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2660 
2661     __ fmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2662 %}
2663 
2664 enc_class fmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2665     MacroAssembler _masm(&cbuf);
2666 
2667     FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2668     FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2669     FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2670     FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2671 
2672     __ fmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2673 %}
2674 
2675 enc_class fnmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2676     MacroAssembler _masm(&cbuf);
2677 
2678     FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2679     FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2680     FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2681     FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2682 
2683     __ fnmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2684 %}
2685 
2686 enc_class fnmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2687     MacroAssembler _masm(&cbuf);
2688 
2689     FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2690     FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2691     FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2692     FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2693 
2694     __ fnmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2695 %}
2696 
2697 enc_class fnmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{
2698     MacroAssembler _masm(&cbuf);
2699 
2700     FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg);
2701     FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg);
2702     FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg);
2703     FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg);
2704 
2705     __ fnmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd);
2706 %}
2707 
2708 enc_class fnmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{
2709     MacroAssembler _masm(&cbuf);
2710 
2711     FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg);
2712     FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg);
2713     FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg);
2714     FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg);
2715 
2716     __ fnmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd);
2717 %}
2718 
2719 
2720 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2721     MacroAssembler _masm(&cbuf);
2722 
2723     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2724     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2725 
2726     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2727 %}
2728 
2729 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2730     MacroAssembler _masm(&cbuf);
2731 
2732     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2733     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2734 
2735     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2736 %}
2737 
2738 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2739     MacroAssembler _masm(&cbuf);


7643 //  Sqrt float double precision
7644 instruct sqrtF_reg_reg(regF dst, regF src) %{
7645   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7646 
7647   size(4);
7648   format %{ "FSQRTS $src,$dst" %}
7649   ins_encode(fsqrts(dst, src));
7650   ins_pipe(fdivF_reg_reg);
7651 %}
7652 
7653 //  Sqrt float double precision
7654 instruct sqrtD_reg_reg(regD dst, regD src) %{
7655   match(Set dst (SqrtD src));
7656 
7657   size(4);
7658   format %{ "FSQRTD $src,$dst" %}
7659   ins_encode(fsqrtd(dst, src));
7660   ins_pipe(fdivD_reg_reg);
7661 %}
7662 
7663 // Single/Double precision fused floating-point multiply-add (d = a * b + c).
7664 instruct fmaF_regx4(regF dst, regF a, regF b, regF c) %{
7665   predicate(UseFMA);
7666   match(Set dst (FmaF c (Binary a b)));
7667   format %{ "fmadds $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7668   ins_encode(fmadds(dst, a, b, c));
7669   ins_pipe(fmaF_regx4);
7670 %}
7671 

7672 instruct fmaD_regx4(regD dst, regD a, regD b, regD c) %{
7673   predicate(UseFMA);
7674   match(Set dst (FmaD c (Binary a b)));
7675   format %{ "fmaddd $a,$b,$c,$dst\t# $dst = $a * $b + $c" %}
7676   ins_encode(fmaddd(dst, a, b, c));
7677   ins_pipe(fmaD_regx4);
7678 %}
7679 
7680 // Additional patterns matching complement versions that we can map directly to
7681 // variants of the fused multiply-add instructions.
7682 
7683 // Single/Double precision fused floating-point multiply-sub (d = a * b - c)
7684 instruct fmsubF_regx4(regF dst, regF a, regF b, regF c) %{
7685   predicate(UseFMA);
7686   match(Set dst (FmaF (NegF c) (Binary a b)));
7687   format %{ "fmsubs $a,$b,$c,$dst\t# $dst = $a * $b - $c" %}
7688   ins_encode(fmsubs(dst, a, b, c));
7689   ins_pipe(fmaF_regx4);
7690 %}
7691 
7692 instruct fmsubD_regx4(regD dst, regD a, regD b, regD c) %{
7693   predicate(UseFMA);
7694   match(Set dst (FmaD (NegD c) (Binary a b)));
7695   format %{ "fmsubd $a,$b,$c,$dst\t# $dst = $a * $b - $c" %}
7696   ins_encode(fmsubd(dst, a, b, c));
7697   ins_pipe(fmaD_regx4);
7698 %}
7699 
7700 // Single/Double precision fused floating-point neg. multiply-add,
7701 //      d = -1 * a * b - c = -(a * b + c)
7702 instruct fnmaddF_regx4(regF dst, regF a, regF b, regF c) %{
7703   predicate(UseFMA);
7704   match(Set dst (FmaF (NegF c) (Binary (NegF a) b)));
7705   match(Set dst (FmaF (NegF c) (Binary a (NegF b))));
7706   format %{ "fnmadds $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %}
7707   ins_encode(fnmadds(dst, a, b, c));
7708   ins_pipe(fmaF_regx4);
7709 %}
7710 
7711 instruct fnmaddD_regx4(regD dst, regD a, regD b, regD c) %{
7712   predicate(UseFMA);
7713   match(Set dst (FmaD (NegD c) (Binary (NegD a) b)));
7714   match(Set dst (FmaD (NegD c) (Binary a (NegD b))));
7715   format %{ "fnmaddd $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %}
7716   ins_encode(fnmaddd(dst, a, b, c));
7717   ins_pipe(fmaD_regx4);
7718 %}
7719 
7720 // Single/Double precision fused floating-point neg. multiply-sub,
7721 //      d = -1 * a * b + c = -(a * b - c)
7722 instruct fnmsubF_regx4(regF dst, regF a, regF b, regF c) %{
7723   predicate(UseFMA);
7724   match(Set dst (FmaF c (Binary (NegF a) b)));
7725   match(Set dst (FmaF c (Binary a (NegF b))));
7726   format %{ "fnmsubs $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %}
7727   ins_encode(fnmsubs(dst, a, b, c));
7728   ins_pipe(fmaF_regx4);
7729 %}
7730 
7731 instruct fnmsubD_regx4(regD dst, regD a, regD b, regD c) %{
7732   predicate(UseFMA);
7733   match(Set dst (FmaD c (Binary (NegD a) b)));
7734   match(Set dst (FmaD c (Binary a (NegD b))));
7735   format %{ "fnmsubd $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %}
7736   ins_encode(fnmsubd(dst, a, b, c));
7737   ins_pipe(fmaD_regx4);
7738 %}
7739 
7740 //----------Logical Instructions-----------------------------------------------
7741 // And Instructions
7742 // Register And
7743 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7744   match(Set dst (AndI src1 src2));
7745 
7746   size(4);
7747   format %{ "AND    $src1,$src2,$dst" %}
7748   opcode(Assembler::and_op3, Assembler::arith_op);
7749   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7750   ins_pipe(ialu_reg_reg);
7751 %}
7752 
7753 // Immediate And
7754 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7755   match(Set dst (AndI src1 src2));
7756 
7757   size(4);
7758   format %{ "AND    $src1,$src2,$dst" %}


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