1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2018, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc_interface/collectedHeap.inline.hpp"
  30 #include "interpreter/interpreter.hpp"
  31 #include "memory/cardTableModRefBS.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "prims/methodHandles.hpp"
  34 #include "runtime/biasedLocking.hpp"
  35 #include "runtime/interfaceSupport.hpp"
  36 #include "runtime/objectMonitor.hpp"
  37 #include "runtime/os.hpp"
  38 #include "runtime/sharedRuntime.hpp"
  39 #include "runtime/stubRoutines.hpp"
  40 #include "utilities/macros.hpp"
  41 #if INCLUDE_ALL_GCS
  42 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
  43 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
  44 #include "gc_implementation/g1/heapRegion.hpp"
  45 #endif // INCLUDE_ALL_GCS
  46 
  47 #ifdef PRODUCT
  48 #define BLOCK_COMMENT(str) // nothing
  49 #else
  50 #define BLOCK_COMMENT(str) block_comment(str)
  51 #endif
  52 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  53 
  54 #ifdef ASSERT
  55 // On RISC, there's no benefit to verifying instruction boundaries.
  56 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
  57 #endif
  58 
  59 void MacroAssembler::ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop) {
  60   assert(Assembler::is_simm(si31, 31) && si31 >= 0, "si31 out of range");
  61   if (Assembler::is_simm(si31, 16)) {
  62     ld(d, si31, a);
  63     if (emit_filler_nop) nop();
  64   } else {
  65     const int hi = MacroAssembler::largeoffset_si16_si16_hi(si31);
  66     const int lo = MacroAssembler::largeoffset_si16_si16_lo(si31);
  67     addis(d, a, hi);
  68     ld(d, lo, d);
  69   }
  70 }
  71 
  72 void MacroAssembler::ld_largeoffset(Register d, int si31, Register a, int emit_filler_nop) {
  73   assert_different_registers(d, a);
  74   ld_largeoffset_unchecked(d, si31, a, emit_filler_nop);
  75 }
  76 
  77 void MacroAssembler::load_sized_value(Register dst, RegisterOrConstant offs, Register base,
  78                                       size_t size_in_bytes, bool is_signed) {
  79   switch (size_in_bytes) {
  80   case  8:              ld(dst, offs, base);                         break;
  81   case  4:  is_signed ? lwa(dst, offs, base) : lwz(dst, offs, base); break;
  82   case  2:  is_signed ? lha(dst, offs, base) : lhz(dst, offs, base); break;
  83   case  1:  lbz(dst, offs, base); if (is_signed) extsb(dst, dst);    break; // lba doesn't exist :(
  84   default:  ShouldNotReachHere();
  85   }
  86 }
  87 
  88 void MacroAssembler::store_sized_value(Register dst, RegisterOrConstant offs, Register base,
  89                                        size_t size_in_bytes) {
  90   switch (size_in_bytes) {
  91   case  8:  std(dst, offs, base); break;
  92   case  4:  stw(dst, offs, base); break;
  93   case  2:  sth(dst, offs, base); break;
  94   case  1:  stb(dst, offs, base); break;
  95   default:  ShouldNotReachHere();
  96   }
  97 }
  98 
  99 void MacroAssembler::align(int modulus, int max, int rem) {
 100   int padding = (rem + modulus - (offset() % modulus)) % modulus;
 101   if (padding > max) return;
 102   for (int c = (padding >> 2); c > 0; --c) { nop(); }
 103 }
 104 
 105 // Issue instructions that calculate given TOC from global TOC.
 106 void MacroAssembler::calculate_address_from_global_toc(Register dst, address addr, bool hi16, bool lo16,
 107                                                        bool add_relocation, bool emit_dummy_addr) {
 108   int offset = -1;
 109   if (emit_dummy_addr) {
 110     offset = -128; // dummy address
 111   } else if (addr != (address)(intptr_t)-1) {
 112     offset = MacroAssembler::offset_to_global_toc(addr);
 113   }
 114 
 115   if (hi16) {
 116     addis(dst, R29, MacroAssembler::largeoffset_si16_si16_hi(offset));
 117   }
 118   if (lo16) {
 119     if (add_relocation) {
 120       // Relocate at the addi to avoid confusion with a load from the method's TOC.
 121       relocate(internal_word_Relocation::spec(addr));
 122     }
 123     addi(dst, dst, MacroAssembler::largeoffset_si16_si16_lo(offset));
 124   }
 125 }
 126 
 127 int MacroAssembler::patch_calculate_address_from_global_toc_at(address a, address bound, address addr) {
 128   const int offset = MacroAssembler::offset_to_global_toc(addr);
 129 
 130   const address inst2_addr = a;
 131   const int inst2 = *(int *)inst2_addr;
 132 
 133   // The relocation points to the second instruction, the addi,
 134   // and the addi reads and writes the same register dst.
 135   const int dst = inv_rt_field(inst2);
 136   assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
 137 
 138   // Now, find the preceding addis which writes to dst.
 139   int inst1 = 0;
 140   address inst1_addr = inst2_addr - BytesPerInstWord;
 141   while (inst1_addr >= bound) {
 142     inst1 = *(int *) inst1_addr;
 143     if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
 144       // Stop, found the addis which writes dst.
 145       break;
 146     }
 147     inst1_addr -= BytesPerInstWord;
 148   }
 149 
 150   assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
 151   set_imm((int *)inst1_addr, MacroAssembler::largeoffset_si16_si16_hi(offset));
 152   set_imm((int *)inst2_addr, MacroAssembler::largeoffset_si16_si16_lo(offset));
 153   return (int)((intptr_t)addr - (intptr_t)inst1_addr);
 154 }
 155 
 156 address MacroAssembler::get_address_of_calculate_address_from_global_toc_at(address a, address bound) {
 157   const address inst2_addr = a;
 158   const int inst2 = *(int *)inst2_addr;
 159 
 160   // The relocation points to the second instruction, the addi,
 161   // and the addi reads and writes the same register dst.
 162   const int dst = inv_rt_field(inst2);
 163   assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
 164 
 165   // Now, find the preceding addis which writes to dst.
 166   int inst1 = 0;
 167   address inst1_addr = inst2_addr - BytesPerInstWord;
 168   while (inst1_addr >= bound) {
 169     inst1 = *(int *) inst1_addr;
 170     if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
 171       // stop, found the addis which writes dst
 172       break;
 173     }
 174     inst1_addr -= BytesPerInstWord;
 175   }
 176 
 177   assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
 178 
 179   int offset = (get_imm(inst1_addr, 0) << 16) + get_imm(inst2_addr, 0);
 180   // -1 is a special case
 181   if (offset == -1) {
 182     return (address)(intptr_t)-1;
 183   } else {
 184     return global_toc() + offset;
 185   }
 186 }
 187 
 188 #ifdef _LP64
 189 // Patch compressed oops or klass constants.
 190 // Assembler sequence is
 191 // 1) compressed oops:
 192 //    lis  rx = const.hi
 193 //    ori rx = rx | const.lo
 194 // 2) compressed klass:
 195 //    lis  rx = const.hi
 196 //    clrldi rx = rx & 0xFFFFffff // clearMS32b, optional
 197 //    ori rx = rx | const.lo
 198 // Clrldi will be passed by.
 199 int MacroAssembler::patch_set_narrow_oop(address a, address bound, narrowOop data) {
 200   assert(UseCompressedOops, "Should only patch compressed oops");
 201 
 202   const address inst2_addr = a;
 203   const int inst2 = *(int *)inst2_addr;
 204 
 205   // The relocation points to the second instruction, the ori,
 206   // and the ori reads and writes the same register dst.
 207   const int dst = inv_rta_field(inst2);
 208   assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
 209   // Now, find the preceding addis which writes to dst.
 210   int inst1 = 0;
 211   address inst1_addr = inst2_addr - BytesPerInstWord;
 212   bool inst1_found = false;
 213   while (inst1_addr >= bound) {
 214     inst1 = *(int *)inst1_addr;
 215     if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break; }
 216     inst1_addr -= BytesPerInstWord;
 217   }
 218   assert(inst1_found, "inst is not lis");
 219 
 220   int xc = (data >> 16) & 0xffff;
 221   int xd = (data >>  0) & 0xffff;
 222 
 223   set_imm((int *)inst1_addr, (short)(xc)); // see enc_load_con_narrow_hi/_lo
 224   set_imm((int *)inst2_addr,        (xd)); // unsigned int
 225   return (int)((intptr_t)inst2_addr - (intptr_t)inst1_addr);
 226 }
 227 
 228 // Get compressed oop or klass constant.
 229 narrowOop MacroAssembler::get_narrow_oop(address a, address bound) {
 230   assert(UseCompressedOops, "Should only patch compressed oops");
 231 
 232   const address inst2_addr = a;
 233   const int inst2 = *(int *)inst2_addr;
 234 
 235   // The relocation points to the second instruction, the ori,
 236   // and the ori reads and writes the same register dst.
 237   const int dst = inv_rta_field(inst2);
 238   assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
 239   // Now, find the preceding lis which writes to dst.
 240   int inst1 = 0;
 241   address inst1_addr = inst2_addr - BytesPerInstWord;
 242   bool inst1_found = false;
 243 
 244   while (inst1_addr >= bound) {
 245     inst1 = *(int *) inst1_addr;
 246     if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break;}
 247     inst1_addr -= BytesPerInstWord;
 248   }
 249   assert(inst1_found, "inst is not lis");
 250 
 251   uint xl = ((unsigned int) (get_imm(inst2_addr, 0) & 0xffff));
 252   uint xh = (((get_imm(inst1_addr, 0)) & 0xffff) << 16);
 253 
 254   return (int) (xl | xh);
 255 }
 256 #endif // _LP64
 257 
 258 void MacroAssembler::load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc) {
 259   int toc_offset = 0;
 260   // Use RelocationHolder::none for the constant pool entry, otherwise
 261   // we will end up with a failing NativeCall::verify(x) where x is
 262   // the address of the constant pool entry.
 263   // FIXME: We should insert relocation information for oops at the constant
 264   // pool entries instead of inserting it at the loads; patching of a constant
 265   // pool entry should be less expensive.
 266   address oop_address = address_constant((address)a.value(), RelocationHolder::none);
 267   // Relocate at the pc of the load.
 268   relocate(a.rspec());
 269   toc_offset = (int)(oop_address - code()->consts()->start());
 270   ld_largeoffset_unchecked(dst, toc_offset, toc, true);
 271 }
 272 
 273 bool MacroAssembler::is_load_const_from_method_toc_at(address a) {
 274   const address inst1_addr = a;
 275   const int inst1 = *(int *)inst1_addr;
 276 
 277    // The relocation points to the ld or the addis.
 278    return (is_ld(inst1)) ||
 279           (is_addis(inst1) && inv_ra_field(inst1) != 0);
 280 }
 281 
 282 int MacroAssembler::get_offset_of_load_const_from_method_toc_at(address a) {
 283   assert(is_load_const_from_method_toc_at(a), "must be load_const_from_method_toc");
 284 
 285   const address inst1_addr = a;
 286   const int inst1 = *(int *)inst1_addr;
 287 
 288   if (is_ld(inst1)) {
 289     return inv_d1_field(inst1);
 290   } else if (is_addis(inst1)) {
 291     const int dst = inv_rt_field(inst1);
 292 
 293     // Now, find the succeeding ld which reads and writes to dst.
 294     address inst2_addr = inst1_addr + BytesPerInstWord;
 295     int inst2 = 0;
 296     while (true) {
 297       inst2 = *(int *) inst2_addr;
 298       if (is_ld(inst2) && inv_ra_field(inst2) == dst && inv_rt_field(inst2) == dst) {
 299         // Stop, found the ld which reads and writes dst.
 300         break;
 301       }
 302       inst2_addr += BytesPerInstWord;
 303     }
 304     return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);
 305   }
 306   ShouldNotReachHere();
 307   return 0;
 308 }
 309 
 310 // Get the constant from a `load_const' sequence.
 311 long MacroAssembler::get_const(address a) {
 312   assert(is_load_const_at(a), "not a load of a constant");
 313   const int *p = (const int*) a;
 314   unsigned long x = (((unsigned long) (get_imm(a,0) & 0xffff)) << 48);
 315   if (is_ori(*(p+1))) {
 316     x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 32);
 317     x |= (((unsigned long) (get_imm(a,3) & 0xffff)) << 16);
 318     x |= (((unsigned long) (get_imm(a,4) & 0xffff)));
 319   } else if (is_lis(*(p+1))) {
 320     x |= (((unsigned long) (get_imm(a,2) & 0xffff)) << 32);
 321     x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 16);
 322     x |= (((unsigned long) (get_imm(a,3) & 0xffff)));
 323   } else {
 324     ShouldNotReachHere();
 325     return (long) 0;
 326   }
 327   return (long) x;
 328 }
 329 
 330 // Patch the 64 bit constant of a `load_const' sequence. This is a low
 331 // level procedure. It neither flushes the instruction cache nor is it
 332 // mt safe.
 333 void MacroAssembler::patch_const(address a, long x) {
 334   assert(is_load_const_at(a), "not a load of a constant");
 335   int *p = (int*) a;
 336   if (is_ori(*(p+1))) {
 337     set_imm(0 + p, (x >> 48) & 0xffff);
 338     set_imm(1 + p, (x >> 32) & 0xffff);
 339     set_imm(3 + p, (x >> 16) & 0xffff);
 340     set_imm(4 + p, x & 0xffff);
 341   } else if (is_lis(*(p+1))) {
 342     set_imm(0 + p, (x >> 48) & 0xffff);
 343     set_imm(2 + p, (x >> 32) & 0xffff);
 344     set_imm(1 + p, (x >> 16) & 0xffff);
 345     set_imm(3 + p, x & 0xffff);
 346   } else {
 347     ShouldNotReachHere();
 348   }
 349 }
 350 
 351 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
 352   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
 353   int index = oop_recorder()->allocate_metadata_index(obj);
 354   RelocationHolder rspec = metadata_Relocation::spec(index);
 355   return AddressLiteral((address)obj, rspec);
 356 }
 357 
 358 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
 359   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
 360   int index = oop_recorder()->find_index(obj);
 361   RelocationHolder rspec = metadata_Relocation::spec(index);
 362   return AddressLiteral((address)obj, rspec);
 363 }
 364 
 365 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
 366   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
 367   int oop_index = oop_recorder()->allocate_oop_index(obj);
 368   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
 369 }
 370 
 371 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
 372   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
 373   int oop_index = oop_recorder()->find_index(obj);
 374   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
 375 }
 376 
 377 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
 378                                                       Register tmp, int offset) {
 379   intptr_t value = *delayed_value_addr;
 380   if (value != 0) {
 381     return RegisterOrConstant(value + offset);
 382   }
 383 
 384   // Load indirectly to solve generation ordering problem.
 385   // static address, no relocation
 386   int simm16_offset = load_const_optimized(tmp, delayed_value_addr, noreg, true);
 387   ld(tmp, simm16_offset, tmp); // must be aligned ((xa & 3) == 0)
 388 
 389   if (offset != 0) {
 390     addi(tmp, tmp, offset);
 391   }
 392 
 393   return RegisterOrConstant(tmp);
 394 }
 395 
 396 #ifndef PRODUCT
 397 void MacroAssembler::pd_print_patched_instruction(address branch) {
 398   Unimplemented(); // TODO: PPC port
 399 }
 400 #endif // ndef PRODUCT
 401 
 402 // Conditional far branch for destinations encodable in 24+2 bits.
 403 void MacroAssembler::bc_far(int boint, int biint, Label& dest, int optimize) {
 404 
 405   // If requested by flag optimize, relocate the bc_far as a
 406   // runtime_call and prepare for optimizing it when the code gets
 407   // relocated.
 408   if (optimize == bc_far_optimize_on_relocate) {
 409     relocate(relocInfo::runtime_call_type);
 410   }
 411 
 412   // variant 2:
 413   //
 414   //    b!cxx SKIP
 415   //    bxx   DEST
 416   //  SKIP:
 417   //
 418 
 419   const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
 420                                                 opposite_bcond(inv_boint_bcond(boint)));
 421 
 422   // We emit two branches.
 423   // First, a conditional branch which jumps around the far branch.
 424   const address not_taken_pc = pc() + 2 * BytesPerInstWord;
 425   const address bc_pc        = pc();
 426   bc(opposite_boint, biint, not_taken_pc);
 427 
 428   const int bc_instr = *(int*)bc_pc;
 429   assert(not_taken_pc == (address)inv_bd_field(bc_instr, (intptr_t)bc_pc), "postcondition");
 430   assert(opposite_boint == inv_bo_field(bc_instr), "postcondition");
 431   assert(boint == add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(bc_instr))),
 432                                      opposite_bcond(inv_boint_bcond(inv_bo_field(bc_instr)))),
 433          "postcondition");
 434   assert(biint == inv_bi_field(bc_instr), "postcondition");
 435 
 436   // Second, an unconditional far branch which jumps to dest.
 437   // Note: target(dest) remembers the current pc (see CodeSection::target)
 438   //       and returns the current pc if the label is not bound yet; when
 439   //       the label gets bound, the unconditional far branch will be patched.
 440   const address target_pc = target(dest);
 441   const address b_pc  = pc();
 442   b(target_pc);
 443 
 444   assert(not_taken_pc == pc(),                     "postcondition");
 445   assert(dest.is_bound() || target_pc == b_pc, "postcondition");
 446 }
 447 
 448 bool MacroAssembler::is_bc_far_at(address instruction_addr) {
 449   return is_bc_far_variant1_at(instruction_addr) ||
 450          is_bc_far_variant2_at(instruction_addr) ||
 451          is_bc_far_variant3_at(instruction_addr);
 452 }
 453 
 454 address MacroAssembler::get_dest_of_bc_far_at(address instruction_addr) {
 455   if (is_bc_far_variant1_at(instruction_addr)) {
 456     const address instruction_1_addr = instruction_addr;
 457     const int instruction_1 = *(int*)instruction_1_addr;
 458     return (address)inv_bd_field(instruction_1, (intptr_t)instruction_1_addr);
 459   } else if (is_bc_far_variant2_at(instruction_addr)) {
 460     const address instruction_2_addr = instruction_addr + 4;
 461     return bxx_destination(instruction_2_addr);
 462   } else if (is_bc_far_variant3_at(instruction_addr)) {
 463     return instruction_addr + 8;
 464   }
 465   // variant 4 ???
 466   ShouldNotReachHere();
 467   return NULL;
 468 }
 469 void MacroAssembler::set_dest_of_bc_far_at(address instruction_addr, address dest) {
 470 
 471   if (is_bc_far_variant3_at(instruction_addr)) {
 472     // variant 3, far cond branch to the next instruction, already patched to nops:
 473     //
 474     //    nop
 475     //    endgroup
 476     //  SKIP/DEST:
 477     //
 478     return;
 479   }
 480 
 481   // first, extract boint and biint from the current branch
 482   int boint = 0;
 483   int biint = 0;
 484 
 485   ResourceMark rm;
 486   const int code_size = 2 * BytesPerInstWord;
 487   CodeBuffer buf(instruction_addr, code_size);
 488   MacroAssembler masm(&buf);
 489   if (is_bc_far_variant2_at(instruction_addr) && dest == instruction_addr + 8) {
 490     // Far branch to next instruction: Optimize it by patching nops (produce variant 3).
 491     masm.nop();
 492     masm.endgroup();
 493   } else {
 494     if (is_bc_far_variant1_at(instruction_addr)) {
 495       // variant 1, the 1st instruction contains the destination address:
 496       //
 497       //    bcxx  DEST
 498       //    endgroup
 499       //
 500       const int instruction_1 = *(int*)(instruction_addr);
 501       boint = inv_bo_field(instruction_1);
 502       biint = inv_bi_field(instruction_1);
 503     } else if (is_bc_far_variant2_at(instruction_addr)) {
 504       // variant 2, the 2nd instruction contains the destination address:
 505       //
 506       //    b!cxx SKIP
 507       //    bxx   DEST
 508       //  SKIP:
 509       //
 510       const int instruction_1 = *(int*)(instruction_addr);
 511       boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(instruction_1))),
 512           opposite_bcond(inv_boint_bcond(inv_bo_field(instruction_1))));
 513       biint = inv_bi_field(instruction_1);
 514     } else {
 515       // variant 4???
 516       ShouldNotReachHere();
 517     }
 518 
 519     // second, set the new branch destination and optimize the code
 520     if (dest != instruction_addr + 4 && // the bc_far is still unbound!
 521         masm.is_within_range_of_bcxx(dest, instruction_addr)) {
 522       // variant 1:
 523       //
 524       //    bcxx  DEST
 525       //    endgroup
 526       //
 527       masm.bc(boint, biint, dest);
 528       masm.endgroup();
 529     } else {
 530       // variant 2:
 531       //
 532       //    b!cxx SKIP
 533       //    bxx   DEST
 534       //  SKIP:
 535       //
 536       const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
 537                                                     opposite_bcond(inv_boint_bcond(boint)));
 538       const address not_taken_pc = masm.pc() + 2 * BytesPerInstWord;
 539       masm.bc(opposite_boint, biint, not_taken_pc);
 540       masm.b(dest);
 541     }
 542   }
 543   ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
 544 }
 545 
 546 // Emit a NOT mt-safe patchable 64 bit absolute call/jump.
 547 void MacroAssembler::bxx64_patchable(address dest, relocInfo::relocType rt, bool link) {
 548   // get current pc
 549   uint64_t start_pc = (uint64_t) pc();
 550 
 551   const address pc_of_bl = (address) (start_pc + (6*BytesPerInstWord)); // bl is last
 552   const address pc_of_b  = (address) (start_pc + (0*BytesPerInstWord)); // b is first
 553 
 554   // relocate here
 555   if (rt != relocInfo::none) {
 556     relocate(rt);
 557   }
 558 
 559   if ( ReoptimizeCallSequences &&
 560        (( link && is_within_range_of_b(dest, pc_of_bl)) ||
 561         (!link && is_within_range_of_b(dest, pc_of_b)))) {
 562     // variant 2:
 563     // Emit an optimized, pc-relative call/jump.
 564 
 565     if (link) {
 566       // some padding
 567       nop();
 568       nop();
 569       nop();
 570       nop();
 571       nop();
 572       nop();
 573 
 574       // do the call
 575       assert(pc() == pc_of_bl, "just checking");
 576       bl(dest, relocInfo::none);
 577     } else {
 578       // do the jump
 579       assert(pc() == pc_of_b, "just checking");
 580       b(dest, relocInfo::none);
 581 
 582       // some padding
 583       nop();
 584       nop();
 585       nop();
 586       nop();
 587       nop();
 588       nop();
 589     }
 590 
 591     // Assert that we can identify the emitted call/jump.
 592     assert(is_bxx64_patchable_variant2_at((address)start_pc, link),
 593            "can't identify emitted call");
 594   } else {
 595     // variant 1:
 596     mr(R0, R11);  // spill R11 -> R0.
 597 
 598     // Load the destination address into CTR,
 599     // calculate destination relative to global toc.
 600     calculate_address_from_global_toc(R11, dest, true, true, false);
 601 
 602     mtctr(R11);
 603     mr(R11, R0);  // spill R11 <- R0.
 604     nop();
 605 
 606     // do the call/jump
 607     if (link) {
 608       bctrl();
 609     } else{
 610       bctr();
 611     }
 612     // Assert that we can identify the emitted call/jump.
 613     assert(is_bxx64_patchable_variant1b_at((address)start_pc, link),
 614            "can't identify emitted call");
 615   }
 616 
 617   // Assert that we can identify the emitted call/jump.
 618   assert(is_bxx64_patchable_at((address)start_pc, link),
 619          "can't identify emitted call");
 620   assert(get_dest_of_bxx64_patchable_at((address)start_pc, link) == dest,
 621          "wrong encoding of dest address");
 622 }
 623 
 624 // Identify a bxx64_patchable instruction.
 625 bool MacroAssembler::is_bxx64_patchable_at(address instruction_addr, bool link) {
 626   return is_bxx64_patchable_variant1b_at(instruction_addr, link)
 627     //|| is_bxx64_patchable_variant1_at(instruction_addr, link)
 628       || is_bxx64_patchable_variant2_at(instruction_addr, link);
 629 }
 630 
 631 // Does the call64_patchable instruction use a pc-relative encoding of
 632 // the call destination?
 633 bool MacroAssembler::is_bxx64_patchable_pcrelative_at(address instruction_addr, bool link) {
 634   // variant 2 is pc-relative
 635   return is_bxx64_patchable_variant2_at(instruction_addr, link);
 636 }
 637 
 638 // Identify variant 1.
 639 bool MacroAssembler::is_bxx64_patchable_variant1_at(address instruction_addr, bool link) {
 640   unsigned int* instr = (unsigned int*) instruction_addr;
 641   return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
 642       && is_mtctr(instr[5]) // mtctr
 643     && is_load_const_at(instruction_addr);
 644 }
 645 
 646 // Identify variant 1b: load destination relative to global toc.
 647 bool MacroAssembler::is_bxx64_patchable_variant1b_at(address instruction_addr, bool link) {
 648   unsigned int* instr = (unsigned int*) instruction_addr;
 649   return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
 650     && is_mtctr(instr[3]) // mtctr
 651     && is_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord, instruction_addr);
 652 }
 653 
 654 // Identify variant 2.
 655 bool MacroAssembler::is_bxx64_patchable_variant2_at(address instruction_addr, bool link) {
 656   unsigned int* instr = (unsigned int*) instruction_addr;
 657   if (link) {
 658     return is_bl (instr[6])  // bl dest is last
 659       && is_nop(instr[0])  // nop
 660       && is_nop(instr[1])  // nop
 661       && is_nop(instr[2])  // nop
 662       && is_nop(instr[3])  // nop
 663       && is_nop(instr[4])  // nop
 664       && is_nop(instr[5]); // nop
 665   } else {
 666     return is_b  (instr[0])  // b  dest is first
 667       && is_nop(instr[1])  // nop
 668       && is_nop(instr[2])  // nop
 669       && is_nop(instr[3])  // nop
 670       && is_nop(instr[4])  // nop
 671       && is_nop(instr[5])  // nop
 672       && is_nop(instr[6]); // nop
 673   }
 674 }
 675 
 676 // Set dest address of a bxx64_patchable instruction.
 677 void MacroAssembler::set_dest_of_bxx64_patchable_at(address instruction_addr, address dest, bool link) {
 678   ResourceMark rm;
 679   int code_size = MacroAssembler::bxx64_patchable_size;
 680   CodeBuffer buf(instruction_addr, code_size);
 681   MacroAssembler masm(&buf);
 682   masm.bxx64_patchable(dest, relocInfo::none, link);
 683   ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
 684 }
 685 
 686 // Get dest address of a bxx64_patchable instruction.
 687 address MacroAssembler::get_dest_of_bxx64_patchable_at(address instruction_addr, bool link) {
 688   if (is_bxx64_patchable_variant1_at(instruction_addr, link)) {
 689     return (address) (unsigned long) get_const(instruction_addr);
 690   } else if (is_bxx64_patchable_variant2_at(instruction_addr, link)) {
 691     unsigned int* instr = (unsigned int*) instruction_addr;
 692     if (link) {
 693       const int instr_idx = 6; // bl is last
 694       int branchoffset = branch_destination(instr[instr_idx], 0);
 695       return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
 696     } else {
 697       const int instr_idx = 0; // b is first
 698       int branchoffset = branch_destination(instr[instr_idx], 0);
 699       return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
 700     }
 701   // Load dest relative to global toc.
 702   } else if (is_bxx64_patchable_variant1b_at(instruction_addr, link)) {
 703     return get_address_of_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord,
 704                                                                instruction_addr);
 705   } else {
 706     ShouldNotReachHere();
 707     return NULL;
 708   }
 709 }
 710 
 711 // Uses ordering which corresponds to ABI:
 712 //    _savegpr0_14:  std  r14,-144(r1)
 713 //    _savegpr0_15:  std  r15,-136(r1)
 714 //    _savegpr0_16:  std  r16,-128(r1)
 715 void MacroAssembler::save_nonvolatile_gprs(Register dst, int offset) {
 716   std(R14, offset, dst);   offset += 8;
 717   std(R15, offset, dst);   offset += 8;
 718   std(R16, offset, dst);   offset += 8;
 719   std(R17, offset, dst);   offset += 8;
 720   std(R18, offset, dst);   offset += 8;
 721   std(R19, offset, dst);   offset += 8;
 722   std(R20, offset, dst);   offset += 8;
 723   std(R21, offset, dst);   offset += 8;
 724   std(R22, offset, dst);   offset += 8;
 725   std(R23, offset, dst);   offset += 8;
 726   std(R24, offset, dst);   offset += 8;
 727   std(R25, offset, dst);   offset += 8;
 728   std(R26, offset, dst);   offset += 8;
 729   std(R27, offset, dst);   offset += 8;
 730   std(R28, offset, dst);   offset += 8;
 731   std(R29, offset, dst);   offset += 8;
 732   std(R30, offset, dst);   offset += 8;
 733   std(R31, offset, dst);   offset += 8;
 734 
 735   stfd(F14, offset, dst);   offset += 8;
 736   stfd(F15, offset, dst);   offset += 8;
 737   stfd(F16, offset, dst);   offset += 8;
 738   stfd(F17, offset, dst);   offset += 8;
 739   stfd(F18, offset, dst);   offset += 8;
 740   stfd(F19, offset, dst);   offset += 8;
 741   stfd(F20, offset, dst);   offset += 8;
 742   stfd(F21, offset, dst);   offset += 8;
 743   stfd(F22, offset, dst);   offset += 8;
 744   stfd(F23, offset, dst);   offset += 8;
 745   stfd(F24, offset, dst);   offset += 8;
 746   stfd(F25, offset, dst);   offset += 8;
 747   stfd(F26, offset, dst);   offset += 8;
 748   stfd(F27, offset, dst);   offset += 8;
 749   stfd(F28, offset, dst);   offset += 8;
 750   stfd(F29, offset, dst);   offset += 8;
 751   stfd(F30, offset, dst);   offset += 8;
 752   stfd(F31, offset, dst);
 753 }
 754 
 755 // Uses ordering which corresponds to ABI:
 756 //    _restgpr0_14:  ld   r14,-144(r1)
 757 //    _restgpr0_15:  ld   r15,-136(r1)
 758 //    _restgpr0_16:  ld   r16,-128(r1)
 759 void MacroAssembler::restore_nonvolatile_gprs(Register src, int offset) {
 760   ld(R14, offset, src);   offset += 8;
 761   ld(R15, offset, src);   offset += 8;
 762   ld(R16, offset, src);   offset += 8;
 763   ld(R17, offset, src);   offset += 8;
 764   ld(R18, offset, src);   offset += 8;
 765   ld(R19, offset, src);   offset += 8;
 766   ld(R20, offset, src);   offset += 8;
 767   ld(R21, offset, src);   offset += 8;
 768   ld(R22, offset, src);   offset += 8;
 769   ld(R23, offset, src);   offset += 8;
 770   ld(R24, offset, src);   offset += 8;
 771   ld(R25, offset, src);   offset += 8;
 772   ld(R26, offset, src);   offset += 8;
 773   ld(R27, offset, src);   offset += 8;
 774   ld(R28, offset, src);   offset += 8;
 775   ld(R29, offset, src);   offset += 8;
 776   ld(R30, offset, src);   offset += 8;
 777   ld(R31, offset, src);   offset += 8;
 778 
 779   // FP registers
 780   lfd(F14, offset, src);   offset += 8;
 781   lfd(F15, offset, src);   offset += 8;
 782   lfd(F16, offset, src);   offset += 8;
 783   lfd(F17, offset, src);   offset += 8;
 784   lfd(F18, offset, src);   offset += 8;
 785   lfd(F19, offset, src);   offset += 8;
 786   lfd(F20, offset, src);   offset += 8;
 787   lfd(F21, offset, src);   offset += 8;
 788   lfd(F22, offset, src);   offset += 8;
 789   lfd(F23, offset, src);   offset += 8;
 790   lfd(F24, offset, src);   offset += 8;
 791   lfd(F25, offset, src);   offset += 8;
 792   lfd(F26, offset, src);   offset += 8;
 793   lfd(F27, offset, src);   offset += 8;
 794   lfd(F28, offset, src);   offset += 8;
 795   lfd(F29, offset, src);   offset += 8;
 796   lfd(F30, offset, src);   offset += 8;
 797   lfd(F31, offset, src);
 798 }
 799 
 800 // For verify_oops.
 801 void MacroAssembler::save_volatile_gprs(Register dst, int offset) {
 802   std(R2,  offset, dst);   offset += 8;
 803   std(R3,  offset, dst);   offset += 8;
 804   std(R4,  offset, dst);   offset += 8;
 805   std(R5,  offset, dst);   offset += 8;
 806   std(R6,  offset, dst);   offset += 8;
 807   std(R7,  offset, dst);   offset += 8;
 808   std(R8,  offset, dst);   offset += 8;
 809   std(R9,  offset, dst);   offset += 8;
 810   std(R10, offset, dst);   offset += 8;
 811   std(R11, offset, dst);   offset += 8;
 812   std(R12, offset, dst);
 813 }
 814 
 815 // For verify_oops.
 816 void MacroAssembler::restore_volatile_gprs(Register src, int offset) {
 817   ld(R2,  offset, src);   offset += 8;
 818   ld(R3,  offset, src);   offset += 8;
 819   ld(R4,  offset, src);   offset += 8;
 820   ld(R5,  offset, src);   offset += 8;
 821   ld(R6,  offset, src);   offset += 8;
 822   ld(R7,  offset, src);   offset += 8;
 823   ld(R8,  offset, src);   offset += 8;
 824   ld(R9,  offset, src);   offset += 8;
 825   ld(R10, offset, src);   offset += 8;
 826   ld(R11, offset, src);   offset += 8;
 827   ld(R12, offset, src);
 828 }
 829 
 830 void MacroAssembler::save_LR_CR(Register tmp) {
 831   mfcr(tmp);
 832   std(tmp, _abi(cr), R1_SP);
 833   mflr(tmp);
 834   std(tmp, _abi(lr), R1_SP);
 835   // Tmp must contain lr on exit! (see return_addr and prolog in ppc64.ad)
 836 }
 837 
 838 void MacroAssembler::restore_LR_CR(Register tmp) {
 839   assert(tmp != R1_SP, "must be distinct");
 840   ld(tmp, _abi(lr), R1_SP);
 841   mtlr(tmp);
 842   ld(tmp, _abi(cr), R1_SP);
 843   mtcr(tmp);
 844 }
 845 
 846 address MacroAssembler::get_PC_trash_LR(Register result) {
 847   Label L;
 848   bl(L);
 849   bind(L);
 850   address lr_pc = pc();
 851   mflr(result);
 852   return lr_pc;
 853 }
 854 
 855 void MacroAssembler::resize_frame(Register offset, Register tmp) {
 856 #ifdef ASSERT
 857   assert_different_registers(offset, tmp, R1_SP);
 858   andi_(tmp, offset, frame::alignment_in_bytes-1);
 859   asm_assert_eq("resize_frame: unaligned", 0x204);
 860 #endif
 861 
 862   // tmp <- *(SP)
 863   ld(tmp, _abi(callers_sp), R1_SP);
 864   // addr <- SP + offset;
 865   // *(addr) <- tmp;
 866   // SP <- addr
 867   stdux(tmp, R1_SP, offset);
 868 }
 869 
 870 void MacroAssembler::resize_frame(int offset, Register tmp) {
 871   assert(is_simm(offset, 16), "too big an offset");
 872   assert_different_registers(tmp, R1_SP);
 873   assert((offset & (frame::alignment_in_bytes-1))==0, "resize_frame: unaligned");
 874   // tmp <- *(SP)
 875   ld(tmp, _abi(callers_sp), R1_SP);
 876   // addr <- SP + offset;
 877   // *(addr) <- tmp;
 878   // SP <- addr
 879   stdu(tmp, offset, R1_SP);
 880 }
 881 
 882 void MacroAssembler::resize_frame_absolute(Register addr, Register tmp1, Register tmp2) {
 883   // (addr == tmp1) || (addr == tmp2) is allowed here!
 884   assert(tmp1 != tmp2, "must be distinct");
 885 
 886   // compute offset w.r.t. current stack pointer
 887   // tmp_1 <- addr - SP (!)
 888   subf(tmp1, R1_SP, addr);
 889 
 890   // atomically update SP keeping back link.
 891   resize_frame(tmp1/* offset */, tmp2/* tmp */);
 892 }
 893 
 894 void MacroAssembler::push_frame(Register bytes, Register tmp) {
 895 #ifdef ASSERT
 896   assert(bytes != R0, "r0 not allowed here");
 897   andi_(R0, bytes, frame::alignment_in_bytes-1);
 898   asm_assert_eq("push_frame(Reg, Reg): unaligned", 0x203);
 899 #endif
 900   neg(tmp, bytes);
 901   stdux(R1_SP, R1_SP, tmp);
 902 }
 903 
 904 // Push a frame of size `bytes'.
 905 void MacroAssembler::push_frame(unsigned int bytes, Register tmp) {
 906   long offset = align_addr(bytes, frame::alignment_in_bytes);
 907   if (is_simm(-offset, 16)) {
 908     stdu(R1_SP, -offset, R1_SP);
 909   } else {
 910     load_const(tmp, -offset);
 911     stdux(R1_SP, R1_SP, tmp);
 912   }
 913 }
 914 
 915 // Push a frame of size `bytes' plus abi_reg_args on top.
 916 void MacroAssembler::push_frame_reg_args(unsigned int bytes, Register tmp) {
 917   push_frame(bytes + frame::abi_reg_args_size, tmp);
 918 }
 919 
 920 // Setup up a new C frame with a spill area for non-volatile GPRs and
 921 // additional space for local variables.
 922 void MacroAssembler::push_frame_reg_args_nonvolatiles(unsigned int bytes,
 923                                                       Register tmp) {
 924   push_frame(bytes + frame::abi_reg_args_size + frame::spill_nonvolatiles_size, tmp);
 925 }
 926 
 927 // Pop current C frame.
 928 void MacroAssembler::pop_frame() {
 929   ld(R1_SP, _abi(callers_sp), R1_SP);
 930 }
 931 
 932 #if defined(ABI_ELFv2)
 933 address MacroAssembler::branch_to(Register r_function_entry, bool and_link) {
 934   // TODO(asmundak): make sure the caller uses R12 as function descriptor
 935   // most of the times.
 936   if (R12 != r_function_entry) {
 937     mr(R12, r_function_entry);
 938   }
 939   mtctr(R12);
 940   // Do a call or a branch.
 941   if (and_link) {
 942     bctrl();
 943   } else {
 944     bctr();
 945   }
 946   _last_calls_return_pc = pc();
 947 
 948   return _last_calls_return_pc;
 949 }
 950 
 951 // Call a C function via a function descriptor and use full C
 952 // calling conventions. Updates and returns _last_calls_return_pc.
 953 address MacroAssembler::call_c(Register r_function_entry) {
 954   return branch_to(r_function_entry, /*and_link=*/true);
 955 }
 956 
 957 // For tail calls: only branch, don't link, so callee returns to caller of this function.
 958 address MacroAssembler::call_c_and_return_to_caller(Register r_function_entry) {
 959   return branch_to(r_function_entry, /*and_link=*/false);
 960 }
 961 
 962 address MacroAssembler::call_c(address function_entry, relocInfo::relocType rt) {
 963   load_const(R12, function_entry, R0);
 964   return branch_to(R12,  /*and_link=*/true);
 965 }
 966 
 967 #else
 968 // Generic version of a call to C function via a function descriptor
 969 // with variable support for C calling conventions (TOC, ENV, etc.).
 970 // Updates and returns _last_calls_return_pc.
 971 address MacroAssembler::branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
 972                                   bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee) {
 973   // we emit standard ptrgl glue code here
 974   assert((function_descriptor != R0), "function_descriptor cannot be R0");
 975 
 976   // retrieve necessary entries from the function descriptor
 977   ld(R0, in_bytes(FunctionDescriptor::entry_offset()), function_descriptor);
 978   mtctr(R0);
 979 
 980   if (load_toc_of_callee) {
 981     ld(R2_TOC, in_bytes(FunctionDescriptor::toc_offset()), function_descriptor);
 982   }
 983   if (load_env_of_callee) {
 984     ld(R11, in_bytes(FunctionDescriptor::env_offset()), function_descriptor);
 985   } else if (load_toc_of_callee) {
 986     li(R11, 0);
 987   }
 988 
 989   // do a call or a branch
 990   if (and_link) {
 991     bctrl();
 992   } else {
 993     bctr();
 994   }
 995   _last_calls_return_pc = pc();
 996 
 997   return _last_calls_return_pc;
 998 }
 999 
1000 // Call a C function via a function descriptor and use full C calling
1001 // conventions.
1002 // We don't use the TOC in generated code, so there is no need to save
1003 // and restore its value.
1004 address MacroAssembler::call_c(Register fd) {
1005   return branch_to(fd, /*and_link=*/true,
1006                        /*save toc=*/false,
1007                        /*restore toc=*/false,
1008                        /*load toc=*/true,
1009                        /*load env=*/true);
1010 }
1011 
1012 address MacroAssembler::call_c_and_return_to_caller(Register fd) {
1013   return branch_to(fd, /*and_link=*/false,
1014                        /*save toc=*/false,
1015                        /*restore toc=*/false,
1016                        /*load toc=*/true,
1017                        /*load env=*/true);
1018 }
1019 
1020 address MacroAssembler::call_c(const FunctionDescriptor* fd, relocInfo::relocType rt) {
1021   if (rt != relocInfo::none) {
1022     // this call needs to be relocatable
1023     if (!ReoptimizeCallSequences
1024         || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1025         || fd == NULL   // support code-size estimation
1026         || !fd->is_friend_function()
1027         || fd->entry() == NULL) {
1028       // it's not a friend function as defined by class FunctionDescriptor,
1029       // so do a full call-c here.
1030       load_const(R11, (address)fd, R0);
1031 
1032       bool has_env = (fd != NULL && fd->env() != NULL);
1033       return branch_to(R11, /*and_link=*/true,
1034                             /*save toc=*/false,
1035                             /*restore toc=*/false,
1036                             /*load toc=*/true,
1037                             /*load env=*/has_env);
1038     } else {
1039       // It's a friend function. Load the entry point and don't care about
1040       // toc and env. Use an optimizable call instruction, but ensure the
1041       // same code-size as in the case of a non-friend function.
1042       nop();
1043       nop();
1044       nop();
1045       bl64_patchable(fd->entry(), rt);
1046       _last_calls_return_pc = pc();
1047       return _last_calls_return_pc;
1048     }
1049   } else {
1050     // This call does not need to be relocatable, do more aggressive
1051     // optimizations.
1052     if (!ReoptimizeCallSequences
1053       || !fd->is_friend_function()) {
1054       // It's not a friend function as defined by class FunctionDescriptor,
1055       // so do a full call-c here.
1056       load_const(R11, (address)fd, R0);
1057       return branch_to(R11, /*and_link=*/true,
1058                             /*save toc=*/false,
1059                             /*restore toc=*/false,
1060                             /*load toc=*/true,
1061                             /*load env=*/true);
1062     } else {
1063       // it's a friend function, load the entry point and don't care about
1064       // toc and env.
1065       address dest = fd->entry();
1066       if (is_within_range_of_b(dest, pc())) {
1067         bl(dest);
1068       } else {
1069         bl64_patchable(dest, rt);
1070       }
1071       _last_calls_return_pc = pc();
1072       return _last_calls_return_pc;
1073     }
1074   }
1075 }
1076 
1077 // Call a C function.  All constants needed reside in TOC.
1078 //
1079 // Read the address to call from the TOC.
1080 // Read env from TOC, if fd specifies an env.
1081 // Read new TOC from TOC.
1082 address MacroAssembler::call_c_using_toc(const FunctionDescriptor* fd,
1083                                          relocInfo::relocType rt, Register toc) {
1084   if (!ReoptimizeCallSequences
1085     || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1086     || !fd->is_friend_function()) {
1087     // It's not a friend function as defined by class FunctionDescriptor,
1088     // so do a full call-c here.
1089     assert(fd->entry() != NULL, "function must be linked");
1090 
1091     AddressLiteral fd_entry(fd->entry());
1092     load_const_from_method_toc(R11, fd_entry, toc);
1093     mtctr(R11);
1094     if (fd->env() == NULL) {
1095       li(R11, 0);
1096       nop();
1097     } else {
1098       AddressLiteral fd_env(fd->env());
1099       load_const_from_method_toc(R11, fd_env, toc);
1100     }
1101     AddressLiteral fd_toc(fd->toc());
1102     load_toc_from_toc(R2_TOC, fd_toc, toc);
1103     // R2_TOC is killed.
1104     bctrl();
1105     _last_calls_return_pc = pc();
1106   } else {
1107     // It's a friend function, load the entry point and don't care about
1108     // toc and env. Use an optimizable call instruction, but ensure the
1109     // same code-size as in the case of a non-friend function.
1110     nop();
1111     bl64_patchable(fd->entry(), rt);
1112     _last_calls_return_pc = pc();
1113   }
1114   return _last_calls_return_pc;
1115 }
1116 #endif // ABI_ELFv2
1117 
1118 void MacroAssembler::call_VM_base(Register oop_result,
1119                                   Register last_java_sp,
1120                                   address  entry_point,
1121                                   bool     check_exceptions) {
1122   BLOCK_COMMENT("call_VM {");
1123   // Determine last_java_sp register.
1124   if (!last_java_sp->is_valid()) {
1125     last_java_sp = R1_SP;
1126   }
1127   set_top_ijava_frame_at_SP_as_last_Java_frame(last_java_sp, R11_scratch1);
1128 
1129   // ARG1 must hold thread address.
1130   mr(R3_ARG1, R16_thread);
1131 #if defined(ABI_ELFv2)
1132   address return_pc = call_c(entry_point, relocInfo::none);
1133 #else
1134   address return_pc = call_c((FunctionDescriptor*)entry_point, relocInfo::none);
1135 #endif
1136 
1137   reset_last_Java_frame();
1138 
1139   // Check for pending exceptions.
1140   if (check_exceptions) {
1141     // We don't check for exceptions here.
1142     ShouldNotReachHere();
1143   }
1144 
1145   // Get oop result if there is one and reset the value in the thread.
1146   if (oop_result->is_valid()) {
1147     get_vm_result(oop_result);
1148   }
1149 
1150   _last_calls_return_pc = return_pc;
1151   BLOCK_COMMENT("} call_VM");
1152 }
1153 
1154 void MacroAssembler::call_VM_leaf_base(address entry_point) {
1155   BLOCK_COMMENT("call_VM_leaf {");
1156 #if defined(ABI_ELFv2)
1157   call_c(entry_point, relocInfo::none);
1158 #else
1159   call_c(CAST_FROM_FN_PTR(FunctionDescriptor*, entry_point), relocInfo::none);
1160 #endif
1161   BLOCK_COMMENT("} call_VM_leaf");
1162 }
1163 
1164 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
1165   call_VM_base(oop_result, noreg, entry_point, check_exceptions);
1166 }
1167 
1168 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1,
1169                              bool check_exceptions) {
1170   // R3_ARG1 is reserved for the thread.
1171   mr_if_needed(R4_ARG2, arg_1);
1172   call_VM(oop_result, entry_point, check_exceptions);
1173 }
1174 
1175 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
1176                              bool check_exceptions) {
1177   // R3_ARG1 is reserved for the thread
1178   mr_if_needed(R4_ARG2, arg_1);
1179   assert(arg_2 != R4_ARG2, "smashed argument");
1180   mr_if_needed(R5_ARG3, arg_2);
1181   call_VM(oop_result, entry_point, check_exceptions);
1182 }
1183 
1184 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3,
1185                              bool check_exceptions) {
1186   // R3_ARG1 is reserved for the thread
1187   mr_if_needed(R4_ARG2, arg_1);
1188   assert(arg_2 != R4_ARG2, "smashed argument");
1189   mr_if_needed(R5_ARG3, arg_2);
1190   mr_if_needed(R6_ARG4, arg_3);
1191   call_VM(oop_result, entry_point, check_exceptions);
1192 }
1193 
1194 void MacroAssembler::call_VM_leaf(address entry_point) {
1195   call_VM_leaf_base(entry_point);
1196 }
1197 
1198 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
1199   mr_if_needed(R3_ARG1, arg_1);
1200   call_VM_leaf(entry_point);
1201 }
1202 
1203 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
1204   mr_if_needed(R3_ARG1, arg_1);
1205   assert(arg_2 != R3_ARG1, "smashed argument");
1206   mr_if_needed(R4_ARG2, arg_2);
1207   call_VM_leaf(entry_point);
1208 }
1209 
1210 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1211   mr_if_needed(R3_ARG1, arg_1);
1212   assert(arg_2 != R3_ARG1, "smashed argument");
1213   mr_if_needed(R4_ARG2, arg_2);
1214   assert(arg_3 != R3_ARG1 && arg_3 != R4_ARG2, "smashed argument");
1215   mr_if_needed(R5_ARG3, arg_3);
1216   call_VM_leaf(entry_point);
1217 }
1218 
1219 // Check whether instruction is a read access to the polling page
1220 // which was emitted by load_from_polling_page(..).
1221 bool MacroAssembler::is_load_from_polling_page(int instruction, void* ucontext,
1222                                                address* polling_address_ptr) {
1223   if (!is_ld(instruction))
1224     return false; // It's not a ld. Fail.
1225 
1226   int rt = inv_rt_field(instruction);
1227   int ra = inv_ra_field(instruction);
1228   int ds = inv_ds_field(instruction);
1229   if (!(ds == 0 && ra != 0 && rt == 0)) {
1230     return false; // It's not a ld(r0, X, ra). Fail.
1231   }
1232 
1233   if (!ucontext) {
1234     // Set polling address.
1235     if (polling_address_ptr != NULL) {
1236       *polling_address_ptr = NULL;
1237     }
1238     return true; // No ucontext given. Can't check value of ra. Assume true.
1239   }
1240 
1241 #ifdef LINUX
1242   // Ucontext given. Check that register ra contains the address of
1243   // the safepoing polling page.
1244   ucontext_t* uc = (ucontext_t*) ucontext;
1245   // Set polling address.
1246   address addr = (address)uc->uc_mcontext.regs->gpr[ra] + (ssize_t)ds;
1247   if (polling_address_ptr != NULL) {
1248     *polling_address_ptr = addr;
1249   }
1250   return os::is_poll_address(addr);
1251 #else
1252   // Not on Linux, ucontext must be NULL.
1253   ShouldNotReachHere();
1254   return false;
1255 #endif
1256 }
1257 
1258 bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
1259 #ifdef LINUX
1260   ucontext_t* uc = (ucontext_t*) ucontext;
1261 
1262   if (is_stwx(instruction) || is_stwux(instruction)) {
1263     int ra = inv_ra_field(instruction);
1264     int rb = inv_rb_field(instruction);
1265 
1266     // look up content of ra and rb in ucontext
1267     address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
1268     long rb_val=(long)uc->uc_mcontext.regs->gpr[rb];
1269     return os::is_memory_serialize_page(thread, ra_val+rb_val);
1270   } else if (is_stw(instruction) || is_stwu(instruction)) {
1271     int ra = inv_ra_field(instruction);
1272     int d1 = inv_d1_field(instruction);
1273 
1274     // look up content of ra in ucontext
1275     address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
1276     return os::is_memory_serialize_page(thread, ra_val+d1);
1277   } else {
1278     return false;
1279   }
1280 #else
1281   // workaround not needed on !LINUX :-)
1282   ShouldNotCallThis();
1283   return false;
1284 #endif
1285 }
1286 
1287 void MacroAssembler::bang_stack_with_offset(int offset) {
1288   // When increasing the stack, the old stack pointer will be written
1289   // to the new top of stack according to the PPC64 abi.
1290   // Therefore, stack banging is not necessary when increasing
1291   // the stack by <= os::vm_page_size() bytes.
1292   // When increasing the stack by a larger amount, this method is
1293   // called repeatedly to bang the intermediate pages.
1294 
1295   // Stack grows down, caller passes positive offset.
1296   assert(offset > 0, "must bang with positive offset");
1297 
1298   long stdoffset = -offset;
1299 
1300   if (is_simm(stdoffset, 16)) {
1301     // Signed 16 bit offset, a simple std is ok.
1302     if (UseLoadInstructionsForStackBangingPPC64) {
1303       ld(R0, (int)(signed short)stdoffset, R1_SP);
1304     } else {
1305       std(R0,(int)(signed short)stdoffset, R1_SP);
1306     }
1307   } else if (is_simm(stdoffset, 31)) {
1308     const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1309     const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1310 
1311     Register tmp = R11;
1312     addis(tmp, R1_SP, hi);
1313     if (UseLoadInstructionsForStackBangingPPC64) {
1314       ld(R0,  lo, tmp);
1315     } else {
1316       std(R0, lo, tmp);
1317     }
1318   } else {
1319     ShouldNotReachHere();
1320   }
1321 }
1322 
1323 // If instruction is a stack bang of the form
1324 //    std    R0,    x(Ry),       (see bang_stack_with_offset())
1325 //    stdu   R1_SP, x(R1_SP),    (see push_frame(), resize_frame())
1326 // or stdux  R1_SP, Rx, R1_SP    (see push_frame(), resize_frame())
1327 // return the banged address. Otherwise, return 0.
1328 address MacroAssembler::get_stack_bang_address(int instruction, void *ucontext) {
1329 #ifdef LINUX
1330   ucontext_t* uc = (ucontext_t*) ucontext;
1331   int rs = inv_rs_field(instruction);
1332   int ra = inv_ra_field(instruction);
1333   if (   (is_ld(instruction)   && rs == 0 &&  UseLoadInstructionsForStackBangingPPC64)
1334       || (is_std(instruction)  && rs == 0 && !UseLoadInstructionsForStackBangingPPC64)
1335       || (is_stdu(instruction) && rs == 1)) {
1336     int ds = inv_ds_field(instruction);
1337     // return banged address
1338     return ds+(address)uc->uc_mcontext.regs->gpr[ra];
1339   } else if (is_stdux(instruction) && rs == 1) {
1340     int rb = inv_rb_field(instruction);
1341     address sp = (address)uc->uc_mcontext.regs->gpr[1];
1342     long rb_val = (long)uc->uc_mcontext.regs->gpr[rb];
1343     return ra != 1 || rb_val >= 0 ? NULL         // not a stack bang
1344                                   : sp + rb_val; // banged address
1345   }
1346   return NULL; // not a stack bang
1347 #else
1348   // workaround not needed on !LINUX :-)
1349   ShouldNotCallThis();
1350   return NULL;
1351 #endif
1352 }
1353 
1354 // CmpxchgX sets condition register to cmpX(current, compare).
1355 void MacroAssembler::cmpxchgw(ConditionRegister flag, Register dest_current_value,
1356                               Register compare_value, Register exchange_value,
1357                               Register addr_base, int semantics, bool cmpxchgx_hint,
1358                               Register int_flag_success, bool contention_hint) {
1359   Label retry;
1360   Label failed;
1361   Label done;
1362 
1363   // Save one branch if result is returned via register and
1364   // result register is different from the other ones.
1365   bool use_result_reg    = (int_flag_success != noreg);
1366   bool preset_result_reg = (int_flag_success != dest_current_value && int_flag_success != compare_value &&
1367                             int_flag_success != exchange_value && int_flag_success != addr_base);
1368 
1369   // release/fence semantics
1370   if (semantics & MemBarRel) {
1371     release();
1372   }
1373 
1374   if (use_result_reg && preset_result_reg) {
1375     li(int_flag_success, 0); // preset (assume cas failed)
1376   }
1377 
1378   // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1379   if (contention_hint) { // Don't try to reserve if cmp fails.
1380     lwz(dest_current_value, 0, addr_base);
1381     cmpw(flag, dest_current_value, compare_value);
1382     bne(flag, failed);
1383   }
1384 
1385   // atomic emulation loop
1386   bind(retry);
1387 
1388   lwarx(dest_current_value, addr_base, cmpxchgx_hint);
1389   cmpw(flag, dest_current_value, compare_value);
1390   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1391     bne_predict_not_taken(flag, failed);
1392   } else {
1393     bne(                  flag, failed);
1394   }
1395   // branch to done  => (flag == ne), (dest_current_value != compare_value)
1396   // fall through    => (flag == eq), (dest_current_value == compare_value)
1397 
1398   stwcx_(exchange_value, addr_base);
1399   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1400     bne_predict_not_taken(CCR0, retry); // StXcx_ sets CCR0.
1401   } else {
1402     bne(                  CCR0, retry); // StXcx_ sets CCR0.
1403   }
1404   // fall through    => (flag == eq), (dest_current_value == compare_value), (swapped)
1405 
1406   // Result in register (must do this at the end because int_flag_success can be the
1407   // same register as one above).
1408   if (use_result_reg) {
1409     li(int_flag_success, 1);
1410   }
1411 
1412   if (semantics & MemBarFenceAfter) {
1413     fence();
1414   } else if (semantics & MemBarAcq) {
1415     isync();
1416   }
1417 
1418   if (use_result_reg && !preset_result_reg) {
1419     b(done);
1420   }
1421 
1422   bind(failed);
1423   if (use_result_reg && !preset_result_reg) {
1424     li(int_flag_success, 0);
1425   }
1426 
1427   bind(done);
1428   // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1429   // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1430 }
1431 
1432 // Preforms atomic compare exchange:
1433 //   if (compare_value == *addr_base)
1434 //     *addr_base = exchange_value
1435 //     int_flag_success = 1;
1436 //   else
1437 //     int_flag_success = 0;
1438 //
1439 // ConditionRegister flag       = cmp(compare_value, *addr_base)
1440 // Register dest_current_value  = *addr_base
1441 // Register compare_value       Used to compare with value in memory
1442 // Register exchange_value      Written to memory if compare_value == *addr_base
1443 // Register addr_base           The memory location to compareXChange
1444 // Register int_flag_success    Set to 1 if exchange_value was written to *addr_base
1445 //
1446 // To avoid the costly compare exchange the value is tested beforehand.
1447 // Several special cases exist to avoid that unnecessary information is generated.
1448 //
1449 void MacroAssembler::cmpxchgd(ConditionRegister flag,
1450                               Register dest_current_value, Register compare_value, Register exchange_value,
1451                               Register addr_base, int semantics, bool cmpxchgx_hint,
1452                               Register int_flag_success, Label* failed_ext, bool contention_hint) {
1453   Label retry;
1454   Label failed_int;
1455   Label& failed = (failed_ext != NULL) ? *failed_ext : failed_int;
1456   Label done;
1457 
1458   // Save one branch if result is returned via register and result register is different from the other ones.
1459   bool use_result_reg    = (int_flag_success!=noreg);
1460   bool preset_result_reg = (int_flag_success!=dest_current_value && int_flag_success!=compare_value &&
1461                             int_flag_success!=exchange_value && int_flag_success!=addr_base);
1462   assert(int_flag_success == noreg || failed_ext == NULL, "cannot have both");
1463 
1464   // release/fence semantics
1465   if (semantics & MemBarRel) {
1466     release();
1467   }
1468 
1469   if (use_result_reg && preset_result_reg) {
1470     li(int_flag_success, 0); // preset (assume cas failed)
1471   }
1472 
1473   // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1474   if (contention_hint) { // Don't try to reserve if cmp fails.
1475     ld(dest_current_value, 0, addr_base);
1476     cmpd(flag, dest_current_value, compare_value);
1477     bne(flag, failed);
1478   }
1479 
1480   // atomic emulation loop
1481   bind(retry);
1482 
1483   ldarx(dest_current_value, addr_base, cmpxchgx_hint);
1484   cmpd(flag, dest_current_value, compare_value);
1485   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1486     bne_predict_not_taken(flag, failed);
1487   } else {
1488     bne(                  flag, failed);
1489   }
1490 
1491   stdcx_(exchange_value, addr_base);
1492   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1493     bne_predict_not_taken(CCR0, retry); // stXcx_ sets CCR0
1494   } else {
1495     bne(                  CCR0, retry); // stXcx_ sets CCR0
1496   }
1497 
1498   // result in register (must do this at the end because int_flag_success can be the same register as one above)
1499   if (use_result_reg) {
1500     li(int_flag_success, 1);
1501   }
1502 
1503   // POWER6 doesn't need isync in CAS.
1504   // Always emit isync to be on the safe side.
1505   if (semantics & MemBarFenceAfter) {
1506     fence();
1507   } else if (semantics & MemBarAcq) {
1508     isync();
1509   }
1510 
1511   if (use_result_reg && !preset_result_reg) {
1512     b(done);
1513   }
1514 
1515   bind(failed_int);
1516   if (use_result_reg && !preset_result_reg) {
1517     li(int_flag_success, 0);
1518   }
1519 
1520   bind(done);
1521   // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1522   // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1523 }
1524 
1525 // Look up the method for a megamorphic invokeinterface call.
1526 // The target method is determined by <intf_klass, itable_index>.
1527 // The receiver klass is in recv_klass.
1528 // On success, the result will be in method_result, and execution falls through.
1529 // On failure, execution transfers to the given label.
1530 void MacroAssembler::lookup_interface_method(Register recv_klass,
1531                                              Register intf_klass,
1532                                              RegisterOrConstant itable_index,
1533                                              Register method_result,
1534                                              Register scan_temp,
1535                                              Register temp2,
1536                                              Label& L_no_such_interface,
1537                                              bool return_method) {
1538   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
1539 
1540   // Compute start of first itableOffsetEntry (which is at the end of the vtable).
1541   int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
1542   int itentry_off = itableMethodEntry::method_offset_in_bytes();
1543   int logMEsize   = exact_log2(itableMethodEntry::size() * wordSize);
1544   int scan_step   = itableOffsetEntry::size() * wordSize;
1545   int log_vte_size= exact_log2(vtableEntry::size() * wordSize);
1546 
1547   lwz(scan_temp, InstanceKlass::vtable_length_offset() * wordSize, recv_klass);
1548   // %%% We should store the aligned, prescaled offset in the klassoop.
1549   // Then the next several instructions would fold away.
1550 
1551   sldi(scan_temp, scan_temp, log_vte_size);
1552   addi(scan_temp, scan_temp, vtable_base);
1553   add(scan_temp, recv_klass, scan_temp);
1554 
1555   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1556   if (return_method) {
1557     if (itable_index.is_register()) {
1558       Register itable_offset = itable_index.as_register();
1559       sldi(method_result, itable_offset, logMEsize);
1560       if (itentry_off) { addi(method_result, method_result, itentry_off); }
1561       add(method_result, method_result, recv_klass);
1562     } else {
1563       long itable_offset = (long)itable_index.as_constant();
1564       // static address, no relocation
1565       load_const_optimized(temp2, (itable_offset << logMEsize) + itentry_off); // static address, no relocation
1566       add(method_result, temp2, recv_klass);
1567     }
1568   }
1569 
1570   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
1571   //   if (scan->interface() == intf) {
1572   //     result = (klass + scan->offset() + itable_index);
1573   //   }
1574   // }
1575   Label search, found_method;
1576 
1577   for (int peel = 1; peel >= 0; peel--) {
1578     // %%%% Could load both offset and interface in one ldx, if they were
1579     // in the opposite order. This would save a load.
1580     ld(temp2, itableOffsetEntry::interface_offset_in_bytes(), scan_temp);
1581 
1582     // Check that this entry is non-null. A null entry means that
1583     // the receiver class doesn't implement the interface, and wasn't the
1584     // same as when the caller was compiled.
1585     cmpd(CCR0, temp2, intf_klass);
1586 
1587     if (peel) {
1588       beq(CCR0, found_method);
1589     } else {
1590       bne(CCR0, search);
1591       // (invert the test to fall through to found_method...)
1592     }
1593 
1594     if (!peel) break;
1595 
1596     bind(search);
1597 
1598     cmpdi(CCR0, temp2, 0);
1599     beq(CCR0, L_no_such_interface);
1600     addi(scan_temp, scan_temp, scan_step);
1601   }
1602 
1603   bind(found_method);
1604 
1605   // Got a hit.
1606   if (return_method) {
1607     int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
1608     lwz(scan_temp, ito_offset, scan_temp);
1609     ldx(method_result, scan_temp, method_result);
1610   }
1611 }
1612 
1613 // virtual method calling
1614 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1615                                            RegisterOrConstant vtable_index,
1616                                            Register method_result) {
1617 
1618   assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
1619 
1620   const int base = InstanceKlass::vtable_start_offset() * wordSize;
1621   assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1622 
1623   if (vtable_index.is_register()) {
1624     sldi(vtable_index.as_register(), vtable_index.as_register(), LogBytesPerWord);
1625     add(recv_klass, vtable_index.as_register(), recv_klass);
1626   } else {
1627     addi(recv_klass, recv_klass, vtable_index.as_constant() << LogBytesPerWord);
1628   }
1629   ld(R19_method, base + vtableEntry::method_offset_in_bytes(), recv_klass);
1630 }
1631 
1632 /////////////////////////////////////////// subtype checking ////////////////////////////////////////////
1633 
1634 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1635                                                    Register super_klass,
1636                                                    Register temp1_reg,
1637                                                    Register temp2_reg,
1638                                                    Label& L_success,
1639                                                    Label& L_failure) {
1640 
1641   const Register check_cache_offset = temp1_reg;
1642   const Register cached_super       = temp2_reg;
1643 
1644   assert_different_registers(sub_klass, super_klass, check_cache_offset, cached_super);
1645 
1646   int sco_offset = in_bytes(Klass::super_check_offset_offset());
1647   int sc_offset  = in_bytes(Klass::secondary_super_cache_offset());
1648 
1649   // If the pointers are equal, we are done (e.g., String[] elements).
1650   // This self-check enables sharing of secondary supertype arrays among
1651   // non-primary types such as array-of-interface. Otherwise, each such
1652   // type would need its own customized SSA.
1653   // We move this check to the front of the fast path because many
1654   // type checks are in fact trivially successful in this manner,
1655   // so we get a nicely predicted branch right at the start of the check.
1656   cmpd(CCR0, sub_klass, super_klass);
1657   beq(CCR0, L_success);
1658 
1659   // Check the supertype display:
1660   lwz(check_cache_offset, sco_offset, super_klass);
1661   // The loaded value is the offset from KlassOopDesc.
1662 
1663   ldx(cached_super, check_cache_offset, sub_klass);
1664   cmpd(CCR0, cached_super, super_klass);
1665   beq(CCR0, L_success);
1666 
1667   // This check has worked decisively for primary supers.
1668   // Secondary supers are sought in the super_cache ('super_cache_addr').
1669   // (Secondary supers are interfaces and very deeply nested subtypes.)
1670   // This works in the same check above because of a tricky aliasing
1671   // between the super_cache and the primary super display elements.
1672   // (The 'super_check_addr' can address either, as the case requires.)
1673   // Note that the cache is updated below if it does not help us find
1674   // what we need immediately.
1675   // So if it was a primary super, we can just fail immediately.
1676   // Otherwise, it's the slow path for us (no success at this point).
1677 
1678   cmpwi(CCR0, check_cache_offset, sc_offset);
1679   bne(CCR0, L_failure);
1680   // bind(slow_path); // fallthru
1681 }
1682 
1683 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1684                                                    Register super_klass,
1685                                                    Register temp1_reg,
1686                                                    Register temp2_reg,
1687                                                    Label* L_success,
1688                                                    Register result_reg) {
1689   const Register array_ptr = temp1_reg; // current value from cache array
1690   const Register temp      = temp2_reg;
1691 
1692   assert_different_registers(sub_klass, super_klass, array_ptr, temp);
1693 
1694   int source_offset = in_bytes(Klass::secondary_supers_offset());
1695   int target_offset = in_bytes(Klass::secondary_super_cache_offset());
1696 
1697   int length_offset = Array<Klass*>::length_offset_in_bytes();
1698   int base_offset   = Array<Klass*>::base_offset_in_bytes();
1699 
1700   Label hit, loop, failure, fallthru;
1701 
1702   ld(array_ptr, source_offset, sub_klass);
1703 
1704   //assert(4 == arrayOopDesc::length_length_in_bytes(), "precondition violated.");
1705   lwz(temp, length_offset, array_ptr);
1706   cmpwi(CCR0, temp, 0);
1707   beq(CCR0, result_reg!=noreg ? failure : fallthru); // length 0
1708 
1709   mtctr(temp); // load ctr
1710 
1711   bind(loop);
1712   // Oops in table are NO MORE compressed.
1713   ld(temp, base_offset, array_ptr);
1714   cmpd(CCR0, temp, super_klass);
1715   beq(CCR0, hit);
1716   addi(array_ptr, array_ptr, BytesPerWord);
1717   bdnz(loop);
1718 
1719   bind(failure);
1720   if (result_reg!=noreg) li(result_reg, 1); // load non-zero result (indicates a miss)
1721   b(fallthru);
1722 
1723   bind(hit);
1724   std(super_klass, target_offset, sub_klass); // save result to cache
1725   if (result_reg != noreg) li(result_reg, 0); // load zero result (indicates a hit)
1726   if (L_success != NULL) b(*L_success);
1727 
1728   bind(fallthru);
1729 }
1730 
1731 // Try fast path, then go to slow one if not successful
1732 void MacroAssembler::check_klass_subtype(Register sub_klass,
1733                          Register super_klass,
1734                          Register temp1_reg,
1735                          Register temp2_reg,
1736                          Label& L_success) {
1737   Label L_failure;
1738   check_klass_subtype_fast_path(sub_klass, super_klass, temp1_reg, temp2_reg, L_success, L_failure);
1739   check_klass_subtype_slow_path(sub_klass, super_klass, temp1_reg, temp2_reg, &L_success);
1740   bind(L_failure); // Fallthru if not successful.
1741 }
1742 
1743 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
1744                                               Register temp_reg,
1745                                               Label& wrong_method_type) {
1746   assert_different_registers(mtype_reg, mh_reg, temp_reg);
1747   // Compare method type against that of the receiver.
1748   load_heap_oop_not_null(temp_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg), mh_reg);
1749   cmpd(CCR0, temp_reg, mtype_reg);
1750   bne(CCR0, wrong_method_type);
1751 }
1752 
1753 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
1754                                                    Register temp_reg,
1755                                                    int extra_slot_offset) {
1756   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1757   int stackElementSize = Interpreter::stackElementSize;
1758   int offset = extra_slot_offset * stackElementSize;
1759   if (arg_slot.is_constant()) {
1760     offset += arg_slot.as_constant() * stackElementSize;
1761     return offset;
1762   } else {
1763     assert(temp_reg != noreg, "must specify");
1764     sldi(temp_reg, arg_slot.as_register(), exact_log2(stackElementSize));
1765     if (offset != 0)
1766       addi(temp_reg, temp_reg, offset);
1767     return temp_reg;
1768   }
1769 }
1770 
1771 void MacroAssembler::biased_locking_enter(ConditionRegister cr_reg, Register obj_reg,
1772                                           Register mark_reg, Register temp_reg,
1773                                           Register temp2_reg, Label& done, Label* slow_case) {
1774   assert(UseBiasedLocking, "why call this otherwise?");
1775 
1776 #ifdef ASSERT
1777   assert_different_registers(obj_reg, mark_reg, temp_reg, temp2_reg);
1778 #endif
1779 
1780   Label cas_label;
1781 
1782   // Branch to done if fast path fails and no slow_case provided.
1783   Label *slow_case_int = (slow_case != NULL) ? slow_case : &done;
1784 
1785   // Biased locking
1786   // See whether the lock is currently biased toward our thread and
1787   // whether the epoch is still valid
1788   // Note that the runtime guarantees sufficient alignment of JavaThread
1789   // pointers to allow age to be placed into low bits
1790   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits,
1791          "biased locking makes assumptions about bit layout");
1792 
1793   if (PrintBiasedLockingStatistics) {
1794     load_const(temp_reg, (address) BiasedLocking::total_entry_count_addr(), temp2_reg);
1795     lwz(temp2_reg, 0, temp_reg);
1796     addi(temp2_reg, temp2_reg, 1);
1797     stw(temp2_reg, 0, temp_reg);
1798   }
1799 
1800   andi(temp_reg, mark_reg, markOopDesc::biased_lock_mask_in_place);
1801   cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
1802   bne(cr_reg, cas_label);
1803 
1804   load_klass(temp_reg, obj_reg);
1805 
1806   load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
1807   ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
1808   orr(temp_reg, R16_thread, temp_reg);
1809   xorr(temp_reg, mark_reg, temp_reg);
1810   andr(temp_reg, temp_reg, temp2_reg);
1811   cmpdi(cr_reg, temp_reg, 0);
1812   if (PrintBiasedLockingStatistics) {
1813     Label l;
1814     bne(cr_reg, l);
1815     load_const(mark_reg, (address) BiasedLocking::biased_lock_entry_count_addr());
1816     lwz(temp2_reg, 0, mark_reg);
1817     addi(temp2_reg, temp2_reg, 1);
1818     stw(temp2_reg, 0, mark_reg);
1819     // restore mark_reg
1820     ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
1821     bind(l);
1822   }
1823   beq(cr_reg, done);
1824 
1825   Label try_revoke_bias;
1826   Label try_rebias;
1827 
1828   // At this point we know that the header has the bias pattern and
1829   // that we are not the bias owner in the current epoch. We need to
1830   // figure out more details about the state of the header in order to
1831   // know what operations can be legally performed on the object's
1832   // header.
1833 
1834   // If the low three bits in the xor result aren't clear, that means
1835   // the prototype header is no longer biased and we have to revoke
1836   // the bias on this object.
1837   andi(temp2_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
1838   cmpwi(cr_reg, temp2_reg, 0);
1839   bne(cr_reg, try_revoke_bias);
1840 
1841   // Biasing is still enabled for this data type. See whether the
1842   // epoch of the current bias is still valid, meaning that the epoch
1843   // bits of the mark word are equal to the epoch bits of the
1844   // prototype header. (Note that the prototype header's epoch bits
1845   // only change at a safepoint.) If not, attempt to rebias the object
1846   // toward the current thread. Note that we must be absolutely sure
1847   // that the current epoch is invalid in order to do this because
1848   // otherwise the manipulations it performs on the mark word are
1849   // illegal.
1850 
1851   int shift_amount = 64 - markOopDesc::epoch_shift;
1852   // rotate epoch bits to right (little) end and set other bits to 0
1853   // [ big part | epoch | little part ] -> [ 0..0 | epoch ]
1854   rldicl_(temp2_reg, temp_reg, shift_amount, 64 - markOopDesc::epoch_bits);
1855   // branch if epoch bits are != 0, i.e. they differ, because the epoch has been incremented
1856   bne(CCR0, try_rebias);
1857 
1858   // The epoch of the current bias is still valid but we know nothing
1859   // about the owner; it might be set or it might be clear. Try to
1860   // acquire the bias of the object using an atomic operation. If this
1861   // fails we will go in to the runtime to revoke the object's bias.
1862   // Note that we first construct the presumed unbiased header so we
1863   // don't accidentally blow away another thread's valid bias.
1864   andi(mark_reg, mark_reg, (markOopDesc::biased_lock_mask_in_place |
1865                                 markOopDesc::age_mask_in_place |
1866                                 markOopDesc::epoch_mask_in_place));
1867   orr(temp_reg, R16_thread, mark_reg);
1868 
1869   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1870 
1871   // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1872   fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1873   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1874            /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1875            /*where=*/obj_reg,
1876            MacroAssembler::MemBarAcq,
1877            MacroAssembler::cmpxchgx_hint_acquire_lock(),
1878            noreg, slow_case_int); // bail out if failed
1879 
1880   // If the biasing toward our thread failed, this means that
1881   // another thread succeeded in biasing it toward itself and we
1882   // need to revoke that bias. The revocation will occur in the
1883   // interpreter runtime in the slow case.
1884   if (PrintBiasedLockingStatistics) {
1885     load_const(temp_reg, (address) BiasedLocking::anonymously_biased_lock_entry_count_addr(), temp2_reg);
1886     lwz(temp2_reg, 0, temp_reg);
1887     addi(temp2_reg, temp2_reg, 1);
1888     stw(temp2_reg, 0, temp_reg);
1889   }
1890   b(done);
1891 
1892   bind(try_rebias);
1893   // At this point we know the epoch has expired, meaning that the
1894   // current "bias owner", if any, is actually invalid. Under these
1895   // circumstances _only_, we are allowed to use the current header's
1896   // value as the comparison value when doing the cas to acquire the
1897   // bias in the current epoch. In other words, we allow transfer of
1898   // the bias from one thread to another directly in this situation.
1899   andi(temp_reg, mark_reg, markOopDesc::age_mask_in_place);
1900   orr(temp_reg, R16_thread, temp_reg);
1901   load_klass(temp2_reg, obj_reg);
1902   ld(temp2_reg, in_bytes(Klass::prototype_header_offset()), temp2_reg);
1903   orr(temp_reg, temp_reg, temp2_reg);
1904 
1905   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1906 
1907   // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1908   fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1909   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1910                  /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1911                  /*where=*/obj_reg,
1912                  MacroAssembler::MemBarAcq,
1913                  MacroAssembler::cmpxchgx_hint_acquire_lock(),
1914                  noreg, slow_case_int); // bail out if failed
1915 
1916   // If the biasing toward our thread failed, this means that
1917   // another thread succeeded in biasing it toward itself and we
1918   // need to revoke that bias. The revocation will occur in the
1919   // interpreter runtime in the slow case.
1920   if (PrintBiasedLockingStatistics) {
1921     load_const(temp_reg, (address) BiasedLocking::rebiased_lock_entry_count_addr(), temp2_reg);
1922     lwz(temp2_reg, 0, temp_reg);
1923     addi(temp2_reg, temp2_reg, 1);
1924     stw(temp2_reg, 0, temp_reg);
1925   }
1926   b(done);
1927 
1928   bind(try_revoke_bias);
1929   // The prototype mark in the klass doesn't have the bias bit set any
1930   // more, indicating that objects of this data type are not supposed
1931   // to be biased any more. We are going to try to reset the mark of
1932   // this object to the prototype value and fall through to the
1933   // CAS-based locking scheme. Note that if our CAS fails, it means
1934   // that another thread raced us for the privilege of revoking the
1935   // bias of this particular object, so it's okay to continue in the
1936   // normal locking code.
1937   load_klass(temp_reg, obj_reg);
1938   ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
1939   andi(temp2_reg, mark_reg, markOopDesc::age_mask_in_place);
1940   orr(temp_reg, temp_reg, temp2_reg);
1941 
1942   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1943 
1944   // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1945   fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1946   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1947                  /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1948                  /*where=*/obj_reg,
1949                  MacroAssembler::MemBarAcq,
1950                  MacroAssembler::cmpxchgx_hint_acquire_lock());
1951 
1952   // reload markOop in mark_reg before continuing with lightweight locking
1953   ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
1954 
1955   // Fall through to the normal CAS-based lock, because no matter what
1956   // the result of the above CAS, some thread must have succeeded in
1957   // removing the bias bit from the object's header.
1958   if (PrintBiasedLockingStatistics) {
1959     Label l;
1960     bne(cr_reg, l);
1961     load_const(temp_reg, (address) BiasedLocking::revoked_lock_entry_count_addr(), temp2_reg);
1962     lwz(temp2_reg, 0, temp_reg);
1963     addi(temp2_reg, temp2_reg, 1);
1964     stw(temp2_reg, 0, temp_reg);
1965     bind(l);
1966   }
1967 
1968   bind(cas_label);
1969 }
1970 
1971 void MacroAssembler::biased_locking_exit (ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done) {
1972   // Check for biased locking unlock case, which is a no-op
1973   // Note: we do not have to check the thread ID for two reasons.
1974   // First, the interpreter checks for IllegalMonitorStateException at
1975   // a higher level. Second, if the bias was revoked while we held the
1976   // lock, the object could not be rebiased toward another thread, so
1977   // the bias bit would be clear.
1978 
1979   ld(temp_reg, 0, mark_addr);
1980   andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
1981 
1982   cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
1983   beq(cr_reg, done);
1984 }
1985 
1986 // "The box" is the space on the stack where we copy the object mark.
1987 void MacroAssembler::compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
1988                                                Register temp, Register displaced_header, Register current_header) {
1989   assert_different_registers(oop, box, temp, displaced_header, current_header);
1990   assert(flag != CCR0, "bad condition register");
1991   Label cont;
1992   Label object_has_monitor;
1993   Label cas_failed;
1994 
1995   // Load markOop from object into displaced_header.
1996   ld(displaced_header, oopDesc::mark_offset_in_bytes(), oop);
1997 
1998 
1999   // Always do locking in runtime.
2000   if (EmitSync & 0x01) {
2001     cmpdi(flag, oop, 0); // Oop can't be 0 here => always false.
2002     return;
2003   }
2004 
2005   if (UseBiasedLocking) {
2006     biased_locking_enter(flag, oop, displaced_header, temp, current_header, cont);
2007   }
2008 
2009   // Handle existing monitor.
2010   if ((EmitSync & 0x02) == 0) {
2011     // The object has an existing monitor iff (mark & monitor_value) != 0.
2012     andi_(temp, displaced_header, markOopDesc::monitor_value);
2013     bne(CCR0, object_has_monitor);
2014   }
2015 
2016   // Set displaced_header to be (markOop of object | UNLOCK_VALUE).
2017   ori(displaced_header, displaced_header, markOopDesc::unlocked_value);
2018 
2019   // Load Compare Value application register.
2020 
2021   // Initialize the box. (Must happen before we update the object mark!)
2022   std(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2023 
2024   // Must fence, otherwise, preceding store(s) may float below cmpxchg.
2025   // Compare object markOop with mark and if equal exchange scratch1 with object markOop.
2026   // CmpxchgX sets cr_reg to cmpX(current, displaced).
2027   membar(Assembler::StoreStore);
2028   cmpxchgd(/*flag=*/flag,
2029            /*current_value=*/current_header,
2030            /*compare_value=*/displaced_header,
2031            /*exchange_value=*/box,
2032            /*where=*/oop,
2033            MacroAssembler::MemBarAcq,
2034            MacroAssembler::cmpxchgx_hint_acquire_lock(),
2035            noreg,
2036            &cas_failed);
2037   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2038 
2039   // If the compare-and-exchange succeeded, then we found an unlocked
2040   // object and we have now locked it.
2041   b(cont);
2042 
2043   bind(cas_failed);
2044   // We did not see an unlocked object so try the fast recursive case.
2045 
2046   // Check if the owner is self by comparing the value in the markOop of object
2047   // (current_header) with the stack pointer.
2048   sub(current_header, current_header, R1_SP);
2049   load_const_optimized(temp, (address) (~(os::vm_page_size()-1) |
2050                                         markOopDesc::lock_mask_in_place));
2051 
2052   and_(R0/*==0?*/, current_header, temp);
2053   // If condition is true we are cont and hence we can store 0 as the
2054   // displaced header in the box, which indicates that it is a recursive lock.
2055   mcrf(flag,CCR0);
2056   std(R0/*==0, perhaps*/, BasicLock::displaced_header_offset_in_bytes(), box);
2057 
2058   // Handle existing monitor.
2059   if ((EmitSync & 0x02) == 0) {
2060     b(cont);
2061 
2062     bind(object_has_monitor);
2063     // The object's monitor m is unlocked iff m->owner == NULL,
2064     // otherwise m->owner may contain a thread or a stack address.
2065     //
2066     // Try to CAS m->owner from NULL to current thread.
2067     addi(temp, displaced_header, ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value);
2068     li(displaced_header, 0);
2069     // CmpxchgX sets flag to cmpX(current, displaced).
2070     cmpxchgd(/*flag=*/flag,
2071              /*current_value=*/current_header,
2072              /*compare_value=*/displaced_header,
2073              /*exchange_value=*/R16_thread,
2074              /*where=*/temp,
2075              MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq,
2076              MacroAssembler::cmpxchgx_hint_acquire_lock());
2077 
2078     // Store a non-null value into the box.
2079     std(box, BasicLock::displaced_header_offset_in_bytes(), box);
2080 
2081 #   ifdef ASSERT
2082     bne(flag, cont);
2083     // We have acquired the monitor, check some invariants.
2084     addi(/*monitor=*/temp, temp, -ObjectMonitor::owner_offset_in_bytes());
2085     // Invariant 1: _recursions should be 0.
2086     //assert(ObjectMonitor::recursions_size_in_bytes() == 8, "unexpected size");
2087     asm_assert_mem8_is_zero(ObjectMonitor::recursions_offset_in_bytes(), temp,
2088                             "monitor->_recursions should be 0", -1);
2089     // Invariant 2: OwnerIsThread shouldn't be 0.
2090     //assert(ObjectMonitor::OwnerIsThread_size_in_bytes() == 4, "unexpected size");
2091     //asm_assert_mem4_isnot_zero(ObjectMonitor::OwnerIsThread_offset_in_bytes(), temp,
2092     //                           "monitor->OwnerIsThread shouldn't be 0", -1);
2093 #   endif
2094   }
2095 
2096   bind(cont);
2097   // flag == EQ indicates success
2098   // flag == NE indicates failure
2099 }
2100 
2101 void MacroAssembler::compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
2102                                                  Register temp, Register displaced_header, Register current_header) {
2103   assert_different_registers(oop, box, temp, displaced_header, current_header);
2104   assert(flag != CCR0, "bad condition register");
2105   Label cont;
2106   Label object_has_monitor;
2107 
2108   // Always do locking in runtime.
2109   if (EmitSync & 0x01) {
2110     cmpdi(flag, oop, 0); // Oop can't be 0 here => always false.
2111     return;
2112   }
2113 
2114   if (UseBiasedLocking) {
2115     biased_locking_exit(flag, oop, current_header, cont);
2116   }
2117 
2118   // Find the lock address and load the displaced header from the stack.
2119   ld(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2120 
2121   // If the displaced header is 0, we have a recursive unlock.
2122   cmpdi(flag, displaced_header, 0);
2123   beq(flag, cont);
2124 
2125   // Handle existing monitor.
2126   if ((EmitSync & 0x02) == 0) {
2127     // The object has an existing monitor iff (mark & monitor_value) != 0.
2128     ld(current_header, oopDesc::mark_offset_in_bytes(), oop);
2129     andi(temp, current_header, markOopDesc::monitor_value);
2130     cmpdi(flag, temp, 0);
2131     bne(flag, object_has_monitor);
2132   }
2133 
2134 
2135   // Check if it is still a light weight lock, this is is true if we see
2136   // the stack address of the basicLock in the markOop of the object.
2137   // Cmpxchg sets flag to cmpd(current_header, box).
2138   cmpxchgd(/*flag=*/flag,
2139            /*current_value=*/current_header,
2140            /*compare_value=*/box,
2141            /*exchange_value=*/displaced_header,
2142            /*where=*/oop,
2143            MacroAssembler::MemBarRel,
2144            MacroAssembler::cmpxchgx_hint_release_lock(),
2145            noreg,
2146            &cont);
2147 
2148   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2149 
2150   // Handle existing monitor.
2151   if ((EmitSync & 0x02) == 0) {
2152     b(cont);
2153 
2154     bind(object_has_monitor);
2155     addi(current_header, current_header, -markOopDesc::monitor_value); // monitor
2156     ld(temp,             ObjectMonitor::owner_offset_in_bytes(), current_header);
2157     ld(displaced_header, ObjectMonitor::recursions_offset_in_bytes(), current_header);
2158     xorr(temp, R16_thread, temp);      // Will be 0 if we are the owner.
2159     orr(temp, temp, displaced_header); // Will be 0 if there are 0 recursions.
2160     cmpdi(flag, temp, 0);
2161     bne(flag, cont);
2162 
2163     ld(temp,             ObjectMonitor::EntryList_offset_in_bytes(), current_header);
2164     ld(displaced_header, ObjectMonitor::cxq_offset_in_bytes(), current_header);
2165     orr(temp, temp, displaced_header); // Will be 0 if both are 0.
2166     cmpdi(flag, temp, 0);
2167     bne(flag, cont);
2168     release();
2169     std(temp, ObjectMonitor::owner_offset_in_bytes(), current_header);
2170   }
2171 
2172   bind(cont);
2173   // flag == EQ indicates success
2174   // flag == NE indicates failure
2175 }
2176 
2177 // Write serialization page so VM thread can do a pseudo remote membar.
2178 // We use the current thread pointer to calculate a thread specific
2179 // offset to write to within the page. This minimizes bus traffic
2180 // due to cache line collision.
2181 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
2182   srdi(tmp2, thread, os::get_serialize_page_shift_count());
2183 
2184   int mask = os::vm_page_size() - sizeof(int);
2185   if (Assembler::is_simm(mask, 16)) {
2186     andi(tmp2, tmp2, mask);
2187   } else {
2188     lis(tmp1, (int)((signed short) (mask >> 16)));
2189     ori(tmp1, tmp1, mask & 0x0000ffff);
2190     andr(tmp2, tmp2, tmp1);
2191   }
2192 
2193   load_const(tmp1, (long) os::get_memory_serialize_page());
2194   release();
2195   stwx(R0, tmp1, tmp2);
2196 }
2197 
2198 
2199 // GC barrier helper macros
2200 
2201 // Write the card table byte if needed.
2202 void MacroAssembler::card_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp) {
2203   CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
2204   assert(bs->kind() == BarrierSet::CardTableModRef ||
2205          bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
2206 #ifdef ASSERT
2207   cmpdi(CCR0, Rnew_val, 0);
2208   asm_assert_ne("null oop not allowed", 0x321);
2209 #endif
2210   card_table_write(bs->byte_map_base, Rtmp, Rstore_addr);
2211 }
2212 
2213 // Write the card table byte.
2214 void MacroAssembler::card_table_write(jbyte* byte_map_base, Register Rtmp, Register Robj) {
2215   assert_different_registers(Robj, Rtmp, R0);
2216   load_const_optimized(Rtmp, (address)byte_map_base, R0);
2217   srdi(Robj, Robj, CardTableModRefBS::card_shift);
2218   li(R0, 0); // dirty
2219   if (UseConcMarkSweepGC) membar(Assembler::StoreStore);
2220   stbx(R0, Rtmp, Robj);
2221 }
2222 
2223 #if INCLUDE_ALL_GCS
2224 // General G1 pre-barrier generator.
2225 // Goal: record the previous value if it is not null.
2226 void MacroAssembler::g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val,
2227                                           Register Rtmp1, Register Rtmp2, bool needs_frame) {
2228   Label runtime, filtered;
2229 
2230   // Is marking active?
2231   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
2232     lwz(Rtmp1, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_active()), R16_thread);
2233   } else {
2234     guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
2235     lbz(Rtmp1, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_active()), R16_thread);
2236   }
2237   cmpdi(CCR0, Rtmp1, 0);
2238   beq(CCR0, filtered);
2239 
2240   // Do we need to load the previous value?
2241   if (Robj != noreg) {
2242     // Load the previous value...
2243     if (UseCompressedOops) {
2244       lwz(Rpre_val, offset, Robj);
2245     } else {
2246       ld(Rpre_val, offset, Robj);
2247     }
2248     // Previous value has been loaded into Rpre_val.
2249   }
2250   assert(Rpre_val != noreg, "must have a real register");
2251 
2252   // Is the previous value null?
2253   cmpdi(CCR0, Rpre_val, 0);
2254   beq(CCR0, filtered);
2255 
2256   if (Robj != noreg && UseCompressedOops) {
2257     decode_heap_oop_not_null(Rpre_val);
2258   }
2259 
2260   // OK, it's not filtered, so we'll need to call enqueue. In the normal
2261   // case, pre_val will be a scratch G-reg, but there are some cases in
2262   // which it's an O-reg. In the first case, do a normal call. In the
2263   // latter, do a save here and call the frameless version.
2264 
2265   // Can we store original value in the thread's buffer?
2266   // Is index == 0?
2267   // (The index field is typed as size_t.)
2268   const Register Rbuffer = Rtmp1, Rindex = Rtmp2;
2269 
2270   ld(Rindex, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2271   cmpdi(CCR0, Rindex, 0);
2272   beq(CCR0, runtime); // If index == 0, goto runtime.
2273   ld(Rbuffer, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_buf()), R16_thread);
2274 
2275   addi(Rindex, Rindex, -wordSize); // Decrement index.
2276   std(Rindex, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2277 
2278   // Record the previous value.
2279   stdx(Rpre_val, Rbuffer, Rindex);
2280   b(filtered);
2281 
2282   bind(runtime);
2283 
2284   // VM call need frame to access(write) O register.
2285   if (needs_frame) {
2286     save_LR_CR(Rtmp1);
2287     push_frame_reg_args(0, Rtmp2);
2288   }
2289 
2290   if (Rpre_val->is_volatile() && Robj == noreg) mr(R31, Rpre_val); // Save pre_val across C call if it was preloaded.
2291   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), Rpre_val, R16_thread);
2292   if (Rpre_val->is_volatile() && Robj == noreg) mr(Rpre_val, R31); // restore
2293 
2294   if (needs_frame) {
2295     pop_frame();
2296     restore_LR_CR(Rtmp1);
2297   }
2298 
2299   bind(filtered);
2300 }
2301 
2302 // General G1 post-barrier generator
2303 // Store cross-region card.
2304 void MacroAssembler::g1_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp1, Register Rtmp2, Register Rtmp3, Label *filtered_ext) {
2305   Label runtime, filtered_int;
2306   Label& filtered = (filtered_ext != NULL) ? *filtered_ext : filtered_int;
2307   assert_different_registers(Rstore_addr, Rnew_val, Rtmp1, Rtmp2);
2308 
2309   G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
2310   assert(bs->kind() == BarrierSet::G1SATBCT ||
2311          bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
2312 
2313   // Does store cross heap regions?
2314   if (G1RSBarrierRegionFilter) {
2315     xorr(Rtmp1, Rstore_addr, Rnew_val);
2316     srdi_(Rtmp1, Rtmp1, HeapRegion::LogOfHRGrainBytes);
2317     beq(CCR0, filtered);
2318   }
2319 
2320   // Crosses regions, storing NULL?
2321 #ifdef ASSERT
2322   cmpdi(CCR0, Rnew_val, 0);
2323   asm_assert_ne("null oop not allowed (G1)", 0x322); // Checked by caller on PPC64, so following branch is obsolete:
2324   //beq(CCR0, filtered);
2325 #endif
2326 
2327   // Storing region crossing non-NULL, is card already dirty?
2328   assert(sizeof(*bs->byte_map_base) == sizeof(jbyte), "adjust this code");
2329   const Register Rcard_addr = Rtmp1;
2330   Register Rbase = Rtmp2;
2331   load_const_optimized(Rbase, (address)bs->byte_map_base, /*temp*/ Rtmp3);
2332 
2333   srdi(Rcard_addr, Rstore_addr, CardTableModRefBS::card_shift);
2334 
2335   // Get the address of the card.
2336   lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr);
2337   cmpwi(CCR0, Rtmp3, (int)G1SATBCardTableModRefBS::g1_young_card_val());
2338   beq(CCR0, filtered);
2339 
2340   membar(Assembler::StoreLoad);
2341   lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr);  // Reload after membar.
2342   cmpwi(CCR0, Rtmp3 /* card value */, CardTableModRefBS::dirty_card_val());
2343   beq(CCR0, filtered);
2344 
2345   // Storing a region crossing, non-NULL oop, card is clean.
2346   // Dirty card and log.
2347   li(Rtmp3, CardTableModRefBS::dirty_card_val());
2348   //release(); // G1: oops are allowed to get visible after dirty marking.
2349   stbx(Rtmp3, Rbase, Rcard_addr);
2350 
2351   add(Rcard_addr, Rbase, Rcard_addr); // This is the address which needs to get enqueued.
2352   Rbase = noreg; // end of lifetime
2353 
2354   const Register Rqueue_index = Rtmp2,
2355                  Rqueue_buf   = Rtmp3;
2356   ld(Rqueue_index, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2357   cmpdi(CCR0, Rqueue_index, 0);
2358   beq(CCR0, runtime); // index == 0 then jump to runtime
2359   ld(Rqueue_buf, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_buf()), R16_thread);
2360 
2361   addi(Rqueue_index, Rqueue_index, -wordSize); // decrement index
2362   std(Rqueue_index, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2363 
2364   stdx(Rcard_addr, Rqueue_buf, Rqueue_index); // store card
2365   b(filtered);
2366 
2367   bind(runtime);
2368 
2369   // Save the live input values.
2370   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), Rcard_addr, R16_thread);
2371 
2372   bind(filtered_int);
2373 }
2374 #endif // INCLUDE_ALL_GCS
2375 
2376 // Values for last_Java_pc, and last_Java_sp must comply to the rules
2377 // in frame_ppc.hpp.
2378 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) {
2379   // Always set last_Java_pc and flags first because once last_Java_sp
2380   // is visible has_last_Java_frame is true and users will look at the
2381   // rest of the fields. (Note: flags should always be zero before we
2382   // get here so doesn't need to be set.)
2383 
2384   // Verify that last_Java_pc was zeroed on return to Java
2385   asm_assert_mem8_is_zero(in_bytes(JavaThread::last_Java_pc_offset()), R16_thread,
2386                           "last_Java_pc not zeroed before leaving Java", 0x200);
2387 
2388   // When returning from calling out from Java mode the frame anchor's
2389   // last_Java_pc will always be set to NULL. It is set here so that
2390   // if we are doing a call to native (not VM) that we capture the
2391   // known pc and don't have to rely on the native call having a
2392   // standard frame linkage where we can find the pc.
2393   if (last_Java_pc != noreg)
2394     std(last_Java_pc, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
2395 
2396   // Set last_Java_sp last.
2397   std(last_Java_sp, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
2398 }
2399 
2400 void MacroAssembler::reset_last_Java_frame(void) {
2401   asm_assert_mem8_isnot_zero(in_bytes(JavaThread::last_Java_sp_offset()),
2402                              R16_thread, "SP was not set, still zero", 0x202);
2403 
2404   BLOCK_COMMENT("reset_last_Java_frame {");
2405   li(R0, 0);
2406 
2407   // _last_Java_sp = 0
2408   std(R0, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
2409 
2410   // _last_Java_pc = 0
2411   std(R0, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
2412   BLOCK_COMMENT("} reset_last_Java_frame");
2413 }
2414 
2415 void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1) {
2416   assert_different_registers(sp, tmp1);
2417 
2418   // sp points to a TOP_IJAVA_FRAME, retrieve frame's PC via
2419   // TOP_IJAVA_FRAME_ABI.
2420   // FIXME: assert that we really have a TOP_IJAVA_FRAME here!
2421 #ifdef CC_INTERP
2422   ld(tmp1/*pc*/, _top_ijava_frame_abi(frame_manager_lr), sp);
2423 #else
2424   address entry = pc();
2425   load_const_optimized(tmp1, entry);
2426 #endif
2427 
2428   set_last_Java_frame(/*sp=*/sp, /*pc=*/tmp1);
2429 }
2430 
2431 void MacroAssembler::get_vm_result(Register oop_result) {
2432   // Read:
2433   //   R16_thread
2434   //   R16_thread->in_bytes(JavaThread::vm_result_offset())
2435   //
2436   // Updated:
2437   //   oop_result
2438   //   R16_thread->in_bytes(JavaThread::vm_result_offset())
2439 
2440   ld(oop_result, in_bytes(JavaThread::vm_result_offset()), R16_thread);
2441   li(R0, 0);
2442   std(R0, in_bytes(JavaThread::vm_result_offset()), R16_thread);
2443 
2444   verify_oop(oop_result);
2445 }
2446 
2447 void MacroAssembler::get_vm_result_2(Register metadata_result) {
2448   // Read:
2449   //   R16_thread
2450   //   R16_thread->in_bytes(JavaThread::vm_result_2_offset())
2451   //
2452   // Updated:
2453   //   metadata_result
2454   //   R16_thread->in_bytes(JavaThread::vm_result_2_offset())
2455 
2456   ld(metadata_result, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
2457   li(R0, 0);
2458   std(R0, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
2459 }
2460 
2461 
2462 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
2463   Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided.
2464   if (Universe::narrow_klass_base() != 0) {
2465     // Use dst as temp if it is free.
2466     load_const(R0, Universe::narrow_klass_base(), (dst != current && dst != R0) ? dst : noreg);
2467     sub(dst, current, R0);
2468     current = dst;
2469   }
2470   if (Universe::narrow_klass_shift() != 0) {
2471     srdi(dst, current, Universe::narrow_klass_shift());
2472     current = dst;
2473   }
2474   mr_if_needed(dst, current); // Move may be required.
2475 }
2476 
2477 void MacroAssembler::store_klass(Register dst_oop, Register klass, Register ck) {
2478   if (UseCompressedClassPointers) {
2479     encode_klass_not_null(ck, klass);
2480     stw(ck, oopDesc::klass_offset_in_bytes(), dst_oop);
2481   } else {
2482     std(klass, oopDesc::klass_offset_in_bytes(), dst_oop);
2483   }
2484 }
2485 
2486 void MacroAssembler::store_klass_gap(Register dst_oop, Register val) {
2487   if (UseCompressedClassPointers) {
2488     if (val == noreg) {
2489       val = R0;
2490       li(val, 0);
2491     }
2492     stw(val, oopDesc::klass_gap_offset_in_bytes(), dst_oop); // klass gap if compressed
2493   }
2494 }
2495 
2496 int MacroAssembler::instr_size_for_decode_klass_not_null() {
2497   if (!UseCompressedClassPointers) return 0;
2498   int num_instrs = 1;  // shift or move
2499   if (Universe::narrow_klass_base() != 0) num_instrs = 7;  // shift + load const + add
2500   return num_instrs * BytesPerInstWord;
2501 }
2502 
2503 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
2504   assert(dst != R0, "Dst reg may not be R0, as R0 is used here.");
2505   if (src == noreg) src = dst;
2506   Register shifted_src = src;
2507   if (Universe::narrow_klass_shift() != 0 ||
2508       Universe::narrow_klass_base() == 0 && src != dst) {  // Move required.
2509     shifted_src = dst;
2510     sldi(shifted_src, src, Universe::narrow_klass_shift());
2511   }
2512   if (Universe::narrow_klass_base() != 0) {
2513     load_const(R0, Universe::narrow_klass_base());
2514     add(dst, shifted_src, R0);
2515   }
2516 }
2517 
2518 void MacroAssembler::load_klass(Register dst, Register src) {
2519   if (UseCompressedClassPointers) {
2520     lwz(dst, oopDesc::klass_offset_in_bytes(), src);
2521     // Attention: no null check here!
2522     decode_klass_not_null(dst, dst);
2523   } else {
2524     ld(dst, oopDesc::klass_offset_in_bytes(), src);
2525   }
2526 }
2527 
2528 void MacroAssembler::load_klass_with_trap_null_check(Register dst, Register src) {
2529   if (!os::zero_page_read_protected()) {
2530     if (TrapBasedNullChecks) {
2531       trap_null_check(src);
2532     }
2533   }
2534   load_klass(dst, src);
2535 }
2536 
2537 void MacroAssembler::reinit_heapbase(Register d, Register tmp) {
2538   if (Universe::heap() != NULL) {
2539     load_const_optimized(R30, Universe::narrow_ptrs_base(), tmp);
2540   } else {
2541     // Heap not yet allocated. Load indirectly.
2542     int simm16_offset = load_const_optimized(R30, Universe::narrow_ptrs_base_addr(), tmp, true);
2543     ld(R30, simm16_offset, R30);
2544   }
2545 }
2546 
2547 // Clear Array
2548 // Kills both input registers. tmp == R0 is allowed.
2549 void MacroAssembler::clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp) {
2550   // Procedure for large arrays (uses data cache block zero instruction).
2551     Label startloop, fast, fastloop, small_rest, restloop, done;
2552     const int cl_size         = VM_Version::get_cache_line_size(),
2553               cl_dwords       = cl_size>>3,
2554               cl_dw_addr_bits = exact_log2(cl_dwords),
2555               dcbz_min        = 1;                     // Min count of dcbz executions, needs to be >0.
2556 
2557 //2:
2558     cmpdi(CCR1, cnt_dwords, ((dcbz_min+1)<<cl_dw_addr_bits)-1); // Big enough? (ensure >=dcbz_min lines included).
2559     blt(CCR1, small_rest);                                      // Too small.
2560     rldicl_(tmp, base_ptr, 64-3, 64-cl_dw_addr_bits);           // Extract dword offset within first cache line.
2561     beq(CCR0, fast);                                            // Already 128byte aligned.
2562 
2563     subfic(tmp, tmp, cl_dwords);
2564     mtctr(tmp);                        // Set ctr to hit 128byte boundary (0<ctr<cl_dwords).
2565     subf(cnt_dwords, tmp, cnt_dwords); // rest.
2566     li(tmp, 0);
2567 //10:
2568   bind(startloop);                     // Clear at the beginning to reach 128byte boundary.
2569     std(tmp, 0, base_ptr);             // Clear 8byte aligned block.
2570     addi(base_ptr, base_ptr, 8);
2571     bdnz(startloop);
2572 //13:
2573   bind(fast);                                  // Clear 128byte blocks.
2574     srdi(tmp, cnt_dwords, cl_dw_addr_bits);    // Loop count for 128byte loop (>0).
2575     andi(cnt_dwords, cnt_dwords, cl_dwords-1); // Rest in dwords.
2576     mtctr(tmp);                                // Load counter.
2577 //16:
2578   bind(fastloop);
2579     dcbz(base_ptr);                    // Clear 128byte aligned block.
2580     addi(base_ptr, base_ptr, cl_size);
2581     bdnz(fastloop);
2582     if (InsertEndGroupPPC64) { endgroup(); } else { nop(); }
2583 //20:
2584   bind(small_rest);
2585     cmpdi(CCR0, cnt_dwords, 0);        // size 0?
2586     beq(CCR0, done);                   // rest == 0
2587     li(tmp, 0);
2588     mtctr(cnt_dwords);                 // Load counter.
2589 //24:
2590   bind(restloop);                      // Clear rest.
2591     std(tmp, 0, base_ptr);             // Clear 8byte aligned block.
2592     addi(base_ptr, base_ptr, 8);
2593     bdnz(restloop);
2594 //27:
2595   bind(done);
2596 }
2597 
2598 /////////////////////////////////////////// String intrinsics ////////////////////////////////////////////
2599 
2600 // Search for a single jchar in an jchar[].
2601 //
2602 // Assumes that result differs from all other registers.
2603 //
2604 // Haystack, needle are the addresses of jchar-arrays.
2605 // NeedleChar is needle[0] if it is known at compile time.
2606 // Haycnt is the length of the haystack. We assume haycnt >=1.
2607 //
2608 // Preserves haystack, haycnt, kills all other registers.
2609 //
2610 // If needle == R0, we search for the constant needleChar.
2611 void MacroAssembler::string_indexof_1(Register result, Register haystack, Register haycnt,
2612                                       Register needle, jchar needleChar,
2613                                       Register tmp1, Register tmp2) {
2614 
2615   assert_different_registers(result, haystack, haycnt, needle, tmp1, tmp2);
2616 
2617   Label L_InnerLoop, L_FinalCheck, L_Found1, L_Found2, L_Found3, L_NotFound, L_End;
2618   Register needle0 = needle, // Contains needle[0].
2619            addr = tmp1,
2620            ch1 = tmp2,
2621            ch2 = R0;
2622 
2623 //2 (variable) or 3 (const):
2624    if (needle != R0) lhz(needle0, 0, needle); // Preload needle character, needle has len==1.
2625    dcbtct(haystack, 0x00);                        // Indicate R/O access to haystack.
2626 
2627    srwi_(tmp2, haycnt, 1);   // Shift right by exact_log2(UNROLL_FACTOR).
2628    mr(addr, haystack);
2629    beq(CCR0, L_FinalCheck);
2630    mtctr(tmp2);              // Move to count register.
2631 //8:
2632   bind(L_InnerLoop);             // Main work horse (2x unrolled search loop).
2633    lhz(ch1, 0, addr);        // Load characters from haystack.
2634    lhz(ch2, 2, addr);
2635    (needle != R0) ? cmpw(CCR0, ch1, needle0) : cmplwi(CCR0, ch1, needleChar);
2636    (needle != R0) ? cmpw(CCR1, ch2, needle0) : cmplwi(CCR1, ch2, needleChar);
2637    beq(CCR0, L_Found1);   // Did we find the needle?
2638    beq(CCR1, L_Found2);
2639    addi(addr, addr, 4);
2640    bdnz(L_InnerLoop);
2641 //16:
2642   bind(L_FinalCheck);
2643    andi_(R0, haycnt, 1);
2644    beq(CCR0, L_NotFound);
2645    lhz(ch1, 0, addr);        // One position left at which we have to compare.
2646    (needle != R0) ? cmpw(CCR1, ch1, needle0) : cmplwi(CCR1, ch1, needleChar);
2647    beq(CCR1, L_Found3);
2648 //21:
2649   bind(L_NotFound);
2650    li(result, -1);           // Not found.
2651    b(L_End);
2652 
2653   bind(L_Found2);
2654    addi(addr, addr, 2);
2655 //24:
2656   bind(L_Found1);
2657   bind(L_Found3);                  // Return index ...
2658    subf(addr, haystack, addr); // relative to haystack,
2659    srdi(result, addr, 1);      // in characters.
2660   bind(L_End);
2661 }
2662 
2663 
2664 // Implementation of IndexOf for jchar arrays.
2665 //
2666 // The length of haystack and needle are not constant, i.e. passed in a register.
2667 //
2668 // Preserves registers haystack, needle.
2669 // Kills registers haycnt, needlecnt.
2670 // Assumes that result differs from all other registers.
2671 // Haystack, needle are the addresses of jchar-arrays.
2672 // Haycnt, needlecnt are the lengths of them, respectively.
2673 //
2674 // Needlecntval must be zero or 15-bit unsigned immediate and > 1.
2675 void MacroAssembler::string_indexof(Register result, Register haystack, Register haycnt,
2676                                     Register needle, ciTypeArray* needle_values, Register needlecnt, int needlecntval,
2677                                     Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
2678 
2679   // Ensure 0<needlecnt<=haycnt in ideal graph as prerequisite!
2680   Label L_TooShort, L_Found, L_NotFound, L_End;
2681   Register last_addr = haycnt, // Kill haycnt at the beginning.
2682            addr      = tmp1,
2683            n_start   = tmp2,
2684            ch1       = tmp3,
2685            ch2       = R0;
2686 
2687   // **************************************************************************************************
2688   // Prepare for main loop: optimized for needle count >=2, bail out otherwise.
2689   // **************************************************************************************************
2690 
2691 //1 (variable) or 3 (const):
2692    dcbtct(needle, 0x00);    // Indicate R/O access to str1.
2693    dcbtct(haystack, 0x00);  // Indicate R/O access to str2.
2694 
2695   // Compute last haystack addr to use if no match gets found.
2696   if (needlecntval == 0) { // variable needlecnt
2697 //3:
2698    subf(ch1, needlecnt, haycnt);      // Last character index to compare is haycnt-needlecnt.
2699    addi(addr, haystack, -2);          // Accesses use pre-increment.
2700    cmpwi(CCR6, needlecnt, 2);
2701    blt(CCR6, L_TooShort);          // Variable needlecnt: handle short needle separately.
2702    slwi(ch1, ch1, 1);                 // Scale to number of bytes.
2703    lwz(n_start, 0, needle);           // Load first 2 characters of needle.
2704    add(last_addr, haystack, ch1);     // Point to last address to compare (haystack+2*(haycnt-needlecnt)).
2705    addi(needlecnt, needlecnt, -2);    // Rest of needle.
2706   } else { // constant needlecnt
2707   guarantee(needlecntval != 1, "IndexOf with single-character needle must be handled separately");
2708   assert((needlecntval & 0x7fff) == needlecntval, "wrong immediate");
2709 //5:
2710    addi(ch1, haycnt, -needlecntval);  // Last character index to compare is haycnt-needlecnt.
2711    lwz(n_start, 0, needle);           // Load first 2 characters of needle.
2712    addi(addr, haystack, -2);          // Accesses use pre-increment.
2713    slwi(ch1, ch1, 1);                 // Scale to number of bytes.
2714    add(last_addr, haystack, ch1);     // Point to last address to compare (haystack+2*(haycnt-needlecnt)).
2715    li(needlecnt, needlecntval-2);     // Rest of needle.
2716   }
2717 
2718   // Main Loop (now we have at least 3 characters).
2719 //11:
2720   Label L_OuterLoop, L_InnerLoop, L_FinalCheck, L_Comp1, L_Comp2, L_Comp3;
2721   bind(L_OuterLoop); // Search for 1st 2 characters.
2722   Register addr_diff = tmp4;
2723    subf(addr_diff, addr, last_addr); // Difference between already checked address and last address to check.
2724    addi(addr, addr, 2);              // This is the new address we want to use for comparing.
2725    srdi_(ch2, addr_diff, 2);
2726    beq(CCR0, L_FinalCheck);       // 2 characters left?
2727    mtctr(ch2);                       // addr_diff/4
2728 //16:
2729   bind(L_InnerLoop);                // Main work horse (2x unrolled search loop)
2730    lwz(ch1, 0, addr);           // Load 2 characters of haystack (ignore alignment).
2731    lwz(ch2, 2, addr);
2732    cmpw(CCR0, ch1, n_start); // Compare 2 characters (1 would be sufficient but try to reduce branches to CompLoop).
2733    cmpw(CCR1, ch2, n_start);
2734    beq(CCR0, L_Comp1);       // Did we find the needle start?
2735    beq(CCR1, L_Comp2);
2736    addi(addr, addr, 4);
2737    bdnz(L_InnerLoop);
2738 //24:
2739   bind(L_FinalCheck);
2740    rldicl_(addr_diff, addr_diff, 64-1, 63); // Remaining characters not covered by InnerLoop: (addr_diff>>1)&1.
2741    beq(CCR0, L_NotFound);
2742    lwz(ch1, 0, addr);                       // One position left at which we have to compare.
2743    cmpw(CCR1, ch1, n_start);
2744    beq(CCR1, L_Comp3);
2745 //29:
2746   bind(L_NotFound);
2747    li(result, -1); // not found
2748    b(L_End);
2749 
2750 
2751    // **************************************************************************************************
2752    // Special Case: unfortunately, the variable needle case can be called with needlecnt<2
2753    // **************************************************************************************************
2754 //31:
2755  if ((needlecntval>>1) !=1 ) { // Const needlecnt is 2 or 3? Reduce code size.
2756   int nopcnt = 5;
2757   if (needlecntval !=0 ) ++nopcnt; // Balance alignment (other case: see below).
2758   if (needlecntval == 0) {         // We have to handle these cases separately.
2759   Label L_OneCharLoop;
2760   bind(L_TooShort);
2761    mtctr(haycnt);
2762    lhz(n_start, 0, needle);    // First character of needle
2763   bind(L_OneCharLoop);
2764    lhzu(ch1, 2, addr);
2765    cmpw(CCR1, ch1, n_start);
2766    beq(CCR1, L_Found);      // Did we find the one character needle?
2767    bdnz(L_OneCharLoop);
2768    li(result, -1);             // Not found.
2769    b(L_End);
2770   } // 8 instructions, so no impact on alignment.
2771   for (int x = 0; x < nopcnt; ++x) nop();
2772  }
2773 
2774   // **************************************************************************************************
2775   // Regular Case Part II: compare rest of needle (first 2 characters have been compared already)
2776   // **************************************************************************************************
2777 
2778   // Compare the rest
2779 //36 if needlecntval==0, else 37:
2780   bind(L_Comp2);
2781    addi(addr, addr, 2); // First comparison has failed, 2nd one hit.
2782   bind(L_Comp1);            // Addr points to possible needle start.
2783   bind(L_Comp3);            // Could have created a copy and use a different return address but saving code size here.
2784   if (needlecntval != 2) {  // Const needlecnt==2?
2785    if (needlecntval != 3) {
2786     if (needlecntval == 0) beq(CCR6, L_Found); // Variable needlecnt==2?
2787     Register ind_reg = tmp4;
2788     li(ind_reg, 2*2);   // First 2 characters are already compared, use index 2.
2789     mtctr(needlecnt);   // Decremented by 2, still > 0.
2790 //40:
2791    Label L_CompLoop;
2792    bind(L_CompLoop);
2793     lhzx(ch2, needle, ind_reg);
2794     lhzx(ch1, addr, ind_reg);
2795     cmpw(CCR1, ch1, ch2);
2796     bne(CCR1, L_OuterLoop);
2797     addi(ind_reg, ind_reg, 2);
2798     bdnz(L_CompLoop);
2799    } else { // No loop required if there's only one needle character left.
2800     lhz(ch2, 2*2, needle);
2801     lhz(ch1, 2*2, addr);
2802     cmpw(CCR1, ch1, ch2);
2803     bne(CCR1, L_OuterLoop);
2804    }
2805   }
2806   // Return index ...
2807 //46:
2808   bind(L_Found);
2809    subf(addr, haystack, addr); // relative to haystack, ...
2810    srdi(result, addr, 1);      // in characters.
2811 //48:
2812   bind(L_End);
2813 }
2814 
2815 // Implementation of Compare for jchar arrays.
2816 //
2817 // Kills the registers str1, str2, cnt1, cnt2.
2818 // Kills cr0, ctr.
2819 // Assumes that result differes from the input registers.
2820 void MacroAssembler::string_compare(Register str1_reg, Register str2_reg, Register cnt1_reg, Register cnt2_reg,
2821                                     Register result_reg, Register tmp_reg) {
2822    assert_different_registers(result_reg, str1_reg, str2_reg, cnt1_reg, cnt2_reg, tmp_reg);
2823 
2824    Label Ldone, Lslow_case, Lslow_loop, Lfast_loop;
2825    Register cnt_diff = R0,
2826             limit_reg = cnt1_reg,
2827             chr1_reg = result_reg,
2828             chr2_reg = cnt2_reg,
2829             addr_diff = str2_reg;
2830 
2831    // Offset 0 should be 32 byte aligned.
2832 //-4:
2833     dcbtct(str1_reg, 0x00);  // Indicate R/O access to str1.
2834     dcbtct(str2_reg, 0x00);  // Indicate R/O access to str2.
2835 //-2:
2836    // Compute min(cnt1, cnt2) and check if 0 (bail out if we don't need to compare characters).
2837     subf(result_reg, cnt2_reg, cnt1_reg);  // difference between cnt1/2
2838     subf_(addr_diff, str1_reg, str2_reg);  // alias?
2839     beq(CCR0, Ldone);                   // return cnt difference if both ones are identical
2840     srawi(limit_reg, result_reg, 31);      // generate signmask (cnt1/2 must be non-negative so cnt_diff can't overflow)
2841     mr(cnt_diff, result_reg);
2842     andr(limit_reg, result_reg, limit_reg); // difference or zero (negative): cnt1<cnt2 ? cnt1-cnt2 : 0
2843     add_(limit_reg, cnt2_reg, limit_reg);  // min(cnt1, cnt2)==0?
2844     beq(CCR0, Ldone);                   // return cnt difference if one has 0 length
2845 
2846     lhz(chr1_reg, 0, str1_reg);            // optional: early out if first characters mismatch
2847     lhzx(chr2_reg, str1_reg, addr_diff);   // optional: early out if first characters mismatch
2848     addi(tmp_reg, limit_reg, -1);          // min(cnt1, cnt2)-1
2849     subf_(result_reg, chr2_reg, chr1_reg); // optional: early out if first characters mismatch
2850     bne(CCR0, Ldone);                   // optional: early out if first characters mismatch
2851 
2852    // Set loop counter by scaling down tmp_reg
2853     srawi_(chr2_reg, tmp_reg, exact_log2(4)); // (min(cnt1, cnt2)-1)/4
2854     ble(CCR0, Lslow_case);                 // need >4 characters for fast loop
2855     andi(limit_reg, tmp_reg, 4-1);            // remaining characters
2856 
2857    // Adapt str1_reg str2_reg for the first loop iteration
2858     mtctr(chr2_reg);                 // (min(cnt1, cnt2)-1)/4
2859     addi(limit_reg, limit_reg, 4+1); // compare last 5-8 characters in slow_case if mismatch found in fast_loop
2860 //16:
2861    // Compare the rest of the characters
2862    bind(Lfast_loop);
2863     ld(chr1_reg, 0, str1_reg);
2864     ldx(chr2_reg, str1_reg, addr_diff);
2865     cmpd(CCR0, chr2_reg, chr1_reg);
2866     bne(CCR0, Lslow_case); // return chr1_reg
2867     addi(str1_reg, str1_reg, 4*2);
2868     bdnz(Lfast_loop);
2869     addi(limit_reg, limit_reg, -4); // no mismatch found in fast_loop, only 1-4 characters missing
2870 //23:
2871    bind(Lslow_case);
2872     mtctr(limit_reg);
2873 //24:
2874    bind(Lslow_loop);
2875     lhz(chr1_reg, 0, str1_reg);
2876     lhzx(chr2_reg, str1_reg, addr_diff);
2877     subf_(result_reg, chr2_reg, chr1_reg);
2878     bne(CCR0, Ldone); // return chr1_reg
2879     addi(str1_reg, str1_reg, 1*2);
2880     bdnz(Lslow_loop);
2881 //30:
2882    // If strings are equal up to min length, return the length difference.
2883     mr(result_reg, cnt_diff);
2884     nop(); // alignment
2885 //32:
2886    // Otherwise, return the difference between the first mismatched chars.
2887    bind(Ldone);
2888 }
2889 
2890 
2891 // Compare char[] arrays.
2892 //
2893 // str1_reg   USE only
2894 // str2_reg   USE only
2895 // cnt_reg    USE_DEF, due to tmp reg shortage
2896 // result_reg DEF only, might compromise USE only registers
2897 void MacroAssembler::char_arrays_equals(Register str1_reg, Register str2_reg, Register cnt_reg, Register result_reg,
2898                                         Register tmp1_reg, Register tmp2_reg, Register tmp3_reg, Register tmp4_reg,
2899                                         Register tmp5_reg) {
2900 
2901   // Str1 may be the same register as str2 which can occur e.g. after scalar replacement.
2902   assert_different_registers(result_reg, str1_reg, cnt_reg, tmp1_reg, tmp2_reg, tmp3_reg, tmp4_reg, tmp5_reg);
2903   assert_different_registers(result_reg, str2_reg, cnt_reg, tmp1_reg, tmp2_reg, tmp3_reg, tmp4_reg, tmp5_reg);
2904 
2905   // Offset 0 should be 32 byte aligned.
2906   Label Linit_cbc, Lcbc, Lloop, Ldone_true, Ldone_false;
2907   Register index_reg = tmp5_reg;
2908   Register cbc_iter  = tmp4_reg;
2909 
2910 //-1:
2911   dcbtct(str1_reg, 0x00);  // Indicate R/O access to str1.
2912   dcbtct(str2_reg, 0x00);  // Indicate R/O access to str2.
2913 //1:
2914   andi(cbc_iter, cnt_reg, 4-1);            // Remaining iterations after 4 java characters per iteration loop.
2915   li(index_reg, 0); // init
2916   li(result_reg, 0); // assume false
2917   srwi_(tmp2_reg, cnt_reg, exact_log2(4)); // Div: 4 java characters per iteration (main loop).
2918 
2919   cmpwi(CCR1, cbc_iter, 0);             // CCR1 = (cbc_iter==0)
2920   beq(CCR0, Linit_cbc);                 // too short
2921     mtctr(tmp2_reg);
2922 //8:
2923     bind(Lloop);
2924       ldx(tmp1_reg, str1_reg, index_reg);
2925       ldx(tmp2_reg, str2_reg, index_reg);
2926       cmpd(CCR0, tmp1_reg, tmp2_reg);
2927       bne(CCR0, Ldone_false);  // Unequal char pair found -> done.
2928       addi(index_reg, index_reg, 4*sizeof(jchar));
2929       bdnz(Lloop);
2930 //14:
2931   bind(Linit_cbc);
2932   beq(CCR1, Ldone_true);
2933     mtctr(cbc_iter);
2934 //16:
2935     bind(Lcbc);
2936       lhzx(tmp1_reg, str1_reg, index_reg);
2937       lhzx(tmp2_reg, str2_reg, index_reg);
2938       cmpw(CCR0, tmp1_reg, tmp2_reg);
2939       bne(CCR0, Ldone_false);  // Unequal char pair found -> done.
2940       addi(index_reg, index_reg, 1*sizeof(jchar));
2941       bdnz(Lcbc);
2942     nop();
2943   bind(Ldone_true);
2944   li(result_reg, 1);
2945 //24:
2946   bind(Ldone_false);
2947 }
2948 
2949 
2950 void MacroAssembler::char_arrays_equalsImm(Register str1_reg, Register str2_reg, int cntval, Register result_reg,
2951                                            Register tmp1_reg, Register tmp2_reg) {
2952   // Str1 may be the same register as str2 which can occur e.g. after scalar replacement.
2953   assert_different_registers(result_reg, str1_reg, tmp1_reg, tmp2_reg);
2954   assert_different_registers(result_reg, str2_reg, tmp1_reg, tmp2_reg);
2955   assert(sizeof(jchar) == 2, "must be");
2956   assert(cntval >= 0 && ((cntval & 0x7fff) == cntval), "wrong immediate");
2957 
2958   Label Ldone_false;
2959 
2960   if (cntval < 16) { // short case
2961     if (cntval != 0) li(result_reg, 0); // assume false
2962 
2963     const int num_bytes = cntval*sizeof(jchar);
2964     int index = 0;
2965     for (int next_index; (next_index = index + 8) <= num_bytes; index = next_index) {
2966       ld(tmp1_reg, index, str1_reg);
2967       ld(tmp2_reg, index, str2_reg);
2968       cmpd(CCR0, tmp1_reg, tmp2_reg);
2969       bne(CCR0, Ldone_false);
2970     }
2971     if (cntval & 2) {
2972       lwz(tmp1_reg, index, str1_reg);
2973       lwz(tmp2_reg, index, str2_reg);
2974       cmpw(CCR0, tmp1_reg, tmp2_reg);
2975       bne(CCR0, Ldone_false);
2976       index += 4;
2977     }
2978     if (cntval & 1) {
2979       lhz(tmp1_reg, index, str1_reg);
2980       lhz(tmp2_reg, index, str2_reg);
2981       cmpw(CCR0, tmp1_reg, tmp2_reg);
2982       bne(CCR0, Ldone_false);
2983     }
2984     // fallthrough: true
2985   } else {
2986     Label Lloop;
2987     Register index_reg = tmp1_reg;
2988     const int loopcnt = cntval/4;
2989     assert(loopcnt > 0, "must be");
2990     // Offset 0 should be 32 byte aligned.
2991     //2:
2992     dcbtct(str1_reg, 0x00);  // Indicate R/O access to str1.
2993     dcbtct(str2_reg, 0x00);  // Indicate R/O access to str2.
2994     li(tmp2_reg, loopcnt);
2995     li(index_reg, 0); // init
2996     li(result_reg, 0); // assume false
2997     mtctr(tmp2_reg);
2998     //8:
2999     bind(Lloop);
3000     ldx(R0, str1_reg, index_reg);
3001     ldx(tmp2_reg, str2_reg, index_reg);
3002     cmpd(CCR0, R0, tmp2_reg);
3003     bne(CCR0, Ldone_false);  // Unequal char pair found -> done.
3004     addi(index_reg, index_reg, 4*sizeof(jchar));
3005     bdnz(Lloop);
3006     //14:
3007     if (cntval & 2) {
3008       lwzx(R0, str1_reg, index_reg);
3009       lwzx(tmp2_reg, str2_reg, index_reg);
3010       cmpw(CCR0, R0, tmp2_reg);
3011       bne(CCR0, Ldone_false);
3012       if (cntval & 1) addi(index_reg, index_reg, 2*sizeof(jchar));
3013     }
3014     if (cntval & 1) {
3015       lhzx(R0, str1_reg, index_reg);
3016       lhzx(tmp2_reg, str2_reg, index_reg);
3017       cmpw(CCR0, R0, tmp2_reg);
3018       bne(CCR0, Ldone_false);
3019     }
3020     // fallthru: true
3021   }
3022   li(result_reg, 1);
3023   bind(Ldone_false);
3024 }
3025 
3026 // Helpers for Intrinsic Emitters
3027 //
3028 // Revert the byte order of a 32bit value in a register
3029 //   src: 0x44556677
3030 //   dst: 0x77665544
3031 // Three steps to obtain the result:
3032 //  1) Rotate src (as doubleword) left 5 bytes. That puts the leftmost byte of the src word
3033 //     into the rightmost byte position. Afterwards, everything left of the rightmost byte is cleared.
3034 //     This value initializes dst.
3035 //  2) Rotate src (as word) left 3 bytes. That puts the rightmost byte of the src word into the leftmost
3036 //     byte position. Furthermore, byte 5 is rotated into byte 6 position where it is supposed to go.
3037 //     This value is mask inserted into dst with a [0..23] mask of 1s.
3038 //  3) Rotate src (as word) left 1 byte. That puts byte 6 into byte 5 position.
3039 //     This value is mask inserted into dst with a [8..15] mask of 1s.
3040 void MacroAssembler::load_reverse_32(Register dst, Register src) {
3041   assert_different_registers(dst, src);
3042 
3043   rldicl(dst, src, (4+1)*8, 56);       // Rotate byte 4 into position 7 (rightmost), clear all to the left.
3044   rlwimi(dst, src,     3*8,  0, 23);   // Insert byte 5 into position 6, 7 into 4, leave pos 7 alone.
3045   rlwimi(dst, src,     1*8,  8, 15);   // Insert byte 6 into position 5, leave the rest alone.
3046 }
3047 
3048 // Calculate the column addresses of the crc32 lookup table into distinct registers.
3049 // This loop-invariant calculation is moved out of the loop body, reducing the loop
3050 // body size from 20 to 16 instructions.
3051 // Returns the offset that was used to calculate the address of column tc3.
3052 // Due to register shortage, setting tc3 may overwrite table. With the return offset
3053 // at hand, the original table address can be easily reconstructed.
3054 int MacroAssembler::crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3) {
3055 
3056 #ifdef VM_LITTLE_ENDIAN
3057   // This is what we implement (the DOLIT4 part):
3058   // ========================================================================= */
3059   // #define DOLIT4 c ^= *buf4++; \
3060   //         c = crc_table[3][c & 0xff] ^ crc_table[2][(c >> 8) & 0xff] ^ \
3061   //             crc_table[1][(c >> 16) & 0xff] ^ crc_table[0][c >> 24]
3062   // #define DOLIT32 DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4
3063   // ========================================================================= */
3064   const int ix0 = 3*(4*CRC32_COLUMN_SIZE);
3065   const int ix1 = 2*(4*CRC32_COLUMN_SIZE);
3066   const int ix2 = 1*(4*CRC32_COLUMN_SIZE);
3067   const int ix3 = 0*(4*CRC32_COLUMN_SIZE);
3068 #else
3069   // This is what we implement (the DOBIG4 part):
3070   // =========================================================================
3071   // #define DOBIG4 c ^= *++buf4; \
3072   //         c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
3073   //             crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
3074   // #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
3075   // =========================================================================
3076   const int ix0 = 4*(4*CRC32_COLUMN_SIZE);
3077   const int ix1 = 5*(4*CRC32_COLUMN_SIZE);
3078   const int ix2 = 6*(4*CRC32_COLUMN_SIZE);
3079   const int ix3 = 7*(4*CRC32_COLUMN_SIZE);
3080 #endif
3081   assert_different_registers(table, tc0, tc1, tc2);
3082   assert(table == tc3, "must be!");
3083 
3084   if (ix0 != 0) addi(tc0, table, ix0);
3085   if (ix1 != 0) addi(tc1, table, ix1);
3086   if (ix2 != 0) addi(tc2, table, ix2);
3087   if (ix3 != 0) addi(tc3, table, ix3);
3088 
3089   return ix3;
3090 }
3091 
3092 /**
3093  * uint32_t crc;
3094  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
3095  */
3096 void MacroAssembler::fold_byte_crc32(Register crc, Register val, Register table, Register tmp) {
3097   assert_different_registers(crc, table, tmp);
3098   assert_different_registers(val, table);
3099 
3100   if (crc == val) {                   // Must rotate first to use the unmodified value.
3101     rlwinm(tmp, val, 2, 24-2, 31-2);  // Insert (rightmost) byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
3102                                       // As we use a word (4-byte) instruction, we have to adapt the mask bit positions.
3103     srwi(crc, crc, 8);                // Unsigned shift, clear leftmost 8 bits.
3104   } else {
3105     srwi(crc, crc, 8);                // Unsigned shift, clear leftmost 8 bits.
3106     rlwinm(tmp, val, 2, 24-2, 31-2);  // Insert (rightmost) byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
3107   }
3108   lwzx(tmp, table, tmp);
3109   xorr(crc, crc, tmp);
3110 }
3111 
3112 /**
3113  * uint32_t crc;
3114  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
3115  */
3116 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
3117   fold_byte_crc32(crc, crc, table, tmp);
3118 }
3119 
3120 /**
3121  * Emits code to update CRC-32 with a byte value according to constants in table.
3122  *
3123  * @param [in,out]crc   Register containing the crc.
3124  * @param [in]val       Register containing the byte to fold into the CRC.
3125  * @param [in]table     Register containing the table of crc constants.
3126  *
3127  * uint32_t crc;
3128  * val = crc_table[(val ^ crc) & 0xFF];
3129  * crc = val ^ (crc >> 8);
3130  */
3131 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3132   BLOCK_COMMENT("update_byte_crc32:");
3133   xorr(val, val, crc);
3134   fold_byte_crc32(crc, val, table, val);
3135 }
3136 
3137 /**
3138  * @param crc   register containing existing CRC (32-bit)
3139  * @param buf   register pointing to input byte buffer (byte*)
3140  * @param len   register containing number of bytes
3141  * @param table register pointing to CRC table
3142  */
3143 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
3144                                            Register data, bool loopAlignment, bool invertCRC) {
3145   assert_different_registers(crc, buf, len, table, data);
3146 
3147   Label L_mainLoop, L_done;
3148   const int mainLoop_stepping  = 1;
3149   const int mainLoop_alignment = loopAlignment ? 32 : 4; // (InputForNewCode > 4 ? InputForNewCode : 32) : 4;
3150 
3151   // Process all bytes in a single-byte loop.
3152   cmpdi(CCR0, len, 0);                           // Anything to do?
3153   mtctr(len);
3154   beq(CCR0, L_done);
3155 
3156   if (invertCRC) {
3157     nand(crc, crc, crc);                         // ~c
3158   }
3159 
3160   align(mainLoop_alignment);
3161   BIND(L_mainLoop);
3162     lbz(data, 0, buf);                           // Byte from buffer, zero-extended.
3163     addi(buf, buf, mainLoop_stepping);           // Advance buffer position.
3164     update_byte_crc32(crc, data, table);
3165     bdnz(L_mainLoop);                            // Iterate.
3166 
3167   if (invertCRC) {
3168     nand(crc, crc, crc);                         // ~c
3169   }
3170 
3171   bind(L_done);
3172 }
3173 
3174 /**
3175  * Emits code to update CRC-32 with a 4-byte value according to constants in table
3176  * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c
3177  */
3178 // A not on the lookup table address(es):
3179 // The lookup table consists of two sets of four columns each.
3180 // The columns {0..3} are used for little-endian machines.
3181 // The columns {4..7} are used for big-endian machines.
3182 // To save the effort of adding the column offset to the table address each time
3183 // a table element is looked up, it is possible to pass the pre-calculated
3184 // column addresses.
3185 // Uses R9..R12 as work register. Must be saved/restored by caller, if necessary.
3186 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
3187                                         Register t0,  Register t1,  Register t2,  Register t3,
3188                                         Register tc0, Register tc1, Register tc2, Register tc3) {
3189   assert_different_registers(crc, t3);
3190 
3191   // XOR crc with next four bytes of buffer.
3192   lwz(t3, bufDisp, buf);
3193   if (bufInc != 0) {
3194     addi(buf, buf, bufInc);
3195   }
3196   xorr(t3, t3, crc);
3197 
3198   // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
3199   rlwinm(t0, t3,  2,         24-2, 31-2);  // ((t1 >>  0) & 0xff) << 2
3200   rlwinm(t1, t3,  32+(2- 8), 24-2, 31-2);  // ((t1 >>  8) & 0xff) << 2
3201   rlwinm(t2, t3,  32+(2-16), 24-2, 31-2);  // ((t1 >> 16) & 0xff) << 2
3202   rlwinm(t3, t3,  32+(2-24), 24-2, 31-2);  // ((t1 >> 24) & 0xff) << 2
3203 
3204   // Use the pre-calculated column addresses.
3205   // Load pre-calculated table values.
3206   lwzx(t0, tc0, t0);
3207   lwzx(t1, tc1, t1);
3208   lwzx(t2, tc2, t2);
3209   lwzx(t3, tc3, t3);
3210 
3211   // Calculate new crc from table values.
3212   xorr(t0,  t0, t1);
3213   xorr(t2,  t2, t3);
3214   xorr(crc, t0, t2);  // Now crc contains the final checksum value.
3215 }
3216 
3217 /**
3218  * @param crc   register containing existing CRC (32-bit)
3219  * @param buf   register pointing to input byte buffer (byte*)
3220  * @param len   register containing number of bytes
3221  * @param table register pointing to CRC table
3222  *
3223  * Uses R9..R12 as work register. Must be saved/restored by caller!
3224  */
3225 void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
3226                                         Register t0,  Register t1,  Register t2,  Register t3,
3227                                         Register tc0, Register tc1, Register tc2, Register tc3) {
3228   assert_different_registers(crc, buf, len, table);
3229 
3230   Label L_mainLoop, L_tail;
3231   Register  tmp  = t0;
3232   Register  data = t0;
3233   Register  tmp2 = t1;
3234   const int mainLoop_stepping  = 8;
3235   const int tailLoop_stepping  = 1;
3236   const int log_stepping       = exact_log2(mainLoop_stepping);
3237   const int mainLoop_alignment = 32; // InputForNewCode > 4 ? InputForNewCode : 32;
3238   const int complexThreshold   = 2*mainLoop_stepping;
3239 
3240   // Don't test for len <= 0 here. This pathological case should not occur anyway.
3241   // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
3242   // The situation itself is detected and handled correctly by the conditional branches
3243   // following  aghi(len, -stepping) and aghi(len, +stepping).
3244   assert(tailLoop_stepping == 1, "check tailLoop_stepping!");
3245 
3246   BLOCK_COMMENT("kernel_crc32_2word {");
3247 
3248   nand(crc, crc, crc);                           // ~c
3249 
3250   // Check for short (<mainLoop_stepping) buffer.
3251   cmpdi(CCR0, len, complexThreshold);
3252   blt(CCR0, L_tail);
3253 
3254   // Pre-mainLoop alignment did show a slight (1%) positive effect on performance.
3255   // We leave the code in for reference. Maybe we need alignment when we exploit vector instructions.
3256   {
3257     // Align buf addr to mainLoop_stepping boundary.
3258     neg(tmp2, buf);                           // Calculate # preLoop iterations for alignment.
3259     rldicl(tmp2, tmp2, 0, 64-log_stepping);   // Rotate tmp2 0 bits, insert into tmp2, anding with mask with 1s from 62..63.
3260 
3261     if (complexThreshold > mainLoop_stepping) {
3262       sub(len, len, tmp2);                       // Remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
3263     } else {
3264       sub(tmp, len, tmp2);                       // Remaining bytes for main loop.
3265       cmpdi(CCR0, tmp, mainLoop_stepping);
3266       blt(CCR0, L_tail);                         // For less than one mainloop_stepping left, do only tail processing
3267       mr(len, tmp);                              // remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
3268     }
3269     update_byteLoop_crc32(crc, buf, tmp2, table, data, false, false);
3270   }
3271 
3272   srdi(tmp2, len, log_stepping);                 // #iterations for mainLoop
3273   andi(len, len, mainLoop_stepping-1);           // remaining bytes for tailLoop
3274   mtctr(tmp2);
3275 
3276 #ifdef VM_LITTLE_ENDIAN
3277   Register crc_rv = crc;
3278 #else
3279   Register crc_rv = tmp;                         // Load_reverse needs separate registers to work on.
3280                                                  // Occupies tmp, but frees up crc.
3281   load_reverse_32(crc_rv, crc);                  // Revert byte order because we are dealing with big-endian data.
3282   tmp = crc;
3283 #endif
3284 
3285   int reconstructTableOffset = crc32_table_columns(table, tc0, tc1, tc2, tc3);
3286 
3287   align(mainLoop_alignment);                     // Octoword-aligned loop address. Shows 2% improvement.
3288   BIND(L_mainLoop);
3289     update_1word_crc32(crc_rv, buf, table, 0, 0, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
3290     update_1word_crc32(crc_rv, buf, table, 4, mainLoop_stepping, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
3291     bdnz(L_mainLoop);
3292 
3293 #ifndef VM_LITTLE_ENDIAN
3294   load_reverse_32(crc, crc_rv);                  // Revert byte order because we are dealing with big-endian data.
3295   tmp = crc_rv;                                  // Tmp uses it's original register again.
3296 #endif
3297 
3298   // Restore original table address for tailLoop.
3299   if (reconstructTableOffset != 0) {
3300     addi(table, table, -reconstructTableOffset);
3301   }
3302 
3303   // Process last few (<complexThreshold) bytes of buffer.
3304   BIND(L_tail);
3305   update_byteLoop_crc32(crc, buf, len, table, data, false, false);
3306 
3307   nand(crc, crc, crc);                           // ~c
3308   BLOCK_COMMENT("} kernel_crc32_2word");
3309 }
3310 
3311 /**
3312  * @param crc   register containing existing CRC (32-bit)
3313  * @param buf   register pointing to input byte buffer (byte*)
3314  * @param len   register containing number of bytes
3315  * @param table register pointing to CRC table
3316  *
3317  * uses R9..R12 as work register. Must be saved/restored by caller!
3318  */
3319 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
3320                                         Register t0,  Register t1,  Register t2,  Register t3,
3321                                         Register tc0, Register tc1, Register tc2, Register tc3) {
3322   assert_different_registers(crc, buf, len, table);
3323 
3324   Label L_mainLoop, L_tail;
3325   Register  tmp          = t0;
3326   Register  data         = t0;
3327   Register  tmp2         = t1;
3328   const int mainLoop_stepping  = 4;
3329   const int tailLoop_stepping  = 1;
3330   const int log_stepping       = exact_log2(mainLoop_stepping);
3331   const int mainLoop_alignment = 32; // InputForNewCode > 4 ? InputForNewCode : 32;
3332   const int complexThreshold   = 2*mainLoop_stepping;
3333 
3334   // Don't test for len <= 0 here. This pathological case should not occur anyway.
3335   // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
3336   // The situation itself is detected and handled correctly by the conditional branches
3337   // following  aghi(len, -stepping) and aghi(len, +stepping).
3338   assert(tailLoop_stepping == 1, "check tailLoop_stepping!");
3339 
3340   BLOCK_COMMENT("kernel_crc32_1word {");
3341 
3342   nand(crc, crc, crc);                           // ~c
3343 
3344   // Check for short (<mainLoop_stepping) buffer.
3345   cmpdi(CCR0, len, complexThreshold);
3346   blt(CCR0, L_tail);
3347 
3348   // Pre-mainLoop alignment did show a slight (1%) positive effect on performance.
3349   // We leave the code in for reference. Maybe we need alignment when we exploit vector instructions.
3350   {
3351     // Align buf addr to mainLoop_stepping boundary.
3352     neg(tmp2, buf);                              // Calculate # preLoop iterations for alignment.
3353     rldicl(tmp2, tmp2, 0, 64-log_stepping);      // Rotate tmp2 0 bits, insert into tmp2, anding with mask with 1s from 62..63.
3354 
3355     if (complexThreshold > mainLoop_stepping) {
3356       sub(len, len, tmp2);                       // Remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
3357     } else {
3358       sub(tmp, len, tmp2);                       // Remaining bytes for main loop.
3359       cmpdi(CCR0, tmp, mainLoop_stepping);
3360       blt(CCR0, L_tail);                         // For less than one mainloop_stepping left, do only tail processing
3361       mr(len, tmp);                              // remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
3362     }
3363     update_byteLoop_crc32(crc, buf, tmp2, table, data, false, false);
3364   }
3365 
3366   srdi(tmp2, len, log_stepping);                 // #iterations for mainLoop
3367   andi(len, len, mainLoop_stepping-1);           // remaining bytes for tailLoop
3368   mtctr(tmp2);
3369 
3370 #ifdef VM_LITTLE_ENDIAN
3371   Register crc_rv = crc;
3372 #else
3373   Register crc_rv = tmp;                         // Load_reverse needs separate registers to work on.
3374                                                  // Occupies tmp, but frees up crc.
3375   load_reverse_32(crc_rv, crc);                  // evert byte order because we are dealing with big-endian data.
3376   tmp = crc;
3377 #endif
3378 
3379   int reconstructTableOffset = crc32_table_columns(table, tc0, tc1, tc2, tc3);
3380 
3381   align(mainLoop_alignment);                     // Octoword-aligned loop address. Shows 2% improvement.
3382   BIND(L_mainLoop);
3383     update_1word_crc32(crc_rv, buf, table, 0, mainLoop_stepping, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
3384     bdnz(L_mainLoop);
3385 
3386 #ifndef VM_LITTLE_ENDIAN
3387   load_reverse_32(crc, crc_rv);                  // Revert byte order because we are dealing with big-endian data.
3388   tmp = crc_rv;                                  // Tmp uses it's original register again.
3389 #endif
3390 
3391   // Restore original table address for tailLoop.
3392   if (reconstructTableOffset != 0) {
3393     addi(table, table, -reconstructTableOffset);
3394   }
3395 
3396   // Process last few (<complexThreshold) bytes of buffer.
3397   BIND(L_tail);
3398   update_byteLoop_crc32(crc, buf, len, table, data, false, false);
3399 
3400   nand(crc, crc, crc);                           // ~c
3401   BLOCK_COMMENT("} kernel_crc32_1word");
3402 }
3403 
3404 /**
3405  * @param crc   register containing existing CRC (32-bit)
3406  * @param buf   register pointing to input byte buffer (byte*)
3407  * @param len   register containing number of bytes
3408  * @param table register pointing to CRC table
3409  *
3410  * Uses R7_ARG5, R8_ARG6 as work registers.
3411  */
3412 void MacroAssembler::kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
3413                                         Register t0,  Register t1,  Register t2,  Register t3) {
3414   assert_different_registers(crc, buf, len, table);
3415 
3416   Register  data = t0;                   // Holds the current byte to be folded into crc.
3417 
3418   BLOCK_COMMENT("kernel_crc32_1byte {");
3419 
3420   // Process all bytes in a single-byte loop.
3421   update_byteLoop_crc32(crc, buf, len, table, data, true, true);
3422 
3423   BLOCK_COMMENT("} kernel_crc32_1byte");
3424 }
3425 
3426 /**
3427  * @param crc             register containing existing CRC (32-bit)
3428  * @param buf             register pointing to input byte buffer (byte*)
3429  * @param len             register containing number of bytes
3430  * @param table           register pointing to CRC table
3431  * @param constants       register pointing to CRC table for 128-bit aligned memory
3432  * @param barretConstants register pointing to table for barrett reduction
3433  * @param t0              volatile register
3434  * @param t1              volatile register
3435  * @param t2              volatile register
3436  * @param t3              volatile register
3437  */
3438 void MacroAssembler::kernel_crc32_1word_vpmsumd(Register crc, Register buf, Register len, Register table,
3439                         Register constants,  Register barretConstants,
3440                         Register t0,  Register t1, Register t2, Register t3, Register t4) {
3441   assert_different_registers(crc, buf, len, table);
3442 
3443   Label L_alignedHead, L_tail, L_alignTail, L_start, L_end;
3444 
3445   Register  prealign     = t0;
3446   Register  postalign    = t0;
3447 
3448   BLOCK_COMMENT("kernel_crc32_1word_vpmsumb {");
3449 
3450   // 1. use kernel_crc32_1word for shorter than 384bit
3451   clrldi(len, len, 32);
3452   cmpdi(CCR0, len, 384);
3453   bge(CCR0, L_start);
3454 
3455     Register tc0 = t4;
3456     Register tc1 = constants;
3457     Register tc2 = barretConstants;
3458     kernel_crc32_1word(crc, buf, len, table,t0, t1, t2, t3, tc0, tc1, tc2, table);
3459     b(L_end);
3460 
3461   BIND(L_start);
3462 
3463     // 2. ~c
3464     nand(crc, crc, crc);
3465 
3466     // 3. calculate from 0 to first 128bit-aligned address
3467     clrldi_(prealign, buf, 57);
3468     beq(CCR0, L_alignedHead);
3469 
3470     subfic(prealign, prealign, 128);
3471 
3472     subf(len, prealign, len);
3473     update_byteLoop_crc32(crc, buf, prealign, table, t2, false, false);
3474 
3475     // 4. calculate from first 128bit-aligned address to last 128bit-aligned address
3476     BIND(L_alignedHead);
3477 
3478     clrldi(postalign, len, 57);
3479     subf(len, postalign, len);
3480 
3481     // len must be more than 256bit
3482     kernel_crc32_1word_aligned(crc, buf, len, constants, barretConstants, t1, t2, t3);
3483 
3484     // 5. calculate remaining
3485     cmpdi(CCR0, postalign, 0);
3486     beq(CCR0, L_tail);
3487 
3488     update_byteLoop_crc32(crc, buf, postalign, table, t2, false, false);
3489 
3490     BIND(L_tail);
3491 
3492     // 6. ~c
3493     nand(crc, crc, crc);
3494 
3495   BIND(L_end);
3496 
3497   BLOCK_COMMENT("} kernel_crc32_1word_vpmsumb");
3498 }
3499 
3500 /**
3501  * @param crc             register containing existing CRC (32-bit)
3502  * @param buf             register pointing to input byte buffer (byte*)
3503  * @param len             register containing number of bytes
3504  * @param constants       register pointing to CRC table for 128-bit aligned memory
3505  * @param barretConstants register pointing to table for barrett reduction
3506  * @param t0              volatile register
3507  * @param t1              volatile register
3508  * @param t2              volatile register
3509  */
3510 void MacroAssembler::kernel_crc32_1word_aligned(Register crc, Register buf, Register len,
3511     Register constants, Register barretConstants, Register t0, Register t1, Register t2) {
3512   Label L_mainLoop, L_tail, L_alignTail, L_barrett_reduction, L_end, L_first_warm_up_done, L_first_cool_down, L_second_cool_down, L_XOR, L_test;
3513   Label L_lv0, L_lv1, L_lv2, L_lv3, L_lv4, L_lv5, L_lv6, L_lv7, L_lv8, L_lv9, L_lv10, L_lv11, L_lv12, L_lv13, L_lv14, L_lv15;
3514   Label L_1, L_2, L_3, L_4;
3515 
3516   Register  rLoaded      = t0;
3517   Register  rTmp1        = t1;
3518   Register  rTmp2        = t2;
3519   Register  off16        = R22;
3520   Register  off32        = R23;
3521   Register  off48        = R24;
3522   Register  off64        = R25;
3523   Register  off80        = R26;
3524   Register  off96        = R27;
3525   Register  off112       = R28;
3526   Register  rIdx         = R29;
3527   Register  rMax         = R30;
3528   Register  constantsPos = R31;
3529 
3530   VectorRegister mask_32bit = VR24;
3531   VectorRegister mask_64bit = VR25;
3532   VectorRegister zeroes     = VR26;
3533   VectorRegister const1     = VR27;
3534   VectorRegister const2     = VR28;
3535 
3536   // Save non-volatile vector registers (frameless).
3537   Register offset = t1;   int offsetInt = 0;
3538   offsetInt -= 16; li(offset, -16);           stvx(VR20, offset, R1_SP);
3539   offsetInt -= 16; addi(offset, offset, -16); stvx(VR21, offset, R1_SP);
3540   offsetInt -= 16; addi(offset, offset, -16); stvx(VR22, offset, R1_SP);
3541   offsetInt -= 16; addi(offset, offset, -16); stvx(VR23, offset, R1_SP);
3542   offsetInt -= 16; addi(offset, offset, -16); stvx(VR24, offset, R1_SP);
3543   offsetInt -= 16; addi(offset, offset, -16); stvx(VR25, offset, R1_SP);
3544   offsetInt -= 16; addi(offset, offset, -16); stvx(VR26, offset, R1_SP);
3545   offsetInt -= 16; addi(offset, offset, -16); stvx(VR27, offset, R1_SP);
3546   offsetInt -= 16; addi(offset, offset, -16); stvx(VR28, offset, R1_SP);
3547   offsetInt -= 8; std(R22, offsetInt, R1_SP);
3548   offsetInt -= 8; std(R23, offsetInt, R1_SP);
3549   offsetInt -= 8; std(R24, offsetInt, R1_SP);
3550   offsetInt -= 8; std(R25, offsetInt, R1_SP);
3551   offsetInt -= 8; std(R26, offsetInt, R1_SP);
3552   offsetInt -= 8; std(R27, offsetInt, R1_SP);
3553   offsetInt -= 8; std(R28, offsetInt, R1_SP);
3554   offsetInt -= 8; std(R29, offsetInt, R1_SP);
3555   offsetInt -= 8; std(R30, offsetInt, R1_SP);
3556   offsetInt -= 8; std(R31, offsetInt, R1_SP);
3557 
3558   // Set constants
3559   li(off16, 16);
3560   li(off32, 32);
3561   li(off48, 48);
3562   li(off64, 64);
3563   li(off80, 80);
3564   li(off96, 96);
3565   li(off112, 112);
3566 
3567   clrldi(crc, crc, 32);
3568 
3569   vxor(zeroes, zeroes, zeroes);
3570   vspltisw(VR0, -1);
3571 
3572   vsldoi(mask_32bit, zeroes, VR0, 4);
3573   vsldoi(mask_64bit, zeroes, VR0, 8);
3574 
3575   // Get the initial value into v8
3576   vxor(VR8, VR8, VR8);
3577   mtvrd(VR8, crc);
3578   vsldoi(VR8, zeroes, VR8, 8); // shift into bottom 32 bits
3579 
3580   li (rLoaded, 0);
3581 
3582   rldicr(rIdx, len, 0, 56);
3583 
3584   {
3585     BIND(L_1);
3586     // Checksum in blocks of MAX_SIZE (32768)
3587     lis(rMax, 0);
3588     ori(rMax, rMax, 32768);
3589     mr(rTmp2, rMax);
3590     cmpd(CCR0, rIdx, rMax);
3591     bgt(CCR0, L_2);
3592     mr(rMax, rIdx);
3593 
3594     BIND(L_2);
3595     subf(rIdx, rMax, rIdx);
3596 
3597     // our main loop does 128 bytes at a time
3598     srdi(rMax, rMax, 7);
3599 
3600     /*
3601      * Work out the offset into the constants table to start at. Each
3602      * constant is 16 bytes, and it is used against 128 bytes of input
3603      * data - 128 / 16 = 8
3604      */
3605     sldi(rTmp1, rMax, 4);
3606     srdi(rTmp2, rTmp2, 3);
3607     subf(rTmp1, rTmp1, rTmp2);
3608 
3609     // We reduce our final 128 bytes in a separate step
3610     addi(rMax, rMax, -1);
3611     mtctr(rMax);
3612 
3613     // Find the start of our constants
3614     add(constantsPos, constants, rTmp1);
3615 
3616     // zero VR0-v7 which will contain our checksums
3617     vxor(VR0, VR0, VR0);
3618     vxor(VR1, VR1, VR1);
3619     vxor(VR2, VR2, VR2);
3620     vxor(VR3, VR3, VR3);
3621     vxor(VR4, VR4, VR4);
3622     vxor(VR5, VR5, VR5);
3623     vxor(VR6, VR6, VR6);
3624     vxor(VR7, VR7, VR7);
3625 
3626     lvx(const1, constantsPos);
3627 
3628     /*
3629      * If we are looping back to consume more data we use the values
3630      * already in VR16-v23.
3631      */
3632     cmpdi(CCR0, rLoaded, 1);
3633     beq(CCR0, L_3);
3634     {
3635 
3636       // First warm up pass
3637       lvx(VR16, buf);
3638       lvx(VR17, off16, buf);
3639       lvx(VR18, off32, buf);
3640       lvx(VR19, off48, buf);
3641       lvx(VR20, off64, buf);
3642       lvx(VR21, off80, buf);
3643       lvx(VR22, off96, buf);
3644       lvx(VR23, off112, buf);
3645       addi(buf, buf, 8*16);
3646 
3647       // xor in initial value
3648       vxor(VR16, VR16, VR8);
3649     }
3650 
3651     BIND(L_3);
3652     bdz(L_first_warm_up_done);
3653 
3654     addi(constantsPos, constantsPos, 16);
3655     lvx(const2, constantsPos);
3656 
3657     // Second warm up pass
3658     vpmsumd(VR8, VR16, const1);
3659     lvx(VR16, buf);
3660 
3661     vpmsumd(VR9, VR17, const1);
3662     lvx(VR17, off16, buf);
3663 
3664     vpmsumd(VR10, VR18, const1);
3665     lvx(VR18, off32, buf);
3666 
3667     vpmsumd(VR11, VR19, const1);
3668     lvx(VR19, off48, buf);
3669 
3670     vpmsumd(VR12, VR20, const1);
3671     lvx(VR20, off64, buf);
3672 
3673     vpmsumd(VR13, VR21, const1);
3674     lvx(VR21, off80, buf);
3675 
3676     vpmsumd(VR14, VR22, const1);
3677     lvx(VR22, off96, buf);
3678 
3679     vpmsumd(VR15, VR23, const1);
3680     lvx(VR23, off112, buf);
3681 
3682     addi(buf, buf, 8 * 16);
3683 
3684     bdz(L_first_cool_down);
3685 
3686     /*
3687      * main loop. We modulo schedule it such that it takes three iterations
3688      * to complete - first iteration load, second iteration vpmsum, third
3689      * iteration xor.
3690      */
3691     {
3692       BIND(L_4);
3693       lvx(const1, constantsPos); addi(constantsPos, constantsPos, 16);
3694 
3695       vxor(VR0, VR0, VR8);
3696       vpmsumd(VR8, VR16, const2);
3697       lvx(VR16, buf);
3698 
3699       vxor(VR1, VR1, VR9);
3700       vpmsumd(VR9, VR17, const2);
3701       lvx(VR17, off16, buf);
3702 
3703       vxor(VR2, VR2, VR10);
3704       vpmsumd(VR10, VR18, const2);
3705       lvx(VR18, off32, buf);
3706 
3707       vxor(VR3, VR3, VR11);
3708       vpmsumd(VR11, VR19, const2);
3709       lvx(VR19, off48, buf);
3710       lvx(const2, constantsPos);
3711 
3712       vxor(VR4, VR4, VR12);
3713       vpmsumd(VR12, VR20, const1);
3714       lvx(VR20, off64, buf);
3715 
3716       vxor(VR5, VR5, VR13);
3717       vpmsumd(VR13, VR21, const1);
3718       lvx(VR21, off80, buf);
3719 
3720       vxor(VR6, VR6, VR14);
3721       vpmsumd(VR14, VR22, const1);
3722       lvx(VR22, off96, buf);
3723 
3724       vxor(VR7, VR7, VR15);
3725       vpmsumd(VR15, VR23, const1);
3726       lvx(VR23, off112, buf);
3727 
3728       addi(buf, buf, 8 * 16);
3729 
3730       bdnz(L_4);
3731     }
3732 
3733     BIND(L_first_cool_down);
3734 
3735     // First cool down pass
3736     lvx(const1, constantsPos);
3737     addi(constantsPos, constantsPos, 16);
3738 
3739     vxor(VR0, VR0, VR8);
3740     vpmsumd(VR8, VR16, const1);
3741 
3742     vxor(VR1, VR1, VR9);
3743     vpmsumd(VR9, VR17, const1);
3744 
3745     vxor(VR2, VR2, VR10);
3746     vpmsumd(VR10, VR18, const1);
3747 
3748     vxor(VR3, VR3, VR11);
3749     vpmsumd(VR11, VR19, const1);
3750 
3751     vxor(VR4, VR4, VR12);
3752     vpmsumd(VR12, VR20, const1);
3753 
3754     vxor(VR5, VR5, VR13);
3755     vpmsumd(VR13, VR21, const1);
3756 
3757     vxor(VR6, VR6, VR14);
3758     vpmsumd(VR14, VR22, const1);
3759 
3760     vxor(VR7, VR7, VR15);
3761     vpmsumd(VR15, VR23, const1);
3762 
3763     BIND(L_second_cool_down);
3764     // Second cool down pass
3765     vxor(VR0, VR0, VR8);
3766     vxor(VR1, VR1, VR9);
3767     vxor(VR2, VR2, VR10);
3768     vxor(VR3, VR3, VR11);
3769     vxor(VR4, VR4, VR12);
3770     vxor(VR5, VR5, VR13);
3771     vxor(VR6, VR6, VR14);
3772     vxor(VR7, VR7, VR15);
3773 
3774     /*
3775      * vpmsumd produces a 96 bit result in the least significant bits
3776      * of the register. Since we are bit reflected we have to shift it
3777      * left 32 bits so it occupies the least significant bits in the
3778      * bit reflected domain.
3779      */
3780     vsldoi(VR0, VR0, zeroes, 4);
3781     vsldoi(VR1, VR1, zeroes, 4);
3782     vsldoi(VR2, VR2, zeroes, 4);
3783     vsldoi(VR3, VR3, zeroes, 4);
3784     vsldoi(VR4, VR4, zeroes, 4);
3785     vsldoi(VR5, VR5, zeroes, 4);
3786     vsldoi(VR6, VR6, zeroes, 4);
3787     vsldoi(VR7, VR7, zeroes, 4);
3788 
3789     // xor with last 1024 bits
3790     lvx(VR8, buf);
3791     lvx(VR9, off16, buf);
3792     lvx(VR10, off32, buf);
3793     lvx(VR11, off48, buf);
3794     lvx(VR12, off64, buf);
3795     lvx(VR13, off80, buf);
3796     lvx(VR14, off96, buf);
3797     lvx(VR15, off112, buf);
3798     addi(buf, buf, 8 * 16);
3799 
3800     vxor(VR16, VR0, VR8);
3801     vxor(VR17, VR1, VR9);
3802     vxor(VR18, VR2, VR10);
3803     vxor(VR19, VR3, VR11);
3804     vxor(VR20, VR4, VR12);
3805     vxor(VR21, VR5, VR13);
3806     vxor(VR22, VR6, VR14);
3807     vxor(VR23, VR7, VR15);
3808 
3809     li(rLoaded, 1);
3810     cmpdi(CCR0, rIdx, 0);
3811     addi(rIdx, rIdx, 128);
3812     bne(CCR0, L_1);
3813   }
3814 
3815   // Work out how many bytes we have left
3816   andi_(len, len, 127);
3817 
3818   // Calculate where in the constant table we need to start
3819   subfic(rTmp1, len, 128);
3820   add(constantsPos, constantsPos, rTmp1);
3821 
3822   // How many 16 byte chunks are in the tail
3823   srdi(rIdx, len, 4);
3824   mtctr(rIdx);
3825 
3826   /*
3827    * Reduce the previously calculated 1024 bits to 64 bits, shifting
3828    * 32 bits to include the trailing 32 bits of zeros
3829    */
3830   lvx(VR0, constantsPos);
3831   lvx(VR1, off16, constantsPos);
3832   lvx(VR2, off32, constantsPos);
3833   lvx(VR3, off48, constantsPos);
3834   lvx(VR4, off64, constantsPos);
3835   lvx(VR5, off80, constantsPos);
3836   lvx(VR6, off96, constantsPos);
3837   lvx(VR7, off112, constantsPos);
3838   addi(constantsPos, constantsPos, 8 * 16);
3839 
3840   vpmsumw(VR0, VR16, VR0);
3841   vpmsumw(VR1, VR17, VR1);
3842   vpmsumw(VR2, VR18, VR2);
3843   vpmsumw(VR3, VR19, VR3);
3844   vpmsumw(VR4, VR20, VR4);
3845   vpmsumw(VR5, VR21, VR5);
3846   vpmsumw(VR6, VR22, VR6);
3847   vpmsumw(VR7, VR23, VR7);
3848 
3849   // Now reduce the tail (0 - 112 bytes)
3850   cmpdi(CCR0, rIdx, 0);
3851   beq(CCR0, L_XOR);
3852 
3853   lvx(VR16, buf); addi(buf, buf, 16);
3854   lvx(VR17, constantsPos);
3855   vpmsumw(VR16, VR16, VR17);
3856   vxor(VR0, VR0, VR16);
3857   beq(CCR0, L_XOR);
3858 
3859   lvx(VR16, buf); addi(buf, buf, 16);
3860   lvx(VR17, off16, constantsPos);
3861   vpmsumw(VR16, VR16, VR17);
3862   vxor(VR0, VR0, VR16);
3863   beq(CCR0, L_XOR);
3864 
3865   lvx(VR16, buf); addi(buf, buf, 16);
3866   lvx(VR17, off32, constantsPos);
3867   vpmsumw(VR16, VR16, VR17);
3868   vxor(VR0, VR0, VR16);
3869   beq(CCR0, L_XOR);
3870 
3871   lvx(VR16, buf); addi(buf, buf, 16);
3872   lvx(VR17, off48,constantsPos);
3873   vpmsumw(VR16, VR16, VR17);
3874   vxor(VR0, VR0, VR16);
3875   beq(CCR0, L_XOR);
3876 
3877   lvx(VR16, buf); addi(buf, buf, 16);
3878   lvx(VR17, off64, constantsPos);
3879   vpmsumw(VR16, VR16, VR17);
3880   vxor(VR0, VR0, VR16);
3881   beq(CCR0, L_XOR);
3882 
3883   lvx(VR16, buf); addi(buf, buf, 16);
3884   lvx(VR17, off80, constantsPos);
3885   vpmsumw(VR16, VR16, VR17);
3886   vxor(VR0, VR0, VR16);
3887   beq(CCR0, L_XOR);
3888 
3889   lvx(VR16, buf); addi(buf, buf, 16);
3890   lvx(VR17, off96, constantsPos);
3891   vpmsumw(VR16, VR16, VR17);
3892   vxor(VR0, VR0, VR16);
3893 
3894   // Now xor all the parallel chunks together
3895   BIND(L_XOR);
3896   vxor(VR0, VR0, VR1);
3897   vxor(VR2, VR2, VR3);
3898   vxor(VR4, VR4, VR5);
3899   vxor(VR6, VR6, VR7);
3900 
3901   vxor(VR0, VR0, VR2);
3902   vxor(VR4, VR4, VR6);
3903 
3904   vxor(VR0, VR0, VR4);
3905 
3906   b(L_barrett_reduction);
3907 
3908   BIND(L_first_warm_up_done);
3909   lvx(const1, constantsPos);
3910   addi(constantsPos, constantsPos, 16);
3911   vpmsumd(VR8,  VR16, const1);
3912   vpmsumd(VR9,  VR17, const1);
3913   vpmsumd(VR10, VR18, const1);
3914   vpmsumd(VR11, VR19, const1);
3915   vpmsumd(VR12, VR20, const1);
3916   vpmsumd(VR13, VR21, const1);
3917   vpmsumd(VR14, VR22, const1);
3918   vpmsumd(VR15, VR23, const1);
3919   b(L_second_cool_down);
3920 
3921   BIND(L_barrett_reduction);
3922 
3923   lvx(const1, barretConstants);
3924   addi(barretConstants, barretConstants, 16);
3925   lvx(const2, barretConstants);
3926 
3927   vsldoi(VR1, VR0, VR0, 8);
3928   vxor(VR0, VR0, VR1);    // xor two 64 bit results together
3929 
3930   // shift left one bit
3931   vspltisb(VR1, 1);
3932   vsl(VR0, VR0, VR1);
3933 
3934   vand(VR0, VR0, mask_64bit);
3935 
3936   /*
3937    * The reflected version of Barrett reduction. Instead of bit
3938    * reflecting our data (which is expensive to do), we bit reflect our
3939    * constants and our algorithm, which means the intermediate data in
3940    * our vector registers goes from 0-63 instead of 63-0. We can reflect
3941    * the algorithm because we don't carry in mod 2 arithmetic.
3942    */
3943   vand(VR1, VR0, mask_32bit);  // bottom 32 bits of a
3944   vpmsumd(VR1, VR1, const1);   // ma
3945   vand(VR1, VR1, mask_32bit);  // bottom 32bits of ma
3946   vpmsumd(VR1, VR1, const2);   // qn */
3947   vxor(VR0, VR0, VR1);         // a - qn, subtraction is xor in GF(2)
3948 
3949   /*
3950    * Since we are bit reflected, the result (ie the low 32 bits) is in
3951    * the high 32 bits. We just need to shift it left 4 bytes
3952    * V0 [ 0 1 X 3 ]
3953    * V0 [ 0 X 2 3 ]
3954    */
3955   vsldoi(VR0, VR0, zeroes, 4);    // shift result into top 64 bits of
3956 
3957   // Get it into r3
3958   mfvrd(crc, VR0);
3959 
3960   BIND(L_end);
3961 
3962   offsetInt = 0;
3963   // Restore non-volatile Vector registers (frameless).
3964   offsetInt -= 16; li(offset, -16);           lvx(VR20, offset, R1_SP);
3965   offsetInt -= 16; addi(offset, offset, -16); lvx(VR21, offset, R1_SP);
3966   offsetInt -= 16; addi(offset, offset, -16); lvx(VR22, offset, R1_SP);
3967   offsetInt -= 16; addi(offset, offset, -16); lvx(VR23, offset, R1_SP);
3968   offsetInt -= 16; addi(offset, offset, -16); lvx(VR24, offset, R1_SP);
3969   offsetInt -= 16; addi(offset, offset, -16); lvx(VR25, offset, R1_SP);
3970   offsetInt -= 16; addi(offset, offset, -16); lvx(VR26, offset, R1_SP);
3971   offsetInt -= 16; addi(offset, offset, -16); lvx(VR27, offset, R1_SP);
3972   offsetInt -= 16; addi(offset, offset, -16); lvx(VR28, offset, R1_SP);
3973   offsetInt -= 8;  ld(R22, offsetInt, R1_SP);
3974   offsetInt -= 8;  ld(R23, offsetInt, R1_SP);
3975   offsetInt -= 8;  ld(R24, offsetInt, R1_SP);
3976   offsetInt -= 8;  ld(R25, offsetInt, R1_SP);
3977   offsetInt -= 8;  ld(R26, offsetInt, R1_SP);
3978   offsetInt -= 8;  ld(R27, offsetInt, R1_SP);
3979   offsetInt -= 8;  ld(R28, offsetInt, R1_SP);
3980   offsetInt -= 8;  ld(R29, offsetInt, R1_SP);
3981   offsetInt -= 8;  ld(R30, offsetInt, R1_SP);
3982   offsetInt -= 8;  ld(R31, offsetInt, R1_SP);
3983 }
3984 
3985 void MacroAssembler::kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp) {
3986   assert_different_registers(crc, buf, /* len,  not used!! */ table, tmp);
3987 
3988   BLOCK_COMMENT("kernel_crc32_singleByte:");
3989   nand(crc, crc, crc);       // ~c
3990 
3991   lbz(tmp, 0, buf);          // Byte from buffer, zero-extended.
3992   update_byte_crc32(crc, tmp, table);
3993 
3994   nand(crc, crc, crc);       // ~c
3995 }
3996 
3997 
3998 void MacroAssembler::asm_assert(bool check_equal, const char *msg, int id) {
3999 #ifdef ASSERT
4000   Label ok;
4001   if (check_equal) {
4002     beq(CCR0, ok);
4003   } else {
4004     bne(CCR0, ok);
4005   }
4006   stop(msg, id);
4007   bind(ok);
4008 #endif
4009 }
4010 
4011 void MacroAssembler::asm_assert_mems_zero(bool check_equal, int size, int mem_offset,
4012                                           Register mem_base, const char* msg, int id) {
4013 #ifdef ASSERT
4014   switch (size) {
4015     case 4:
4016       lwz(R0, mem_offset, mem_base);
4017       cmpwi(CCR0, R0, 0);
4018       break;
4019     case 8:
4020       ld(R0, mem_offset, mem_base);
4021       cmpdi(CCR0, R0, 0);
4022       break;
4023     default:
4024       ShouldNotReachHere();
4025   }
4026   asm_assert(check_equal, msg, id);
4027 #endif // ASSERT
4028 }
4029 
4030 void MacroAssembler::verify_thread() {
4031   if (VerifyThread) {
4032     unimplemented("'VerifyThread' currently not implemented on PPC");
4033   }
4034 }
4035 
4036 // READ: oop. KILL: R0. Volatile floats perhaps.
4037 void MacroAssembler::verify_oop(Register oop, const char* msg) {
4038   if (!VerifyOops) {
4039     return;
4040   }
4041 
4042   address/* FunctionDescriptor** */fd = StubRoutines::verify_oop_subroutine_entry_address();
4043   const Register tmp = R11; // Will be preserved.
4044   const int nbytes_save = 11*8; // Volatile gprs except R0.
4045   save_volatile_gprs(R1_SP, -nbytes_save); // except R0
4046 
4047   if (oop == tmp) mr(R4_ARG2, oop);
4048   save_LR_CR(tmp); // save in old frame
4049   push_frame_reg_args(nbytes_save, tmp);
4050   // load FunctionDescriptor** / entry_address *
4051   load_const_optimized(tmp, fd, R0);
4052   // load FunctionDescriptor* / entry_address
4053   ld(tmp, 0, tmp);
4054   if (oop != tmp) mr_if_needed(R4_ARG2, oop);
4055   load_const_optimized(R3_ARG1, (address)msg, R0);
4056   // Call destination for its side effect.
4057   call_c(tmp);
4058 
4059   pop_frame();
4060   restore_LR_CR(tmp);
4061   restore_volatile_gprs(R1_SP, -nbytes_save); // except R0
4062 }
4063 
4064 const char* stop_types[] = {
4065   "stop",
4066   "untested",
4067   "unimplemented",
4068   "shouldnotreachhere"
4069 };
4070 
4071 static void stop_on_request(int tp, const char* msg) {
4072   tty->print("PPC assembly code requires stop: (%s) %s\n", stop_types[tp%/*stop_end*/4], msg);
4073   guarantee(false, err_msg("PPC assembly code requires stop: %s", msg));
4074 }
4075 
4076 // Call a C-function that prints output.
4077 void MacroAssembler::stop(int type, const char* msg, int id) {
4078 #ifndef PRODUCT
4079   block_comment(err_msg("stop: %s %s {", stop_types[type%stop_end], msg));
4080 #else
4081   block_comment("stop {");
4082 #endif
4083 
4084   // setup arguments
4085   load_const_optimized(R3_ARG1, type);
4086   load_const_optimized(R4_ARG2, (void *)msg, /*tmp=*/R0);
4087   call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), R3_ARG1, R4_ARG2);
4088   illtrap();
4089   emit_int32(id);
4090   block_comment("} stop;");
4091 }
4092 
4093 #ifndef PRODUCT
4094 // Write pattern 0x0101010101010101 in memory region [low-before, high+after].
4095 // Val, addr are temp registers.
4096 // If low == addr, addr is killed.
4097 // High is preserved.
4098 void MacroAssembler::zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) {
4099   if (!ZapMemory) return;
4100 
4101   assert_different_registers(low, val);
4102 
4103   BLOCK_COMMENT("zap memory region {");
4104   load_const_optimized(val, 0x0101010101010101);
4105   int size = before + after;
4106   if (low == high && size < 5 && size > 0) {
4107     int offset = -before*BytesPerWord;
4108     for (int i = 0; i < size; ++i) {
4109       std(val, offset, low);
4110       offset += (1*BytesPerWord);
4111     }
4112   } else {
4113     addi(addr, low, -before*BytesPerWord);
4114     assert_different_registers(high, val);
4115     if (after) addi(high, high, after * BytesPerWord);
4116     Label loop;
4117     bind(loop);
4118     std(val, 0, addr);
4119     addi(addr, addr, 8);
4120     cmpd(CCR6, addr, high);
4121     ble(CCR6, loop);
4122     if (after) addi(high, high, -after * BytesPerWord);  // Correct back to old value.
4123   }
4124   BLOCK_COMMENT("} zap memory region");
4125 }
4126 
4127 #endif // !PRODUCT
4128 
4129 SkipIfEqualZero::SkipIfEqualZero(MacroAssembler* masm, Register temp, const bool* flag_addr) : _masm(masm), _label() {
4130   int simm16_offset = masm->load_const_optimized(temp, (address)flag_addr, R0, true);
4131   assert(sizeof(bool) == 1, "PowerPC ABI");
4132   masm->lbz(temp, simm16_offset, temp);
4133   masm->cmpwi(CCR0, temp, 0);
4134   masm->beq(CCR0, _label);
4135 }
4136 
4137 SkipIfEqualZero::~SkipIfEqualZero() {
4138   _masm->bind(_label);
4139 }