1 /*
2 * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_VM_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_VM_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by a few frequently used macros.
32
33 class ciTypeArray;
34
35 class MacroAssembler: public Assembler {
36 public:
37 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
38
39 //
40 // Optimized instruction emitters
41 //
42
43 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
44 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
45
46 // load d = *[a+si31]
47 // Emits several instructions if the offset is not encodable in one instruction.
48 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
49 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
50 inline static bool is_ld_largeoffset(address a);
51 inline static int get_ld_largeoffset_offset(address a);
52
53 inline void round_to(Register r, int modulus);
54
55 // Load/store with type given by parameter.
56 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
57 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
58
59 // Move register if destination register and target register are different
60 inline void mr_if_needed(Register rd, Register rs);
61 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
62 // This is dedicated for emitting scheduled mach nodes. For better
63 // readability of the ad file I put it here.
64 // Endgroups are not needed if
65 // - the scheduler is off
66 // - the scheduler found that there is a natural group end, in that
67 // case it reduced the size of the instruction used in the test
68 // yielding 'needed'.
69 inline void endgroup_if_needed(bool needed);
70
71 // Memory barriers.
72 inline void membar(int bits);
73 inline void release();
74 inline void acquire();
75 inline void fence();
76
77 // nop padding
78 void align(int modulus, int max = 252, int rem = 0);
79
80 //
81 // Constants, loading constants, TOC support
82 //
83
84 // Address of the global TOC.
85 inline static address global_toc();
86 // Offset of given address to the global TOC.
87 inline static int offset_to_global_toc(const address addr);
88
89 // Address of TOC of the current method.
90 inline address method_toc();
91 // Offset of given address to TOC of the current method.
92 inline int offset_to_method_toc(const address addr);
93
94 // Global TOC.
95 void calculate_address_from_global_toc(Register dst, address addr,
96 bool hi16 = true, bool lo16 = true,
97 bool add_relocation = true, bool emit_dummy_addr = false);
98 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
99 calculate_address_from_global_toc(dst, addr, true, false);
100 };
101 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
102 calculate_address_from_global_toc(dst, addr, false, true);
103 };
104
105 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
106 static int patch_calculate_address_from_global_toc_at(address a, address addr, address bound);
107 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
108
109 #ifdef _LP64
110 // Patch narrow oop constant.
111 inline static bool is_set_narrow_oop(address a, address bound);
112 static int patch_set_narrow_oop(address a, address bound, narrowOop data);
113 static narrowOop get_narrow_oop(address a, address bound);
114 #endif
115
116 inline static bool is_load_const_at(address a);
117
118 // Emits an oop const to the constant pool, loads the constant, and
119 // sets a relocation info with address current_pc.
120 void load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc);
121 void load_toc_from_toc(Register dst, AddressLiteral& a, Register toc) {
122 assert(dst == R2_TOC, "base register must be TOC");
123 load_const_from_method_toc(dst, a, toc);
124 }
125
126 static bool is_load_const_from_method_toc_at(address a);
127 static int get_offset_of_load_const_from_method_toc_at(address a);
128
129 // Get the 64 bit constant from a `load_const' sequence.
130 static long get_const(address load_const);
131
132 // Patch the 64 bit constant of a `load_const' sequence. This is a
133 // low level procedure. It neither flushes the instruction cache nor
134 // is it atomic.
135 static void patch_const(address load_const, long x);
136
137 // Metadata in code that we have to keep track of.
138 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
139 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
140 // Oops used directly in compiled code are stored in the constant pool,
141 // and loaded from there.
142 // Allocate new entry for oop in constant pool. Generate relocation.
143 AddressLiteral allocate_oop_address(jobject obj);
144 // Find oop obj in constant pool. Return relocation with it's index.
145 AddressLiteral constant_oop_address(jobject obj);
146
147 // Find oop in constant pool and emit instructions to load it.
148 // Uses constant_oop_address.
149 inline void set_oop_constant(jobject obj, Register d);
150 // Same as load_address.
151 inline void set_oop (AddressLiteral obj_addr, Register d);
152
153 // Read runtime constant: Issue load if constant not yet established,
154 // else use real constant.
155 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
156 Register tmp,
157 int offset);
158
159 //
160 // branch, jump
161 //
162
163 inline void pd_patch_instruction(address branch, address target);
164 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
165
166 // Conditional far branch for destinations encodable in 24+2 bits.
167 // Same interface as bc, e.g. no inverse boint-field.
168 enum {
169 bc_far_optimize_not = 0,
170 bc_far_optimize_on_relocate = 1
171 };
172 // optimize: flag for telling the conditional far branch to optimize
173 // itself when relocated.
174 void bc_far(int boint, int biint, Label& dest, int optimize);
175 // Relocation of conditional far branches.
176 static bool is_bc_far_at(address instruction_addr);
177 static address get_dest_of_bc_far_at(address instruction_addr);
178 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
179 private:
180 static bool inline is_bc_far_variant1_at(address instruction_addr);
181 static bool inline is_bc_far_variant2_at(address instruction_addr);
182 static bool inline is_bc_far_variant3_at(address instruction_addr);
183 public:
184
185 // Convenience bc_far versions.
186 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
187 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
188 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
189 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
190 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
191 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
192 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
193 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
194
195 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
196 private:
197 enum {
198 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
199 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
200 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
201 };
202 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
203 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
204 // Does the instruction use a pc-relative encoding of the destination?
205 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
206 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
207 // Load destination relative to global toc.
208 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
209 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
210 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
211 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
212
213 public:
214 // call
215 enum {
216 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
217 bl64_patchable_size = bxx64_patchable_size,
218 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
219 };
220 inline void bl64_patchable(address target, relocInfo::relocType rt) {
221 bxx64_patchable(target, rt, /*link=*/true);
222 }
223 inline static bool is_bl64_patchable_at(address instruction_addr) {
224 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
225 }
226 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
227 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
228 }
229 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
230 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
231 }
232 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
233 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
234 }
235 // jump
236 enum {
237 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
238 b64_patchable_size = bxx64_patchable_size,
239 };
240 inline void b64_patchable(address target, relocInfo::relocType rt) {
241 bxx64_patchable(target, rt, /*link=*/false);
242 }
243 inline static bool is_b64_patchable_at(address instruction_addr) {
244 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
245 }
246 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
247 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
248 }
249 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
250 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
251 }
252 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
253 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
254 }
255
256 //
257 // Support for frame handling
258 //
259
260 // some ABI-related functions
261 void save_nonvolatile_gprs( Register dst_base, int offset);
262 void restore_nonvolatile_gprs(Register src_base, int offset);
263 void save_volatile_gprs( Register dst_base, int offset);
264 void restore_volatile_gprs(Register src_base, int offset);
265 void save_LR_CR( Register tmp); // tmp contains LR on return.
266 void restore_LR_CR(Register tmp);
267
268 // Get current PC using bl-next-instruction trick.
269 address get_PC_trash_LR(Register result);
270
271 // Resize current frame either relatively wrt to current SP or absolute.
272 void resize_frame(Register offset, Register tmp);
273 void resize_frame(int offset, Register tmp);
274 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
275
276 // Push a frame of size bytes.
277 void push_frame(Register bytes, Register tmp);
278
279 // Push a frame of size `bytes'. No abi space provided.
280 void push_frame(unsigned int bytes, Register tmp);
281
282 // Push a frame of size `bytes' plus abi_reg_args on top.
283 void push_frame_reg_args(unsigned int bytes, Register tmp);
284
285 // Setup up a new C frame with a spill area for non-volatile GPRs and additional
286 // space for local variables
287 void push_frame_reg_args_nonvolatiles(unsigned int bytes, Register tmp);
288
289 // pop current C frame
290 void pop_frame();
291
292 //
293 // Calls
294 //
295
296 private:
297 address _last_calls_return_pc;
298
299 #if defined(ABI_ELFv2)
300 // Generic version of a call to C function.
301 // Updates and returns _last_calls_return_pc.
302 address branch_to(Register function_entry, bool and_link);
303 #else
304 // Generic version of a call to C function via a function descriptor
305 // with variable support for C calling conventions (TOC, ENV, etc.).
306 // updates and returns _last_calls_return_pc.
307 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
308 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
309 #endif
310
311 public:
312
313 // Get the pc where the last call will return to. returns _last_calls_return_pc.
314 inline address last_calls_return_pc();
315
316 #if defined(ABI_ELFv2)
317 // Call a C function via a function descriptor and use full C
318 // calling conventions. Updates and returns _last_calls_return_pc.
319 address call_c(Register function_entry);
320 // For tail calls: only branch, don't link, so callee returns to caller of this function.
321 address call_c_and_return_to_caller(Register function_entry);
322 address call_c(address function_entry, relocInfo::relocType rt);
323 #else
324 // Call a C function via a function descriptor and use full C
325 // calling conventions. Updates and returns _last_calls_return_pc.
326 address call_c(Register function_descriptor);
327 // For tail calls: only branch, don't link, so callee returns to caller of this function.
328 address call_c_and_return_to_caller(Register function_descriptor);
329 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
330 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
331 Register toc);
332 #endif
333
334 protected:
335
336 // It is imperative that all calls into the VM are handled via the
337 // call_VM macros. They make sure that the stack linkage is setup
338 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
339 // while call_VM_leaf's correspond to LEAF entry points.
340 //
341 // This is the base routine called by the different versions of
342 // call_VM. The interpreter may customize this version by overriding
343 // it for its purposes (e.g., to save/restore additional registers
344 // when doing a VM call).
345 //
346 // If no last_java_sp is specified (noreg) then SP will be used instead.
347 virtual void call_VM_base(
348 // where an oop-result ends up if any; use noreg otherwise
349 Register oop_result,
350 // to set up last_Java_frame in stubs; use noreg otherwise
351 Register last_java_sp,
352 // the entry point
353 address entry_point,
354 // flag which indicates if exception should be checked
355 bool check_exception = true
356 );
357
358 // Support for VM calls. This is the base routine called by the
359 // different versions of call_VM_leaf. The interpreter may customize
360 // this version by overriding it for its purposes (e.g., to
361 // save/restore additional registers when doing a VM call).
362 void call_VM_leaf_base(address entry_point);
363
364 public:
365 // Call into the VM.
366 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
367 // Makes sure oop return values are visible to the GC.
368 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
369 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
370 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
371 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
372 void call_VM_leaf(address entry_point);
373 void call_VM_leaf(address entry_point, Register arg_1);
374 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
375 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
376
377 // Call a stub function via a function descriptor, but don't save
378 // TOC before call, don't setup TOC and ENV for call, and don't
379 // restore TOC after call. Updates and returns _last_calls_return_pc.
380 inline address call_stub(Register function_entry);
381 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
382
383 //
384 // Java utilities
385 //
386
387 // Read from the polling page, its address is already in a register.
388 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
389 // Check whether instruction is a read access to the polling page
390 // which was emitted by load_from_polling_page(..).
391 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be NULL*/,
392 address* polling_address_ptr = NULL);
393
394 // Check whether instruction is a write access to the memory
395 // serialization page realized by one of the instructions stw, stwu,
396 // stwx, or stwux.
397 static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext);
398
399 // Support for NULL-checks
400 //
401 // Generates code that causes a NULL OS exception if the content of reg is NULL.
402 // If the accessed location is M[reg + offset] and the offset is known, provide the
403 // offset. No explicit code generation is needed if the offset is within a certain
404 // range (0 <= offset <= page_size).
405
406 // Stack overflow checking
407 void bang_stack_with_offset(int offset);
408
409 // If instruction is a stack bang of the form ld, stdu, or
410 // stdux, return the banged address. Otherwise, return 0.
411 static address get_stack_bang_address(int instruction, void* ucontext);
412
413 // Atomics
414 // CmpxchgX sets condition register to cmpX(current, compare).
415 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
416 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
417 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
418 // The stxcx will probably not be succeeded by a releasing store.
419 static inline bool cmpxchgx_hint_release_lock() { return false; }
420 static inline bool cmpxchgx_hint_atomic_update() { return false; }
421
422 // Cmpxchg semantics
423 enum {
424 MemBarNone = 0,
425 MemBarRel = 1,
426 MemBarAcq = 2,
427 MemBarFenceAfter = 4 // use powers of 2
428 };
429 void cmpxchgw(ConditionRegister flag,
430 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base,
431 int semantics, bool cmpxchgx_hint = false,
432 Register int_flag_success = noreg, bool contention_hint = false);
433 void cmpxchgd(ConditionRegister flag,
434 Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base,
435 int semantics, bool cmpxchgx_hint = false,
436 Register int_flag_success = noreg, Label* failed = NULL, bool contention_hint = false);
437
438 // interface method calling
439 void lookup_interface_method(Register recv_klass,
440 Register intf_klass,
441 RegisterOrConstant itable_index,
442 Register method_result,
443 Register temp_reg, Register temp2_reg,
444 Label& no_such_interface,
445 bool return_method = true);
446
447 // virtual method calling
448 void lookup_virtual_method(Register recv_klass,
449 RegisterOrConstant vtable_index,
450 Register method_result);
451
452 // Test sub_klass against super_klass, with fast and slow paths.
453
454 // The fast path produces a tri-state answer: yes / no / maybe-slow.
455 // One of the three labels can be NULL, meaning take the fall-through.
456 // If super_check_offset is -1, the value is loaded up from super_klass.
457 // No registers are killed, except temp_reg and temp2_reg.
458 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
459 void check_klass_subtype_fast_path(Register sub_klass,
460 Register super_klass,
461 Register temp1_reg,
462 Register temp2_reg,
463 Label& L_success,
464 Label& L_failure);
465
466 // The rest of the type check; must be wired to a corresponding fast path.
467 // It does not repeat the fast path logic, so don't use it standalone.
468 // The temp_reg can be noreg, if no temps are available.
469 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
470 // Updates the sub's secondary super cache as necessary.
471 void check_klass_subtype_slow_path(Register sub_klass,
472 Register super_klass,
473 Register temp1_reg,
474 Register temp2_reg,
475 Label* L_success = NULL,
476 Register result_reg = noreg);
477
478 // Simplified, combined version, good for typical uses.
479 // Falls through on failure.
480 void check_klass_subtype(Register sub_klass,
481 Register super_klass,
482 Register temp1_reg,
483 Register temp2_reg,
484 Label& L_success);
485
486 // Method handle support (JSR 292).
487 void check_method_handle_type(Register mtype_reg, Register mh_reg, Register temp_reg, Label& wrong_method_type);
488
489 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
490
491 // Biased locking support
492 // Upon entry,obj_reg must contain the target object, and mark_reg
493 // must contain the target object's header.
494 // Destroys mark_reg if an attempt is made to bias an anonymously
495 // biased lock. In this case a failure will go either to the slow
496 // case or fall through with the notEqual condition code set with
497 // the expectation that the slow case in the runtime will be called.
498 // In the fall-through case where the CAS-based lock is done,
499 // mark_reg is not destroyed.
500 void biased_locking_enter(ConditionRegister cr_reg, Register obj_reg, Register mark_reg, Register temp_reg,
501 Register temp2_reg, Label& done, Label* slow_case = NULL);
502 // Upon entry, the base register of mark_addr must contain the oop.
503 // Destroys temp_reg.
504 // If allow_delay_slot_filling is set to true, the next instruction
505 // emitted after this one will go in an annulled delay slot if the
506 // biased locking exit case failed.
507 void biased_locking_exit(ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done);
508
509 void compiler_fast_lock_object( ConditionRegister flag, Register oop, Register box, Register tmp1, Register tmp2, Register tmp3);
510 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box, Register tmp1, Register tmp2, Register tmp3);
511
512 // Support for serializing memory accesses between threads
513 void serialize_memory(Register thread, Register tmp1, Register tmp2);
514
515 // GC barrier support.
516 void card_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp);
517 void card_table_write(jbyte* byte_map_base, Register Rtmp, Register Robj);
518
519 void resolve_jobject(Register value, Register tmp1, Register tmp2, bool needs_frame);
520
521 #if INCLUDE_ALL_GCS
522 // General G1 pre-barrier generator.
523 void g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val,
524 Register Rtmp1, Register Rtmp2, bool needs_frame = false);
525 // General G1 post-barrier generator
526 void g1_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp1,
527 Register Rtmp2, Register Rtmp3, Label *filtered_ext = NULL);
528 #endif
529
530 // Support for managing the JavaThread pointer (i.e.; the reference to
531 // thread-local information).
532
533 // Support for last Java frame (but use call_VM instead where possible):
534 // access R16_thread->last_Java_sp.
535 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
536 void reset_last_Java_frame(void);
537 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1);
538
539 // Read vm result from thread: oop_result = R16_thread->result;
540 void get_vm_result (Register oop_result);
541 void get_vm_result_2(Register metadata_result);
542
543 static bool needs_explicit_null_check(intptr_t offset);
544
545 // Trap-instruction-based checks.
546 // Range checks can be distinguished from zero checks as they check 32 bit,
547 // zero checks all 64 bits (tw, td).
548 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
549 static bool is_trap_null_check(int x) {
550 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
551 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
552 }
553
554 inline void trap_zombie_not_entrant();
555 static bool is_trap_zombie_not_entrant(int x) { return is_tdi(x, traptoUnconditional, 0/*reg 0*/, 1); }
556
557 inline void trap_should_not_reach_here();
558 static bool is_trap_should_not_reach_here(int x) { return is_tdi(x, traptoUnconditional, 0/*reg 0*/, 2); }
559
560 inline void trap_ic_miss_check(Register a, Register b);
561 static bool is_trap_ic_miss_check(int x) {
562 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
563 }
564
565 // Implicit or explicit null check, jumps to static address exception_entry.
566 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
567
568 // Check accessed object for null. Use SIGTRAP-based null checks on AIX.
569 inline void load_with_trap_null_check(Register d, int si16, Register s1);
570
571 // Load heap oop and decompress. Loaded oop may not be null.
572 inline void load_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1 = noreg);
573 inline void store_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1,
574 /*specify if d must stay uncompressed*/ Register tmp = noreg);
575
576 // Null allowed.
577 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1 = noreg);
578
579 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
580 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
581 inline void decode_heap_oop_not_null(Register d);
582
583 // Null allowed.
584 inline void decode_heap_oop(Register d);
585
586 // Load/Store klass oop from klass field. Compress.
587 void load_klass(Register dst, Register src);
588 void load_klass_with_trap_null_check(Register dst, Register src);
589 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
590 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
591 static int instr_size_for_decode_klass_not_null();
592 void decode_klass_not_null(Register dst, Register src = noreg);
593 void encode_klass_not_null(Register dst, Register src = noreg);
594
595 // Load common heap base into register.
596 void reinit_heapbase(Register d, Register tmp = noreg);
597
598 // SIGTRAP-based range checks for arrays.
599 inline void trap_range_check_l(Register a, Register b);
600 inline void trap_range_check_l(Register a, int si16);
601 static bool is_trap_range_check_l(int x) {
602 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
603 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
604 }
605 inline void trap_range_check_le(Register a, int si16);
606 static bool is_trap_range_check_le(int x) {
607 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
608 }
609 inline void trap_range_check_g(Register a, int si16);
610 static bool is_trap_range_check_g(int x) {
611 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
612 }
613 inline void trap_range_check_ge(Register a, Register b);
614 inline void trap_range_check_ge(Register a, int si16);
615 static bool is_trap_range_check_ge(int x) {
616 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
617 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
618 }
619 static bool is_trap_range_check(int x) {
620 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
621 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
622 }
623
624 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0);
625
626 // Needle of length 1.
627 void string_indexof_1(Register result, Register haystack, Register haycnt,
628 Register needle, jchar needleChar,
629 Register tmp1, Register tmp2);
630 // General indexof, eventually with constant needle length.
631 void string_indexof(Register result, Register haystack, Register haycnt,
632 Register needle, ciTypeArray* needle_values, Register needlecnt, int needlecntval,
633 Register tmp1, Register tmp2, Register tmp3, Register tmp4);
634 void string_compare(Register str1_reg, Register str2_reg, Register cnt1_reg, Register cnt2_reg,
635 Register result_reg, Register tmp_reg);
636 void char_arrays_equals(Register str1_reg, Register str2_reg, Register cnt_reg, Register result_reg,
637 Register tmp1_reg, Register tmp2_reg, Register tmp3_reg, Register tmp4_reg,
638 Register tmp5_reg);
639 void char_arrays_equalsImm(Register str1_reg, Register str2_reg, int cntval, Register result_reg,
640 Register tmp1_reg, Register tmp2_reg);
641
642 // CRC32 Intrinsics.
643 void load_reverse_32(Register dst, Register src);
644 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
645 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
646 void fold_8bit_crc32(Register crc, Register table, Register tmp);
647 void update_byte_crc32(Register crc, Register val, Register table);
648 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
649 Register data, bool loopAlignment, bool invertCRC);
650 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
651 Register t0, Register t1, Register t2, Register t3,
652 Register tc0, Register tc1, Register tc2, Register tc3);
653 void kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
654 Register t0, Register t1, Register t2, Register t3,
655 Register tc0, Register tc1, Register tc2, Register tc3);
656 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
657 Register t0, Register t1, Register t2, Register t3,
658 Register tc0, Register tc1, Register tc2, Register tc3);
659 void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
660 Register t0, Register t1, Register t2, Register t3);
661 void kernel_crc32_1word_vpmsumd(Register crc, Register buf, Register len, Register table,
662 Register constants, Register barretConstants,
663 Register t0, Register t1, Register t2, Register t3, Register t4);
664 void kernel_crc32_1word_aligned(Register crc, Register buf, Register len,
665 Register constants, Register barretConstants,
666 Register t0, Register t1, Register t2);
667
668 void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp);
669
670 //
671 // Debugging
672 //
673
674 // assert on cr0
675 void asm_assert(bool check_equal, const char* msg, int id);
676 void asm_assert_eq(const char* msg, int id) { asm_assert(true, msg, id); }
677 void asm_assert_ne(const char* msg, int id) { asm_assert(false, msg, id); }
678
679 private:
680 void asm_assert_mems_zero(bool check_equal, int size, int mem_offset, Register mem_base,
681 const char* msg, int id);
682
683 public:
684
685 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg, int id) {
686 asm_assert_mems_zero(true, 8, mem_offset, mem_base, msg, id);
687 }
688 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg, int id) {
689 asm_assert_mems_zero(false, 8, mem_offset, mem_base, msg, id);
690 }
691
692 // Verify R16_thread contents.
693 void verify_thread();
694
695 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
696 void verify_oop(Register reg, const char* s = "broken oop");
697
698 // TODO: verify method and klass metadata (compare against vptr?)
699 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
700 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
701
702 // Convenience method returning function entry. For the ELFv1 case
703 // creates function descriptor at the current address and returs
704 // the pointer to it. For the ELFv2 case returns the current address.
705 inline address function_entry();
706
707 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
708 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
709
710 private:
711
712 enum {
713 stop_stop = 0,
714 stop_untested = 1,
715 stop_unimplemented = 2,
716 stop_shouldnotreachhere = 3,
717 stop_end = 4
718 };
719 void stop(int type, const char* msg, int id);
720
721 public:
722 // Prints msg, dumps registers and stops execution.
723 void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); }
724 void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); }
725 void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); }
726 void should_not_reach_here() { stop(stop_shouldnotreachhere, "", -1); }
727
728 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
729 };
730
731 // class SkipIfEqualZero:
732 //
733 // Instantiating this class will result in assembly code being output that will
734 // jump around any code emitted between the creation of the instance and it's
735 // automatic destruction at the end of a scope block, depending on the value of
736 // the flag passed to the constructor, which will be checked at run-time.
737 class SkipIfEqualZero : public StackObj {
738 private:
739 MacroAssembler* _masm;
740 Label _label;
741
742 public:
743 // 'Temp' is a temp register that this object can use (and trash).
744 explicit SkipIfEqualZero(MacroAssembler*, Register temp, const bool* flag_addr);
745 ~SkipIfEqualZero();
746 };
747
748 #endif // CPU_PPC_VM_MACROASSEMBLER_PPC_HPP