1 /* 2 * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_CFGPrinter.hpp" 27 #include "c1/c1_CodeStubs.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_FrameMap.hpp" 30 #include "c1/c1_IR.hpp" 31 #include "c1/c1_LIRGenerator.hpp" 32 #include "c1/c1_LinearScan.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "code/vmreg.inline.hpp" 35 #include "runtime/timerTrace.hpp" 36 #include "utilities/bitMap.inline.hpp" 37 38 #ifndef PRODUCT 39 40 static LinearScanStatistic _stat_before_alloc; 41 static LinearScanStatistic _stat_after_asign; 42 static LinearScanStatistic _stat_final; 43 44 static LinearScanTimers _total_timer; 45 46 // helper macro for short definition of timer 47 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); 48 49 // helper macro for short definition of trace-output inside code 50 #define TRACE_LINEAR_SCAN(level, code) \ 51 if (TraceLinearScanLevel >= level) { \ 52 code; \ 53 } 54 55 #else 56 57 #define TIME_LINEAR_SCAN(timer_name) 58 #define TRACE_LINEAR_SCAN(level, code) 59 60 #endif 61 62 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words 63 #ifdef _LP64 64 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1}; 65 #else 66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1}; 67 #endif 68 69 70 // Implementation of LinearScan 71 72 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) 73 : _compilation(ir->compilation()) 74 , _ir(ir) 75 , _gen(gen) 76 , _frame_map(frame_map) 77 , _num_virtual_regs(gen->max_virtual_register_number()) 78 , _has_fpu_registers(false) 79 , _num_calls(-1) 80 , _max_spills(0) 81 , _unused_spill_slot(-1) 82 , _intervals(0) // initialized later with correct length 83 , _new_intervals_from_allocation(new IntervalList()) 84 , _sorted_intervals(NULL) 85 , _needs_full_resort(false) 86 , _lir_ops(0) // initialized later with correct length 87 , _block_of_op(0) // initialized later with correct length 88 , _has_info(0) 89 , _has_call(0) 90 , _scope_value_cache(0) // initialized later with correct length 91 , _interval_in_loop(0) // initialized later with correct length 92 , _cached_blocks(*ir->linear_scan_order()) 93 #ifdef X86 94 , _fpu_stack_allocator(NULL) 95 #endif 96 { 97 assert(this->ir() != NULL, "check if valid"); 98 assert(this->compilation() != NULL, "check if valid"); 99 assert(this->gen() != NULL, "check if valid"); 100 assert(this->frame_map() != NULL, "check if valid"); 101 } 102 103 104 // ********** functions for converting LIR-Operands to register numbers 105 // 106 // Emulate a flat register file comprising physical integer registers, 107 // physical floating-point registers and virtual registers, in that order. 108 // Virtual registers already have appropriate numbers, since V0 is 109 // the number of physical registers. 110 // Returns -1 for hi word if opr is a single word operand. 111 // 112 // Note: the inverse operation (calculating an operand for register numbers) 113 // is done in calc_operand_for_interval() 114 115 int LinearScan::reg_num(LIR_Opr opr) { 116 assert(opr->is_register(), "should not call this otherwise"); 117 118 if (opr->is_virtual_register()) { 119 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); 120 return opr->vreg_number(); 121 } else if (opr->is_single_cpu()) { 122 return opr->cpu_regnr(); 123 } else if (opr->is_double_cpu()) { 124 return opr->cpu_regnrLo(); 125 #ifdef X86 126 } else if (opr->is_single_xmm()) { 127 return opr->fpu_regnr() + pd_first_xmm_reg; 128 } else if (opr->is_double_xmm()) { 129 return opr->fpu_regnrLo() + pd_first_xmm_reg; 130 #endif 131 } else if (opr->is_single_fpu()) { 132 return opr->fpu_regnr() + pd_first_fpu_reg; 133 } else if (opr->is_double_fpu()) { 134 return opr->fpu_regnrLo() + pd_first_fpu_reg; 135 } else { 136 ShouldNotReachHere(); 137 return -1; 138 } 139 } 140 141 int LinearScan::reg_numHi(LIR_Opr opr) { 142 assert(opr->is_register(), "should not call this otherwise"); 143 144 if (opr->is_virtual_register()) { 145 return -1; 146 } else if (opr->is_single_cpu()) { 147 return -1; 148 } else if (opr->is_double_cpu()) { 149 return opr->cpu_regnrHi(); 150 #ifdef X86 151 } else if (opr->is_single_xmm()) { 152 return -1; 153 } else if (opr->is_double_xmm()) { 154 return -1; 155 #endif 156 } else if (opr->is_single_fpu()) { 157 return -1; 158 } else if (opr->is_double_fpu()) { 159 return opr->fpu_regnrHi() + pd_first_fpu_reg; 160 } else { 161 ShouldNotReachHere(); 162 return -1; 163 } 164 } 165 166 167 // ********** functions for classification of intervals 168 169 bool LinearScan::is_precolored_interval(const Interval* i) { 170 return i->reg_num() < LinearScan::nof_regs; 171 } 172 173 bool LinearScan::is_virtual_interval(const Interval* i) { 174 return i->reg_num() >= LIR_OprDesc::vreg_base; 175 } 176 177 bool LinearScan::is_precolored_cpu_interval(const Interval* i) { 178 return i->reg_num() < LinearScan::nof_cpu_regs; 179 } 180 181 bool LinearScan::is_virtual_cpu_interval(const Interval* i) { 182 #if defined(__SOFTFP__) || defined(E500V2) 183 return i->reg_num() >= LIR_OprDesc::vreg_base; 184 #else 185 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); 186 #endif // __SOFTFP__ or E500V2 187 } 188 189 bool LinearScan::is_precolored_fpu_interval(const Interval* i) { 190 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; 191 } 192 193 bool LinearScan::is_virtual_fpu_interval(const Interval* i) { 194 #if defined(__SOFTFP__) || defined(E500V2) 195 return false; 196 #else 197 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); 198 #endif // __SOFTFP__ or E500V2 199 } 200 201 bool LinearScan::is_in_fpu_register(const Interval* i) { 202 // fixed intervals not needed for FPU stack allocation 203 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; 204 } 205 206 bool LinearScan::is_oop_interval(const Interval* i) { 207 // fixed intervals never contain oops 208 return i->reg_num() >= nof_regs && i->type() == T_OBJECT; 209 } 210 211 212 // ********** General helper functions 213 214 // compute next unused stack index that can be used for spilling 215 int LinearScan::allocate_spill_slot(bool double_word) { 216 int spill_slot; 217 if (double_word) { 218 if ((_max_spills & 1) == 1) { 219 // alignment of double-word values 220 // the hole because of the alignment is filled with the next single-word value 221 assert(_unused_spill_slot == -1, "wasting a spill slot"); 222 _unused_spill_slot = _max_spills; 223 _max_spills++; 224 } 225 spill_slot = _max_spills; 226 _max_spills += 2; 227 228 } else if (_unused_spill_slot != -1) { 229 // re-use hole that was the result of a previous double-word alignment 230 spill_slot = _unused_spill_slot; 231 _unused_spill_slot = -1; 232 233 } else { 234 spill_slot = _max_spills; 235 _max_spills++; 236 } 237 238 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); 239 240 // the class OopMapValue uses only 11 bits for storing the name of the 241 // oop location. So a stack slot bigger than 2^11 leads to an overflow 242 // that is not reported in product builds. Prevent this by checking the 243 // spill slot here (altough this value and the later used location name 244 // are slightly different) 245 if (result > 2000) { 246 bailout("too many stack slots used"); 247 } 248 249 return result; 250 } 251 252 void LinearScan::assign_spill_slot(Interval* it) { 253 // assign the canonical spill slot of the parent (if a part of the interval 254 // is already spilled) or allocate a new spill slot 255 if (it->canonical_spill_slot() >= 0) { 256 it->assign_reg(it->canonical_spill_slot()); 257 } else { 258 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); 259 it->set_canonical_spill_slot(spill); 260 it->assign_reg(spill); 261 } 262 } 263 264 void LinearScan::propagate_spill_slots() { 265 if (!frame_map()->finalize_frame(max_spills())) { 266 bailout("frame too large"); 267 } 268 } 269 270 // create a new interval with a predefined reg_num 271 // (only used for parent intervals that are created during the building phase) 272 Interval* LinearScan::create_interval(int reg_num) { 273 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); 274 275 Interval* interval = new Interval(reg_num); 276 _intervals.at_put(reg_num, interval); 277 278 // assign register number for precolored intervals 279 if (reg_num < LIR_OprDesc::vreg_base) { 280 interval->assign_reg(reg_num); 281 } 282 return interval; 283 } 284 285 // assign a new reg_num to the interval and append it to the list of intervals 286 // (only used for child intervals that are created during register allocation) 287 void LinearScan::append_interval(Interval* it) { 288 it->set_reg_num(_intervals.length()); 289 _intervals.append(it); 290 _new_intervals_from_allocation->append(it); 291 } 292 293 // copy the vreg-flags if an interval is split 294 void LinearScan::copy_register_flags(Interval* from, Interval* to) { 295 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { 296 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); 297 } 298 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { 299 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); 300 } 301 302 // Note: do not copy the must_start_in_memory flag because it is not necessary for child 303 // intervals (only the very beginning of the interval must be in memory) 304 } 305 306 307 // ********** spill move optimization 308 // eliminate moves from register to stack if stack slot is known to be correct 309 310 // called during building of intervals 311 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { 312 assert(interval->is_split_parent(), "can only be called for split parents"); 313 314 switch (interval->spill_state()) { 315 case noDefinitionFound: 316 assert(interval->spill_definition_pos() == -1, "must no be set before"); 317 interval->set_spill_definition_pos(def_pos); 318 interval->set_spill_state(oneDefinitionFound); 319 break; 320 321 case oneDefinitionFound: 322 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); 323 if (def_pos < interval->spill_definition_pos() - 2) { 324 // second definition found, so no spill optimization possible for this interval 325 interval->set_spill_state(noOptimization); 326 } else { 327 // two consecutive definitions (because of two-operand LIR form) 328 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); 329 } 330 break; 331 332 case noOptimization: 333 // nothing to do 334 break; 335 336 default: 337 assert(false, "other states not allowed at this time"); 338 } 339 } 340 341 // called during register allocation 342 void LinearScan::change_spill_state(Interval* interval, int spill_pos) { 343 switch (interval->spill_state()) { 344 case oneDefinitionFound: { 345 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); 346 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); 347 348 if (def_loop_depth < spill_loop_depth) { 349 // the loop depth of the spilling position is higher then the loop depth 350 // at the definition of the interval -> move write to memory out of loop 351 // by storing at definitin of the interval 352 interval->set_spill_state(storeAtDefinition); 353 } else { 354 // the interval is currently spilled only once, so for now there is no 355 // reason to store the interval at the definition 356 interval->set_spill_state(oneMoveInserted); 357 } 358 break; 359 } 360 361 case oneMoveInserted: { 362 // the interval is spilled more then once, so it is better to store it to 363 // memory at the definition 364 interval->set_spill_state(storeAtDefinition); 365 break; 366 } 367 368 case storeAtDefinition: 369 case startInMemory: 370 case noOptimization: 371 case noDefinitionFound: 372 // nothing to do 373 break; 374 375 default: 376 assert(false, "other states not allowed at this time"); 377 } 378 } 379 380 381 bool LinearScan::must_store_at_definition(const Interval* i) { 382 return i->is_split_parent() && i->spill_state() == storeAtDefinition; 383 } 384 385 // called once before asignment of register numbers 386 void LinearScan::eliminate_spill_moves() { 387 TIME_LINEAR_SCAN(timer_eliminate_spill_moves); 388 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); 389 390 // collect all intervals that must be stored after their definion. 391 // the list is sorted by Interval::spill_definition_pos 392 Interval* interval; 393 Interval* temp_list; 394 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); 395 396 #ifdef ASSERT 397 Interval* prev = NULL; 398 Interval* temp = interval; 399 while (temp != Interval::end()) { 400 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); 401 if (prev != NULL) { 402 assert(temp->from() >= prev->from(), "intervals not sorted"); 403 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); 404 } 405 406 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); 407 assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); 408 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); 409 410 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); 411 412 temp = temp->next(); 413 } 414 #endif 415 416 LIR_InsertionBuffer insertion_buffer; 417 int num_blocks = block_count(); 418 for (int i = 0; i < num_blocks; i++) { 419 BlockBegin* block = block_at(i); 420 LIR_OpList* instructions = block->lir()->instructions_list(); 421 int num_inst = instructions->length(); 422 bool has_new = false; 423 424 // iterate all instructions of the block. skip the first because it is always a label 425 for (int j = 1; j < num_inst; j++) { 426 LIR_Op* op = instructions->at(j); 427 int op_id = op->id(); 428 429 if (op_id == -1) { 430 // remove move from register to stack if the stack slot is guaranteed to be correct. 431 // only moves that have been inserted by LinearScan can be removed. 432 assert(op->code() == lir_move, "only moves can have a op_id of -1"); 433 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 434 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); 435 436 LIR_Op1* op1 = (LIR_Op1*)op; 437 Interval* interval = interval_at(op1->result_opr()->vreg_number()); 438 439 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { 440 // move target is a stack slot that is always correct, so eliminate instruction 441 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); 442 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num 443 } 444 445 } else { 446 // insert move from register to stack just after the beginning of the interval 447 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); 448 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); 449 450 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { 451 if (!has_new) { 452 // prepare insertion buffer (appended when all instructions of the block are processed) 453 insertion_buffer.init(block->lir()); 454 has_new = true; 455 } 456 457 LIR_Opr from_opr = operand_for_interval(interval); 458 LIR_Opr to_opr = canonical_spill_opr(interval); 459 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); 460 assert(to_opr->is_stack(), "to operand must be a stack slot"); 461 462 insertion_buffer.move(j, from_opr, to_opr); 463 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); 464 465 interval = interval->next(); 466 } 467 } 468 } // end of instruction iteration 469 470 if (has_new) { 471 block->lir()->append(&insertion_buffer); 472 } 473 } // end of block iteration 474 475 assert(interval == Interval::end(), "missed an interval"); 476 } 477 478 479 // ********** Phase 1: number all instructions in all blocks 480 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. 481 482 void LinearScan::number_instructions() { 483 { 484 // dummy-timer to measure the cost of the timer itself 485 // (this time is then subtracted from all other timers to get the real value) 486 TIME_LINEAR_SCAN(timer_do_nothing); 487 } 488 TIME_LINEAR_SCAN(timer_number_instructions); 489 490 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. 491 int num_blocks = block_count(); 492 int num_instructions = 0; 493 int i; 494 for (i = 0; i < num_blocks; i++) { 495 num_instructions += block_at(i)->lir()->instructions_list()->length(); 496 } 497 498 // initialize with correct length 499 _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL); 500 _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL); 501 502 int op_id = 0; 503 int idx = 0; 504 505 for (i = 0; i < num_blocks; i++) { 506 BlockBegin* block = block_at(i); 507 block->set_first_lir_instruction_id(op_id); 508 LIR_OpList* instructions = block->lir()->instructions_list(); 509 510 int num_inst = instructions->length(); 511 for (int j = 0; j < num_inst; j++) { 512 LIR_Op* op = instructions->at(j); 513 op->set_id(op_id); 514 515 _lir_ops.at_put(idx, op); 516 _block_of_op.at_put(idx, block); 517 assert(lir_op_with_id(op_id) == op, "must match"); 518 519 idx++; 520 op_id += 2; // numbering of lir_ops by two 521 } 522 block->set_last_lir_instruction_id(op_id - 2); 523 } 524 assert(idx == num_instructions, "must match"); 525 assert(idx * 2 == op_id, "must match"); 526 527 _has_call.initialize(num_instructions); 528 _has_info.initialize(num_instructions); 529 } 530 531 532 // ********** Phase 2: compute local live sets separately for each block 533 // (sets live_gen and live_kill for each block) 534 535 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { 536 LIR_Opr opr = value->operand(); 537 Constant* con = value->as_Constant(); 538 539 // check some asumptions about debug information 540 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); 541 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); 542 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 543 544 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 545 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 546 int reg = opr->vreg_number(); 547 if (!live_kill.at(reg)) { 548 live_gen.set_bit(reg); 549 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); 550 } 551 } 552 } 553 554 555 void LinearScan::compute_local_live_sets() { 556 TIME_LINEAR_SCAN(timer_compute_local_live_sets); 557 558 int num_blocks = block_count(); 559 int live_size = live_set_size(); 560 bool local_has_fpu_registers = false; 561 int local_num_calls = 0; 562 LIR_OpVisitState visitor; 563 564 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); 565 566 // iterate all blocks 567 for (int i = 0; i < num_blocks; i++) { 568 BlockBegin* block = block_at(i); 569 570 ResourceBitMap live_gen(live_size); 571 ResourceBitMap live_kill(live_size); 572 573 if (block->is_set(BlockBegin::exception_entry_flag)) { 574 // Phi functions at the begin of an exception handler are 575 // implicitly defined (= killed) at the beginning of the block. 576 for_each_phi_fun(block, phi, 577 live_kill.set_bit(phi->operand()->vreg_number()) 578 ); 579 } 580 581 LIR_OpList* instructions = block->lir()->instructions_list(); 582 int num_inst = instructions->length(); 583 584 // iterate all instructions of the block. skip the first because it is always a label 585 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 586 for (int j = 1; j < num_inst; j++) { 587 LIR_Op* op = instructions->at(j); 588 589 // visit operation to collect all operands 590 visitor.visit(op); 591 592 if (visitor.has_call()) { 593 _has_call.set_bit(op->id() >> 1); 594 local_num_calls++; 595 } 596 if (visitor.info_count() > 0) { 597 _has_info.set_bit(op->id() >> 1); 598 } 599 600 // iterate input operands of instruction 601 int k, n, reg; 602 n = visitor.opr_count(LIR_OpVisitState::inputMode); 603 for (k = 0; k < n; k++) { 604 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 605 assert(opr->is_register(), "visitor should only return register operands"); 606 607 if (opr->is_virtual_register()) { 608 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 609 reg = opr->vreg_number(); 610 if (!live_kill.at(reg)) { 611 live_gen.set_bit(reg); 612 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); 613 } 614 if (block->loop_index() >= 0) { 615 local_interval_in_loop.set_bit(reg, block->loop_index()); 616 } 617 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 618 } 619 620 #ifdef ASSERT 621 // fixed intervals are never live at block boundaries, so 622 // they need not be processed in live sets. 623 // this is checked by these assertions to be sure about it. 624 // the entry block may have incoming values in registers, which is ok. 625 if (!opr->is_virtual_register() && block != ir()->start()) { 626 reg = reg_num(opr); 627 if (is_processed_reg_num(reg)) { 628 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 629 } 630 reg = reg_numHi(opr); 631 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 632 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 633 } 634 } 635 #endif 636 } 637 638 // Add uses of live locals from interpreter's point of view for proper debug information generation 639 n = visitor.info_count(); 640 for (k = 0; k < n; k++) { 641 CodeEmitInfo* info = visitor.info_at(k); 642 ValueStack* stack = info->stack(); 643 for_each_state_value(stack, value, 644 set_live_gen_kill(value, op, live_gen, live_kill) 645 ); 646 } 647 648 // iterate temp operands of instruction 649 n = visitor.opr_count(LIR_OpVisitState::tempMode); 650 for (k = 0; k < n; k++) { 651 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 652 assert(opr->is_register(), "visitor should only return register operands"); 653 654 if (opr->is_virtual_register()) { 655 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 656 reg = opr->vreg_number(); 657 live_kill.set_bit(reg); 658 if (block->loop_index() >= 0) { 659 local_interval_in_loop.set_bit(reg, block->loop_index()); 660 } 661 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 662 } 663 664 #ifdef ASSERT 665 // fixed intervals are never live at block boundaries, so 666 // they need not be processed in live sets 667 // process them only in debug mode so that this can be checked 668 if (!opr->is_virtual_register()) { 669 reg = reg_num(opr); 670 if (is_processed_reg_num(reg)) { 671 live_kill.set_bit(reg_num(opr)); 672 } 673 reg = reg_numHi(opr); 674 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 675 live_kill.set_bit(reg); 676 } 677 } 678 #endif 679 } 680 681 // iterate output operands of instruction 682 n = visitor.opr_count(LIR_OpVisitState::outputMode); 683 for (k = 0; k < n; k++) { 684 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 685 assert(opr->is_register(), "visitor should only return register operands"); 686 687 if (opr->is_virtual_register()) { 688 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 689 reg = opr->vreg_number(); 690 live_kill.set_bit(reg); 691 if (block->loop_index() >= 0) { 692 local_interval_in_loop.set_bit(reg, block->loop_index()); 693 } 694 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 695 } 696 697 #ifdef ASSERT 698 // fixed intervals are never live at block boundaries, so 699 // they need not be processed in live sets 700 // process them only in debug mode so that this can be checked 701 if (!opr->is_virtual_register()) { 702 reg = reg_num(opr); 703 if (is_processed_reg_num(reg)) { 704 live_kill.set_bit(reg_num(opr)); 705 } 706 reg = reg_numHi(opr); 707 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 708 live_kill.set_bit(reg); 709 } 710 } 711 #endif 712 } 713 } // end of instruction iteration 714 715 block->set_live_gen (live_gen); 716 block->set_live_kill(live_kill); 717 block->set_live_in (ResourceBitMap(live_size)); 718 block->set_live_out (ResourceBitMap(live_size)); 719 720 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); 721 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); 722 } // end of block iteration 723 724 // propagate local calculated information into LinearScan object 725 _has_fpu_registers = local_has_fpu_registers; 726 compilation()->set_has_fpu_code(local_has_fpu_registers); 727 728 _num_calls = local_num_calls; 729 _interval_in_loop = local_interval_in_loop; 730 } 731 732 733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets 734 // (sets live_in and live_out for each block) 735 736 void LinearScan::compute_global_live_sets() { 737 TIME_LINEAR_SCAN(timer_compute_global_live_sets); 738 739 int num_blocks = block_count(); 740 bool change_occurred; 741 bool change_occurred_in_block; 742 int iteration_count = 0; 743 ResourceBitMap live_out(live_set_size()); // scratch set for calculations 744 745 // Perform a backward dataflow analysis to compute live_out and live_in for each block. 746 // The loop is executed until a fixpoint is reached (no changes in an iteration) 747 // Exception handlers must be processed because not all live values are 748 // present in the state array, e.g. because of global value numbering 749 do { 750 change_occurred = false; 751 752 // iterate all blocks in reverse order 753 for (int i = num_blocks - 1; i >= 0; i--) { 754 BlockBegin* block = block_at(i); 755 756 change_occurred_in_block = false; 757 758 // live_out(block) is the union of live_in(sux), for successors sux of block 759 int n = block->number_of_sux(); 760 int e = block->number_of_exception_handlers(); 761 if (n + e > 0) { 762 // block has successors 763 if (n > 0) { 764 live_out.set_from(block->sux_at(0)->live_in()); 765 for (int j = 1; j < n; j++) { 766 live_out.set_union(block->sux_at(j)->live_in()); 767 } 768 } else { 769 live_out.clear(); 770 } 771 for (int j = 0; j < e; j++) { 772 live_out.set_union(block->exception_handler_at(j)->live_in()); 773 } 774 775 if (!block->live_out().is_same(live_out)) { 776 // A change occurred. Swap the old and new live out sets to avoid copying. 777 ResourceBitMap temp = block->live_out(); 778 block->set_live_out(live_out); 779 live_out = temp; 780 781 change_occurred = true; 782 change_occurred_in_block = true; 783 } 784 } 785 786 if (iteration_count == 0 || change_occurred_in_block) { 787 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) 788 // note: live_in has to be computed only in first iteration or if live_out has changed! 789 ResourceBitMap live_in = block->live_in(); 790 live_in.set_from(block->live_out()); 791 live_in.set_difference(block->live_kill()); 792 live_in.set_union(block->live_gen()); 793 } 794 795 #ifndef PRODUCT 796 if (TraceLinearScanLevel >= 4) { 797 char c = ' '; 798 if (iteration_count == 0 || change_occurred_in_block) { 799 c = '*'; 800 } 801 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); 802 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); 803 } 804 #endif 805 } 806 iteration_count++; 807 808 if (change_occurred && iteration_count > 50) { 809 BAILOUT("too many iterations in compute_global_live_sets"); 810 } 811 } while (change_occurred); 812 813 814 #ifdef ASSERT 815 // check that fixed intervals are not live at block boundaries 816 // (live set must be empty at fixed intervals) 817 for (int i = 0; i < num_blocks; i++) { 818 BlockBegin* block = block_at(i); 819 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { 820 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); 821 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); 822 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); 823 } 824 } 825 #endif 826 827 // check that the live_in set of the first block is empty 828 ResourceBitMap live_in_args(ir()->start()->live_in().size()); 829 if (!ir()->start()->live_in().is_same(live_in_args)) { 830 #ifdef ASSERT 831 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); 832 tty->print_cr("affected registers:"); 833 print_bitmap(ir()->start()->live_in()); 834 835 // print some additional information to simplify debugging 836 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { 837 if (ir()->start()->live_in().at(i)) { 838 Instruction* instr = gen()->instruction_for_vreg(i); 839 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); 840 841 for (int j = 0; j < num_blocks; j++) { 842 BlockBegin* block = block_at(j); 843 if (block->live_gen().at(i)) { 844 tty->print_cr(" used in block B%d", block->block_id()); 845 } 846 if (block->live_kill().at(i)) { 847 tty->print_cr(" defined in block B%d", block->block_id()); 848 } 849 } 850 } 851 } 852 853 #endif 854 // when this fails, virtual registers are used before they are defined. 855 assert(false, "live_in set of first block must be empty"); 856 // bailout of if this occurs in product mode. 857 bailout("live_in set of first block not empty"); 858 } 859 } 860 861 862 // ********** Phase 4: build intervals 863 // (fills the list _intervals) 864 865 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { 866 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); 867 LIR_Opr opr = value->operand(); 868 Constant* con = value->as_Constant(); 869 870 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 871 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 872 add_use(opr, from, to, use_kind); 873 } 874 } 875 876 877 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { 878 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); 879 assert(opr->is_register(), "should not be called otherwise"); 880 881 if (opr->is_virtual_register()) { 882 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 883 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); 884 885 } else { 886 int reg = reg_num(opr); 887 if (is_processed_reg_num(reg)) { 888 add_def(reg, def_pos, use_kind, opr->type_register()); 889 } 890 reg = reg_numHi(opr); 891 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 892 add_def(reg, def_pos, use_kind, opr->type_register()); 893 } 894 } 895 } 896 897 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { 898 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); 899 assert(opr->is_register(), "should not be called otherwise"); 900 901 if (opr->is_virtual_register()) { 902 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 903 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); 904 905 } else { 906 int reg = reg_num(opr); 907 if (is_processed_reg_num(reg)) { 908 add_use(reg, from, to, use_kind, opr->type_register()); 909 } 910 reg = reg_numHi(opr); 911 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 912 add_use(reg, from, to, use_kind, opr->type_register()); 913 } 914 } 915 } 916 917 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { 918 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); 919 assert(opr->is_register(), "should not be called otherwise"); 920 921 if (opr->is_virtual_register()) { 922 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 923 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); 924 925 } else { 926 int reg = reg_num(opr); 927 if (is_processed_reg_num(reg)) { 928 add_temp(reg, temp_pos, use_kind, opr->type_register()); 929 } 930 reg = reg_numHi(opr); 931 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 932 add_temp(reg, temp_pos, use_kind, opr->type_register()); 933 } 934 } 935 } 936 937 938 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { 939 Interval* interval = interval_at(reg_num); 940 if (interval != NULL) { 941 assert(interval->reg_num() == reg_num, "wrong interval"); 942 943 if (type != T_ILLEGAL) { 944 interval->set_type(type); 945 } 946 947 Range* r = interval->first(); 948 if (r->from() <= def_pos) { 949 // Update the starting point (when a range is first created for a use, its 950 // start is the beginning of the current block until a def is encountered.) 951 r->set_from(def_pos); 952 interval->add_use_pos(def_pos, use_kind); 953 954 } else { 955 // Dead value - make vacuous interval 956 // also add use_kind for dead intervals 957 interval->add_range(def_pos, def_pos + 1); 958 interval->add_use_pos(def_pos, use_kind); 959 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); 960 } 961 962 } else { 963 // Dead value - make vacuous interval 964 // also add use_kind for dead intervals 965 interval = create_interval(reg_num); 966 if (type != T_ILLEGAL) { 967 interval->set_type(type); 968 } 969 970 interval->add_range(def_pos, def_pos + 1); 971 interval->add_use_pos(def_pos, use_kind); 972 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); 973 } 974 975 change_spill_definition_pos(interval, def_pos); 976 if (use_kind == noUse && interval->spill_state() <= startInMemory) { 977 // detection of method-parameters and roundfp-results 978 // TODO: move this directly to position where use-kind is computed 979 interval->set_spill_state(startInMemory); 980 } 981 } 982 983 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { 984 Interval* interval = interval_at(reg_num); 985 if (interval == NULL) { 986 interval = create_interval(reg_num); 987 } 988 assert(interval->reg_num() == reg_num, "wrong interval"); 989 990 if (type != T_ILLEGAL) { 991 interval->set_type(type); 992 } 993 994 interval->add_range(from, to); 995 interval->add_use_pos(to, use_kind); 996 } 997 998 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { 999 Interval* interval = interval_at(reg_num); 1000 if (interval == NULL) { 1001 interval = create_interval(reg_num); 1002 } 1003 assert(interval->reg_num() == reg_num, "wrong interval"); 1004 1005 if (type != T_ILLEGAL) { 1006 interval->set_type(type); 1007 } 1008 1009 interval->add_range(temp_pos, temp_pos + 1); 1010 interval->add_use_pos(temp_pos, use_kind); 1011 } 1012 1013 1014 // the results of this functions are used for optimizing spilling and reloading 1015 // if the functions return shouldHaveRegister and the interval is spilled, 1016 // it is not reloaded to a register. 1017 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { 1018 if (op->code() == lir_move) { 1019 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1020 LIR_Op1* move = (LIR_Op1*)op; 1021 LIR_Opr res = move->result_opr(); 1022 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1023 1024 if (result_in_memory) { 1025 // Begin of an interval with must_start_in_memory set. 1026 // This interval will always get a stack slot first, so return noUse. 1027 return noUse; 1028 1029 } else if (move->in_opr()->is_stack()) { 1030 // method argument (condition must be equal to handle_method_arguments) 1031 return noUse; 1032 1033 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1034 // Move from register to register 1035 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1036 // special handling of phi-function moves inside osr-entry blocks 1037 // input operand must have a register instead of output operand (leads to better register allocation) 1038 return shouldHaveRegister; 1039 } 1040 } 1041 } 1042 1043 if (opr->is_virtual() && 1044 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { 1045 // result is a stack-slot, so prevent immediate reloading 1046 return noUse; 1047 } 1048 1049 // all other operands require a register 1050 return mustHaveRegister; 1051 } 1052 1053 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { 1054 if (op->code() == lir_move) { 1055 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1056 LIR_Op1* move = (LIR_Op1*)op; 1057 LIR_Opr res = move->result_opr(); 1058 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1059 1060 if (result_in_memory) { 1061 // Move to an interval with must_start_in_memory set. 1062 // To avoid moves from stack to stack (not allowed) force the input operand to a register 1063 return mustHaveRegister; 1064 1065 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1066 // Move from register to register 1067 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1068 // special handling of phi-function moves inside osr-entry blocks 1069 // input operand must have a register instead of output operand (leads to better register allocation) 1070 return mustHaveRegister; 1071 } 1072 1073 // The input operand is not forced to a register (moves from stack to register are allowed), 1074 // but it is faster if the input operand is in a register 1075 return shouldHaveRegister; 1076 } 1077 } 1078 1079 1080 #if defined(X86) || defined(S390) 1081 if (op->code() == lir_cmove) { 1082 // conditional moves can handle stack operands 1083 assert(op->result_opr()->is_register(), "result must always be in a register"); 1084 return shouldHaveRegister; 1085 } 1086 1087 // optimizations for second input operand of arithmehtic operations on Intel 1088 // this operand is allowed to be on the stack in some cases 1089 BasicType opr_type = opr->type_register(); 1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { 1091 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) { 1092 // SSE float instruction (T_DOUBLE only supported with SSE2) 1093 switch (op->code()) { 1094 case lir_cmp: 1095 case lir_add: 1096 case lir_sub: 1097 case lir_mul: 1098 case lir_div: 1099 { 1100 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1101 LIR_Op2* op2 = (LIR_Op2*)op; 1102 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1103 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1104 return shouldHaveRegister; 1105 } 1106 } 1107 default: 1108 break; 1109 } 1110 } else { 1111 // FPU stack float instruction 1112 switch (op->code()) { 1113 case lir_add: 1114 case lir_sub: 1115 case lir_mul: 1116 case lir_div: 1117 { 1118 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1119 LIR_Op2* op2 = (LIR_Op2*)op; 1120 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1121 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1122 return shouldHaveRegister; 1123 } 1124 } 1125 default: 1126 break; 1127 } 1128 } 1129 // We want to sometimes use logical operations on pointers, in particular in GC barriers. 1130 // Since 64bit logical operations do not current support operands on stack, we have to make sure 1131 // T_OBJECT doesn't get spilled along with T_LONG. 1132 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) { 1133 // integer instruction (note: long operands must always be in register) 1134 switch (op->code()) { 1135 case lir_cmp: 1136 case lir_add: 1137 case lir_sub: 1138 case lir_logic_and: 1139 case lir_logic_or: 1140 case lir_logic_xor: 1141 { 1142 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1143 LIR_Op2* op2 = (LIR_Op2*)op; 1144 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1145 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1146 return shouldHaveRegister; 1147 } 1148 } 1149 default: 1150 break; 1151 } 1152 } 1153 #endif // X86 S390 1154 1155 // all other operands require a register 1156 return mustHaveRegister; 1157 } 1158 1159 1160 void LinearScan::handle_method_arguments(LIR_Op* op) { 1161 // special handling for method arguments (moves from stack to virtual register): 1162 // the interval gets no register assigned, but the stack slot. 1163 // it is split before the first use by the register allocator. 1164 1165 if (op->code() == lir_move) { 1166 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1167 LIR_Op1* move = (LIR_Op1*)op; 1168 1169 if (move->in_opr()->is_stack()) { 1170 #ifdef ASSERT 1171 int arg_size = compilation()->method()->arg_size(); 1172 LIR_Opr o = move->in_opr(); 1173 if (o->is_single_stack()) { 1174 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); 1175 } else if (o->is_double_stack()) { 1176 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); 1177 } else { 1178 ShouldNotReachHere(); 1179 } 1180 1181 assert(move->id() > 0, "invalid id"); 1182 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); 1183 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); 1184 1185 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); 1186 #endif 1187 1188 Interval* interval = interval_at(reg_num(move->result_opr())); 1189 1190 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); 1191 interval->set_canonical_spill_slot(stack_slot); 1192 interval->assign_reg(stack_slot); 1193 } 1194 } 1195 } 1196 1197 void LinearScan::handle_doubleword_moves(LIR_Op* op) { 1198 // special handling for doubleword move from memory to register: 1199 // in this case the registers of the input address and the result 1200 // registers must not overlap -> add a temp range for the input registers 1201 if (op->code() == lir_move) { 1202 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1203 LIR_Op1* move = (LIR_Op1*)op; 1204 1205 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { 1206 LIR_Address* address = move->in_opr()->as_address_ptr(); 1207 if (address != NULL) { 1208 if (address->base()->is_valid()) { 1209 add_temp(address->base(), op->id(), noUse); 1210 } 1211 if (address->index()->is_valid()) { 1212 add_temp(address->index(), op->id(), noUse); 1213 } 1214 } 1215 } 1216 } 1217 } 1218 1219 void LinearScan::add_register_hints(LIR_Op* op) { 1220 switch (op->code()) { 1221 case lir_move: // fall through 1222 case lir_convert: { 1223 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); 1224 LIR_Op1* move = (LIR_Op1*)op; 1225 1226 LIR_Opr move_from = move->in_opr(); 1227 LIR_Opr move_to = move->result_opr(); 1228 1229 if (move_to->is_register() && move_from->is_register()) { 1230 Interval* from = interval_at(reg_num(move_from)); 1231 Interval* to = interval_at(reg_num(move_to)); 1232 if (from != NULL && to != NULL) { 1233 to->set_register_hint(from); 1234 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); 1235 } 1236 } 1237 break; 1238 } 1239 case lir_cmove: { 1240 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); 1241 LIR_Op2* cmove = (LIR_Op2*)op; 1242 1243 LIR_Opr move_from = cmove->in_opr1(); 1244 LIR_Opr move_to = cmove->result_opr(); 1245 1246 if (move_to->is_register() && move_from->is_register()) { 1247 Interval* from = interval_at(reg_num(move_from)); 1248 Interval* to = interval_at(reg_num(move_to)); 1249 if (from != NULL && to != NULL) { 1250 to->set_register_hint(from); 1251 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); 1252 } 1253 } 1254 break; 1255 } 1256 default: 1257 break; 1258 } 1259 } 1260 1261 1262 void LinearScan::build_intervals() { 1263 TIME_LINEAR_SCAN(timer_build_intervals); 1264 1265 // initialize interval list with expected number of intervals 1266 // (32 is added to have some space for split children without having to resize the list) 1267 _intervals = IntervalList(num_virtual_regs() + 32); 1268 // initialize all slots that are used by build_intervals 1269 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); 1270 1271 // create a list with all caller-save registers (cpu, fpu, xmm) 1272 // when an instruction is a call, a temp range is created for all these registers 1273 int num_caller_save_registers = 0; 1274 int caller_save_registers[LinearScan::nof_regs]; 1275 1276 int i; 1277 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) { 1278 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); 1279 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1280 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1281 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1282 } 1283 1284 // temp ranges for fpu registers are only created when the method has 1285 // virtual fpu operands. Otherwise no allocation for fpu registers is 1286 // perfomed and so the temp ranges would be useless 1287 if (has_fpu_registers()) { 1288 #ifdef X86 1289 if (UseSSE < 2) { 1290 #endif 1291 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { 1292 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); 1293 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1294 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1295 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1296 } 1297 #ifdef X86 1298 } 1299 if (UseSSE > 0) { 1300 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms(); 1301 for (i = 0; i < num_caller_save_xmm_regs; i ++) { 1302 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); 1303 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1304 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1305 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1306 } 1307 } 1308 #endif 1309 } 1310 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); 1311 1312 1313 LIR_OpVisitState visitor; 1314 1315 // iterate all blocks in reverse order 1316 for (i = block_count() - 1; i >= 0; i--) { 1317 BlockBegin* block = block_at(i); 1318 LIR_OpList* instructions = block->lir()->instructions_list(); 1319 int block_from = block->first_lir_instruction_id(); 1320 int block_to = block->last_lir_instruction_id(); 1321 1322 assert(block_from == instructions->at(0)->id(), "must be"); 1323 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); 1324 1325 // Update intervals for registers live at the end of this block; 1326 ResourceBitMap live = block->live_out(); 1327 int size = (int)live.size(); 1328 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { 1329 assert(live.at(number), "should not stop here otherwise"); 1330 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); 1331 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); 1332 1333 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); 1334 1335 // add special use positions for loop-end blocks when the 1336 // interval is used anywhere inside this loop. It's possible 1337 // that the block was part of a non-natural loop, so it might 1338 // have an invalid loop index. 1339 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && 1340 block->loop_index() != -1 && 1341 is_interval_in_loop(number, block->loop_index())) { 1342 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); 1343 } 1344 } 1345 1346 // iterate all instructions of the block in reverse order. 1347 // skip the first instruction because it is always a label 1348 // definitions of intervals are processed before uses 1349 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 1350 for (int j = instructions->length() - 1; j >= 1; j--) { 1351 LIR_Op* op = instructions->at(j); 1352 int op_id = op->id(); 1353 1354 // visit operation to collect all operands 1355 visitor.visit(op); 1356 1357 // add a temp range for each register if operation destroys caller-save registers 1358 if (visitor.has_call()) { 1359 for (int k = 0; k < num_caller_save_registers; k++) { 1360 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); 1361 } 1362 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); 1363 } 1364 1365 // Add any platform dependent temps 1366 pd_add_temps(op); 1367 1368 // visit definitions (output and temp operands) 1369 int k, n; 1370 n = visitor.opr_count(LIR_OpVisitState::outputMode); 1371 for (k = 0; k < n; k++) { 1372 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 1373 assert(opr->is_register(), "visitor should only return register operands"); 1374 add_def(opr, op_id, use_kind_of_output_operand(op, opr)); 1375 } 1376 1377 n = visitor.opr_count(LIR_OpVisitState::tempMode); 1378 for (k = 0; k < n; k++) { 1379 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 1380 assert(opr->is_register(), "visitor should only return register operands"); 1381 add_temp(opr, op_id, mustHaveRegister); 1382 } 1383 1384 // visit uses (input operands) 1385 n = visitor.opr_count(LIR_OpVisitState::inputMode); 1386 for (k = 0; k < n; k++) { 1387 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 1388 assert(opr->is_register(), "visitor should only return register operands"); 1389 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); 1390 } 1391 1392 // Add uses of live locals from interpreter's point of view for proper 1393 // debug information generation 1394 // Treat these operands as temp values (if the life range is extended 1395 // to a call site, the value would be in a register at the call otherwise) 1396 n = visitor.info_count(); 1397 for (k = 0; k < n; k++) { 1398 CodeEmitInfo* info = visitor.info_at(k); 1399 ValueStack* stack = info->stack(); 1400 for_each_state_value(stack, value, 1401 add_use(value, block_from, op_id + 1, noUse); 1402 ); 1403 } 1404 1405 // special steps for some instructions (especially moves) 1406 handle_method_arguments(op); 1407 handle_doubleword_moves(op); 1408 add_register_hints(op); 1409 1410 } // end of instruction iteration 1411 } // end of block iteration 1412 1413 1414 // add the range [0, 1[ to all fixed intervals 1415 // -> the register allocator need not handle unhandled fixed intervals 1416 for (int n = 0; n < LinearScan::nof_regs; n++) { 1417 Interval* interval = interval_at(n); 1418 if (interval != NULL) { 1419 interval->add_range(0, 1); 1420 } 1421 } 1422 } 1423 1424 1425 // ********** Phase 5: actual register allocation 1426 1427 int LinearScan::interval_cmp(Interval** a, Interval** b) { 1428 if (*a != NULL) { 1429 if (*b != NULL) { 1430 return (*a)->from() - (*b)->from(); 1431 } else { 1432 return -1; 1433 } 1434 } else { 1435 if (*b != NULL) { 1436 return 1; 1437 } else { 1438 return 0; 1439 } 1440 } 1441 } 1442 1443 #ifndef PRODUCT 1444 int interval_cmp(Interval* const& l, Interval* const& r) { 1445 return l->from() - r->from(); 1446 } 1447 1448 bool find_interval(Interval* interval, IntervalArray* intervals) { 1449 bool found; 1450 int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found); 1451 1452 if (!found) { 1453 return false; 1454 } 1455 1456 int from = interval->from(); 1457 1458 // The index we've found using binary search is pointing to an interval 1459 // that is defined in the same place as the interval we were looking for. 1460 // So now we have to look around that index and find exact interval. 1461 for (int i = idx; i >= 0; i--) { 1462 if (intervals->at(i) == interval) { 1463 return true; 1464 } 1465 if (intervals->at(i)->from() != from) { 1466 break; 1467 } 1468 } 1469 1470 for (int i = idx + 1; i < intervals->length(); i++) { 1471 if (intervals->at(i) == interval) { 1472 return true; 1473 } 1474 if (intervals->at(i)->from() != from) { 1475 break; 1476 } 1477 } 1478 1479 return false; 1480 } 1481 1482 bool LinearScan::is_sorted(IntervalArray* intervals) { 1483 int from = -1; 1484 int null_count = 0; 1485 1486 for (int i = 0; i < intervals->length(); i++) { 1487 Interval* it = intervals->at(i); 1488 if (it != NULL) { 1489 assert(from <= it->from(), "Intervals are unordered"); 1490 from = it->from(); 1491 } else { 1492 null_count++; 1493 } 1494 } 1495 1496 assert(null_count == 0, "Sorted intervals should not contain nulls"); 1497 1498 null_count = 0; 1499 1500 for (int i = 0; i < interval_count(); i++) { 1501 Interval* interval = interval_at(i); 1502 if (interval != NULL) { 1503 assert(find_interval(interval, intervals), "Lists do not contain same intervals"); 1504 } else { 1505 null_count++; 1506 } 1507 } 1508 1509 assert(interval_count() - null_count == intervals->length(), 1510 "Sorted list should contain the same amount of non-NULL intervals as unsorted list"); 1511 1512 return true; 1513 } 1514 #endif 1515 1516 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { 1517 if (*prev != NULL) { 1518 (*prev)->set_next(interval); 1519 } else { 1520 *first = interval; 1521 } 1522 *prev = interval; 1523 } 1524 1525 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { 1526 assert(is_sorted(_sorted_intervals), "interval list is not sorted"); 1527 1528 *list1 = *list2 = Interval::end(); 1529 1530 Interval* list1_prev = NULL; 1531 Interval* list2_prev = NULL; 1532 Interval* v; 1533 1534 const int n = _sorted_intervals->length(); 1535 for (int i = 0; i < n; i++) { 1536 v = _sorted_intervals->at(i); 1537 if (v == NULL) continue; 1538 1539 if (is_list1(v)) { 1540 add_to_list(list1, &list1_prev, v); 1541 } else if (is_list2 == NULL || is_list2(v)) { 1542 add_to_list(list2, &list2_prev, v); 1543 } 1544 } 1545 1546 if (list1_prev != NULL) list1_prev->set_next(Interval::end()); 1547 if (list2_prev != NULL) list2_prev->set_next(Interval::end()); 1548 1549 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1550 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1551 } 1552 1553 1554 void LinearScan::sort_intervals_before_allocation() { 1555 TIME_LINEAR_SCAN(timer_sort_intervals_before); 1556 1557 if (_needs_full_resort) { 1558 // There is no known reason why this should occur but just in case... 1559 assert(false, "should never occur"); 1560 // Re-sort existing interval list because an Interval::from() has changed 1561 _sorted_intervals->sort(interval_cmp); 1562 _needs_full_resort = false; 1563 } 1564 1565 IntervalList* unsorted_list = &_intervals; 1566 int unsorted_len = unsorted_list->length(); 1567 int sorted_len = 0; 1568 int unsorted_idx; 1569 int sorted_idx = 0; 1570 int sorted_from_max = -1; 1571 1572 // calc number of items for sorted list (sorted list must not contain NULL values) 1573 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1574 if (unsorted_list->at(unsorted_idx) != NULL) { 1575 sorted_len++; 1576 } 1577 } 1578 IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL); 1579 1580 // special sorting algorithm: the original interval-list is almost sorted, 1581 // only some intervals are swapped. So this is much faster than a complete QuickSort 1582 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1583 Interval* cur_interval = unsorted_list->at(unsorted_idx); 1584 1585 if (cur_interval != NULL) { 1586 int cur_from = cur_interval->from(); 1587 1588 if (sorted_from_max <= cur_from) { 1589 sorted_list->at_put(sorted_idx++, cur_interval); 1590 sorted_from_max = cur_interval->from(); 1591 } else { 1592 // the asumption that the intervals are already sorted failed, 1593 // so this interval must be sorted in manually 1594 int j; 1595 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { 1596 sorted_list->at_put(j + 1, sorted_list->at(j)); 1597 } 1598 sorted_list->at_put(j + 1, cur_interval); 1599 sorted_idx++; 1600 } 1601 } 1602 } 1603 _sorted_intervals = sorted_list; 1604 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1605 } 1606 1607 void LinearScan::sort_intervals_after_allocation() { 1608 TIME_LINEAR_SCAN(timer_sort_intervals_after); 1609 1610 if (_needs_full_resort) { 1611 // Re-sort existing interval list because an Interval::from() has changed 1612 _sorted_intervals->sort(interval_cmp); 1613 _needs_full_resort = false; 1614 } 1615 1616 IntervalArray* old_list = _sorted_intervals; 1617 IntervalList* new_list = _new_intervals_from_allocation; 1618 int old_len = old_list->length(); 1619 int new_len = new_list->length(); 1620 1621 if (new_len == 0) { 1622 // no intervals have been added during allocation, so sorted list is already up to date 1623 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1624 return; 1625 } 1626 1627 // conventional sort-algorithm for new intervals 1628 new_list->sort(interval_cmp); 1629 1630 // merge old and new list (both already sorted) into one combined list 1631 int combined_list_len = old_len + new_len; 1632 IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL); 1633 int old_idx = 0; 1634 int new_idx = 0; 1635 1636 while (old_idx + new_idx < old_len + new_len) { 1637 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { 1638 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); 1639 old_idx++; 1640 } else { 1641 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); 1642 new_idx++; 1643 } 1644 } 1645 1646 _sorted_intervals = combined_list; 1647 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1648 } 1649 1650 1651 void LinearScan::allocate_registers() { 1652 TIME_LINEAR_SCAN(timer_allocate_registers); 1653 1654 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; 1655 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; 1656 1657 // allocate cpu registers 1658 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, 1659 is_precolored_cpu_interval, is_virtual_cpu_interval); 1660 1661 // allocate fpu registers 1662 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, 1663 is_precolored_fpu_interval, is_virtual_fpu_interval); 1664 1665 // the fpu interval allocation cannot be moved down below with the fpu section as 1666 // the cpu_lsw.walk() changes interval positions. 1667 1668 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); 1669 cpu_lsw.walk(); 1670 cpu_lsw.finish_allocation(); 1671 1672 if (has_fpu_registers()) { 1673 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); 1674 fpu_lsw.walk(); 1675 fpu_lsw.finish_allocation(); 1676 } 1677 } 1678 1679 1680 // ********** Phase 6: resolve data flow 1681 // (insert moves at edges between blocks if intervals have been split) 1682 1683 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode 1684 // instead of returning NULL 1685 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { 1686 Interval* result = interval->split_child_at_op_id(op_id, mode); 1687 if (result != NULL) { 1688 return result; 1689 } 1690 1691 assert(false, "must find an interval, but do a clean bailout in product mode"); 1692 result = new Interval(LIR_OprDesc::vreg_base); 1693 result->assign_reg(0); 1694 result->set_type(T_INT); 1695 BAILOUT_("LinearScan: interval is NULL", result); 1696 } 1697 1698 1699 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { 1700 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1701 assert(interval_at(reg_num) != NULL, "no interval found"); 1702 1703 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); 1704 } 1705 1706 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { 1707 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1708 assert(interval_at(reg_num) != NULL, "no interval found"); 1709 1710 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); 1711 } 1712 1713 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { 1714 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1715 assert(interval_at(reg_num) != NULL, "no interval found"); 1716 1717 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); 1718 } 1719 1720 1721 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1722 DEBUG_ONLY(move_resolver.check_empty()); 1723 1724 const int num_regs = num_virtual_regs(); 1725 const int size = live_set_size(); 1726 const ResourceBitMap live_at_edge = to_block->live_in(); 1727 1728 // visit all registers where the live_at_edge bit is set 1729 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 1730 assert(r < num_regs, "live information set for not exisiting interval"); 1731 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); 1732 1733 Interval* from_interval = interval_at_block_end(from_block, r); 1734 Interval* to_interval = interval_at_block_begin(to_block, r); 1735 1736 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { 1737 // need to insert move instruction 1738 move_resolver.add_mapping(from_interval, to_interval); 1739 } 1740 } 1741 } 1742 1743 1744 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1745 if (from_block->number_of_sux() <= 1) { 1746 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); 1747 1748 LIR_OpList* instructions = from_block->lir()->instructions_list(); 1749 LIR_OpBranch* branch = instructions->last()->as_OpBranch(); 1750 if (branch != NULL) { 1751 // insert moves before branch 1752 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 1753 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); 1754 } else { 1755 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); 1756 } 1757 1758 } else { 1759 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); 1760 #ifdef ASSERT 1761 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); 1762 1763 // because the number of predecessor edges matches the number of 1764 // successor edges, blocks which are reached by switch statements 1765 // may have be more than one predecessor but it will be guaranteed 1766 // that all predecessors will be the same. 1767 for (int i = 0; i < to_block->number_of_preds(); i++) { 1768 assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); 1769 } 1770 #endif 1771 1772 move_resolver.set_insert_position(to_block->lir(), 0); 1773 } 1774 } 1775 1776 1777 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split 1778 void LinearScan::resolve_data_flow() { 1779 TIME_LINEAR_SCAN(timer_resolve_data_flow); 1780 1781 int num_blocks = block_count(); 1782 MoveResolver move_resolver(this); 1783 ResourceBitMap block_completed(num_blocks); 1784 ResourceBitMap already_resolved(num_blocks); 1785 1786 int i; 1787 for (i = 0; i < num_blocks; i++) { 1788 BlockBegin* block = block_at(i); 1789 1790 // check if block has only one predecessor and only one successor 1791 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { 1792 LIR_OpList* instructions = block->lir()->instructions_list(); 1793 assert(instructions->at(0)->code() == lir_label, "block must start with label"); 1794 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); 1795 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); 1796 1797 // check if block is empty (only label and branch) 1798 if (instructions->length() == 2) { 1799 BlockBegin* pred = block->pred_at(0); 1800 BlockBegin* sux = block->sux_at(0); 1801 1802 // prevent optimization of two consecutive blocks 1803 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { 1804 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); 1805 block_completed.set_bit(block->linear_scan_number()); 1806 1807 // directly resolve between pred and sux (without looking at the empty block between) 1808 resolve_collect_mappings(pred, sux, move_resolver); 1809 if (move_resolver.has_mappings()) { 1810 move_resolver.set_insert_position(block->lir(), 0); 1811 move_resolver.resolve_and_append_moves(); 1812 } 1813 } 1814 } 1815 } 1816 } 1817 1818 1819 for (i = 0; i < num_blocks; i++) { 1820 if (!block_completed.at(i)) { 1821 BlockBegin* from_block = block_at(i); 1822 already_resolved.set_from(block_completed); 1823 1824 int num_sux = from_block->number_of_sux(); 1825 for (int s = 0; s < num_sux; s++) { 1826 BlockBegin* to_block = from_block->sux_at(s); 1827 1828 // check for duplicate edges between the same blocks (can happen with switch blocks) 1829 if (!already_resolved.at(to_block->linear_scan_number())) { 1830 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); 1831 already_resolved.set_bit(to_block->linear_scan_number()); 1832 1833 // collect all intervals that have been split between from_block and to_block 1834 resolve_collect_mappings(from_block, to_block, move_resolver); 1835 if (move_resolver.has_mappings()) { 1836 resolve_find_insert_pos(from_block, to_block, move_resolver); 1837 move_resolver.resolve_and_append_moves(); 1838 } 1839 } 1840 } 1841 } 1842 } 1843 } 1844 1845 1846 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { 1847 if (interval_at(reg_num) == NULL) { 1848 // if a phi function is never used, no interval is created -> ignore this 1849 return; 1850 } 1851 1852 Interval* interval = interval_at_block_begin(block, reg_num); 1853 int reg = interval->assigned_reg(); 1854 int regHi = interval->assigned_regHi(); 1855 1856 if ((reg < nof_regs && interval->always_in_memory()) || 1857 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { 1858 // the interval is split to get a short range that is located on the stack 1859 // in the following two cases: 1860 // * the interval started in memory (e.g. method parameter), but is currently in a register 1861 // this is an optimization for exception handling that reduces the number of moves that 1862 // are necessary for resolving the states when an exception uses this exception handler 1863 // * the interval would be on the fpu stack at the begin of the exception handler 1864 // this is not allowed because of the complicated fpu stack handling on Intel 1865 1866 // range that will be spilled to memory 1867 int from_op_id = block->first_lir_instruction_id(); 1868 int to_op_id = from_op_id + 1; // short live range of length 1 1869 assert(interval->from() <= from_op_id && interval->to() >= to_op_id, 1870 "no split allowed between exception entry and first instruction"); 1871 1872 if (interval->from() != from_op_id) { 1873 // the part before from_op_id is unchanged 1874 interval = interval->split(from_op_id); 1875 interval->assign_reg(reg, regHi); 1876 append_interval(interval); 1877 } else { 1878 _needs_full_resort = true; 1879 } 1880 assert(interval->from() == from_op_id, "must be true now"); 1881 1882 Interval* spilled_part = interval; 1883 if (interval->to() != to_op_id) { 1884 // the part after to_op_id is unchanged 1885 spilled_part = interval->split_from_start(to_op_id); 1886 append_interval(spilled_part); 1887 move_resolver.add_mapping(spilled_part, interval); 1888 } 1889 assign_spill_slot(spilled_part); 1890 1891 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); 1892 } 1893 } 1894 1895 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { 1896 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); 1897 DEBUG_ONLY(move_resolver.check_empty()); 1898 1899 // visit all registers where the live_in bit is set 1900 int size = live_set_size(); 1901 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1902 resolve_exception_entry(block, r, move_resolver); 1903 } 1904 1905 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1906 for_each_phi_fun(block, phi, 1907 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) 1908 ); 1909 1910 if (move_resolver.has_mappings()) { 1911 // insert moves after first instruction 1912 move_resolver.set_insert_position(block->lir(), 0); 1913 move_resolver.resolve_and_append_moves(); 1914 } 1915 } 1916 1917 1918 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { 1919 if (interval_at(reg_num) == NULL) { 1920 // if a phi function is never used, no interval is created -> ignore this 1921 return; 1922 } 1923 1924 // the computation of to_interval is equal to resolve_collect_mappings, 1925 // but from_interval is more complicated because of phi functions 1926 BlockBegin* to_block = handler->entry_block(); 1927 Interval* to_interval = interval_at_block_begin(to_block, reg_num); 1928 1929 if (phi != NULL) { 1930 // phi function of the exception entry block 1931 // no moves are created for this phi function in the LIR_Generator, so the 1932 // interval at the throwing instruction must be searched using the operands 1933 // of the phi function 1934 Value from_value = phi->operand_at(handler->phi_operand()); 1935 1936 // with phi functions it can happen that the same from_value is used in 1937 // multiple mappings, so notify move-resolver that this is allowed 1938 move_resolver.set_multiple_reads_allowed(); 1939 1940 Constant* con = from_value->as_Constant(); 1941 if (con != NULL && !con->is_pinned()) { 1942 // unpinned constants may have no register, so add mapping from constant to interval 1943 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); 1944 } else { 1945 // search split child at the throwing op_id 1946 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); 1947 move_resolver.add_mapping(from_interval, to_interval); 1948 } 1949 1950 } else { 1951 // no phi function, so use reg_num also for from_interval 1952 // search split child at the throwing op_id 1953 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); 1954 if (from_interval != to_interval) { 1955 // optimization to reduce number of moves: when to_interval is on stack and 1956 // the stack slot is known to be always correct, then no move is necessary 1957 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { 1958 move_resolver.add_mapping(from_interval, to_interval); 1959 } 1960 } 1961 } 1962 } 1963 1964 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { 1965 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); 1966 1967 DEBUG_ONLY(move_resolver.check_empty()); 1968 assert(handler->lir_op_id() == -1, "already processed this xhandler"); 1969 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); 1970 assert(handler->entry_code() == NULL, "code already present"); 1971 1972 // visit all registers where the live_in bit is set 1973 BlockBegin* block = handler->entry_block(); 1974 int size = live_set_size(); 1975 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1976 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); 1977 } 1978 1979 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1980 for_each_phi_fun(block, phi, 1981 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) 1982 ); 1983 1984 if (move_resolver.has_mappings()) { 1985 LIR_List* entry_code = new LIR_List(compilation()); 1986 move_resolver.set_insert_position(entry_code, 0); 1987 move_resolver.resolve_and_append_moves(); 1988 1989 entry_code->jump(handler->entry_block()); 1990 handler->set_entry_code(entry_code); 1991 } 1992 } 1993 1994 1995 void LinearScan::resolve_exception_handlers() { 1996 MoveResolver move_resolver(this); 1997 LIR_OpVisitState visitor; 1998 int num_blocks = block_count(); 1999 2000 int i; 2001 for (i = 0; i < num_blocks; i++) { 2002 BlockBegin* block = block_at(i); 2003 if (block->is_set(BlockBegin::exception_entry_flag)) { 2004 resolve_exception_entry(block, move_resolver); 2005 } 2006 } 2007 2008 for (i = 0; i < num_blocks; i++) { 2009 BlockBegin* block = block_at(i); 2010 LIR_List* ops = block->lir(); 2011 int num_ops = ops->length(); 2012 2013 // iterate all instructions of the block. skip the first because it is always a label 2014 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); 2015 for (int j = 1; j < num_ops; j++) { 2016 LIR_Op* op = ops->at(j); 2017 int op_id = op->id(); 2018 2019 if (op_id != -1 && has_info(op_id)) { 2020 // visit operation to collect all operands 2021 visitor.visit(op); 2022 assert(visitor.info_count() > 0, "should not visit otherwise"); 2023 2024 XHandlers* xhandlers = visitor.all_xhandler(); 2025 int n = xhandlers->length(); 2026 for (int k = 0; k < n; k++) { 2027 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); 2028 } 2029 2030 #ifdef ASSERT 2031 } else { 2032 visitor.visit(op); 2033 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 2034 #endif 2035 } 2036 } 2037 } 2038 } 2039 2040 2041 // ********** Phase 7: assign register numbers back to LIR 2042 // (includes computation of debug information and oop maps) 2043 2044 VMReg LinearScan::vm_reg_for_interval(Interval* interval) { 2045 VMReg reg = interval->cached_vm_reg(); 2046 if (!reg->is_valid() ) { 2047 reg = vm_reg_for_operand(operand_for_interval(interval)); 2048 interval->set_cached_vm_reg(reg); 2049 } 2050 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); 2051 return reg; 2052 } 2053 2054 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { 2055 assert(opr->is_oop(), "currently only implemented for oop operands"); 2056 return frame_map()->regname(opr); 2057 } 2058 2059 2060 LIR_Opr LinearScan::operand_for_interval(Interval* interval) { 2061 LIR_Opr opr = interval->cached_opr(); 2062 if (opr->is_illegal()) { 2063 opr = calc_operand_for_interval(interval); 2064 interval->set_cached_opr(opr); 2065 } 2066 2067 assert(opr == calc_operand_for_interval(interval), "wrong cached value"); 2068 return opr; 2069 } 2070 2071 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { 2072 int assigned_reg = interval->assigned_reg(); 2073 BasicType type = interval->type(); 2074 2075 if (assigned_reg >= nof_regs) { 2076 // stack slot 2077 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2078 return LIR_OprFact::stack(assigned_reg - nof_regs, type); 2079 2080 } else { 2081 // register 2082 switch (type) { 2083 case T_OBJECT: { 2084 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2085 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2086 return LIR_OprFact::single_cpu_oop(assigned_reg); 2087 } 2088 2089 case T_ADDRESS: { 2090 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2091 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2092 return LIR_OprFact::single_cpu_address(assigned_reg); 2093 } 2094 2095 case T_METADATA: { 2096 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2097 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2098 return LIR_OprFact::single_cpu_metadata(assigned_reg); 2099 } 2100 2101 #ifdef __SOFTFP__ 2102 case T_FLOAT: // fall through 2103 #endif // __SOFTFP__ 2104 case T_INT: { 2105 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2106 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2107 return LIR_OprFact::single_cpu(assigned_reg); 2108 } 2109 2110 #ifdef __SOFTFP__ 2111 case T_DOUBLE: // fall through 2112 #endif // __SOFTFP__ 2113 case T_LONG: { 2114 int assigned_regHi = interval->assigned_regHi(); 2115 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2116 assert(num_physical_regs(T_LONG) == 1 || 2117 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); 2118 2119 assert(assigned_reg != assigned_regHi, "invalid allocation"); 2120 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, 2121 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); 2122 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); 2123 if (requires_adjacent_regs(T_LONG)) { 2124 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); 2125 } 2126 2127 #ifdef _LP64 2128 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); 2129 #else 2130 #if defined(SPARC) || defined(PPC32) 2131 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); 2132 #else 2133 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); 2134 #endif // SPARC 2135 #endif // LP64 2136 } 2137 2138 #ifndef __SOFTFP__ 2139 case T_FLOAT: { 2140 #ifdef X86 2141 if (UseSSE >= 1) { 2142 int last_xmm_reg = pd_last_xmm_reg; 2143 #ifdef _LP64 2144 if (UseAVX < 3) { 2145 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 2146 } 2147 #endif 2148 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register"); 2149 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2150 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); 2151 } 2152 #endif 2153 2154 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2155 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2156 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); 2157 } 2158 2159 case T_DOUBLE: { 2160 #ifdef X86 2161 if (UseSSE >= 2) { 2162 int last_xmm_reg = pd_last_xmm_reg; 2163 #ifdef _LP64 2164 if (UseAVX < 3) { 2165 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 2166 } 2167 #endif 2168 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register"); 2169 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); 2170 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); 2171 } 2172 #endif 2173 2174 #ifdef SPARC 2175 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2176 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2177 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2178 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); 2179 #elif defined(ARM32) 2180 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2181 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2182 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2183 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); 2184 #else 2185 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2186 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); 2187 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); 2188 #endif 2189 return result; 2190 } 2191 #endif // __SOFTFP__ 2192 2193 default: { 2194 ShouldNotReachHere(); 2195 return LIR_OprFact::illegalOpr; 2196 } 2197 } 2198 } 2199 } 2200 2201 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { 2202 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); 2203 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); 2204 } 2205 2206 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { 2207 assert(opr->is_virtual(), "should not call this otherwise"); 2208 2209 Interval* interval = interval_at(opr->vreg_number()); 2210 assert(interval != NULL, "interval must exist"); 2211 2212 if (op_id != -1) { 2213 #ifdef ASSERT 2214 BlockBegin* block = block_of_op_with_id(op_id); 2215 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { 2216 // check if spill moves could have been appended at the end of this block, but 2217 // before the branch instruction. So the split child information for this branch would 2218 // be incorrect. 2219 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); 2220 if (branch != NULL) { 2221 if (block->live_out().at(opr->vreg_number())) { 2222 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 2223 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); 2224 } 2225 } 2226 } 2227 #endif 2228 2229 // operands are not changed when an interval is split during allocation, 2230 // so search the right interval here 2231 interval = split_child_at_op_id(interval, op_id, mode); 2232 } 2233 2234 LIR_Opr res = operand_for_interval(interval); 2235 2236 #ifdef X86 2237 // new semantic for is_last_use: not only set on definite end of interval, 2238 // but also before hole 2239 // This may still miss some cases (e.g. for dead values), but it is not necessary that the 2240 // last use information is completely correct 2241 // information is only needed for fpu stack allocation 2242 if (res->is_fpu_register()) { 2243 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { 2244 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); 2245 res = res->make_last_use(); 2246 } 2247 } 2248 #endif 2249 2250 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); 2251 2252 return res; 2253 } 2254 2255 2256 #ifdef ASSERT 2257 // some methods used to check correctness of debug information 2258 2259 void assert_no_register_values(GrowableArray<ScopeValue*>* values) { 2260 if (values == NULL) { 2261 return; 2262 } 2263 2264 for (int i = 0; i < values->length(); i++) { 2265 ScopeValue* value = values->at(i); 2266 2267 if (value->is_location()) { 2268 Location location = ((LocationValue*)value)->location(); 2269 assert(location.where() == Location::on_stack, "value is in register"); 2270 } 2271 } 2272 } 2273 2274 void assert_no_register_values(GrowableArray<MonitorValue*>* values) { 2275 if (values == NULL) { 2276 return; 2277 } 2278 2279 for (int i = 0; i < values->length(); i++) { 2280 MonitorValue* value = values->at(i); 2281 2282 if (value->owner()->is_location()) { 2283 Location location = ((LocationValue*)value->owner())->location(); 2284 assert(location.where() == Location::on_stack, "owner is in register"); 2285 } 2286 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); 2287 } 2288 } 2289 2290 void assert_equal(Location l1, Location l2) { 2291 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); 2292 } 2293 2294 void assert_equal(ScopeValue* v1, ScopeValue* v2) { 2295 if (v1->is_location()) { 2296 assert(v2->is_location(), ""); 2297 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); 2298 } else if (v1->is_constant_int()) { 2299 assert(v2->is_constant_int(), ""); 2300 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); 2301 } else if (v1->is_constant_double()) { 2302 assert(v2->is_constant_double(), ""); 2303 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); 2304 } else if (v1->is_constant_long()) { 2305 assert(v2->is_constant_long(), ""); 2306 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); 2307 } else if (v1->is_constant_oop()) { 2308 assert(v2->is_constant_oop(), ""); 2309 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); 2310 } else { 2311 ShouldNotReachHere(); 2312 } 2313 } 2314 2315 void assert_equal(MonitorValue* m1, MonitorValue* m2) { 2316 assert_equal(m1->owner(), m2->owner()); 2317 assert_equal(m1->basic_lock(), m2->basic_lock()); 2318 } 2319 2320 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { 2321 assert(d1->scope() == d2->scope(), "not equal"); 2322 assert(d1->bci() == d2->bci(), "not equal"); 2323 2324 if (d1->locals() != NULL) { 2325 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); 2326 assert(d1->locals()->length() == d2->locals()->length(), "not equal"); 2327 for (int i = 0; i < d1->locals()->length(); i++) { 2328 assert_equal(d1->locals()->at(i), d2->locals()->at(i)); 2329 } 2330 } else { 2331 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); 2332 } 2333 2334 if (d1->expressions() != NULL) { 2335 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); 2336 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); 2337 for (int i = 0; i < d1->expressions()->length(); i++) { 2338 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); 2339 } 2340 } else { 2341 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); 2342 } 2343 2344 if (d1->monitors() != NULL) { 2345 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); 2346 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); 2347 for (int i = 0; i < d1->monitors()->length(); i++) { 2348 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); 2349 } 2350 } else { 2351 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); 2352 } 2353 2354 if (d1->caller() != NULL) { 2355 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); 2356 assert_equal(d1->caller(), d2->caller()); 2357 } else { 2358 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); 2359 } 2360 } 2361 2362 void check_stack_depth(CodeEmitInfo* info, int stack_end) { 2363 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { 2364 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); 2365 switch (code) { 2366 case Bytecodes::_ifnull : // fall through 2367 case Bytecodes::_ifnonnull : // fall through 2368 case Bytecodes::_ifeq : // fall through 2369 case Bytecodes::_ifne : // fall through 2370 case Bytecodes::_iflt : // fall through 2371 case Bytecodes::_ifge : // fall through 2372 case Bytecodes::_ifgt : // fall through 2373 case Bytecodes::_ifle : // fall through 2374 case Bytecodes::_if_icmpeq : // fall through 2375 case Bytecodes::_if_icmpne : // fall through 2376 case Bytecodes::_if_icmplt : // fall through 2377 case Bytecodes::_if_icmpge : // fall through 2378 case Bytecodes::_if_icmpgt : // fall through 2379 case Bytecodes::_if_icmple : // fall through 2380 case Bytecodes::_if_acmpeq : // fall through 2381 case Bytecodes::_if_acmpne : 2382 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); 2383 break; 2384 } 2385 } 2386 } 2387 2388 #endif // ASSERT 2389 2390 2391 IntervalWalker* LinearScan::init_compute_oop_maps() { 2392 // setup lists of potential oops for walking 2393 Interval* oop_intervals; 2394 Interval* non_oop_intervals; 2395 2396 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); 2397 2398 // intervals that have no oops inside need not to be processed 2399 // to ensure a walking until the last instruction id, add a dummy interval 2400 // with a high operation id 2401 non_oop_intervals = new Interval(any_reg); 2402 non_oop_intervals->add_range(max_jint - 2, max_jint - 1); 2403 2404 return new IntervalWalker(this, oop_intervals, non_oop_intervals); 2405 } 2406 2407 2408 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { 2409 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); 2410 2411 // walk before the current operation -> intervals that start at 2412 // the operation (= output operands of the operation) are not 2413 // included in the oop map 2414 iw->walk_before(op->id()); 2415 2416 int frame_size = frame_map()->framesize(); 2417 int arg_count = frame_map()->oop_map_arg_count(); 2418 OopMap* map = new OopMap(frame_size, arg_count); 2419 2420 // Iterate through active intervals 2421 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { 2422 int assigned_reg = interval->assigned_reg(); 2423 2424 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); 2425 assert(interval->assigned_regHi() == any_reg, "oop must be single word"); 2426 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); 2427 2428 // Check if this range covers the instruction. Intervals that 2429 // start or end at the current operation are not included in the 2430 // oop map, except in the case of patching moves. For patching 2431 // moves, any intervals which end at this instruction are included 2432 // in the oop map since we may safepoint while doing the patch 2433 // before we've consumed the inputs. 2434 if (op->is_patching() || op->id() < interval->current_to()) { 2435 2436 // caller-save registers must not be included into oop-maps at calls 2437 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); 2438 2439 VMReg name = vm_reg_for_interval(interval); 2440 set_oop(map, name); 2441 2442 // Spill optimization: when the stack value is guaranteed to be always correct, 2443 // then it must be added to the oop map even if the interval is currently in a register 2444 if (interval->always_in_memory() && 2445 op->id() > interval->spill_definition_pos() && 2446 interval->assigned_reg() != interval->canonical_spill_slot()) { 2447 assert(interval->spill_definition_pos() > 0, "position not set correctly"); 2448 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); 2449 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); 2450 2451 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); 2452 } 2453 } 2454 } 2455 2456 // add oops from lock stack 2457 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); 2458 int locks_count = info->stack()->total_locks_size(); 2459 for (int i = 0; i < locks_count; i++) { 2460 set_oop(map, frame_map()->monitor_object_regname(i)); 2461 } 2462 2463 return map; 2464 } 2465 2466 2467 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { 2468 assert(visitor.info_count() > 0, "no oop map needed"); 2469 2470 // compute oop_map only for first CodeEmitInfo 2471 // because it is (in most cases) equal for all other infos of the same operation 2472 CodeEmitInfo* first_info = visitor.info_at(0); 2473 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); 2474 2475 for (int i = 0; i < visitor.info_count(); i++) { 2476 CodeEmitInfo* info = visitor.info_at(i); 2477 OopMap* oop_map = first_oop_map; 2478 2479 // compute worst case interpreter size in case of a deoptimization 2480 _compilation->update_interpreter_frame_size(info->interpreter_frame_size()); 2481 2482 if (info->stack()->locks_size() != first_info->stack()->locks_size()) { 2483 // this info has a different number of locks then the precomputed oop map 2484 // (possible for lock and unlock instructions) -> compute oop map with 2485 // correct lock information 2486 oop_map = compute_oop_map(iw, op, info, visitor.has_call()); 2487 } 2488 2489 if (info->_oop_map == NULL) { 2490 info->_oop_map = oop_map; 2491 } else { 2492 // a CodeEmitInfo can not be shared between different LIR-instructions 2493 // because interval splitting can occur anywhere between two instructions 2494 // and so the oop maps must be different 2495 // -> check if the already set oop_map is exactly the one calculated for this operation 2496 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); 2497 } 2498 } 2499 } 2500 2501 2502 // frequently used constants 2503 // Allocate them with new so they are never destroyed (otherwise, a 2504 // forced exit could destroy these objects while they are still in 2505 // use). 2506 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL); 2507 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1); 2508 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0); 2509 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1); 2510 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2); 2511 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location()); 2512 2513 void LinearScan::init_compute_debug_info() { 2514 // cache for frequently used scope values 2515 // (cpu registers and stack slots) 2516 int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2; 2517 _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL); 2518 } 2519 2520 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { 2521 Location loc; 2522 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { 2523 bailout("too large frame"); 2524 } 2525 ScopeValue* object_scope_value = new LocationValue(loc); 2526 2527 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { 2528 bailout("too large frame"); 2529 } 2530 return new MonitorValue(object_scope_value, loc); 2531 } 2532 2533 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { 2534 Location loc; 2535 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { 2536 bailout("too large frame"); 2537 } 2538 return new LocationValue(loc); 2539 } 2540 2541 2542 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2543 assert(opr->is_constant(), "should not be called otherwise"); 2544 2545 LIR_Const* c = opr->as_constant_ptr(); 2546 BasicType t = c->type(); 2547 switch (t) { 2548 case T_OBJECT: { 2549 jobject value = c->as_jobject(); 2550 if (value == NULL) { 2551 scope_values->append(_oop_null_scope_value); 2552 } else { 2553 scope_values->append(new ConstantOopWriteValue(c->as_jobject())); 2554 } 2555 return 1; 2556 } 2557 2558 case T_INT: // fall through 2559 case T_FLOAT: { 2560 int value = c->as_jint_bits(); 2561 switch (value) { 2562 case -1: scope_values->append(_int_m1_scope_value); break; 2563 case 0: scope_values->append(_int_0_scope_value); break; 2564 case 1: scope_values->append(_int_1_scope_value); break; 2565 case 2: scope_values->append(_int_2_scope_value); break; 2566 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; 2567 } 2568 return 1; 2569 } 2570 2571 case T_LONG: // fall through 2572 case T_DOUBLE: { 2573 #ifdef _LP64 2574 scope_values->append(_int_0_scope_value); 2575 scope_values->append(new ConstantLongValue(c->as_jlong_bits())); 2576 #else 2577 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { 2578 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2579 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2580 } else { 2581 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2582 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2583 } 2584 #endif 2585 return 2; 2586 } 2587 2588 case T_ADDRESS: { 2589 #ifdef _LP64 2590 scope_values->append(new ConstantLongValue(c->as_jint())); 2591 #else 2592 scope_values->append(new ConstantIntValue(c->as_jint())); 2593 #endif 2594 return 1; 2595 } 2596 2597 default: 2598 ShouldNotReachHere(); 2599 return -1; 2600 } 2601 } 2602 2603 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2604 if (opr->is_single_stack()) { 2605 int stack_idx = opr->single_stack_ix(); 2606 bool is_oop = opr->is_oop_register(); 2607 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); 2608 2609 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2610 if (sv == NULL) { 2611 Location::Type loc_type = is_oop ? Location::oop : Location::normal; 2612 sv = location_for_name(stack_idx, loc_type); 2613 _scope_value_cache.at_put(cache_idx, sv); 2614 } 2615 2616 // check if cached value is correct 2617 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); 2618 2619 scope_values->append(sv); 2620 return 1; 2621 2622 } else if (opr->is_single_cpu()) { 2623 bool is_oop = opr->is_oop_register(); 2624 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); 2625 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); 2626 2627 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2628 if (sv == NULL) { 2629 Location::Type loc_type = is_oop ? Location::oop : int_loc_type; 2630 VMReg rname = frame_map()->regname(opr); 2631 sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2632 _scope_value_cache.at_put(cache_idx, sv); 2633 } 2634 2635 // check if cached value is correct 2636 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); 2637 2638 scope_values->append(sv); 2639 return 1; 2640 2641 #ifdef X86 2642 } else if (opr->is_single_xmm()) { 2643 VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); 2644 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); 2645 2646 scope_values->append(sv); 2647 return 1; 2648 #endif 2649 2650 } else if (opr->is_single_fpu()) { 2651 #ifdef X86 2652 // the exact location of fpu stack values is only known 2653 // during fpu stack allocation, so the stack allocator object 2654 // must be present 2655 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2656 assert(_fpu_stack_allocator != NULL, "must be present"); 2657 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2658 #endif 2659 2660 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; 2661 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); 2662 #ifndef __SOFTFP__ 2663 #ifndef VM_LITTLE_ENDIAN 2664 // On S390 a (single precision) float value occupies only the high 2665 // word of the full double register. So when the double register is 2666 // stored to memory (e.g. by the RegisterSaver), then the float value 2667 // is found at offset 0. I.e. the code below is not needed on S390. 2668 #ifndef S390 2669 if (! float_saved_as_double) { 2670 // On big endian system, we may have an issue if float registers use only 2671 // the low half of the (same) double registers. 2672 // Both the float and the double could have the same regnr but would correspond 2673 // to two different addresses once saved. 2674 2675 // get next safely (no assertion checks) 2676 VMReg next = VMRegImpl::as_VMReg(1+rname->value()); 2677 if (next->is_reg() && 2678 (next->as_FloatRegister() == rname->as_FloatRegister())) { 2679 // the back-end does use the same numbering for the double and the float 2680 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float 2681 } 2682 } 2683 #endif // !S390 2684 #endif 2685 #endif 2686 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2687 2688 scope_values->append(sv); 2689 return 1; 2690 2691 } else { 2692 // double-size operands 2693 2694 ScopeValue* first; 2695 ScopeValue* second; 2696 2697 if (opr->is_double_stack()) { 2698 #ifdef _LP64 2699 Location loc1; 2700 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; 2701 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { 2702 bailout("too large frame"); 2703 } 2704 // Does this reverse on x86 vs. sparc? 2705 first = new LocationValue(loc1); 2706 second = _int_0_scope_value; 2707 #else 2708 Location loc1, loc2; 2709 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { 2710 bailout("too large frame"); 2711 } 2712 first = new LocationValue(loc1); 2713 second = new LocationValue(loc2); 2714 #endif // _LP64 2715 2716 } else if (opr->is_double_cpu()) { 2717 #ifdef _LP64 2718 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2719 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); 2720 second = _int_0_scope_value; 2721 #else 2722 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2723 VMReg rname_second = opr->as_register_hi()->as_VMReg(); 2724 2725 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { 2726 // lo/hi and swapped relative to first and second, so swap them 2727 VMReg tmp = rname_first; 2728 rname_first = rname_second; 2729 rname_second = tmp; 2730 } 2731 2732 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2733 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2734 #endif //_LP64 2735 2736 2737 #ifdef X86 2738 } else if (opr->is_double_xmm()) { 2739 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); 2740 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); 2741 # ifdef _LP64 2742 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2743 second = _int_0_scope_value; 2744 # else 2745 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2746 // %%% This is probably a waste but we'll keep things as they were for now 2747 if (true) { 2748 VMReg rname_second = rname_first->next(); 2749 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2750 } 2751 # endif 2752 #endif 2753 2754 } else if (opr->is_double_fpu()) { 2755 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of 2756 // the double as float registers in the native ordering. On X86, 2757 // fpu_regnrLo is a FPU stack slot whose VMReg represents 2758 // the low-order word of the double and fpu_regnrLo + 1 is the 2759 // name for the other half. *first and *second must represent the 2760 // least and most significant words, respectively. 2761 2762 #ifdef X86 2763 // the exact location of fpu stack values is only known 2764 // during fpu stack allocation, so the stack allocator object 2765 // must be present 2766 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2767 assert(_fpu_stack_allocator != NULL, "must be present"); 2768 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2769 2770 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); 2771 #endif 2772 #ifdef SPARC 2773 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); 2774 #endif 2775 #ifdef ARM32 2776 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); 2777 #endif 2778 #ifdef PPC32 2779 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); 2780 #endif 2781 2782 #ifdef VM_LITTLE_ENDIAN 2783 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo()); 2784 #else 2785 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); 2786 #endif 2787 2788 #ifdef _LP64 2789 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2790 second = _int_0_scope_value; 2791 #else 2792 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2793 // %%% This is probably a waste but we'll keep things as they were for now 2794 if (true) { 2795 VMReg rname_second = rname_first->next(); 2796 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2797 } 2798 #endif 2799 2800 } else { 2801 ShouldNotReachHere(); 2802 first = NULL; 2803 second = NULL; 2804 } 2805 2806 assert(first != NULL && second != NULL, "must be set"); 2807 // The convention the interpreter uses is that the second local 2808 // holds the first raw word of the native double representation. 2809 // This is actually reasonable, since locals and stack arrays 2810 // grow downwards in all implementations. 2811 // (If, on some machine, the interpreter's Java locals or stack 2812 // were to grow upwards, the embedded doubles would be word-swapped.) 2813 scope_values->append(second); 2814 scope_values->append(first); 2815 return 2; 2816 } 2817 } 2818 2819 2820 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) { 2821 if (value != NULL) { 2822 LIR_Opr opr = value->operand(); 2823 Constant* con = value->as_Constant(); 2824 2825 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); 2826 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 2827 2828 if (con != NULL && !con->is_pinned() && !opr->is_constant()) { 2829 // Unpinned constants may have a virtual operand for a part of the lifetime 2830 // or may be illegal when it was optimized away, 2831 // so always use a constant operand 2832 opr = LIR_OprFact::value_type(con->type()); 2833 } 2834 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); 2835 2836 if (opr->is_virtual()) { 2837 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; 2838 2839 BlockBegin* block = block_of_op_with_id(op_id); 2840 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { 2841 // generating debug information for the last instruction of a block. 2842 // if this instruction is a branch, spill moves are inserted before this branch 2843 // and so the wrong operand would be returned (spill moves at block boundaries are not 2844 // considered in the live ranges of intervals) 2845 // Solution: use the first op_id of the branch target block instead. 2846 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { 2847 if (block->live_out().at(opr->vreg_number())) { 2848 op_id = block->sux_at(0)->first_lir_instruction_id(); 2849 mode = LIR_OpVisitState::outputMode; 2850 } 2851 } 2852 } 2853 2854 // Get current location of operand 2855 // The operand must be live because debug information is considered when building the intervals 2856 // if the interval is not live, color_lir_opr will cause an assertion failure 2857 opr = color_lir_opr(opr, op_id, mode); 2858 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); 2859 2860 // Append to ScopeValue array 2861 return append_scope_value_for_operand(opr, scope_values); 2862 2863 } else { 2864 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); 2865 assert(opr->is_constant(), "operand must be constant"); 2866 2867 return append_scope_value_for_constant(opr, scope_values); 2868 } 2869 } else { 2870 // append a dummy value because real value not needed 2871 scope_values->append(_illegal_value); 2872 return 1; 2873 } 2874 } 2875 2876 2877 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) { 2878 IRScopeDebugInfo* caller_debug_info = NULL; 2879 2880 ValueStack* caller_state = cur_state->caller_state(); 2881 if (caller_state != NULL) { 2882 // process recursively to compute outermost scope first 2883 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state); 2884 } 2885 2886 // initialize these to null. 2887 // If we don't need deopt info or there are no locals, expressions or monitors, 2888 // then these get recorded as no information and avoids the allocation of 0 length arrays. 2889 GrowableArray<ScopeValue*>* locals = NULL; 2890 GrowableArray<ScopeValue*>* expressions = NULL; 2891 GrowableArray<MonitorValue*>* monitors = NULL; 2892 2893 // describe local variable values 2894 int nof_locals = cur_state->locals_size(); 2895 if (nof_locals > 0) { 2896 locals = new GrowableArray<ScopeValue*>(nof_locals); 2897 2898 int pos = 0; 2899 while (pos < nof_locals) { 2900 assert(pos < cur_state->locals_size(), "why not?"); 2901 2902 Value local = cur_state->local_at(pos); 2903 pos += append_scope_value(op_id, local, locals); 2904 2905 assert(locals->length() == pos, "must match"); 2906 } 2907 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); 2908 assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); 2909 } else if (cur_scope->method()->max_locals() > 0) { 2910 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be"); 2911 nof_locals = cur_scope->method()->max_locals(); 2912 locals = new GrowableArray<ScopeValue*>(nof_locals); 2913 for(int i = 0; i < nof_locals; i++) { 2914 locals->append(_illegal_value); 2915 } 2916 } 2917 2918 // describe expression stack 2919 int nof_stack = cur_state->stack_size(); 2920 if (nof_stack > 0) { 2921 expressions = new GrowableArray<ScopeValue*>(nof_stack); 2922 2923 int pos = 0; 2924 while (pos < nof_stack) { 2925 Value expression = cur_state->stack_at_inc(pos); 2926 append_scope_value(op_id, expression, expressions); 2927 2928 assert(expressions->length() == pos, "must match"); 2929 } 2930 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries"); 2931 } 2932 2933 // describe monitors 2934 int nof_locks = cur_state->locks_size(); 2935 if (nof_locks > 0) { 2936 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0; 2937 monitors = new GrowableArray<MonitorValue*>(nof_locks); 2938 for (int i = 0; i < nof_locks; i++) { 2939 monitors->append(location_for_monitor_index(lock_offset + i)); 2940 } 2941 } 2942 2943 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info); 2944 } 2945 2946 2947 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { 2948 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); 2949 2950 IRScope* innermost_scope = info->scope(); 2951 ValueStack* innermost_state = info->stack(); 2952 2953 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); 2954 2955 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size())); 2956 2957 if (info->_scope_debug_info == NULL) { 2958 // compute debug information 2959 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state); 2960 } else { 2961 // debug information already set. Check that it is correct from the current point of view 2962 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state))); 2963 } 2964 } 2965 2966 2967 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { 2968 LIR_OpVisitState visitor; 2969 int num_inst = instructions->length(); 2970 bool has_dead = false; 2971 2972 for (int j = 0; j < num_inst; j++) { 2973 LIR_Op* op = instructions->at(j); 2974 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves 2975 has_dead = true; 2976 continue; 2977 } 2978 int op_id = op->id(); 2979 2980 // visit instruction to get list of operands 2981 visitor.visit(op); 2982 2983 // iterate all modes of the visitor and process all virtual operands 2984 for_each_visitor_mode(mode) { 2985 int n = visitor.opr_count(mode); 2986 for (int k = 0; k < n; k++) { 2987 LIR_Opr opr = visitor.opr_at(mode, k); 2988 if (opr->is_virtual_register()) { 2989 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); 2990 } 2991 } 2992 } 2993 2994 if (visitor.info_count() > 0) { 2995 // exception handling 2996 if (compilation()->has_exception_handlers()) { 2997 XHandlers* xhandlers = visitor.all_xhandler(); 2998 int n = xhandlers->length(); 2999 for (int k = 0; k < n; k++) { 3000 XHandler* handler = xhandlers->handler_at(k); 3001 if (handler->entry_code() != NULL) { 3002 assign_reg_num(handler->entry_code()->instructions_list(), NULL); 3003 } 3004 } 3005 } else { 3006 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 3007 } 3008 3009 // compute oop map 3010 assert(iw != NULL, "needed for compute_oop_map"); 3011 compute_oop_map(iw, visitor, op); 3012 3013 // compute debug information 3014 if (!use_fpu_stack_allocation()) { 3015 // compute debug information if fpu stack allocation is not needed. 3016 // when fpu stack allocation is needed, the debug information can not 3017 // be computed here because the exact location of fpu operands is not known 3018 // -> debug information is created inside the fpu stack allocator 3019 int n = visitor.info_count(); 3020 for (int k = 0; k < n; k++) { 3021 compute_debug_info(visitor.info_at(k), op_id); 3022 } 3023 } 3024 } 3025 3026 #ifdef ASSERT 3027 // make sure we haven't made the op invalid. 3028 op->verify(); 3029 #endif 3030 3031 // remove useless moves 3032 if (op->code() == lir_move) { 3033 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 3034 LIR_Op1* move = (LIR_Op1*)op; 3035 LIR_Opr src = move->in_opr(); 3036 LIR_Opr dst = move->result_opr(); 3037 if (dst == src || 3038 (!dst->is_pointer() && !src->is_pointer() && 3039 src->is_same_register(dst))) { 3040 instructions->at_put(j, NULL); 3041 has_dead = true; 3042 } 3043 } 3044 } 3045 3046 if (has_dead) { 3047 // iterate all instructions of the block and remove all null-values. 3048 int insert_point = 0; 3049 for (int j = 0; j < num_inst; j++) { 3050 LIR_Op* op = instructions->at(j); 3051 if (op != NULL) { 3052 if (insert_point != j) { 3053 instructions->at_put(insert_point, op); 3054 } 3055 insert_point++; 3056 } 3057 } 3058 instructions->trunc_to(insert_point); 3059 } 3060 } 3061 3062 void LinearScan::assign_reg_num() { 3063 TIME_LINEAR_SCAN(timer_assign_reg_num); 3064 3065 init_compute_debug_info(); 3066 IntervalWalker* iw = init_compute_oop_maps(); 3067 3068 int num_blocks = block_count(); 3069 for (int i = 0; i < num_blocks; i++) { 3070 BlockBegin* block = block_at(i); 3071 assign_reg_num(block->lir()->instructions_list(), iw); 3072 } 3073 } 3074 3075 3076 void LinearScan::do_linear_scan() { 3077 NOT_PRODUCT(_total_timer.begin_method()); 3078 3079 number_instructions(); 3080 3081 NOT_PRODUCT(print_lir(1, "Before Register Allocation")); 3082 3083 compute_local_live_sets(); 3084 compute_global_live_sets(); 3085 CHECK_BAILOUT(); 3086 3087 build_intervals(); 3088 CHECK_BAILOUT(); 3089 sort_intervals_before_allocation(); 3090 3091 NOT_PRODUCT(print_intervals("Before Register Allocation")); 3092 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); 3093 3094 allocate_registers(); 3095 CHECK_BAILOUT(); 3096 3097 resolve_data_flow(); 3098 if (compilation()->has_exception_handlers()) { 3099 resolve_exception_handlers(); 3100 } 3101 // fill in number of spill slots into frame_map 3102 propagate_spill_slots(); 3103 CHECK_BAILOUT(); 3104 3105 NOT_PRODUCT(print_intervals("After Register Allocation")); 3106 NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); 3107 3108 sort_intervals_after_allocation(); 3109 3110 DEBUG_ONLY(verify()); 3111 3112 eliminate_spill_moves(); 3113 assign_reg_num(); 3114 CHECK_BAILOUT(); 3115 3116 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); 3117 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); 3118 3119 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); 3120 3121 if (use_fpu_stack_allocation()) { 3122 allocate_fpu_stack(); // Only has effect on Intel 3123 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); 3124 } 3125 } 3126 3127 { TIME_LINEAR_SCAN(timer_optimize_lir); 3128 3129 EdgeMoveOptimizer::optimize(ir()->code()); 3130 ControlFlowOptimizer::optimize(ir()->code()); 3131 // check that cfg is still correct after optimizations 3132 ir()->verify(); 3133 } 3134 3135 NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); 3136 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); 3137 NOT_PRODUCT(_total_timer.end_method(this)); 3138 } 3139 3140 3141 // ********** Printing functions 3142 3143 #ifndef PRODUCT 3144 3145 void LinearScan::print_timers(double total) { 3146 _total_timer.print(total); 3147 } 3148 3149 void LinearScan::print_statistics() { 3150 _stat_before_alloc.print("before allocation"); 3151 _stat_after_asign.print("after assignment of register"); 3152 _stat_final.print("after optimization"); 3153 } 3154 3155 void LinearScan::print_bitmap(BitMap& b) { 3156 for (unsigned int i = 0; i < b.size(); i++) { 3157 if (b.at(i)) tty->print("%d ", i); 3158 } 3159 tty->cr(); 3160 } 3161 3162 void LinearScan::print_intervals(const char* label) { 3163 if (TraceLinearScanLevel >= 1) { 3164 int i; 3165 tty->cr(); 3166 tty->print_cr("%s", label); 3167 3168 for (i = 0; i < interval_count(); i++) { 3169 Interval* interval = interval_at(i); 3170 if (interval != NULL) { 3171 interval->print(); 3172 } 3173 } 3174 3175 tty->cr(); 3176 tty->print_cr("--- Basic Blocks ---"); 3177 for (i = 0; i < block_count(); i++) { 3178 BlockBegin* block = block_at(i); 3179 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); 3180 } 3181 tty->cr(); 3182 tty->cr(); 3183 } 3184 3185 if (PrintCFGToFile) { 3186 CFGPrinter::print_intervals(&_intervals, label); 3187 } 3188 } 3189 3190 void LinearScan::print_lir(int level, const char* label, bool hir_valid) { 3191 if (TraceLinearScanLevel >= level) { 3192 tty->cr(); 3193 tty->print_cr("%s", label); 3194 print_LIR(ir()->linear_scan_order()); 3195 tty->cr(); 3196 } 3197 3198 if (level == 1 && PrintCFGToFile) { 3199 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); 3200 } 3201 } 3202 3203 #endif //PRODUCT 3204 3205 3206 // ********** verification functions for allocation 3207 // (check that all intervals have a correct register and that no registers are overwritten) 3208 #ifdef ASSERT 3209 3210 void LinearScan::verify() { 3211 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); 3212 verify_intervals(); 3213 3214 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); 3215 verify_no_oops_in_fixed_intervals(); 3216 3217 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); 3218 verify_constants(); 3219 3220 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); 3221 verify_registers(); 3222 3223 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); 3224 } 3225 3226 void LinearScan::verify_intervals() { 3227 int len = interval_count(); 3228 bool has_error = false; 3229 3230 for (int i = 0; i < len; i++) { 3231 Interval* i1 = interval_at(i); 3232 if (i1 == NULL) continue; 3233 3234 i1->check_split_children(); 3235 3236 if (i1->reg_num() != i) { 3237 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); 3238 has_error = true; 3239 } 3240 3241 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { 3242 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); 3243 has_error = true; 3244 } 3245 3246 if (i1->assigned_reg() == any_reg) { 3247 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); 3248 has_error = true; 3249 } 3250 3251 if (i1->assigned_reg() == i1->assigned_regHi()) { 3252 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); 3253 has_error = true; 3254 } 3255 3256 if (!is_processed_reg_num(i1->assigned_reg())) { 3257 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); 3258 has_error = true; 3259 } 3260 3261 // special intervals that are created in MoveResolver 3262 // -> ignore them because the range information has no meaning there 3263 if (i1->from() == 1 && i1->to() == 2) continue; 3264 3265 if (i1->first() == Range::end()) { 3266 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); 3267 has_error = true; 3268 } 3269 3270 for (Range* r = i1->first(); r != Range::end(); r = r->next()) { 3271 if (r->from() >= r->to()) { 3272 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); 3273 has_error = true; 3274 } 3275 } 3276 3277 for (int j = i + 1; j < len; j++) { 3278 Interval* i2 = interval_at(j); 3279 if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue; 3280 3281 int r1 = i1->assigned_reg(); 3282 int r1Hi = i1->assigned_regHi(); 3283 int r2 = i2->assigned_reg(); 3284 int r2Hi = i2->assigned_regHi(); 3285 if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) { 3286 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); 3287 i1->print(); tty->cr(); 3288 i2->print(); tty->cr(); 3289 has_error = true; 3290 } 3291 } 3292 } 3293 3294 assert(has_error == false, "register allocation invalid"); 3295 } 3296 3297 3298 void LinearScan::verify_no_oops_in_fixed_intervals() { 3299 Interval* fixed_intervals; 3300 Interval* other_intervals; 3301 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); 3302 3303 // to ensure a walking until the last instruction id, add a dummy interval 3304 // with a high operation id 3305 other_intervals = new Interval(any_reg); 3306 other_intervals->add_range(max_jint - 2, max_jint - 1); 3307 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); 3308 3309 LIR_OpVisitState visitor; 3310 for (int i = 0; i < block_count(); i++) { 3311 BlockBegin* block = block_at(i); 3312 3313 LIR_OpList* instructions = block->lir()->instructions_list(); 3314 3315 for (int j = 0; j < instructions->length(); j++) { 3316 LIR_Op* op = instructions->at(j); 3317 int op_id = op->id(); 3318 3319 visitor.visit(op); 3320 3321 if (visitor.info_count() > 0) { 3322 iw->walk_before(op->id()); 3323 bool check_live = true; 3324 if (op->code() == lir_move) { 3325 LIR_Op1* move = (LIR_Op1*)op; 3326 check_live = (move->patch_code() == lir_patch_none); 3327 } 3328 LIR_OpBranch* branch = op->as_OpBranch(); 3329 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { 3330 // Don't bother checking the stub in this case since the 3331 // exception stub will never return to normal control flow. 3332 check_live = false; 3333 } 3334 3335 // Make sure none of the fixed registers is live across an 3336 // oopmap since we can't handle that correctly. 3337 if (check_live) { 3338 for (Interval* interval = iw->active_first(fixedKind); 3339 interval != Interval::end(); 3340 interval = interval->next()) { 3341 if (interval->current_to() > op->id() + 1) { 3342 // This interval is live out of this op so make sure 3343 // that this interval represents some value that's 3344 // referenced by this op either as an input or output. 3345 bool ok = false; 3346 for_each_visitor_mode(mode) { 3347 int n = visitor.opr_count(mode); 3348 for (int k = 0; k < n; k++) { 3349 LIR_Opr opr = visitor.opr_at(mode, k); 3350 if (opr->is_fixed_cpu()) { 3351 if (interval_at(reg_num(opr)) == interval) { 3352 ok = true; 3353 break; 3354 } 3355 int hi = reg_numHi(opr); 3356 if (hi != -1 && interval_at(hi) == interval) { 3357 ok = true; 3358 break; 3359 } 3360 } 3361 } 3362 } 3363 assert(ok, "fixed intervals should never be live across an oopmap point"); 3364 } 3365 } 3366 } 3367 } 3368 3369 // oop-maps at calls do not contain registers, so check is not needed 3370 if (!visitor.has_call()) { 3371 3372 for_each_visitor_mode(mode) { 3373 int n = visitor.opr_count(mode); 3374 for (int k = 0; k < n; k++) { 3375 LIR_Opr opr = visitor.opr_at(mode, k); 3376 3377 if (opr->is_fixed_cpu() && opr->is_oop()) { 3378 // operand is a non-virtual cpu register and contains an oop 3379 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); 3380 3381 Interval* interval = interval_at(reg_num(opr)); 3382 assert(interval != NULL, "no interval"); 3383 3384 if (mode == LIR_OpVisitState::inputMode) { 3385 if (interval->to() >= op_id + 1) { 3386 assert(interval->to() < op_id + 2 || 3387 interval->has_hole_between(op_id, op_id + 2), 3388 "oop input operand live after instruction"); 3389 } 3390 } else if (mode == LIR_OpVisitState::outputMode) { 3391 if (interval->from() <= op_id - 1) { 3392 assert(interval->has_hole_between(op_id - 1, op_id), 3393 "oop input operand live after instruction"); 3394 } 3395 } 3396 } 3397 } 3398 } 3399 } 3400 } 3401 } 3402 } 3403 3404 3405 void LinearScan::verify_constants() { 3406 int num_regs = num_virtual_regs(); 3407 int size = live_set_size(); 3408 int num_blocks = block_count(); 3409 3410 for (int i = 0; i < num_blocks; i++) { 3411 BlockBegin* block = block_at(i); 3412 ResourceBitMap live_at_edge = block->live_in(); 3413 3414 // visit all registers where the live_at_edge bit is set 3415 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 3416 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); 3417 3418 Value value = gen()->instruction_for_vreg(r); 3419 3420 assert(value != NULL, "all intervals live across block boundaries must have Value"); 3421 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); 3422 assert(value->operand()->vreg_number() == r, "register number must match"); 3423 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); 3424 } 3425 } 3426 } 3427 3428 3429 class RegisterVerifier: public StackObj { 3430 private: 3431 LinearScan* _allocator; 3432 BlockList _work_list; // all blocks that must be processed 3433 IntervalsList _saved_states; // saved information of previous check 3434 3435 // simplified access to methods of LinearScan 3436 Compilation* compilation() const { return _allocator->compilation(); } 3437 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } 3438 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } 3439 3440 // currently, only registers are processed 3441 int state_size() { return LinearScan::nof_regs; } 3442 3443 // accessors 3444 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } 3445 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } 3446 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } 3447 3448 // helper functions 3449 IntervalList* copy(IntervalList* input_state); 3450 void state_put(IntervalList* input_state, int reg, Interval* interval); 3451 bool check_state(IntervalList* input_state, int reg, Interval* interval); 3452 3453 void process_block(BlockBegin* block); 3454 void process_xhandler(XHandler* xhandler, IntervalList* input_state); 3455 void process_successor(BlockBegin* block, IntervalList* input_state); 3456 void process_operations(LIR_List* ops, IntervalList* input_state); 3457 3458 public: 3459 RegisterVerifier(LinearScan* allocator) 3460 : _allocator(allocator) 3461 , _work_list(16) 3462 , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL) 3463 { } 3464 3465 void verify(BlockBegin* start); 3466 }; 3467 3468 3469 // entry function from LinearScan that starts the verification 3470 void LinearScan::verify_registers() { 3471 RegisterVerifier verifier(this); 3472 verifier.verify(block_at(0)); 3473 } 3474 3475 3476 void RegisterVerifier::verify(BlockBegin* start) { 3477 // setup input registers (method arguments) for first block 3478 int input_state_len = state_size(); 3479 IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL); 3480 CallingConvention* args = compilation()->frame_map()->incoming_arguments(); 3481 for (int n = 0; n < args->length(); n++) { 3482 LIR_Opr opr = args->at(n); 3483 if (opr->is_register()) { 3484 Interval* interval = interval_at(reg_num(opr)); 3485 3486 if (interval->assigned_reg() < state_size()) { 3487 input_state->at_put(interval->assigned_reg(), interval); 3488 } 3489 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { 3490 input_state->at_put(interval->assigned_regHi(), interval); 3491 } 3492 } 3493 } 3494 3495 set_state_for_block(start, input_state); 3496 add_to_work_list(start); 3497 3498 // main loop for verification 3499 do { 3500 BlockBegin* block = _work_list.at(0); 3501 _work_list.remove_at(0); 3502 3503 process_block(block); 3504 } while (!_work_list.is_empty()); 3505 } 3506 3507 void RegisterVerifier::process_block(BlockBegin* block) { 3508 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); 3509 3510 // must copy state because it is modified 3511 IntervalList* input_state = copy(state_for_block(block)); 3512 3513 if (TraceLinearScanLevel >= 4) { 3514 tty->print_cr("Input-State of intervals:"); 3515 tty->print(" "); 3516 for (int i = 0; i < state_size(); i++) { 3517 if (input_state->at(i) != NULL) { 3518 tty->print(" %4d", input_state->at(i)->reg_num()); 3519 } else { 3520 tty->print(" __"); 3521 } 3522 } 3523 tty->cr(); 3524 tty->cr(); 3525 } 3526 3527 // process all operations of the block 3528 process_operations(block->lir(), input_state); 3529 3530 // iterate all successors 3531 for (int i = 0; i < block->number_of_sux(); i++) { 3532 process_successor(block->sux_at(i), input_state); 3533 } 3534 } 3535 3536 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) { 3537 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); 3538 3539 // must copy state because it is modified 3540 input_state = copy(input_state); 3541 3542 if (xhandler->entry_code() != NULL) { 3543 process_operations(xhandler->entry_code(), input_state); 3544 } 3545 process_successor(xhandler->entry_block(), input_state); 3546 } 3547 3548 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) { 3549 IntervalList* saved_state = state_for_block(block); 3550 3551 if (saved_state != NULL) { 3552 // this block was already processed before. 3553 // check if new input_state is consistent with saved_state 3554 3555 bool saved_state_correct = true; 3556 for (int i = 0; i < state_size(); i++) { 3557 if (input_state->at(i) != saved_state->at(i)) { 3558 // current input_state and previous saved_state assume a different 3559 // interval in this register -> assume that this register is invalid 3560 if (saved_state->at(i) != NULL) { 3561 // invalidate old calculation only if it assumed that 3562 // register was valid. when the register was already invalid, 3563 // then the old calculation was correct. 3564 saved_state_correct = false; 3565 saved_state->at_put(i, NULL); 3566 3567 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); 3568 } 3569 } 3570 } 3571 3572 if (saved_state_correct) { 3573 // already processed block with correct input_state 3574 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); 3575 } else { 3576 // must re-visit this block 3577 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); 3578 add_to_work_list(block); 3579 } 3580 3581 } else { 3582 // block was not processed before, so set initial input_state 3583 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); 3584 3585 set_state_for_block(block, copy(input_state)); 3586 add_to_work_list(block); 3587 } 3588 } 3589 3590 3591 IntervalList* RegisterVerifier::copy(IntervalList* input_state) { 3592 IntervalList* copy_state = new IntervalList(input_state->length()); 3593 copy_state->appendAll(input_state); 3594 return copy_state; 3595 } 3596 3597 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) { 3598 if (reg != LinearScan::any_reg && reg < state_size()) { 3599 if (interval != NULL) { 3600 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); 3601 } else if (input_state->at(reg) != NULL) { 3602 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); 3603 } 3604 3605 input_state->at_put(reg, interval); 3606 } 3607 } 3608 3609 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) { 3610 if (reg != LinearScan::any_reg && reg < state_size()) { 3611 if (input_state->at(reg) != interval) { 3612 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); 3613 return true; 3614 } 3615 } 3616 return false; 3617 } 3618 3619 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) { 3620 // visit all instructions of the block 3621 LIR_OpVisitState visitor; 3622 bool has_error = false; 3623 3624 for (int i = 0; i < ops->length(); i++) { 3625 LIR_Op* op = ops->at(i); 3626 visitor.visit(op); 3627 3628 TRACE_LINEAR_SCAN(4, op->print_on(tty)); 3629 3630 // check if input operands are correct 3631 int j; 3632 int n = visitor.opr_count(LIR_OpVisitState::inputMode); 3633 for (j = 0; j < n; j++) { 3634 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); 3635 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3636 Interval* interval = interval_at(reg_num(opr)); 3637 if (op->id() != -1) { 3638 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); 3639 } 3640 3641 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); 3642 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); 3643 3644 // When an operand is marked with is_last_use, then the fpu stack allocator 3645 // removes the register from the fpu stack -> the register contains no value 3646 if (opr->is_last_use()) { 3647 state_put(input_state, interval->assigned_reg(), NULL); 3648 state_put(input_state, interval->assigned_regHi(), NULL); 3649 } 3650 } 3651 } 3652 3653 // invalidate all caller save registers at calls 3654 if (visitor.has_call()) { 3655 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) { 3656 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); 3657 } 3658 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { 3659 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); 3660 } 3661 3662 #ifdef X86 3663 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms(); 3664 for (j = 0; j < num_caller_save_xmm_regs; j++) { 3665 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); 3666 } 3667 #endif 3668 } 3669 3670 // process xhandler before output and temp operands 3671 XHandlers* xhandlers = visitor.all_xhandler(); 3672 n = xhandlers->length(); 3673 for (int k = 0; k < n; k++) { 3674 process_xhandler(xhandlers->handler_at(k), input_state); 3675 } 3676 3677 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) 3678 n = visitor.opr_count(LIR_OpVisitState::tempMode); 3679 for (j = 0; j < n; j++) { 3680 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); 3681 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3682 Interval* interval = interval_at(reg_num(opr)); 3683 if (op->id() != -1) { 3684 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); 3685 } 3686 3687 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3688 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3689 } 3690 } 3691 3692 // set output operands 3693 n = visitor.opr_count(LIR_OpVisitState::outputMode); 3694 for (j = 0; j < n; j++) { 3695 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); 3696 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3697 Interval* interval = interval_at(reg_num(opr)); 3698 if (op->id() != -1) { 3699 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); 3700 } 3701 3702 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3703 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3704 } 3705 } 3706 } 3707 assert(has_error == false, "Error in register allocation"); 3708 } 3709 3710 #endif // ASSERT 3711 3712 3713 3714 // **** Implementation of MoveResolver ****************************** 3715 3716 MoveResolver::MoveResolver(LinearScan* allocator) : 3717 _allocator(allocator), 3718 _multiple_reads_allowed(false), 3719 _mapping_from(8), 3720 _mapping_from_opr(8), 3721 _mapping_to(8), 3722 _insert_list(NULL), 3723 _insert_idx(-1), 3724 _insertion_buffer() 3725 { 3726 for (int i = 0; i < LinearScan::nof_regs; i++) { 3727 _register_blocked[i] = 0; 3728 } 3729 DEBUG_ONLY(check_empty()); 3730 } 3731 3732 3733 #ifdef ASSERT 3734 3735 void MoveResolver::check_empty() { 3736 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); 3737 for (int i = 0; i < LinearScan::nof_regs; i++) { 3738 assert(register_blocked(i) == 0, "register map must be empty before and after processing"); 3739 } 3740 assert(_multiple_reads_allowed == false, "must have default value"); 3741 } 3742 3743 void MoveResolver::verify_before_resolve() { 3744 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); 3745 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); 3746 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); 3747 3748 int i, j; 3749 if (!_multiple_reads_allowed) { 3750 for (i = 0; i < _mapping_from.length(); i++) { 3751 for (j = i + 1; j < _mapping_from.length(); j++) { 3752 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); 3753 } 3754 } 3755 } 3756 3757 for (i = 0; i < _mapping_to.length(); i++) { 3758 for (j = i + 1; j < _mapping_to.length(); j++) { 3759 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); 3760 } 3761 } 3762 3763 3764 ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); 3765 if (!_multiple_reads_allowed) { 3766 for (i = 0; i < _mapping_from.length(); i++) { 3767 Interval* it = _mapping_from.at(i); 3768 if (it != NULL) { 3769 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); 3770 used_regs.set_bit(it->assigned_reg()); 3771 3772 if (it->assigned_regHi() != LinearScan::any_reg) { 3773 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); 3774 used_regs.set_bit(it->assigned_regHi()); 3775 } 3776 } 3777 } 3778 } 3779 3780 used_regs.clear(); 3781 for (i = 0; i < _mapping_to.length(); i++) { 3782 Interval* it = _mapping_to.at(i); 3783 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); 3784 used_regs.set_bit(it->assigned_reg()); 3785 3786 if (it->assigned_regHi() != LinearScan::any_reg) { 3787 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); 3788 used_regs.set_bit(it->assigned_regHi()); 3789 } 3790 } 3791 3792 used_regs.clear(); 3793 for (i = 0; i < _mapping_from.length(); i++) { 3794 Interval* it = _mapping_from.at(i); 3795 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { 3796 used_regs.set_bit(it->assigned_reg()); 3797 } 3798 } 3799 for (i = 0; i < _mapping_to.length(); i++) { 3800 Interval* it = _mapping_to.at(i); 3801 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); 3802 } 3803 } 3804 3805 #endif // ASSERT 3806 3807 3808 // mark assigned_reg and assigned_regHi of the interval as blocked 3809 void MoveResolver::block_registers(Interval* it) { 3810 int reg = it->assigned_reg(); 3811 if (reg < LinearScan::nof_regs) { 3812 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3813 set_register_blocked(reg, 1); 3814 } 3815 reg = it->assigned_regHi(); 3816 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3817 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3818 set_register_blocked(reg, 1); 3819 } 3820 } 3821 3822 // mark assigned_reg and assigned_regHi of the interval as unblocked 3823 void MoveResolver::unblock_registers(Interval* it) { 3824 int reg = it->assigned_reg(); 3825 if (reg < LinearScan::nof_regs) { 3826 assert(register_blocked(reg) > 0, "register already marked as unused"); 3827 set_register_blocked(reg, -1); 3828 } 3829 reg = it->assigned_regHi(); 3830 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3831 assert(register_blocked(reg) > 0, "register already marked as unused"); 3832 set_register_blocked(reg, -1); 3833 } 3834 } 3835 3836 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) 3837 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { 3838 int from_reg = -1; 3839 int from_regHi = -1; 3840 if (from != NULL) { 3841 from_reg = from->assigned_reg(); 3842 from_regHi = from->assigned_regHi(); 3843 } 3844 3845 int reg = to->assigned_reg(); 3846 if (reg < LinearScan::nof_regs) { 3847 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3848 return false; 3849 } 3850 } 3851 reg = to->assigned_regHi(); 3852 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3853 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3854 return false; 3855 } 3856 } 3857 3858 return true; 3859 } 3860 3861 3862 void MoveResolver::create_insertion_buffer(LIR_List* list) { 3863 assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); 3864 _insertion_buffer.init(list); 3865 } 3866 3867 void MoveResolver::append_insertion_buffer() { 3868 if (_insertion_buffer.initialized()) { 3869 _insertion_buffer.lir_list()->append(&_insertion_buffer); 3870 } 3871 assert(!_insertion_buffer.initialized(), "must be uninitialized now"); 3872 3873 _insert_list = NULL; 3874 _insert_idx = -1; 3875 } 3876 3877 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { 3878 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); 3879 assert(from_interval->type() == to_interval->type(), "move between different types"); 3880 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3881 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3882 3883 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); 3884 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3885 3886 if (!_multiple_reads_allowed) { 3887 // the last_use flag is an optimization for FPU stack allocation. When the same 3888 // input interval is used in more than one move, then it is too difficult to determine 3889 // if this move is really the last use. 3890 from_opr = from_opr->make_last_use(); 3891 } 3892 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3893 3894 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3895 } 3896 3897 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { 3898 assert(from_opr->type() == to_interval->type(), "move between different types"); 3899 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3900 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3901 3902 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3903 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3904 3905 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3906 } 3907 3908 3909 void MoveResolver::resolve_mappings() { 3910 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); 3911 DEBUG_ONLY(verify_before_resolve()); 3912 3913 // Block all registers that are used as input operands of a move. 3914 // When a register is blocked, no move to this register is emitted. 3915 // This is necessary for detecting cycles in moves. 3916 int i; 3917 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3918 Interval* from_interval = _mapping_from.at(i); 3919 if (from_interval != NULL) { 3920 block_registers(from_interval); 3921 } 3922 } 3923 3924 int spill_candidate = -1; 3925 while (_mapping_from.length() > 0) { 3926 bool processed_interval = false; 3927 3928 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3929 Interval* from_interval = _mapping_from.at(i); 3930 Interval* to_interval = _mapping_to.at(i); 3931 3932 if (save_to_process_move(from_interval, to_interval)) { 3933 // this inverval can be processed because target is free 3934 if (from_interval != NULL) { 3935 insert_move(from_interval, to_interval); 3936 unblock_registers(from_interval); 3937 } else { 3938 insert_move(_mapping_from_opr.at(i), to_interval); 3939 } 3940 _mapping_from.remove_at(i); 3941 _mapping_from_opr.remove_at(i); 3942 _mapping_to.remove_at(i); 3943 3944 processed_interval = true; 3945 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { 3946 // this interval cannot be processed now because target is not free 3947 // it starts in a register, so it is a possible candidate for spilling 3948 spill_candidate = i; 3949 } 3950 } 3951 3952 if (!processed_interval) { 3953 // no move could be processed because there is a cycle in the move list 3954 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory 3955 assert(spill_candidate != -1, "no interval in register for spilling found"); 3956 3957 // create a new spill interval and assign a stack slot to it 3958 Interval* from_interval = _mapping_from.at(spill_candidate); 3959 Interval* spill_interval = new Interval(-1); 3960 spill_interval->set_type(from_interval->type()); 3961 3962 // add a dummy range because real position is difficult to calculate 3963 // Note: this range is a special case when the integrity of the allocation is checked 3964 spill_interval->add_range(1, 2); 3965 3966 // do not allocate a new spill slot for temporary interval, but 3967 // use spill slot assigned to from_interval. Otherwise moves from 3968 // one stack slot to another can happen (not allowed by LIR_Assembler 3969 int spill_slot = from_interval->canonical_spill_slot(); 3970 if (spill_slot < 0) { 3971 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); 3972 from_interval->set_canonical_spill_slot(spill_slot); 3973 } 3974 spill_interval->assign_reg(spill_slot); 3975 allocator()->append_interval(spill_interval); 3976 3977 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); 3978 3979 // insert a move from register to stack and update the mapping 3980 insert_move(from_interval, spill_interval); 3981 _mapping_from.at_put(spill_candidate, spill_interval); 3982 unblock_registers(from_interval); 3983 } 3984 } 3985 3986 // reset to default value 3987 _multiple_reads_allowed = false; 3988 3989 // check that all intervals have been processed 3990 DEBUG_ONLY(check_empty()); 3991 } 3992 3993 3994 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { 3995 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 3996 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); 3997 3998 create_insertion_buffer(insert_list); 3999 _insert_list = insert_list; 4000 _insert_idx = insert_idx; 4001 } 4002 4003 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { 4004 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 4005 4006 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { 4007 // insert position changed -> resolve current mappings 4008 resolve_mappings(); 4009 } 4010 4011 if (insert_list != _insert_list) { 4012 // block changed -> append insertion_buffer because it is 4013 // bound to a specific block and create a new insertion_buffer 4014 append_insertion_buffer(); 4015 create_insertion_buffer(insert_list); 4016 } 4017 4018 _insert_list = insert_list; 4019 _insert_idx = insert_idx; 4020 } 4021 4022 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { 4023 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 4024 4025 _mapping_from.append(from_interval); 4026 _mapping_from_opr.append(LIR_OprFact::illegalOpr); 4027 _mapping_to.append(to_interval); 4028 } 4029 4030 4031 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { 4032 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 4033 assert(from_opr->is_constant(), "only for constants"); 4034 4035 _mapping_from.append(NULL); 4036 _mapping_from_opr.append(from_opr); 4037 _mapping_to.append(to_interval); 4038 } 4039 4040 void MoveResolver::resolve_and_append_moves() { 4041 if (has_mappings()) { 4042 resolve_mappings(); 4043 } 4044 append_insertion_buffer(); 4045 } 4046 4047 4048 4049 // **** Implementation of Range ************************************* 4050 4051 Range::Range(int from, int to, Range* next) : 4052 _from(from), 4053 _to(to), 4054 _next(next) 4055 { 4056 } 4057 4058 // initialize sentinel 4059 Range* Range::_end = NULL; 4060 void Range::initialize(Arena* arena) { 4061 _end = new (arena) Range(max_jint, max_jint, NULL); 4062 } 4063 4064 int Range::intersects_at(Range* r2) const { 4065 const Range* r1 = this; 4066 4067 assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); 4068 assert(r1 != _end && r2 != _end, "empty ranges not allowed"); 4069 4070 do { 4071 if (r1->from() < r2->from()) { 4072 if (r1->to() <= r2->from()) { 4073 r1 = r1->next(); if (r1 == _end) return -1; 4074 } else { 4075 return r2->from(); 4076 } 4077 } else if (r2->from() < r1->from()) { 4078 if (r2->to() <= r1->from()) { 4079 r2 = r2->next(); if (r2 == _end) return -1; 4080 } else { 4081 return r1->from(); 4082 } 4083 } else { // r1->from() == r2->from() 4084 if (r1->from() == r1->to()) { 4085 r1 = r1->next(); if (r1 == _end) return -1; 4086 } else if (r2->from() == r2->to()) { 4087 r2 = r2->next(); if (r2 == _end) return -1; 4088 } else { 4089 return r1->from(); 4090 } 4091 } 4092 } while (true); 4093 } 4094 4095 #ifndef PRODUCT 4096 void Range::print(outputStream* out) const { 4097 out->print("[%d, %d[ ", _from, _to); 4098 } 4099 #endif 4100 4101 4102 4103 // **** Implementation of Interval ********************************** 4104 4105 // initialize sentinel 4106 Interval* Interval::_end = NULL; 4107 void Interval::initialize(Arena* arena) { 4108 Range::initialize(arena); 4109 _end = new (arena) Interval(-1); 4110 } 4111 4112 Interval::Interval(int reg_num) : 4113 _reg_num(reg_num), 4114 _type(T_ILLEGAL), 4115 _first(Range::end()), 4116 _use_pos_and_kinds(12), 4117 _current(Range::end()), 4118 _next(_end), 4119 _state(invalidState), 4120 _assigned_reg(LinearScan::any_reg), 4121 _assigned_regHi(LinearScan::any_reg), 4122 _cached_to(-1), 4123 _cached_opr(LIR_OprFact::illegalOpr), 4124 _cached_vm_reg(VMRegImpl::Bad()), 4125 _split_children(0), 4126 _canonical_spill_slot(-1), 4127 _insert_move_when_activated(false), 4128 _register_hint(NULL), 4129 _spill_state(noDefinitionFound), 4130 _spill_definition_pos(-1) 4131 { 4132 _split_parent = this; 4133 _current_split_child = this; 4134 } 4135 4136 int Interval::calc_to() { 4137 assert(_first != Range::end(), "interval has no range"); 4138 4139 Range* r = _first; 4140 while (r->next() != Range::end()) { 4141 r = r->next(); 4142 } 4143 return r->to(); 4144 } 4145 4146 4147 #ifdef ASSERT 4148 // consistency check of split-children 4149 void Interval::check_split_children() { 4150 if (_split_children.length() > 0) { 4151 assert(is_split_parent(), "only split parents can have children"); 4152 4153 for (int i = 0; i < _split_children.length(); i++) { 4154 Interval* i1 = _split_children.at(i); 4155 4156 assert(i1->split_parent() == this, "not a split child of this interval"); 4157 assert(i1->type() == type(), "must be equal for all split children"); 4158 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); 4159 4160 for (int j = i + 1; j < _split_children.length(); j++) { 4161 Interval* i2 = _split_children.at(j); 4162 4163 assert(i1->reg_num() != i2->reg_num(), "same register number"); 4164 4165 if (i1->from() < i2->from()) { 4166 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); 4167 } else { 4168 assert(i2->from() < i1->from(), "intervals start at same op_id"); 4169 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); 4170 } 4171 } 4172 } 4173 } 4174 } 4175 #endif // ASSERT 4176 4177 Interval* Interval::register_hint(bool search_split_child) const { 4178 if (!search_split_child) { 4179 return _register_hint; 4180 } 4181 4182 if (_register_hint != NULL) { 4183 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); 4184 4185 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { 4186 return _register_hint; 4187 4188 } else if (_register_hint->_split_children.length() > 0) { 4189 // search the first split child that has a register assigned 4190 int len = _register_hint->_split_children.length(); 4191 for (int i = 0; i < len; i++) { 4192 Interval* cur = _register_hint->_split_children.at(i); 4193 4194 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { 4195 return cur; 4196 } 4197 } 4198 } 4199 } 4200 4201 // no hint interval found that has a register assigned 4202 return NULL; 4203 } 4204 4205 4206 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { 4207 assert(is_split_parent(), "can only be called for split parents"); 4208 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4209 4210 Interval* result; 4211 if (_split_children.length() == 0) { 4212 result = this; 4213 } else { 4214 result = NULL; 4215 int len = _split_children.length(); 4216 4217 // in outputMode, the end of the interval (op_id == cur->to()) is not valid 4218 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); 4219 4220 int i; 4221 for (i = 0; i < len; i++) { 4222 Interval* cur = _split_children.at(i); 4223 if (cur->from() <= op_id && op_id < cur->to() + to_offset) { 4224 if (i > 0) { 4225 // exchange current split child to start of list (faster access for next call) 4226 _split_children.at_put(i, _split_children.at(0)); 4227 _split_children.at_put(0, cur); 4228 } 4229 4230 // interval found 4231 result = cur; 4232 break; 4233 } 4234 } 4235 4236 #ifdef ASSERT 4237 for (i = 0; i < len; i++) { 4238 Interval* tmp = _split_children.at(i); 4239 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { 4240 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); 4241 result->print(); 4242 tmp->print(); 4243 assert(false, "two valid result intervals found"); 4244 } 4245 } 4246 #endif 4247 } 4248 4249 assert(result != NULL, "no matching interval found"); 4250 assert(result->covers(op_id, mode), "op_id not covered by interval"); 4251 4252 return result; 4253 } 4254 4255 4256 // returns the last split child that ends before the given op_id 4257 Interval* Interval::split_child_before_op_id(int op_id) { 4258 assert(op_id >= 0, "invalid op_id"); 4259 4260 Interval* parent = split_parent(); 4261 Interval* result = NULL; 4262 4263 int len = parent->_split_children.length(); 4264 assert(len > 0, "no split children available"); 4265 4266 for (int i = len - 1; i >= 0; i--) { 4267 Interval* cur = parent->_split_children.at(i); 4268 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { 4269 result = cur; 4270 } 4271 } 4272 4273 assert(result != NULL, "no split child found"); 4274 return result; 4275 } 4276 4277 4278 // checks if op_id is covered by any split child 4279 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { 4280 assert(is_split_parent(), "can only be called for split parents"); 4281 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4282 4283 if (_split_children.length() == 0) { 4284 // simple case if interval was not split 4285 return covers(op_id, mode); 4286 4287 } else { 4288 // extended case: check all split children 4289 int len = _split_children.length(); 4290 for (int i = 0; i < len; i++) { 4291 Interval* cur = _split_children.at(i); 4292 if (cur->covers(op_id, mode)) { 4293 return true; 4294 } 4295 } 4296 return false; 4297 } 4298 } 4299 4300 4301 // Note: use positions are sorted descending -> first use has highest index 4302 int Interval::first_usage(IntervalUseKind min_use_kind) const { 4303 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4304 4305 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4306 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4307 return _use_pos_and_kinds.at(i); 4308 } 4309 } 4310 return max_jint; 4311 } 4312 4313 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { 4314 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4315 4316 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4317 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4318 return _use_pos_and_kinds.at(i); 4319 } 4320 } 4321 return max_jint; 4322 } 4323 4324 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { 4325 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4326 4327 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4328 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { 4329 return _use_pos_and_kinds.at(i); 4330 } 4331 } 4332 return max_jint; 4333 } 4334 4335 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { 4336 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4337 4338 int prev = 0; 4339 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4340 if (_use_pos_and_kinds.at(i) > from) { 4341 return prev; 4342 } 4343 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4344 prev = _use_pos_and_kinds.at(i); 4345 } 4346 } 4347 return prev; 4348 } 4349 4350 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { 4351 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); 4352 4353 // do not add use positions for precolored intervals because 4354 // they are never used 4355 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { 4356 #ifdef ASSERT 4357 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4358 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4359 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); 4360 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4361 if (i > 0) { 4362 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); 4363 } 4364 } 4365 #endif 4366 4367 // Note: add_use is called in descending order, so list gets sorted 4368 // automatically by just appending new use positions 4369 int len = _use_pos_and_kinds.length(); 4370 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { 4371 _use_pos_and_kinds.append(pos); 4372 _use_pos_and_kinds.append(use_kind); 4373 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { 4374 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); 4375 _use_pos_and_kinds.at_put(len - 1, use_kind); 4376 } 4377 } 4378 } 4379 4380 void Interval::add_range(int from, int to) { 4381 assert(from < to, "invalid range"); 4382 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); 4383 assert(from <= first()->to(), "not inserting at begin of interval"); 4384 4385 if (first()->from() <= to) { 4386 // join intersecting ranges 4387 first()->set_from(MIN2(from, first()->from())); 4388 first()->set_to (MAX2(to, first()->to())); 4389 } else { 4390 // insert new range 4391 _first = new Range(from, to, first()); 4392 } 4393 } 4394 4395 Interval* Interval::new_split_child() { 4396 // allocate new interval 4397 Interval* result = new Interval(-1); 4398 result->set_type(type()); 4399 4400 Interval* parent = split_parent(); 4401 result->_split_parent = parent; 4402 result->set_register_hint(parent); 4403 4404 // insert new interval in children-list of parent 4405 if (parent->_split_children.length() == 0) { 4406 assert(is_split_parent(), "list must be initialized at first split"); 4407 4408 parent->_split_children = IntervalList(4); 4409 parent->_split_children.append(this); 4410 } 4411 parent->_split_children.append(result); 4412 4413 return result; 4414 } 4415 4416 // split this interval at the specified position and return 4417 // the remainder as a new interval. 4418 // 4419 // when an interval is split, a bi-directional link is established between the original interval 4420 // (the split parent) and the intervals that are split off this interval (the split children) 4421 // When a split child is split again, the new created interval is also a direct child 4422 // of the original parent (there is no tree of split children stored, but a flat list) 4423 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) 4424 // 4425 // Note: The new interval has no valid reg_num 4426 Interval* Interval::split(int split_pos) { 4427 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4428 4429 // allocate new interval 4430 Interval* result = new_split_child(); 4431 4432 // split the ranges 4433 Range* prev = NULL; 4434 Range* cur = _first; 4435 while (cur != Range::end() && cur->to() <= split_pos) { 4436 prev = cur; 4437 cur = cur->next(); 4438 } 4439 assert(cur != Range::end(), "split interval after end of last range"); 4440 4441 if (cur->from() < split_pos) { 4442 result->_first = new Range(split_pos, cur->to(), cur->next()); 4443 cur->set_to(split_pos); 4444 cur->set_next(Range::end()); 4445 4446 } else { 4447 assert(prev != NULL, "split before start of first range"); 4448 result->_first = cur; 4449 prev->set_next(Range::end()); 4450 } 4451 result->_current = result->_first; 4452 _cached_to = -1; // clear cached value 4453 4454 // split list of use positions 4455 int total_len = _use_pos_and_kinds.length(); 4456 int start_idx = total_len - 2; 4457 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { 4458 start_idx -= 2; 4459 } 4460 4461 intStack new_use_pos_and_kinds(total_len - start_idx); 4462 int i; 4463 for (i = start_idx + 2; i < total_len; i++) { 4464 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); 4465 } 4466 4467 _use_pos_and_kinds.trunc_to(start_idx + 2); 4468 result->_use_pos_and_kinds = _use_pos_and_kinds; 4469 _use_pos_and_kinds = new_use_pos_and_kinds; 4470 4471 #ifdef ASSERT 4472 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4473 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4474 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); 4475 4476 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4477 assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); 4478 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4479 } 4480 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { 4481 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); 4482 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4483 } 4484 #endif 4485 4486 return result; 4487 } 4488 4489 // split this interval at the specified position and return 4490 // the head as a new interval (the original interval is the tail) 4491 // 4492 // Currently, only the first range can be split, and the new interval 4493 // must not have split positions 4494 Interval* Interval::split_from_start(int split_pos) { 4495 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4496 assert(split_pos > from() && split_pos < to(), "can only split inside interval"); 4497 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); 4498 assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); 4499 4500 // allocate new interval 4501 Interval* result = new_split_child(); 4502 4503 // the new created interval has only one range (checked by assertion above), 4504 // so the splitting of the ranges is very simple 4505 result->add_range(_first->from(), split_pos); 4506 4507 if (split_pos == _first->to()) { 4508 assert(_first->next() != Range::end(), "must not be at end"); 4509 _first = _first->next(); 4510 } else { 4511 _first->set_from(split_pos); 4512 } 4513 4514 return result; 4515 } 4516 4517 4518 // returns true if the op_id is inside the interval 4519 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { 4520 Range* cur = _first; 4521 4522 while (cur != Range::end() && cur->to() < op_id) { 4523 cur = cur->next(); 4524 } 4525 if (cur != Range::end()) { 4526 assert(cur->to() != cur->next()->from(), "ranges not separated"); 4527 4528 if (mode == LIR_OpVisitState::outputMode) { 4529 return cur->from() <= op_id && op_id < cur->to(); 4530 } else { 4531 return cur->from() <= op_id && op_id <= cur->to(); 4532 } 4533 } 4534 return false; 4535 } 4536 4537 // returns true if the interval has any hole between hole_from and hole_to 4538 // (even if the hole has only the length 1) 4539 bool Interval::has_hole_between(int hole_from, int hole_to) { 4540 assert(hole_from < hole_to, "check"); 4541 assert(from() <= hole_from && hole_to <= to(), "index out of interval"); 4542 4543 Range* cur = _first; 4544 while (cur != Range::end()) { 4545 assert(cur->to() < cur->next()->from(), "no space between ranges"); 4546 4547 // hole-range starts before this range -> hole 4548 if (hole_from < cur->from()) { 4549 return true; 4550 4551 // hole-range completely inside this range -> no hole 4552 } else if (hole_to <= cur->to()) { 4553 return false; 4554 4555 // overlapping of hole-range with this range -> hole 4556 } else if (hole_from <= cur->to()) { 4557 return true; 4558 } 4559 4560 cur = cur->next(); 4561 } 4562 4563 return false; 4564 } 4565 4566 4567 #ifndef PRODUCT 4568 void Interval::print(outputStream* out) const { 4569 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; 4570 const char* UseKind2Name[] = { "N", "L", "S", "M" }; 4571 4572 const char* type_name; 4573 LIR_Opr opr = LIR_OprFact::illegal(); 4574 if (reg_num() < LIR_OprDesc::vreg_base) { 4575 type_name = "fixed"; 4576 // need a temporary operand for fixed intervals because type() cannot be called 4577 #ifdef X86 4578 int last_xmm_reg = pd_last_xmm_reg; 4579 #ifdef _LP64 4580 if (UseAVX < 3) { 4581 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 4582 } 4583 #endif 4584 #endif 4585 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { 4586 opr = LIR_OprFact::single_cpu(assigned_reg()); 4587 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { 4588 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); 4589 #ifdef X86 4590 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) { 4591 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); 4592 #endif 4593 } else { 4594 ShouldNotReachHere(); 4595 } 4596 } else { 4597 type_name = type2name(type()); 4598 if (assigned_reg() != -1 && 4599 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) { 4600 opr = LinearScan::calc_operand_for_interval(this); 4601 } 4602 } 4603 4604 out->print("%d %s ", reg_num(), type_name); 4605 if (opr->is_valid()) { 4606 out->print("\""); 4607 opr->print(out); 4608 out->print("\" "); 4609 } 4610 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); 4611 4612 // print ranges 4613 Range* cur = _first; 4614 while (cur != Range::end()) { 4615 cur->print(out); 4616 cur = cur->next(); 4617 assert(cur != NULL, "range list not closed with range sentinel"); 4618 } 4619 4620 // print use positions 4621 int prev = 0; 4622 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4623 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4624 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4625 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); 4626 4627 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); 4628 prev = _use_pos_and_kinds.at(i); 4629 } 4630 4631 out->print(" \"%s\"", SpillState2Name[spill_state()]); 4632 out->cr(); 4633 } 4634 #endif 4635 4636 4637 4638 // **** Implementation of IntervalWalker **************************** 4639 4640 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4641 : _compilation(allocator->compilation()) 4642 , _allocator(allocator) 4643 { 4644 _unhandled_first[fixedKind] = unhandled_fixed_first; 4645 _unhandled_first[anyKind] = unhandled_any_first; 4646 _active_first[fixedKind] = Interval::end(); 4647 _inactive_first[fixedKind] = Interval::end(); 4648 _active_first[anyKind] = Interval::end(); 4649 _inactive_first[anyKind] = Interval::end(); 4650 _current_position = -1; 4651 _current = NULL; 4652 next_interval(); 4653 } 4654 4655 4656 // append interval at top of list 4657 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { 4658 interval->set_next(*list); *list = interval; 4659 } 4660 4661 4662 // append interval in order of current range from() 4663 void IntervalWalker::append_sorted(Interval** list, Interval* interval) { 4664 Interval* prev = NULL; 4665 Interval* cur = *list; 4666 while (cur->current_from() < interval->current_from()) { 4667 prev = cur; cur = cur->next(); 4668 } 4669 if (prev == NULL) { 4670 *list = interval; 4671 } else { 4672 prev->set_next(interval); 4673 } 4674 interval->set_next(cur); 4675 } 4676 4677 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { 4678 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); 4679 4680 Interval* prev = NULL; 4681 Interval* cur = *list; 4682 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { 4683 prev = cur; cur = cur->next(); 4684 } 4685 if (prev == NULL) { 4686 *list = interval; 4687 } else { 4688 prev->set_next(interval); 4689 } 4690 interval->set_next(cur); 4691 } 4692 4693 4694 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { 4695 while (*list != Interval::end() && *list != i) { 4696 list = (*list)->next_addr(); 4697 } 4698 if (*list != Interval::end()) { 4699 assert(*list == i, "check"); 4700 *list = (*list)->next(); 4701 return true; 4702 } else { 4703 return false; 4704 } 4705 } 4706 4707 void IntervalWalker::remove_from_list(Interval* i) { 4708 bool deleted; 4709 4710 if (i->state() == activeState) { 4711 deleted = remove_from_list(active_first_addr(anyKind), i); 4712 } else { 4713 assert(i->state() == inactiveState, "invalid state"); 4714 deleted = remove_from_list(inactive_first_addr(anyKind), i); 4715 } 4716 4717 assert(deleted, "interval has not been found in list"); 4718 } 4719 4720 4721 void IntervalWalker::walk_to(IntervalState state, int from) { 4722 assert (state == activeState || state == inactiveState, "wrong state"); 4723 for_each_interval_kind(kind) { 4724 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); 4725 Interval* next = *prev; 4726 while (next->current_from() <= from) { 4727 Interval* cur = next; 4728 next = cur->next(); 4729 4730 bool range_has_changed = false; 4731 while (cur->current_to() <= from) { 4732 cur->next_range(); 4733 range_has_changed = true; 4734 } 4735 4736 // also handle move from inactive list to active list 4737 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); 4738 4739 if (range_has_changed) { 4740 // remove cur from list 4741 *prev = next; 4742 if (cur->current_at_end()) { 4743 // move to handled state (not maintained as a list) 4744 cur->set_state(handledState); 4745 interval_moved(cur, kind, state, handledState); 4746 } else if (cur->current_from() <= from){ 4747 // sort into active list 4748 append_sorted(active_first_addr(kind), cur); 4749 cur->set_state(activeState); 4750 if (*prev == cur) { 4751 assert(state == activeState, "check"); 4752 prev = cur->next_addr(); 4753 } 4754 interval_moved(cur, kind, state, activeState); 4755 } else { 4756 // sort into inactive list 4757 append_sorted(inactive_first_addr(kind), cur); 4758 cur->set_state(inactiveState); 4759 if (*prev == cur) { 4760 assert(state == inactiveState, "check"); 4761 prev = cur->next_addr(); 4762 } 4763 interval_moved(cur, kind, state, inactiveState); 4764 } 4765 } else { 4766 prev = cur->next_addr(); 4767 continue; 4768 } 4769 } 4770 } 4771 } 4772 4773 4774 void IntervalWalker::next_interval() { 4775 IntervalKind kind; 4776 Interval* any = _unhandled_first[anyKind]; 4777 Interval* fixed = _unhandled_first[fixedKind]; 4778 4779 if (any != Interval::end()) { 4780 // intervals may start at same position -> prefer fixed interval 4781 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; 4782 4783 assert (kind == fixedKind && fixed->from() <= any->from() || 4784 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); 4785 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); 4786 4787 } else if (fixed != Interval::end()) { 4788 kind = fixedKind; 4789 } else { 4790 _current = NULL; return; 4791 } 4792 _current_kind = kind; 4793 _current = _unhandled_first[kind]; 4794 _unhandled_first[kind] = _current->next(); 4795 _current->set_next(Interval::end()); 4796 _current->rewind_range(); 4797 } 4798 4799 4800 void IntervalWalker::walk_to(int lir_op_id) { 4801 assert(_current_position <= lir_op_id, "can not walk backwards"); 4802 while (current() != NULL) { 4803 bool is_active = current()->from() <= lir_op_id; 4804 int id = is_active ? current()->from() : lir_op_id; 4805 4806 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) 4807 4808 // set _current_position prior to call of walk_to 4809 _current_position = id; 4810 4811 // call walk_to even if _current_position == id 4812 walk_to(activeState, id); 4813 walk_to(inactiveState, id); 4814 4815 if (is_active) { 4816 current()->set_state(activeState); 4817 if (activate_current()) { 4818 append_sorted(active_first_addr(current_kind()), current()); 4819 interval_moved(current(), current_kind(), unhandledState, activeState); 4820 } 4821 4822 next_interval(); 4823 } else { 4824 return; 4825 } 4826 } 4827 } 4828 4829 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { 4830 #ifndef PRODUCT 4831 if (TraceLinearScanLevel >= 4) { 4832 #define print_state(state) \ 4833 switch(state) {\ 4834 case unhandledState: tty->print("unhandled"); break;\ 4835 case activeState: tty->print("active"); break;\ 4836 case inactiveState: tty->print("inactive"); break;\ 4837 case handledState: tty->print("handled"); break;\ 4838 default: ShouldNotReachHere(); \ 4839 } 4840 4841 print_state(from); tty->print(" to "); print_state(to); 4842 tty->fill_to(23); 4843 interval->print(); 4844 4845 #undef print_state 4846 } 4847 #endif 4848 } 4849 4850 4851 4852 // **** Implementation of LinearScanWalker ************************** 4853 4854 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4855 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) 4856 , _move_resolver(allocator) 4857 { 4858 for (int i = 0; i < LinearScan::nof_regs; i++) { 4859 _spill_intervals[i] = new IntervalList(2); 4860 } 4861 } 4862 4863 4864 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { 4865 for (int i = _first_reg; i <= _last_reg; i++) { 4866 _use_pos[i] = max_jint; 4867 4868 if (!only_process_use_pos) { 4869 _block_pos[i] = max_jint; 4870 _spill_intervals[i]->clear(); 4871 } 4872 } 4873 } 4874 4875 inline void LinearScanWalker::exclude_from_use(int reg) { 4876 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); 4877 if (reg >= _first_reg && reg <= _last_reg) { 4878 _use_pos[reg] = 0; 4879 } 4880 } 4881 inline void LinearScanWalker::exclude_from_use(Interval* i) { 4882 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4883 4884 exclude_from_use(i->assigned_reg()); 4885 exclude_from_use(i->assigned_regHi()); 4886 } 4887 4888 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { 4889 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); 4890 4891 if (reg >= _first_reg && reg <= _last_reg) { 4892 if (_use_pos[reg] > use_pos) { 4893 _use_pos[reg] = use_pos; 4894 } 4895 if (!only_process_use_pos) { 4896 _spill_intervals[reg]->append(i); 4897 } 4898 } 4899 } 4900 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { 4901 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4902 if (use_pos != -1) { 4903 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); 4904 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); 4905 } 4906 } 4907 4908 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { 4909 if (reg >= _first_reg && reg <= _last_reg) { 4910 if (_block_pos[reg] > block_pos) { 4911 _block_pos[reg] = block_pos; 4912 } 4913 if (_use_pos[reg] > block_pos) { 4914 _use_pos[reg] = block_pos; 4915 } 4916 } 4917 } 4918 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { 4919 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4920 if (block_pos != -1) { 4921 set_block_pos(i->assigned_reg(), i, block_pos); 4922 set_block_pos(i->assigned_regHi(), i, block_pos); 4923 } 4924 } 4925 4926 4927 void LinearScanWalker::free_exclude_active_fixed() { 4928 Interval* list = active_first(fixedKind); 4929 while (list != Interval::end()) { 4930 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); 4931 exclude_from_use(list); 4932 list = list->next(); 4933 } 4934 } 4935 4936 void LinearScanWalker::free_exclude_active_any() { 4937 Interval* list = active_first(anyKind); 4938 while (list != Interval::end()) { 4939 exclude_from_use(list); 4940 list = list->next(); 4941 } 4942 } 4943 4944 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { 4945 Interval* list = inactive_first(fixedKind); 4946 while (list != Interval::end()) { 4947 if (cur->to() <= list->current_from()) { 4948 assert(list->current_intersects_at(cur) == -1, "must not intersect"); 4949 set_use_pos(list, list->current_from(), true); 4950 } else { 4951 set_use_pos(list, list->current_intersects_at(cur), true); 4952 } 4953 list = list->next(); 4954 } 4955 } 4956 4957 void LinearScanWalker::free_collect_inactive_any(Interval* cur) { 4958 Interval* list = inactive_first(anyKind); 4959 while (list != Interval::end()) { 4960 set_use_pos(list, list->current_intersects_at(cur), true); 4961 list = list->next(); 4962 } 4963 } 4964 4965 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { 4966 Interval* list = unhandled_first(kind); 4967 while (list != Interval::end()) { 4968 set_use_pos(list, list->intersects_at(cur), true); 4969 if (kind == fixedKind && cur->to() <= list->from()) { 4970 set_use_pos(list, list->from(), true); 4971 } 4972 list = list->next(); 4973 } 4974 } 4975 4976 void LinearScanWalker::spill_exclude_active_fixed() { 4977 Interval* list = active_first(fixedKind); 4978 while (list != Interval::end()) { 4979 exclude_from_use(list); 4980 list = list->next(); 4981 } 4982 } 4983 4984 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { 4985 Interval* list = unhandled_first(fixedKind); 4986 while (list != Interval::end()) { 4987 set_block_pos(list, list->intersects_at(cur)); 4988 list = list->next(); 4989 } 4990 } 4991 4992 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { 4993 Interval* list = inactive_first(fixedKind); 4994 while (list != Interval::end()) { 4995 if (cur->to() > list->current_from()) { 4996 set_block_pos(list, list->current_intersects_at(cur)); 4997 } else { 4998 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); 4999 } 5000 5001 list = list->next(); 5002 } 5003 } 5004 5005 void LinearScanWalker::spill_collect_active_any() { 5006 Interval* list = active_first(anyKind); 5007 while (list != Interval::end()) { 5008 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 5009 list = list->next(); 5010 } 5011 } 5012 5013 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { 5014 Interval* list = inactive_first(anyKind); 5015 while (list != Interval::end()) { 5016 if (list->current_intersects(cur)) { 5017 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 5018 } 5019 list = list->next(); 5020 } 5021 } 5022 5023 5024 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { 5025 // output all moves here. When source and target are equal, the move is 5026 // optimized away later in assign_reg_nums 5027 5028 op_id = (op_id + 1) & ~1; 5029 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); 5030 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); 5031 5032 // calculate index of instruction inside instruction list of current block 5033 // the minimal index (for a block with no spill moves) can be calculated because the 5034 // numbering of instructions is known. 5035 // When the block already contains spill moves, the index must be increased until the 5036 // correct index is reached. 5037 LIR_OpList* list = op_block->lir()->instructions_list(); 5038 int index = (op_id - list->at(0)->id()) / 2; 5039 assert(list->at(index)->id() <= op_id, "error in calculation"); 5040 5041 while (list->at(index)->id() != op_id) { 5042 index++; 5043 assert(0 <= index && index < list->length(), "index out of bounds"); 5044 } 5045 assert(1 <= index && index < list->length(), "index out of bounds"); 5046 assert(list->at(index)->id() == op_id, "error in calculation"); 5047 5048 // insert new instruction before instruction at position index 5049 _move_resolver.move_insert_position(op_block->lir(), index - 1); 5050 _move_resolver.add_mapping(src_it, dst_it); 5051 } 5052 5053 5054 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { 5055 int from_block_nr = min_block->linear_scan_number(); 5056 int to_block_nr = max_block->linear_scan_number(); 5057 5058 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); 5059 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); 5060 assert(from_block_nr < to_block_nr, "must cross block boundary"); 5061 5062 // Try to split at end of max_block. If this would be after 5063 // max_split_pos, then use the begin of max_block 5064 int optimal_split_pos = max_block->last_lir_instruction_id() + 2; 5065 if (optimal_split_pos > max_split_pos) { 5066 optimal_split_pos = max_block->first_lir_instruction_id(); 5067 } 5068 5069 int min_loop_depth = max_block->loop_depth(); 5070 for (int i = to_block_nr - 1; i >= from_block_nr; i--) { 5071 BlockBegin* cur = block_at(i); 5072 5073 if (cur->loop_depth() < min_loop_depth) { 5074 // block with lower loop-depth found -> split at the end of this block 5075 min_loop_depth = cur->loop_depth(); 5076 optimal_split_pos = cur->last_lir_instruction_id() + 2; 5077 } 5078 } 5079 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); 5080 5081 return optimal_split_pos; 5082 } 5083 5084 5085 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { 5086 int optimal_split_pos = -1; 5087 if (min_split_pos == max_split_pos) { 5088 // trivial case, no optimization of split position possible 5089 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); 5090 optimal_split_pos = min_split_pos; 5091 5092 } else { 5093 assert(min_split_pos < max_split_pos, "must be true then"); 5094 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); 5095 5096 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the 5097 // beginning of a block, then min_split_pos is also a possible split position. 5098 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos 5099 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); 5100 5101 // reason for using max_split_pos - 1: otherwise there would be an assertion failure 5102 // when an interval ends at the end of the last block of the method 5103 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no 5104 // block at this op_id) 5105 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); 5106 5107 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); 5108 if (min_block == max_block) { 5109 // split position cannot be moved to block boundary, so split as late as possible 5110 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); 5111 optimal_split_pos = max_split_pos; 5112 5113 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { 5114 // Do not move split position if the interval has a hole before max_split_pos. 5115 // Intervals resulting from Phi-Functions have more than one definition (marked 5116 // as mustHaveRegister) with a hole before each definition. When the register is needed 5117 // for the second definition, an earlier reloading is unnecessary. 5118 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); 5119 optimal_split_pos = max_split_pos; 5120 5121 } else { 5122 // seach optimal block boundary between min_split_pos and max_split_pos 5123 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); 5124 5125 if (do_loop_optimization) { 5126 // Loop optimization: if a loop-end marker is found between min- and max-position, 5127 // then split before this loop 5128 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); 5129 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); 5130 5131 assert(loop_end_pos > min_split_pos, "invalid order"); 5132 if (loop_end_pos < max_split_pos) { 5133 // loop-end marker found between min- and max-position 5134 // if it is not the end marker for the same loop as the min-position, then move 5135 // the max-position to this loop block. 5136 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading 5137 // of the interval (normally, only mustHaveRegister causes a reloading) 5138 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); 5139 5140 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); 5141 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); 5142 5143 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); 5144 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { 5145 optimal_split_pos = -1; 5146 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); 5147 } else { 5148 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); 5149 } 5150 } 5151 } 5152 5153 if (optimal_split_pos == -1) { 5154 // not calculated by loop optimization 5155 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); 5156 } 5157 } 5158 } 5159 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); 5160 5161 return optimal_split_pos; 5162 } 5163 5164 5165 /* 5166 split an interval at the optimal position between min_split_pos and 5167 max_split_pos in two parts: 5168 1) the left part has already a location assigned 5169 2) the right part is sorted into to the unhandled-list 5170 */ 5171 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { 5172 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); 5173 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5174 5175 assert(it->from() < min_split_pos, "cannot split at start of interval"); 5176 assert(current_position() < min_split_pos, "cannot split before current position"); 5177 assert(min_split_pos <= max_split_pos, "invalid order"); 5178 assert(max_split_pos <= it->to(), "cannot split after end of interval"); 5179 5180 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); 5181 5182 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5183 assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); 5184 assert(optimal_split_pos > it->from(), "cannot split at start of interval"); 5185 5186 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { 5187 // the split position would be just before the end of the interval 5188 // -> no split at all necessary 5189 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); 5190 return; 5191 } 5192 5193 // must calculate this before the actual split is performed and before split position is moved to odd op_id 5194 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); 5195 5196 if (!allocator()->is_block_begin(optimal_split_pos)) { 5197 // move position before actual instruction (odd op_id) 5198 optimal_split_pos = (optimal_split_pos - 1) | 1; 5199 } 5200 5201 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5202 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5203 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5204 5205 Interval* split_part = it->split(optimal_split_pos); 5206 5207 allocator()->append_interval(split_part); 5208 allocator()->copy_register_flags(it, split_part); 5209 split_part->set_insert_move_when_activated(move_necessary); 5210 append_to_unhandled(unhandled_first_addr(anyKind), split_part); 5211 5212 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); 5213 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5214 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); 5215 } 5216 5217 /* 5218 split an interval at the optimal position between min_split_pos and 5219 max_split_pos in two parts: 5220 1) the left part has already a location assigned 5221 2) the right part is always on the stack and therefore ignored in further processing 5222 */ 5223 void LinearScanWalker::split_for_spilling(Interval* it) { 5224 // calculate allowed range of splitting position 5225 int max_split_pos = current_position(); 5226 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); 5227 5228 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); 5229 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5230 5231 assert(it->state() == activeState, "why spill interval that is not active?"); 5232 assert(it->from() <= min_split_pos, "cannot split before start of interval"); 5233 assert(min_split_pos <= max_split_pos, "invalid order"); 5234 assert(max_split_pos < it->to(), "cannot split at end end of interval"); 5235 assert(current_position() < it->to(), "interval must not end before current position"); 5236 5237 if (min_split_pos == it->from()) { 5238 // the whole interval is never used, so spill it entirely to memory 5239 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); 5240 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); 5241 5242 allocator()->assign_spill_slot(it); 5243 allocator()->change_spill_state(it, min_split_pos); 5244 5245 // Also kick parent intervals out of register to memory when they have no use 5246 // position. This avoids short interval in register surrounded by intervals in 5247 // memory -> avoid useless moves from memory to register and back 5248 Interval* parent = it; 5249 while (parent != NULL && parent->is_split_child()) { 5250 parent = parent->split_child_before_op_id(parent->from()); 5251 5252 if (parent->assigned_reg() < LinearScan::nof_regs) { 5253 if (parent->first_usage(shouldHaveRegister) == max_jint) { 5254 // parent is never used, so kick it out of its assigned register 5255 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); 5256 allocator()->assign_spill_slot(parent); 5257 } else { 5258 // do not go further back because the register is actually used by the interval 5259 parent = NULL; 5260 } 5261 } 5262 } 5263 5264 } else { 5265 // search optimal split pos, split interval and spill only the right hand part 5266 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); 5267 5268 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5269 assert(optimal_split_pos < it->to(), "cannot split at end of interval"); 5270 assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); 5271 5272 if (!allocator()->is_block_begin(optimal_split_pos)) { 5273 // move position before actual instruction (odd op_id) 5274 optimal_split_pos = (optimal_split_pos - 1) | 1; 5275 } 5276 5277 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5278 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5279 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5280 5281 Interval* spilled_part = it->split(optimal_split_pos); 5282 allocator()->append_interval(spilled_part); 5283 allocator()->assign_spill_slot(spilled_part); 5284 allocator()->change_spill_state(spilled_part, optimal_split_pos); 5285 5286 if (!allocator()->is_block_begin(optimal_split_pos)) { 5287 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); 5288 insert_move(optimal_split_pos, it, spilled_part); 5289 } 5290 5291 // the current_split_child is needed later when moves are inserted for reloading 5292 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); 5293 spilled_part->make_current_split_child(); 5294 5295 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); 5296 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5297 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); 5298 } 5299 } 5300 5301 5302 void LinearScanWalker::split_stack_interval(Interval* it) { 5303 int min_split_pos = current_position() + 1; 5304 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); 5305 5306 split_before_usage(it, min_split_pos, max_split_pos); 5307 } 5308 5309 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { 5310 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); 5311 int max_split_pos = register_available_until; 5312 5313 split_before_usage(it, min_split_pos, max_split_pos); 5314 } 5315 5316 void LinearScanWalker::split_and_spill_interval(Interval* it) { 5317 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); 5318 5319 int current_pos = current_position(); 5320 if (it->state() == inactiveState) { 5321 // the interval is currently inactive, so no spill slot is needed for now. 5322 // when the split part is activated, the interval has a new chance to get a register, 5323 // so in the best case no stack slot is necessary 5324 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); 5325 split_before_usage(it, current_pos + 1, current_pos + 1); 5326 5327 } else { 5328 // search the position where the interval must have a register and split 5329 // at the optimal position before. 5330 // The new created part is added to the unhandled list and will get a register 5331 // when it is activated 5332 int min_split_pos = current_pos + 1; 5333 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); 5334 5335 split_before_usage(it, min_split_pos, max_split_pos); 5336 5337 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); 5338 split_for_spilling(it); 5339 } 5340 } 5341 5342 5343 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5344 int min_full_reg = any_reg; 5345 int max_partial_reg = any_reg; 5346 5347 for (int i = _first_reg; i <= _last_reg; i++) { 5348 if (i == ignore_reg) { 5349 // this register must be ignored 5350 5351 } else if (_use_pos[i] >= interval_to) { 5352 // this register is free for the full interval 5353 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5354 min_full_reg = i; 5355 } 5356 } else if (_use_pos[i] > reg_needed_until) { 5357 // this register is at least free until reg_needed_until 5358 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5359 max_partial_reg = i; 5360 } 5361 } 5362 } 5363 5364 if (min_full_reg != any_reg) { 5365 return min_full_reg; 5366 } else if (max_partial_reg != any_reg) { 5367 *need_split = true; 5368 return max_partial_reg; 5369 } else { 5370 return any_reg; 5371 } 5372 } 5373 5374 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5375 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5376 5377 int min_full_reg = any_reg; 5378 int max_partial_reg = any_reg; 5379 5380 for (int i = _first_reg; i < _last_reg; i+=2) { 5381 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { 5382 // this register is free for the full interval 5383 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5384 min_full_reg = i; 5385 } 5386 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5387 // this register is at least free until reg_needed_until 5388 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5389 max_partial_reg = i; 5390 } 5391 } 5392 } 5393 5394 if (min_full_reg != any_reg) { 5395 return min_full_reg; 5396 } else if (max_partial_reg != any_reg) { 5397 *need_split = true; 5398 return max_partial_reg; 5399 } else { 5400 return any_reg; 5401 } 5402 } 5403 5404 5405 bool LinearScanWalker::alloc_free_reg(Interval* cur) { 5406 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); 5407 5408 init_use_lists(true); 5409 free_exclude_active_fixed(); 5410 free_exclude_active_any(); 5411 free_collect_inactive_fixed(cur); 5412 free_collect_inactive_any(cur); 5413 // free_collect_unhandled(fixedKind, cur); 5414 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5415 5416 // _use_pos contains the start of the next interval that has this register assigned 5417 // (either as a fixed register or a normal allocated register in the past) 5418 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely 5419 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); 5420 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); 5421 5422 int hint_reg, hint_regHi; 5423 Interval* register_hint = cur->register_hint(); 5424 if (register_hint != NULL) { 5425 hint_reg = register_hint->assigned_reg(); 5426 hint_regHi = register_hint->assigned_regHi(); 5427 5428 if (allocator()->is_precolored_cpu_interval(register_hint)) { 5429 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); 5430 hint_regHi = hint_reg + 1; // connect e.g. eax-edx 5431 } 5432 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); 5433 5434 } else { 5435 hint_reg = any_reg; 5436 hint_regHi = any_reg; 5437 } 5438 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); 5439 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); 5440 5441 // the register must be free at least until this position 5442 int reg_needed_until = cur->from() + 1; 5443 int interval_to = cur->to(); 5444 5445 bool need_split = false; 5446 int split_pos = -1; 5447 int reg = any_reg; 5448 int regHi = any_reg; 5449 5450 if (_adjacent_regs) { 5451 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); 5452 regHi = reg + 1; 5453 if (reg == any_reg) { 5454 return false; 5455 } 5456 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5457 5458 } else { 5459 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); 5460 if (reg == any_reg) { 5461 return false; 5462 } 5463 split_pos = _use_pos[reg]; 5464 5465 if (_num_phys_regs == 2) { 5466 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); 5467 5468 if (_use_pos[reg] < interval_to && regHi == any_reg) { 5469 // do not split interval if only one register can be assigned until the split pos 5470 // (when one register is found for the whole interval, split&spill is only 5471 // performed for the hi register) 5472 return false; 5473 5474 } else if (regHi != any_reg) { 5475 split_pos = MIN2(split_pos, _use_pos[regHi]); 5476 5477 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5478 if (reg > regHi) { 5479 int temp = reg; 5480 reg = regHi; 5481 regHi = temp; 5482 } 5483 } 5484 } 5485 } 5486 5487 cur->assign_reg(reg, regHi); 5488 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); 5489 5490 assert(split_pos > 0, "invalid split_pos"); 5491 if (need_split) { 5492 // register not available for full interval, so split it 5493 split_when_partial_register_available(cur, split_pos); 5494 } 5495 5496 // only return true if interval is completely assigned 5497 return _num_phys_regs == 1 || regHi != any_reg; 5498 } 5499 5500 5501 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5502 int max_reg = any_reg; 5503 5504 for (int i = _first_reg; i <= _last_reg; i++) { 5505 if (i == ignore_reg) { 5506 // this register must be ignored 5507 5508 } else if (_use_pos[i] > reg_needed_until) { 5509 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { 5510 max_reg = i; 5511 } 5512 } 5513 } 5514 5515 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { 5516 *need_split = true; 5517 } 5518 5519 return max_reg; 5520 } 5521 5522 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5523 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5524 5525 int max_reg = any_reg; 5526 5527 for (int i = _first_reg; i < _last_reg; i+=2) { 5528 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5529 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { 5530 max_reg = i; 5531 } 5532 } 5533 } 5534 5535 if (max_reg != any_reg && 5536 (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) { 5537 *need_split = true; 5538 } 5539 5540 return max_reg; 5541 } 5542 5543 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { 5544 assert(reg != any_reg, "no register assigned"); 5545 5546 for (int i = 0; i < _spill_intervals[reg]->length(); i++) { 5547 Interval* it = _spill_intervals[reg]->at(i); 5548 remove_from_list(it); 5549 split_and_spill_interval(it); 5550 } 5551 5552 if (regHi != any_reg) { 5553 IntervalList* processed = _spill_intervals[reg]; 5554 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { 5555 Interval* it = _spill_intervals[regHi]->at(i); 5556 if (processed->find(it) == -1) { 5557 remove_from_list(it); 5558 split_and_spill_interval(it); 5559 } 5560 } 5561 } 5562 } 5563 5564 5565 // Split an Interval and spill it to memory so that cur can be placed in a register 5566 void LinearScanWalker::alloc_locked_reg(Interval* cur) { 5567 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); 5568 5569 // collect current usage of registers 5570 init_use_lists(false); 5571 spill_exclude_active_fixed(); 5572 // spill_block_unhandled_fixed(cur); 5573 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5574 spill_block_inactive_fixed(cur); 5575 spill_collect_active_any(); 5576 spill_collect_inactive_any(cur); 5577 5578 #ifndef PRODUCT 5579 if (TraceLinearScanLevel >= 4) { 5580 tty->print_cr(" state of registers:"); 5581 for (int i = _first_reg; i <= _last_reg; i++) { 5582 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); 5583 for (int j = 0; j < _spill_intervals[i]->length(); j++) { 5584 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); 5585 } 5586 tty->cr(); 5587 } 5588 } 5589 #endif 5590 5591 // the register must be free at least until this position 5592 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); 5593 int interval_to = cur->to(); 5594 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); 5595 5596 int split_pos = 0; 5597 int use_pos = 0; 5598 bool need_split = false; 5599 int reg, regHi; 5600 5601 if (_adjacent_regs) { 5602 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); 5603 regHi = reg + 1; 5604 5605 if (reg != any_reg) { 5606 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5607 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); 5608 } 5609 } else { 5610 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); 5611 regHi = any_reg; 5612 5613 if (reg != any_reg) { 5614 use_pos = _use_pos[reg]; 5615 split_pos = _block_pos[reg]; 5616 5617 if (_num_phys_regs == 2) { 5618 if (cur->assigned_reg() != any_reg) { 5619 regHi = reg; 5620 reg = cur->assigned_reg(); 5621 } else { 5622 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); 5623 if (regHi != any_reg) { 5624 use_pos = MIN2(use_pos, _use_pos[regHi]); 5625 split_pos = MIN2(split_pos, _block_pos[regHi]); 5626 } 5627 } 5628 5629 if (regHi != any_reg && reg > regHi) { 5630 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5631 int temp = reg; 5632 reg = regHi; 5633 regHi = temp; 5634 } 5635 } 5636 } 5637 } 5638 5639 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { 5640 // the first use of cur is later than the spilling position -> spill cur 5641 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); 5642 5643 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { 5644 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); 5645 // assign a reasonable register and do a bailout in product mode to avoid errors 5646 allocator()->assign_spill_slot(cur); 5647 BAILOUT("LinearScan: no register found"); 5648 } 5649 5650 split_and_spill_interval(cur); 5651 } else { 5652 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); 5653 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); 5654 assert(split_pos > 0, "invalid split_pos"); 5655 assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); 5656 5657 cur->assign_reg(reg, regHi); 5658 if (need_split) { 5659 // register not available for full interval, so split it 5660 split_when_partial_register_available(cur, split_pos); 5661 } 5662 5663 // perform splitting and spilling for all affected intervalls 5664 split_and_spill_intersecting_intervals(reg, regHi); 5665 } 5666 } 5667 5668 bool LinearScanWalker::no_allocation_possible(Interval* cur) { 5669 #ifdef X86 5670 // fast calculation of intervals that can never get a register because the 5671 // the next instruction is a call that blocks all registers 5672 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) 5673 5674 // check if this interval is the result of a split operation 5675 // (an interval got a register until this position) 5676 int pos = cur->from(); 5677 if ((pos & 1) == 1) { 5678 // the current instruction is a call that blocks all registers 5679 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { 5680 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); 5681 5682 // safety check that there is really no register available 5683 assert(alloc_free_reg(cur) == false, "found a register for this interval"); 5684 return true; 5685 } 5686 5687 } 5688 #endif 5689 return false; 5690 } 5691 5692 void LinearScanWalker::init_vars_for_alloc(Interval* cur) { 5693 BasicType type = cur->type(); 5694 _num_phys_regs = LinearScan::num_physical_regs(type); 5695 _adjacent_regs = LinearScan::requires_adjacent_regs(type); 5696 5697 if (pd_init_regs_for_alloc(cur)) { 5698 // the appropriate register range was selected. 5699 } else if (type == T_FLOAT || type == T_DOUBLE) { 5700 _first_reg = pd_first_fpu_reg; 5701 _last_reg = pd_last_fpu_reg; 5702 } else { 5703 _first_reg = pd_first_cpu_reg; 5704 _last_reg = FrameMap::last_cpu_reg(); 5705 } 5706 5707 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); 5708 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); 5709 } 5710 5711 5712 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { 5713 if (op->code() != lir_move) { 5714 return false; 5715 } 5716 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 5717 5718 LIR_Opr in = ((LIR_Op1*)op)->in_opr(); 5719 LIR_Opr res = ((LIR_Op1*)op)->result_opr(); 5720 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); 5721 } 5722 5723 // optimization (especially for phi functions of nested loops): 5724 // assign same spill slot to non-intersecting intervals 5725 void LinearScanWalker::combine_spilled_intervals(Interval* cur) { 5726 if (cur->is_split_child()) { 5727 // optimization is only suitable for split parents 5728 return; 5729 } 5730 5731 Interval* register_hint = cur->register_hint(false); 5732 if (register_hint == NULL) { 5733 // cur is not the target of a move, otherwise register_hint would be set 5734 return; 5735 } 5736 assert(register_hint->is_split_parent(), "register hint must be split parent"); 5737 5738 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { 5739 // combining the stack slots for intervals where spill move optimization is applied 5740 // is not benefitial and would cause problems 5741 return; 5742 } 5743 5744 int begin_pos = cur->from(); 5745 int end_pos = cur->to(); 5746 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { 5747 // safety check that lir_op_with_id is allowed 5748 return; 5749 } 5750 5751 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { 5752 // cur and register_hint are not connected with two moves 5753 return; 5754 } 5755 5756 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); 5757 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); 5758 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { 5759 // register_hint must be split, otherwise the re-writing of use positions does not work 5760 return; 5761 } 5762 5763 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); 5764 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); 5765 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); 5766 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); 5767 5768 if (begin_hint->assigned_reg() < LinearScan::nof_regs) { 5769 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur 5770 return; 5771 } 5772 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); 5773 5774 // modify intervals such that cur gets the same stack slot as register_hint 5775 // delete use positions to prevent the intervals to get a register at beginning 5776 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); 5777 cur->remove_first_use_pos(); 5778 end_hint->remove_first_use_pos(); 5779 } 5780 5781 5782 // allocate a physical register or memory location to an interval 5783 bool LinearScanWalker::activate_current() { 5784 Interval* cur = current(); 5785 bool result = true; 5786 5787 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); 5788 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); 5789 5790 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5791 // activating an interval that has a stack slot assigned -> split it at first use position 5792 // used for method parameters 5793 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); 5794 5795 split_stack_interval(cur); 5796 result = false; 5797 5798 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { 5799 // activating an interval that must start in a stack slot, but may get a register later 5800 // used for lir_roundfp: rounding is done by store to stack and reload later 5801 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); 5802 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); 5803 5804 allocator()->assign_spill_slot(cur); 5805 split_stack_interval(cur); 5806 result = false; 5807 5808 } else if (cur->assigned_reg() == any_reg) { 5809 // interval has not assigned register -> normal allocation 5810 // (this is the normal case for most intervals) 5811 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); 5812 5813 // assign same spill slot to non-intersecting intervals 5814 combine_spilled_intervals(cur); 5815 5816 init_vars_for_alloc(cur); 5817 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { 5818 // no empty register available. 5819 // split and spill another interval so that this interval gets a register 5820 alloc_locked_reg(cur); 5821 } 5822 5823 // spilled intervals need not be move to active-list 5824 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5825 result = false; 5826 } 5827 } 5828 5829 // load spilled values that become active from stack slot to register 5830 if (cur->insert_move_when_activated()) { 5831 assert(cur->is_split_child(), "must be"); 5832 assert(cur->current_split_child() != NULL, "must be"); 5833 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); 5834 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); 5835 5836 insert_move(cur->from(), cur->current_split_child(), cur); 5837 } 5838 cur->make_current_split_child(); 5839 5840 return result; // true = interval is moved to active list 5841 } 5842 5843 5844 // Implementation of EdgeMoveOptimizer 5845 5846 EdgeMoveOptimizer::EdgeMoveOptimizer() : 5847 _edge_instructions(4), 5848 _edge_instructions_idx(4) 5849 { 5850 } 5851 5852 void EdgeMoveOptimizer::optimize(BlockList* code) { 5853 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); 5854 5855 // ignore the first block in the list (index 0 is not processed) 5856 for (int i = code->length() - 1; i >= 1; i--) { 5857 BlockBegin* block = code->at(i); 5858 5859 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { 5860 optimizer.optimize_moves_at_block_end(block); 5861 } 5862 if (block->number_of_sux() == 2) { 5863 optimizer.optimize_moves_at_block_begin(block); 5864 } 5865 } 5866 } 5867 5868 5869 // clear all internal data structures 5870 void EdgeMoveOptimizer::init_instructions() { 5871 _edge_instructions.clear(); 5872 _edge_instructions_idx.clear(); 5873 } 5874 5875 // append a lir-instruction-list and the index of the current operation in to the list 5876 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { 5877 _edge_instructions.append(instructions); 5878 _edge_instructions_idx.append(instructions_idx); 5879 } 5880 5881 // return the current operation of the given edge (predecessor or successor) 5882 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { 5883 LIR_OpList* instructions = _edge_instructions.at(edge); 5884 int idx = _edge_instructions_idx.at(edge); 5885 5886 if (idx < instructions->length()) { 5887 return instructions->at(idx); 5888 } else { 5889 return NULL; 5890 } 5891 } 5892 5893 // removes the current operation of the given edge (predecessor or successor) 5894 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { 5895 LIR_OpList* instructions = _edge_instructions.at(edge); 5896 int idx = _edge_instructions_idx.at(edge); 5897 instructions->remove_at(idx); 5898 5899 if (decrement_index) { 5900 _edge_instructions_idx.at_put(edge, idx - 1); 5901 } 5902 } 5903 5904 5905 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { 5906 if (op1 == NULL || op2 == NULL) { 5907 // at least one block is already empty -> no optimization possible 5908 return true; 5909 } 5910 5911 if (op1->code() == lir_move && op2->code() == lir_move) { 5912 assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); 5913 assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); 5914 LIR_Op1* move1 = (LIR_Op1*)op1; 5915 LIR_Op1* move2 = (LIR_Op1*)op2; 5916 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { 5917 // these moves are exactly equal and can be optimized 5918 return false; 5919 } 5920 5921 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { 5922 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); 5923 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); 5924 LIR_Op1* fxch1 = (LIR_Op1*)op1; 5925 LIR_Op1* fxch2 = (LIR_Op1*)op2; 5926 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { 5927 // equal FPU stack operations can be optimized 5928 return false; 5929 } 5930 5931 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { 5932 // equal FPU stack operations can be optimized 5933 return false; 5934 } 5935 5936 // no optimization possible 5937 return true; 5938 } 5939 5940 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { 5941 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); 5942 5943 if (block->is_predecessor(block)) { 5944 // currently we can't handle this correctly. 5945 return; 5946 } 5947 5948 init_instructions(); 5949 int num_preds = block->number_of_preds(); 5950 assert(num_preds > 1, "do not call otherwise"); 5951 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 5952 5953 // setup a list with the lir-instructions of all predecessors 5954 int i; 5955 for (i = 0; i < num_preds; i++) { 5956 BlockBegin* pred = block->pred_at(i); 5957 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 5958 5959 if (pred->number_of_sux() != 1) { 5960 // this can happen with switch-statements where multiple edges are between 5961 // the same blocks. 5962 return; 5963 } 5964 5965 assert(pred->number_of_sux() == 1, "can handle only one successor"); 5966 assert(pred->sux_at(0) == block, "invalid control flow"); 5967 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 5968 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 5969 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 5970 5971 if (pred_instructions->last()->info() != NULL) { 5972 // can not optimize instructions when debug info is needed 5973 return; 5974 } 5975 5976 // ignore the unconditional branch at the end of the block 5977 append_instructions(pred_instructions, pred_instructions->length() - 2); 5978 } 5979 5980 5981 // process lir-instructions while all predecessors end with the same instruction 5982 while (true) { 5983 LIR_Op* op = instruction_at(0); 5984 for (i = 1; i < num_preds; i++) { 5985 if (operations_different(op, instruction_at(i))) { 5986 // these instructions are different and cannot be optimized -> 5987 // no further optimization possible 5988 return; 5989 } 5990 } 5991 5992 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); 5993 5994 // insert the instruction at the beginning of the current block 5995 block->lir()->insert_before(1, op); 5996 5997 // delete the instruction at the end of all predecessors 5998 for (i = 0; i < num_preds; i++) { 5999 remove_cur_instruction(i, true); 6000 } 6001 } 6002 } 6003 6004 6005 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { 6006 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); 6007 6008 init_instructions(); 6009 int num_sux = block->number_of_sux(); 6010 6011 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 6012 6013 assert(num_sux == 2, "method should not be called otherwise"); 6014 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 6015 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 6016 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 6017 6018 if (cur_instructions->last()->info() != NULL) { 6019 // can no optimize instructions when debug info is needed 6020 return; 6021 } 6022 6023 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); 6024 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { 6025 // not a valid case for optimization 6026 // currently, only blocks that end with two branches (conditional branch followed 6027 // by unconditional branch) are optimized 6028 return; 6029 } 6030 6031 // now it is guaranteed that the block ends with two branch instructions. 6032 // the instructions are inserted at the end of the block before these two branches 6033 int insert_idx = cur_instructions->length() - 2; 6034 6035 int i; 6036 #ifdef ASSERT 6037 for (i = insert_idx - 1; i >= 0; i--) { 6038 LIR_Op* op = cur_instructions->at(i); 6039 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { 6040 assert(false, "block with two successors can have only two branch instructions"); 6041 } 6042 } 6043 #endif 6044 6045 // setup a list with the lir-instructions of all successors 6046 for (i = 0; i < num_sux; i++) { 6047 BlockBegin* sux = block->sux_at(i); 6048 LIR_OpList* sux_instructions = sux->lir()->instructions_list(); 6049 6050 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); 6051 6052 if (sux->number_of_preds() != 1) { 6053 // this can happen with switch-statements where multiple edges are between 6054 // the same blocks. 6055 return; 6056 } 6057 assert(sux->pred_at(0) == block, "invalid control flow"); 6058 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 6059 6060 // ignore the label at the beginning of the block 6061 append_instructions(sux_instructions, 1); 6062 } 6063 6064 // process lir-instructions while all successors begin with the same instruction 6065 while (true) { 6066 LIR_Op* op = instruction_at(0); 6067 for (i = 1; i < num_sux; i++) { 6068 if (operations_different(op, instruction_at(i))) { 6069 // these instructions are different and cannot be optimized -> 6070 // no further optimization possible 6071 return; 6072 } 6073 } 6074 6075 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); 6076 6077 // insert instruction at end of current block 6078 block->lir()->insert_before(insert_idx, op); 6079 insert_idx++; 6080 6081 // delete the instructions at the beginning of all successors 6082 for (i = 0; i < num_sux; i++) { 6083 remove_cur_instruction(i, false); 6084 } 6085 } 6086 } 6087 6088 6089 // Implementation of ControlFlowOptimizer 6090 6091 ControlFlowOptimizer::ControlFlowOptimizer() : 6092 _original_preds(4) 6093 { 6094 } 6095 6096 void ControlFlowOptimizer::optimize(BlockList* code) { 6097 ControlFlowOptimizer optimizer = ControlFlowOptimizer(); 6098 6099 // push the OSR entry block to the end so that we're not jumping over it. 6100 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); 6101 if (osr_entry) { 6102 int index = osr_entry->linear_scan_number(); 6103 assert(code->at(index) == osr_entry, "wrong index"); 6104 code->remove_at(index); 6105 code->append(osr_entry); 6106 } 6107 6108 optimizer.reorder_short_loops(code); 6109 optimizer.delete_empty_blocks(code); 6110 optimizer.delete_unnecessary_jumps(code); 6111 optimizer.delete_jumps_to_return(code); 6112 } 6113 6114 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { 6115 int i = header_idx + 1; 6116 int max_end = MIN2(header_idx + ShortLoopSize, code->length()); 6117 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { 6118 i++; 6119 } 6120 6121 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { 6122 int end_idx = i - 1; 6123 BlockBegin* end_block = code->at(end_idx); 6124 6125 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { 6126 // short loop from header_idx to end_idx found -> reorder blocks such that 6127 // the header_block is the last block instead of the first block of the loop 6128 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", 6129 end_idx - header_idx + 1, 6130 header_block->block_id(), end_block->block_id())); 6131 6132 for (int j = header_idx; j < end_idx; j++) { 6133 code->at_put(j, code->at(j + 1)); 6134 } 6135 code->at_put(end_idx, header_block); 6136 6137 // correct the flags so that any loop alignment occurs in the right place. 6138 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); 6139 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); 6140 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); 6141 } 6142 } 6143 } 6144 6145 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { 6146 for (int i = code->length() - 1; i >= 0; i--) { 6147 BlockBegin* block = code->at(i); 6148 6149 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { 6150 reorder_short_loop(code, block, i); 6151 } 6152 } 6153 6154 DEBUG_ONLY(verify(code)); 6155 } 6156 6157 // only blocks with exactly one successor can be deleted. Such blocks 6158 // must always end with an unconditional branch to this successor 6159 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { 6160 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { 6161 return false; 6162 } 6163 6164 LIR_OpList* instructions = block->lir()->instructions_list(); 6165 6166 assert(instructions->length() >= 2, "block must have label and branch"); 6167 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6168 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); 6169 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); 6170 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); 6171 6172 // block must have exactly one successor 6173 6174 if (instructions->length() == 2 && instructions->last()->info() == NULL) { 6175 return true; 6176 } 6177 return false; 6178 } 6179 6180 // substitute branch targets in all branch-instructions of this blocks 6181 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { 6182 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); 6183 6184 LIR_OpList* instructions = block->lir()->instructions_list(); 6185 6186 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6187 for (int i = instructions->length() - 1; i >= 1; i--) { 6188 LIR_Op* op = instructions->at(i); 6189 6190 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { 6191 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6192 LIR_OpBranch* branch = (LIR_OpBranch*)op; 6193 6194 if (branch->block() == target_from) { 6195 branch->change_block(target_to); 6196 } 6197 if (branch->ublock() == target_from) { 6198 branch->change_ublock(target_to); 6199 } 6200 } 6201 } 6202 } 6203 6204 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { 6205 int old_pos = 0; 6206 int new_pos = 0; 6207 int num_blocks = code->length(); 6208 6209 while (old_pos < num_blocks) { 6210 BlockBegin* block = code->at(old_pos); 6211 6212 if (can_delete_block(block)) { 6213 BlockBegin* new_target = block->sux_at(0); 6214 6215 // propagate backward branch target flag for correct code alignment 6216 if (block->is_set(BlockBegin::backward_branch_target_flag)) { 6217 new_target->set(BlockBegin::backward_branch_target_flag); 6218 } 6219 6220 // collect a list with all predecessors that contains each predecessor only once 6221 // the predecessors of cur are changed during the substitution, so a copy of the 6222 // predecessor list is necessary 6223 int j; 6224 _original_preds.clear(); 6225 for (j = block->number_of_preds() - 1; j >= 0; j--) { 6226 BlockBegin* pred = block->pred_at(j); 6227 if (_original_preds.find(pred) == -1) { 6228 _original_preds.append(pred); 6229 } 6230 } 6231 6232 for (j = _original_preds.length() - 1; j >= 0; j--) { 6233 BlockBegin* pred = _original_preds.at(j); 6234 substitute_branch_target(pred, block, new_target); 6235 pred->substitute_sux(block, new_target); 6236 } 6237 } else { 6238 // adjust position of this block in the block list if blocks before 6239 // have been deleted 6240 if (new_pos != old_pos) { 6241 code->at_put(new_pos, code->at(old_pos)); 6242 } 6243 new_pos++; 6244 } 6245 old_pos++; 6246 } 6247 code->trunc_to(new_pos); 6248 6249 DEBUG_ONLY(verify(code)); 6250 } 6251 6252 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { 6253 // skip the last block because there a branch is always necessary 6254 for (int i = code->length() - 2; i >= 0; i--) { 6255 BlockBegin* block = code->at(i); 6256 LIR_OpList* instructions = block->lir()->instructions_list(); 6257 6258 LIR_Op* last_op = instructions->last(); 6259 if (last_op->code() == lir_branch) { 6260 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6261 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; 6262 6263 assert(last_branch->block() != NULL, "last branch must always have a block as target"); 6264 assert(last_branch->label() == last_branch->block()->label(), "must be equal"); 6265 6266 if (last_branch->info() == NULL) { 6267 if (last_branch->block() == code->at(i + 1)) { 6268 6269 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); 6270 6271 // delete last branch instruction 6272 instructions->trunc_to(instructions->length() - 1); 6273 6274 } else { 6275 LIR_Op* prev_op = instructions->at(instructions->length() - 2); 6276 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { 6277 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6278 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; 6279 6280 if (prev_branch->stub() == NULL) { 6281 6282 LIR_Op2* prev_cmp = NULL; 6283 // There might be a cmove inserted for profiling which depends on the same 6284 // compare. If we change the condition of the respective compare, we have 6285 // to take care of this cmove as well. 6286 LIR_Op2* prev_cmove = NULL; 6287 6288 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { 6289 prev_op = instructions->at(j); 6290 // check for the cmove 6291 if (prev_op->code() == lir_cmove) { 6292 assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2"); 6293 prev_cmove = (LIR_Op2*)prev_op; 6294 assert(prev_branch->cond() == prev_cmove->condition(), "should be the same"); 6295 } 6296 if (prev_op->code() == lir_cmp) { 6297 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); 6298 prev_cmp = (LIR_Op2*)prev_op; 6299 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); 6300 } 6301 } 6302 assert(prev_cmp != NULL, "should have found comp instruction for branch"); 6303 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { 6304 6305 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); 6306 6307 // eliminate a conditional branch to the immediate successor 6308 prev_branch->change_block(last_branch->block()); 6309 prev_branch->negate_cond(); 6310 prev_cmp->set_condition(prev_branch->cond()); 6311 instructions->trunc_to(instructions->length() - 1); 6312 // if we do change the condition, we have to change the cmove as well 6313 if (prev_cmove != NULL) { 6314 prev_cmove->set_condition(prev_branch->cond()); 6315 LIR_Opr t = prev_cmove->in_opr1(); 6316 prev_cmove->set_in_opr1(prev_cmove->in_opr2()); 6317 prev_cmove->set_in_opr2(t); 6318 } 6319 } 6320 } 6321 } 6322 } 6323 } 6324 } 6325 } 6326 6327 DEBUG_ONLY(verify(code)); 6328 } 6329 6330 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { 6331 #ifdef ASSERT 6332 ResourceBitMap return_converted(BlockBegin::number_of_blocks()); 6333 #endif 6334 6335 for (int i = code->length() - 1; i >= 0; i--) { 6336 BlockBegin* block = code->at(i); 6337 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 6338 LIR_Op* cur_last_op = cur_instructions->last(); 6339 6340 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6341 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { 6342 // the block contains only a label and a return 6343 // if a predecessor ends with an unconditional jump to this block, then the jump 6344 // can be replaced with a return instruction 6345 // 6346 // Note: the original block with only a return statement cannot be deleted completely 6347 // because the predecessors might have other (conditional) jumps to this block 6348 // -> this may lead to unnecesary return instructions in the final code 6349 6350 assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); 6351 assert(block->number_of_sux() == 0 || 6352 (return_converted.at(block->block_id()) && block->number_of_sux() == 1), 6353 "blocks that end with return must not have successors"); 6354 6355 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); 6356 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); 6357 6358 for (int j = block->number_of_preds() - 1; j >= 0; j--) { 6359 BlockBegin* pred = block->pred_at(j); 6360 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 6361 LIR_Op* pred_last_op = pred_instructions->last(); 6362 6363 if (pred_last_op->code() == lir_branch) { 6364 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 6365 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; 6366 6367 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { 6368 // replace the jump to a return with a direct return 6369 // Note: currently the edge between the blocks is not deleted 6370 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); 6371 #ifdef ASSERT 6372 return_converted.set_bit(pred->block_id()); 6373 #endif 6374 } 6375 } 6376 } 6377 } 6378 } 6379 } 6380 6381 6382 #ifdef ASSERT 6383 void ControlFlowOptimizer::verify(BlockList* code) { 6384 for (int i = 0; i < code->length(); i++) { 6385 BlockBegin* block = code->at(i); 6386 LIR_OpList* instructions = block->lir()->instructions_list(); 6387 6388 int j; 6389 for (j = 0; j < instructions->length(); j++) { 6390 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); 6391 6392 if (op_branch != NULL) { 6393 assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid"); 6394 assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid"); 6395 } 6396 } 6397 6398 for (j = 0; j < block->number_of_sux() - 1; j++) { 6399 BlockBegin* sux = block->sux_at(j); 6400 assert(code->find(sux) != -1, "successor not valid"); 6401 } 6402 6403 for (j = 0; j < block->number_of_preds() - 1; j++) { 6404 BlockBegin* pred = block->pred_at(j); 6405 assert(code->find(pred) != -1, "successor not valid"); 6406 } 6407 } 6408 } 6409 #endif 6410 6411 6412 #ifndef PRODUCT 6413 6414 // Implementation of LinearStatistic 6415 6416 const char* LinearScanStatistic::counter_name(int counter_idx) { 6417 switch (counter_idx) { 6418 case counter_method: return "compiled methods"; 6419 case counter_fpu_method: return "methods using fpu"; 6420 case counter_loop_method: return "methods with loops"; 6421 case counter_exception_method:return "methods with xhandler"; 6422 6423 case counter_loop: return "loops"; 6424 case counter_block: return "blocks"; 6425 case counter_loop_block: return "blocks inside loop"; 6426 case counter_exception_block: return "exception handler entries"; 6427 case counter_interval: return "intervals"; 6428 case counter_fixed_interval: return "fixed intervals"; 6429 case counter_range: return "ranges"; 6430 case counter_fixed_range: return "fixed ranges"; 6431 case counter_use_pos: return "use positions"; 6432 case counter_fixed_use_pos: return "fixed use positions"; 6433 case counter_spill_slots: return "spill slots"; 6434 6435 // counter for classes of lir instructions 6436 case counter_instruction: return "total instructions"; 6437 case counter_label: return "labels"; 6438 case counter_entry: return "method entries"; 6439 case counter_return: return "method returns"; 6440 case counter_call: return "method calls"; 6441 case counter_move: return "moves"; 6442 case counter_cmp: return "compare"; 6443 case counter_cond_branch: return "conditional branches"; 6444 case counter_uncond_branch: return "unconditional branches"; 6445 case counter_stub_branch: return "branches to stub"; 6446 case counter_alu: return "artithmetic + logic"; 6447 case counter_alloc: return "allocations"; 6448 case counter_sync: return "synchronisation"; 6449 case counter_throw: return "throw"; 6450 case counter_unwind: return "unwind"; 6451 case counter_typecheck: return "type+null-checks"; 6452 case counter_fpu_stack: return "fpu-stack"; 6453 case counter_misc_inst: return "other instructions"; 6454 case counter_other_inst: return "misc. instructions"; 6455 6456 // counter for different types of moves 6457 case counter_move_total: return "total moves"; 6458 case counter_move_reg_reg: return "register->register"; 6459 case counter_move_reg_stack: return "register->stack"; 6460 case counter_move_stack_reg: return "stack->register"; 6461 case counter_move_stack_stack:return "stack->stack"; 6462 case counter_move_reg_mem: return "register->memory"; 6463 case counter_move_mem_reg: return "memory->register"; 6464 case counter_move_const_any: return "constant->any"; 6465 6466 case blank_line_1: return ""; 6467 case blank_line_2: return ""; 6468 6469 default: ShouldNotReachHere(); return ""; 6470 } 6471 } 6472 6473 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { 6474 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { 6475 return counter_method; 6476 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { 6477 return counter_block; 6478 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { 6479 return counter_instruction; 6480 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { 6481 return counter_move_total; 6482 } 6483 return invalid_counter; 6484 } 6485 6486 LinearScanStatistic::LinearScanStatistic() { 6487 for (int i = 0; i < number_of_counters; i++) { 6488 _counters_sum[i] = 0; 6489 _counters_max[i] = -1; 6490 } 6491 6492 } 6493 6494 // add the method-local numbers to the total sum 6495 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { 6496 for (int i = 0; i < number_of_counters; i++) { 6497 _counters_sum[i] += method_statistic._counters_sum[i]; 6498 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); 6499 } 6500 } 6501 6502 void LinearScanStatistic::print(const char* title) { 6503 if (CountLinearScan || TraceLinearScanLevel > 0) { 6504 tty->cr(); 6505 tty->print_cr("***** LinearScan statistic - %s *****", title); 6506 6507 for (int i = 0; i < number_of_counters; i++) { 6508 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { 6509 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); 6510 6511 LinearScanStatistic::Counter cntr = base_counter(i); 6512 if (cntr != invalid_counter) { 6513 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]); 6514 } else { 6515 tty->print(" "); 6516 } 6517 6518 if (_counters_max[i] >= 0) { 6519 tty->print("%8d", _counters_max[i]); 6520 } 6521 } 6522 tty->cr(); 6523 } 6524 } 6525 } 6526 6527 void LinearScanStatistic::collect(LinearScan* allocator) { 6528 inc_counter(counter_method); 6529 if (allocator->has_fpu_registers()) { 6530 inc_counter(counter_fpu_method); 6531 } 6532 if (allocator->num_loops() > 0) { 6533 inc_counter(counter_loop_method); 6534 } 6535 inc_counter(counter_loop, allocator->num_loops()); 6536 inc_counter(counter_spill_slots, allocator->max_spills()); 6537 6538 int i; 6539 for (i = 0; i < allocator->interval_count(); i++) { 6540 Interval* cur = allocator->interval_at(i); 6541 6542 if (cur != NULL) { 6543 inc_counter(counter_interval); 6544 inc_counter(counter_use_pos, cur->num_use_positions()); 6545 if (LinearScan::is_precolored_interval(cur)) { 6546 inc_counter(counter_fixed_interval); 6547 inc_counter(counter_fixed_use_pos, cur->num_use_positions()); 6548 } 6549 6550 Range* range = cur->first(); 6551 while (range != Range::end()) { 6552 inc_counter(counter_range); 6553 if (LinearScan::is_precolored_interval(cur)) { 6554 inc_counter(counter_fixed_range); 6555 } 6556 range = range->next(); 6557 } 6558 } 6559 } 6560 6561 bool has_xhandlers = false; 6562 // Note: only count blocks that are in code-emit order 6563 for (i = 0; i < allocator->ir()->code()->length(); i++) { 6564 BlockBegin* cur = allocator->ir()->code()->at(i); 6565 6566 inc_counter(counter_block); 6567 if (cur->loop_depth() > 0) { 6568 inc_counter(counter_loop_block); 6569 } 6570 if (cur->is_set(BlockBegin::exception_entry_flag)) { 6571 inc_counter(counter_exception_block); 6572 has_xhandlers = true; 6573 } 6574 6575 LIR_OpList* instructions = cur->lir()->instructions_list(); 6576 for (int j = 0; j < instructions->length(); j++) { 6577 LIR_Op* op = instructions->at(j); 6578 6579 inc_counter(counter_instruction); 6580 6581 switch (op->code()) { 6582 case lir_label: inc_counter(counter_label); break; 6583 case lir_std_entry: 6584 case lir_osr_entry: inc_counter(counter_entry); break; 6585 case lir_return: inc_counter(counter_return); break; 6586 6587 case lir_rtcall: 6588 case lir_static_call: 6589 case lir_optvirtual_call: 6590 case lir_virtual_call: inc_counter(counter_call); break; 6591 6592 case lir_move: { 6593 inc_counter(counter_move); 6594 inc_counter(counter_move_total); 6595 6596 LIR_Opr in = op->as_Op1()->in_opr(); 6597 LIR_Opr res = op->as_Op1()->result_opr(); 6598 if (in->is_register()) { 6599 if (res->is_register()) { 6600 inc_counter(counter_move_reg_reg); 6601 } else if (res->is_stack()) { 6602 inc_counter(counter_move_reg_stack); 6603 } else if (res->is_address()) { 6604 inc_counter(counter_move_reg_mem); 6605 } else { 6606 ShouldNotReachHere(); 6607 } 6608 } else if (in->is_stack()) { 6609 if (res->is_register()) { 6610 inc_counter(counter_move_stack_reg); 6611 } else { 6612 inc_counter(counter_move_stack_stack); 6613 } 6614 } else if (in->is_address()) { 6615 assert(res->is_register(), "must be"); 6616 inc_counter(counter_move_mem_reg); 6617 } else if (in->is_constant()) { 6618 inc_counter(counter_move_const_any); 6619 } else { 6620 ShouldNotReachHere(); 6621 } 6622 break; 6623 } 6624 6625 case lir_cmp: inc_counter(counter_cmp); break; 6626 6627 case lir_branch: 6628 case lir_cond_float_branch: { 6629 LIR_OpBranch* branch = op->as_OpBranch(); 6630 if (branch->block() == NULL) { 6631 inc_counter(counter_stub_branch); 6632 } else if (branch->cond() == lir_cond_always) { 6633 inc_counter(counter_uncond_branch); 6634 } else { 6635 inc_counter(counter_cond_branch); 6636 } 6637 break; 6638 } 6639 6640 case lir_neg: 6641 case lir_add: 6642 case lir_sub: 6643 case lir_mul: 6644 case lir_mul_strictfp: 6645 case lir_div: 6646 case lir_div_strictfp: 6647 case lir_rem: 6648 case lir_sqrt: 6649 case lir_abs: 6650 case lir_log10: 6651 case lir_logic_and: 6652 case lir_logic_or: 6653 case lir_logic_xor: 6654 case lir_shl: 6655 case lir_shr: 6656 case lir_ushr: inc_counter(counter_alu); break; 6657 6658 case lir_alloc_object: 6659 case lir_alloc_array: inc_counter(counter_alloc); break; 6660 6661 case lir_monaddr: 6662 case lir_lock: 6663 case lir_unlock: inc_counter(counter_sync); break; 6664 6665 case lir_throw: inc_counter(counter_throw); break; 6666 6667 case lir_unwind: inc_counter(counter_unwind); break; 6668 6669 case lir_null_check: 6670 case lir_leal: 6671 case lir_instanceof: 6672 case lir_checkcast: 6673 case lir_store_check: inc_counter(counter_typecheck); break; 6674 6675 case lir_fpop_raw: 6676 case lir_fxch: 6677 case lir_fld: inc_counter(counter_fpu_stack); break; 6678 6679 case lir_nop: 6680 case lir_push: 6681 case lir_pop: 6682 case lir_convert: 6683 case lir_roundfp: 6684 case lir_cmove: inc_counter(counter_misc_inst); break; 6685 6686 default: inc_counter(counter_other_inst); break; 6687 } 6688 } 6689 } 6690 6691 if (has_xhandlers) { 6692 inc_counter(counter_exception_method); 6693 } 6694 } 6695 6696 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { 6697 if (CountLinearScan || TraceLinearScanLevel > 0) { 6698 6699 LinearScanStatistic local_statistic = LinearScanStatistic(); 6700 6701 local_statistic.collect(allocator); 6702 global_statistic.sum_up(local_statistic); 6703 6704 if (TraceLinearScanLevel > 2) { 6705 local_statistic.print("current local statistic"); 6706 } 6707 } 6708 } 6709 6710 6711 // Implementation of LinearTimers 6712 6713 LinearScanTimers::LinearScanTimers() { 6714 for (int i = 0; i < number_of_timers; i++) { 6715 timer(i)->reset(); 6716 } 6717 } 6718 6719 const char* LinearScanTimers::timer_name(int idx) { 6720 switch (idx) { 6721 case timer_do_nothing: return "Nothing (Time Check)"; 6722 case timer_number_instructions: return "Number Instructions"; 6723 case timer_compute_local_live_sets: return "Local Live Sets"; 6724 case timer_compute_global_live_sets: return "Global Live Sets"; 6725 case timer_build_intervals: return "Build Intervals"; 6726 case timer_sort_intervals_before: return "Sort Intervals Before"; 6727 case timer_allocate_registers: return "Allocate Registers"; 6728 case timer_resolve_data_flow: return "Resolve Data Flow"; 6729 case timer_sort_intervals_after: return "Sort Intervals After"; 6730 case timer_eliminate_spill_moves: return "Spill optimization"; 6731 case timer_assign_reg_num: return "Assign Reg Num"; 6732 case timer_allocate_fpu_stack: return "Allocate FPU Stack"; 6733 case timer_optimize_lir: return "Optimize LIR"; 6734 default: ShouldNotReachHere(); return ""; 6735 } 6736 } 6737 6738 void LinearScanTimers::begin_method() { 6739 if (TimeEachLinearScan) { 6740 // reset all timers to measure only current method 6741 for (int i = 0; i < number_of_timers; i++) { 6742 timer(i)->reset(); 6743 } 6744 } 6745 } 6746 6747 void LinearScanTimers::end_method(LinearScan* allocator) { 6748 if (TimeEachLinearScan) { 6749 6750 double c = timer(timer_do_nothing)->seconds(); 6751 double total = 0; 6752 for (int i = 1; i < number_of_timers; i++) { 6753 total += timer(i)->seconds() - c; 6754 } 6755 6756 if (total >= 0.0005) { 6757 // print all information in one line for automatic processing 6758 tty->print("@"); allocator->compilation()->method()->print_name(); 6759 6760 tty->print("@ %d ", allocator->compilation()->method()->code_size()); 6761 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); 6762 tty->print("@ %d ", allocator->block_count()); 6763 tty->print("@ %d ", allocator->num_virtual_regs()); 6764 tty->print("@ %d ", allocator->interval_count()); 6765 tty->print("@ %d ", allocator->_num_calls); 6766 tty->print("@ %d ", allocator->num_loops()); 6767 6768 tty->print("@ %6.6f ", total); 6769 for (int i = 1; i < number_of_timers; i++) { 6770 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); 6771 } 6772 tty->cr(); 6773 } 6774 } 6775 } 6776 6777 void LinearScanTimers::print(double total_time) { 6778 if (TimeLinearScan) { 6779 // correction value: sum of dummy-timer that only measures the time that 6780 // is necesary to start and stop itself 6781 double c = timer(timer_do_nothing)->seconds(); 6782 6783 for (int i = 0; i < number_of_timers; i++) { 6784 double t = timer(i)->seconds(); 6785 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); 6786 } 6787 } 6788 } 6789 6790 #endif // #ifndef PRODUCT