1 /*
2 * Copyright (c) 2005, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
1087 // optimizations for second input operand of arithmehtic operations on Intel
1088 // this operand is allowed to be on the stack in some cases
1089 BasicType opr_type = opr->type_register();
1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) {
1092 // SSE float instruction (T_DOUBLE only supported with SSE2)
1093 switch (op->code()) {
1094 case lir_cmp:
1095 case lir_add:
1096 case lir_sub:
1097 case lir_mul:
1098 case lir_div:
1099 {
1100 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101 LIR_Op2* op2 = (LIR_Op2*)op;
1102 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104 return shouldHaveRegister;
1105 }
1106 }
1107 }
1108 } else {
1109 // FPU stack float instruction
1110 switch (op->code()) {
1111 case lir_add:
1112 case lir_sub:
1113 case lir_mul:
1114 case lir_div:
1115 {
1116 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1117 LIR_Op2* op2 = (LIR_Op2*)op;
1118 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1119 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1120 return shouldHaveRegister;
1121 }
1122 }
1123 }
1124 }
1125 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1126 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1127 // T_OBJECT doesn't get spilled along with T_LONG.
1128 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1129 // integer instruction (note: long operands must always be in register)
1130 switch (op->code()) {
1131 case lir_cmp:
1132 case lir_add:
1133 case lir_sub:
1134 case lir_logic_and:
1135 case lir_logic_or:
1136 case lir_logic_xor:
1137 {
1138 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1139 LIR_Op2* op2 = (LIR_Op2*)op;
1140 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1141 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1142 return shouldHaveRegister;
1143 }
1144 }
1145 }
1146 }
1147 #endif // X86 S390
1148
1149 // all other operands require a register
1150 return mustHaveRegister;
1151 }
1152
1153
1154 void LinearScan::handle_method_arguments(LIR_Op* op) {
1155 // special handling for method arguments (moves from stack to virtual register):
1156 // the interval gets no register assigned, but the stack slot.
1157 // it is split before the first use by the register allocator.
1158
1159 if (op->code() == lir_move) {
1160 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1161 LIR_Op1* move = (LIR_Op1*)op;
1162
1163 if (move->in_opr()->is_stack()) {
1164 #ifdef ASSERT
1230 }
1231 break;
1232 }
1233 case lir_cmove: {
1234 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1235 LIR_Op2* cmove = (LIR_Op2*)op;
1236
1237 LIR_Opr move_from = cmove->in_opr1();
1238 LIR_Opr move_to = cmove->result_opr();
1239
1240 if (move_to->is_register() && move_from->is_register()) {
1241 Interval* from = interval_at(reg_num(move_from));
1242 Interval* to = interval_at(reg_num(move_to));
1243 if (from != NULL && to != NULL) {
1244 to->set_register_hint(from);
1245 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1246 }
1247 }
1248 break;
1249 }
1250 }
1251 }
1252
1253
1254 void LinearScan::build_intervals() {
1255 TIME_LINEAR_SCAN(timer_build_intervals);
1256
1257 // initialize interval list with expected number of intervals
1258 // (32 is added to have some space for split children without having to resize the list)
1259 _intervals = IntervalList(num_virtual_regs() + 32);
1260 // initialize all slots that are used by build_intervals
1261 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1262
1263 // create a list with all caller-save registers (cpu, fpu, xmm)
1264 // when an instruction is a call, a temp range is created for all these registers
1265 int num_caller_save_registers = 0;
1266 int caller_save_registers[LinearScan::nof_regs];
1267
1268 int i;
1269 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
3010 // -> debug information is created inside the fpu stack allocator
3011 int n = visitor.info_count();
3012 for (int k = 0; k < n; k++) {
3013 compute_debug_info(visitor.info_at(k), op_id);
3014 }
3015 }
3016 }
3017
3018 #ifdef ASSERT
3019 // make sure we haven't made the op invalid.
3020 op->verify();
3021 #endif
3022
3023 // remove useless moves
3024 if (op->code() == lir_move) {
3025 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3026 LIR_Op1* move = (LIR_Op1*)op;
3027 LIR_Opr src = move->in_opr();
3028 LIR_Opr dst = move->result_opr();
3029 if (dst == src ||
3030 !dst->is_pointer() && !src->is_pointer() &&
3031 src->is_same_register(dst)) {
3032 instructions->at_put(j, NULL);
3033 has_dead = true;
3034 }
3035 }
3036 }
3037
3038 if (has_dead) {
3039 // iterate all instructions of the block and remove all null-values.
3040 int insert_point = 0;
3041 for (int j = 0; j < num_inst; j++) {
3042 LIR_Op* op = instructions->at(j);
3043 if (op != NULL) {
3044 if (insert_point != j) {
3045 instructions->at_put(insert_point, op);
3046 }
3047 insert_point++;
3048 }
3049 }
3050 instructions->trunc_to(insert_point);
3051 }
|
1 /*
2 * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
1087 // optimizations for second input operand of arithmehtic operations on Intel
1088 // this operand is allowed to be on the stack in some cases
1089 BasicType opr_type = opr->type_register();
1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) {
1092 // SSE float instruction (T_DOUBLE only supported with SSE2)
1093 switch (op->code()) {
1094 case lir_cmp:
1095 case lir_add:
1096 case lir_sub:
1097 case lir_mul:
1098 case lir_div:
1099 {
1100 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101 LIR_Op2* op2 = (LIR_Op2*)op;
1102 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104 return shouldHaveRegister;
1105 }
1106 }
1107 default:
1108 break;
1109 }
1110 } else {
1111 // FPU stack float instruction
1112 switch (op->code()) {
1113 case lir_add:
1114 case lir_sub:
1115 case lir_mul:
1116 case lir_div:
1117 {
1118 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1119 LIR_Op2* op2 = (LIR_Op2*)op;
1120 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1121 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1122 return shouldHaveRegister;
1123 }
1124 }
1125 default:
1126 break;
1127 }
1128 }
1129 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1130 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1131 // T_OBJECT doesn't get spilled along with T_LONG.
1132 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1133 // integer instruction (note: long operands must always be in register)
1134 switch (op->code()) {
1135 case lir_cmp:
1136 case lir_add:
1137 case lir_sub:
1138 case lir_logic_and:
1139 case lir_logic_or:
1140 case lir_logic_xor:
1141 {
1142 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1143 LIR_Op2* op2 = (LIR_Op2*)op;
1144 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1145 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1146 return shouldHaveRegister;
1147 }
1148 }
1149 default:
1150 break;
1151 }
1152 }
1153 #endif // X86 S390
1154
1155 // all other operands require a register
1156 return mustHaveRegister;
1157 }
1158
1159
1160 void LinearScan::handle_method_arguments(LIR_Op* op) {
1161 // special handling for method arguments (moves from stack to virtual register):
1162 // the interval gets no register assigned, but the stack slot.
1163 // it is split before the first use by the register allocator.
1164
1165 if (op->code() == lir_move) {
1166 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1167 LIR_Op1* move = (LIR_Op1*)op;
1168
1169 if (move->in_opr()->is_stack()) {
1170 #ifdef ASSERT
1236 }
1237 break;
1238 }
1239 case lir_cmove: {
1240 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1241 LIR_Op2* cmove = (LIR_Op2*)op;
1242
1243 LIR_Opr move_from = cmove->in_opr1();
1244 LIR_Opr move_to = cmove->result_opr();
1245
1246 if (move_to->is_register() && move_from->is_register()) {
1247 Interval* from = interval_at(reg_num(move_from));
1248 Interval* to = interval_at(reg_num(move_to));
1249 if (from != NULL && to != NULL) {
1250 to->set_register_hint(from);
1251 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1252 }
1253 }
1254 break;
1255 }
1256 default:
1257 break;
1258 }
1259 }
1260
1261
1262 void LinearScan::build_intervals() {
1263 TIME_LINEAR_SCAN(timer_build_intervals);
1264
1265 // initialize interval list with expected number of intervals
1266 // (32 is added to have some space for split children without having to resize the list)
1267 _intervals = IntervalList(num_virtual_regs() + 32);
1268 // initialize all slots that are used by build_intervals
1269 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1270
1271 // create a list with all caller-save registers (cpu, fpu, xmm)
1272 // when an instruction is a call, a temp range is created for all these registers
1273 int num_caller_save_registers = 0;
1274 int caller_save_registers[LinearScan::nof_regs];
1275
1276 int i;
1277 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
3018 // -> debug information is created inside the fpu stack allocator
3019 int n = visitor.info_count();
3020 for (int k = 0; k < n; k++) {
3021 compute_debug_info(visitor.info_at(k), op_id);
3022 }
3023 }
3024 }
3025
3026 #ifdef ASSERT
3027 // make sure we haven't made the op invalid.
3028 op->verify();
3029 #endif
3030
3031 // remove useless moves
3032 if (op->code() == lir_move) {
3033 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3034 LIR_Op1* move = (LIR_Op1*)op;
3035 LIR_Opr src = move->in_opr();
3036 LIR_Opr dst = move->result_opr();
3037 if (dst == src ||
3038 (!dst->is_pointer() && !src->is_pointer() &&
3039 src->is_same_register(dst))) {
3040 instructions->at_put(j, NULL);
3041 has_dead = true;
3042 }
3043 }
3044 }
3045
3046 if (has_dead) {
3047 // iterate all instructions of the block and remove all null-values.
3048 int insert_point = 0;
3049 for (int j = 0; j < num_inst; j++) {
3050 LIR_Op* op = instructions->at(j);
3051 if (op != NULL) {
3052 if (insert_point != j) {
3053 instructions->at_put(insert_point, op);
3054 }
3055 insert_point++;
3056 }
3057 }
3058 instructions->trunc_to(insert_point);
3059 }
|