1 /* 2 * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "vmreg_x86.inline.hpp" 42 43 44 // These masks are used to provide 128-bit aligned bitmasks to the XMM 45 // instructions, to allow sign-masking or sign-bit flipping. They allow 46 // fast versions of NegF/NegD and AbsF/AbsD. 47 48 // Note: 'double' and 'long long' have 32-bits alignment on x86. 49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 51 // of 128-bits operands for SSE instructions. 52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 53 // Store the value to a 128-bits operand. 54 operand[0] = lo; 55 operand[1] = hi; 56 return operand; 57 } 58 59 // Buffer for 128-bits masks used by SSE instructions. 60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 61 62 // Static initialization during VM startup. 63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 67 68 69 70 NEEDS_CLEANUP // remove this definitions ? 71 const Register IC_Klass = rax; // where the IC klass is cached 72 const Register SYNC_header = rax; // synchronization header 73 const Register SHIFT_count = rcx; // where count for shift operations must be 74 75 #define __ _masm-> 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2) { 82 if (tmp1 == preserve) { 83 assert_different_registers(tmp1, tmp2, extra); 84 tmp1 = extra; 85 } else if (tmp2 == preserve) { 86 assert_different_registers(tmp1, tmp2, extra); 87 tmp2 = extra; 88 } 89 assert_different_registers(preserve, tmp1, tmp2); 90 } 91 92 93 94 static void select_different_registers(Register preserve, 95 Register extra, 96 Register &tmp1, 97 Register &tmp2, 98 Register &tmp3) { 99 if (tmp1 == preserve) { 100 assert_different_registers(tmp1, tmp2, tmp3, extra); 101 tmp1 = extra; 102 } else if (tmp2 == preserve) { 103 assert_different_registers(tmp1, tmp2, tmp3, extra); 104 tmp2 = extra; 105 } else if (tmp3 == preserve) { 106 assert_different_registers(tmp1, tmp2, tmp3, extra); 107 tmp3 = extra; 108 } 109 assert_different_registers(preserve, tmp1, tmp2, tmp3); 110 } 111 112 113 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 115 if (opr->is_constant()) { 116 LIR_Const* constant = opr->as_constant_ptr(); 117 switch (constant->type()) { 118 case T_INT: { 119 return true; 120 } 121 122 default: 123 return false; 124 } 125 } 126 return false; 127 } 128 129 130 LIR_Opr LIR_Assembler::receiverOpr() { 131 return FrameMap::receiver_opr; 132 } 133 134 LIR_Opr LIR_Assembler::osrBufferPointer() { 135 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 136 } 137 138 //--------------fpu register translations----------------------- 139 140 141 address LIR_Assembler::float_constant(float f) { 142 address const_addr = __ float_constant(f); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 address LIR_Assembler::double_constant(double d) { 153 address const_addr = __ double_constant(d); 154 if (const_addr == NULL) { 155 bailout("const section overflow"); 156 return __ code()->consts()->start(); 157 } else { 158 return const_addr; 159 } 160 } 161 162 163 void LIR_Assembler::set_24bit_FPU() { 164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 165 } 166 167 void LIR_Assembler::reset_FPU() { 168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 169 } 170 171 void LIR_Assembler::fpop() { 172 __ fpop(); 173 } 174 175 void LIR_Assembler::fxch(int i) { 176 __ fxch(i); 177 } 178 179 void LIR_Assembler::fld(int i) { 180 __ fld_s(i); 181 } 182 183 void LIR_Assembler::ffree(int i) { 184 __ ffree(i); 185 } 186 187 void LIR_Assembler::breakpoint() { 188 __ int3(); 189 } 190 191 void LIR_Assembler::push(LIR_Opr opr) { 192 if (opr->is_single_cpu()) { 193 __ push_reg(opr->as_register()); 194 } else if (opr->is_double_cpu()) { 195 NOT_LP64(__ push_reg(opr->as_register_hi())); 196 __ push_reg(opr->as_register_lo()); 197 } else if (opr->is_stack()) { 198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 199 } else if (opr->is_constant()) { 200 LIR_Const* const_opr = opr->as_constant_ptr(); 201 if (const_opr->type() == T_OBJECT) { 202 __ push_oop(const_opr->as_jobject()); 203 } else if (const_opr->type() == T_INT) { 204 __ push_jint(const_opr->as_jint()); 205 } else { 206 ShouldNotReachHere(); 207 } 208 209 } else { 210 ShouldNotReachHere(); 211 } 212 } 213 214 void LIR_Assembler::pop(LIR_Opr opr) { 215 if (opr->is_single_cpu()) { 216 __ pop_reg(opr->as_register()); 217 } else { 218 ShouldNotReachHere(); 219 } 220 } 221 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 223 return addr->base()->is_illegal() && addr->index()->is_illegal(); 224 } 225 226 //------------------------------------------- 227 228 Address LIR_Assembler::as_Address(LIR_Address* addr) { 229 return as_Address(addr, rscratch1); 230 } 231 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 233 if (addr->base()->is_illegal()) { 234 assert(addr->index()->is_illegal(), "must be illegal too"); 235 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 236 if (! __ reachable(laddr)) { 237 __ movptr(tmp, laddr.addr()); 238 Address res(tmp, 0); 239 return res; 240 } else { 241 return __ as_Address(laddr); 242 } 243 } 244 245 Register base = addr->base()->as_pointer_register(); 246 247 if (addr->index()->is_illegal()) { 248 return Address( base, addr->disp()); 249 } else if (addr->index()->is_cpu_register()) { 250 Register index = addr->index()->as_pointer_register(); 251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 252 } else if (addr->index()->is_constant()) { 253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 254 assert(Assembler::is_simm32(addr_offset), "must be"); 255 256 return Address(base, addr_offset); 257 } else { 258 Unimplemented(); 259 return Address(); 260 } 261 } 262 263 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 265 Address base = as_Address(addr); 266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 267 } 268 269 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 271 return as_Address(addr); 272 } 273 274 275 void LIR_Assembler::osr_entry() { 276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 277 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 278 ValueStack* entry_state = osr_entry->state(); 279 int number_of_locks = entry_state->locks_size(); 280 281 // we jump here if osr happens with the interpreter 282 // state set up to continue at the beginning of the 283 // loop that triggered osr - in particular, we have 284 // the following registers setup: 285 // 286 // rcx: osr buffer 287 // 288 289 // build frame 290 ciMethod* m = compilation()->method(); 291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 292 293 // OSR buffer is 294 // 295 // locals[nlocals-1..0] 296 // monitors[0..number_of_locks] 297 // 298 // locals is a direct copy of the interpreter frame so in the osr buffer 299 // so first slot in the local array is the last local from the interpreter 300 // and last slot is local[0] (receiver) from the interpreter 301 // 302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 304 // in the interpreter frame (the method lock if a sync method) 305 306 // Initialize monitors in the compiled activation. 307 // rcx: pointer to osr buffer 308 // 309 // All other registers are dead at this point and the locals will be 310 // copied into place by code emitted in the IR. 311 312 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 314 int monitor_offset = BytesPerWord * method()->max_locals() + 315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 317 // the OSR buffer using 2 word entries: first the lock and then 318 // the oop. 319 for (int i = 0; i < number_of_locks; i++) { 320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 321 #ifdef ASSERT 322 // verify the interpreter's monitor has a non-null object 323 { 324 Label L; 325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 326 __ jcc(Assembler::notZero, L); 327 __ stop("locked object is NULL"); 328 __ bind(L); 329 } 330 #endif 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 334 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 335 } 336 } 337 } 338 339 340 // inline cache check; done before the frame is built. 341 int LIR_Assembler::check_icache() { 342 Register receiver = FrameMap::receiver_opr->as_register(); 343 Register ic_klass = IC_Klass; 344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 346 if (!do_post_padding) { 347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 349 } 350 int offset = __ offset(); 351 __ inline_cache_check(receiver, IC_Klass); 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353 if (do_post_padding) { 354 // force alignment after the cache check. 355 // It's been verified to be aligned if !VerifyOops 356 __ align(CodeEntryAlignment); 357 } 358 return offset; 359 } 360 361 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363 jobject o = NULL; 364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 365 __ movoop(reg, o); 366 patching_epilog(patch, lir_patch_normal, reg, info); 367 } 368 369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 370 Metadata* o = NULL; 371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 372 __ mov_metadata(reg, o); 373 patching_epilog(patch, lir_patch_normal, reg, info); 374 } 375 376 // This specifies the rsp decrement needed to build the frame 377 int LIR_Assembler::initial_frame_size_in_bytes() const { 378 // if rounding, must let FrameMap know! 379 380 // The frame_map records size in slots (32bit word) 381 382 // subtract two words to account for return address and link 383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 384 } 385 386 387 int LIR_Assembler::emit_exception_handler() { 388 // if the last instruction is a call (typically to do a throw which 389 // is coming at the end after block reordering) the return address 390 // must still point into the code area in order to avoid assertion 391 // failures when searching for the corresponding bci => add a nop 392 // (was bug 5/14/1999 - gri) 393 __ nop(); 394 395 // generate code for exception handler 396 address handler_base = __ start_a_stub(exception_handler_size()); 397 if (handler_base == NULL) { 398 // not enough space left for the handler 399 bailout("exception handler overflow"); 400 return -1; 401 } 402 403 int offset = code_offset(); 404 405 // the exception oop and pc are in rax, and rdx 406 // no other registers need to be preserved, so invalidate them 407 __ invalidate_registers(false, true, true, false, true, true); 408 409 // check that there is really an exception 410 __ verify_not_null_oop(rax); 411 412 // search an exception handler (rax: exception oop, rdx: throwing pc) 413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 414 __ should_not_reach_here(); 415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 416 __ end_a_stub(); 417 418 return offset; 419 } 420 421 422 // Emit the code to remove the frame from the stack in the exception 423 // unwind path. 424 int LIR_Assembler::emit_unwind_handler() { 425 #ifndef PRODUCT 426 if (CommentedAssembly) { 427 _masm->block_comment("Unwind handler"); 428 } 429 #endif 430 431 int offset = code_offset(); 432 433 // Fetch the exception from TLS and clear out exception related thread state 434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 435 NOT_LP64(__ get_thread(rsi)); 436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 439 440 __ bind(_unwind_handler_entry); 441 __ verify_not_null_oop(rax); 442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 444 } 445 446 // Preform needed unlocking 447 MonitorExitStub* stub = NULL; 448 if (method()->is_synchronized()) { 449 monitor_address(0, FrameMap::rax_opr); 450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 451 __ unlock_object(rdi, rsi, rax, *stub->entry()); 452 __ bind(*stub->continuation()); 453 } 454 455 if (compilation()->env()->dtrace_method_probes()) { 456 #ifdef _LP64 457 __ mov(rdi, r15_thread); 458 __ mov_metadata(rsi, method()->constant_encoding()); 459 #else 460 __ get_thread(rax); 461 __ movptr(Address(rsp, 0), rax); 462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 463 #endif 464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 465 } 466 467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 468 __ mov(rax, rbx); // Restore the exception 469 } 470 471 // remove the activation and dispatch to the unwind handler 472 __ remove_frame(initial_frame_size_in_bytes()); 473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 474 475 // Emit the slow path assembly 476 if (stub != NULL) { 477 stub->emit_code(this); 478 } 479 480 return offset; 481 } 482 483 484 int LIR_Assembler::emit_deopt_handler() { 485 // if the last instruction is a call (typically to do a throw which 486 // is coming at the end after block reordering) the return address 487 // must still point into the code area in order to avoid assertion 488 // failures when searching for the corresponding bci => add a nop 489 // (was bug 5/14/1999 - gri) 490 __ nop(); 491 492 // generate code for exception handler 493 address handler_base = __ start_a_stub(deopt_handler_size()); 494 if (handler_base == NULL) { 495 // not enough space left for the handler 496 bailout("deopt handler overflow"); 497 return -1; 498 } 499 500 int offset = code_offset(); 501 InternalAddress here(__ pc()); 502 503 __ pushptr(here.addr()); 504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 506 __ end_a_stub(); 507 508 return offset; 509 } 510 511 512 void LIR_Assembler::return_op(LIR_Opr result) { 513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 515 assert(result->fpu() == 0, "result must already be on TOS"); 516 } 517 518 // Pop the stack before the safepoint code 519 __ remove_frame(initial_frame_size_in_bytes()); 520 521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 522 __ reserved_stack_check(); 523 } 524 525 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 530 531 if (Assembler::is_polling_page_far()) { 532 __ lea(rscratch1, polling_page); 533 __ relocate(relocInfo::poll_return_type); 534 __ testl(rax, Address(rscratch1, 0)); 535 } else { 536 __ testl(rax, polling_page); 537 } 538 __ ret(0); 539 } 540 541 542 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 544 guarantee(info != NULL, "Shouldn't be NULL"); 545 int offset = __ offset(); 546 if (Assembler::is_polling_page_far()) { 547 __ lea(rscratch1, polling_page); 548 offset = __ offset(); 549 add_debug_info_for_branch(info); 550 __ relocate(relocInfo::poll_type); 551 __ testl(rax, Address(rscratch1, 0)); 552 } else { 553 add_debug_info_for_branch(info); 554 __ testl(rax, polling_page); 555 } 556 return offset; 557 } 558 559 560 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 561 if (from_reg != to_reg) __ mov(to_reg, from_reg); 562 } 563 564 void LIR_Assembler::swap_reg(Register a, Register b) { 565 __ xchgptr(a, b); 566 } 567 568 569 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 570 assert(src->is_constant(), "should not call otherwise"); 571 assert(dest->is_register(), "should not call otherwise"); 572 LIR_Const* c = src->as_constant_ptr(); 573 574 switch (c->type()) { 575 case T_INT: { 576 assert(patch_code == lir_patch_none, "no patching handled here"); 577 __ movl(dest->as_register(), c->as_jint()); 578 break; 579 } 580 581 case T_ADDRESS: { 582 assert(patch_code == lir_patch_none, "no patching handled here"); 583 __ movptr(dest->as_register(), c->as_jint()); 584 break; 585 } 586 587 case T_LONG: { 588 assert(patch_code == lir_patch_none, "no patching handled here"); 589 #ifdef _LP64 590 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 591 #else 592 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 593 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 594 #endif // _LP64 595 break; 596 } 597 598 case T_OBJECT: { 599 if (patch_code != lir_patch_none) { 600 jobject2reg_with_patching(dest->as_register(), info); 601 } else { 602 __ movoop(dest->as_register(), c->as_jobject()); 603 } 604 break; 605 } 606 607 case T_METADATA: { 608 if (patch_code != lir_patch_none) { 609 klass2reg_with_patching(dest->as_register(), info); 610 } else { 611 __ mov_metadata(dest->as_register(), c->as_metadata()); 612 } 613 break; 614 } 615 616 case T_FLOAT: { 617 if (dest->is_single_xmm()) { 618 if (c->is_zero_float()) { 619 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 620 } else { 621 __ movflt(dest->as_xmm_float_reg(), 622 InternalAddress(float_constant(c->as_jfloat()))); 623 } 624 } else { 625 assert(dest->is_single_fpu(), "must be"); 626 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 627 if (c->is_zero_float()) { 628 __ fldz(); 629 } else if (c->is_one_float()) { 630 __ fld1(); 631 } else { 632 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 633 } 634 } 635 break; 636 } 637 638 case T_DOUBLE: { 639 if (dest->is_double_xmm()) { 640 if (c->is_zero_double()) { 641 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 642 } else { 643 __ movdbl(dest->as_xmm_double_reg(), 644 InternalAddress(double_constant(c->as_jdouble()))); 645 } 646 } else { 647 assert(dest->is_double_fpu(), "must be"); 648 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 649 if (c->is_zero_double()) { 650 __ fldz(); 651 } else if (c->is_one_double()) { 652 __ fld1(); 653 } else { 654 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 655 } 656 } 657 break; 658 } 659 660 default: 661 ShouldNotReachHere(); 662 } 663 } 664 665 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 666 assert(src->is_constant(), "should not call otherwise"); 667 assert(dest->is_stack(), "should not call otherwise"); 668 LIR_Const* c = src->as_constant_ptr(); 669 670 switch (c->type()) { 671 case T_INT: // fall through 672 case T_FLOAT: 673 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 674 break; 675 676 case T_ADDRESS: 677 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 678 break; 679 680 case T_OBJECT: 681 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 682 break; 683 684 case T_LONG: // fall through 685 case T_DOUBLE: 686 #ifdef _LP64 687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 688 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 689 #else 690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 691 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 692 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 693 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 694 #endif // _LP64 695 break; 696 697 default: 698 ShouldNotReachHere(); 699 } 700 } 701 702 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 703 assert(src->is_constant(), "should not call otherwise"); 704 assert(dest->is_address(), "should not call otherwise"); 705 LIR_Const* c = src->as_constant_ptr(); 706 LIR_Address* addr = dest->as_address_ptr(); 707 708 int null_check_here = code_offset(); 709 switch (type) { 710 case T_INT: // fall through 711 case T_FLOAT: 712 __ movl(as_Address(addr), c->as_jint_bits()); 713 break; 714 715 case T_ADDRESS: 716 __ movptr(as_Address(addr), c->as_jint_bits()); 717 break; 718 719 case T_OBJECT: // fall through 720 case T_ARRAY: 721 if (c->as_jobject() == NULL) { 722 if (UseCompressedOops && !wide) { 723 __ movl(as_Address(addr), (int32_t)NULL_WORD); 724 } else { 725 #ifdef _LP64 726 __ xorptr(rscratch1, rscratch1); 727 null_check_here = code_offset(); 728 __ movptr(as_Address(addr), rscratch1); 729 #else 730 __ movptr(as_Address(addr), NULL_WORD); 731 #endif 732 } 733 } else { 734 if (is_literal_address(addr)) { 735 ShouldNotReachHere(); 736 __ movoop(as_Address(addr, noreg), c->as_jobject()); 737 } else { 738 #ifdef _LP64 739 __ movoop(rscratch1, c->as_jobject()); 740 if (UseCompressedOops && !wide) { 741 __ encode_heap_oop(rscratch1); 742 null_check_here = code_offset(); 743 __ movl(as_Address_lo(addr), rscratch1); 744 } else { 745 null_check_here = code_offset(); 746 __ movptr(as_Address_lo(addr), rscratch1); 747 } 748 #else 749 __ movoop(as_Address(addr), c->as_jobject()); 750 #endif 751 } 752 } 753 break; 754 755 case T_LONG: // fall through 756 case T_DOUBLE: 757 #ifdef _LP64 758 if (is_literal_address(addr)) { 759 ShouldNotReachHere(); 760 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 761 } else { 762 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 763 null_check_here = code_offset(); 764 __ movptr(as_Address_lo(addr), r10); 765 } 766 #else 767 // Always reachable in 32bit so this doesn't produce useless move literal 768 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 769 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 770 #endif // _LP64 771 break; 772 773 case T_BOOLEAN: // fall through 774 case T_BYTE: 775 __ movb(as_Address(addr), c->as_jint() & 0xFF); 776 break; 777 778 case T_CHAR: // fall through 779 case T_SHORT: 780 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 781 break; 782 783 default: 784 ShouldNotReachHere(); 785 }; 786 787 if (info != NULL) { 788 add_debug_info_for_null_check(null_check_here, info); 789 } 790 } 791 792 793 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 794 assert(src->is_register(), "should not call otherwise"); 795 assert(dest->is_register(), "should not call otherwise"); 796 797 // move between cpu-registers 798 if (dest->is_single_cpu()) { 799 #ifdef _LP64 800 if (src->type() == T_LONG) { 801 // Can do LONG -> OBJECT 802 move_regs(src->as_register_lo(), dest->as_register()); 803 return; 804 } 805 #endif 806 assert(src->is_single_cpu(), "must match"); 807 if (src->type() == T_OBJECT) { 808 __ verify_oop(src->as_register()); 809 } 810 move_regs(src->as_register(), dest->as_register()); 811 812 } else if (dest->is_double_cpu()) { 813 #ifdef _LP64 814 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 815 // Surprising to me but we can see move of a long to t_object 816 __ verify_oop(src->as_register()); 817 move_regs(src->as_register(), dest->as_register_lo()); 818 return; 819 } 820 #endif 821 assert(src->is_double_cpu(), "must match"); 822 Register f_lo = src->as_register_lo(); 823 Register f_hi = src->as_register_hi(); 824 Register t_lo = dest->as_register_lo(); 825 Register t_hi = dest->as_register_hi(); 826 #ifdef _LP64 827 assert(f_hi == f_lo, "must be same"); 828 assert(t_hi == t_lo, "must be same"); 829 move_regs(f_lo, t_lo); 830 #else 831 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 832 833 834 if (f_lo == t_hi && f_hi == t_lo) { 835 swap_reg(f_lo, f_hi); 836 } else if (f_hi == t_lo) { 837 assert(f_lo != t_hi, "overwriting register"); 838 move_regs(f_hi, t_hi); 839 move_regs(f_lo, t_lo); 840 } else { 841 assert(f_hi != t_lo, "overwriting register"); 842 move_regs(f_lo, t_lo); 843 move_regs(f_hi, t_hi); 844 } 845 #endif // LP64 846 847 // special moves from fpu-register to xmm-register 848 // necessary for method results 849 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 850 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 851 __ fld_s(Address(rsp, 0)); 852 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 853 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 854 __ fld_d(Address(rsp, 0)); 855 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 856 __ fstp_s(Address(rsp, 0)); 857 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 858 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 859 __ fstp_d(Address(rsp, 0)); 860 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 861 862 // move between xmm-registers 863 } else if (dest->is_single_xmm()) { 864 assert(src->is_single_xmm(), "must match"); 865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 866 } else if (dest->is_double_xmm()) { 867 assert(src->is_double_xmm(), "must match"); 868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 869 870 // move between fpu-registers (no instruction necessary because of fpu-stack) 871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 874 } else { 875 ShouldNotReachHere(); 876 } 877 } 878 879 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 880 assert(src->is_register(), "should not call otherwise"); 881 assert(dest->is_stack(), "should not call otherwise"); 882 883 if (src->is_single_cpu()) { 884 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 885 if (type == T_OBJECT || type == T_ARRAY) { 886 __ verify_oop(src->as_register()); 887 __ movptr (dst, src->as_register()); 888 } else if (type == T_METADATA) { 889 __ movptr (dst, src->as_register()); 890 } else { 891 __ movl (dst, src->as_register()); 892 } 893 894 } else if (src->is_double_cpu()) { 895 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 896 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 897 __ movptr (dstLO, src->as_register_lo()); 898 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 899 900 } else if (src->is_single_xmm()) { 901 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 902 __ movflt(dst_addr, src->as_xmm_float_reg()); 903 904 } else if (src->is_double_xmm()) { 905 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 906 __ movdbl(dst_addr, src->as_xmm_double_reg()); 907 908 } else if (src->is_single_fpu()) { 909 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 910 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 911 if (pop_fpu_stack) __ fstp_s (dst_addr); 912 else __ fst_s (dst_addr); 913 914 } else if (src->is_double_fpu()) { 915 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 916 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 917 if (pop_fpu_stack) __ fstp_d (dst_addr); 918 else __ fst_d (dst_addr); 919 920 } else { 921 ShouldNotReachHere(); 922 } 923 } 924 925 926 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 927 LIR_Address* to_addr = dest->as_address_ptr(); 928 PatchingStub* patch = NULL; 929 Register compressed_src = rscratch1; 930 931 if (type == T_ARRAY || type == T_OBJECT) { 932 __ verify_oop(src->as_register()); 933 #ifdef _LP64 934 if (UseCompressedOops && !wide) { 935 __ movptr(compressed_src, src->as_register()); 936 __ encode_heap_oop(compressed_src); 937 if (patch_code != lir_patch_none) { 938 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 939 } 940 } 941 #endif 942 } 943 944 if (patch_code != lir_patch_none) { 945 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 946 Address toa = as_Address(to_addr); 947 assert(toa.disp() != 0, "must have"); 948 } 949 950 int null_check_here = code_offset(); 951 switch (type) { 952 case T_FLOAT: { 953 if (src->is_single_xmm()) { 954 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 955 } else { 956 assert(src->is_single_fpu(), "must be"); 957 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 958 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 959 else __ fst_s (as_Address(to_addr)); 960 } 961 break; 962 } 963 964 case T_DOUBLE: { 965 if (src->is_double_xmm()) { 966 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 967 } else { 968 assert(src->is_double_fpu(), "must be"); 969 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 970 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 971 else __ fst_d (as_Address(to_addr)); 972 } 973 break; 974 } 975 976 case T_ARRAY: // fall through 977 case T_OBJECT: // fall through 978 if (UseCompressedOops && !wide) { 979 __ movl(as_Address(to_addr), compressed_src); 980 } else { 981 __ movptr(as_Address(to_addr), src->as_register()); 982 } 983 break; 984 case T_METADATA: 985 // We get here to store a method pointer to the stack to pass to 986 // a dtrace runtime call. This can't work on 64 bit with 987 // compressed klass ptrs: T_METADATA can be a compressed klass 988 // ptr or a 64 bit method pointer. 989 LP64_ONLY(ShouldNotReachHere()); 990 __ movptr(as_Address(to_addr), src->as_register()); 991 break; 992 case T_ADDRESS: 993 __ movptr(as_Address(to_addr), src->as_register()); 994 break; 995 case T_INT: 996 __ movl(as_Address(to_addr), src->as_register()); 997 break; 998 999 case T_LONG: { 1000 Register from_lo = src->as_register_lo(); 1001 Register from_hi = src->as_register_hi(); 1002 #ifdef _LP64 1003 __ movptr(as_Address_lo(to_addr), from_lo); 1004 #else 1005 Register base = to_addr->base()->as_register(); 1006 Register index = noreg; 1007 if (to_addr->index()->is_register()) { 1008 index = to_addr->index()->as_register(); 1009 } 1010 if (base == from_lo || index == from_lo) { 1011 assert(base != from_hi, "can't be"); 1012 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1013 __ movl(as_Address_hi(to_addr), from_hi); 1014 if (patch != NULL) { 1015 patching_epilog(patch, lir_patch_high, base, info); 1016 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1017 patch_code = lir_patch_low; 1018 } 1019 __ movl(as_Address_lo(to_addr), from_lo); 1020 } else { 1021 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1022 __ movl(as_Address_lo(to_addr), from_lo); 1023 if (patch != NULL) { 1024 patching_epilog(patch, lir_patch_low, base, info); 1025 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1026 patch_code = lir_patch_high; 1027 } 1028 __ movl(as_Address_hi(to_addr), from_hi); 1029 } 1030 #endif // _LP64 1031 break; 1032 } 1033 1034 case T_BYTE: // fall through 1035 case T_BOOLEAN: { 1036 Register src_reg = src->as_register(); 1037 Address dst_addr = as_Address(to_addr); 1038 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1039 __ movb(dst_addr, src_reg); 1040 break; 1041 } 1042 1043 case T_CHAR: // fall through 1044 case T_SHORT: 1045 __ movw(as_Address(to_addr), src->as_register()); 1046 break; 1047 1048 default: 1049 ShouldNotReachHere(); 1050 } 1051 if (info != NULL) { 1052 add_debug_info_for_null_check(null_check_here, info); 1053 } 1054 1055 if (patch_code != lir_patch_none) { 1056 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1057 } 1058 } 1059 1060 1061 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1062 assert(src->is_stack(), "should not call otherwise"); 1063 assert(dest->is_register(), "should not call otherwise"); 1064 1065 if (dest->is_single_cpu()) { 1066 if (type == T_ARRAY || type == T_OBJECT) { 1067 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1068 __ verify_oop(dest->as_register()); 1069 } else if (type == T_METADATA) { 1070 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1071 } else { 1072 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1073 } 1074 1075 } else if (dest->is_double_cpu()) { 1076 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1077 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1078 __ movptr(dest->as_register_lo(), src_addr_LO); 1079 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1080 1081 } else if (dest->is_single_xmm()) { 1082 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1083 __ movflt(dest->as_xmm_float_reg(), src_addr); 1084 1085 } else if (dest->is_double_xmm()) { 1086 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1087 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1088 1089 } else if (dest->is_single_fpu()) { 1090 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1091 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1092 __ fld_s(src_addr); 1093 1094 } else if (dest->is_double_fpu()) { 1095 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1096 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1097 __ fld_d(src_addr); 1098 1099 } else { 1100 ShouldNotReachHere(); 1101 } 1102 } 1103 1104 1105 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1106 if (src->is_single_stack()) { 1107 if (type == T_OBJECT || type == T_ARRAY) { 1108 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1109 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1110 } else { 1111 #ifndef _LP64 1112 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1113 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1114 #else 1115 //no pushl on 64bits 1116 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1117 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1118 #endif 1119 } 1120 1121 } else if (src->is_double_stack()) { 1122 #ifdef _LP64 1123 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1124 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1125 #else 1126 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1127 // push and pop the part at src + wordSize, adding wordSize for the previous push 1128 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1129 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1130 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1131 #endif // _LP64 1132 1133 } else { 1134 ShouldNotReachHere(); 1135 } 1136 } 1137 1138 1139 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1140 assert(src->is_address(), "should not call otherwise"); 1141 assert(dest->is_register(), "should not call otherwise"); 1142 1143 LIR_Address* addr = src->as_address_ptr(); 1144 Address from_addr = as_Address(addr); 1145 1146 if (addr->base()->type() == T_OBJECT) { 1147 __ verify_oop(addr->base()->as_pointer_register()); 1148 } 1149 1150 switch (type) { 1151 case T_BOOLEAN: // fall through 1152 case T_BYTE: // fall through 1153 case T_CHAR: // fall through 1154 case T_SHORT: 1155 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1156 // on pre P6 processors we may get partial register stalls 1157 // so blow away the value of to_rinfo before loading a 1158 // partial word into it. Do it here so that it precedes 1159 // the potential patch point below. 1160 __ xorptr(dest->as_register(), dest->as_register()); 1161 } 1162 break; 1163 } 1164 1165 PatchingStub* patch = NULL; 1166 if (patch_code != lir_patch_none) { 1167 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1168 assert(from_addr.disp() != 0, "must have"); 1169 } 1170 if (info != NULL) { 1171 add_debug_info_for_null_check_here(info); 1172 } 1173 1174 switch (type) { 1175 case T_FLOAT: { 1176 if (dest->is_single_xmm()) { 1177 __ movflt(dest->as_xmm_float_reg(), from_addr); 1178 } else { 1179 assert(dest->is_single_fpu(), "must be"); 1180 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1181 __ fld_s(from_addr); 1182 } 1183 break; 1184 } 1185 1186 case T_DOUBLE: { 1187 if (dest->is_double_xmm()) { 1188 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1189 } else { 1190 assert(dest->is_double_fpu(), "must be"); 1191 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1192 __ fld_d(from_addr); 1193 } 1194 break; 1195 } 1196 1197 case T_OBJECT: // fall through 1198 case T_ARRAY: // fall through 1199 if (UseCompressedOops && !wide) { 1200 __ movl(dest->as_register(), from_addr); 1201 } else { 1202 __ movptr(dest->as_register(), from_addr); 1203 } 1204 break; 1205 1206 case T_ADDRESS: 1207 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1208 __ movl(dest->as_register(), from_addr); 1209 } else { 1210 __ movptr(dest->as_register(), from_addr); 1211 } 1212 break; 1213 case T_INT: 1214 __ movl(dest->as_register(), from_addr); 1215 break; 1216 1217 case T_LONG: { 1218 Register to_lo = dest->as_register_lo(); 1219 Register to_hi = dest->as_register_hi(); 1220 #ifdef _LP64 1221 __ movptr(to_lo, as_Address_lo(addr)); 1222 #else 1223 Register base = addr->base()->as_register(); 1224 Register index = noreg; 1225 if (addr->index()->is_register()) { 1226 index = addr->index()->as_register(); 1227 } 1228 if ((base == to_lo && index == to_hi) || 1229 (base == to_hi && index == to_lo)) { 1230 // addresses with 2 registers are only formed as a result of 1231 // array access so this code will never have to deal with 1232 // patches or null checks. 1233 assert(info == NULL && patch == NULL, "must be"); 1234 __ lea(to_hi, as_Address(addr)); 1235 __ movl(to_lo, Address(to_hi, 0)); 1236 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1237 } else if (base == to_lo || index == to_lo) { 1238 assert(base != to_hi, "can't be"); 1239 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1240 __ movl(to_hi, as_Address_hi(addr)); 1241 if (patch != NULL) { 1242 patching_epilog(patch, lir_patch_high, base, info); 1243 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1244 patch_code = lir_patch_low; 1245 } 1246 __ movl(to_lo, as_Address_lo(addr)); 1247 } else { 1248 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1249 __ movl(to_lo, as_Address_lo(addr)); 1250 if (patch != NULL) { 1251 patching_epilog(patch, lir_patch_low, base, info); 1252 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1253 patch_code = lir_patch_high; 1254 } 1255 __ movl(to_hi, as_Address_hi(addr)); 1256 } 1257 #endif // _LP64 1258 break; 1259 } 1260 1261 case T_BOOLEAN: // fall through 1262 case T_BYTE: { 1263 Register dest_reg = dest->as_register(); 1264 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1265 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1266 __ movsbl(dest_reg, from_addr); 1267 } else { 1268 __ movb(dest_reg, from_addr); 1269 __ shll(dest_reg, 24); 1270 __ sarl(dest_reg, 24); 1271 } 1272 break; 1273 } 1274 1275 case T_CHAR: { 1276 Register dest_reg = dest->as_register(); 1277 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1278 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1279 __ movzwl(dest_reg, from_addr); 1280 } else { 1281 __ movw(dest_reg, from_addr); 1282 } 1283 break; 1284 } 1285 1286 case T_SHORT: { 1287 Register dest_reg = dest->as_register(); 1288 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1289 __ movswl(dest_reg, from_addr); 1290 } else { 1291 __ movw(dest_reg, from_addr); 1292 __ shll(dest_reg, 16); 1293 __ sarl(dest_reg, 16); 1294 } 1295 break; 1296 } 1297 1298 default: 1299 ShouldNotReachHere(); 1300 } 1301 1302 if (patch != NULL) { 1303 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1304 } 1305 1306 if (type == T_ARRAY || type == T_OBJECT) { 1307 #ifdef _LP64 1308 if (UseCompressedOops && !wide) { 1309 __ decode_heap_oop(dest->as_register()); 1310 } 1311 #endif 1312 __ verify_oop(dest->as_register()); 1313 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1314 #ifdef _LP64 1315 if (UseCompressedClassPointers) { 1316 __ decode_klass_not_null(dest->as_register()); 1317 } 1318 #endif 1319 } 1320 } 1321 1322 1323 NEEDS_CLEANUP; // This could be static? 1324 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1325 int elem_size = type2aelembytes(type); 1326 switch (elem_size) { 1327 case 1: return Address::times_1; 1328 case 2: return Address::times_2; 1329 case 4: return Address::times_4; 1330 case 8: return Address::times_8; 1331 } 1332 ShouldNotReachHere(); 1333 return Address::no_scale; 1334 } 1335 1336 1337 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1338 switch (op->code()) { 1339 case lir_idiv: 1340 case lir_irem: 1341 arithmetic_idiv(op->code(), 1342 op->in_opr1(), 1343 op->in_opr2(), 1344 op->in_opr3(), 1345 op->result_opr(), 1346 op->info()); 1347 break; 1348 case lir_fmad: 1349 __ fmad(op->result_opr()->as_xmm_double_reg(), 1350 op->in_opr1()->as_xmm_double_reg(), 1351 op->in_opr2()->as_xmm_double_reg(), 1352 op->in_opr3()->as_xmm_double_reg()); 1353 break; 1354 case lir_fmaf: 1355 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1356 op->in_opr1()->as_xmm_float_reg(), 1357 op->in_opr2()->as_xmm_float_reg(), 1358 op->in_opr3()->as_xmm_float_reg()); 1359 break; 1360 default: ShouldNotReachHere(); break; 1361 } 1362 } 1363 1364 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1365 #ifdef ASSERT 1366 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1367 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1368 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1369 #endif 1370 1371 if (op->cond() == lir_cond_always) { 1372 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1373 __ jmp (*(op->label())); 1374 } else { 1375 Assembler::Condition acond = Assembler::zero; 1376 if (op->code() == lir_cond_float_branch) { 1377 assert(op->ublock() != NULL, "must have unordered successor"); 1378 __ jcc(Assembler::parity, *(op->ublock()->label())); 1379 switch(op->cond()) { 1380 case lir_cond_equal: acond = Assembler::equal; break; 1381 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1382 case lir_cond_less: acond = Assembler::below; break; 1383 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1384 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1385 case lir_cond_greater: acond = Assembler::above; break; 1386 default: ShouldNotReachHere(); 1387 } 1388 } else { 1389 switch (op->cond()) { 1390 case lir_cond_equal: acond = Assembler::equal; break; 1391 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1392 case lir_cond_less: acond = Assembler::less; break; 1393 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1394 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1395 case lir_cond_greater: acond = Assembler::greater; break; 1396 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1397 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1398 default: ShouldNotReachHere(); 1399 } 1400 } 1401 __ jcc(acond,*(op->label())); 1402 } 1403 } 1404 1405 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1406 LIR_Opr src = op->in_opr(); 1407 LIR_Opr dest = op->result_opr(); 1408 1409 switch (op->bytecode()) { 1410 case Bytecodes::_i2l: 1411 #ifdef _LP64 1412 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1413 #else 1414 move_regs(src->as_register(), dest->as_register_lo()); 1415 move_regs(src->as_register(), dest->as_register_hi()); 1416 __ sarl(dest->as_register_hi(), 31); 1417 #endif // LP64 1418 break; 1419 1420 case Bytecodes::_l2i: 1421 #ifdef _LP64 1422 __ movl(dest->as_register(), src->as_register_lo()); 1423 #else 1424 move_regs(src->as_register_lo(), dest->as_register()); 1425 #endif 1426 break; 1427 1428 case Bytecodes::_i2b: 1429 move_regs(src->as_register(), dest->as_register()); 1430 __ sign_extend_byte(dest->as_register()); 1431 break; 1432 1433 case Bytecodes::_i2c: 1434 move_regs(src->as_register(), dest->as_register()); 1435 __ andl(dest->as_register(), 0xFFFF); 1436 break; 1437 1438 case Bytecodes::_i2s: 1439 move_regs(src->as_register(), dest->as_register()); 1440 __ sign_extend_short(dest->as_register()); 1441 break; 1442 1443 1444 case Bytecodes::_f2d: 1445 case Bytecodes::_d2f: 1446 if (dest->is_single_xmm()) { 1447 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1448 } else if (dest->is_double_xmm()) { 1449 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1450 } else { 1451 assert(src->fpu() == dest->fpu(), "register must be equal"); 1452 // do nothing (float result is rounded later through spilling) 1453 } 1454 break; 1455 1456 case Bytecodes::_i2f: 1457 case Bytecodes::_i2d: 1458 if (dest->is_single_xmm()) { 1459 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1460 } else if (dest->is_double_xmm()) { 1461 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1462 } else { 1463 assert(dest->fpu() == 0, "result must be on TOS"); 1464 __ movl(Address(rsp, 0), src->as_register()); 1465 __ fild_s(Address(rsp, 0)); 1466 } 1467 break; 1468 1469 case Bytecodes::_f2i: 1470 case Bytecodes::_d2i: 1471 if (src->is_single_xmm()) { 1472 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1473 } else if (src->is_double_xmm()) { 1474 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1475 } else { 1476 assert(src->fpu() == 0, "input must be on TOS"); 1477 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1478 __ fist_s(Address(rsp, 0)); 1479 __ movl(dest->as_register(), Address(rsp, 0)); 1480 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1481 } 1482 1483 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1484 assert(op->stub() != NULL, "stub required"); 1485 __ cmpl(dest->as_register(), 0x80000000); 1486 __ jcc(Assembler::equal, *op->stub()->entry()); 1487 __ bind(*op->stub()->continuation()); 1488 break; 1489 1490 case Bytecodes::_l2f: 1491 case Bytecodes::_l2d: 1492 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1493 assert(dest->fpu() == 0, "result must be on TOS"); 1494 1495 __ movptr(Address(rsp, 0), src->as_register_lo()); 1496 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1497 __ fild_d(Address(rsp, 0)); 1498 // float result is rounded later through spilling 1499 break; 1500 1501 case Bytecodes::_f2l: 1502 case Bytecodes::_d2l: 1503 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1504 assert(src->fpu() == 0, "input must be on TOS"); 1505 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1506 1507 // instruction sequence too long to inline it here 1508 { 1509 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1510 } 1511 break; 1512 1513 default: ShouldNotReachHere(); 1514 } 1515 } 1516 1517 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1518 if (op->init_check()) { 1519 __ cmpb(Address(op->klass()->as_register(), 1520 InstanceKlass::init_state_offset()), 1521 InstanceKlass::fully_initialized); 1522 add_debug_info_for_null_check_here(op->stub()->info()); 1523 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1524 } 1525 __ allocate_object(op->obj()->as_register(), 1526 op->tmp1()->as_register(), 1527 op->tmp2()->as_register(), 1528 op->header_size(), 1529 op->object_size(), 1530 op->klass()->as_register(), 1531 *op->stub()->entry()); 1532 __ bind(*op->stub()->continuation()); 1533 } 1534 1535 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1536 Register len = op->len()->as_register(); 1537 LP64_ONLY( __ movslq(len, len); ) 1538 1539 if (UseSlowPath || 1540 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1541 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1542 __ jmp(*op->stub()->entry()); 1543 } else { 1544 Register tmp1 = op->tmp1()->as_register(); 1545 Register tmp2 = op->tmp2()->as_register(); 1546 Register tmp3 = op->tmp3()->as_register(); 1547 if (len == tmp1) { 1548 tmp1 = tmp3; 1549 } else if (len == tmp2) { 1550 tmp2 = tmp3; 1551 } else if (len == tmp3) { 1552 // everything is ok 1553 } else { 1554 __ mov(tmp3, len); 1555 } 1556 __ allocate_array(op->obj()->as_register(), 1557 len, 1558 tmp1, 1559 tmp2, 1560 arrayOopDesc::header_size(op->type()), 1561 array_element_size(op->type()), 1562 op->klass()->as_register(), 1563 *op->stub()->entry()); 1564 } 1565 __ bind(*op->stub()->continuation()); 1566 } 1567 1568 void LIR_Assembler::type_profile_helper(Register mdo, 1569 ciMethodData *md, ciProfileData *data, 1570 Register recv, Label* update_done) { 1571 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1572 Label next_test; 1573 // See if the receiver is receiver[n]. 1574 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1575 __ jccb(Assembler::notEqual, next_test); 1576 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1577 __ addptr(data_addr, DataLayout::counter_increment); 1578 __ jmp(*update_done); 1579 __ bind(next_test); 1580 } 1581 1582 // Didn't find receiver; find next empty slot and fill it in 1583 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1584 Label next_test; 1585 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1586 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1587 __ jccb(Assembler::notEqual, next_test); 1588 __ movptr(recv_addr, recv); 1589 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1590 __ jmp(*update_done); 1591 __ bind(next_test); 1592 } 1593 } 1594 1595 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1596 // we always need a stub for the failure case. 1597 CodeStub* stub = op->stub(); 1598 Register obj = op->object()->as_register(); 1599 Register k_RInfo = op->tmp1()->as_register(); 1600 Register klass_RInfo = op->tmp2()->as_register(); 1601 Register dst = op->result_opr()->as_register(); 1602 ciKlass* k = op->klass(); 1603 Register Rtmp1 = noreg; 1604 1605 // check if it needs to be profiled 1606 ciMethodData* md = NULL; 1607 ciProfileData* data = NULL; 1608 1609 if (op->should_profile()) { 1610 ciMethod* method = op->profiled_method(); 1611 assert(method != NULL, "Should have method"); 1612 int bci = op->profiled_bci(); 1613 md = method->method_data_or_null(); 1614 assert(md != NULL, "Sanity"); 1615 data = md->bci_to_data(bci); 1616 assert(data != NULL, "need data for type check"); 1617 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1618 } 1619 Label profile_cast_success, profile_cast_failure; 1620 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1621 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1622 1623 if (obj == k_RInfo) { 1624 k_RInfo = dst; 1625 } else if (obj == klass_RInfo) { 1626 klass_RInfo = dst; 1627 } 1628 if (k->is_loaded() && !UseCompressedClassPointers) { 1629 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1630 } else { 1631 Rtmp1 = op->tmp3()->as_register(); 1632 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1633 } 1634 1635 assert_different_registers(obj, k_RInfo, klass_RInfo); 1636 1637 __ cmpptr(obj, (int32_t)NULL_WORD); 1638 if (op->should_profile()) { 1639 Label not_null; 1640 __ jccb(Assembler::notEqual, not_null); 1641 // Object is null; update MDO and exit 1642 Register mdo = klass_RInfo; 1643 __ mov_metadata(mdo, md->constant_encoding()); 1644 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1645 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1646 __ orl(data_addr, header_bits); 1647 __ jmp(*obj_is_null); 1648 __ bind(not_null); 1649 } else { 1650 __ jcc(Assembler::equal, *obj_is_null); 1651 } 1652 1653 if (!k->is_loaded()) { 1654 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1655 } else { 1656 #ifdef _LP64 1657 __ mov_metadata(k_RInfo, k->constant_encoding()); 1658 #endif // _LP64 1659 } 1660 __ verify_oop(obj); 1661 1662 if (op->fast_check()) { 1663 // get object class 1664 // not a safepoint as obj null check happens earlier 1665 #ifdef _LP64 1666 if (UseCompressedClassPointers) { 1667 __ load_klass(Rtmp1, obj); 1668 __ cmpptr(k_RInfo, Rtmp1); 1669 } else { 1670 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1671 } 1672 #else 1673 if (k->is_loaded()) { 1674 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1675 } else { 1676 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1677 } 1678 #endif 1679 __ jcc(Assembler::notEqual, *failure_target); 1680 // successful cast, fall through to profile or jump 1681 } else { 1682 // get object class 1683 // not a safepoint as obj null check happens earlier 1684 __ load_klass(klass_RInfo, obj); 1685 if (k->is_loaded()) { 1686 // See if we get an immediate positive hit 1687 #ifdef _LP64 1688 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1689 #else 1690 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1691 #endif // _LP64 1692 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1693 __ jcc(Assembler::notEqual, *failure_target); 1694 // successful cast, fall through to profile or jump 1695 } else { 1696 // See if we get an immediate positive hit 1697 __ jcc(Assembler::equal, *success_target); 1698 // check for self 1699 #ifdef _LP64 1700 __ cmpptr(klass_RInfo, k_RInfo); 1701 #else 1702 __ cmpklass(klass_RInfo, k->constant_encoding()); 1703 #endif // _LP64 1704 __ jcc(Assembler::equal, *success_target); 1705 1706 __ push(klass_RInfo); 1707 #ifdef _LP64 1708 __ push(k_RInfo); 1709 #else 1710 __ pushklass(k->constant_encoding()); 1711 #endif // _LP64 1712 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1713 __ pop(klass_RInfo); 1714 __ pop(klass_RInfo); 1715 // result is a boolean 1716 __ cmpl(klass_RInfo, 0); 1717 __ jcc(Assembler::equal, *failure_target); 1718 // successful cast, fall through to profile or jump 1719 } 1720 } else { 1721 // perform the fast part of the checking logic 1722 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1723 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1724 __ push(klass_RInfo); 1725 __ push(k_RInfo); 1726 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1727 __ pop(klass_RInfo); 1728 __ pop(k_RInfo); 1729 // result is a boolean 1730 __ cmpl(k_RInfo, 0); 1731 __ jcc(Assembler::equal, *failure_target); 1732 // successful cast, fall through to profile or jump 1733 } 1734 } 1735 if (op->should_profile()) { 1736 Register mdo = klass_RInfo, recv = k_RInfo; 1737 __ bind(profile_cast_success); 1738 __ mov_metadata(mdo, md->constant_encoding()); 1739 __ load_klass(recv, obj); 1740 Label update_done; 1741 type_profile_helper(mdo, md, data, recv, success); 1742 __ jmp(*success); 1743 1744 __ bind(profile_cast_failure); 1745 __ mov_metadata(mdo, md->constant_encoding()); 1746 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1747 __ subptr(counter_addr, DataLayout::counter_increment); 1748 __ jmp(*failure); 1749 } 1750 __ jmp(*success); 1751 } 1752 1753 1754 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1755 LIR_Code code = op->code(); 1756 if (code == lir_store_check) { 1757 Register value = op->object()->as_register(); 1758 Register array = op->array()->as_register(); 1759 Register k_RInfo = op->tmp1()->as_register(); 1760 Register klass_RInfo = op->tmp2()->as_register(); 1761 Register Rtmp1 = op->tmp3()->as_register(); 1762 1763 CodeStub* stub = op->stub(); 1764 1765 // check if it needs to be profiled 1766 ciMethodData* md = NULL; 1767 ciProfileData* data = NULL; 1768 1769 if (op->should_profile()) { 1770 ciMethod* method = op->profiled_method(); 1771 assert(method != NULL, "Should have method"); 1772 int bci = op->profiled_bci(); 1773 md = method->method_data_or_null(); 1774 assert(md != NULL, "Sanity"); 1775 data = md->bci_to_data(bci); 1776 assert(data != NULL, "need data for type check"); 1777 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1778 } 1779 Label profile_cast_success, profile_cast_failure, done; 1780 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1781 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1782 1783 __ cmpptr(value, (int32_t)NULL_WORD); 1784 if (op->should_profile()) { 1785 Label not_null; 1786 __ jccb(Assembler::notEqual, not_null); 1787 // Object is null; update MDO and exit 1788 Register mdo = klass_RInfo; 1789 __ mov_metadata(mdo, md->constant_encoding()); 1790 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1791 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1792 __ orl(data_addr, header_bits); 1793 __ jmp(done); 1794 __ bind(not_null); 1795 } else { 1796 __ jcc(Assembler::equal, done); 1797 } 1798 1799 add_debug_info_for_null_check_here(op->info_for_exception()); 1800 __ load_klass(k_RInfo, array); 1801 __ load_klass(klass_RInfo, value); 1802 1803 // get instance klass (it's already uncompressed) 1804 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1805 // perform the fast part of the checking logic 1806 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1807 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1808 __ push(klass_RInfo); 1809 __ push(k_RInfo); 1810 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1811 __ pop(klass_RInfo); 1812 __ pop(k_RInfo); 1813 // result is a boolean 1814 __ cmpl(k_RInfo, 0); 1815 __ jcc(Assembler::equal, *failure_target); 1816 // fall through to the success case 1817 1818 if (op->should_profile()) { 1819 Register mdo = klass_RInfo, recv = k_RInfo; 1820 __ bind(profile_cast_success); 1821 __ mov_metadata(mdo, md->constant_encoding()); 1822 __ load_klass(recv, value); 1823 Label update_done; 1824 type_profile_helper(mdo, md, data, recv, &done); 1825 __ jmpb(done); 1826 1827 __ bind(profile_cast_failure); 1828 __ mov_metadata(mdo, md->constant_encoding()); 1829 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1830 __ subptr(counter_addr, DataLayout::counter_increment); 1831 __ jmp(*stub->entry()); 1832 } 1833 1834 __ bind(done); 1835 } else 1836 if (code == lir_checkcast) { 1837 Register obj = op->object()->as_register(); 1838 Register dst = op->result_opr()->as_register(); 1839 Label success; 1840 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1841 __ bind(success); 1842 if (dst != obj) { 1843 __ mov(dst, obj); 1844 } 1845 } else 1846 if (code == lir_instanceof) { 1847 Register obj = op->object()->as_register(); 1848 Register dst = op->result_opr()->as_register(); 1849 Label success, failure, done; 1850 emit_typecheck_helper(op, &success, &failure, &failure); 1851 __ bind(failure); 1852 __ xorptr(dst, dst); 1853 __ jmpb(done); 1854 __ bind(success); 1855 __ movptr(dst, 1); 1856 __ bind(done); 1857 } else { 1858 ShouldNotReachHere(); 1859 } 1860 1861 } 1862 1863 1864 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1865 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1866 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1867 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1868 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1869 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1870 Register addr = op->addr()->as_register(); 1871 if (os::is_MP()) { 1872 __ lock(); 1873 } 1874 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1875 1876 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1877 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1878 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1879 Register newval = op->new_value()->as_register(); 1880 Register cmpval = op->cmp_value()->as_register(); 1881 assert(cmpval == rax, "wrong register"); 1882 assert(newval != NULL, "new val must be register"); 1883 assert(cmpval != newval, "cmp and new values must be in different registers"); 1884 assert(cmpval != addr, "cmp and addr must be in different registers"); 1885 assert(newval != addr, "new value and addr must be in different registers"); 1886 1887 if ( op->code() == lir_cas_obj) { 1888 #ifdef _LP64 1889 if (UseCompressedOops) { 1890 __ encode_heap_oop(cmpval); 1891 __ mov(rscratch1, newval); 1892 __ encode_heap_oop(rscratch1); 1893 if (os::is_MP()) { 1894 __ lock(); 1895 } 1896 // cmpval (rax) is implicitly used by this instruction 1897 __ cmpxchgl(rscratch1, Address(addr, 0)); 1898 } else 1899 #endif 1900 { 1901 if (os::is_MP()) { 1902 __ lock(); 1903 } 1904 __ cmpxchgptr(newval, Address(addr, 0)); 1905 } 1906 } else { 1907 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1908 if (os::is_MP()) { 1909 __ lock(); 1910 } 1911 __ cmpxchgl(newval, Address(addr, 0)); 1912 } 1913 #ifdef _LP64 1914 } else if (op->code() == lir_cas_long) { 1915 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1916 Register newval = op->new_value()->as_register_lo(); 1917 Register cmpval = op->cmp_value()->as_register_lo(); 1918 assert(cmpval == rax, "wrong register"); 1919 assert(newval != NULL, "new val must be register"); 1920 assert(cmpval != newval, "cmp and new values must be in different registers"); 1921 assert(cmpval != addr, "cmp and addr must be in different registers"); 1922 assert(newval != addr, "new value and addr must be in different registers"); 1923 if (os::is_MP()) { 1924 __ lock(); 1925 } 1926 __ cmpxchgq(newval, Address(addr, 0)); 1927 #endif // _LP64 1928 } else { 1929 Unimplemented(); 1930 } 1931 } 1932 1933 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1934 Assembler::Condition acond, ncond; 1935 switch (condition) { 1936 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1937 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1938 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1939 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1940 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1941 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1942 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1943 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1944 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1945 ShouldNotReachHere(); 1946 } 1947 1948 if (opr1->is_cpu_register()) { 1949 reg2reg(opr1, result); 1950 } else if (opr1->is_stack()) { 1951 stack2reg(opr1, result, result->type()); 1952 } else if (opr1->is_constant()) { 1953 const2reg(opr1, result, lir_patch_none, NULL); 1954 } else { 1955 ShouldNotReachHere(); 1956 } 1957 1958 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1959 // optimized version that does not require a branch 1960 if (opr2->is_single_cpu()) { 1961 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1962 __ cmov(ncond, result->as_register(), opr2->as_register()); 1963 } else if (opr2->is_double_cpu()) { 1964 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1965 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1966 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1967 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1968 } else if (opr2->is_single_stack()) { 1969 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 1970 } else if (opr2->is_double_stack()) { 1971 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 1972 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 1973 } else { 1974 ShouldNotReachHere(); 1975 } 1976 1977 } else { 1978 Label skip; 1979 __ jcc (acond, skip); 1980 if (opr2->is_cpu_register()) { 1981 reg2reg(opr2, result); 1982 } else if (opr2->is_stack()) { 1983 stack2reg(opr2, result, result->type()); 1984 } else if (opr2->is_constant()) { 1985 const2reg(opr2, result, lir_patch_none, NULL); 1986 } else { 1987 ShouldNotReachHere(); 1988 } 1989 __ bind(skip); 1990 } 1991 } 1992 1993 1994 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1995 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1996 1997 if (left->is_single_cpu()) { 1998 assert(left == dest, "left and dest must be equal"); 1999 Register lreg = left->as_register(); 2000 2001 if (right->is_single_cpu()) { 2002 // cpu register - cpu register 2003 Register rreg = right->as_register(); 2004 switch (code) { 2005 case lir_add: __ addl (lreg, rreg); break; 2006 case lir_sub: __ subl (lreg, rreg); break; 2007 case lir_mul: __ imull(lreg, rreg); break; 2008 default: ShouldNotReachHere(); 2009 } 2010 2011 } else if (right->is_stack()) { 2012 // cpu register - stack 2013 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2014 switch (code) { 2015 case lir_add: __ addl(lreg, raddr); break; 2016 case lir_sub: __ subl(lreg, raddr); break; 2017 default: ShouldNotReachHere(); 2018 } 2019 2020 } else if (right->is_constant()) { 2021 // cpu register - constant 2022 jint c = right->as_constant_ptr()->as_jint(); 2023 switch (code) { 2024 case lir_add: { 2025 __ incrementl(lreg, c); 2026 break; 2027 } 2028 case lir_sub: { 2029 __ decrementl(lreg, c); 2030 break; 2031 } 2032 default: ShouldNotReachHere(); 2033 } 2034 2035 } else { 2036 ShouldNotReachHere(); 2037 } 2038 2039 } else if (left->is_double_cpu()) { 2040 assert(left == dest, "left and dest must be equal"); 2041 Register lreg_lo = left->as_register_lo(); 2042 Register lreg_hi = left->as_register_hi(); 2043 2044 if (right->is_double_cpu()) { 2045 // cpu register - cpu register 2046 Register rreg_lo = right->as_register_lo(); 2047 Register rreg_hi = right->as_register_hi(); 2048 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2049 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2050 switch (code) { 2051 case lir_add: 2052 __ addptr(lreg_lo, rreg_lo); 2053 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2054 break; 2055 case lir_sub: 2056 __ subptr(lreg_lo, rreg_lo); 2057 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2058 break; 2059 case lir_mul: 2060 #ifdef _LP64 2061 __ imulq(lreg_lo, rreg_lo); 2062 #else 2063 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2064 __ imull(lreg_hi, rreg_lo); 2065 __ imull(rreg_hi, lreg_lo); 2066 __ addl (rreg_hi, lreg_hi); 2067 __ mull (rreg_lo); 2068 __ addl (lreg_hi, rreg_hi); 2069 #endif // _LP64 2070 break; 2071 default: 2072 ShouldNotReachHere(); 2073 } 2074 2075 } else if (right->is_constant()) { 2076 // cpu register - constant 2077 #ifdef _LP64 2078 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2079 __ movptr(r10, (intptr_t) c); 2080 switch (code) { 2081 case lir_add: 2082 __ addptr(lreg_lo, r10); 2083 break; 2084 case lir_sub: 2085 __ subptr(lreg_lo, r10); 2086 break; 2087 default: 2088 ShouldNotReachHere(); 2089 } 2090 #else 2091 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2092 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2093 switch (code) { 2094 case lir_add: 2095 __ addptr(lreg_lo, c_lo); 2096 __ adcl(lreg_hi, c_hi); 2097 break; 2098 case lir_sub: 2099 __ subptr(lreg_lo, c_lo); 2100 __ sbbl(lreg_hi, c_hi); 2101 break; 2102 default: 2103 ShouldNotReachHere(); 2104 } 2105 #endif // _LP64 2106 2107 } else { 2108 ShouldNotReachHere(); 2109 } 2110 2111 } else if (left->is_single_xmm()) { 2112 assert(left == dest, "left and dest must be equal"); 2113 XMMRegister lreg = left->as_xmm_float_reg(); 2114 2115 if (right->is_single_xmm()) { 2116 XMMRegister rreg = right->as_xmm_float_reg(); 2117 switch (code) { 2118 case lir_add: __ addss(lreg, rreg); break; 2119 case lir_sub: __ subss(lreg, rreg); break; 2120 case lir_mul_strictfp: // fall through 2121 case lir_mul: __ mulss(lreg, rreg); break; 2122 case lir_div_strictfp: // fall through 2123 case lir_div: __ divss(lreg, rreg); break; 2124 default: ShouldNotReachHere(); 2125 } 2126 } else { 2127 Address raddr; 2128 if (right->is_single_stack()) { 2129 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2130 } else if (right->is_constant()) { 2131 // hack for now 2132 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2133 } else { 2134 ShouldNotReachHere(); 2135 } 2136 switch (code) { 2137 case lir_add: __ addss(lreg, raddr); break; 2138 case lir_sub: __ subss(lreg, raddr); break; 2139 case lir_mul_strictfp: // fall through 2140 case lir_mul: __ mulss(lreg, raddr); break; 2141 case lir_div_strictfp: // fall through 2142 case lir_div: __ divss(lreg, raddr); break; 2143 default: ShouldNotReachHere(); 2144 } 2145 } 2146 2147 } else if (left->is_double_xmm()) { 2148 assert(left == dest, "left and dest must be equal"); 2149 2150 XMMRegister lreg = left->as_xmm_double_reg(); 2151 if (right->is_double_xmm()) { 2152 XMMRegister rreg = right->as_xmm_double_reg(); 2153 switch (code) { 2154 case lir_add: __ addsd(lreg, rreg); break; 2155 case lir_sub: __ subsd(lreg, rreg); break; 2156 case lir_mul_strictfp: // fall through 2157 case lir_mul: __ mulsd(lreg, rreg); break; 2158 case lir_div_strictfp: // fall through 2159 case lir_div: __ divsd(lreg, rreg); break; 2160 default: ShouldNotReachHere(); 2161 } 2162 } else { 2163 Address raddr; 2164 if (right->is_double_stack()) { 2165 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2166 } else if (right->is_constant()) { 2167 // hack for now 2168 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2169 } else { 2170 ShouldNotReachHere(); 2171 } 2172 switch (code) { 2173 case lir_add: __ addsd(lreg, raddr); break; 2174 case lir_sub: __ subsd(lreg, raddr); break; 2175 case lir_mul_strictfp: // fall through 2176 case lir_mul: __ mulsd(lreg, raddr); break; 2177 case lir_div_strictfp: // fall through 2178 case lir_div: __ divsd(lreg, raddr); break; 2179 default: ShouldNotReachHere(); 2180 } 2181 } 2182 2183 } else if (left->is_single_fpu()) { 2184 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2185 2186 if (right->is_single_fpu()) { 2187 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2188 2189 } else { 2190 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2191 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2192 2193 Address raddr; 2194 if (right->is_single_stack()) { 2195 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2196 } else if (right->is_constant()) { 2197 address const_addr = float_constant(right->as_jfloat()); 2198 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2199 // hack for now 2200 raddr = __ as_Address(InternalAddress(const_addr)); 2201 } else { 2202 ShouldNotReachHere(); 2203 } 2204 2205 switch (code) { 2206 case lir_add: __ fadd_s(raddr); break; 2207 case lir_sub: __ fsub_s(raddr); break; 2208 case lir_mul_strictfp: // fall through 2209 case lir_mul: __ fmul_s(raddr); break; 2210 case lir_div_strictfp: // fall through 2211 case lir_div: __ fdiv_s(raddr); break; 2212 default: ShouldNotReachHere(); 2213 } 2214 } 2215 2216 } else if (left->is_double_fpu()) { 2217 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2218 2219 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2220 // Double values require special handling for strictfp mul/div on x86 2221 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2222 __ fmulp(left->fpu_regnrLo() + 1); 2223 } 2224 2225 if (right->is_double_fpu()) { 2226 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2227 2228 } else { 2229 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2230 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2231 2232 Address raddr; 2233 if (right->is_double_stack()) { 2234 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2235 } else if (right->is_constant()) { 2236 // hack for now 2237 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2238 } else { 2239 ShouldNotReachHere(); 2240 } 2241 2242 switch (code) { 2243 case lir_add: __ fadd_d(raddr); break; 2244 case lir_sub: __ fsub_d(raddr); break; 2245 case lir_mul_strictfp: // fall through 2246 case lir_mul: __ fmul_d(raddr); break; 2247 case lir_div_strictfp: // fall through 2248 case lir_div: __ fdiv_d(raddr); break; 2249 default: ShouldNotReachHere(); 2250 } 2251 } 2252 2253 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2254 // Double values require special handling for strictfp mul/div on x86 2255 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2256 __ fmulp(dest->fpu_regnrLo() + 1); 2257 } 2258 2259 } else if (left->is_single_stack() || left->is_address()) { 2260 assert(left == dest, "left and dest must be equal"); 2261 2262 Address laddr; 2263 if (left->is_single_stack()) { 2264 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2265 } else if (left->is_address()) { 2266 laddr = as_Address(left->as_address_ptr()); 2267 } else { 2268 ShouldNotReachHere(); 2269 } 2270 2271 if (right->is_single_cpu()) { 2272 Register rreg = right->as_register(); 2273 switch (code) { 2274 case lir_add: __ addl(laddr, rreg); break; 2275 case lir_sub: __ subl(laddr, rreg); break; 2276 default: ShouldNotReachHere(); 2277 } 2278 } else if (right->is_constant()) { 2279 jint c = right->as_constant_ptr()->as_jint(); 2280 switch (code) { 2281 case lir_add: { 2282 __ incrementl(laddr, c); 2283 break; 2284 } 2285 case lir_sub: { 2286 __ decrementl(laddr, c); 2287 break; 2288 } 2289 default: ShouldNotReachHere(); 2290 } 2291 } else { 2292 ShouldNotReachHere(); 2293 } 2294 2295 } else { 2296 ShouldNotReachHere(); 2297 } 2298 } 2299 2300 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2301 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2302 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2303 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2304 2305 bool left_is_tos = (left_index == 0); 2306 bool dest_is_tos = (dest_index == 0); 2307 int non_tos_index = (left_is_tos ? right_index : left_index); 2308 2309 switch (code) { 2310 case lir_add: 2311 if (pop_fpu_stack) __ faddp(non_tos_index); 2312 else if (dest_is_tos) __ fadd (non_tos_index); 2313 else __ fadda(non_tos_index); 2314 break; 2315 2316 case lir_sub: 2317 if (left_is_tos) { 2318 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2319 else if (dest_is_tos) __ fsub (non_tos_index); 2320 else __ fsubra(non_tos_index); 2321 } else { 2322 if (pop_fpu_stack) __ fsubp (non_tos_index); 2323 else if (dest_is_tos) __ fsubr (non_tos_index); 2324 else __ fsuba (non_tos_index); 2325 } 2326 break; 2327 2328 case lir_mul_strictfp: // fall through 2329 case lir_mul: 2330 if (pop_fpu_stack) __ fmulp(non_tos_index); 2331 else if (dest_is_tos) __ fmul (non_tos_index); 2332 else __ fmula(non_tos_index); 2333 break; 2334 2335 case lir_div_strictfp: // fall through 2336 case lir_div: 2337 if (left_is_tos) { 2338 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2339 else if (dest_is_tos) __ fdiv (non_tos_index); 2340 else __ fdivra(non_tos_index); 2341 } else { 2342 if (pop_fpu_stack) __ fdivp (non_tos_index); 2343 else if (dest_is_tos) __ fdivr (non_tos_index); 2344 else __ fdiva (non_tos_index); 2345 } 2346 break; 2347 2348 case lir_rem: 2349 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2350 __ fremr(noreg); 2351 break; 2352 2353 default: 2354 ShouldNotReachHere(); 2355 } 2356 } 2357 2358 2359 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2360 if (value->is_double_xmm()) { 2361 switch(code) { 2362 case lir_abs : 2363 { 2364 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2365 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2366 } 2367 __ andpd(dest->as_xmm_double_reg(), 2368 ExternalAddress((address)double_signmask_pool)); 2369 } 2370 break; 2371 2372 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2373 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2374 default : ShouldNotReachHere(); 2375 } 2376 2377 } else if (value->is_double_fpu()) { 2378 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2379 switch(code) { 2380 case lir_abs : __ fabs() ; break; 2381 case lir_sqrt : __ fsqrt(); break; 2382 default : ShouldNotReachHere(); 2383 } 2384 } else { 2385 Unimplemented(); 2386 } 2387 } 2388 2389 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2390 // assert(left->destroys_register(), "check"); 2391 if (left->is_single_cpu()) { 2392 Register reg = left->as_register(); 2393 if (right->is_constant()) { 2394 int val = right->as_constant_ptr()->as_jint(); 2395 switch (code) { 2396 case lir_logic_and: __ andl (reg, val); break; 2397 case lir_logic_or: __ orl (reg, val); break; 2398 case lir_logic_xor: __ xorl (reg, val); break; 2399 default: ShouldNotReachHere(); 2400 } 2401 } else if (right->is_stack()) { 2402 // added support for stack operands 2403 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2404 switch (code) { 2405 case lir_logic_and: __ andl (reg, raddr); break; 2406 case lir_logic_or: __ orl (reg, raddr); break; 2407 case lir_logic_xor: __ xorl (reg, raddr); break; 2408 default: ShouldNotReachHere(); 2409 } 2410 } else { 2411 Register rright = right->as_register(); 2412 switch (code) { 2413 case lir_logic_and: __ andptr (reg, rright); break; 2414 case lir_logic_or : __ orptr (reg, rright); break; 2415 case lir_logic_xor: __ xorptr (reg, rright); break; 2416 default: ShouldNotReachHere(); 2417 } 2418 } 2419 move_regs(reg, dst->as_register()); 2420 } else { 2421 Register l_lo = left->as_register_lo(); 2422 Register l_hi = left->as_register_hi(); 2423 if (right->is_constant()) { 2424 #ifdef _LP64 2425 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2426 switch (code) { 2427 case lir_logic_and: 2428 __ andq(l_lo, rscratch1); 2429 break; 2430 case lir_logic_or: 2431 __ orq(l_lo, rscratch1); 2432 break; 2433 case lir_logic_xor: 2434 __ xorq(l_lo, rscratch1); 2435 break; 2436 default: ShouldNotReachHere(); 2437 } 2438 #else 2439 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2440 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2441 switch (code) { 2442 case lir_logic_and: 2443 __ andl(l_lo, r_lo); 2444 __ andl(l_hi, r_hi); 2445 break; 2446 case lir_logic_or: 2447 __ orl(l_lo, r_lo); 2448 __ orl(l_hi, r_hi); 2449 break; 2450 case lir_logic_xor: 2451 __ xorl(l_lo, r_lo); 2452 __ xorl(l_hi, r_hi); 2453 break; 2454 default: ShouldNotReachHere(); 2455 } 2456 #endif // _LP64 2457 } else { 2458 #ifdef _LP64 2459 Register r_lo; 2460 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2461 r_lo = right->as_register(); 2462 } else { 2463 r_lo = right->as_register_lo(); 2464 } 2465 #else 2466 Register r_lo = right->as_register_lo(); 2467 Register r_hi = right->as_register_hi(); 2468 assert(l_lo != r_hi, "overwriting registers"); 2469 #endif 2470 switch (code) { 2471 case lir_logic_and: 2472 __ andptr(l_lo, r_lo); 2473 NOT_LP64(__ andptr(l_hi, r_hi);) 2474 break; 2475 case lir_logic_or: 2476 __ orptr(l_lo, r_lo); 2477 NOT_LP64(__ orptr(l_hi, r_hi);) 2478 break; 2479 case lir_logic_xor: 2480 __ xorptr(l_lo, r_lo); 2481 NOT_LP64(__ xorptr(l_hi, r_hi);) 2482 break; 2483 default: ShouldNotReachHere(); 2484 } 2485 } 2486 2487 Register dst_lo = dst->as_register_lo(); 2488 Register dst_hi = dst->as_register_hi(); 2489 2490 #ifdef _LP64 2491 move_regs(l_lo, dst_lo); 2492 #else 2493 if (dst_lo == l_hi) { 2494 assert(dst_hi != l_lo, "overwriting registers"); 2495 move_regs(l_hi, dst_hi); 2496 move_regs(l_lo, dst_lo); 2497 } else { 2498 assert(dst_lo != l_hi, "overwriting registers"); 2499 move_regs(l_lo, dst_lo); 2500 move_regs(l_hi, dst_hi); 2501 } 2502 #endif // _LP64 2503 } 2504 } 2505 2506 2507 // we assume that rax, and rdx can be overwritten 2508 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2509 2510 assert(left->is_single_cpu(), "left must be register"); 2511 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2512 assert(result->is_single_cpu(), "result must be register"); 2513 2514 // assert(left->destroys_register(), "check"); 2515 // assert(right->destroys_register(), "check"); 2516 2517 Register lreg = left->as_register(); 2518 Register dreg = result->as_register(); 2519 2520 if (right->is_constant()) { 2521 int divisor = right->as_constant_ptr()->as_jint(); 2522 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2523 if (code == lir_idiv) { 2524 assert(lreg == rax, "must be rax,"); 2525 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2526 __ cdql(); // sign extend into rdx:rax 2527 if (divisor == 2) { 2528 __ subl(lreg, rdx); 2529 } else { 2530 __ andl(rdx, divisor - 1); 2531 __ addl(lreg, rdx); 2532 } 2533 __ sarl(lreg, log2_intptr(divisor)); 2534 move_regs(lreg, dreg); 2535 } else if (code == lir_irem) { 2536 Label done; 2537 __ mov(dreg, lreg); 2538 __ andl(dreg, 0x80000000 | (divisor - 1)); 2539 __ jcc(Assembler::positive, done); 2540 __ decrement(dreg); 2541 __ orl(dreg, ~(divisor - 1)); 2542 __ increment(dreg); 2543 __ bind(done); 2544 } else { 2545 ShouldNotReachHere(); 2546 } 2547 } else { 2548 Register rreg = right->as_register(); 2549 assert(lreg == rax, "left register must be rax,"); 2550 assert(rreg != rdx, "right register must not be rdx"); 2551 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2552 2553 move_regs(lreg, rax); 2554 2555 int idivl_offset = __ corrected_idivl(rreg); 2556 add_debug_info_for_div0(idivl_offset, info); 2557 if (code == lir_irem) { 2558 move_regs(rdx, dreg); // result is in rdx 2559 } else { 2560 move_regs(rax, dreg); 2561 } 2562 } 2563 } 2564 2565 2566 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2567 if (opr1->is_single_cpu()) { 2568 Register reg1 = opr1->as_register(); 2569 if (opr2->is_single_cpu()) { 2570 // cpu register - cpu register 2571 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2572 __ cmpptr(reg1, opr2->as_register()); 2573 } else { 2574 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2575 __ cmpl(reg1, opr2->as_register()); 2576 } 2577 } else if (opr2->is_stack()) { 2578 // cpu register - stack 2579 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2580 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2581 } else { 2582 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2583 } 2584 } else if (opr2->is_constant()) { 2585 // cpu register - constant 2586 LIR_Const* c = opr2->as_constant_ptr(); 2587 if (c->type() == T_INT) { 2588 __ cmpl(reg1, c->as_jint()); 2589 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2590 // In 64bit oops are single register 2591 jobject o = c->as_jobject(); 2592 if (o == NULL) { 2593 __ cmpptr(reg1, (int32_t)NULL_WORD); 2594 } else { 2595 #ifdef _LP64 2596 __ movoop(rscratch1, o); 2597 __ cmpptr(reg1, rscratch1); 2598 #else 2599 __ cmpoop(reg1, c->as_jobject()); 2600 #endif // _LP64 2601 } 2602 } else { 2603 fatal("unexpected type: %s", basictype_to_str(c->type())); 2604 } 2605 // cpu register - address 2606 } else if (opr2->is_address()) { 2607 if (op->info() != NULL) { 2608 add_debug_info_for_null_check_here(op->info()); 2609 } 2610 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2611 } else { 2612 ShouldNotReachHere(); 2613 } 2614 2615 } else if(opr1->is_double_cpu()) { 2616 Register xlo = opr1->as_register_lo(); 2617 Register xhi = opr1->as_register_hi(); 2618 if (opr2->is_double_cpu()) { 2619 #ifdef _LP64 2620 __ cmpptr(xlo, opr2->as_register_lo()); 2621 #else 2622 // cpu register - cpu register 2623 Register ylo = opr2->as_register_lo(); 2624 Register yhi = opr2->as_register_hi(); 2625 __ subl(xlo, ylo); 2626 __ sbbl(xhi, yhi); 2627 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2628 __ orl(xhi, xlo); 2629 } 2630 #endif // _LP64 2631 } else if (opr2->is_constant()) { 2632 // cpu register - constant 0 2633 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2634 #ifdef _LP64 2635 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2636 #else 2637 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2638 __ orl(xhi, xlo); 2639 #endif // _LP64 2640 } else { 2641 ShouldNotReachHere(); 2642 } 2643 2644 } else if (opr1->is_single_xmm()) { 2645 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2646 if (opr2->is_single_xmm()) { 2647 // xmm register - xmm register 2648 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2649 } else if (opr2->is_stack()) { 2650 // xmm register - stack 2651 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2652 } else if (opr2->is_constant()) { 2653 // xmm register - constant 2654 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2655 } else if (opr2->is_address()) { 2656 // xmm register - address 2657 if (op->info() != NULL) { 2658 add_debug_info_for_null_check_here(op->info()); 2659 } 2660 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2661 } else { 2662 ShouldNotReachHere(); 2663 } 2664 2665 } else if (opr1->is_double_xmm()) { 2666 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2667 if (opr2->is_double_xmm()) { 2668 // xmm register - xmm register 2669 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2670 } else if (opr2->is_stack()) { 2671 // xmm register - stack 2672 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2673 } else if (opr2->is_constant()) { 2674 // xmm register - constant 2675 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2676 } else if (opr2->is_address()) { 2677 // xmm register - address 2678 if (op->info() != NULL) { 2679 add_debug_info_for_null_check_here(op->info()); 2680 } 2681 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2682 } else { 2683 ShouldNotReachHere(); 2684 } 2685 2686 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2687 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2688 assert(opr2->is_fpu_register(), "both must be registers"); 2689 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2690 2691 } else if (opr1->is_address() && opr2->is_constant()) { 2692 LIR_Const* c = opr2->as_constant_ptr(); 2693 #ifdef _LP64 2694 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2695 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2696 __ movoop(rscratch1, c->as_jobject()); 2697 } 2698 #endif // LP64 2699 if (op->info() != NULL) { 2700 add_debug_info_for_null_check_here(op->info()); 2701 } 2702 // special case: address - constant 2703 LIR_Address* addr = opr1->as_address_ptr(); 2704 if (c->type() == T_INT) { 2705 __ cmpl(as_Address(addr), c->as_jint()); 2706 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2707 #ifdef _LP64 2708 // %%% Make this explode if addr isn't reachable until we figure out a 2709 // better strategy by giving noreg as the temp for as_Address 2710 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2711 #else 2712 __ cmpoop(as_Address(addr), c->as_jobject()); 2713 #endif // _LP64 2714 } else { 2715 ShouldNotReachHere(); 2716 } 2717 2718 } else { 2719 ShouldNotReachHere(); 2720 } 2721 } 2722 2723 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2724 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2725 if (left->is_single_xmm()) { 2726 assert(right->is_single_xmm(), "must match"); 2727 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2728 } else if (left->is_double_xmm()) { 2729 assert(right->is_double_xmm(), "must match"); 2730 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2731 2732 } else { 2733 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2734 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2735 2736 assert(left->fpu() == 0, "left must be on TOS"); 2737 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2738 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2739 } 2740 } else { 2741 assert(code == lir_cmp_l2i, "check"); 2742 #ifdef _LP64 2743 Label done; 2744 Register dest = dst->as_register(); 2745 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2746 __ movl(dest, -1); 2747 __ jccb(Assembler::less, done); 2748 __ set_byte_if_not_zero(dest); 2749 __ movzbl(dest, dest); 2750 __ bind(done); 2751 #else 2752 __ lcmp2int(left->as_register_hi(), 2753 left->as_register_lo(), 2754 right->as_register_hi(), 2755 right->as_register_lo()); 2756 move_regs(left->as_register_hi(), dst->as_register()); 2757 #endif // _LP64 2758 } 2759 } 2760 2761 2762 void LIR_Assembler::align_call(LIR_Code code) { 2763 if (os::is_MP()) { 2764 // make sure that the displacement word of the call ends up word aligned 2765 int offset = __ offset(); 2766 switch (code) { 2767 case lir_static_call: 2768 case lir_optvirtual_call: 2769 case lir_dynamic_call: 2770 offset += NativeCall::displacement_offset; 2771 break; 2772 case lir_icvirtual_call: 2773 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2774 break; 2775 case lir_virtual_call: // currently, sparc-specific for niagara 2776 default: ShouldNotReachHere(); 2777 } 2778 __ align(BytesPerWord, offset); 2779 } 2780 } 2781 2782 2783 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2784 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2785 "must be aligned"); 2786 __ call(AddressLiteral(op->addr(), rtype)); 2787 add_call_info(code_offset(), op->info()); 2788 } 2789 2790 2791 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2792 __ ic_call(op->addr()); 2793 add_call_info(code_offset(), op->info()); 2794 assert(!os::is_MP() || 2795 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2796 "must be aligned"); 2797 } 2798 2799 2800 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2801 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2802 ShouldNotReachHere(); 2803 } 2804 2805 2806 void LIR_Assembler::emit_static_call_stub() { 2807 address call_pc = __ pc(); 2808 address stub = __ start_a_stub(call_stub_size()); 2809 if (stub == NULL) { 2810 bailout("static call stub overflow"); 2811 return; 2812 } 2813 2814 int start = __ offset(); 2815 if (os::is_MP()) { 2816 // make sure that the displacement word of the call ends up word aligned 2817 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2818 } 2819 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2820 __ mov_metadata(rbx, (Metadata*)NULL); 2821 // must be set to -1 at code generation time 2822 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2823 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2824 __ jump(RuntimeAddress(__ pc())); 2825 2826 if (UseAOT) { 2827 // Trampoline to aot code 2828 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2829 #ifdef _LP64 2830 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2831 #else 2832 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2833 #endif 2834 __ jmp(rax); 2835 } 2836 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2837 __ end_a_stub(); 2838 } 2839 2840 2841 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2842 assert(exceptionOop->as_register() == rax, "must match"); 2843 assert(exceptionPC->as_register() == rdx, "must match"); 2844 2845 // exception object is not added to oop map by LinearScan 2846 // (LinearScan assumes that no oops are in fixed registers) 2847 info->add_register_oop(exceptionOop); 2848 Runtime1::StubID unwind_id; 2849 2850 // get current pc information 2851 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2852 int pc_for_athrow_offset = __ offset(); 2853 InternalAddress pc_for_athrow(__ pc()); 2854 __ lea(exceptionPC->as_register(), pc_for_athrow); 2855 add_call_info(pc_for_athrow_offset, info); // for exception handler 2856 2857 __ verify_not_null_oop(rax); 2858 // search an exception handler (rax: exception oop, rdx: throwing pc) 2859 if (compilation()->has_fpu_code()) { 2860 unwind_id = Runtime1::handle_exception_id; 2861 } else { 2862 unwind_id = Runtime1::handle_exception_nofpu_id; 2863 } 2864 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2865 2866 // enough room for two byte trap 2867 __ nop(); 2868 } 2869 2870 2871 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2872 assert(exceptionOop->as_register() == rax, "must match"); 2873 2874 __ jmp(_unwind_handler_entry); 2875 } 2876 2877 2878 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2879 2880 // optimized version for linear scan: 2881 // * count must be already in ECX (guaranteed by LinearScan) 2882 // * left and dest must be equal 2883 // * tmp must be unused 2884 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2885 assert(left == dest, "left and dest must be equal"); 2886 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2887 2888 if (left->is_single_cpu()) { 2889 Register value = left->as_register(); 2890 assert(value != SHIFT_count, "left cannot be ECX"); 2891 2892 switch (code) { 2893 case lir_shl: __ shll(value); break; 2894 case lir_shr: __ sarl(value); break; 2895 case lir_ushr: __ shrl(value); break; 2896 default: ShouldNotReachHere(); 2897 } 2898 } else if (left->is_double_cpu()) { 2899 Register lo = left->as_register_lo(); 2900 Register hi = left->as_register_hi(); 2901 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2902 #ifdef _LP64 2903 switch (code) { 2904 case lir_shl: __ shlptr(lo); break; 2905 case lir_shr: __ sarptr(lo); break; 2906 case lir_ushr: __ shrptr(lo); break; 2907 default: ShouldNotReachHere(); 2908 } 2909 #else 2910 2911 switch (code) { 2912 case lir_shl: __ lshl(hi, lo); break; 2913 case lir_shr: __ lshr(hi, lo, true); break; 2914 case lir_ushr: __ lshr(hi, lo, false); break; 2915 default: ShouldNotReachHere(); 2916 } 2917 #endif // LP64 2918 } else { 2919 ShouldNotReachHere(); 2920 } 2921 } 2922 2923 2924 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2925 if (dest->is_single_cpu()) { 2926 // first move left into dest so that left is not destroyed by the shift 2927 Register value = dest->as_register(); 2928 count = count & 0x1F; // Java spec 2929 2930 move_regs(left->as_register(), value); 2931 switch (code) { 2932 case lir_shl: __ shll(value, count); break; 2933 case lir_shr: __ sarl(value, count); break; 2934 case lir_ushr: __ shrl(value, count); break; 2935 default: ShouldNotReachHere(); 2936 } 2937 } else if (dest->is_double_cpu()) { 2938 #ifndef _LP64 2939 Unimplemented(); 2940 #else 2941 // first move left into dest so that left is not destroyed by the shift 2942 Register value = dest->as_register_lo(); 2943 count = count & 0x1F; // Java spec 2944 2945 move_regs(left->as_register_lo(), value); 2946 switch (code) { 2947 case lir_shl: __ shlptr(value, count); break; 2948 case lir_shr: __ sarptr(value, count); break; 2949 case lir_ushr: __ shrptr(value, count); break; 2950 default: ShouldNotReachHere(); 2951 } 2952 #endif // _LP64 2953 } else { 2954 ShouldNotReachHere(); 2955 } 2956 } 2957 2958 2959 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2960 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2961 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2962 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2963 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2964 } 2965 2966 2967 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2968 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2969 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2970 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2971 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 2972 } 2973 2974 2975 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2976 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2977 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2978 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2979 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 2980 } 2981 2982 2983 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 2984 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2985 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2986 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2987 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 2988 } 2989 2990 2991 // This code replaces a call to arraycopy; no exception may 2992 // be thrown in this code, they must be thrown in the System.arraycopy 2993 // activation frame; we could save some checks if this would not be the case 2994 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2995 ciArrayKlass* default_type = op->expected_type(); 2996 Register src = op->src()->as_register(); 2997 Register dst = op->dst()->as_register(); 2998 Register src_pos = op->src_pos()->as_register(); 2999 Register dst_pos = op->dst_pos()->as_register(); 3000 Register length = op->length()->as_register(); 3001 Register tmp = op->tmp()->as_register(); 3002 3003 CodeStub* stub = op->stub(); 3004 int flags = op->flags(); 3005 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3006 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3007 3008 // if we don't know anything, just go through the generic arraycopy 3009 if (default_type == NULL) { 3010 Label done; 3011 // save outgoing arguments on stack in case call to System.arraycopy is needed 3012 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3013 // for interpreter calling conventions. Now we have to do it in new style conventions. 3014 // For the moment until C1 gets the new register allocator I just force all the 3015 // args to the right place (except the register args) and then on the back side 3016 // reload the register args properly if we go slow path. Yuck 3017 3018 // These are proper for the calling convention 3019 store_parameter(length, 2); 3020 store_parameter(dst_pos, 1); 3021 store_parameter(dst, 0); 3022 3023 // these are just temporary placements until we need to reload 3024 store_parameter(src_pos, 3); 3025 store_parameter(src, 4); 3026 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3027 3028 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3029 3030 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3031 3032 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3033 #ifdef _LP64 3034 // The arguments are in java calling convention so we can trivially shift them to C 3035 // convention 3036 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3037 __ mov(c_rarg0, j_rarg0); 3038 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3039 __ mov(c_rarg1, j_rarg1); 3040 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3041 __ mov(c_rarg2, j_rarg2); 3042 assert_different_registers(c_rarg3, j_rarg4); 3043 __ mov(c_rarg3, j_rarg3); 3044 #ifdef _WIN64 3045 // Allocate abi space for args but be sure to keep stack aligned 3046 __ subptr(rsp, 6*wordSize); 3047 store_parameter(j_rarg4, 4); 3048 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3049 __ call(RuntimeAddress(C_entry)); 3050 } else { 3051 #ifndef PRODUCT 3052 if (PrintC1Statistics) { 3053 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3054 } 3055 #endif 3056 __ call(RuntimeAddress(copyfunc_addr)); 3057 } 3058 __ addptr(rsp, 6*wordSize); 3059 #else 3060 __ mov(c_rarg4, j_rarg4); 3061 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3062 __ call(RuntimeAddress(C_entry)); 3063 } else { 3064 #ifndef PRODUCT 3065 if (PrintC1Statistics) { 3066 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3067 } 3068 #endif 3069 __ call(RuntimeAddress(copyfunc_addr)); 3070 } 3071 #endif // _WIN64 3072 #else 3073 __ push(length); 3074 __ push(dst_pos); 3075 __ push(dst); 3076 __ push(src_pos); 3077 __ push(src); 3078 3079 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3080 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3081 } else { 3082 #ifndef PRODUCT 3083 if (PrintC1Statistics) { 3084 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3085 } 3086 #endif 3087 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3088 } 3089 3090 #endif // _LP64 3091 3092 __ cmpl(rax, 0); 3093 __ jcc(Assembler::equal, *stub->continuation()); 3094 3095 if (copyfunc_addr != NULL) { 3096 __ mov(tmp, rax); 3097 __ xorl(tmp, -1); 3098 } 3099 3100 // Reload values from the stack so they are where the stub 3101 // expects them. 3102 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3103 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3104 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3105 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3106 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3107 3108 if (copyfunc_addr != NULL) { 3109 __ subl(length, tmp); 3110 __ addl(src_pos, tmp); 3111 __ addl(dst_pos, tmp); 3112 } 3113 __ jmp(*stub->entry()); 3114 3115 __ bind(*stub->continuation()); 3116 return; 3117 } 3118 3119 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3120 3121 int elem_size = type2aelembytes(basic_type); 3122 Address::ScaleFactor scale; 3123 3124 switch (elem_size) { 3125 case 1 : 3126 scale = Address::times_1; 3127 break; 3128 case 2 : 3129 scale = Address::times_2; 3130 break; 3131 case 4 : 3132 scale = Address::times_4; 3133 break; 3134 case 8 : 3135 scale = Address::times_8; 3136 break; 3137 default: 3138 scale = Address::no_scale; 3139 ShouldNotReachHere(); 3140 } 3141 3142 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3143 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3144 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3145 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3146 3147 // length and pos's are all sign extended at this point on 64bit 3148 3149 // test for NULL 3150 if (flags & LIR_OpArrayCopy::src_null_check) { 3151 __ testptr(src, src); 3152 __ jcc(Assembler::zero, *stub->entry()); 3153 } 3154 if (flags & LIR_OpArrayCopy::dst_null_check) { 3155 __ testptr(dst, dst); 3156 __ jcc(Assembler::zero, *stub->entry()); 3157 } 3158 3159 // If the compiler was not able to prove that exact type of the source or the destination 3160 // of the arraycopy is an array type, check at runtime if the source or the destination is 3161 // an instance type. 3162 if (flags & LIR_OpArrayCopy::type_check) { 3163 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3164 __ load_klass(tmp, dst); 3165 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3166 __ jcc(Assembler::greaterEqual, *stub->entry()); 3167 } 3168 3169 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3170 __ load_klass(tmp, src); 3171 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3172 __ jcc(Assembler::greaterEqual, *stub->entry()); 3173 } 3174 } 3175 3176 // check if negative 3177 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3178 __ testl(src_pos, src_pos); 3179 __ jcc(Assembler::less, *stub->entry()); 3180 } 3181 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3182 __ testl(dst_pos, dst_pos); 3183 __ jcc(Assembler::less, *stub->entry()); 3184 } 3185 3186 if (flags & LIR_OpArrayCopy::src_range_check) { 3187 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3188 __ cmpl(tmp, src_length_addr); 3189 __ jcc(Assembler::above, *stub->entry()); 3190 } 3191 if (flags & LIR_OpArrayCopy::dst_range_check) { 3192 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3193 __ cmpl(tmp, dst_length_addr); 3194 __ jcc(Assembler::above, *stub->entry()); 3195 } 3196 3197 if (flags & LIR_OpArrayCopy::length_positive_check) { 3198 __ testl(length, length); 3199 __ jcc(Assembler::less, *stub->entry()); 3200 } 3201 3202 #ifdef _LP64 3203 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3204 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3205 #endif 3206 3207 if (flags & LIR_OpArrayCopy::type_check) { 3208 // We don't know the array types are compatible 3209 if (basic_type != T_OBJECT) { 3210 // Simple test for basic type arrays 3211 if (UseCompressedClassPointers) { 3212 __ movl(tmp, src_klass_addr); 3213 __ cmpl(tmp, dst_klass_addr); 3214 } else { 3215 __ movptr(tmp, src_klass_addr); 3216 __ cmpptr(tmp, dst_klass_addr); 3217 } 3218 __ jcc(Assembler::notEqual, *stub->entry()); 3219 } else { 3220 // For object arrays, if src is a sub class of dst then we can 3221 // safely do the copy. 3222 Label cont, slow; 3223 3224 __ push(src); 3225 __ push(dst); 3226 3227 __ load_klass(src, src); 3228 __ load_klass(dst, dst); 3229 3230 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3231 3232 __ push(src); 3233 __ push(dst); 3234 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3235 __ pop(dst); 3236 __ pop(src); 3237 3238 __ cmpl(src, 0); 3239 __ jcc(Assembler::notEqual, cont); 3240 3241 __ bind(slow); 3242 __ pop(dst); 3243 __ pop(src); 3244 3245 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3246 if (copyfunc_addr != NULL) { // use stub if available 3247 // src is not a sub class of dst so we have to do a 3248 // per-element check. 3249 3250 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3251 if ((flags & mask) != mask) { 3252 // Check that at least both of them object arrays. 3253 assert(flags & mask, "one of the two should be known to be an object array"); 3254 3255 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3256 __ load_klass(tmp, src); 3257 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3258 __ load_klass(tmp, dst); 3259 } 3260 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3261 Address klass_lh_addr(tmp, lh_offset); 3262 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3263 __ cmpl(klass_lh_addr, objArray_lh); 3264 __ jcc(Assembler::notEqual, *stub->entry()); 3265 } 3266 3267 // Spill because stubs can use any register they like and it's 3268 // easier to restore just those that we care about. 3269 store_parameter(dst, 0); 3270 store_parameter(dst_pos, 1); 3271 store_parameter(length, 2); 3272 store_parameter(src_pos, 3); 3273 store_parameter(src, 4); 3274 3275 #ifndef _LP64 3276 __ movptr(tmp, dst_klass_addr); 3277 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3278 __ push(tmp); 3279 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3280 __ push(tmp); 3281 __ push(length); 3282 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3283 __ push(tmp); 3284 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3285 __ push(tmp); 3286 3287 __ call_VM_leaf(copyfunc_addr, 5); 3288 #else 3289 __ movl2ptr(length, length); //higher 32bits must be null 3290 3291 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3292 assert_different_registers(c_rarg0, dst, dst_pos, length); 3293 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3294 assert_different_registers(c_rarg1, dst, length); 3295 3296 __ mov(c_rarg2, length); 3297 assert_different_registers(c_rarg2, dst); 3298 3299 #ifdef _WIN64 3300 // Allocate abi space for args but be sure to keep stack aligned 3301 __ subptr(rsp, 6*wordSize); 3302 __ load_klass(c_rarg3, dst); 3303 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3304 store_parameter(c_rarg3, 4); 3305 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3306 __ call(RuntimeAddress(copyfunc_addr)); 3307 __ addptr(rsp, 6*wordSize); 3308 #else 3309 __ load_klass(c_rarg4, dst); 3310 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3311 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3312 __ call(RuntimeAddress(copyfunc_addr)); 3313 #endif 3314 3315 #endif 3316 3317 #ifndef PRODUCT 3318 if (PrintC1Statistics) { 3319 Label failed; 3320 __ testl(rax, rax); 3321 __ jcc(Assembler::notZero, failed); 3322 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3323 __ bind(failed); 3324 } 3325 #endif 3326 3327 __ testl(rax, rax); 3328 __ jcc(Assembler::zero, *stub->continuation()); 3329 3330 #ifndef PRODUCT 3331 if (PrintC1Statistics) { 3332 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3333 } 3334 #endif 3335 3336 __ mov(tmp, rax); 3337 3338 __ xorl(tmp, -1); 3339 3340 // Restore previously spilled arguments 3341 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3342 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3343 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3344 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3345 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3346 3347 3348 __ subl(length, tmp); 3349 __ addl(src_pos, tmp); 3350 __ addl(dst_pos, tmp); 3351 } 3352 3353 __ jmp(*stub->entry()); 3354 3355 __ bind(cont); 3356 __ pop(dst); 3357 __ pop(src); 3358 } 3359 } 3360 3361 #ifdef ASSERT 3362 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3363 // Sanity check the known type with the incoming class. For the 3364 // primitive case the types must match exactly with src.klass and 3365 // dst.klass each exactly matching the default type. For the 3366 // object array case, if no type check is needed then either the 3367 // dst type is exactly the expected type and the src type is a 3368 // subtype which we can't check or src is the same array as dst 3369 // but not necessarily exactly of type default_type. 3370 Label known_ok, halt; 3371 __ mov_metadata(tmp, default_type->constant_encoding()); 3372 #ifdef _LP64 3373 if (UseCompressedClassPointers) { 3374 __ encode_klass_not_null(tmp); 3375 } 3376 #endif 3377 3378 if (basic_type != T_OBJECT) { 3379 3380 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3381 else __ cmpptr(tmp, dst_klass_addr); 3382 __ jcc(Assembler::notEqual, halt); 3383 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3384 else __ cmpptr(tmp, src_klass_addr); 3385 __ jcc(Assembler::equal, known_ok); 3386 } else { 3387 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3388 else __ cmpptr(tmp, dst_klass_addr); 3389 __ jcc(Assembler::equal, known_ok); 3390 __ cmpptr(src, dst); 3391 __ jcc(Assembler::equal, known_ok); 3392 } 3393 __ bind(halt); 3394 __ stop("incorrect type information in arraycopy"); 3395 __ bind(known_ok); 3396 } 3397 #endif 3398 3399 #ifndef PRODUCT 3400 if (PrintC1Statistics) { 3401 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3402 } 3403 #endif 3404 3405 #ifdef _LP64 3406 assert_different_registers(c_rarg0, dst, dst_pos, length); 3407 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3408 assert_different_registers(c_rarg1, length); 3409 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3410 __ mov(c_rarg2, length); 3411 3412 #else 3413 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3414 store_parameter(tmp, 0); 3415 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3416 store_parameter(tmp, 1); 3417 store_parameter(length, 2); 3418 #endif // _LP64 3419 3420 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3421 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3422 const char *name; 3423 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3424 __ call_VM_leaf(entry, 0); 3425 3426 __ bind(*stub->continuation()); 3427 } 3428 3429 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3430 assert(op->crc()->is_single_cpu(), "crc must be register"); 3431 assert(op->val()->is_single_cpu(), "byte value must be register"); 3432 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3433 Register crc = op->crc()->as_register(); 3434 Register val = op->val()->as_register(); 3435 Register res = op->result_opr()->as_register(); 3436 3437 assert_different_registers(val, crc, res); 3438 3439 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3440 __ notl(crc); // ~crc 3441 __ update_byte_crc32(crc, val, res); 3442 __ notl(crc); // ~crc 3443 __ mov(res, crc); 3444 } 3445 3446 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3447 Register obj = op->obj_opr()->as_register(); // may not be an oop 3448 Register hdr = op->hdr_opr()->as_register(); 3449 Register lock = op->lock_opr()->as_register(); 3450 if (!UseFastLocking) { 3451 __ jmp(*op->stub()->entry()); 3452 } else if (op->code() == lir_lock) { 3453 Register scratch = noreg; 3454 if (UseBiasedLocking) { 3455 scratch = op->scratch_opr()->as_register(); 3456 } 3457 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3458 // add debug info for NullPointerException only if one is possible 3459 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3460 if (op->info() != NULL) { 3461 add_debug_info_for_null_check(null_check_offset, op->info()); 3462 } 3463 // done 3464 } else if (op->code() == lir_unlock) { 3465 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3466 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3467 } else { 3468 Unimplemented(); 3469 } 3470 __ bind(*op->stub()->continuation()); 3471 } 3472 3473 3474 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3475 ciMethod* method = op->profiled_method(); 3476 int bci = op->profiled_bci(); 3477 ciMethod* callee = op->profiled_callee(); 3478 3479 // Update counter for all call types 3480 ciMethodData* md = method->method_data_or_null(); 3481 assert(md != NULL, "Sanity"); 3482 ciProfileData* data = md->bci_to_data(bci); 3483 assert(data->is_CounterData(), "need CounterData for calls"); 3484 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3485 Register mdo = op->mdo()->as_register(); 3486 __ mov_metadata(mdo, md->constant_encoding()); 3487 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3488 Bytecodes::Code bc = method->java_code_at_bci(bci); 3489 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 3490 // Perform additional virtual call profiling for invokevirtual and 3491 // invokeinterface bytecodes 3492 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3493 !callee_is_static && // required for optimized MH invokes 3494 C1ProfileVirtualCalls) { 3495 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3496 Register recv = op->recv()->as_register(); 3497 assert_different_registers(mdo, recv); 3498 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3499 ciKlass* known_klass = op->known_holder(); 3500 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3501 // We know the type that will be seen at this call site; we can 3502 // statically update the MethodData* rather than needing to do 3503 // dynamic tests on the receiver type 3504 3505 // NOTE: we should probably put a lock around this search to 3506 // avoid collisions by concurrent compilations 3507 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3508 uint i; 3509 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3510 ciKlass* receiver = vc_data->receiver(i); 3511 if (known_klass->equals(receiver)) { 3512 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3513 __ addptr(data_addr, DataLayout::counter_increment); 3514 return; 3515 } 3516 } 3517 3518 // Receiver type not found in profile data; select an empty slot 3519 3520 // Note that this is less efficient than it should be because it 3521 // always does a write to the receiver part of the 3522 // VirtualCallData rather than just the first time 3523 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3524 ciKlass* receiver = vc_data->receiver(i); 3525 if (receiver == NULL) { 3526 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3527 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3528 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3529 __ addptr(data_addr, DataLayout::counter_increment); 3530 return; 3531 } 3532 } 3533 } else { 3534 __ load_klass(recv, recv); 3535 Label update_done; 3536 type_profile_helper(mdo, md, data, recv, &update_done); 3537 // Receiver did not match any saved receiver and there is no empty row for it. 3538 // Increment total counter to indicate polymorphic case. 3539 __ addptr(counter_addr, DataLayout::counter_increment); 3540 3541 __ bind(update_done); 3542 } 3543 } else { 3544 // Static call 3545 __ addptr(counter_addr, DataLayout::counter_increment); 3546 } 3547 } 3548 3549 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3550 Register obj = op->obj()->as_register(); 3551 Register tmp = op->tmp()->as_pointer_register(); 3552 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3553 ciKlass* exact_klass = op->exact_klass(); 3554 intptr_t current_klass = op->current_klass(); 3555 bool not_null = op->not_null(); 3556 bool no_conflict = op->no_conflict(); 3557 3558 Label update, next, none; 3559 3560 bool do_null = !not_null; 3561 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3562 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3563 3564 assert(do_null || do_update, "why are we here?"); 3565 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3566 3567 __ verify_oop(obj); 3568 3569 if (tmp != obj) { 3570 __ mov(tmp, obj); 3571 } 3572 if (do_null) { 3573 __ testptr(tmp, tmp); 3574 __ jccb(Assembler::notZero, update); 3575 if (!TypeEntries::was_null_seen(current_klass)) { 3576 __ orptr(mdo_addr, TypeEntries::null_seen); 3577 } 3578 if (do_update) { 3579 #ifndef ASSERT 3580 __ jmpb(next); 3581 } 3582 #else 3583 __ jmp(next); 3584 } 3585 } else { 3586 __ testptr(tmp, tmp); 3587 __ jccb(Assembler::notZero, update); 3588 __ stop("unexpect null obj"); 3589 #endif 3590 } 3591 3592 __ bind(update); 3593 3594 if (do_update) { 3595 #ifdef ASSERT 3596 if (exact_klass != NULL) { 3597 Label ok; 3598 __ load_klass(tmp, tmp); 3599 __ push(tmp); 3600 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3601 __ cmpptr(tmp, Address(rsp, 0)); 3602 __ jccb(Assembler::equal, ok); 3603 __ stop("exact klass and actual klass differ"); 3604 __ bind(ok); 3605 __ pop(tmp); 3606 } 3607 #endif 3608 if (!no_conflict) { 3609 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3610 if (exact_klass != NULL) { 3611 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3612 } else { 3613 __ load_klass(tmp, tmp); 3614 } 3615 3616 __ xorptr(tmp, mdo_addr); 3617 __ testptr(tmp, TypeEntries::type_klass_mask); 3618 // klass seen before, nothing to do. The unknown bit may have been 3619 // set already but no need to check. 3620 __ jccb(Assembler::zero, next); 3621 3622 __ testptr(tmp, TypeEntries::type_unknown); 3623 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3624 3625 if (TypeEntries::is_type_none(current_klass)) { 3626 __ cmpptr(mdo_addr, 0); 3627 __ jccb(Assembler::equal, none); 3628 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3629 __ jccb(Assembler::equal, none); 3630 // There is a chance that the checks above (re-reading profiling 3631 // data from memory) fail if another thread has just set the 3632 // profiling to this obj's klass 3633 __ xorptr(tmp, mdo_addr); 3634 __ testptr(tmp, TypeEntries::type_klass_mask); 3635 __ jccb(Assembler::zero, next); 3636 } 3637 } else { 3638 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3639 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3640 3641 __ movptr(tmp, mdo_addr); 3642 __ testptr(tmp, TypeEntries::type_unknown); 3643 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3644 } 3645 3646 // different than before. Cannot keep accurate profile. 3647 __ orptr(mdo_addr, TypeEntries::type_unknown); 3648 3649 if (TypeEntries::is_type_none(current_klass)) { 3650 __ jmpb(next); 3651 3652 __ bind(none); 3653 // first time here. Set profile type. 3654 __ movptr(mdo_addr, tmp); 3655 } 3656 } else { 3657 // There's a single possible klass at this profile point 3658 assert(exact_klass != NULL, "should be"); 3659 if (TypeEntries::is_type_none(current_klass)) { 3660 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3661 __ xorptr(tmp, mdo_addr); 3662 __ testptr(tmp, TypeEntries::type_klass_mask); 3663 #ifdef ASSERT 3664 __ jcc(Assembler::zero, next); 3665 3666 { 3667 Label ok; 3668 __ push(tmp); 3669 __ cmpptr(mdo_addr, 0); 3670 __ jcc(Assembler::equal, ok); 3671 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3672 __ jcc(Assembler::equal, ok); 3673 // may have been set by another thread 3674 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3675 __ xorptr(tmp, mdo_addr); 3676 __ testptr(tmp, TypeEntries::type_mask); 3677 __ jcc(Assembler::zero, ok); 3678 3679 __ stop("unexpected profiling mismatch"); 3680 __ bind(ok); 3681 __ pop(tmp); 3682 } 3683 #else 3684 __ jccb(Assembler::zero, next); 3685 #endif 3686 // first time here. Set profile type. 3687 __ movptr(mdo_addr, tmp); 3688 } else { 3689 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3690 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3691 3692 __ movptr(tmp, mdo_addr); 3693 __ testptr(tmp, TypeEntries::type_unknown); 3694 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3695 3696 __ orptr(mdo_addr, TypeEntries::type_unknown); 3697 } 3698 } 3699 3700 __ bind(next); 3701 } 3702 } 3703 3704 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3705 Unimplemented(); 3706 } 3707 3708 3709 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3710 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3711 } 3712 3713 3714 void LIR_Assembler::align_backward_branch_target() { 3715 __ align(BytesPerWord); 3716 } 3717 3718 3719 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3720 if (left->is_single_cpu()) { 3721 __ negl(left->as_register()); 3722 move_regs(left->as_register(), dest->as_register()); 3723 3724 } else if (left->is_double_cpu()) { 3725 Register lo = left->as_register_lo(); 3726 #ifdef _LP64 3727 Register dst = dest->as_register_lo(); 3728 __ movptr(dst, lo); 3729 __ negptr(dst); 3730 #else 3731 Register hi = left->as_register_hi(); 3732 __ lneg(hi, lo); 3733 if (dest->as_register_lo() == hi) { 3734 assert(dest->as_register_hi() != lo, "destroying register"); 3735 move_regs(hi, dest->as_register_hi()); 3736 move_regs(lo, dest->as_register_lo()); 3737 } else { 3738 move_regs(lo, dest->as_register_lo()); 3739 move_regs(hi, dest->as_register_hi()); 3740 } 3741 #endif // _LP64 3742 3743 } else if (dest->is_single_xmm()) { 3744 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3745 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3746 } 3747 if (UseAVX > 0) { 3748 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3749 ExternalAddress((address)float_signflip_pool)); 3750 } else { 3751 __ xorps(dest->as_xmm_float_reg(), 3752 ExternalAddress((address)float_signflip_pool)); 3753 } 3754 } else if (dest->is_double_xmm()) { 3755 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3756 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3757 } 3758 if (UseAVX > 0) { 3759 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3760 ExternalAddress((address)double_signflip_pool)); 3761 } else { 3762 __ xorpd(dest->as_xmm_double_reg(), 3763 ExternalAddress((address)double_signflip_pool)); 3764 } 3765 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3766 assert(left->fpu() == 0, "arg must be on TOS"); 3767 assert(dest->fpu() == 0, "dest must be TOS"); 3768 __ fchs(); 3769 3770 } else { 3771 ShouldNotReachHere(); 3772 } 3773 } 3774 3775 3776 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3777 assert(addr->is_address() && dest->is_register(), "check"); 3778 Register reg; 3779 reg = dest->as_pointer_register(); 3780 __ lea(reg, as_Address(addr->as_address_ptr())); 3781 } 3782 3783 3784 3785 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3786 assert(!tmp->is_valid(), "don't need temporary"); 3787 __ call(RuntimeAddress(dest)); 3788 if (info != NULL) { 3789 add_call_info_here(info); 3790 } 3791 } 3792 3793 3794 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3795 assert(type == T_LONG, "only for volatile long fields"); 3796 3797 if (info != NULL) { 3798 add_debug_info_for_null_check_here(info); 3799 } 3800 3801 if (src->is_double_xmm()) { 3802 if (dest->is_double_cpu()) { 3803 #ifdef _LP64 3804 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3805 #else 3806 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3807 __ psrlq(src->as_xmm_double_reg(), 32); 3808 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3809 #endif // _LP64 3810 } else if (dest->is_double_stack()) { 3811 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3812 } else if (dest->is_address()) { 3813 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3814 } else { 3815 ShouldNotReachHere(); 3816 } 3817 3818 } else if (dest->is_double_xmm()) { 3819 if (src->is_double_stack()) { 3820 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3821 } else if (src->is_address()) { 3822 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3823 } else { 3824 ShouldNotReachHere(); 3825 } 3826 3827 } else if (src->is_double_fpu()) { 3828 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3829 if (dest->is_double_stack()) { 3830 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3831 } else if (dest->is_address()) { 3832 __ fistp_d(as_Address(dest->as_address_ptr())); 3833 } else { 3834 ShouldNotReachHere(); 3835 } 3836 3837 } else if (dest->is_double_fpu()) { 3838 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3839 if (src->is_double_stack()) { 3840 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3841 } else if (src->is_address()) { 3842 __ fild_d(as_Address(src->as_address_ptr())); 3843 } else { 3844 ShouldNotReachHere(); 3845 } 3846 } else { 3847 ShouldNotReachHere(); 3848 } 3849 } 3850 3851 #ifdef ASSERT 3852 // emit run-time assertion 3853 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3854 assert(op->code() == lir_assert, "must be"); 3855 3856 if (op->in_opr1()->is_valid()) { 3857 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3858 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3859 } else { 3860 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3861 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3862 } 3863 3864 Label ok; 3865 if (op->condition() != lir_cond_always) { 3866 Assembler::Condition acond = Assembler::zero; 3867 switch (op->condition()) { 3868 case lir_cond_equal: acond = Assembler::equal; break; 3869 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3870 case lir_cond_less: acond = Assembler::less; break; 3871 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3872 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3873 case lir_cond_greater: acond = Assembler::greater; break; 3874 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3875 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3876 default: ShouldNotReachHere(); 3877 } 3878 __ jcc(acond, ok); 3879 } 3880 if (op->halt()) { 3881 const char* str = __ code_string(op->msg()); 3882 __ stop(str); 3883 } else { 3884 breakpoint(); 3885 } 3886 __ bind(ok); 3887 } 3888 #endif 3889 3890 void LIR_Assembler::membar() { 3891 // QQQ sparc TSO uses this, 3892 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3893 } 3894 3895 void LIR_Assembler::membar_acquire() { 3896 // No x86 machines currently require load fences 3897 } 3898 3899 void LIR_Assembler::membar_release() { 3900 // No x86 machines currently require store fences 3901 } 3902 3903 void LIR_Assembler::membar_loadload() { 3904 // no-op 3905 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3906 } 3907 3908 void LIR_Assembler::membar_storestore() { 3909 // no-op 3910 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3911 } 3912 3913 void LIR_Assembler::membar_loadstore() { 3914 // no-op 3915 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3916 } 3917 3918 void LIR_Assembler::membar_storeload() { 3919 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3920 } 3921 3922 void LIR_Assembler::on_spin_wait() { 3923 __ pause (); 3924 } 3925 3926 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3927 assert(result_reg->is_register(), "check"); 3928 #ifdef _LP64 3929 // __ get_thread(result_reg->as_register_lo()); 3930 __ mov(result_reg->as_register(), r15_thread); 3931 #else 3932 __ get_thread(result_reg->as_register()); 3933 #endif // _LP64 3934 } 3935 3936 3937 void LIR_Assembler::peephole(LIR_List*) { 3938 // do nothing for now 3939 } 3940 3941 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3942 assert(data == dest, "xchg/xadd uses only 2 operands"); 3943 3944 if (data->type() == T_INT) { 3945 if (code == lir_xadd) { 3946 if (os::is_MP()) { 3947 __ lock(); 3948 } 3949 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3950 } else { 3951 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3952 } 3953 } else if (data->is_oop()) { 3954 assert (code == lir_xchg, "xadd for oops"); 3955 Register obj = data->as_register(); 3956 #ifdef _LP64 3957 if (UseCompressedOops) { 3958 __ encode_heap_oop(obj); 3959 __ xchgl(obj, as_Address(src->as_address_ptr())); 3960 __ decode_heap_oop(obj); 3961 } else { 3962 __ xchgptr(obj, as_Address(src->as_address_ptr())); 3963 } 3964 #else 3965 __ xchgl(obj, as_Address(src->as_address_ptr())); 3966 #endif 3967 } else if (data->type() == T_LONG) { 3968 #ifdef _LP64 3969 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 3970 if (code == lir_xadd) { 3971 if (os::is_MP()) { 3972 __ lock(); 3973 } 3974 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 3975 } else { 3976 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 3977 } 3978 #else 3979 ShouldNotReachHere(); 3980 #endif 3981 } else { 3982 ShouldNotReachHere(); 3983 } 3984 } 3985 3986 #undef __