63 uint ireg = def->ideal_reg();
64 if (ireg == 0 || ireg == Op_RegFlags) {
65 assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %u, spill_type: %s",
66 def->_idx, def->Name(), use->_idx, use->Name(), ireg,
67 MachSpillCopyNode::spill_type(spill_type));
68 C->record_method_not_compilable("attempted to spill a non-spillable item");
69 return NULL;
70 }
71 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
72 return NULL;
73 }
74 const RegMask *i_mask = &def->out_RegMask();
75 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
76 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
77 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
78 const RegMask *w_o_mask;
79
80 int num_regs = RegMask::num_registers(ireg);
81 bool is_vect = RegMask::is_vector(ireg);
82 if( w_mask->overlap( *o_mask ) && // Overlap AND
83 ((num_regs == 1) // Single use or aligned
84 || is_vect // or vector
85 || !is_vect && o_mask->is_aligned_pairs()) ) {
86 assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
87 // Don't come here for mis-aligned doubles
88 w_o_mask = w_mask;
89 } else { // wide ideal mask does not overlap with o_mask
90 // Mis-aligned doubles come here and XMM->FPR moves on x86.
91 w_o_mask = o_mask; // Must target desired registers
92 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
93 // a reg-reg move or do I need a trip across register classes
94 // (and thus through memory)?
95 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
96 // Here we assume a trip through memory is required.
97 w_i_mask = &C->FIRST_STACK_mask();
98 }
99 return new MachSpillCopyNode(spill_type, def, *w_i_mask, *w_o_mask );
100 }
101
102 //------------------------------insert_proj------------------------------------
103 // Insert the spill at chosen location. Skip over any intervening Proj's or
104 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
105 // instead. Update high-pressure indices. Create a new live range.
1016 // this hack is only allowed for debug info which is Java state
1017 // and therefore never a derived pointer.)
1018 continue;
1019 }
1020 }
1021 // Grab register mask info
1022 const RegMask &dmask = def->out_RegMask();
1023 const RegMask &umask = n->in_RegMask(inpidx);
1024 bool is_vect = RegMask::is_vector(def->ideal_reg());
1025 assert(inpidx < oopoff, "cannot use-split oop map info");
1026
1027 bool dup = UPblock[slidx];
1028 bool uup = umask.is_UP();
1029
1030 // Need special logic to handle bound USES. Insert a split at this
1031 // bound use if we can't rematerialize the def, or if we need the
1032 // split to form a misaligned pair.
1033 if( !umask.is_AllStack() &&
1034 (int)umask.Size() <= lrgs(useidx).num_regs() &&
1035 (!def->rematerialize() ||
1036 !is_vect && umask.is_misaligned_pair())) {
1037 // These need a Split regardless of overlap or pressure
1038 // SPLIT - NO DEF - NO CISC SPILL
1039 maxlrg = split_USE(MachSpillCopyNode::Bound, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1040 // If it wasn't split bail
1041 if (!maxlrg) {
1042 return 0;
1043 }
1044 insidx++; // Reset iterator to skip USE side split
1045 continue;
1046 }
1047
1048 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
1049 // The use at the call can force the def down so insert
1050 // a split before the use to allow the def more freedom.
1051 maxlrg = split_USE(MachSpillCopyNode::CallUse, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1052 // If it wasn't split bail
1053 if (!maxlrg) {
1054 return 0;
1055 }
1056 insidx++; // Reset iterator to skip USE side split
1171 // ********** Handle DEFS **********
1172 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1173 // just reset the Reaches info in LRP regions. DEFS must always update
1174 // UP info.
1175 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1176 uint slidx = lrg2reach[defidx];
1177 // Add to defs list for later assignment of new live range number
1178 defs->push(n);
1179 // Set a flag on the Node indicating it has already spilled.
1180 // Only do it for capacity spills not conflict spills.
1181 if( !deflrg._direct_conflict )
1182 set_was_spilled(n);
1183 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1184 // Grab UP info for DEF
1185 const RegMask &dmask = n->out_RegMask();
1186 bool defup = dmask.is_UP();
1187 uint ireg = n->ideal_reg();
1188 bool is_vect = RegMask::is_vector(ireg);
1189 // Only split at Def if this is a HRP block or bound (and spilled once)
1190 if( !n->rematerialize() &&
1191 (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) &&
1192 (deflrg._direct_conflict || deflrg._must_spill)) ||
1193 // Check for LRG being up in a register and we are inside a high
1194 // pressure area. Spill it down immediately.
1195 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1196 assert( !n->rematerialize(), "" );
1197 assert( !n->is_SpillCopy(), "" );
1198 // Do a split at the def site.
1199 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1200 // If it wasn't split bail
1201 if (!maxlrg) {
1202 return 0;
1203 }
1204 // Split DEF's Down
1205 UPblock[slidx] = 0;
1206 #ifndef PRODUCT
1207 // DEBUG
1208 if( trace_spilling() ) {
1209 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1210 tty->print("%d, UP %d:\n",slidx,false);
1211 n->dump();
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63 uint ireg = def->ideal_reg();
64 if (ireg == 0 || ireg == Op_RegFlags) {
65 assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %u, spill_type: %s",
66 def->_idx, def->Name(), use->_idx, use->Name(), ireg,
67 MachSpillCopyNode::spill_type(spill_type));
68 C->record_method_not_compilable("attempted to spill a non-spillable item");
69 return NULL;
70 }
71 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
72 return NULL;
73 }
74 const RegMask *i_mask = &def->out_RegMask();
75 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
76 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
77 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
78 const RegMask *w_o_mask;
79
80 int num_regs = RegMask::num_registers(ireg);
81 bool is_vect = RegMask::is_vector(ireg);
82 if( w_mask->overlap( *o_mask ) && // Overlap AND
83 (num_regs == 1 // Single use or aligned
84 || is_vect // or vector
85 || (!is_vect && o_mask->is_aligned_pairs())) ) {
86 assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
87 // Don't come here for mis-aligned doubles
88 w_o_mask = w_mask;
89 } else { // wide ideal mask does not overlap with o_mask
90 // Mis-aligned doubles come here and XMM->FPR moves on x86.
91 w_o_mask = o_mask; // Must target desired registers
92 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
93 // a reg-reg move or do I need a trip across register classes
94 // (and thus through memory)?
95 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
96 // Here we assume a trip through memory is required.
97 w_i_mask = &C->FIRST_STACK_mask();
98 }
99 return new MachSpillCopyNode(spill_type, def, *w_i_mask, *w_o_mask );
100 }
101
102 //------------------------------insert_proj------------------------------------
103 // Insert the spill at chosen location. Skip over any intervening Proj's or
104 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
105 // instead. Update high-pressure indices. Create a new live range.
1016 // this hack is only allowed for debug info which is Java state
1017 // and therefore never a derived pointer.)
1018 continue;
1019 }
1020 }
1021 // Grab register mask info
1022 const RegMask &dmask = def->out_RegMask();
1023 const RegMask &umask = n->in_RegMask(inpidx);
1024 bool is_vect = RegMask::is_vector(def->ideal_reg());
1025 assert(inpidx < oopoff, "cannot use-split oop map info");
1026
1027 bool dup = UPblock[slidx];
1028 bool uup = umask.is_UP();
1029
1030 // Need special logic to handle bound USES. Insert a split at this
1031 // bound use if we can't rematerialize the def, or if we need the
1032 // split to form a misaligned pair.
1033 if( !umask.is_AllStack() &&
1034 (int)umask.Size() <= lrgs(useidx).num_regs() &&
1035 (!def->rematerialize() ||
1036 (!is_vect && umask.is_misaligned_pair()))) {
1037 // These need a Split regardless of overlap or pressure
1038 // SPLIT - NO DEF - NO CISC SPILL
1039 maxlrg = split_USE(MachSpillCopyNode::Bound, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1040 // If it wasn't split bail
1041 if (!maxlrg) {
1042 return 0;
1043 }
1044 insidx++; // Reset iterator to skip USE side split
1045 continue;
1046 }
1047
1048 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
1049 // The use at the call can force the def down so insert
1050 // a split before the use to allow the def more freedom.
1051 maxlrg = split_USE(MachSpillCopyNode::CallUse, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1052 // If it wasn't split bail
1053 if (!maxlrg) {
1054 return 0;
1055 }
1056 insidx++; // Reset iterator to skip USE side split
1171 // ********** Handle DEFS **********
1172 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1173 // just reset the Reaches info in LRP regions. DEFS must always update
1174 // UP info.
1175 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1176 uint slidx = lrg2reach[defidx];
1177 // Add to defs list for later assignment of new live range number
1178 defs->push(n);
1179 // Set a flag on the Node indicating it has already spilled.
1180 // Only do it for capacity spills not conflict spills.
1181 if( !deflrg._direct_conflict )
1182 set_was_spilled(n);
1183 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1184 // Grab UP info for DEF
1185 const RegMask &dmask = n->out_RegMask();
1186 bool defup = dmask.is_UP();
1187 uint ireg = n->ideal_reg();
1188 bool is_vect = RegMask::is_vector(ireg);
1189 // Only split at Def if this is a HRP block or bound (and spilled once)
1190 if( !n->rematerialize() &&
1191 (((dmask.is_bound(ireg) || (!is_vect && dmask.is_misaligned_pair())) &&
1192 (deflrg._direct_conflict || deflrg._must_spill)) ||
1193 // Check for LRG being up in a register and we are inside a high
1194 // pressure area. Spill it down immediately.
1195 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1196 assert( !n->rematerialize(), "" );
1197 assert( !n->is_SpillCopy(), "" );
1198 // Do a split at the def site.
1199 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1200 // If it wasn't split bail
1201 if (!maxlrg) {
1202 return 0;
1203 }
1204 // Split DEF's Down
1205 UPblock[slidx] = 0;
1206 #ifndef PRODUCT
1207 // DEBUG
1208 if( trace_spilling() ) {
1209 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1210 tty->print("%d, UP %d:\n",slidx,false);
1211 n->dump();
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