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src/hotspot/cpu/aarch64/assembler_aarch64.hpp

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rev 52195 : 8212043: Add floating-point Math.min/max intrinsics
Summary: Floating-point Math.min() and Math.max() intrinsics are enabled on AArch64 platform
Reviewed-by: duke


1832 
1833   // Floating-point data-processing (2 source)
1834   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1835                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1836     starti;
1837     f(op31, 31, 29);
1838     f(0b11110, 28, 24);
1839     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1840     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1841   }
1842 
1843 #define INSN(NAME, op31, type, opcode)                  \
1844   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1845     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1846   }
1847 
1848   INSN(fmuls, 0b000, 0b00, 0b0000);
1849   INSN(fdivs, 0b000, 0b00, 0b0001);
1850   INSN(fadds, 0b000, 0b00, 0b0010);
1851   INSN(fsubs, 0b000, 0b00, 0b0011);


1852   INSN(fnmuls, 0b000, 0b00, 0b1000);
1853 
1854   INSN(fmuld, 0b000, 0b01, 0b0000);
1855   INSN(fdivd, 0b000, 0b01, 0b0001);
1856   INSN(faddd, 0b000, 0b01, 0b0010);
1857   INSN(fsubd, 0b000, 0b01, 0b0011);


1858   INSN(fnmuld, 0b000, 0b01, 0b1000);
1859 
1860 #undef INSN
1861 
1862    // Floating-point data-processing (3 source)
1863   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1864                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1865                        FloatRegister Va) {
1866     starti;
1867     f(op31, 31, 29);
1868     f(0b11111, 28, 24);
1869     f(type, 23, 22), f(o1, 21), f(o0, 15);
1870     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1871   }
1872 
1873 #define INSN(NAME, op31, type, o1, o0)                                  \
1874   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1875             FloatRegister Va) {                                         \
1876     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1877   }




1832 
1833   // Floating-point data-processing (2 source)
1834   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1835                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1836     starti;
1837     f(op31, 31, 29);
1838     f(0b11110, 28, 24);
1839     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1840     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1841   }
1842 
1843 #define INSN(NAME, op31, type, opcode)                  \
1844   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1845     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1846   }
1847 
1848   INSN(fmuls, 0b000, 0b00, 0b0000);
1849   INSN(fdivs, 0b000, 0b00, 0b0001);
1850   INSN(fadds, 0b000, 0b00, 0b0010);
1851   INSN(fsubs, 0b000, 0b00, 0b0011);
1852   INSN(fmaxs, 0b000, 0b00, 0b0100);
1853   INSN(fmins, 0b000, 0b00, 0b0101);
1854   INSN(fnmuls, 0b000, 0b00, 0b1000);
1855 
1856   INSN(fmuld, 0b000, 0b01, 0b0000);
1857   INSN(fdivd, 0b000, 0b01, 0b0001);
1858   INSN(faddd, 0b000, 0b01, 0b0010);
1859   INSN(fsubd, 0b000, 0b01, 0b0011);
1860   INSN(fmaxd, 0b000, 0b01, 0b0100);
1861   INSN(fmind, 0b000, 0b01, 0b0101);
1862   INSN(fnmuld, 0b000, 0b01, 0b1000);
1863 
1864 #undef INSN
1865 
1866    // Floating-point data-processing (3 source)
1867   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1868                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1869                        FloatRegister Va) {
1870     starti;
1871     f(op31, 31, 29);
1872     f(0b11111, 28, 24);
1873     f(type, 23, 22), f(o1, 21), f(o0, 15);
1874     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1875   }
1876 
1877 #define INSN(NAME, op31, type, o1, o0)                                  \
1878   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1879             FloatRegister Va) {                                         \
1880     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1881   }
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