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src/hotspot/cpu/aarch64/assembler_aarch64.hpp

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rev 53001 : 8212043: Add floating-point Math.min/max intrinsics
Summary: Floating-point Math.min() and Math.max() intrinsics are enabled on AArch64 platform
Reviewed-by: adinn, aph


1809 
1810   // Floating-point data-processing (2 source)
1811   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1812                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1813     starti;
1814     f(op31, 31, 29);
1815     f(0b11110, 28, 24);
1816     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1817     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1818   }
1819 
1820 #define INSN(NAME, op31, type, opcode)                  \
1821   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1822     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1823   }
1824 
1825   INSN(fmuls, 0b000, 0b00, 0b0000);
1826   INSN(fdivs, 0b000, 0b00, 0b0001);
1827   INSN(fadds, 0b000, 0b00, 0b0010);
1828   INSN(fsubs, 0b000, 0b00, 0b0011);


1829   INSN(fnmuls, 0b000, 0b00, 0b1000);
1830 
1831   INSN(fmuld, 0b000, 0b01, 0b0000);
1832   INSN(fdivd, 0b000, 0b01, 0b0001);
1833   INSN(faddd, 0b000, 0b01, 0b0010);
1834   INSN(fsubd, 0b000, 0b01, 0b0011);


1835   INSN(fnmuld, 0b000, 0b01, 0b1000);
1836 
1837 #undef INSN
1838 
1839    // Floating-point data-processing (3 source)
1840   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1841                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1842                        FloatRegister Va) {
1843     starti;
1844     f(op31, 31, 29);
1845     f(0b11111, 28, 24);
1846     f(type, 23, 22), f(o1, 21), f(o0, 15);
1847     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1848   }
1849 
1850 #define INSN(NAME, op31, type, o1, o0)                                  \
1851   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1852             FloatRegister Va) {                                         \
1853     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1854   }




1809 
1810   // Floating-point data-processing (2 source)
1811   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1812                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1813     starti;
1814     f(op31, 31, 29);
1815     f(0b11110, 28, 24);
1816     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1817     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1818   }
1819 
1820 #define INSN(NAME, op31, type, opcode)                  \
1821   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1822     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1823   }
1824 
1825   INSN(fmuls, 0b000, 0b00, 0b0000);
1826   INSN(fdivs, 0b000, 0b00, 0b0001);
1827   INSN(fadds, 0b000, 0b00, 0b0010);
1828   INSN(fsubs, 0b000, 0b00, 0b0011);
1829   INSN(fmaxs, 0b000, 0b00, 0b0100);
1830   INSN(fmins, 0b000, 0b00, 0b0101);
1831   INSN(fnmuls, 0b000, 0b00, 0b1000);
1832 
1833   INSN(fmuld, 0b000, 0b01, 0b0000);
1834   INSN(fdivd, 0b000, 0b01, 0b0001);
1835   INSN(faddd, 0b000, 0b01, 0b0010);
1836   INSN(fsubd, 0b000, 0b01, 0b0011);
1837   INSN(fmaxd, 0b000, 0b01, 0b0100);
1838   INSN(fmind, 0b000, 0b01, 0b0101);
1839   INSN(fnmuld, 0b000, 0b01, 0b1000);
1840 
1841 #undef INSN
1842 
1843    // Floating-point data-processing (3 source)
1844   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1845                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1846                        FloatRegister Va) {
1847     starti;
1848     f(op31, 31, 29);
1849     f(0b11111, 28, 24);
1850     f(type, 23, 22), f(o1, 21), f(o0, 15);
1851     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1852   }
1853 
1854 #define INSN(NAME, op31, type, o1, o0)                                  \
1855   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1856             FloatRegister Va) {                                         \
1857     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1858   }
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