src/hotspot/cpu/aarch64/aarch64.ad

rev 53043 : 8214922: Add vectorization support for fmin/fmax
Reviewed-by: duke

*** 15750,15759 ****
--- 15750,15787 ----
               as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
    %}
    ins_pipe(pipe_class_default);
  %}
  
+ instruct reduce_max4F(vRegF dst, vRegF src1, vecX src2) %{
+   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MaxReductionV src1 src2));
+   ins_cost(INSN_COST);
+   effect(TEMP_DEF dst);
+   format %{ "fmaxv $dst, T4S, $src2\n\t"
+             "fmaxs $dst, $dst, $src1\t max reduction4F" %}
+   ins_encode %{
+     __ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
+     __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
+   %}
+   ins_pipe(pipe_class_default);
+ %}
+ 
+ instruct reduce_min4F(vRegF dst, vRegF src1, vecX src2) %{
+   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MinReductionV src1 src2));
+   ins_cost(INSN_COST);
+   effect(TEMP_DEF dst);
+   format %{ "fminv $dst, T4S, $src2\n\t"
+             "fmins $dst, $dst, $src1\t min reduction4F" %}
+   ins_encode %{
+     __ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
+     __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
+   %}
+   ins_pipe(pipe_class_default);
+ %}
+ 
  // ====================VECTOR ARITHMETIC=======================================
  
  // --------------------------------- ADD --------------------------------------
  
  instruct vadd8B(vecD dst, vecD src1, vecD src2)
*** 17124,17133 ****
--- 17152,17245 ----
              (int)$shift$$constant);
    %}
    ins_pipe(vshift128_imm);
  %}
  
+ instruct vmax2F(vecD dst, vecD src1, vecD src2)
+ %{
+   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MaxV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmax  $dst,$src1,$src2\t# vector (2F)" %}
+   ins_encode %{
+     __ fmax(as_FloatRegister($dst$$reg), __ T2S,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp64);
+ %}
+ 
+ instruct vmax4F(vecX dst, vecX src1, vecX src2)
+ %{
+   predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MaxV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmax  $dst,$src1,$src2\t# vector (4S)" %}
+   ins_encode %{
+     __ fmax(as_FloatRegister($dst$$reg), __ T4S,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp128);
+ %}
+ 
+ instruct vmax2D(vecX dst, vecX src1, vecX src2)
+ %{
+   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+   match(Set dst (MaxV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmax  $dst,$src1,$src2\t# vector (2D)" %}
+   ins_encode %{
+     __ fmax(as_FloatRegister($dst$$reg), __ T2D,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp128);
+ %}
+ 
+ instruct vmin2F(vecD dst, vecD src1, vecD src2)
+ %{
+   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MinV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmin  $dst,$src1,$src2\t# vector (2F)" %}
+   ins_encode %{
+     __ fmin(as_FloatRegister($dst$$reg), __ T2S,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp64);
+ %}
+ 
+ instruct vmin4F(vecX dst, vecX src1, vecX src2)
+ %{
+   predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+   match(Set dst (MinV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmin  $dst,$src1,$src2\t# vector (4S)" %}
+   ins_encode %{
+     __ fmin(as_FloatRegister($dst$$reg), __ T4S,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp128);
+ %}
+ 
+ instruct vmin2D(vecX dst, vecX src1, vecX src2)
+ %{
+   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+   match(Set dst (MinV src1 src2));
+   ins_cost(INSN_COST);
+   format %{ "fmin  $dst,$src1,$src2\t# vector (2D)" %}
+   ins_encode %{
+     __ fmin(as_FloatRegister($dst$$reg), __ T2D,
+             as_FloatRegister($src1$$reg),
+             as_FloatRegister($src2$$reg));
+   %}
+   ins_pipe(vdop_fp128);
+ %}
+ 
  //----------PEEPHOLE RULES-----------------------------------------------------
  // These must follow all instruction definitions as they use the names
  // defined in the instructions definitions.
  //
  // peepmatch ( root_instr_name [preceding_instruction]* );