15735 instruct reduce_mul2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
15736 %{
15737 match(Set dst (MulReductionVD src1 src2));
15738 ins_cost(INSN_COST);
15739 effect(TEMP tmp, TEMP dst);
15740 format %{ "fmuld $dst, $src1, $src2\n\t"
15741 "ins $tmp, D, $src2, 0, 1\n\t"
15742 "fmuld $dst, $dst, $tmp\t add reduction2d"
15743 %}
15744 ins_encode %{
15745 __ fmuld(as_FloatRegister($dst$$reg),
15746 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15747 __ ins(as_FloatRegister($tmp$$reg), __ D,
15748 as_FloatRegister($src2$$reg), 0, 1);
15749 __ fmuld(as_FloatRegister($dst$$reg),
15750 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15751 %}
15752 ins_pipe(pipe_class_default);
15753 %}
15754
15755 // ====================VECTOR ARITHMETIC=======================================
15756
15757 // --------------------------------- ADD --------------------------------------
15758
15759 instruct vadd8B(vecD dst, vecD src1, vecD src2)
15760 %{
15761 predicate(n->as_Vector()->length() == 4 ||
15762 n->as_Vector()->length() == 8);
15763 match(Set dst (AddVB src1 src2));
15764 ins_cost(INSN_COST);
15765 format %{ "addv $dst,$src1,$src2\t# vector (8B)" %}
15766 ins_encode %{
15767 __ addv(as_FloatRegister($dst$$reg), __ T8B,
15768 as_FloatRegister($src1$$reg),
15769 as_FloatRegister($src2$$reg));
15770 %}
15771 ins_pipe(vdop64);
15772 %}
15773
15774 instruct vadd16B(vecX dst, vecX src1, vecX src2)
17107 format %{ "sshr $dst, $src, $shift\t# vector (2D)" %}
17108 ins_encode %{
17109 __ sshr(as_FloatRegister($dst$$reg), __ T2D,
17110 as_FloatRegister($src$$reg),
17111 (int)$shift$$constant);
17112 %}
17113 ins_pipe(vshift128_imm);
17114 %}
17115
17116 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
17117 predicate(n->as_Vector()->length() == 2);
17118 match(Set dst (URShiftVL src shift));
17119 ins_cost(INSN_COST);
17120 format %{ "ushr $dst, $src, $shift\t# vector (2D)" %}
17121 ins_encode %{
17122 __ ushr(as_FloatRegister($dst$$reg), __ T2D,
17123 as_FloatRegister($src$$reg),
17124 (int)$shift$$constant);
17125 %}
17126 ins_pipe(vshift128_imm);
17127 %}
17128
17129 //----------PEEPHOLE RULES-----------------------------------------------------
17130 // These must follow all instruction definitions as they use the names
17131 // defined in the instructions definitions.
17132 //
17133 // peepmatch ( root_instr_name [preceding_instruction]* );
17134 //
17135 // peepconstraint %{
17136 // (instruction_number.operand_name relational_op instruction_number.operand_name
17137 // [, ...] );
17138 // // instruction numbers are zero-based using left to right order in peepmatch
17139 //
17140 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
17141 // // provide an instruction_number.operand_name for each operand that appears
17142 // // in the replacement instruction's match rule
17143 //
17144 // ---------VM FLAGS---------------------------------------------------------
17145 //
17146 // All peephole optimizations can be turned off using -XX:-OptoPeephole
|
15735 instruct reduce_mul2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
15736 %{
15737 match(Set dst (MulReductionVD src1 src2));
15738 ins_cost(INSN_COST);
15739 effect(TEMP tmp, TEMP dst);
15740 format %{ "fmuld $dst, $src1, $src2\n\t"
15741 "ins $tmp, D, $src2, 0, 1\n\t"
15742 "fmuld $dst, $dst, $tmp\t add reduction2d"
15743 %}
15744 ins_encode %{
15745 __ fmuld(as_FloatRegister($dst$$reg),
15746 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15747 __ ins(as_FloatRegister($tmp$$reg), __ D,
15748 as_FloatRegister($src2$$reg), 0, 1);
15749 __ fmuld(as_FloatRegister($dst$$reg),
15750 as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15751 %}
15752 ins_pipe(pipe_class_default);
15753 %}
15754
15755 instruct reduce_max4F(vRegF dst, vRegF src1, vecX src2) %{
15756 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15757 match(Set dst (MaxReductionV src1 src2));
15758 ins_cost(INSN_COST);
15759 effect(TEMP_DEF dst);
15760 format %{ "fmaxv $dst, T4S, $src2\n\t"
15761 "fmaxs $dst, $dst, $src1\t max reduction4F" %}
15762 ins_encode %{
15763 __ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
15764 __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
15765 %}
15766 ins_pipe(pipe_class_default);
15767 %}
15768
15769 instruct reduce_min4F(vRegF dst, vRegF src1, vecX src2) %{
15770 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15771 match(Set dst (MinReductionV src1 src2));
15772 ins_cost(INSN_COST);
15773 effect(TEMP_DEF dst);
15774 format %{ "fminv $dst, T4S, $src2\n\t"
15775 "fmins $dst, $dst, $src1\t min reduction4F" %}
15776 ins_encode %{
15777 __ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
15778 __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
15779 %}
15780 ins_pipe(pipe_class_default);
15781 %}
15782
15783 // ====================VECTOR ARITHMETIC=======================================
15784
15785 // --------------------------------- ADD --------------------------------------
15786
15787 instruct vadd8B(vecD dst, vecD src1, vecD src2)
15788 %{
15789 predicate(n->as_Vector()->length() == 4 ||
15790 n->as_Vector()->length() == 8);
15791 match(Set dst (AddVB src1 src2));
15792 ins_cost(INSN_COST);
15793 format %{ "addv $dst,$src1,$src2\t# vector (8B)" %}
15794 ins_encode %{
15795 __ addv(as_FloatRegister($dst$$reg), __ T8B,
15796 as_FloatRegister($src1$$reg),
15797 as_FloatRegister($src2$$reg));
15798 %}
15799 ins_pipe(vdop64);
15800 %}
15801
15802 instruct vadd16B(vecX dst, vecX src1, vecX src2)
17135 format %{ "sshr $dst, $src, $shift\t# vector (2D)" %}
17136 ins_encode %{
17137 __ sshr(as_FloatRegister($dst$$reg), __ T2D,
17138 as_FloatRegister($src$$reg),
17139 (int)$shift$$constant);
17140 %}
17141 ins_pipe(vshift128_imm);
17142 %}
17143
17144 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
17145 predicate(n->as_Vector()->length() == 2);
17146 match(Set dst (URShiftVL src shift));
17147 ins_cost(INSN_COST);
17148 format %{ "ushr $dst, $src, $shift\t# vector (2D)" %}
17149 ins_encode %{
17150 __ ushr(as_FloatRegister($dst$$reg), __ T2D,
17151 as_FloatRegister($src$$reg),
17152 (int)$shift$$constant);
17153 %}
17154 ins_pipe(vshift128_imm);
17155 %}
17156
17157 instruct vmax2F(vecD dst, vecD src1, vecD src2)
17158 %{
17159 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17160 match(Set dst (MaxV src1 src2));
17161 ins_cost(INSN_COST);
17162 format %{ "fmax $dst,$src1,$src2\t# vector (2F)" %}
17163 ins_encode %{
17164 __ fmax(as_FloatRegister($dst$$reg), __ T2S,
17165 as_FloatRegister($src1$$reg),
17166 as_FloatRegister($src2$$reg));
17167 %}
17168 ins_pipe(vdop_fp64);
17169 %}
17170
17171 instruct vmax4F(vecX dst, vecX src1, vecX src2)
17172 %{
17173 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17174 match(Set dst (MaxV src1 src2));
17175 ins_cost(INSN_COST);
17176 format %{ "fmax $dst,$src1,$src2\t# vector (4S)" %}
17177 ins_encode %{
17178 __ fmax(as_FloatRegister($dst$$reg), __ T4S,
17179 as_FloatRegister($src1$$reg),
17180 as_FloatRegister($src2$$reg));
17181 %}
17182 ins_pipe(vdop_fp128);
17183 %}
17184
17185 instruct vmax2D(vecX dst, vecX src1, vecX src2)
17186 %{
17187 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17188 match(Set dst (MaxV src1 src2));
17189 ins_cost(INSN_COST);
17190 format %{ "fmax $dst,$src1,$src2\t# vector (2D)" %}
17191 ins_encode %{
17192 __ fmax(as_FloatRegister($dst$$reg), __ T2D,
17193 as_FloatRegister($src1$$reg),
17194 as_FloatRegister($src2$$reg));
17195 %}
17196 ins_pipe(vdop_fp128);
17197 %}
17198
17199 instruct vmin2F(vecD dst, vecD src1, vecD src2)
17200 %{
17201 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17202 match(Set dst (MinV src1 src2));
17203 ins_cost(INSN_COST);
17204 format %{ "fmin $dst,$src1,$src2\t# vector (2F)" %}
17205 ins_encode %{
17206 __ fmin(as_FloatRegister($dst$$reg), __ T2S,
17207 as_FloatRegister($src1$$reg),
17208 as_FloatRegister($src2$$reg));
17209 %}
17210 ins_pipe(vdop_fp64);
17211 %}
17212
17213 instruct vmin4F(vecX dst, vecX src1, vecX src2)
17214 %{
17215 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17216 match(Set dst (MinV src1 src2));
17217 ins_cost(INSN_COST);
17218 format %{ "fmin $dst,$src1,$src2\t# vector (4S)" %}
17219 ins_encode %{
17220 __ fmin(as_FloatRegister($dst$$reg), __ T4S,
17221 as_FloatRegister($src1$$reg),
17222 as_FloatRegister($src2$$reg));
17223 %}
17224 ins_pipe(vdop_fp128);
17225 %}
17226
17227 instruct vmin2D(vecX dst, vecX src1, vecX src2)
17228 %{
17229 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17230 match(Set dst (MinV src1 src2));
17231 ins_cost(INSN_COST);
17232 format %{ "fmin $dst,$src1,$src2\t# vector (2D)" %}
17233 ins_encode %{
17234 __ fmin(as_FloatRegister($dst$$reg), __ T2D,
17235 as_FloatRegister($src1$$reg),
17236 as_FloatRegister($src2$$reg));
17237 %}
17238 ins_pipe(vdop_fp128);
17239 %}
17240
17241 //----------PEEPHOLE RULES-----------------------------------------------------
17242 // These must follow all instruction definitions as they use the names
17243 // defined in the instructions definitions.
17244 //
17245 // peepmatch ( root_instr_name [preceding_instruction]* );
17246 //
17247 // peepconstraint %{
17248 // (instruction_number.operand_name relational_op instruction_number.operand_name
17249 // [, ...] );
17250 // // instruction numbers are zero-based using left to right order in peepmatch
17251 //
17252 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
17253 // // provide an instruction_number.operand_name for each operand that appears
17254 // // in the replacement instruction's match rule
17255 //
17256 // ---------VM FLAGS---------------------------------------------------------
17257 //
17258 // All peephole optimizations can be turned off using -XX:-OptoPeephole
|