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src/hotspot/cpu/aarch64/aarch64.ad

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rev 53101 : 8214922: Add vectorization support for fmin/fmax
Reviewed-by: duke


15740 instruct reduce_mul2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
15741 %{
15742   match(Set dst (MulReductionVD src1 src2));
15743   ins_cost(INSN_COST);
15744   effect(TEMP tmp, TEMP dst);
15745   format %{ "fmuld $dst, $src1, $src2\n\t"
15746             "ins   $tmp, D, $src2, 0, 1\n\t"
15747             "fmuld $dst, $dst, $tmp\t add reduction2d"
15748   %}
15749   ins_encode %{
15750     __ fmuld(as_FloatRegister($dst$$reg),
15751              as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15752     __ ins(as_FloatRegister($tmp$$reg), __ D,
15753            as_FloatRegister($src2$$reg), 0, 1);
15754     __ fmuld(as_FloatRegister($dst$$reg),
15755              as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15756   %}
15757   ins_pipe(pipe_class_default);
15758 %}
15759 




























































































15760 // ====================VECTOR ARITHMETIC=======================================
15761 
15762 // --------------------------------- ADD --------------------------------------
15763 
15764 instruct vadd8B(vecD dst, vecD src1, vecD src2)
15765 %{
15766   predicate(n->as_Vector()->length() == 4 ||
15767             n->as_Vector()->length() == 8);
15768   match(Set dst (AddVB src1 src2));
15769   ins_cost(INSN_COST);
15770   format %{ "addv  $dst,$src1,$src2\t# vector (8B)" %}
15771   ins_encode %{
15772     __ addv(as_FloatRegister($dst$$reg), __ T8B,
15773             as_FloatRegister($src1$$reg),
15774             as_FloatRegister($src2$$reg));
15775   %}
15776   ins_pipe(vdop64);
15777 %}
15778 
15779 instruct vadd16B(vecX dst, vecX src1, vecX src2)


17276   format %{ "sshr    $dst, $src, $shift\t# vector (2D)" %}
17277   ins_encode %{
17278     __ sshr(as_FloatRegister($dst$$reg), __ T2D,
17279             as_FloatRegister($src$$reg),
17280             (int)$shift$$constant);
17281   %}
17282   ins_pipe(vshift128_imm);
17283 %}
17284 
17285 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
17286   predicate(n->as_Vector()->length() == 2);
17287   match(Set dst (URShiftVL src shift));
17288   ins_cost(INSN_COST);
17289   format %{ "ushr    $dst, $src, $shift\t# vector (2D)" %}
17290   ins_encode %{
17291     __ ushr(as_FloatRegister($dst$$reg), __ T2D,
17292             as_FloatRegister($src$$reg),
17293             (int)$shift$$constant);
17294   %}
17295   ins_pipe(vshift128_imm);




















































































17296 %}
17297 
17298 //----------PEEPHOLE RULES-----------------------------------------------------
17299 // These must follow all instruction definitions as they use the names
17300 // defined in the instructions definitions.
17301 //
17302 // peepmatch ( root_instr_name [preceding_instruction]* );
17303 //
17304 // peepconstraint %{
17305 // (instruction_number.operand_name relational_op instruction_number.operand_name
17306 //  [, ...] );
17307 // // instruction numbers are zero-based using left to right order in peepmatch
17308 //
17309 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
17310 // // provide an instruction_number.operand_name for each operand that appears
17311 // // in the replacement instruction's match rule
17312 //
17313 // ---------VM FLAGS---------------------------------------------------------
17314 //
17315 // All peephole optimizations can be turned off using -XX:-OptoPeephole




15740 instruct reduce_mul2D(vRegD dst, vRegD src1, vecX src2, vecX tmp)
15741 %{
15742   match(Set dst (MulReductionVD src1 src2));
15743   ins_cost(INSN_COST);
15744   effect(TEMP tmp, TEMP dst);
15745   format %{ "fmuld $dst, $src1, $src2\n\t"
15746             "ins   $tmp, D, $src2, 0, 1\n\t"
15747             "fmuld $dst, $dst, $tmp\t add reduction2d"
15748   %}
15749   ins_encode %{
15750     __ fmuld(as_FloatRegister($dst$$reg),
15751              as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15752     __ ins(as_FloatRegister($tmp$$reg), __ D,
15753            as_FloatRegister($src2$$reg), 0, 1);
15754     __ fmuld(as_FloatRegister($dst$$reg),
15755              as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15756   %}
15757   ins_pipe(pipe_class_default);
15758 %}
15759 
15760 instruct reduce_max2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{
15761   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15762   match(Set dst (MaxReductionV src1 src2));
15763   ins_cost(INSN_COST);
15764   effect(TEMP_DEF dst, TEMP tmp);
15765   format %{ "fmaxs $dst, $src1, $src2\n\t"
15766             "ins   $tmp, S, $src2, 0, 1\n\t"
15767             "fmaxs $dst, $dst, $tmp\t max reduction2F" %}
15768   ins_encode %{
15769     __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15770     __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1);
15771     __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15772   %}
15773   ins_pipe(pipe_class_default);
15774 %}
15775 
15776 instruct reduce_max4F(vRegF dst, vRegF src1, vecX src2) %{
15777   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15778   match(Set dst (MaxReductionV src1 src2));
15779   ins_cost(INSN_COST);
15780   effect(TEMP_DEF dst);
15781   format %{ "fmaxv $dst, T4S, $src2\n\t"
15782             "fmaxs $dst, $dst, $src1\t max reduction4F" %}
15783   ins_encode %{
15784     __ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
15785     __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
15786   %}
15787   ins_pipe(pipe_class_default);
15788 %}
15789 
15790 instruct reduce_max2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{
15791   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
15792   match(Set dst (MaxReductionV src1 src2));
15793   ins_cost(INSN_COST);
15794   effect(TEMP_DEF dst, TEMP tmp);
15795   format %{ "fmaxd $dst, $src1, $src2\n\t"
15796             "ins   $tmp, D, $src2, 0, 1\n\t"
15797             "fmaxd $dst, $dst, $tmp\t max reduction2D" %}
15798   ins_encode %{
15799     __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15800     __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1);
15801     __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15802   %}
15803   ins_pipe(pipe_class_default);
15804 %}
15805 
15806 instruct reduce_min2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{
15807   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15808   match(Set dst (MinReductionV src1 src2));
15809   ins_cost(INSN_COST);
15810   effect(TEMP_DEF dst, TEMP tmp);
15811   format %{ "fmins $dst, $src1, $src2\n\t"
15812             "ins   $tmp, S, $src2, 0, 1\n\t"
15813             "fmins $dst, $dst, $tmp\t min reduction2F" %}
15814   ins_encode %{
15815     __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15816     __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1);
15817     __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15818   %}
15819   ins_pipe(pipe_class_default);
15820 %}
15821 
15822 instruct reduce_min4F(vRegF dst, vRegF src1, vecX src2) %{
15823   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
15824   match(Set dst (MinReductionV src1 src2));
15825   ins_cost(INSN_COST);
15826   effect(TEMP_DEF dst);
15827   format %{ "fminv $dst, T4S, $src2\n\t"
15828             "fmins $dst, $dst, $src1\t min reduction4F" %}
15829   ins_encode %{
15830     __ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
15831     __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
15832   %}
15833   ins_pipe(pipe_class_default);
15834 %}
15835 
15836 instruct reduce_min2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{
15837   predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
15838   match(Set dst (MinReductionV src1 src2));
15839   ins_cost(INSN_COST);
15840   effect(TEMP_DEF dst, TEMP tmp);
15841   format %{ "fmind $dst, $src1, $src2\n\t"
15842             "ins   $tmp, D, $src2, 0, 1\n\t"
15843             "fmind $dst, $dst, $tmp\t min reduction2D" %}
15844   ins_encode %{
15845     __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15846     __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1);
15847     __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
15848   %}
15849   ins_pipe(pipe_class_default);
15850 %}
15851 
15852 // ====================VECTOR ARITHMETIC=======================================
15853 
15854 // --------------------------------- ADD --------------------------------------
15855 
15856 instruct vadd8B(vecD dst, vecD src1, vecD src2)
15857 %{
15858   predicate(n->as_Vector()->length() == 4 ||
15859             n->as_Vector()->length() == 8);
15860   match(Set dst (AddVB src1 src2));
15861   ins_cost(INSN_COST);
15862   format %{ "addv  $dst,$src1,$src2\t# vector (8B)" %}
15863   ins_encode %{
15864     __ addv(as_FloatRegister($dst$$reg), __ T8B,
15865             as_FloatRegister($src1$$reg),
15866             as_FloatRegister($src2$$reg));
15867   %}
15868   ins_pipe(vdop64);
15869 %}
15870 
15871 instruct vadd16B(vecX dst, vecX src1, vecX src2)


17368   format %{ "sshr    $dst, $src, $shift\t# vector (2D)" %}
17369   ins_encode %{
17370     __ sshr(as_FloatRegister($dst$$reg), __ T2D,
17371             as_FloatRegister($src$$reg),
17372             (int)$shift$$constant);
17373   %}
17374   ins_pipe(vshift128_imm);
17375 %}
17376 
17377 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
17378   predicate(n->as_Vector()->length() == 2);
17379   match(Set dst (URShiftVL src shift));
17380   ins_cost(INSN_COST);
17381   format %{ "ushr    $dst, $src, $shift\t# vector (2D)" %}
17382   ins_encode %{
17383     __ ushr(as_FloatRegister($dst$$reg), __ T2D,
17384             as_FloatRegister($src$$reg),
17385             (int)$shift$$constant);
17386   %}
17387   ins_pipe(vshift128_imm);
17388 %}
17389 
17390 instruct vmax2F(vecD dst, vecD src1, vecD src2)
17391 %{
17392   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17393   match(Set dst (MaxV src1 src2));
17394   ins_cost(INSN_COST);
17395   format %{ "fmax  $dst,$src1,$src2\t# vector (2F)" %}
17396   ins_encode %{
17397     __ fmax(as_FloatRegister($dst$$reg), __ T2S,
17398             as_FloatRegister($src1$$reg),
17399             as_FloatRegister($src2$$reg));
17400   %}
17401   ins_pipe(vdop_fp64);
17402 %}
17403 
17404 instruct vmax4F(vecX dst, vecX src1, vecX src2)
17405 %{
17406   predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17407   match(Set dst (MaxV src1 src2));
17408   ins_cost(INSN_COST);
17409   format %{ "fmax  $dst,$src1,$src2\t# vector (4S)" %}
17410   ins_encode %{
17411     __ fmax(as_FloatRegister($dst$$reg), __ T4S,
17412             as_FloatRegister($src1$$reg),
17413             as_FloatRegister($src2$$reg));
17414   %}
17415   ins_pipe(vdop_fp128);
17416 %}
17417 
17418 instruct vmax2D(vecX dst, vecX src1, vecX src2)
17419 %{
17420   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17421   match(Set dst (MaxV src1 src2));
17422   ins_cost(INSN_COST);
17423   format %{ "fmax  $dst,$src1,$src2\t# vector (2D)" %}
17424   ins_encode %{
17425     __ fmax(as_FloatRegister($dst$$reg), __ T2D,
17426             as_FloatRegister($src1$$reg),
17427             as_FloatRegister($src2$$reg));
17428   %}
17429   ins_pipe(vdop_fp128);
17430 %}
17431 
17432 instruct vmin2F(vecD dst, vecD src1, vecD src2)
17433 %{
17434   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17435   match(Set dst (MinV src1 src2));
17436   ins_cost(INSN_COST);
17437   format %{ "fmin  $dst,$src1,$src2\t# vector (2F)" %}
17438   ins_encode %{
17439     __ fmin(as_FloatRegister($dst$$reg), __ T2S,
17440             as_FloatRegister($src1$$reg),
17441             as_FloatRegister($src2$$reg));
17442   %}
17443   ins_pipe(vdop_fp64);
17444 %}
17445 
17446 instruct vmin4F(vecX dst, vecX src1, vecX src2)
17447 %{
17448   predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17449   match(Set dst (MinV src1 src2));
17450   ins_cost(INSN_COST);
17451   format %{ "fmin  $dst,$src1,$src2\t# vector (4S)" %}
17452   ins_encode %{
17453     __ fmin(as_FloatRegister($dst$$reg), __ T4S,
17454             as_FloatRegister($src1$$reg),
17455             as_FloatRegister($src2$$reg));
17456   %}
17457   ins_pipe(vdop_fp128);
17458 %}
17459 
17460 instruct vmin2D(vecX dst, vecX src1, vecX src2)
17461 %{
17462   predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17463   match(Set dst (MinV src1 src2));
17464   ins_cost(INSN_COST);
17465   format %{ "fmin  $dst,$src1,$src2\t# vector (2D)" %}
17466   ins_encode %{
17467     __ fmin(as_FloatRegister($dst$$reg), __ T2D,
17468             as_FloatRegister($src1$$reg),
17469             as_FloatRegister($src2$$reg));
17470   %}
17471   ins_pipe(vdop_fp128);
17472 %}
17473 
17474 //----------PEEPHOLE RULES-----------------------------------------------------
17475 // These must follow all instruction definitions as they use the names
17476 // defined in the instructions definitions.
17477 //
17478 // peepmatch ( root_instr_name [preceding_instruction]* );
17479 //
17480 // peepconstraint %{
17481 // (instruction_number.operand_name relational_op instruction_number.operand_name
17482 //  [, ...] );
17483 // // instruction numbers are zero-based using left to right order in peepmatch
17484 //
17485 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
17486 // // provide an instruction_number.operand_name for each operand that appears
17487 // // in the replacement instruction's match rule
17488 //
17489 // ---------VM FLAGS---------------------------------------------------------
17490 //
17491 // All peephole optimizations can be turned off using -XX:-OptoPeephole


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