src/hotspot/cpu/aarch64/assembler_aarch64.hpp

rev 53101 : 8214922: Add vectorization support for fmin/fmax
Reviewed-by: duke

*** 2235,2244 ****
--- 2235,2257 ----
    INSN(clz,   1, 0b100000010010);
    INSN(cnt,   0, 0b100000010110);
  
  #undef INSN
  
+ #define INSN(NAME, opc) \
+   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                  \
+     starti;                                                                            \
+     assert(T == T4S, "arrangement must be T4S");                                       \
+     f(0b01101110, 31, 24), f(opc, 23), f(0b0110000111110, 22, 10);                     \
+     rf(Vn, 5), rf(Vd, 0);                                                              \
+   }
+ 
+   INSN(fmaxv, 0);
+   INSN(fminv, 1);
+ 
+ #undef INSN
+ 
  #define INSN(NAME, op0, cmode0) \
    void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
      unsigned cmode = cmode0;                                                           \
      unsigned op = op0;                                                                 \
      starti;                                                                            \
*** 2276,2285 ****
--- 2289,2300 ----
    INSN(fdiv, 1, 0, 0b111111);
    INSN(fmul, 1, 0, 0b110111);
    INSN(fsub, 0, 1, 0b110101);
    INSN(fmla, 0, 0, 0b110011);
    INSN(fmls, 0, 1, 0b110011);
+   INSN(fmax, 0, 0, 0b111101);
+   INSN(fmin, 0, 1, 0b111101);
  
  #undef INSN
  
  #define INSN(NAME, opc)                                                                 \
    void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \