1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (2 * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
349 __ nop();
350 }
351 }
352 int offset = __ offset();
353 __ inline_cache_check(receiver, IC_Klass);
354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
355 if (do_post_padding) {
356 // force alignment after the cache check.
357 // It's been verified to be aligned if !VerifyOops
358 __ align(CodeEntryAlignment);
359 }
360 return offset;
361 }
362
363
364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 jobject o = NULL;
366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
367 __ movoop(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
372 Metadata* o = NULL;
373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
374 __ mov_metadata(reg, o);
375 patching_epilog(patch, lir_patch_normal, reg, info);
376 }
377
378 // This specifies the rsp decrement needed to build the frame
379 int LIR_Assembler::initial_frame_size_in_bytes() const {
380 // if rounding, must let FrameMap know!
381
382 // The frame_map records size in slots (32bit word)
383
384 // subtract two words to account for return address and link
385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
386 }
387
388
389 int LIR_Assembler::emit_exception_handler() {
390 // if the last instruction is a call (typically to do a throw which
391 // is coming at the end after block reordering) the return address
392 // must still point into the code area in order to avoid assertion
393 // failures when searching for the corresponding bci => add a nop
394 // (was bug 5/14/1999 - gri)
395 __ nop();
396
397 // generate code for exception handler
398 address handler_base = __ start_a_stub(exception_handler_size);
399 if (handler_base == NULL) {
400 // not enough space left for the handler
401 bailout("exception handler overflow");
402 return -1;
403 }
404
405 int offset = code_offset();
406
407 // the exception oop and pc are in rax, and rdx
408 // no other registers need to be preserved, so invalidate them
409 __ invalidate_registers(false, true, true, false, true, true);
410
411 // check that there is really an exception
412 __ verify_not_null_oop(rax);
413
414 // search an exception handler (rax: exception oop, rdx: throwing pc)
415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
416 __ should_not_reach_here();
417 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
418 __ end_a_stub();
419
420 return offset;
421 }
422
423
424 // Emit the code to remove the frame from the stack in the exception
425 // unwind path.
426 int LIR_Assembler::emit_unwind_handler() {
427 #ifndef PRODUCT
428 if (CommentedAssembly) {
429 _masm->block_comment("Unwind handler");
430 }
431 #endif
432
433 int offset = code_offset();
434
435 // Fetch the exception from TLS and clear out exception related thread state
436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
437 NOT_LP64(__ get_thread(rsi));
438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
441
442 __ bind(_unwind_handler_entry);
443 __ verify_not_null_oop(rax);
444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
446 }
447
448 // Preform needed unlocking
449 MonitorExitStub* stub = NULL;
450 if (method()->is_synchronized()) {
451 monitor_address(0, FrameMap::rax_opr);
452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
453 __ unlock_object(rdi, rsi, rax, *stub->entry());
454 __ bind(*stub->continuation());
455 }
456
457 if (compilation()->env()->dtrace_method_probes()) {
458 #ifdef _LP64
459 __ mov(rdi, r15_thread);
460 __ mov_metadata(rsi, method()->constant_encoding());
461 #else
462 __ get_thread(rax);
463 __ movptr(Address(rsp, 0), rax);
464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
465 #endif
466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
467 }
468
469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
470 __ mov(rax, rbx); // Restore the exception
471 }
472
473 // remove the activation and dispatch to the unwind handler
474 __ remove_frame(initial_frame_size_in_bytes());
475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
476
477 // Emit the slow path assembly
478 if (stub != NULL) {
479 stub->emit_code(this);
480 }
481
482 return offset;
483 }
484
485
486 int LIR_Assembler::emit_deopt_handler() {
487 // if the last instruction is a call (typically to do a throw which
488 // is coming at the end after block reordering) the return address
489 // must still point into the code area in order to avoid assertion
490 // failures when searching for the corresponding bci => add a nop
491 // (was bug 5/14/1999 - gri)
492 __ nop();
493
494 // generate code for exception handler
495 address handler_base = __ start_a_stub(deopt_handler_size);
496 if (handler_base == NULL) {
497 // not enough space left for the handler
498 bailout("deopt handler overflow");
499 return -1;
500 }
501
502 int offset = code_offset();
503 InternalAddress here(__ pc());
504
505 __ pushptr(here.addr());
506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
507 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
508 __ end_a_stub();
509
510 return offset;
511 }
512
513
514 // This is the fast version of java.lang.String.compare; it has not
515 // OSR-entry and therefore, we generate a slow version for OSR's
516 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
517 __ movptr (rbx, rcx); // receiver is in rcx
518 __ movptr (rax, arg1->as_register());
519
520 // Get addresses of first characters from both Strings
521 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
522 if (java_lang_String::has_offset_field()) {
523 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
524 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
525 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
526 } else {
527 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
528 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
529 }
530
531 // rbx, may be NULL
532 add_debug_info_for_null_check_here(info);
533 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
534 if (java_lang_String::has_offset_field()) {
535 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
536 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
537 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
538 } else {
539 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
540 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
541 }
542
543 // compute minimum length (in rax) and difference of lengths (on top of stack)
544 __ mov (rcx, rbx);
545 __ subptr(rbx, rax); // subtract lengths
546 __ push (rbx); // result
547 __ cmov (Assembler::lessEqual, rax, rcx);
548
549 // is minimum length 0?
550 Label noLoop, haveResult;
551 __ testptr (rax, rax);
552 __ jcc (Assembler::zero, noLoop);
553
554 // compare first characters
555 __ load_unsigned_short(rcx, Address(rdi, 0));
556 __ load_unsigned_short(rbx, Address(rsi, 0));
557 __ subl(rcx, rbx);
558 __ jcc(Assembler::notZero, haveResult);
559 // starting loop
560 __ decrement(rax); // we already tested index: skip one
561 __ jcc(Assembler::zero, noLoop);
562
563 // set rsi.edi to the end of the arrays (arrays have same length)
564 // negate the index
565
566 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
567 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
568 __ negptr(rax);
569
570 // compare the strings in a loop
571
572 Label loop;
573 __ align(wordSize);
574 __ bind(loop);
575 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
576 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
577 __ subl(rcx, rbx);
578 __ jcc(Assembler::notZero, haveResult);
579 __ increment(rax);
580 __ jcc(Assembler::notZero, loop);
581
582 // strings are equal up to min length
583
584 __ bind(noLoop);
585 __ pop(rax);
586 return_op(LIR_OprFact::illegalOpr);
587
588 __ bind(haveResult);
589 // leave instruction is going to discard the TOS value
590 __ mov (rax, rcx); // result of call is in rax,
591 }
592
593
594 void LIR_Assembler::return_op(LIR_Opr result) {
595 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
596 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
597 assert(result->fpu() == 0, "result must already be on TOS");
598 }
599
600 // Pop the stack before the safepoint code
601 __ remove_frame(initial_frame_size_in_bytes());
602
603 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
604
605 // Note: we do not need to round double result; float result has the right precision
606 // the poll sets the condition code, but no data registers
607 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
608
609 if (Assembler::is_polling_page_far()) {
610 __ lea(rscratch1, polling_page);
611 __ relocate(relocInfo::poll_return_type);
612 __ testl(rax, Address(rscratch1, 0));
613 } else {
614 __ testl(rax, polling_page);
615 }
616 __ ret(0);
617 }
618
619
620 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
621 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
622 guarantee(info != NULL, "Shouldn't be NULL");
623 int offset = __ offset();
624 if (Assembler::is_polling_page_far()) {
625 __ lea(rscratch1, polling_page);
626 offset = __ offset();
627 add_debug_info_for_branch(info);
628 __ relocate(relocInfo::poll_type);
629 __ testl(rax, Address(rscratch1, 0));
630 } else {
631 add_debug_info_for_branch(info);
632 __ testl(rax, polling_page);
633 }
634 return offset;
635 }
636
637
638 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
639 if (from_reg != to_reg) __ mov(to_reg, from_reg);
640 }
641
642 void LIR_Assembler::swap_reg(Register a, Register b) {
643 __ xchgptr(a, b);
644 }
645
646
647 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
648 assert(src->is_constant(), "should not call otherwise");
649 assert(dest->is_register(), "should not call otherwise");
650 LIR_Const* c = src->as_constant_ptr();
651
652 switch (c->type()) {
653 case T_INT: {
654 assert(patch_code == lir_patch_none, "no patching handled here");
655 __ movl(dest->as_register(), c->as_jint());
656 break;
657 }
658
659 case T_ADDRESS: {
660 assert(patch_code == lir_patch_none, "no patching handled here");
661 __ movptr(dest->as_register(), c->as_jint());
662 break;
663 }
664
665 case T_LONG: {
666 assert(patch_code == lir_patch_none, "no patching handled here");
667 #ifdef _LP64
668 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
669 #else
670 __ movptr(dest->as_register_lo(), c->as_jint_lo());
671 __ movptr(dest->as_register_hi(), c->as_jint_hi());
672 #endif // _LP64
673 break;
674 }
675
676 case T_OBJECT: {
677 if (patch_code != lir_patch_none) {
678 jobject2reg_with_patching(dest->as_register(), info);
679 } else {
680 __ movoop(dest->as_register(), c->as_jobject());
681 }
682 break;
683 }
684
685 case T_METADATA: {
686 if (patch_code != lir_patch_none) {
687 klass2reg_with_patching(dest->as_register(), info);
688 } else {
689 __ mov_metadata(dest->as_register(), c->as_metadata());
690 }
691 break;
692 }
693
694 case T_FLOAT: {
695 if (dest->is_single_xmm()) {
696 if (c->is_zero_float()) {
697 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
698 } else {
699 __ movflt(dest->as_xmm_float_reg(),
700 InternalAddress(float_constant(c->as_jfloat())));
701 }
702 } else {
703 assert(dest->is_single_fpu(), "must be");
704 assert(dest->fpu_regnr() == 0, "dest must be TOS");
705 if (c->is_zero_float()) {
706 __ fldz();
707 } else if (c->is_one_float()) {
708 __ fld1();
709 } else {
710 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
711 }
712 }
713 break;
714 }
715
716 case T_DOUBLE: {
717 if (dest->is_double_xmm()) {
718 if (c->is_zero_double()) {
719 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
720 } else {
721 __ movdbl(dest->as_xmm_double_reg(),
722 InternalAddress(double_constant(c->as_jdouble())));
723 }
724 } else {
725 assert(dest->is_double_fpu(), "must be");
726 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
727 if (c->is_zero_double()) {
728 __ fldz();
729 } else if (c->is_one_double()) {
730 __ fld1();
731 } else {
732 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
733 }
734 }
735 break;
736 }
737
738 default:
739 ShouldNotReachHere();
740 }
741 }
742
743 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
744 assert(src->is_constant(), "should not call otherwise");
745 assert(dest->is_stack(), "should not call otherwise");
746 LIR_Const* c = src->as_constant_ptr();
747
748 switch (c->type()) {
749 case T_INT: // fall through
750 case T_FLOAT:
751 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
752 break;
753
754 case T_ADDRESS:
755 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
756 break;
757
758 case T_OBJECT:
759 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
760 break;
761
762 case T_LONG: // fall through
763 case T_DOUBLE:
764 #ifdef _LP64
765 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
766 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
767 #else
768 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
769 lo_word_offset_in_bytes), c->as_jint_lo_bits());
770 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
771 hi_word_offset_in_bytes), c->as_jint_hi_bits());
772 #endif // _LP64
773 break;
774
775 default:
776 ShouldNotReachHere();
777 }
778 }
779
780 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
781 assert(src->is_constant(), "should not call otherwise");
782 assert(dest->is_address(), "should not call otherwise");
783 LIR_Const* c = src->as_constant_ptr();
784 LIR_Address* addr = dest->as_address_ptr();
785
786 int null_check_here = code_offset();
787 switch (type) {
788 case T_INT: // fall through
789 case T_FLOAT:
790 __ movl(as_Address(addr), c->as_jint_bits());
791 break;
792
793 case T_ADDRESS:
794 __ movptr(as_Address(addr), c->as_jint_bits());
795 break;
796
797 case T_OBJECT: // fall through
798 case T_ARRAY:
799 if (c->as_jobject() == NULL) {
800 if (UseCompressedOops && !wide) {
801 __ movl(as_Address(addr), (int32_t)NULL_WORD);
802 } else {
803 #ifdef _LP64
804 __ xorptr(rscratch1, rscratch1);
805 null_check_here = code_offset();
806 __ movptr(as_Address(addr), rscratch1);
807 #else
808 __ movptr(as_Address(addr), NULL_WORD);
809 #endif
810 }
811 } else {
812 if (is_literal_address(addr)) {
813 ShouldNotReachHere();
814 __ movoop(as_Address(addr, noreg), c->as_jobject());
815 } else {
816 #ifdef _LP64
817 __ movoop(rscratch1, c->as_jobject());
818 if (UseCompressedOops && !wide) {
819 __ encode_heap_oop(rscratch1);
820 null_check_here = code_offset();
821 __ movl(as_Address_lo(addr), rscratch1);
822 } else {
823 null_check_here = code_offset();
824 __ movptr(as_Address_lo(addr), rscratch1);
825 }
826 #else
827 __ movoop(as_Address(addr), c->as_jobject());
828 #endif
829 }
830 }
831 break;
832
833 case T_LONG: // fall through
834 case T_DOUBLE:
835 #ifdef _LP64
836 if (is_literal_address(addr)) {
837 ShouldNotReachHere();
838 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
839 } else {
840 __ movptr(r10, (intptr_t)c->as_jlong_bits());
841 null_check_here = code_offset();
842 __ movptr(as_Address_lo(addr), r10);
843 }
844 #else
845 // Always reachable in 32bit so this doesn't produce useless move literal
846 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
847 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
848 #endif // _LP64
849 break;
850
851 case T_BOOLEAN: // fall through
852 case T_BYTE:
853 __ movb(as_Address(addr), c->as_jint() & 0xFF);
854 break;
855
856 case T_CHAR: // fall through
857 case T_SHORT:
858 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
859 break;
860
861 default:
862 ShouldNotReachHere();
863 };
864
865 if (info != NULL) {
866 add_debug_info_for_null_check(null_check_here, info);
867 }
868 }
869
870
871 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
872 assert(src->is_register(), "should not call otherwise");
873 assert(dest->is_register(), "should not call otherwise");
874
875 // move between cpu-registers
876 if (dest->is_single_cpu()) {
877 #ifdef _LP64
878 if (src->type() == T_LONG) {
879 // Can do LONG -> OBJECT
880 move_regs(src->as_register_lo(), dest->as_register());
881 return;
882 }
883 #endif
884 assert(src->is_single_cpu(), "must match");
885 if (src->type() == T_OBJECT) {
886 __ verify_oop(src->as_register());
887 }
888 move_regs(src->as_register(), dest->as_register());
889
890 } else if (dest->is_double_cpu()) {
891 #ifdef _LP64
892 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
893 // Surprising to me but we can see move of a long to t_object
894 __ verify_oop(src->as_register());
895 move_regs(src->as_register(), dest->as_register_lo());
896 return;
897 }
898 #endif
899 assert(src->is_double_cpu(), "must match");
900 Register f_lo = src->as_register_lo();
901 Register f_hi = src->as_register_hi();
902 Register t_lo = dest->as_register_lo();
903 Register t_hi = dest->as_register_hi();
904 #ifdef _LP64
905 assert(f_hi == f_lo, "must be same");
906 assert(t_hi == t_lo, "must be same");
907 move_regs(f_lo, t_lo);
908 #else
909 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
910
911
912 if (f_lo == t_hi && f_hi == t_lo) {
913 swap_reg(f_lo, f_hi);
914 } else if (f_hi == t_lo) {
915 assert(f_lo != t_hi, "overwriting register");
916 move_regs(f_hi, t_hi);
917 move_regs(f_lo, t_lo);
918 } else {
919 assert(f_hi != t_lo, "overwriting register");
920 move_regs(f_lo, t_lo);
921 move_regs(f_hi, t_hi);
922 }
923 #endif // LP64
924
925 // special moves from fpu-register to xmm-register
926 // necessary for method results
927 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
928 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
929 __ fld_s(Address(rsp, 0));
930 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
931 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
932 __ fld_d(Address(rsp, 0));
933 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
934 __ fstp_s(Address(rsp, 0));
935 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
936 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
937 __ fstp_d(Address(rsp, 0));
938 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
939
940 // move between xmm-registers
941 } else if (dest->is_single_xmm()) {
942 assert(src->is_single_xmm(), "must match");
943 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
944 } else if (dest->is_double_xmm()) {
945 assert(src->is_double_xmm(), "must match");
946 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
947
948 // move between fpu-registers (no instruction necessary because of fpu-stack)
949 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
950 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
951 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
952 } else {
953 ShouldNotReachHere();
954 }
955 }
956
957 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
958 assert(src->is_register(), "should not call otherwise");
959 assert(dest->is_stack(), "should not call otherwise");
960
961 if (src->is_single_cpu()) {
962 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
963 if (type == T_OBJECT || type == T_ARRAY) {
964 __ verify_oop(src->as_register());
965 __ movptr (dst, src->as_register());
966 } else if (type == T_METADATA) {
967 __ movptr (dst, src->as_register());
968 } else {
969 __ movl (dst, src->as_register());
970 }
971
972 } else if (src->is_double_cpu()) {
973 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
974 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
975 __ movptr (dstLO, src->as_register_lo());
976 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
977
978 } else if (src->is_single_xmm()) {
979 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
980 __ movflt(dst_addr, src->as_xmm_float_reg());
981
982 } else if (src->is_double_xmm()) {
983 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
984 __ movdbl(dst_addr, src->as_xmm_double_reg());
985
986 } else if (src->is_single_fpu()) {
987 assert(src->fpu_regnr() == 0, "argument must be on TOS");
988 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
989 if (pop_fpu_stack) __ fstp_s (dst_addr);
990 else __ fst_s (dst_addr);
991
992 } else if (src->is_double_fpu()) {
993 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
994 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
995 if (pop_fpu_stack) __ fstp_d (dst_addr);
996 else __ fst_d (dst_addr);
997
998 } else {
999 ShouldNotReachHere();
1000 }
1001 }
1002
1003
1004 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1005 LIR_Address* to_addr = dest->as_address_ptr();
1006 PatchingStub* patch = NULL;
1007 Register compressed_src = rscratch1;
1008
1009 if (type == T_ARRAY || type == T_OBJECT) {
1010 __ verify_oop(src->as_register());
1011 #ifdef _LP64
1012 if (UseCompressedOops && !wide) {
1013 __ movptr(compressed_src, src->as_register());
1014 __ encode_heap_oop(compressed_src);
1015 if (patch_code != lir_patch_none) {
1016 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1017 }
1018 }
1019 #endif
1020 }
1021
1022 if (patch_code != lir_patch_none) {
1023 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1024 Address toa = as_Address(to_addr);
1025 assert(toa.disp() != 0, "must have");
1026 }
1027
1028 int null_check_here = code_offset();
1029 switch (type) {
1030 case T_FLOAT: {
1031 if (src->is_single_xmm()) {
1032 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1033 } else {
1034 assert(src->is_single_fpu(), "must be");
1035 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1036 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1037 else __ fst_s (as_Address(to_addr));
1038 }
1039 break;
1040 }
1041
1042 case T_DOUBLE: {
1043 if (src->is_double_xmm()) {
1044 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1045 } else {
1046 assert(src->is_double_fpu(), "must be");
1047 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1048 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1049 else __ fst_d (as_Address(to_addr));
1050 }
1051 break;
1052 }
1053
1054 case T_ARRAY: // fall through
1055 case T_OBJECT: // fall through
1056 if (UseCompressedOops && !wide) {
1057 __ movl(as_Address(to_addr), compressed_src);
1058 } else {
1059 __ movptr(as_Address(to_addr), src->as_register());
1060 }
1061 break;
1062 case T_METADATA:
1063 // We get here to store a method pointer to the stack to pass to
1064 // a dtrace runtime call. This can't work on 64 bit with
1065 // compressed klass ptrs: T_METADATA can be a compressed klass
1066 // ptr or a 64 bit method pointer.
1067 LP64_ONLY(ShouldNotReachHere());
1068 __ movptr(as_Address(to_addr), src->as_register());
1069 break;
1070 case T_ADDRESS:
1071 __ movptr(as_Address(to_addr), src->as_register());
1072 break;
1073 case T_INT:
1074 __ movl(as_Address(to_addr), src->as_register());
1075 break;
1076
1077 case T_LONG: {
1078 Register from_lo = src->as_register_lo();
1079 Register from_hi = src->as_register_hi();
1080 #ifdef _LP64
1081 __ movptr(as_Address_lo(to_addr), from_lo);
1082 #else
1083 Register base = to_addr->base()->as_register();
1084 Register index = noreg;
1085 if (to_addr->index()->is_register()) {
1086 index = to_addr->index()->as_register();
1087 }
1088 if (base == from_lo || index == from_lo) {
1089 assert(base != from_hi, "can't be");
1090 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1091 __ movl(as_Address_hi(to_addr), from_hi);
1092 if (patch != NULL) {
1093 patching_epilog(patch, lir_patch_high, base, info);
1094 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1095 patch_code = lir_patch_low;
1096 }
1097 __ movl(as_Address_lo(to_addr), from_lo);
1098 } else {
1099 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1100 __ movl(as_Address_lo(to_addr), from_lo);
1101 if (patch != NULL) {
1102 patching_epilog(patch, lir_patch_low, base, info);
1103 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1104 patch_code = lir_patch_high;
1105 }
1106 __ movl(as_Address_hi(to_addr), from_hi);
1107 }
1108 #endif // _LP64
1109 break;
1110 }
1111
1112 case T_BYTE: // fall through
1113 case T_BOOLEAN: {
1114 Register src_reg = src->as_register();
1115 Address dst_addr = as_Address(to_addr);
1116 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1117 __ movb(dst_addr, src_reg);
1118 break;
1119 }
1120
1121 case T_CHAR: // fall through
1122 case T_SHORT:
1123 __ movw(as_Address(to_addr), src->as_register());
1124 break;
1125
1126 default:
1127 ShouldNotReachHere();
1128 }
1129 if (info != NULL) {
1130 add_debug_info_for_null_check(null_check_here, info);
1131 }
1132
1133 if (patch_code != lir_patch_none) {
1134 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1135 }
1136 }
1137
1138
1139 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1140 assert(src->is_stack(), "should not call otherwise");
1141 assert(dest->is_register(), "should not call otherwise");
1142
1143 if (dest->is_single_cpu()) {
1144 if (type == T_ARRAY || type == T_OBJECT) {
1145 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1146 __ verify_oop(dest->as_register());
1147 } else if (type == T_METADATA) {
1148 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1149 } else {
1150 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1151 }
1152
1153 } else if (dest->is_double_cpu()) {
1154 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1155 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1156 __ movptr(dest->as_register_lo(), src_addr_LO);
1157 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1158
1159 } else if (dest->is_single_xmm()) {
1160 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1161 __ movflt(dest->as_xmm_float_reg(), src_addr);
1162
1163 } else if (dest->is_double_xmm()) {
1164 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1165 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1166
1167 } else if (dest->is_single_fpu()) {
1168 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1169 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1170 __ fld_s(src_addr);
1171
1172 } else if (dest->is_double_fpu()) {
1173 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1174 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1175 __ fld_d(src_addr);
1176
1177 } else {
1178 ShouldNotReachHere();
1179 }
1180 }
1181
1182
1183 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1184 if (src->is_single_stack()) {
1185 if (type == T_OBJECT || type == T_ARRAY) {
1186 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1187 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1188 } else {
1189 #ifndef _LP64
1190 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1191 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1192 #else
1193 //no pushl on 64bits
1194 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1195 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1196 #endif
1197 }
1198
1199 } else if (src->is_double_stack()) {
1200 #ifdef _LP64
1201 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1202 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1203 #else
1204 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1205 // push and pop the part at src + wordSize, adding wordSize for the previous push
1206 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1207 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1208 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1209 #endif // _LP64
1210
1211 } else {
1212 ShouldNotReachHere();
1213 }
1214 }
1215
1216
1217 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1218 assert(src->is_address(), "should not call otherwise");
1219 assert(dest->is_register(), "should not call otherwise");
1220
1221 LIR_Address* addr = src->as_address_ptr();
1222 Address from_addr = as_Address(addr);
1223
1224 if (addr->base()->type() == T_OBJECT) {
1225 __ verify_oop(addr->base()->as_pointer_register());
1226 }
1227
1228 switch (type) {
1229 case T_BOOLEAN: // fall through
1230 case T_BYTE: // fall through
1231 case T_CHAR: // fall through
1232 case T_SHORT:
1233 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1234 // on pre P6 processors we may get partial register stalls
1235 // so blow away the value of to_rinfo before loading a
1236 // partial word into it. Do it here so that it precedes
1237 // the potential patch point below.
1238 __ xorptr(dest->as_register(), dest->as_register());
1239 }
1240 break;
1241 }
1242
1243 PatchingStub* patch = NULL;
1244 if (patch_code != lir_patch_none) {
1245 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1246 assert(from_addr.disp() != 0, "must have");
1247 }
1248 if (info != NULL) {
1249 add_debug_info_for_null_check_here(info);
1250 }
1251
1252 switch (type) {
1253 case T_FLOAT: {
1254 if (dest->is_single_xmm()) {
1255 __ movflt(dest->as_xmm_float_reg(), from_addr);
1256 } else {
1257 assert(dest->is_single_fpu(), "must be");
1258 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1259 __ fld_s(from_addr);
1260 }
1261 break;
1262 }
1263
1264 case T_DOUBLE: {
1265 if (dest->is_double_xmm()) {
1266 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1267 } else {
1268 assert(dest->is_double_fpu(), "must be");
1269 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1270 __ fld_d(from_addr);
1271 }
1272 break;
1273 }
1274
1275 case T_OBJECT: // fall through
1276 case T_ARRAY: // fall through
1277 if (UseCompressedOops && !wide) {
1278 __ movl(dest->as_register(), from_addr);
1279 } else {
1280 __ movptr(dest->as_register(), from_addr);
1281 }
1282 break;
1283
1284 case T_ADDRESS:
1285 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1286 __ movl(dest->as_register(), from_addr);
1287 } else {
1288 __ movptr(dest->as_register(), from_addr);
1289 }
1290 break;
1291 case T_INT:
1292 __ movl(dest->as_register(), from_addr);
1293 break;
1294
1295 case T_LONG: {
1296 Register to_lo = dest->as_register_lo();
1297 Register to_hi = dest->as_register_hi();
1298 #ifdef _LP64
1299 __ movptr(to_lo, as_Address_lo(addr));
1300 #else
1301 Register base = addr->base()->as_register();
1302 Register index = noreg;
1303 if (addr->index()->is_register()) {
1304 index = addr->index()->as_register();
1305 }
1306 if ((base == to_lo && index == to_hi) ||
1307 (base == to_hi && index == to_lo)) {
1308 // addresses with 2 registers are only formed as a result of
1309 // array access so this code will never have to deal with
1310 // patches or null checks.
1311 assert(info == NULL && patch == NULL, "must be");
1312 __ lea(to_hi, as_Address(addr));
1313 __ movl(to_lo, Address(to_hi, 0));
1314 __ movl(to_hi, Address(to_hi, BytesPerWord));
1315 } else if (base == to_lo || index == to_lo) {
1316 assert(base != to_hi, "can't be");
1317 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1318 __ movl(to_hi, as_Address_hi(addr));
1319 if (patch != NULL) {
1320 patching_epilog(patch, lir_patch_high, base, info);
1321 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1322 patch_code = lir_patch_low;
1323 }
1324 __ movl(to_lo, as_Address_lo(addr));
1325 } else {
1326 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1327 __ movl(to_lo, as_Address_lo(addr));
1328 if (patch != NULL) {
1329 patching_epilog(patch, lir_patch_low, base, info);
1330 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1331 patch_code = lir_patch_high;
1332 }
1333 __ movl(to_hi, as_Address_hi(addr));
1334 }
1335 #endif // _LP64
1336 break;
1337 }
1338
1339 case T_BOOLEAN: // fall through
1340 case T_BYTE: {
1341 Register dest_reg = dest->as_register();
1342 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1343 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1344 __ movsbl(dest_reg, from_addr);
1345 } else {
1346 __ movb(dest_reg, from_addr);
1347 __ shll(dest_reg, 24);
1348 __ sarl(dest_reg, 24);
1349 }
1350 break;
1351 }
1352
1353 case T_CHAR: {
1354 Register dest_reg = dest->as_register();
1355 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1356 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1357 __ movzwl(dest_reg, from_addr);
1358 } else {
1359 __ movw(dest_reg, from_addr);
1360 }
1361 break;
1362 }
1363
1364 case T_SHORT: {
1365 Register dest_reg = dest->as_register();
1366 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1367 __ movswl(dest_reg, from_addr);
1368 } else {
1369 __ movw(dest_reg, from_addr);
1370 __ shll(dest_reg, 16);
1371 __ sarl(dest_reg, 16);
1372 }
1373 break;
1374 }
1375
1376 default:
1377 ShouldNotReachHere();
1378 }
1379
1380 if (patch != NULL) {
1381 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1382 }
1383
1384 if (type == T_ARRAY || type == T_OBJECT) {
1385 #ifdef _LP64
1386 if (UseCompressedOops && !wide) {
1387 __ decode_heap_oop(dest->as_register());
1388 }
1389 #endif
1390 __ verify_oop(dest->as_register());
1391 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1392 #ifdef _LP64
1393 if (UseCompressedClassPointers) {
1394 __ decode_klass_not_null(dest->as_register());
1395 }
1396 #endif
1397 }
1398 }
1399
1400
1401 NEEDS_CLEANUP; // This could be static?
1402 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1403 int elem_size = type2aelembytes(type);
1404 switch (elem_size) {
1405 case 1: return Address::times_1;
1406 case 2: return Address::times_2;
1407 case 4: return Address::times_4;
1408 case 8: return Address::times_8;
1409 }
1410 ShouldNotReachHere();
1411 return Address::no_scale;
1412 }
1413
1414
1415 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1416 switch (op->code()) {
1417 case lir_idiv:
1418 case lir_irem:
1419 arithmetic_idiv(op->code(),
1420 op->in_opr1(),
1421 op->in_opr2(),
1422 op->in_opr3(),
1423 op->result_opr(),
1424 op->info());
1425 break;
1426 default: ShouldNotReachHere(); break;
1427 }
1428 }
1429
1430 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1431 #ifdef ASSERT
1432 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1433 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1434 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1435 #endif
1436
1437 if (op->cond() == lir_cond_always) {
1438 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1439 __ jmp (*(op->label()));
1440 } else {
1441 Assembler::Condition acond = Assembler::zero;
1442 if (op->code() == lir_cond_float_branch) {
1443 assert(op->ublock() != NULL, "must have unordered successor");
1444 __ jcc(Assembler::parity, *(op->ublock()->label()));
1445 switch(op->cond()) {
1446 case lir_cond_equal: acond = Assembler::equal; break;
1447 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1448 case lir_cond_less: acond = Assembler::below; break;
1449 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1450 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1451 case lir_cond_greater: acond = Assembler::above; break;
1452 default: ShouldNotReachHere();
1453 }
1454 } else {
1455 switch (op->cond()) {
1456 case lir_cond_equal: acond = Assembler::equal; break;
1457 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1458 case lir_cond_less: acond = Assembler::less; break;
1459 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1460 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1461 case lir_cond_greater: acond = Assembler::greater; break;
1462 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1463 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1464 default: ShouldNotReachHere();
1465 }
1466 }
1467 __ jcc(acond,*(op->label()));
1468 }
1469 }
1470
1471 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1472 LIR_Opr src = op->in_opr();
1473 LIR_Opr dest = op->result_opr();
1474
1475 switch (op->bytecode()) {
1476 case Bytecodes::_i2l:
1477 #ifdef _LP64
1478 __ movl2ptr(dest->as_register_lo(), src->as_register());
1479 #else
1480 move_regs(src->as_register(), dest->as_register_lo());
1481 move_regs(src->as_register(), dest->as_register_hi());
1482 __ sarl(dest->as_register_hi(), 31);
1483 #endif // LP64
1484 break;
1485
1486 case Bytecodes::_l2i:
1487 #ifdef _LP64
1488 __ movl(dest->as_register(), src->as_register_lo());
1489 #else
1490 move_regs(src->as_register_lo(), dest->as_register());
1491 #endif
1492 break;
1493
1494 case Bytecodes::_i2b:
1495 move_regs(src->as_register(), dest->as_register());
1496 __ sign_extend_byte(dest->as_register());
1497 break;
1498
1499 case Bytecodes::_i2c:
1500 move_regs(src->as_register(), dest->as_register());
1501 __ andl(dest->as_register(), 0xFFFF);
1502 break;
1503
1504 case Bytecodes::_i2s:
1505 move_regs(src->as_register(), dest->as_register());
1506 __ sign_extend_short(dest->as_register());
1507 break;
1508
1509
1510 case Bytecodes::_f2d:
1511 case Bytecodes::_d2f:
1512 if (dest->is_single_xmm()) {
1513 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1514 } else if (dest->is_double_xmm()) {
1515 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1516 } else {
1517 assert(src->fpu() == dest->fpu(), "register must be equal");
1518 // do nothing (float result is rounded later through spilling)
1519 }
1520 break;
1521
1522 case Bytecodes::_i2f:
1523 case Bytecodes::_i2d:
1524 if (dest->is_single_xmm()) {
1525 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1526 } else if (dest->is_double_xmm()) {
1527 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1528 } else {
1529 assert(dest->fpu() == 0, "result must be on TOS");
1530 __ movl(Address(rsp, 0), src->as_register());
1531 __ fild_s(Address(rsp, 0));
1532 }
1533 break;
1534
1535 case Bytecodes::_f2i:
1536 case Bytecodes::_d2i:
1537 if (src->is_single_xmm()) {
1538 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1539 } else if (src->is_double_xmm()) {
1540 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1541 } else {
1542 assert(src->fpu() == 0, "input must be on TOS");
1543 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1544 __ fist_s(Address(rsp, 0));
1545 __ movl(dest->as_register(), Address(rsp, 0));
1546 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1547 }
1548
1549 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1550 assert(op->stub() != NULL, "stub required");
1551 __ cmpl(dest->as_register(), 0x80000000);
1552 __ jcc(Assembler::equal, *op->stub()->entry());
1553 __ bind(*op->stub()->continuation());
1554 break;
1555
1556 case Bytecodes::_l2f:
1557 case Bytecodes::_l2d:
1558 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1559 assert(dest->fpu() == 0, "result must be on TOS");
1560
1561 __ movptr(Address(rsp, 0), src->as_register_lo());
1562 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1563 __ fild_d(Address(rsp, 0));
1564 // float result is rounded later through spilling
1565 break;
1566
1567 case Bytecodes::_f2l:
1568 case Bytecodes::_d2l:
1569 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1570 assert(src->fpu() == 0, "input must be on TOS");
1571 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1572
1573 // instruction sequence too long to inline it here
1574 {
1575 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1576 }
1577 break;
1578
1579 default: ShouldNotReachHere();
1580 }
1581 }
1582
1583 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1584 if (op->init_check()) {
1585 __ cmpb(Address(op->klass()->as_register(),
1586 InstanceKlass::init_state_offset()),
1587 InstanceKlass::fully_initialized);
1588 add_debug_info_for_null_check_here(op->stub()->info());
1589 __ jcc(Assembler::notEqual, *op->stub()->entry());
1590 }
1591 __ allocate_object(op->obj()->as_register(),
1592 op->tmp1()->as_register(),
1593 op->tmp2()->as_register(),
1594 op->header_size(),
1595 op->object_size(),
1596 op->klass()->as_register(),
1597 *op->stub()->entry());
1598 __ bind(*op->stub()->continuation());
1599 }
1600
1601 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1602 Register len = op->len()->as_register();
1603 LP64_ONLY( __ movslq(len, len); )
1604
1605 if (UseSlowPath ||
1606 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1607 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1608 __ jmp(*op->stub()->entry());
1609 } else {
1610 Register tmp1 = op->tmp1()->as_register();
1611 Register tmp2 = op->tmp2()->as_register();
1612 Register tmp3 = op->tmp3()->as_register();
1613 if (len == tmp1) {
1614 tmp1 = tmp3;
1615 } else if (len == tmp2) {
1616 tmp2 = tmp3;
1617 } else if (len == tmp3) {
1618 // everything is ok
1619 } else {
1620 __ mov(tmp3, len);
1621 }
1622 __ allocate_array(op->obj()->as_register(),
1623 len,
1624 tmp1,
1625 tmp2,
1626 arrayOopDesc::header_size(op->type()),
1627 array_element_size(op->type()),
1628 op->klass()->as_register(),
1629 *op->stub()->entry());
1630 }
1631 __ bind(*op->stub()->continuation());
1632 }
1633
1634 void LIR_Assembler::type_profile_helper(Register mdo,
1635 ciMethodData *md, ciProfileData *data,
1636 Register recv, Label* update_done) {
1637 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1638 Label next_test;
1639 // See if the receiver is receiver[n].
1640 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1641 __ jccb(Assembler::notEqual, next_test);
1642 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1643 __ addptr(data_addr, DataLayout::counter_increment);
1644 __ jmp(*update_done);
1645 __ bind(next_test);
1646 }
1647
1648 // Didn't find receiver; find next empty slot and fill it in
1649 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1650 Label next_test;
1651 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1652 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1653 __ jccb(Assembler::notEqual, next_test);
1654 __ movptr(recv_addr, recv);
1655 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1656 __ jmp(*update_done);
1657 __ bind(next_test);
1658 }
1659 }
1660
1661 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1662 // we always need a stub for the failure case.
1663 CodeStub* stub = op->stub();
1664 Register obj = op->object()->as_register();
1665 Register k_RInfo = op->tmp1()->as_register();
1666 Register klass_RInfo = op->tmp2()->as_register();
1667 Register dst = op->result_opr()->as_register();
1668 ciKlass* k = op->klass();
1669 Register Rtmp1 = noreg;
1670
1671 // check if it needs to be profiled
1672 ciMethodData* md;
1673 ciProfileData* data;
1674
1675 if (op->should_profile()) {
1676 ciMethod* method = op->profiled_method();
1677 assert(method != NULL, "Should have method");
1678 int bci = op->profiled_bci();
1679 md = method->method_data_or_null();
1680 assert(md != NULL, "Sanity");
1681 data = md->bci_to_data(bci);
1682 assert(data != NULL, "need data for type check");
1683 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1684 }
1685 Label profile_cast_success, profile_cast_failure;
1686 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1687 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1688
1689 if (obj == k_RInfo) {
1690 k_RInfo = dst;
1691 } else if (obj == klass_RInfo) {
1692 klass_RInfo = dst;
1693 }
1694 if (k->is_loaded() && !UseCompressedClassPointers) {
1695 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1696 } else {
1697 Rtmp1 = op->tmp3()->as_register();
1698 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1699 }
1700
1701 assert_different_registers(obj, k_RInfo, klass_RInfo);
1702
1703 __ cmpptr(obj, (int32_t)NULL_WORD);
1704 if (op->should_profile()) {
1705 Label not_null;
1706 __ jccb(Assembler::notEqual, not_null);
1707 // Object is null; update MDO and exit
1708 Register mdo = klass_RInfo;
1709 __ mov_metadata(mdo, md->constant_encoding());
1710 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1711 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1712 __ orl(data_addr, header_bits);
1713 __ jmp(*obj_is_null);
1714 __ bind(not_null);
1715 } else {
1716 __ jcc(Assembler::equal, *obj_is_null);
1717 }
1718
1719 if (!k->is_loaded()) {
1720 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1721 } else {
1722 #ifdef _LP64
1723 __ mov_metadata(k_RInfo, k->constant_encoding());
1724 #endif // _LP64
1725 }
1726 __ verify_oop(obj);
1727
1728 if (op->fast_check()) {
1729 // get object class
1730 // not a safepoint as obj null check happens earlier
1731 #ifdef _LP64
1732 if (UseCompressedClassPointers) {
1733 __ load_klass(Rtmp1, obj);
1734 __ cmpptr(k_RInfo, Rtmp1);
1735 } else {
1736 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1737 }
1738 #else
1739 if (k->is_loaded()) {
1740 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1741 } else {
1742 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1743 }
1744 #endif
1745 __ jcc(Assembler::notEqual, *failure_target);
1746 // successful cast, fall through to profile or jump
1747 } else {
1748 // get object class
1749 // not a safepoint as obj null check happens earlier
1750 __ load_klass(klass_RInfo, obj);
1751 if (k->is_loaded()) {
1752 // See if we get an immediate positive hit
1753 #ifdef _LP64
1754 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1755 #else
1756 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1757 #endif // _LP64
1758 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1759 __ jcc(Assembler::notEqual, *failure_target);
1760 // successful cast, fall through to profile or jump
1761 } else {
1762 // See if we get an immediate positive hit
1763 __ jcc(Assembler::equal, *success_target);
1764 // check for self
1765 #ifdef _LP64
1766 __ cmpptr(klass_RInfo, k_RInfo);
1767 #else
1768 __ cmpklass(klass_RInfo, k->constant_encoding());
1769 #endif // _LP64
1770 __ jcc(Assembler::equal, *success_target);
1771
1772 __ push(klass_RInfo);
1773 #ifdef _LP64
1774 __ push(k_RInfo);
1775 #else
1776 __ pushklass(k->constant_encoding());
1777 #endif // _LP64
1778 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1779 __ pop(klass_RInfo);
1780 __ pop(klass_RInfo);
1781 // result is a boolean
1782 __ cmpl(klass_RInfo, 0);
1783 __ jcc(Assembler::equal, *failure_target);
1784 // successful cast, fall through to profile or jump
1785 }
1786 } else {
1787 // perform the fast part of the checking logic
1788 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1789 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1790 __ push(klass_RInfo);
1791 __ push(k_RInfo);
1792 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1793 __ pop(klass_RInfo);
1794 __ pop(k_RInfo);
1795 // result is a boolean
1796 __ cmpl(k_RInfo, 0);
1797 __ jcc(Assembler::equal, *failure_target);
1798 // successful cast, fall through to profile or jump
1799 }
1800 }
1801 if (op->should_profile()) {
1802 Register mdo = klass_RInfo, recv = k_RInfo;
1803 __ bind(profile_cast_success);
1804 __ mov_metadata(mdo, md->constant_encoding());
1805 __ load_klass(recv, obj);
1806 Label update_done;
1807 type_profile_helper(mdo, md, data, recv, success);
1808 __ jmp(*success);
1809
1810 __ bind(profile_cast_failure);
1811 __ mov_metadata(mdo, md->constant_encoding());
1812 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1813 __ subptr(counter_addr, DataLayout::counter_increment);
1814 __ jmp(*failure);
1815 }
1816 __ jmp(*success);
1817 }
1818
1819
1820 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1821 LIR_Code code = op->code();
1822 if (code == lir_store_check) {
1823 Register value = op->object()->as_register();
1824 Register array = op->array()->as_register();
1825 Register k_RInfo = op->tmp1()->as_register();
1826 Register klass_RInfo = op->tmp2()->as_register();
1827 Register Rtmp1 = op->tmp3()->as_register();
1828
1829 CodeStub* stub = op->stub();
1830
1831 // check if it needs to be profiled
1832 ciMethodData* md;
1833 ciProfileData* data;
1834
1835 if (op->should_profile()) {
1836 ciMethod* method = op->profiled_method();
1837 assert(method != NULL, "Should have method");
1838 int bci = op->profiled_bci();
1839 md = method->method_data_or_null();
1840 assert(md != NULL, "Sanity");
1841 data = md->bci_to_data(bci);
1842 assert(data != NULL, "need data for type check");
1843 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1844 }
1845 Label profile_cast_success, profile_cast_failure, done;
1846 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1847 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1848
1849 __ cmpptr(value, (int32_t)NULL_WORD);
1850 if (op->should_profile()) {
1851 Label not_null;
1852 __ jccb(Assembler::notEqual, not_null);
1853 // Object is null; update MDO and exit
1854 Register mdo = klass_RInfo;
1855 __ mov_metadata(mdo, md->constant_encoding());
1856 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1857 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1858 __ orl(data_addr, header_bits);
1859 __ jmp(done);
1860 __ bind(not_null);
1861 } else {
1862 __ jcc(Assembler::equal, done);
1863 }
1864
1865 add_debug_info_for_null_check_here(op->info_for_exception());
1866 __ load_klass(k_RInfo, array);
1867 __ load_klass(klass_RInfo, value);
1868
1869 // get instance klass (it's already uncompressed)
1870 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1871 // perform the fast part of the checking logic
1872 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1873 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1874 __ push(klass_RInfo);
1875 __ push(k_RInfo);
1876 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1877 __ pop(klass_RInfo);
1878 __ pop(k_RInfo);
1879 // result is a boolean
1880 __ cmpl(k_RInfo, 0);
1881 __ jcc(Assembler::equal, *failure_target);
1882 // fall through to the success case
1883
1884 if (op->should_profile()) {
1885 Register mdo = klass_RInfo, recv = k_RInfo;
1886 __ bind(profile_cast_success);
1887 __ mov_metadata(mdo, md->constant_encoding());
1888 __ load_klass(recv, value);
1889 Label update_done;
1890 type_profile_helper(mdo, md, data, recv, &done);
1891 __ jmpb(done);
1892
1893 __ bind(profile_cast_failure);
1894 __ mov_metadata(mdo, md->constant_encoding());
1895 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1896 __ subptr(counter_addr, DataLayout::counter_increment);
1897 __ jmp(*stub->entry());
1898 }
1899
1900 __ bind(done);
1901 } else
1902 if (code == lir_checkcast) {
1903 Register obj = op->object()->as_register();
1904 Register dst = op->result_opr()->as_register();
1905 Label success;
1906 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1907 __ bind(success);
1908 if (dst != obj) {
1909 __ mov(dst, obj);
1910 }
1911 } else
1912 if (code == lir_instanceof) {
1913 Register obj = op->object()->as_register();
1914 Register dst = op->result_opr()->as_register();
1915 Label success, failure, done;
1916 emit_typecheck_helper(op, &success, &failure, &failure);
1917 __ bind(failure);
1918 __ xorptr(dst, dst);
1919 __ jmpb(done);
1920 __ bind(success);
1921 __ movptr(dst, 1);
1922 __ bind(done);
1923 } else {
1924 ShouldNotReachHere();
1925 }
1926
1927 }
1928
1929
1930 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1931 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1932 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1933 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1934 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1935 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1936 Register addr = op->addr()->as_register();
1937 if (os::is_MP()) {
1938 __ lock();
1939 }
1940 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1941
1942 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1943 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1944 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1945 Register newval = op->new_value()->as_register();
1946 Register cmpval = op->cmp_value()->as_register();
1947 assert(cmpval == rax, "wrong register");
1948 assert(newval != NULL, "new val must be register");
1949 assert(cmpval != newval, "cmp and new values must be in different registers");
1950 assert(cmpval != addr, "cmp and addr must be in different registers");
1951 assert(newval != addr, "new value and addr must be in different registers");
1952
1953 if ( op->code() == lir_cas_obj) {
1954 #ifdef _LP64
1955 if (UseCompressedOops) {
1956 __ encode_heap_oop(cmpval);
1957 __ mov(rscratch1, newval);
1958 __ encode_heap_oop(rscratch1);
1959 if (os::is_MP()) {
1960 __ lock();
1961 }
1962 // cmpval (rax) is implicitly used by this instruction
1963 __ cmpxchgl(rscratch1, Address(addr, 0));
1964 } else
1965 #endif
1966 {
1967 if (os::is_MP()) {
1968 __ lock();
1969 }
1970 __ cmpxchgptr(newval, Address(addr, 0));
1971 }
1972 } else {
1973 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1974 if (os::is_MP()) {
1975 __ lock();
1976 }
1977 __ cmpxchgl(newval, Address(addr, 0));
1978 }
1979 #ifdef _LP64
1980 } else if (op->code() == lir_cas_long) {
1981 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1982 Register newval = op->new_value()->as_register_lo();
1983 Register cmpval = op->cmp_value()->as_register_lo();
1984 assert(cmpval == rax, "wrong register");
1985 assert(newval != NULL, "new val must be register");
1986 assert(cmpval != newval, "cmp and new values must be in different registers");
1987 assert(cmpval != addr, "cmp and addr must be in different registers");
1988 assert(newval != addr, "new value and addr must be in different registers");
1989 if (os::is_MP()) {
1990 __ lock();
1991 }
1992 __ cmpxchgq(newval, Address(addr, 0));
1993 #endif // _LP64
1994 } else {
1995 Unimplemented();
1996 }
1997 }
1998
1999 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2000 Assembler::Condition acond, ncond;
2001 switch (condition) {
2002 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2003 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2004 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2005 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2006 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2007 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2008 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2009 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2010 default: ShouldNotReachHere();
2011 }
2012
2013 if (opr1->is_cpu_register()) {
2014 reg2reg(opr1, result);
2015 } else if (opr1->is_stack()) {
2016 stack2reg(opr1, result, result->type());
2017 } else if (opr1->is_constant()) {
2018 const2reg(opr1, result, lir_patch_none, NULL);
2019 } else {
2020 ShouldNotReachHere();
2021 }
2022
2023 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2024 // optimized version that does not require a branch
2025 if (opr2->is_single_cpu()) {
2026 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2027 __ cmov(ncond, result->as_register(), opr2->as_register());
2028 } else if (opr2->is_double_cpu()) {
2029 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2030 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2031 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2032 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2033 } else if (opr2->is_single_stack()) {
2034 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2035 } else if (opr2->is_double_stack()) {
2036 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2037 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2038 } else {
2039 ShouldNotReachHere();
2040 }
2041
2042 } else {
2043 Label skip;
2044 __ jcc (acond, skip);
2045 if (opr2->is_cpu_register()) {
2046 reg2reg(opr2, result);
2047 } else if (opr2->is_stack()) {
2048 stack2reg(opr2, result, result->type());
2049 } else if (opr2->is_constant()) {
2050 const2reg(opr2, result, lir_patch_none, NULL);
2051 } else {
2052 ShouldNotReachHere();
2053 }
2054 __ bind(skip);
2055 }
2056 }
2057
2058
2059 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2060 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2061
2062 if (left->is_single_cpu()) {
2063 assert(left == dest, "left and dest must be equal");
2064 Register lreg = left->as_register();
2065
2066 if (right->is_single_cpu()) {
2067 // cpu register - cpu register
2068 Register rreg = right->as_register();
2069 switch (code) {
2070 case lir_add: __ addl (lreg, rreg); break;
2071 case lir_sub: __ subl (lreg, rreg); break;
2072 case lir_mul: __ imull(lreg, rreg); break;
2073 default: ShouldNotReachHere();
2074 }
2075
2076 } else if (right->is_stack()) {
2077 // cpu register - stack
2078 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2079 switch (code) {
2080 case lir_add: __ addl(lreg, raddr); break;
2081 case lir_sub: __ subl(lreg, raddr); break;
2082 default: ShouldNotReachHere();
2083 }
2084
2085 } else if (right->is_constant()) {
2086 // cpu register - constant
2087 jint c = right->as_constant_ptr()->as_jint();
2088 switch (code) {
2089 case lir_add: {
2090 __ incrementl(lreg, c);
2091 break;
2092 }
2093 case lir_sub: {
2094 __ decrementl(lreg, c);
2095 break;
2096 }
2097 default: ShouldNotReachHere();
2098 }
2099
2100 } else {
2101 ShouldNotReachHere();
2102 }
2103
2104 } else if (left->is_double_cpu()) {
2105 assert(left == dest, "left and dest must be equal");
2106 Register lreg_lo = left->as_register_lo();
2107 Register lreg_hi = left->as_register_hi();
2108
2109 if (right->is_double_cpu()) {
2110 // cpu register - cpu register
2111 Register rreg_lo = right->as_register_lo();
2112 Register rreg_hi = right->as_register_hi();
2113 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2114 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2115 switch (code) {
2116 case lir_add:
2117 __ addptr(lreg_lo, rreg_lo);
2118 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2119 break;
2120 case lir_sub:
2121 __ subptr(lreg_lo, rreg_lo);
2122 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2123 break;
2124 case lir_mul:
2125 #ifdef _LP64
2126 __ imulq(lreg_lo, rreg_lo);
2127 #else
2128 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2129 __ imull(lreg_hi, rreg_lo);
2130 __ imull(rreg_hi, lreg_lo);
2131 __ addl (rreg_hi, lreg_hi);
2132 __ mull (rreg_lo);
2133 __ addl (lreg_hi, rreg_hi);
2134 #endif // _LP64
2135 break;
2136 default:
2137 ShouldNotReachHere();
2138 }
2139
2140 } else if (right->is_constant()) {
2141 // cpu register - constant
2142 #ifdef _LP64
2143 jlong c = right->as_constant_ptr()->as_jlong_bits();
2144 __ movptr(r10, (intptr_t) c);
2145 switch (code) {
2146 case lir_add:
2147 __ addptr(lreg_lo, r10);
2148 break;
2149 case lir_sub:
2150 __ subptr(lreg_lo, r10);
2151 break;
2152 default:
2153 ShouldNotReachHere();
2154 }
2155 #else
2156 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2157 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2158 switch (code) {
2159 case lir_add:
2160 __ addptr(lreg_lo, c_lo);
2161 __ adcl(lreg_hi, c_hi);
2162 break;
2163 case lir_sub:
2164 __ subptr(lreg_lo, c_lo);
2165 __ sbbl(lreg_hi, c_hi);
2166 break;
2167 default:
2168 ShouldNotReachHere();
2169 }
2170 #endif // _LP64
2171
2172 } else {
2173 ShouldNotReachHere();
2174 }
2175
2176 } else if (left->is_single_xmm()) {
2177 assert(left == dest, "left and dest must be equal");
2178 XMMRegister lreg = left->as_xmm_float_reg();
2179
2180 if (right->is_single_xmm()) {
2181 XMMRegister rreg = right->as_xmm_float_reg();
2182 switch (code) {
2183 case lir_add: __ addss(lreg, rreg); break;
2184 case lir_sub: __ subss(lreg, rreg); break;
2185 case lir_mul_strictfp: // fall through
2186 case lir_mul: __ mulss(lreg, rreg); break;
2187 case lir_div_strictfp: // fall through
2188 case lir_div: __ divss(lreg, rreg); break;
2189 default: ShouldNotReachHere();
2190 }
2191 } else {
2192 Address raddr;
2193 if (right->is_single_stack()) {
2194 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2195 } else if (right->is_constant()) {
2196 // hack for now
2197 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2198 } else {
2199 ShouldNotReachHere();
2200 }
2201 switch (code) {
2202 case lir_add: __ addss(lreg, raddr); break;
2203 case lir_sub: __ subss(lreg, raddr); break;
2204 case lir_mul_strictfp: // fall through
2205 case lir_mul: __ mulss(lreg, raddr); break;
2206 case lir_div_strictfp: // fall through
2207 case lir_div: __ divss(lreg, raddr); break;
2208 default: ShouldNotReachHere();
2209 }
2210 }
2211
2212 } else if (left->is_double_xmm()) {
2213 assert(left == dest, "left and dest must be equal");
2214
2215 XMMRegister lreg = left->as_xmm_double_reg();
2216 if (right->is_double_xmm()) {
2217 XMMRegister rreg = right->as_xmm_double_reg();
2218 switch (code) {
2219 case lir_add: __ addsd(lreg, rreg); break;
2220 case lir_sub: __ subsd(lreg, rreg); break;
2221 case lir_mul_strictfp: // fall through
2222 case lir_mul: __ mulsd(lreg, rreg); break;
2223 case lir_div_strictfp: // fall through
2224 case lir_div: __ divsd(lreg, rreg); break;
2225 default: ShouldNotReachHere();
2226 }
2227 } else {
2228 Address raddr;
2229 if (right->is_double_stack()) {
2230 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2231 } else if (right->is_constant()) {
2232 // hack for now
2233 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2234 } else {
2235 ShouldNotReachHere();
2236 }
2237 switch (code) {
2238 case lir_add: __ addsd(lreg, raddr); break;
2239 case lir_sub: __ subsd(lreg, raddr); break;
2240 case lir_mul_strictfp: // fall through
2241 case lir_mul: __ mulsd(lreg, raddr); break;
2242 case lir_div_strictfp: // fall through
2243 case lir_div: __ divsd(lreg, raddr); break;
2244 default: ShouldNotReachHere();
2245 }
2246 }
2247
2248 } else if (left->is_single_fpu()) {
2249 assert(dest->is_single_fpu(), "fpu stack allocation required");
2250
2251 if (right->is_single_fpu()) {
2252 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2253
2254 } else {
2255 assert(left->fpu_regnr() == 0, "left must be on TOS");
2256 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2257
2258 Address raddr;
2259 if (right->is_single_stack()) {
2260 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2261 } else if (right->is_constant()) {
2262 address const_addr = float_constant(right->as_jfloat());
2263 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2264 // hack for now
2265 raddr = __ as_Address(InternalAddress(const_addr));
2266 } else {
2267 ShouldNotReachHere();
2268 }
2269
2270 switch (code) {
2271 case lir_add: __ fadd_s(raddr); break;
2272 case lir_sub: __ fsub_s(raddr); break;
2273 case lir_mul_strictfp: // fall through
2274 case lir_mul: __ fmul_s(raddr); break;
2275 case lir_div_strictfp: // fall through
2276 case lir_div: __ fdiv_s(raddr); break;
2277 default: ShouldNotReachHere();
2278 }
2279 }
2280
2281 } else if (left->is_double_fpu()) {
2282 assert(dest->is_double_fpu(), "fpu stack allocation required");
2283
2284 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2285 // Double values require special handling for strictfp mul/div on x86
2286 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2287 __ fmulp(left->fpu_regnrLo() + 1);
2288 }
2289
2290 if (right->is_double_fpu()) {
2291 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2292
2293 } else {
2294 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2295 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2296
2297 Address raddr;
2298 if (right->is_double_stack()) {
2299 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2300 } else if (right->is_constant()) {
2301 // hack for now
2302 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2303 } else {
2304 ShouldNotReachHere();
2305 }
2306
2307 switch (code) {
2308 case lir_add: __ fadd_d(raddr); break;
2309 case lir_sub: __ fsub_d(raddr); break;
2310 case lir_mul_strictfp: // fall through
2311 case lir_mul: __ fmul_d(raddr); break;
2312 case lir_div_strictfp: // fall through
2313 case lir_div: __ fdiv_d(raddr); break;
2314 default: ShouldNotReachHere();
2315 }
2316 }
2317
2318 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2319 // Double values require special handling for strictfp mul/div on x86
2320 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2321 __ fmulp(dest->fpu_regnrLo() + 1);
2322 }
2323
2324 } else if (left->is_single_stack() || left->is_address()) {
2325 assert(left == dest, "left and dest must be equal");
2326
2327 Address laddr;
2328 if (left->is_single_stack()) {
2329 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2330 } else if (left->is_address()) {
2331 laddr = as_Address(left->as_address_ptr());
2332 } else {
2333 ShouldNotReachHere();
2334 }
2335
2336 if (right->is_single_cpu()) {
2337 Register rreg = right->as_register();
2338 switch (code) {
2339 case lir_add: __ addl(laddr, rreg); break;
2340 case lir_sub: __ subl(laddr, rreg); break;
2341 default: ShouldNotReachHere();
2342 }
2343 } else if (right->is_constant()) {
2344 jint c = right->as_constant_ptr()->as_jint();
2345 switch (code) {
2346 case lir_add: {
2347 __ incrementl(laddr, c);
2348 break;
2349 }
2350 case lir_sub: {
2351 __ decrementl(laddr, c);
2352 break;
2353 }
2354 default: ShouldNotReachHere();
2355 }
2356 } else {
2357 ShouldNotReachHere();
2358 }
2359
2360 } else {
2361 ShouldNotReachHere();
2362 }
2363 }
2364
2365 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2366 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2367 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2368 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2369
2370 bool left_is_tos = (left_index == 0);
2371 bool dest_is_tos = (dest_index == 0);
2372 int non_tos_index = (left_is_tos ? right_index : left_index);
2373
2374 switch (code) {
2375 case lir_add:
2376 if (pop_fpu_stack) __ faddp(non_tos_index);
2377 else if (dest_is_tos) __ fadd (non_tos_index);
2378 else __ fadda(non_tos_index);
2379 break;
2380
2381 case lir_sub:
2382 if (left_is_tos) {
2383 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2384 else if (dest_is_tos) __ fsub (non_tos_index);
2385 else __ fsubra(non_tos_index);
2386 } else {
2387 if (pop_fpu_stack) __ fsubp (non_tos_index);
2388 else if (dest_is_tos) __ fsubr (non_tos_index);
2389 else __ fsuba (non_tos_index);
2390 }
2391 break;
2392
2393 case lir_mul_strictfp: // fall through
2394 case lir_mul:
2395 if (pop_fpu_stack) __ fmulp(non_tos_index);
2396 else if (dest_is_tos) __ fmul (non_tos_index);
2397 else __ fmula(non_tos_index);
2398 break;
2399
2400 case lir_div_strictfp: // fall through
2401 case lir_div:
2402 if (left_is_tos) {
2403 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2404 else if (dest_is_tos) __ fdiv (non_tos_index);
2405 else __ fdivra(non_tos_index);
2406 } else {
2407 if (pop_fpu_stack) __ fdivp (non_tos_index);
2408 else if (dest_is_tos) __ fdivr (non_tos_index);
2409 else __ fdiva (non_tos_index);
2410 }
2411 break;
2412
2413 case lir_rem:
2414 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2415 __ fremr(noreg);
2416 break;
2417
2418 default:
2419 ShouldNotReachHere();
2420 }
2421 }
2422
2423
2424 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2425 if (value->is_double_xmm()) {
2426 switch(code) {
2427 case lir_abs :
2428 {
2429 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2430 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2431 }
2432 __ andpd(dest->as_xmm_double_reg(),
2433 ExternalAddress((address)double_signmask_pool));
2434 }
2435 break;
2436
2437 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2438 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2439 default : ShouldNotReachHere();
2440 }
2441
2442 } else if (value->is_double_fpu()) {
2443 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2444 switch(code) {
2445 case lir_log : __ flog() ; break;
2446 case lir_log10 : __ flog10() ; break;
2447 case lir_abs : __ fabs() ; break;
2448 case lir_sqrt : __ fsqrt(); break;
2449 case lir_sin :
2450 // Should consider not saving rbx, if not necessary
2451 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2452 break;
2453 case lir_cos :
2454 // Should consider not saving rbx, if not necessary
2455 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2456 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2457 break;
2458 case lir_tan :
2459 // Should consider not saving rbx, if not necessary
2460 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2461 break;
2462 case lir_exp :
2463 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2464 break;
2465 case lir_pow :
2466 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2467 break;
2468 default : ShouldNotReachHere();
2469 }
2470 } else {
2471 Unimplemented();
2472 }
2473 }
2474
2475 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2476 // assert(left->destroys_register(), "check");
2477 if (left->is_single_cpu()) {
2478 Register reg = left->as_register();
2479 if (right->is_constant()) {
2480 int val = right->as_constant_ptr()->as_jint();
2481 switch (code) {
2482 case lir_logic_and: __ andl (reg, val); break;
2483 case lir_logic_or: __ orl (reg, val); break;
2484 case lir_logic_xor: __ xorl (reg, val); break;
2485 default: ShouldNotReachHere();
2486 }
2487 } else if (right->is_stack()) {
2488 // added support for stack operands
2489 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2490 switch (code) {
2491 case lir_logic_and: __ andl (reg, raddr); break;
2492 case lir_logic_or: __ orl (reg, raddr); break;
2493 case lir_logic_xor: __ xorl (reg, raddr); break;
2494 default: ShouldNotReachHere();
2495 }
2496 } else {
2497 Register rright = right->as_register();
2498 switch (code) {
2499 case lir_logic_and: __ andptr (reg, rright); break;
2500 case lir_logic_or : __ orptr (reg, rright); break;
2501 case lir_logic_xor: __ xorptr (reg, rright); break;
2502 default: ShouldNotReachHere();
2503 }
2504 }
2505 move_regs(reg, dst->as_register());
2506 } else {
2507 Register l_lo = left->as_register_lo();
2508 Register l_hi = left->as_register_hi();
2509 if (right->is_constant()) {
2510 #ifdef _LP64
2511 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2512 switch (code) {
2513 case lir_logic_and:
2514 __ andq(l_lo, rscratch1);
2515 break;
2516 case lir_logic_or:
2517 __ orq(l_lo, rscratch1);
2518 break;
2519 case lir_logic_xor:
2520 __ xorq(l_lo, rscratch1);
2521 break;
2522 default: ShouldNotReachHere();
2523 }
2524 #else
2525 int r_lo = right->as_constant_ptr()->as_jint_lo();
2526 int r_hi = right->as_constant_ptr()->as_jint_hi();
2527 switch (code) {
2528 case lir_logic_and:
2529 __ andl(l_lo, r_lo);
2530 __ andl(l_hi, r_hi);
2531 break;
2532 case lir_logic_or:
2533 __ orl(l_lo, r_lo);
2534 __ orl(l_hi, r_hi);
2535 break;
2536 case lir_logic_xor:
2537 __ xorl(l_lo, r_lo);
2538 __ xorl(l_hi, r_hi);
2539 break;
2540 default: ShouldNotReachHere();
2541 }
2542 #endif // _LP64
2543 } else {
2544 #ifdef _LP64
2545 Register r_lo;
2546 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2547 r_lo = right->as_register();
2548 } else {
2549 r_lo = right->as_register_lo();
2550 }
2551 #else
2552 Register r_lo = right->as_register_lo();
2553 Register r_hi = right->as_register_hi();
2554 assert(l_lo != r_hi, "overwriting registers");
2555 #endif
2556 switch (code) {
2557 case lir_logic_and:
2558 __ andptr(l_lo, r_lo);
2559 NOT_LP64(__ andptr(l_hi, r_hi);)
2560 break;
2561 case lir_logic_or:
2562 __ orptr(l_lo, r_lo);
2563 NOT_LP64(__ orptr(l_hi, r_hi);)
2564 break;
2565 case lir_logic_xor:
2566 __ xorptr(l_lo, r_lo);
2567 NOT_LP64(__ xorptr(l_hi, r_hi);)
2568 break;
2569 default: ShouldNotReachHere();
2570 }
2571 }
2572
2573 Register dst_lo = dst->as_register_lo();
2574 Register dst_hi = dst->as_register_hi();
2575
2576 #ifdef _LP64
2577 move_regs(l_lo, dst_lo);
2578 #else
2579 if (dst_lo == l_hi) {
2580 assert(dst_hi != l_lo, "overwriting registers");
2581 move_regs(l_hi, dst_hi);
2582 move_regs(l_lo, dst_lo);
2583 } else {
2584 assert(dst_lo != l_hi, "overwriting registers");
2585 move_regs(l_lo, dst_lo);
2586 move_regs(l_hi, dst_hi);
2587 }
2588 #endif // _LP64
2589 }
2590 }
2591
2592
2593 // we assume that rax, and rdx can be overwritten
2594 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2595
2596 assert(left->is_single_cpu(), "left must be register");
2597 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2598 assert(result->is_single_cpu(), "result must be register");
2599
2600 // assert(left->destroys_register(), "check");
2601 // assert(right->destroys_register(), "check");
2602
2603 Register lreg = left->as_register();
2604 Register dreg = result->as_register();
2605
2606 if (right->is_constant()) {
2607 int divisor = right->as_constant_ptr()->as_jint();
2608 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2609 if (code == lir_idiv) {
2610 assert(lreg == rax, "must be rax,");
2611 assert(temp->as_register() == rdx, "tmp register must be rdx");
2612 __ cdql(); // sign extend into rdx:rax
2613 if (divisor == 2) {
2614 __ subl(lreg, rdx);
2615 } else {
2616 __ andl(rdx, divisor - 1);
2617 __ addl(lreg, rdx);
2618 }
2619 __ sarl(lreg, log2_intptr(divisor));
2620 move_regs(lreg, dreg);
2621 } else if (code == lir_irem) {
2622 Label done;
2623 __ mov(dreg, lreg);
2624 __ andl(dreg, 0x80000000 | (divisor - 1));
2625 __ jcc(Assembler::positive, done);
2626 __ decrement(dreg);
2627 __ orl(dreg, ~(divisor - 1));
2628 __ increment(dreg);
2629 __ bind(done);
2630 } else {
2631 ShouldNotReachHere();
2632 }
2633 } else {
2634 Register rreg = right->as_register();
2635 assert(lreg == rax, "left register must be rax,");
2636 assert(rreg != rdx, "right register must not be rdx");
2637 assert(temp->as_register() == rdx, "tmp register must be rdx");
2638
2639 move_regs(lreg, rax);
2640
2641 int idivl_offset = __ corrected_idivl(rreg);
2642 add_debug_info_for_div0(idivl_offset, info);
2643 if (code == lir_irem) {
2644 move_regs(rdx, dreg); // result is in rdx
2645 } else {
2646 move_regs(rax, dreg);
2647 }
2648 }
2649 }
2650
2651
2652 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2653 if (opr1->is_single_cpu()) {
2654 Register reg1 = opr1->as_register();
2655 if (opr2->is_single_cpu()) {
2656 // cpu register - cpu register
2657 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2658 __ cmpptr(reg1, opr2->as_register());
2659 } else {
2660 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2661 __ cmpl(reg1, opr2->as_register());
2662 }
2663 } else if (opr2->is_stack()) {
2664 // cpu register - stack
2665 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2666 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2667 } else {
2668 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2669 }
2670 } else if (opr2->is_constant()) {
2671 // cpu register - constant
2672 LIR_Const* c = opr2->as_constant_ptr();
2673 if (c->type() == T_INT) {
2674 __ cmpl(reg1, c->as_jint());
2675 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2676 // In 64bit oops are single register
2677 jobject o = c->as_jobject();
2678 if (o == NULL) {
2679 __ cmpptr(reg1, (int32_t)NULL_WORD);
2680 } else {
2681 #ifdef _LP64
2682 __ movoop(rscratch1, o);
2683 __ cmpptr(reg1, rscratch1);
2684 #else
2685 __ cmpoop(reg1, c->as_jobject());
2686 #endif // _LP64
2687 }
2688 } else {
2689 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2690 }
2691 // cpu register - address
2692 } else if (opr2->is_address()) {
2693 if (op->info() != NULL) {
2694 add_debug_info_for_null_check_here(op->info());
2695 }
2696 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2697 } else {
2698 ShouldNotReachHere();
2699 }
2700
2701 } else if(opr1->is_double_cpu()) {
2702 Register xlo = opr1->as_register_lo();
2703 Register xhi = opr1->as_register_hi();
2704 if (opr2->is_double_cpu()) {
2705 #ifdef _LP64
2706 __ cmpptr(xlo, opr2->as_register_lo());
2707 #else
2708 // cpu register - cpu register
2709 Register ylo = opr2->as_register_lo();
2710 Register yhi = opr2->as_register_hi();
2711 __ subl(xlo, ylo);
2712 __ sbbl(xhi, yhi);
2713 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2714 __ orl(xhi, xlo);
2715 }
2716 #endif // _LP64
2717 } else if (opr2->is_constant()) {
2718 // cpu register - constant 0
2719 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2720 #ifdef _LP64
2721 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2722 #else
2723 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2724 __ orl(xhi, xlo);
2725 #endif // _LP64
2726 } else {
2727 ShouldNotReachHere();
2728 }
2729
2730 } else if (opr1->is_single_xmm()) {
2731 XMMRegister reg1 = opr1->as_xmm_float_reg();
2732 if (opr2->is_single_xmm()) {
2733 // xmm register - xmm register
2734 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2735 } else if (opr2->is_stack()) {
2736 // xmm register - stack
2737 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2738 } else if (opr2->is_constant()) {
2739 // xmm register - constant
2740 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2741 } else if (opr2->is_address()) {
2742 // xmm register - address
2743 if (op->info() != NULL) {
2744 add_debug_info_for_null_check_here(op->info());
2745 }
2746 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2747 } else {
2748 ShouldNotReachHere();
2749 }
2750
2751 } else if (opr1->is_double_xmm()) {
2752 XMMRegister reg1 = opr1->as_xmm_double_reg();
2753 if (opr2->is_double_xmm()) {
2754 // xmm register - xmm register
2755 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2756 } else if (opr2->is_stack()) {
2757 // xmm register - stack
2758 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2759 } else if (opr2->is_constant()) {
2760 // xmm register - constant
2761 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2762 } else if (opr2->is_address()) {
2763 // xmm register - address
2764 if (op->info() != NULL) {
2765 add_debug_info_for_null_check_here(op->info());
2766 }
2767 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2768 } else {
2769 ShouldNotReachHere();
2770 }
2771
2772 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2773 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2774 assert(opr2->is_fpu_register(), "both must be registers");
2775 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2776
2777 } else if (opr1->is_address() && opr2->is_constant()) {
2778 LIR_Const* c = opr2->as_constant_ptr();
2779 #ifdef _LP64
2780 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2781 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2782 __ movoop(rscratch1, c->as_jobject());
2783 }
2784 #endif // LP64
2785 if (op->info() != NULL) {
2786 add_debug_info_for_null_check_here(op->info());
2787 }
2788 // special case: address - constant
2789 LIR_Address* addr = opr1->as_address_ptr();
2790 if (c->type() == T_INT) {
2791 __ cmpl(as_Address(addr), c->as_jint());
2792 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2793 #ifdef _LP64
2794 // %%% Make this explode if addr isn't reachable until we figure out a
2795 // better strategy by giving noreg as the temp for as_Address
2796 __ cmpptr(rscratch1, as_Address(addr, noreg));
2797 #else
2798 __ cmpoop(as_Address(addr), c->as_jobject());
2799 #endif // _LP64
2800 } else {
2801 ShouldNotReachHere();
2802 }
2803
2804 } else {
2805 ShouldNotReachHere();
2806 }
2807 }
2808
2809 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2810 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2811 if (left->is_single_xmm()) {
2812 assert(right->is_single_xmm(), "must match");
2813 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2814 } else if (left->is_double_xmm()) {
2815 assert(right->is_double_xmm(), "must match");
2816 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2817
2818 } else {
2819 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2820 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2821
2822 assert(left->fpu() == 0, "left must be on TOS");
2823 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2824 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2825 }
2826 } else {
2827 assert(code == lir_cmp_l2i, "check");
2828 #ifdef _LP64
2829 Label done;
2830 Register dest = dst->as_register();
2831 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2832 __ movl(dest, -1);
2833 __ jccb(Assembler::less, done);
2834 __ set_byte_if_not_zero(dest);
2835 __ movzbl(dest, dest);
2836 __ bind(done);
2837 #else
2838 __ lcmp2int(left->as_register_hi(),
2839 left->as_register_lo(),
2840 right->as_register_hi(),
2841 right->as_register_lo());
2842 move_regs(left->as_register_hi(), dst->as_register());
2843 #endif // _LP64
2844 }
2845 }
2846
2847
2848 void LIR_Assembler::align_call(LIR_Code code) {
2849 if (os::is_MP()) {
2850 // make sure that the displacement word of the call ends up word aligned
2851 int offset = __ offset();
2852 switch (code) {
2853 case lir_static_call:
2854 case lir_optvirtual_call:
2855 case lir_dynamic_call:
2856 offset += NativeCall::displacement_offset;
2857 break;
2858 case lir_icvirtual_call:
2859 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2860 break;
2861 case lir_virtual_call: // currently, sparc-specific for niagara
2862 default: ShouldNotReachHere();
2863 }
2864 while (offset++ % BytesPerWord != 0) {
2865 __ nop();
2866 }
2867 }
2868 }
2869
2870
2871 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2872 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2873 "must be aligned");
2874 __ call(AddressLiteral(op->addr(), rtype));
2875 add_call_info(code_offset(), op->info());
2876 }
2877
2878
2879 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2880 __ ic_call(op->addr());
2881 add_call_info(code_offset(), op->info());
2882 assert(!os::is_MP() ||
2883 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2884 "must be aligned");
2885 }
2886
2887
2888 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2889 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2890 ShouldNotReachHere();
2891 }
2892
2893
2894 void LIR_Assembler::emit_static_call_stub() {
2895 address call_pc = __ pc();
2896 address stub = __ start_a_stub(call_stub_size);
2897 if (stub == NULL) {
2898 bailout("static call stub overflow");
2899 return;
2900 }
2901
2902 int start = __ offset();
2903 if (os::is_MP()) {
2904 // make sure that the displacement word of the call ends up word aligned
2905 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2906 while (offset++ % BytesPerWord != 0) {
2907 __ nop();
2908 }
2909 }
2910 __ relocate(static_stub_Relocation::spec(call_pc));
2911 __ mov_metadata(rbx, (Metadata*)NULL);
2912 // must be set to -1 at code generation time
2913 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2914 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2915 __ jump(RuntimeAddress(__ pc()));
2916
2917 assert(__ offset() - start <= call_stub_size, "stub too big");
2918 __ end_a_stub();
2919 }
2920
2921
2922 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2923 assert(exceptionOop->as_register() == rax, "must match");
2924 assert(exceptionPC->as_register() == rdx, "must match");
2925
2926 // exception object is not added to oop map by LinearScan
2927 // (LinearScan assumes that no oops are in fixed registers)
2928 info->add_register_oop(exceptionOop);
2929 Runtime1::StubID unwind_id;
2930
2931 // get current pc information
2932 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2933 int pc_for_athrow_offset = __ offset();
2934 InternalAddress pc_for_athrow(__ pc());
2935 __ lea(exceptionPC->as_register(), pc_for_athrow);
2936 add_call_info(pc_for_athrow_offset, info); // for exception handler
2937
2938 __ verify_not_null_oop(rax);
2939 // search an exception handler (rax: exception oop, rdx: throwing pc)
2940 if (compilation()->has_fpu_code()) {
2941 unwind_id = Runtime1::handle_exception_id;
2942 } else {
2943 unwind_id = Runtime1::handle_exception_nofpu_id;
2944 }
2945 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2946
2947 // enough room for two byte trap
2948 __ nop();
2949 }
2950
2951
2952 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2953 assert(exceptionOop->as_register() == rax, "must match");
2954
2955 __ jmp(_unwind_handler_entry);
2956 }
2957
2958
2959 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2960
2961 // optimized version for linear scan:
2962 // * count must be already in ECX (guaranteed by LinearScan)
2963 // * left and dest must be equal
2964 // * tmp must be unused
2965 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2966 assert(left == dest, "left and dest must be equal");
2967 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2968
2969 if (left->is_single_cpu()) {
2970 Register value = left->as_register();
2971 assert(value != SHIFT_count, "left cannot be ECX");
2972
2973 switch (code) {
2974 case lir_shl: __ shll(value); break;
2975 case lir_shr: __ sarl(value); break;
2976 case lir_ushr: __ shrl(value); break;
2977 default: ShouldNotReachHere();
2978 }
2979 } else if (left->is_double_cpu()) {
2980 Register lo = left->as_register_lo();
2981 Register hi = left->as_register_hi();
2982 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2983 #ifdef _LP64
2984 switch (code) {
2985 case lir_shl: __ shlptr(lo); break;
2986 case lir_shr: __ sarptr(lo); break;
2987 case lir_ushr: __ shrptr(lo); break;
2988 default: ShouldNotReachHere();
2989 }
2990 #else
2991
2992 switch (code) {
2993 case lir_shl: __ lshl(hi, lo); break;
2994 case lir_shr: __ lshr(hi, lo, true); break;
2995 case lir_ushr: __ lshr(hi, lo, false); break;
2996 default: ShouldNotReachHere();
2997 }
2998 #endif // LP64
2999 } else {
3000 ShouldNotReachHere();
3001 }
3002 }
3003
3004
3005 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3006 if (dest->is_single_cpu()) {
3007 // first move left into dest so that left is not destroyed by the shift
3008 Register value = dest->as_register();
3009 count = count & 0x1F; // Java spec
3010
3011 move_regs(left->as_register(), value);
3012 switch (code) {
3013 case lir_shl: __ shll(value, count); break;
3014 case lir_shr: __ sarl(value, count); break;
3015 case lir_ushr: __ shrl(value, count); break;
3016 default: ShouldNotReachHere();
3017 }
3018 } else if (dest->is_double_cpu()) {
3019 #ifndef _LP64
3020 Unimplemented();
3021 #else
3022 // first move left into dest so that left is not destroyed by the shift
3023 Register value = dest->as_register_lo();
3024 count = count & 0x1F; // Java spec
3025
3026 move_regs(left->as_register_lo(), value);
3027 switch (code) {
3028 case lir_shl: __ shlptr(value, count); break;
3029 case lir_shr: __ sarptr(value, count); break;
3030 case lir_ushr: __ shrptr(value, count); break;
3031 default: ShouldNotReachHere();
3032 }
3033 #endif // _LP64
3034 } else {
3035 ShouldNotReachHere();
3036 }
3037 }
3038
3039
3040 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3041 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3042 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3043 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3044 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3045 }
3046
3047
3048 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3049 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3050 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3051 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3052 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3053 }
3054
3055
3056 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3057 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3058 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3059 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3060 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3061 }
3062
3063
3064 // This code replaces a call to arraycopy; no exception may
3065 // be thrown in this code, they must be thrown in the System.arraycopy
3066 // activation frame; we could save some checks if this would not be the case
3067 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3068 ciArrayKlass* default_type = op->expected_type();
3069 Register src = op->src()->as_register();
3070 Register dst = op->dst()->as_register();
3071 Register src_pos = op->src_pos()->as_register();
3072 Register dst_pos = op->dst_pos()->as_register();
3073 Register length = op->length()->as_register();
3074 Register tmp = op->tmp()->as_register();
3075
3076 CodeStub* stub = op->stub();
3077 int flags = op->flags();
3078 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3079 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3080
3081 // if we don't know anything, just go through the generic arraycopy
3082 if (default_type == NULL) {
3083 Label done;
3084 // save outgoing arguments on stack in case call to System.arraycopy is needed
3085 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3086 // for interpreter calling conventions. Now we have to do it in new style conventions.
3087 // For the moment until C1 gets the new register allocator I just force all the
3088 // args to the right place (except the register args) and then on the back side
3089 // reload the register args properly if we go slow path. Yuck
3090
3091 // These are proper for the calling convention
3092 store_parameter(length, 2);
3093 store_parameter(dst_pos, 1);
3094 store_parameter(dst, 0);
3095
3096 // these are just temporary placements until we need to reload
3097 store_parameter(src_pos, 3);
3098 store_parameter(src, 4);
3099 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3100
3101 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3102
3103 address copyfunc_addr = StubRoutines::generic_arraycopy();
3104
3105 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3106 #ifdef _LP64
3107 // The arguments are in java calling convention so we can trivially shift them to C
3108 // convention
3109 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3110 __ mov(c_rarg0, j_rarg0);
3111 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3112 __ mov(c_rarg1, j_rarg1);
3113 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3114 __ mov(c_rarg2, j_rarg2);
3115 assert_different_registers(c_rarg3, j_rarg4);
3116 __ mov(c_rarg3, j_rarg3);
3117 #ifdef _WIN64
3118 // Allocate abi space for args but be sure to keep stack aligned
3119 __ subptr(rsp, 6*wordSize);
3120 store_parameter(j_rarg4, 4);
3121 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3122 __ call(RuntimeAddress(C_entry));
3123 } else {
3124 #ifndef PRODUCT
3125 if (PrintC1Statistics) {
3126 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3127 }
3128 #endif
3129 __ call(RuntimeAddress(copyfunc_addr));
3130 }
3131 __ addptr(rsp, 6*wordSize);
3132 #else
3133 __ mov(c_rarg4, j_rarg4);
3134 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3135 __ call(RuntimeAddress(C_entry));
3136 } else {
3137 #ifndef PRODUCT
3138 if (PrintC1Statistics) {
3139 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3140 }
3141 #endif
3142 __ call(RuntimeAddress(copyfunc_addr));
3143 }
3144 #endif // _WIN64
3145 #else
3146 __ push(length);
3147 __ push(dst_pos);
3148 __ push(dst);
3149 __ push(src_pos);
3150 __ push(src);
3151
3152 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3153 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3154 } else {
3155 #ifndef PRODUCT
3156 if (PrintC1Statistics) {
3157 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3158 }
3159 #endif
3160 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3161 }
3162
3163 #endif // _LP64
3164
3165 __ cmpl(rax, 0);
3166 __ jcc(Assembler::equal, *stub->continuation());
3167
3168 if (copyfunc_addr != NULL) {
3169 __ mov(tmp, rax);
3170 __ xorl(tmp, -1);
3171 }
3172
3173 // Reload values from the stack so they are where the stub
3174 // expects them.
3175 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3176 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3177 __ movptr (length, Address(rsp, 2*BytesPerWord));
3178 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3179 __ movptr (src, Address(rsp, 4*BytesPerWord));
3180
3181 if (copyfunc_addr != NULL) {
3182 __ subl(length, tmp);
3183 __ addl(src_pos, tmp);
3184 __ addl(dst_pos, tmp);
3185 }
3186 __ jmp(*stub->entry());
3187
3188 __ bind(*stub->continuation());
3189 return;
3190 }
3191
3192 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3193
3194 int elem_size = type2aelembytes(basic_type);
3195 int shift_amount;
3196 Address::ScaleFactor scale;
3197
3198 switch (elem_size) {
3199 case 1 :
3200 shift_amount = 0;
3201 scale = Address::times_1;
3202 break;
3203 case 2 :
3204 shift_amount = 1;
3205 scale = Address::times_2;
3206 break;
3207 case 4 :
3208 shift_amount = 2;
3209 scale = Address::times_4;
3210 break;
3211 case 8 :
3212 shift_amount = 3;
3213 scale = Address::times_8;
3214 break;
3215 default:
3216 ShouldNotReachHere();
3217 }
3218
3219 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3220 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3221 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3222 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3223
3224 // length and pos's are all sign extended at this point on 64bit
3225
3226 // test for NULL
3227 if (flags & LIR_OpArrayCopy::src_null_check) {
3228 __ testptr(src, src);
3229 __ jcc(Assembler::zero, *stub->entry());
3230 }
3231 if (flags & LIR_OpArrayCopy::dst_null_check) {
3232 __ testptr(dst, dst);
3233 __ jcc(Assembler::zero, *stub->entry());
3234 }
3235
3236 // check if negative
3237 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3238 __ testl(src_pos, src_pos);
3239 __ jcc(Assembler::less, *stub->entry());
3240 }
3241 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3242 __ testl(dst_pos, dst_pos);
3243 __ jcc(Assembler::less, *stub->entry());
3244 }
3245
3246 if (flags & LIR_OpArrayCopy::src_range_check) {
3247 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3248 __ cmpl(tmp, src_length_addr);
3249 __ jcc(Assembler::above, *stub->entry());
3250 }
3251 if (flags & LIR_OpArrayCopy::dst_range_check) {
3252 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3253 __ cmpl(tmp, dst_length_addr);
3254 __ jcc(Assembler::above, *stub->entry());
3255 }
3256
3257 if (flags & LIR_OpArrayCopy::length_positive_check) {
3258 __ testl(length, length);
3259 __ jcc(Assembler::less, *stub->entry());
3260 __ jcc(Assembler::zero, *stub->continuation());
3261 }
3262
3263 #ifdef _LP64
3264 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3265 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3266 #endif
3267
3268 if (flags & LIR_OpArrayCopy::type_check) {
3269 // We don't know the array types are compatible
3270 if (basic_type != T_OBJECT) {
3271 // Simple test for basic type arrays
3272 if (UseCompressedClassPointers) {
3273 __ movl(tmp, src_klass_addr);
3274 __ cmpl(tmp, dst_klass_addr);
3275 } else {
3276 __ movptr(tmp, src_klass_addr);
3277 __ cmpptr(tmp, dst_klass_addr);
3278 }
3279 __ jcc(Assembler::notEqual, *stub->entry());
3280 } else {
3281 // For object arrays, if src is a sub class of dst then we can
3282 // safely do the copy.
3283 Label cont, slow;
3284
3285 __ push(src);
3286 __ push(dst);
3287
3288 __ load_klass(src, src);
3289 __ load_klass(dst, dst);
3290
3291 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3292
3293 __ push(src);
3294 __ push(dst);
3295 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3296 __ pop(dst);
3297 __ pop(src);
3298
3299 __ cmpl(src, 0);
3300 __ jcc(Assembler::notEqual, cont);
3301
3302 __ bind(slow);
3303 __ pop(dst);
3304 __ pop(src);
3305
3306 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3307 if (copyfunc_addr != NULL) { // use stub if available
3308 // src is not a sub class of dst so we have to do a
3309 // per-element check.
3310
3311 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3312 if ((flags & mask) != mask) {
3313 // Check that at least both of them object arrays.
3314 assert(flags & mask, "one of the two should be known to be an object array");
3315
3316 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3317 __ load_klass(tmp, src);
3318 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3319 __ load_klass(tmp, dst);
3320 }
3321 int lh_offset = in_bytes(Klass::layout_helper_offset());
3322 Address klass_lh_addr(tmp, lh_offset);
3323 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3324 __ cmpl(klass_lh_addr, objArray_lh);
3325 __ jcc(Assembler::notEqual, *stub->entry());
3326 }
3327
3328 // Spill because stubs can use any register they like and it's
3329 // easier to restore just those that we care about.
3330 store_parameter(dst, 0);
3331 store_parameter(dst_pos, 1);
3332 store_parameter(length, 2);
3333 store_parameter(src_pos, 3);
3334 store_parameter(src, 4);
3335
3336 #ifndef _LP64
3337 __ movptr(tmp, dst_klass_addr);
3338 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3339 __ push(tmp);
3340 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3341 __ push(tmp);
3342 __ push(length);
3343 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3344 __ push(tmp);
3345 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3346 __ push(tmp);
3347
3348 __ call_VM_leaf(copyfunc_addr, 5);
3349 #else
3350 __ movl2ptr(length, length); //higher 32bits must be null
3351
3352 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3353 assert_different_registers(c_rarg0, dst, dst_pos, length);
3354 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3355 assert_different_registers(c_rarg1, dst, length);
3356
3357 __ mov(c_rarg2, length);
3358 assert_different_registers(c_rarg2, dst);
3359
3360 #ifdef _WIN64
3361 // Allocate abi space for args but be sure to keep stack aligned
3362 __ subptr(rsp, 6*wordSize);
3363 __ load_klass(c_rarg3, dst);
3364 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3365 store_parameter(c_rarg3, 4);
3366 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3367 __ call(RuntimeAddress(copyfunc_addr));
3368 __ addptr(rsp, 6*wordSize);
3369 #else
3370 __ load_klass(c_rarg4, dst);
3371 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3372 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3373 __ call(RuntimeAddress(copyfunc_addr));
3374 #endif
3375
3376 #endif
3377
3378 #ifndef PRODUCT
3379 if (PrintC1Statistics) {
3380 Label failed;
3381 __ testl(rax, rax);
3382 __ jcc(Assembler::notZero, failed);
3383 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3384 __ bind(failed);
3385 }
3386 #endif
3387
3388 __ testl(rax, rax);
3389 __ jcc(Assembler::zero, *stub->continuation());
3390
3391 #ifndef PRODUCT
3392 if (PrintC1Statistics) {
3393 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3394 }
3395 #endif
3396
3397 __ mov(tmp, rax);
3398
3399 __ xorl(tmp, -1);
3400
3401 // Restore previously spilled arguments
3402 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3403 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3404 __ movptr (length, Address(rsp, 2*BytesPerWord));
3405 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3406 __ movptr (src, Address(rsp, 4*BytesPerWord));
3407
3408
3409 __ subl(length, tmp);
3410 __ addl(src_pos, tmp);
3411 __ addl(dst_pos, tmp);
3412 }
3413
3414 __ jmp(*stub->entry());
3415
3416 __ bind(cont);
3417 __ pop(dst);
3418 __ pop(src);
3419 }
3420 }
3421
3422 #ifdef ASSERT
3423 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3424 // Sanity check the known type with the incoming class. For the
3425 // primitive case the types must match exactly with src.klass and
3426 // dst.klass each exactly matching the default type. For the
3427 // object array case, if no type check is needed then either the
3428 // dst type is exactly the expected type and the src type is a
3429 // subtype which we can't check or src is the same array as dst
3430 // but not necessarily exactly of type default_type.
3431 Label known_ok, halt;
3432 __ mov_metadata(tmp, default_type->constant_encoding());
3433 #ifdef _LP64
3434 if (UseCompressedClassPointers) {
3435 __ encode_klass_not_null(tmp);
3436 }
3437 #endif
3438
3439 if (basic_type != T_OBJECT) {
3440
3441 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3442 else __ cmpptr(tmp, dst_klass_addr);
3443 __ jcc(Assembler::notEqual, halt);
3444 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3445 else __ cmpptr(tmp, src_klass_addr);
3446 __ jcc(Assembler::equal, known_ok);
3447 } else {
3448 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3449 else __ cmpptr(tmp, dst_klass_addr);
3450 __ jcc(Assembler::equal, known_ok);
3451 __ cmpptr(src, dst);
3452 __ jcc(Assembler::equal, known_ok);
3453 }
3454 __ bind(halt);
3455 __ stop("incorrect type information in arraycopy");
3456 __ bind(known_ok);
3457 }
3458 #endif
3459
3460 #ifndef PRODUCT
3461 if (PrintC1Statistics) {
3462 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3463 }
3464 #endif
3465
3466 #ifdef _LP64
3467 assert_different_registers(c_rarg0, dst, dst_pos, length);
3468 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3469 assert_different_registers(c_rarg1, length);
3470 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3471 __ mov(c_rarg2, length);
3472
3473 #else
3474 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3475 store_parameter(tmp, 0);
3476 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3477 store_parameter(tmp, 1);
3478 store_parameter(length, 2);
3479 #endif // _LP64
3480
3481 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3482 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3483 const char *name;
3484 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3485 __ call_VM_leaf(entry, 0);
3486
3487 __ bind(*stub->continuation());
3488 }
3489
3490 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3491 assert(op->crc()->is_single_cpu(), "crc must be register");
3492 assert(op->val()->is_single_cpu(), "byte value must be register");
3493 assert(op->result_opr()->is_single_cpu(), "result must be register");
3494 Register crc = op->crc()->as_register();
3495 Register val = op->val()->as_register();
3496 Register res = op->result_opr()->as_register();
3497
3498 assert_different_registers(val, crc, res);
3499
3500 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3501 __ notl(crc); // ~crc
3502 __ update_byte_crc32(crc, val, res);
3503 __ notl(crc); // ~crc
3504 __ mov(res, crc);
3505 }
3506
3507 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3508 Register obj = op->obj_opr()->as_register(); // may not be an oop
3509 Register hdr = op->hdr_opr()->as_register();
3510 Register lock = op->lock_opr()->as_register();
3511 if (!UseFastLocking) {
3512 __ jmp(*op->stub()->entry());
3513 } else if (op->code() == lir_lock) {
3514 Register scratch = noreg;
3515 if (UseBiasedLocking) {
3516 scratch = op->scratch_opr()->as_register();
3517 }
3518 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3519 // add debug info for NullPointerException only if one is possible
3520 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3521 if (op->info() != NULL) {
3522 add_debug_info_for_null_check(null_check_offset, op->info());
3523 }
3524 // done
3525 } else if (op->code() == lir_unlock) {
3526 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3527 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3528 } else {
3529 Unimplemented();
3530 }
3531 __ bind(*op->stub()->continuation());
3532 }
3533
3534
3535 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3536 ciMethod* method = op->profiled_method();
3537 int bci = op->profiled_bci();
3538 ciMethod* callee = op->profiled_callee();
3539
3540 // Update counter for all call types
3541 ciMethodData* md = method->method_data_or_null();
3542 assert(md != NULL, "Sanity");
3543 ciProfileData* data = md->bci_to_data(bci);
3544 assert(data->is_CounterData(), "need CounterData for calls");
3545 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3546 Register mdo = op->mdo()->as_register();
3547 __ mov_metadata(mdo, md->constant_encoding());
3548 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3549 Bytecodes::Code bc = method->java_code_at_bci(bci);
3550 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3551 // Perform additional virtual call profiling for invokevirtual and
3552 // invokeinterface bytecodes
3553 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3554 !callee_is_static && // required for optimized MH invokes
3555 C1ProfileVirtualCalls) {
3556 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3557 Register recv = op->recv()->as_register();
3558 assert_different_registers(mdo, recv);
3559 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3560 ciKlass* known_klass = op->known_holder();
3561 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3562 // We know the type that will be seen at this call site; we can
3563 // statically update the MethodData* rather than needing to do
3564 // dynamic tests on the receiver type
3565
3566 // NOTE: we should probably put a lock around this search to
3567 // avoid collisions by concurrent compilations
3568 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3569 uint i;
3570 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3571 ciKlass* receiver = vc_data->receiver(i);
3572 if (known_klass->equals(receiver)) {
3573 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3574 __ addptr(data_addr, DataLayout::counter_increment);
3575 return;
3576 }
3577 }
3578
3579 // Receiver type not found in profile data; select an empty slot
3580
3581 // Note that this is less efficient than it should be because it
3582 // always does a write to the receiver part of the
3583 // VirtualCallData rather than just the first time
3584 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3585 ciKlass* receiver = vc_data->receiver(i);
3586 if (receiver == NULL) {
3587 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3588 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3589 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3590 __ addptr(data_addr, DataLayout::counter_increment);
3591 return;
3592 }
3593 }
3594 } else {
3595 __ load_klass(recv, recv);
3596 Label update_done;
3597 type_profile_helper(mdo, md, data, recv, &update_done);
3598 // Receiver did not match any saved receiver and there is no empty row for it.
3599 // Increment total counter to indicate polymorphic case.
3600 __ addptr(counter_addr, DataLayout::counter_increment);
3601
3602 __ bind(update_done);
3603 }
3604 } else {
3605 // Static call
3606 __ addptr(counter_addr, DataLayout::counter_increment);
3607 }
3608 }
3609
3610 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3611 Register obj = op->obj()->as_register();
3612 Register tmp = op->tmp()->as_pointer_register();
3613 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3614 ciKlass* exact_klass = op->exact_klass();
3615 intptr_t current_klass = op->current_klass();
3616 bool not_null = op->not_null();
3617 bool no_conflict = op->no_conflict();
3618
3619 Label update, next, none;
3620
3621 bool do_null = !not_null;
3622 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3623 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3624
3625 assert(do_null || do_update, "why are we here?");
3626 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3627
3628 __ verify_oop(obj);
3629
3630 if (tmp != obj) {
3631 __ mov(tmp, obj);
3632 }
3633 if (do_null) {
3634 __ testptr(tmp, tmp);
3635 __ jccb(Assembler::notZero, update);
3636 if (!TypeEntries::was_null_seen(current_klass)) {
3637 __ orptr(mdo_addr, TypeEntries::null_seen);
3638 }
3639 if (do_update) {
3640 #ifndef ASSERT
3641 __ jmpb(next);
3642 }
3643 #else
3644 __ jmp(next);
3645 }
3646 } else {
3647 __ testptr(tmp, tmp);
3648 __ jccb(Assembler::notZero, update);
3649 __ stop("unexpect null obj");
3650 #endif
3651 }
3652
3653 __ bind(update);
3654
3655 if (do_update) {
3656 #ifdef ASSERT
3657 if (exact_klass != NULL) {
3658 Label ok;
3659 __ load_klass(tmp, tmp);
3660 __ push(tmp);
3661 __ mov_metadata(tmp, exact_klass->constant_encoding());
3662 __ cmpptr(tmp, Address(rsp, 0));
3663 __ jccb(Assembler::equal, ok);
3664 __ stop("exact klass and actual klass differ");
3665 __ bind(ok);
3666 __ pop(tmp);
3667 }
3668 #endif
3669 if (!no_conflict) {
3670 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3671 if (exact_klass != NULL) {
3672 __ mov_metadata(tmp, exact_klass->constant_encoding());
3673 } else {
3674 __ load_klass(tmp, tmp);
3675 }
3676
3677 __ xorptr(tmp, mdo_addr);
3678 __ testptr(tmp, TypeEntries::type_klass_mask);
3679 // klass seen before, nothing to do. The unknown bit may have been
3680 // set already but no need to check.
3681 __ jccb(Assembler::zero, next);
3682
3683 __ testptr(tmp, TypeEntries::type_unknown);
3684 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3685
3686 if (TypeEntries::is_type_none(current_klass)) {
3687 __ cmpptr(mdo_addr, 0);
3688 __ jccb(Assembler::equal, none);
3689 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3690 __ jccb(Assembler::equal, none);
3691 // There is a chance that the checks above (re-reading profiling
3692 // data from memory) fail if another thread has just set the
3693 // profiling to this obj's klass
3694 __ xorptr(tmp, mdo_addr);
3695 __ testptr(tmp, TypeEntries::type_klass_mask);
3696 __ jccb(Assembler::zero, next);
3697 }
3698 } else {
3699 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3700 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3701
3702 __ movptr(tmp, mdo_addr);
3703 __ testptr(tmp, TypeEntries::type_unknown);
3704 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3705 }
3706
3707 // different than before. Cannot keep accurate profile.
3708 __ orptr(mdo_addr, TypeEntries::type_unknown);
3709
3710 if (TypeEntries::is_type_none(current_klass)) {
3711 __ jmpb(next);
3712
3713 __ bind(none);
3714 // first time here. Set profile type.
3715 __ movptr(mdo_addr, tmp);
3716 }
3717 } else {
3718 // There's a single possible klass at this profile point
3719 assert(exact_klass != NULL, "should be");
3720 if (TypeEntries::is_type_none(current_klass)) {
3721 __ mov_metadata(tmp, exact_klass->constant_encoding());
3722 __ xorptr(tmp, mdo_addr);
3723 __ testptr(tmp, TypeEntries::type_klass_mask);
3724 #ifdef ASSERT
3725 __ jcc(Assembler::zero, next);
3726
3727 {
3728 Label ok;
3729 __ push(tmp);
3730 __ cmpptr(mdo_addr, 0);
3731 __ jcc(Assembler::equal, ok);
3732 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3733 __ jcc(Assembler::equal, ok);
3734 // may have been set by another thread
3735 __ mov_metadata(tmp, exact_klass->constant_encoding());
3736 __ xorptr(tmp, mdo_addr);
3737 __ testptr(tmp, TypeEntries::type_mask);
3738 __ jcc(Assembler::zero, ok);
3739
3740 __ stop("unexpected profiling mismatch");
3741 __ bind(ok);
3742 __ pop(tmp);
3743 }
3744 #else
3745 __ jccb(Assembler::zero, next);
3746 #endif
3747 // first time here. Set profile type.
3748 __ movptr(mdo_addr, tmp);
3749 } else {
3750 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3751 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3752
3753 __ movptr(tmp, mdo_addr);
3754 __ testptr(tmp, TypeEntries::type_unknown);
3755 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3756
3757 __ orptr(mdo_addr, TypeEntries::type_unknown);
3758 }
3759 }
3760
3761 __ bind(next);
3762 }
3763 }
3764
3765 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3766 Unimplemented();
3767 }
3768
3769
3770 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3771 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3772 }
3773
3774
3775 void LIR_Assembler::align_backward_branch_target() {
3776 __ align(BytesPerWord);
3777 }
3778
3779
3780 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3781 if (left->is_single_cpu()) {
3782 __ negl(left->as_register());
3783 move_regs(left->as_register(), dest->as_register());
3784
3785 } else if (left->is_double_cpu()) {
3786 Register lo = left->as_register_lo();
3787 #ifdef _LP64
3788 Register dst = dest->as_register_lo();
3789 __ movptr(dst, lo);
3790 __ negptr(dst);
3791 #else
3792 Register hi = left->as_register_hi();
3793 __ lneg(hi, lo);
3794 if (dest->as_register_lo() == hi) {
3795 assert(dest->as_register_hi() != lo, "destroying register");
3796 move_regs(hi, dest->as_register_hi());
3797 move_regs(lo, dest->as_register_lo());
3798 } else {
3799 move_regs(lo, dest->as_register_lo());
3800 move_regs(hi, dest->as_register_hi());
3801 }
3802 #endif // _LP64
3803
3804 } else if (dest->is_single_xmm()) {
3805 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3806 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3807 }
3808 __ xorps(dest->as_xmm_float_reg(),
3809 ExternalAddress((address)float_signflip_pool));
3810
3811 } else if (dest->is_double_xmm()) {
3812 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3813 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3814 }
3815 __ xorpd(dest->as_xmm_double_reg(),
3816 ExternalAddress((address)double_signflip_pool));
3817
3818 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3819 assert(left->fpu() == 0, "arg must be on TOS");
3820 assert(dest->fpu() == 0, "dest must be TOS");
3821 __ fchs();
3822
3823 } else {
3824 ShouldNotReachHere();
3825 }
3826 }
3827
3828
3829 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3830 assert(addr->is_address() && dest->is_register(), "check");
3831 Register reg;
3832 reg = dest->as_pointer_register();
3833 __ lea(reg, as_Address(addr->as_address_ptr()));
3834 }
3835
3836
3837
3838 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3839 assert(!tmp->is_valid(), "don't need temporary");
3840 __ call(RuntimeAddress(dest));
3841 if (info != NULL) {
3842 add_call_info_here(info);
3843 }
3844 }
3845
3846
3847 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3848 assert(type == T_LONG, "only for volatile long fields");
3849
3850 if (info != NULL) {
3851 add_debug_info_for_null_check_here(info);
3852 }
3853
3854 if (src->is_double_xmm()) {
3855 if (dest->is_double_cpu()) {
3856 #ifdef _LP64
3857 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3858 #else
3859 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3860 __ psrlq(src->as_xmm_double_reg(), 32);
3861 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3862 #endif // _LP64
3863 } else if (dest->is_double_stack()) {
3864 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3865 } else if (dest->is_address()) {
3866 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3867 } else {
3868 ShouldNotReachHere();
3869 }
3870
3871 } else if (dest->is_double_xmm()) {
3872 if (src->is_double_stack()) {
3873 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3874 } else if (src->is_address()) {
3875 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3876 } else {
3877 ShouldNotReachHere();
3878 }
3879
3880 } else if (src->is_double_fpu()) {
3881 assert(src->fpu_regnrLo() == 0, "must be TOS");
3882 if (dest->is_double_stack()) {
3883 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3884 } else if (dest->is_address()) {
3885 __ fistp_d(as_Address(dest->as_address_ptr()));
3886 } else {
3887 ShouldNotReachHere();
3888 }
3889
3890 } else if (dest->is_double_fpu()) {
3891 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3892 if (src->is_double_stack()) {
3893 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3894 } else if (src->is_address()) {
3895 __ fild_d(as_Address(src->as_address_ptr()));
3896 } else {
3897 ShouldNotReachHere();
3898 }
3899 } else {
3900 ShouldNotReachHere();
3901 }
3902 }
3903
3904 #ifdef ASSERT
3905 // emit run-time assertion
3906 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3907 assert(op->code() == lir_assert, "must be");
3908
3909 if (op->in_opr1()->is_valid()) {
3910 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3911 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3912 } else {
3913 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3914 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3915 }
3916
3917 Label ok;
3918 if (op->condition() != lir_cond_always) {
3919 Assembler::Condition acond = Assembler::zero;
3920 switch (op->condition()) {
3921 case lir_cond_equal: acond = Assembler::equal; break;
3922 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3923 case lir_cond_less: acond = Assembler::less; break;
3924 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3925 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3926 case lir_cond_greater: acond = Assembler::greater; break;
3927 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3928 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3929 default: ShouldNotReachHere();
3930 }
3931 __ jcc(acond, ok);
3932 }
3933 if (op->halt()) {
3934 const char* str = __ code_string(op->msg());
3935 __ stop(str);
3936 } else {
3937 breakpoint();
3938 }
3939 __ bind(ok);
3940 }
3941 #endif
3942
3943 void LIR_Assembler::membar() {
3944 // QQQ sparc TSO uses this,
3945 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3946 }
3947
3948 void LIR_Assembler::membar_acquire() {
3949 // No x86 machines currently require load fences
3950 }
3951
3952 void LIR_Assembler::membar_release() {
3953 // No x86 machines currently require store fences
3954 }
3955
3956 void LIR_Assembler::membar_loadload() {
3957 // no-op
3958 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3959 }
3960
3961 void LIR_Assembler::membar_storestore() {
3962 // no-op
3963 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3964 }
3965
3966 void LIR_Assembler::membar_loadstore() {
3967 // no-op
3968 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3969 }
3970
3971 void LIR_Assembler::membar_storeload() {
3972 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3973 }
3974
3975 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3976 assert(result_reg->is_register(), "check");
3977 #ifdef _LP64
3978 // __ get_thread(result_reg->as_register_lo());
3979 __ mov(result_reg->as_register(), r15_thread);
3980 #else
3981 __ get_thread(result_reg->as_register());
3982 #endif // _LP64
3983 }
3984
3985
3986 void LIR_Assembler::peephole(LIR_List*) {
3987 // do nothing for now
3988 }
3989
3990 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3991 assert(data == dest, "xchg/xadd uses only 2 operands");
3992
3993 if (data->type() == T_INT) {
3994 if (code == lir_xadd) {
3995 if (os::is_MP()) {
3996 __ lock();
3997 }
3998 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3999 } else {
4000 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4001 }
4002 } else if (data->is_oop()) {
4003 assert (code == lir_xchg, "xadd for oops");
4004 Register obj = data->as_register();
4005 #ifdef _LP64
4006 if (UseCompressedOops) {
4007 __ encode_heap_oop(obj);
4008 __ xchgl(obj, as_Address(src->as_address_ptr()));
4009 __ decode_heap_oop(obj);
4010 } else {
4011 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4012 }
4013 #else
4014 __ xchgl(obj, as_Address(src->as_address_ptr()));
4015 #endif
4016 } else if (data->type() == T_LONG) {
4017 #ifdef _LP64
4018 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4019 if (code == lir_xadd) {
4020 if (os::is_MP()) {
4021 __ lock();
4022 }
4023 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4024 } else {
4025 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4026 }
4027 #else
4028 ShouldNotReachHere();
4029 #endif
4030 } else {
4031 ShouldNotReachHere();
4032 }
4033 }
4034
4035 #undef __