1 /*
2 * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2018, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/codeBuffer.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "gc/shared/cardTableBarrierSet.hpp"
35 #include "memory/resourceArea.hpp"
36 #include "memory/universe.hpp"
37 #include "oops/compressedOops.inline.hpp"
38 #include "oops/klass.inline.hpp"
39 #include "opto/compile.hpp"
40 #include "opto/intrinsicnode.hpp"
41 #include "opto/matcher.hpp"
42 #include "prims/methodHandles.hpp"
43 #include "registerSaver_s390.hpp"
44 #include "runtime/biasedLocking.hpp"
45 #include "runtime/icache.hpp"
46 #include "runtime/interfaceSupport.inline.hpp"
47 #include "runtime/objectMonitor.hpp"
48 #include "runtime/os.hpp"
49 #include "runtime/safepoint.hpp"
50 #include "runtime/safepointMechanism.hpp"
51 #include "runtime/sharedRuntime.hpp"
52 #include "runtime/stubRoutines.hpp"
53 #include "utilities/events.hpp"
54 #include "utilities/macros.hpp"
55
56 #include <ucontext.h>
57
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
60
61 // Move 32-bit register if destination and source are different.
62 void MacroAssembler::lr_if_needed(Register rd, Register rs) {
63 if (rs != rd) { z_lr(rd, rs); }
64 }
65
66 // Move register if destination and source are different.
67 void MacroAssembler::lgr_if_needed(Register rd, Register rs) {
68 if (rs != rd) { z_lgr(rd, rs); }
69 }
70
71 // Zero-extend 32-bit register into 64-bit register if destination and source are different.
72 void MacroAssembler::llgfr_if_needed(Register rd, Register rs) {
73 if (rs != rd) { z_llgfr(rd, rs); }
74 }
75
76 // Move float register if destination and source are different.
77 void MacroAssembler::ldr_if_needed(FloatRegister rd, FloatRegister rs) {
78 if (rs != rd) { z_ldr(rd, rs); }
79 }
80
81 // Move integer register if destination and source are different.
82 // It is assumed that shorter-than-int types are already
83 // appropriately sign-extended.
84 void MacroAssembler::move_reg_if_needed(Register dst, BasicType dst_type, Register src,
85 BasicType src_type) {
86 assert((dst_type != T_FLOAT) && (dst_type != T_DOUBLE), "use move_freg for float types");
87 assert((src_type != T_FLOAT) && (src_type != T_DOUBLE), "use move_freg for float types");
88
89 if (dst_type == src_type) {
90 lgr_if_needed(dst, src); // Just move all 64 bits.
91 return;
92 }
93
94 switch (dst_type) {
95 // Do not support these types for now.
96 // case T_BOOLEAN:
97 case T_BYTE: // signed byte
98 switch (src_type) {
99 case T_INT:
100 z_lgbr(dst, src);
101 break;
102 default:
103 ShouldNotReachHere();
104 }
105 return;
106
107 case T_CHAR:
108 case T_SHORT:
109 switch (src_type) {
110 case T_INT:
111 if (dst_type == T_CHAR) {
112 z_llghr(dst, src);
113 } else {
114 z_lghr(dst, src);
115 }
116 break;
117 default:
118 ShouldNotReachHere();
119 }
120 return;
121
122 case T_INT:
123 switch (src_type) {
124 case T_BOOLEAN:
125 case T_BYTE:
126 case T_CHAR:
127 case T_SHORT:
128 case T_INT:
129 case T_LONG:
130 case T_OBJECT:
131 case T_ARRAY:
132 case T_VOID:
133 case T_ADDRESS:
134 lr_if_needed(dst, src);
135 // llgfr_if_needed(dst, src); // zero-extend (in case we need to find a bug).
136 return;
137
138 default:
139 assert(false, "non-integer src type");
140 return;
141 }
142 case T_LONG:
143 switch (src_type) {
144 case T_BOOLEAN:
145 case T_BYTE:
146 case T_CHAR:
147 case T_SHORT:
148 case T_INT:
149 z_lgfr(dst, src); // sign extension
150 return;
151
152 case T_LONG:
153 case T_OBJECT:
154 case T_ARRAY:
155 case T_VOID:
156 case T_ADDRESS:
157 lgr_if_needed(dst, src);
158 return;
159
160 default:
161 assert(false, "non-integer src type");
162 return;
163 }
164 return;
165 case T_OBJECT:
166 case T_ARRAY:
167 case T_VOID:
168 case T_ADDRESS:
169 switch (src_type) {
170 // These types don't make sense to be converted to pointers:
171 // case T_BOOLEAN:
172 // case T_BYTE:
173 // case T_CHAR:
174 // case T_SHORT:
175
176 case T_INT:
177 z_llgfr(dst, src); // zero extension
178 return;
179
180 case T_LONG:
181 case T_OBJECT:
182 case T_ARRAY:
183 case T_VOID:
184 case T_ADDRESS:
185 lgr_if_needed(dst, src);
186 return;
187
188 default:
189 assert(false, "non-integer src type");
190 return;
191 }
192 return;
193 default:
194 assert(false, "non-integer dst type");
195 return;
196 }
197 }
198
199 // Move float register if destination and source are different.
200 void MacroAssembler::move_freg_if_needed(FloatRegister dst, BasicType dst_type,
201 FloatRegister src, BasicType src_type) {
202 assert((dst_type == T_FLOAT) || (dst_type == T_DOUBLE), "use move_reg for int types");
203 assert((src_type == T_FLOAT) || (src_type == T_DOUBLE), "use move_reg for int types");
204 if (dst_type == src_type) {
205 ldr_if_needed(dst, src); // Just move all 64 bits.
206 } else {
207 switch (dst_type) {
208 case T_FLOAT:
209 assert(src_type == T_DOUBLE, "invalid float type combination");
210 z_ledbr(dst, src);
211 return;
212 case T_DOUBLE:
213 assert(src_type == T_FLOAT, "invalid float type combination");
214 z_ldebr(dst, src);
215 return;
216 default:
217 assert(false, "non-float dst type");
218 return;
219 }
220 }
221 }
222
223 // Optimized emitter for reg to mem operations.
224 // Uses modern instructions if running on modern hardware, classic instructions
225 // otherwise. Prefers (usually shorter) classic instructions if applicable.
226 // Data register (reg) cannot be used as work register.
227 //
228 // Don't rely on register locking, instead pass a scratch register (Z_R0 by default).
229 // CAUTION! Passing registers >= Z_R2 may produce bad results on old CPUs!
230 void MacroAssembler::freg2mem_opt(FloatRegister reg,
231 int64_t disp,
232 Register index,
233 Register base,
234 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
235 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
236 Register scratch) {
237 index = (index == noreg) ? Z_R0 : index;
238 if (Displacement::is_shortDisp(disp)) {
239 (this->*classic)(reg, disp, index, base);
240 } else {
241 if (Displacement::is_validDisp(disp)) {
242 (this->*modern)(reg, disp, index, base);
243 } else {
244 if (scratch != Z_R0 && scratch != Z_R1) {
245 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
246 } else {
247 if (scratch != Z_R0) { // scratch == Z_R1
248 if ((scratch == index) || (index == base)) {
249 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
250 } else {
251 add2reg(scratch, disp, base);
252 (this->*classic)(reg, 0, index, scratch);
253 if (base == scratch) {
254 add2reg(base, -disp); // Restore base.
255 }
256 }
257 } else { // scratch == Z_R0
258 z_lgr(scratch, base);
259 add2reg(base, disp);
260 (this->*classic)(reg, 0, index, base);
261 z_lgr(base, scratch); // Restore base.
262 }
263 }
264 }
265 }
266 }
267
268 void MacroAssembler::freg2mem_opt(FloatRegister reg, const Address &a, bool is_double) {
269 if (is_double) {
270 freg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_stdy), CLASSIC_FFUN(z_std));
271 } else {
272 freg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_stey), CLASSIC_FFUN(z_ste));
273 }
274 }
275
276 // Optimized emitter for mem to reg operations.
277 // Uses modern instructions if running on modern hardware, classic instructions
278 // otherwise. Prefers (usually shorter) classic instructions if applicable.
279 // data register (reg) cannot be used as work register.
280 //
281 // Don't rely on register locking, instead pass a scratch register (Z_R0 by default).
282 // CAUTION! Passing registers >= Z_R2 may produce bad results on old CPUs!
283 void MacroAssembler::mem2freg_opt(FloatRegister reg,
284 int64_t disp,
285 Register index,
286 Register base,
287 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
288 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
289 Register scratch) {
290 index = (index == noreg) ? Z_R0 : index;
291 if (Displacement::is_shortDisp(disp)) {
292 (this->*classic)(reg, disp, index, base);
293 } else {
294 if (Displacement::is_validDisp(disp)) {
295 (this->*modern)(reg, disp, index, base);
296 } else {
297 if (scratch != Z_R0 && scratch != Z_R1) {
298 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
299 } else {
300 if (scratch != Z_R0) { // scratch == Z_R1
301 if ((scratch == index) || (index == base)) {
302 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
303 } else {
304 add2reg(scratch, disp, base);
305 (this->*classic)(reg, 0, index, scratch);
306 if (base == scratch) {
307 add2reg(base, -disp); // Restore base.
308 }
309 }
310 } else { // scratch == Z_R0
311 z_lgr(scratch, base);
312 add2reg(base, disp);
313 (this->*classic)(reg, 0, index, base);
314 z_lgr(base, scratch); // Restore base.
315 }
316 }
317 }
318 }
319 }
320
321 void MacroAssembler::mem2freg_opt(FloatRegister reg, const Address &a, bool is_double) {
322 if (is_double) {
323 mem2freg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_ldy), CLASSIC_FFUN(z_ld));
324 } else {
325 mem2freg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_ley), CLASSIC_FFUN(z_le));
326 }
327 }
328
329 // Optimized emitter for reg to mem operations.
330 // Uses modern instructions if running on modern hardware, classic instructions
331 // otherwise. Prefers (usually shorter) classic instructions if applicable.
332 // Data register (reg) cannot be used as work register.
333 //
334 // Don't rely on register locking, instead pass a scratch register
335 // (Z_R0 by default)
336 // CAUTION! passing registers >= Z_R2 may produce bad results on old CPUs!
337 void MacroAssembler::reg2mem_opt(Register reg,
338 int64_t disp,
339 Register index,
340 Register base,
341 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
342 void (MacroAssembler::*classic)(Register, int64_t, Register, Register),
343 Register scratch) {
344 index = (index == noreg) ? Z_R0 : index;
345 if (Displacement::is_shortDisp(disp)) {
346 (this->*classic)(reg, disp, index, base);
347 } else {
348 if (Displacement::is_validDisp(disp)) {
349 (this->*modern)(reg, disp, index, base);
350 } else {
351 if (scratch != Z_R0 && scratch != Z_R1) {
352 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
353 } else {
354 if (scratch != Z_R0) { // scratch == Z_R1
355 if ((scratch == index) || (index == base)) {
356 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
357 } else {
358 add2reg(scratch, disp, base);
359 (this->*classic)(reg, 0, index, scratch);
360 if (base == scratch) {
361 add2reg(base, -disp); // Restore base.
362 }
363 }
364 } else { // scratch == Z_R0
365 if ((scratch == reg) || (scratch == base) || (reg == base)) {
366 (this->*modern)(reg, disp, index, base); // Will fail with disp out of range.
367 } else {
368 z_lgr(scratch, base);
369 add2reg(base, disp);
370 (this->*classic)(reg, 0, index, base);
371 z_lgr(base, scratch); // Restore base.
372 }
373 }
374 }
375 }
376 }
377 }
378
379 int MacroAssembler::reg2mem_opt(Register reg, const Address &a, bool is_double) {
380 int store_offset = offset();
381 if (is_double) {
382 reg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_stg), CLASSIC_IFUN(z_stg));
383 } else {
384 reg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_sty), CLASSIC_IFUN(z_st));
385 }
386 return store_offset;
387 }
388
389 // Optimized emitter for mem to reg operations.
390 // Uses modern instructions if running on modern hardware, classic instructions
391 // otherwise. Prefers (usually shorter) classic instructions if applicable.
392 // Data register (reg) will be used as work register where possible.
393 void MacroAssembler::mem2reg_opt(Register reg,
394 int64_t disp,
395 Register index,
396 Register base,
397 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
398 void (MacroAssembler::*classic)(Register, int64_t, Register, Register)) {
399 index = (index == noreg) ? Z_R0 : index;
400 if (Displacement::is_shortDisp(disp)) {
401 (this->*classic)(reg, disp, index, base);
402 } else {
403 if (Displacement::is_validDisp(disp)) {
404 (this->*modern)(reg, disp, index, base);
405 } else {
406 if ((reg == index) && (reg == base)) {
407 z_sllg(reg, reg, 1);
408 add2reg(reg, disp);
409 (this->*classic)(reg, 0, noreg, reg);
410 } else if ((reg == index) && (reg != Z_R0)) {
411 add2reg(reg, disp);
412 (this->*classic)(reg, 0, reg, base);
413 } else if (reg == base) {
414 add2reg(reg, disp);
415 (this->*classic)(reg, 0, index, reg);
416 } else if (reg != Z_R0) {
417 add2reg(reg, disp, base);
418 (this->*classic)(reg, 0, index, reg);
419 } else { // reg == Z_R0 && reg != base here
420 add2reg(base, disp);
421 (this->*classic)(reg, 0, index, base);
422 add2reg(base, -disp);
423 }
424 }
425 }
426 }
427
428 void MacroAssembler::mem2reg_opt(Register reg, const Address &a, bool is_double) {
429 if (is_double) {
430 z_lg(reg, a);
431 } else {
432 mem2reg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_ly), CLASSIC_IFUN(z_l));
433 }
434 }
435
436 void MacroAssembler::mem2reg_signed_opt(Register reg, const Address &a) {
437 mem2reg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_lgf), CLASSIC_IFUN(z_lgf));
438 }
439
440 void MacroAssembler::and_imm(Register r, long mask,
441 Register tmp /* = Z_R0 */,
442 bool wide /* = false */) {
443 assert(wide || Immediate::is_simm32(mask), "mask value too large");
444
445 if (!wide) {
446 z_nilf(r, mask);
447 return;
448 }
449
450 assert(r != tmp, " need a different temporary register !");
451 load_const_optimized(tmp, mask);
452 z_ngr(r, tmp);
453 }
454
455 // Calculate the 1's complement.
456 // Note: The condition code is neither preserved nor correctly set by this code!!!
457 // Note: (wide == false) does not protect the high order half of the target register
458 // from alteration. It only serves as optimization hint for 32-bit results.
459 void MacroAssembler::not_(Register r1, Register r2, bool wide) {
460
461 if ((r2 == noreg) || (r2 == r1)) { // Calc 1's complement in place.
462 z_xilf(r1, -1);
463 if (wide) {
464 z_xihf(r1, -1);
465 }
466 } else { // Distinct src and dst registers.
467 if (VM_Version::has_DistinctOpnds()) {
468 load_const_optimized(r1, -1);
469 z_xgrk(r1, r2, r1);
470 } else {
471 if (wide) {
472 z_lgr(r1, r2);
473 z_xilf(r1, -1);
474 z_xihf(r1, -1);
475 } else {
476 z_lr(r1, r2);
477 z_xilf(r1, -1);
478 }
479 }
480 }
481 }
482
483 unsigned long MacroAssembler::create_mask(int lBitPos, int rBitPos) {
484 assert(lBitPos >= 0, "zero is leftmost bit position");
485 assert(rBitPos <= 63, "63 is rightmost bit position");
486 assert(lBitPos <= rBitPos, "inverted selection interval");
487 return (lBitPos == 0 ? (unsigned long)(-1L) : ((1UL<<(63-lBitPos+1))-1)) & (~((1UL<<(63-rBitPos))-1));
488 }
489
490 // Helper function for the "Rotate_then_<logicalOP>" emitters.
491 // Rotate src, then mask register contents such that only bits in range survive.
492 // For oneBits == false, all bits not in range are set to 0. Useful for deleting all bits outside range.
493 // For oneBits == true, all bits not in range are set to 1. Useful for preserving all bits outside range.
494 // The caller must ensure that the selected range only contains bits with defined value.
495 void MacroAssembler::rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
496 int nRotate, bool src32bit, bool dst32bit, bool oneBits) {
497 assert(!(dst32bit && lBitPos < 32), "selection interval out of range for int destination");
498 bool sll4rll = (nRotate >= 0) && (nRotate <= (63-rBitPos)); // Substitute SLL(G) for RLL(G).
499 bool srl4rll = (nRotate < 0) && (-nRotate <= lBitPos); // Substitute SRL(G) for RLL(G).
500 // Pre-determine which parts of dst will be zero after shift/rotate.
501 bool llZero = sll4rll && (nRotate >= 16);
502 bool lhZero = (sll4rll && (nRotate >= 32)) || (srl4rll && (nRotate <= -48));
503 bool lfZero = llZero && lhZero;
504 bool hlZero = (sll4rll && (nRotate >= 48)) || (srl4rll && (nRotate <= -32));
505 bool hhZero = (srl4rll && (nRotate <= -16));
506 bool hfZero = hlZero && hhZero;
507
508 // rotate then mask src operand.
509 // if oneBits == true, all bits outside selected range are 1s.
510 // if oneBits == false, all bits outside selected range are 0s.
511 if (src32bit) { // There might be garbage in the upper 32 bits which will get masked away.
512 if (dst32bit) {
513 z_rll(dst, src, nRotate); // Copy and rotate, upper half of reg remains undisturbed.
514 } else {
515 if (sll4rll) { z_sllg(dst, src, nRotate); }
516 else if (srl4rll) { z_srlg(dst, src, -nRotate); }
517 else { z_rllg(dst, src, nRotate); }
518 }
519 } else {
520 if (sll4rll) { z_sllg(dst, src, nRotate); }
521 else if (srl4rll) { z_srlg(dst, src, -nRotate); }
522 else { z_rllg(dst, src, nRotate); }
523 }
524
525 unsigned long range_mask = create_mask(lBitPos, rBitPos);
526 unsigned int range_mask_h = (unsigned int)(range_mask >> 32);
527 unsigned int range_mask_l = (unsigned int)range_mask;
528 unsigned short range_mask_hh = (unsigned short)(range_mask >> 48);
529 unsigned short range_mask_hl = (unsigned short)(range_mask >> 32);
530 unsigned short range_mask_lh = (unsigned short)(range_mask >> 16);
531 unsigned short range_mask_ll = (unsigned short)range_mask;
532 // Works for z9 and newer H/W.
533 if (oneBits) {
534 if ((~range_mask_l) != 0) { z_oilf(dst, ~range_mask_l); } // All bits outside range become 1s.
535 if (((~range_mask_h) != 0) && !dst32bit) { z_oihf(dst, ~range_mask_h); }
536 } else {
537 // All bits outside range become 0s
538 if (((~range_mask_l) != 0) && !lfZero) {
539 z_nilf(dst, range_mask_l);
540 }
541 if (((~range_mask_h) != 0) && !dst32bit && !hfZero) {
542 z_nihf(dst, range_mask_h);
543 }
544 }
545 }
546
547 // Rotate src, then insert selected range from rotated src into dst.
548 // Clear dst before, if requested.
549 void MacroAssembler::rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos,
550 int nRotate, bool clear_dst) {
551 // This version does not depend on src being zero-extended int2long.
552 nRotate &= 0x003f; // For risbg, pretend it's an unsigned value.
553 z_risbg(dst, src, lBitPos, rBitPos, nRotate, clear_dst); // Rotate, then insert selected, clear the rest.
554 }
555
556 // Rotate src, then and selected range from rotated src into dst.
557 // Set condition code only if so requested. Otherwise it is unpredictable.
558 // See performance note in macroAssembler_s390.hpp for important information.
559 void MacroAssembler::rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos,
560 int nRotate, bool test_only) {
561 guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
562 // This version does not depend on src being zero-extended int2long.
563 nRotate &= 0x003f; // For risbg, pretend it's an unsigned value.
564 z_rxsbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
565 }
566
567 // Rotate src, then or selected range from rotated src into dst.
568 // Set condition code only if so requested. Otherwise it is unpredictable.
569 // See performance note in macroAssembler_s390.hpp for important information.
570 void MacroAssembler::rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos,
571 int nRotate, bool test_only) {
572 guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
573 // This version does not depend on src being zero-extended int2long.
574 nRotate &= 0x003f; // For risbg, pretend it's an unsigned value.
575 z_rosbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
576 }
577
578 // Rotate src, then xor selected range from rotated src into dst.
579 // Set condition code only if so requested. Otherwise it is unpredictable.
580 // See performance note in macroAssembler_s390.hpp for important information.
581 void MacroAssembler::rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos,
582 int nRotate, bool test_only) {
583 guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
584 // This version does not depend on src being zero-extended int2long.
585 nRotate &= 0x003f; // For risbg, pretend it's an unsigned value.
586 z_rxsbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
587 }
588
589 void MacroAssembler::add64(Register r1, RegisterOrConstant inc) {
590 if (inc.is_register()) {
591 z_agr(r1, inc.as_register());
592 } else { // constant
593 intptr_t imm = inc.as_constant();
594 add2reg(r1, imm);
595 }
596 }
597 // Helper function to multiply the 64bit contents of a register by a 16bit constant.
598 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
599 // calculation and is thus rather slow.
600 //
601 // There is no handling for special cases, e.g. cval==0 or cval==1.
602 //
603 // Returns len of generated code block.
604 unsigned int MacroAssembler::mul_reg64_const16(Register rval, Register work, int cval) {
605 int block_start = offset();
606
607 bool sign_flip = cval < 0;
608 cval = sign_flip ? -cval : cval;
609
610 BLOCK_COMMENT("Reg64*Con16 {");
611
612 int bit1 = cval & -cval;
613 if (bit1 == cval) {
614 z_sllg(rval, rval, exact_log2(bit1));
615 if (sign_flip) { z_lcgr(rval, rval); }
616 } else {
617 int bit2 = (cval-bit1) & -(cval-bit1);
618 if ((bit1+bit2) == cval) {
619 z_sllg(work, rval, exact_log2(bit1));
620 z_sllg(rval, rval, exact_log2(bit2));
621 z_agr(rval, work);
622 if (sign_flip) { z_lcgr(rval, rval); }
623 } else {
624 if (sign_flip) { z_mghi(rval, -cval); }
625 else { z_mghi(rval, cval); }
626 }
627 }
628 BLOCK_COMMENT("} Reg64*Con16");
629
630 int block_end = offset();
631 return block_end - block_start;
632 }
633
634 // Generic operation r1 := r2 + imm.
635 //
636 // Should produce the best code for each supported CPU version.
637 // r2 == noreg yields r1 := r1 + imm
638 // imm == 0 emits either no instruction or r1 := r2 !
639 // NOTES: 1) Don't use this function where fixed sized
640 // instruction sequences are required!!!
641 // 2) Don't use this function if condition code
642 // setting is required!
643 // 3) Despite being declared as int64_t, the parameter imm
644 // must be a simm_32 value (= signed 32-bit integer).
645 void MacroAssembler::add2reg(Register r1, int64_t imm, Register r2) {
646 assert(Immediate::is_simm32(imm), "probably an implicit conversion went wrong");
647
648 if (r2 == noreg) { r2 = r1; }
649
650 // Handle special case imm == 0.
651 if (imm == 0) {
652 lgr_if_needed(r1, r2);
653 // Nothing else to do.
654 return;
655 }
656
657 if (!PreferLAoverADD || (r2 == Z_R0)) {
658 bool distinctOpnds = VM_Version::has_DistinctOpnds();
659
660 // Can we encode imm in 16 bits signed?
661 if (Immediate::is_simm16(imm)) {
662 if (r1 == r2) {
663 z_aghi(r1, imm);
664 return;
665 }
666 if (distinctOpnds) {
667 z_aghik(r1, r2, imm);
668 return;
669 }
670 z_lgr(r1, r2);
671 z_aghi(r1, imm);
672 return;
673 }
674 } else {
675 // Can we encode imm in 12 bits unsigned?
676 if (Displacement::is_shortDisp(imm)) {
677 z_la(r1, imm, r2);
678 return;
679 }
680 // Can we encode imm in 20 bits signed?
681 if (Displacement::is_validDisp(imm)) {
682 // Always use LAY instruction, so we don't need the tmp register.
683 z_lay(r1, imm, r2);
684 return;
685 }
686
687 }
688
689 // Can handle it (all possible values) with long immediates.
690 lgr_if_needed(r1, r2);
691 z_agfi(r1, imm);
692 }
693
694 // Generic operation r := b + x + d
695 //
696 // Addition of several operands with address generation semantics - sort of:
697 // - no restriction on the registers. Any register will do for any operand.
698 // - x == noreg: operand will be disregarded.
699 // - b == noreg: will use (contents of) result reg as operand (r := r + d).
700 // - x == Z_R0: just disregard
701 // - b == Z_R0: use as operand. This is not address generation semantics!!!
702 //
703 // The same restrictions as on add2reg() are valid!!!
704 void MacroAssembler::add2reg_with_index(Register r, int64_t d, Register x, Register b) {
705 assert(Immediate::is_simm32(d), "probably an implicit conversion went wrong");
706
707 if (x == noreg) { x = Z_R0; }
708 if (b == noreg) { b = r; }
709
710 // Handle special case x == R0.
711 if (x == Z_R0) {
712 // Can simply add the immediate value to the base register.
713 add2reg(r, d, b);
714 return;
715 }
716
717 if (!PreferLAoverADD || (b == Z_R0)) {
718 bool distinctOpnds = VM_Version::has_DistinctOpnds();
719 // Handle special case d == 0.
720 if (d == 0) {
721 if (b == x) { z_sllg(r, b, 1); return; }
722 if (r == x) { z_agr(r, b); return; }
723 if (r == b) { z_agr(r, x); return; }
724 if (distinctOpnds) { z_agrk(r, x, b); return; }
725 z_lgr(r, b);
726 z_agr(r, x);
727 } else {
728 if (x == b) { z_sllg(r, x, 1); }
729 else if (r == x) { z_agr(r, b); }
730 else if (r == b) { z_agr(r, x); }
731 else if (distinctOpnds) { z_agrk(r, x, b); }
732 else {
733 z_lgr(r, b);
734 z_agr(r, x);
735 }
736 add2reg(r, d);
737 }
738 } else {
739 // Can we encode imm in 12 bits unsigned?
740 if (Displacement::is_shortDisp(d)) {
741 z_la(r, d, x, b);
742 return;
743 }
744 // Can we encode imm in 20 bits signed?
745 if (Displacement::is_validDisp(d)) {
746 z_lay(r, d, x, b);
747 return;
748 }
749 z_la(r, 0, x, b);
750 add2reg(r, d);
751 }
752 }
753
754 // Generic emitter (32bit) for direct memory increment.
755 // For optimal code, do not specify Z_R0 as temp register.
756 void MacroAssembler::add2mem_32(const Address &a, int64_t imm, Register tmp) {
757 if (VM_Version::has_MemWithImmALUOps() && Immediate::is_simm8(imm)) {
758 z_asi(a, imm);
759 } else {
760 z_lgf(tmp, a);
761 add2reg(tmp, imm);
762 z_st(tmp, a);
763 }
764 }
765
766 void MacroAssembler::add2mem_64(const Address &a, int64_t imm, Register tmp) {
767 if (VM_Version::has_MemWithImmALUOps() && Immediate::is_simm8(imm)) {
768 z_agsi(a, imm);
769 } else {
770 z_lg(tmp, a);
771 add2reg(tmp, imm);
772 z_stg(tmp, a);
773 }
774 }
775
776 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
777 switch (size_in_bytes) {
778 case 8: z_lg(dst, src); break;
779 case 4: is_signed ? z_lgf(dst, src) : z_llgf(dst, src); break;
780 case 2: is_signed ? z_lgh(dst, src) : z_llgh(dst, src); break;
781 case 1: is_signed ? z_lgb(dst, src) : z_llgc(dst, src); break;
782 default: ShouldNotReachHere();
783 }
784 }
785
786 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
787 switch (size_in_bytes) {
788 case 8: z_stg(src, dst); break;
789 case 4: z_st(src, dst); break;
790 case 2: z_sth(src, dst); break;
791 case 1: z_stc(src, dst); break;
792 default: ShouldNotReachHere();
793 }
794 }
795
796 // Split a si20 offset (20bit, signed) into an ui12 offset (12bit, unsigned) and
797 // a high-order summand in register tmp.
798 //
799 // return value: < 0: No split required, si20 actually has property uimm12.
800 // >= 0: Split performed. Use return value as uimm12 displacement and
801 // tmp as index register.
802 int MacroAssembler::split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate) {
803 assert(Immediate::is_simm20(si20_offset), "sanity");
804 int lg_off = (int)si20_offset & 0x0fff; // Punch out low-order 12 bits, always positive.
805 int ll_off = (int)si20_offset & ~0x0fff; // Force low-order 12 bits to zero.
806 assert((Displacement::is_shortDisp(si20_offset) && (ll_off == 0)) ||
807 !Displacement::is_shortDisp(si20_offset), "unexpected offset values");
808 assert((lg_off+ll_off) == si20_offset, "offset splitup error");
809
810 Register work = accumulate? Z_R0 : tmp;
811
812 if (fixed_codelen) { // Len of code = 10 = 4 + 6.
813 z_lghi(work, ll_off>>12); // Implicit sign extension.
814 z_slag(work, work, 12);
815 } else { // Len of code = 0..10.
816 if (ll_off == 0) { return -1; }
817 // ll_off has 8 significant bits (at most) plus sign.
818 if ((ll_off & 0x0000f000) == 0) { // Non-zero bits only in upper halfbyte.
819 z_llilh(work, ll_off >> 16);
820 if (ll_off < 0) { // Sign-extension required.
821 z_lgfr(work, work);
822 }
823 } else {
824 if ((ll_off & 0x000f0000) == 0) { // Non-zero bits only in lower halfbyte.
825 z_llill(work, ll_off);
826 } else { // Non-zero bits in both halfbytes.
827 z_lghi(work, ll_off>>12); // Implicit sign extension.
828 z_slag(work, work, 12);
829 }
830 }
831 }
832 if (accumulate) { z_algr(tmp, work); } // len of code += 4
833 return lg_off;
834 }
835
836 void MacroAssembler::load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp) {
837 if (Displacement::is_validDisp(si20)) {
838 z_ley(t, si20, a);
839 } else {
840 // Fixed_codelen = true is a simple way to ensure that the size of load_float_largeoffset
841 // does not depend on si20 (scratch buffer emit size == code buffer emit size for constant
842 // pool loads).
843 bool accumulate = true;
844 bool fixed_codelen = true;
845 Register work;
846
847 if (fixed_codelen) {
848 z_lgr(tmp, a); // Lgr_if_needed not applicable due to fixed_codelen.
849 } else {
850 accumulate = (a == tmp);
851 }
852 work = tmp;
853
854 int disp12 = split_largeoffset(si20, work, fixed_codelen, accumulate);
855 if (disp12 < 0) {
856 z_le(t, si20, work);
857 } else {
858 if (accumulate) {
859 z_le(t, disp12, work);
860 } else {
861 z_le(t, disp12, work, a);
862 }
863 }
864 }
865 }
866
867 void MacroAssembler::load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp) {
868 if (Displacement::is_validDisp(si20)) {
869 z_ldy(t, si20, a);
870 } else {
871 // Fixed_codelen = true is a simple way to ensure that the size of load_double_largeoffset
872 // does not depend on si20 (scratch buffer emit size == code buffer emit size for constant
873 // pool loads).
874 bool accumulate = true;
875 bool fixed_codelen = true;
876 Register work;
877
878 if (fixed_codelen) {
879 z_lgr(tmp, a); // Lgr_if_needed not applicable due to fixed_codelen.
880 } else {
881 accumulate = (a == tmp);
882 }
883 work = tmp;
884
885 int disp12 = split_largeoffset(si20, work, fixed_codelen, accumulate);
886 if (disp12 < 0) {
887 z_ld(t, si20, work);
888 } else {
889 if (accumulate) {
890 z_ld(t, disp12, work);
891 } else {
892 z_ld(t, disp12, work, a);
893 }
894 }
895 }
896 }
897
898 // PCrelative TOC access.
899 // Returns distance (in bytes) from current position to start of consts section.
900 // Returns 0 (zero) if no consts section exists or if it has size zero.
901 long MacroAssembler::toc_distance() {
902 CodeSection* cs = code()->consts();
903 return (long)((cs != NULL) ? cs->start()-pc() : 0);
904 }
905
906 // Implementation on x86/sparc assumes that constant and instruction section are
907 // adjacent, but this doesn't hold. Two special situations may occur, that we must
908 // be able to handle:
909 // 1. const section may be located apart from the inst section.
910 // 2. const section may be empty
911 // In both cases, we use the const section's start address to compute the "TOC",
912 // this seems to occur only temporarily; in the final step we always seem to end up
913 // with the pc-relatice variant.
914 //
915 // PC-relative offset could be +/-2**32 -> use long for disp
916 // Furthermore: makes no sense to have special code for
917 // adjacent const and inst sections.
918 void MacroAssembler::load_toc(Register Rtoc) {
919 // Simply use distance from start of const section (should be patched in the end).
920 long disp = toc_distance();
921
922 RelocationHolder rspec = internal_word_Relocation::spec(pc() + disp);
923 relocate(rspec);
924 z_larl(Rtoc, RelAddr::pcrel_off32(disp)); // Offset is in halfwords.
925 }
926
927 // PCrelative TOC access.
928 // Load from anywhere pcrelative (with relocation of load instr)
929 void MacroAssembler::load_long_pcrelative(Register Rdst, address dataLocation) {
930 address pc = this->pc();
931 ptrdiff_t total_distance = dataLocation - pc;
932 RelocationHolder rspec = internal_word_Relocation::spec(dataLocation);
933
934 assert((total_distance & 0x01L) == 0, "halfword alignment is mandatory");
935 assert(total_distance != 0, "sanity");
936
937 // Some extra safety net.
938 if (!RelAddr::is_in_range_of_RelAddr32(total_distance)) {
939 guarantee(RelAddr::is_in_range_of_RelAddr32(total_distance), "load_long_pcrelative can't handle distance " INTPTR_FORMAT, total_distance);
940 }
941
942 (this)->relocate(rspec, relocInfo::pcrel_addr_format);
943 z_lgrl(Rdst, RelAddr::pcrel_off32(total_distance));
944 }
945
946
947 // PCrelative TOC access.
948 // Load from anywhere pcrelative (with relocation of load instr)
949 // loaded addr has to be relocated when added to constant pool.
950 void MacroAssembler::load_addr_pcrelative(Register Rdst, address addrLocation) {
951 address pc = this->pc();
952 ptrdiff_t total_distance = addrLocation - pc;
953 RelocationHolder rspec = internal_word_Relocation::spec(addrLocation);
954
955 assert((total_distance & 0x01L) == 0, "halfword alignment is mandatory");
956
957 // Some extra safety net.
958 if (!RelAddr::is_in_range_of_RelAddr32(total_distance)) {
959 guarantee(RelAddr::is_in_range_of_RelAddr32(total_distance), "load_long_pcrelative can't handle distance " INTPTR_FORMAT, total_distance);
960 }
961
962 (this)->relocate(rspec, relocInfo::pcrel_addr_format);
963 z_lgrl(Rdst, RelAddr::pcrel_off32(total_distance));
964 }
965
966 // Generic operation: load a value from memory and test.
967 // CondCode indicates the sign (<0, ==0, >0) of the loaded value.
968 void MacroAssembler::load_and_test_byte(Register dst, const Address &a) {
969 z_lb(dst, a);
970 z_ltr(dst, dst);
971 }
972
973 void MacroAssembler::load_and_test_short(Register dst, const Address &a) {
974 int64_t disp = a.disp20();
975 if (Displacement::is_shortDisp(disp)) {
976 z_lh(dst, a);
977 } else if (Displacement::is_longDisp(disp)) {
978 z_lhy(dst, a);
979 } else {
980 guarantee(false, "displacement out of range");
981 }
982 z_ltr(dst, dst);
983 }
984
985 void MacroAssembler::load_and_test_int(Register dst, const Address &a) {
986 z_lt(dst, a);
987 }
988
989 void MacroAssembler::load_and_test_int2long(Register dst, const Address &a) {
990 z_ltgf(dst, a);
991 }
992
993 void MacroAssembler::load_and_test_long(Register dst, const Address &a) {
994 z_ltg(dst, a);
995 }
996
997 // Test a bit in memory.
998 void MacroAssembler::testbit(const Address &a, unsigned int bit) {
999 assert(a.index() == noreg, "no index reg allowed in testbit");
1000 if (bit <= 7) {
1001 z_tm(a.disp() + 3, a.base(), 1 << bit);
1002 } else if (bit <= 15) {
1003 z_tm(a.disp() + 2, a.base(), 1 << (bit - 8));
1004 } else if (bit <= 23) {
1005 z_tm(a.disp() + 1, a.base(), 1 << (bit - 16));
1006 } else if (bit <= 31) {
1007 z_tm(a.disp() + 0, a.base(), 1 << (bit - 24));
1008 } else {
1009 ShouldNotReachHere();
1010 }
1011 }
1012
1013 // Test a bit in a register. Result is reflected in CC.
1014 void MacroAssembler::testbit(Register r, unsigned int bitPos) {
1015 if (bitPos < 16) {
1016 z_tmll(r, 1U<<bitPos);
1017 } else if (bitPos < 32) {
1018 z_tmlh(r, 1U<<(bitPos-16));
1019 } else if (bitPos < 48) {
1020 z_tmhl(r, 1U<<(bitPos-32));
1021 } else if (bitPos < 64) {
1022 z_tmhh(r, 1U<<(bitPos-48));
1023 } else {
1024 ShouldNotReachHere();
1025 }
1026 }
1027
1028 void MacroAssembler::prefetch_read(Address a) {
1029 z_pfd(1, a.disp20(), a.indexOrR0(), a.base());
1030 }
1031 void MacroAssembler::prefetch_update(Address a) {
1032 z_pfd(2, a.disp20(), a.indexOrR0(), a.base());
1033 }
1034
1035 // Clear a register, i.e. load const zero into reg.
1036 // Return len (in bytes) of generated instruction(s).
1037 // whole_reg: Clear 64 bits if true, 32 bits otherwise.
1038 // set_cc: Use instruction that sets the condition code, if true.
1039 int MacroAssembler::clear_reg(Register r, bool whole_reg, bool set_cc) {
1040 unsigned int start_off = offset();
1041 if (whole_reg) {
1042 set_cc ? z_xgr(r, r) : z_laz(r, 0, Z_R0);
1043 } else { // Only 32bit register.
1044 set_cc ? z_xr(r, r) : z_lhi(r, 0);
1045 }
1046 return offset() - start_off;
1047 }
1048
1049 #ifdef ASSERT
1050 int MacroAssembler::preset_reg(Register r, unsigned long pattern, int pattern_len) {
1051 switch (pattern_len) {
1052 case 1:
1053 pattern = (pattern & 0x000000ff) | ((pattern & 0x000000ff)<<8);
1054 case 2:
1055 pattern = (pattern & 0x0000ffff) | ((pattern & 0x0000ffff)<<16);
1056 case 4:
1057 pattern = (pattern & 0xffffffffL) | ((pattern & 0xffffffffL)<<32);
1058 case 8:
1059 return load_const_optimized_rtn_len(r, pattern, true);
1060 break;
1061 default:
1062 guarantee(false, "preset_reg: bad len");
1063 }
1064 return 0;
1065 }
1066 #endif
1067
1068 // addr: Address descriptor of memory to clear index register will not be used !
1069 // size: Number of bytes to clear.
1070 // !!! DO NOT USE THEM FOR ATOMIC MEMORY CLEARING !!!
1071 // !!! Use store_const() instead !!!
1072 void MacroAssembler::clear_mem(const Address& addr, unsigned size) {
1073 guarantee(size <= 256, "MacroAssembler::clear_mem: size too large");
1074
1075 if (size == 1) {
1076 z_mvi(addr, 0);
1077 return;
1078 }
1079
1080 switch (size) {
1081 case 2: z_mvhhi(addr, 0);
1082 return;
1083 case 4: z_mvhi(addr, 0);
1084 return;
1085 case 8: z_mvghi(addr, 0);
1086 return;
1087 default: ; // Fallthru to xc.
1088 }
1089
1090 z_xc(addr, size, addr);
1091 }
1092
1093 void MacroAssembler::align(int modulus) {
1094 while (offset() % modulus != 0) z_nop();
1095 }
1096
1097 // Special version for non-relocateable code if required alignment
1098 // is larger than CodeEntryAlignment.
1099 void MacroAssembler::align_address(int modulus) {
1100 while ((uintptr_t)pc() % modulus != 0) z_nop();
1101 }
1102
1103 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1104 Register temp_reg,
1105 int64_t extra_slot_offset) {
1106 // On Z, we can have index and disp in an Address. So don't call argument_offset,
1107 // which issues an unnecessary add instruction.
1108 int stackElementSize = Interpreter::stackElementSize;
1109 int64_t offset = extra_slot_offset * stackElementSize;
1110 const Register argbase = Z_esp;
1111 if (arg_slot.is_constant()) {
1112 offset += arg_slot.as_constant() * stackElementSize;
1113 return Address(argbase, offset);
1114 }
1115 // else
1116 assert(temp_reg != noreg, "must specify");
1117 assert(temp_reg != Z_ARG1, "base and index are conflicting");
1118 z_sllg(temp_reg, arg_slot.as_register(), exact_log2(stackElementSize)); // tempreg = arg_slot << 3
1119 return Address(argbase, temp_reg, offset);
1120 }
1121
1122
1123 //===================================================================
1124 //=== START C O N S T A N T S I N C O D E S T R E A M ===
1125 //===================================================================
1126 //=== P A T CH A B L E C O N S T A N T S ===
1127 //===================================================================
1128
1129
1130 //---------------------------------------------------
1131 // Load (patchable) constant into register
1132 //---------------------------------------------------
1133
1134
1135 // Load absolute address (and try to optimize).
1136 // Note: This method is usable only for position-fixed code,
1137 // referring to a position-fixed target location.
1138 // If not so, relocations and patching must be used.
1139 void MacroAssembler::load_absolute_address(Register d, address addr) {
1140 assert(addr != NULL, "should not happen");
1141 BLOCK_COMMENT("load_absolute_address:");
1142 if (addr == NULL) {
1143 z_larl(d, pc()); // Dummy emit for size calc.
1144 return;
1145 }
1146
1147 if (RelAddr::is_in_range_of_RelAddr32(addr, pc())) {
1148 z_larl(d, addr);
1149 return;
1150 }
1151
1152 load_const_optimized(d, (long)addr);
1153 }
1154
1155 // Load a 64bit constant.
1156 // Patchable code sequence, but not atomically patchable.
1157 // Make sure to keep code size constant -> no value-dependent optimizations.
1158 // Do not kill condition code.
1159 void MacroAssembler::load_const(Register t, long x) {
1160 Assembler::z_iihf(t, (int)(x >> 32));
1161 Assembler::z_iilf(t, (int)(x & 0xffffffff));
1162 }
1163
1164 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1165 // Patchable code sequence, but not atomically patchable.
1166 // Make sure to keep code size constant -> no value-dependent optimizations.
1167 // Do not kill condition code.
1168 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1169 if (sign_extend) { Assembler::z_lgfi(t, x); }
1170 else { Assembler::z_llilf(t, x); }
1171 }
1172
1173 // Load narrow oop constant, no decompression.
1174 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1175 assert(UseCompressedOops, "must be on to call this method");
1176 load_const_32to64(t, a, false /*sign_extend*/);
1177 }
1178
1179 // Load narrow klass constant, compression required.
1180 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1181 assert(UseCompressedClassPointers, "must be on to call this method");
1182 narrowKlass encoded_k = Klass::encode_klass(k);
1183 load_const_32to64(t, encoded_k, false /*sign_extend*/);
1184 }
1185
1186 //------------------------------------------------------
1187 // Compare (patchable) constant with register.
1188 //------------------------------------------------------
1189
1190 // Compare narrow oop in reg with narrow oop constant, no decompression.
1191 void MacroAssembler::compare_immediate_narrow_oop(Register oop1, narrowOop oop2) {
1192 assert(UseCompressedOops, "must be on to call this method");
1193
1194 Assembler::z_clfi(oop1, oop2);
1195 }
1196
1197 // Compare narrow oop in reg with narrow oop constant, no decompression.
1198 void MacroAssembler::compare_immediate_narrow_klass(Register klass1, Klass* klass2) {
1199 assert(UseCompressedClassPointers, "must be on to call this method");
1200 narrowKlass encoded_k = Klass::encode_klass(klass2);
1201
1202 Assembler::z_clfi(klass1, encoded_k);
1203 }
1204
1205 //----------------------------------------------------------
1206 // Check which kind of load_constant we have here.
1207 //----------------------------------------------------------
1208
1209 // Detection of CPU version dependent load_const sequence.
1210 // The detection is valid only for code sequences generated by load_const,
1211 // not load_const_optimized.
1212 bool MacroAssembler::is_load_const(address a) {
1213 unsigned long inst1, inst2;
1214 unsigned int len1, len2;
1215
1216 len1 = get_instruction(a, &inst1);
1217 len2 = get_instruction(a + len1, &inst2);
1218
1219 return is_z_iihf(inst1) && is_z_iilf(inst2);
1220 }
1221
1222 // Detection of CPU version dependent load_const_32to64 sequence.
1223 // Mostly used for narrow oops and narrow Klass pointers.
1224 // The detection is valid only for code sequences generated by load_const_32to64.
1225 bool MacroAssembler::is_load_const_32to64(address pos) {
1226 unsigned long inst1, inst2;
1227 unsigned int len1;
1228
1229 len1 = get_instruction(pos, &inst1);
1230 return is_z_llilf(inst1);
1231 }
1232
1233 // Detection of compare_immediate_narrow sequence.
1234 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1235 bool MacroAssembler::is_compare_immediate32(address pos) {
1236 return is_equal(pos, CLFI_ZOPC, RIL_MASK);
1237 }
1238
1239 // Detection of compare_immediate_narrow sequence.
1240 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1241 bool MacroAssembler::is_compare_immediate_narrow_oop(address pos) {
1242 return is_compare_immediate32(pos);
1243 }
1244
1245 // Detection of compare_immediate_narrow sequence.
1246 // The detection is valid only for code sequences generated by compare_immediate_narrow_klass.
1247 bool MacroAssembler::is_compare_immediate_narrow_klass(address pos) {
1248 return is_compare_immediate32(pos);
1249 }
1250
1251 //-----------------------------------
1252 // patch the load_constant
1253 //-----------------------------------
1254
1255 // CPU-version dependend patching of load_const.
1256 void MacroAssembler::patch_const(address a, long x) {
1257 assert(is_load_const(a), "not a load of a constant");
1258 set_imm32((address)a, (int) ((x >> 32) & 0xffffffff));
1259 set_imm32((address)(a + 6), (int)(x & 0xffffffff));
1260 }
1261
1262 // Patching the value of CPU version dependent load_const_32to64 sequence.
1263 // The passed ptr MUST be in compressed format!
1264 int MacroAssembler::patch_load_const_32to64(address pos, int64_t np) {
1265 assert(is_load_const_32to64(pos), "not a load of a narrow ptr (oop or klass)");
1266
1267 set_imm32(pos, np);
1268 return 6;
1269 }
1270
1271 // Patching the value of CPU version dependent compare_immediate_narrow sequence.
1272 // The passed ptr MUST be in compressed format!
1273 int MacroAssembler::patch_compare_immediate_32(address pos, int64_t np) {
1274 assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1275
1276 set_imm32(pos, np);
1277 return 6;
1278 }
1279
1280 // Patching the immediate value of CPU version dependent load_narrow_oop sequence.
1281 // The passed ptr must NOT be in compressed format!
1282 int MacroAssembler::patch_load_narrow_oop(address pos, oop o) {
1283 assert(UseCompressedOops, "Can only patch compressed oops");
1284
1285 narrowOop no = CompressedOops::encode(o);
1286 return patch_load_const_32to64(pos, no);
1287 }
1288
1289 // Patching the immediate value of CPU version dependent load_narrow_klass sequence.
1290 // The passed ptr must NOT be in compressed format!
1291 int MacroAssembler::patch_load_narrow_klass(address pos, Klass* k) {
1292 assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1293
1294 narrowKlass nk = Klass::encode_klass(k);
1295 return patch_load_const_32to64(pos, nk);
1296 }
1297
1298 // Patching the immediate value of CPU version dependent compare_immediate_narrow_oop sequence.
1299 // The passed ptr must NOT be in compressed format!
1300 int MacroAssembler::patch_compare_immediate_narrow_oop(address pos, oop o) {
1301 assert(UseCompressedOops, "Can only patch compressed oops");
1302
1303 narrowOop no = CompressedOops::encode(o);
1304 return patch_compare_immediate_32(pos, no);
1305 }
1306
1307 // Patching the immediate value of CPU version dependent compare_immediate_narrow_klass sequence.
1308 // The passed ptr must NOT be in compressed format!
1309 int MacroAssembler::patch_compare_immediate_narrow_klass(address pos, Klass* k) {
1310 assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1311
1312 narrowKlass nk = Klass::encode_klass(k);
1313 return patch_compare_immediate_32(pos, nk);
1314 }
1315
1316 //------------------------------------------------------------------------
1317 // Extract the constant from a load_constant instruction stream.
1318 //------------------------------------------------------------------------
1319
1320 // Get constant from a load_const sequence.
1321 long MacroAssembler::get_const(address a) {
1322 assert(is_load_const(a), "not a load of a constant");
1323 unsigned long x;
1324 x = (((unsigned long) (get_imm32(a,0) & 0xffffffff)) << 32);
1325 x |= (((unsigned long) (get_imm32(a,1) & 0xffffffff)));
1326 return (long) x;
1327 }
1328
1329 //--------------------------------------
1330 // Store a constant in memory.
1331 //--------------------------------------
1332
1333 // General emitter to move a constant to memory.
1334 // The store is atomic.
1335 // o Address must be given in RS format (no index register)
1336 // o Displacement should be 12bit unsigned for efficiency. 20bit signed also supported.
1337 // o Constant can be 1, 2, 4, or 8 bytes, signed or unsigned.
1338 // o Memory slot can be 1, 2, 4, or 8 bytes, signed or unsigned.
1339 // o Memory slot must be at least as wide as constant, will assert otherwise.
1340 // o Signed constants will sign-extend, unsigned constants will zero-extend to slot width.
1341 int MacroAssembler::store_const(const Address &dest, long imm,
1342 unsigned int lm, unsigned int lc,
1343 Register scratch) {
1344 int64_t disp = dest.disp();
1345 Register base = dest.base();
1346 assert(!dest.has_index(), "not supported");
1347 assert((lm==1)||(lm==2)||(lm==4)||(lm==8), "memory length not supported");
1348 assert((lc==1)||(lc==2)||(lc==4)||(lc==8), "constant length not supported");
1349 assert(lm>=lc, "memory slot too small");
1350 assert(lc==8 || Immediate::is_simm(imm, lc*8), "const out of range");
1351 assert(Displacement::is_validDisp(disp), "displacement out of range");
1352
1353 bool is_shortDisp = Displacement::is_shortDisp(disp);
1354 int store_offset = -1;
1355
1356 // For target len == 1 it's easy.
1357 if (lm == 1) {
1358 store_offset = offset();
1359 if (is_shortDisp) {
1360 z_mvi(disp, base, imm);
1361 return store_offset;
1362 } else {
1363 z_mviy(disp, base, imm);
1364 return store_offset;
1365 }
1366 }
1367
1368 // All the "good stuff" takes an unsigned displacement.
1369 if (is_shortDisp) {
1370 // NOTE: Cannot use clear_mem for imm==0, because it is not atomic.
1371
1372 store_offset = offset();
1373 switch (lm) {
1374 case 2: // Lc == 1 handled correctly here, even for unsigned. Instruction does no widening.
1375 z_mvhhi(disp, base, imm);
1376 return store_offset;
1377 case 4:
1378 if (Immediate::is_simm16(imm)) {
1379 z_mvhi(disp, base, imm);
1380 return store_offset;
1381 }
1382 break;
1383 case 8:
1384 if (Immediate::is_simm16(imm)) {
1385 z_mvghi(disp, base, imm);
1386 return store_offset;
1387 }
1388 break;
1389 default:
1390 ShouldNotReachHere();
1391 break;
1392 }
1393 }
1394
1395 // Can't optimize, so load value and store it.
1396 guarantee(scratch != noreg, " need a scratch register here !");
1397 if (imm != 0) {
1398 load_const_optimized(scratch, imm); // Preserves CC anyway.
1399 } else {
1400 // Leave CC alone!!
1401 (void) clear_reg(scratch, true, false); // Indicate unused result.
1402 }
1403
1404 store_offset = offset();
1405 if (is_shortDisp) {
1406 switch (lm) {
1407 case 2:
1408 z_sth(scratch, disp, Z_R0, base);
1409 return store_offset;
1410 case 4:
1411 z_st(scratch, disp, Z_R0, base);
1412 return store_offset;
1413 case 8:
1414 z_stg(scratch, disp, Z_R0, base);
1415 return store_offset;
1416 default:
1417 ShouldNotReachHere();
1418 break;
1419 }
1420 } else {
1421 switch (lm) {
1422 case 2:
1423 z_sthy(scratch, disp, Z_R0, base);
1424 return store_offset;
1425 case 4:
1426 z_sty(scratch, disp, Z_R0, base);
1427 return store_offset;
1428 case 8:
1429 z_stg(scratch, disp, Z_R0, base);
1430 return store_offset;
1431 default:
1432 ShouldNotReachHere();
1433 break;
1434 }
1435 }
1436 return -1; // should not reach here
1437 }
1438
1439 //===================================================================
1440 //=== N O T P A T CH A B L E C O N S T A N T S ===
1441 //===================================================================
1442
1443 // Load constant x into register t with a fast instrcution sequence
1444 // depending on the bits in x. Preserves CC under all circumstances.
1445 int MacroAssembler::load_const_optimized_rtn_len(Register t, long x, bool emit) {
1446 if (x == 0) {
1447 int len;
1448 if (emit) {
1449 len = clear_reg(t, true, false);
1450 } else {
1451 len = 4;
1452 }
1453 return len;
1454 }
1455
1456 if (Immediate::is_simm16(x)) {
1457 if (emit) { z_lghi(t, x); }
1458 return 4;
1459 }
1460
1461 // 64 bit value: | part1 | part2 | part3 | part4 |
1462 // At least one part is not zero!
1463 int part1 = ((x >> 32) & 0xffff0000) >> 16;
1464 int part2 = (x >> 32) & 0x0000ffff;
1465 int part3 = (x & 0xffff0000) >> 16;
1466 int part4 = (x & 0x0000ffff);
1467
1468 // Lower word only (unsigned).
1469 if ((part1 == 0) && (part2 == 0)) {
1470 if (part3 == 0) {
1471 if (emit) z_llill(t, part4);
1472 return 4;
1473 }
1474 if (part4 == 0) {
1475 if (emit) z_llilh(t, part3);
1476 return 4;
1477 }
1478 if (emit) z_llilf(t, (int)(x & 0xffffffff));
1479 return 6;
1480 }
1481
1482 // Upper word only.
1483 if ((part3 == 0) && (part4 == 0)) {
1484 if (part1 == 0) {
1485 if (emit) z_llihl(t, part2);
1486 return 4;
1487 }
1488 if (part2 == 0) {
1489 if (emit) z_llihh(t, part1);
1490 return 4;
1491 }
1492 if (emit) z_llihf(t, (int)(x >> 32));
1493 return 6;
1494 }
1495
1496 // Lower word only (signed).
1497 if ((part1 == 0x0000ffff) && (part2 == 0x0000ffff) && ((part3 & 0x00008000) != 0)) {
1498 if (emit) z_lgfi(t, (int)(x & 0xffffffff));
1499 return 6;
1500 }
1501
1502 int len = 0;
1503
1504 if ((part1 == 0) || (part2 == 0)) {
1505 if (part1 == 0) {
1506 if (emit) z_llihl(t, part2);
1507 len += 4;
1508 } else {
1509 if (emit) z_llihh(t, part1);
1510 len += 4;
1511 }
1512 } else {
1513 if (emit) z_llihf(t, (int)(x >> 32));
1514 len += 6;
1515 }
1516
1517 if ((part3 == 0) || (part4 == 0)) {
1518 if (part3 == 0) {
1519 if (emit) z_iill(t, part4);
1520 len += 4;
1521 } else {
1522 if (emit) z_iilh(t, part3);
1523 len += 4;
1524 }
1525 } else {
1526 if (emit) z_iilf(t, (int)(x & 0xffffffff));
1527 len += 6;
1528 }
1529 return len;
1530 }
1531
1532 //=====================================================================
1533 //=== H I G H E R L E V E L B R A N C H E M I T T E R S ===
1534 //=====================================================================
1535
1536 // Note: In the worst case, one of the scratch registers is destroyed!!!
1537 void MacroAssembler::compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1538 // Right operand is constant.
1539 if (x2.is_constant()) {
1540 jlong value = x2.as_constant();
1541 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/true);
1542 return;
1543 }
1544
1545 // Right operand is in register.
1546 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/true);
1547 }
1548
1549 // Note: In the worst case, one of the scratch registers is destroyed!!!
1550 void MacroAssembler::compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1551 // Right operand is constant.
1552 if (x2.is_constant()) {
1553 jlong value = x2.as_constant();
1554 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/false);
1555 return;
1556 }
1557
1558 // Right operand is in register.
1559 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/false);
1560 }
1561
1562 // Note: In the worst case, one of the scratch registers is destroyed!!!
1563 void MacroAssembler::compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1564 // Right operand is constant.
1565 if (x2.is_constant()) {
1566 jlong value = x2.as_constant();
1567 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/true, /*has_sign=*/true);
1568 return;
1569 }
1570
1571 // Right operand is in register.
1572 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/true, /*has_sign=*/true);
1573 }
1574
1575 void MacroAssembler::compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1576 // Right operand is constant.
1577 if (x2.is_constant()) {
1578 jlong value = x2.as_constant();
1579 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/true, /*has_sign=*/false);
1580 return;
1581 }
1582
1583 // Right operand is in register.
1584 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/true, /*has_sign=*/false);
1585 }
1586
1587 // Generate an optimal branch to the branch target.
1588 // Optimal means that a relative branch (brc or brcl) is used if the
1589 // branch distance is short enough. Loading the target address into a
1590 // register and branching via reg is used as fallback only.
1591 //
1592 // Used registers:
1593 // Z_R1 - work reg. Holds branch target address.
1594 // Used in fallback case only.
1595 //
1596 // This version of branch_optimized is good for cases where the target address is known
1597 // and constant, i.e. is never changed (no relocation, no patching).
1598 void MacroAssembler::branch_optimized(Assembler::branch_condition cond, address branch_addr) {
1599 address branch_origin = pc();
1600
1601 if (RelAddr::is_in_range_of_RelAddr16(branch_addr, branch_origin)) {
1602 z_brc(cond, branch_addr);
1603 } else if (RelAddr::is_in_range_of_RelAddr32(branch_addr, branch_origin)) {
1604 z_brcl(cond, branch_addr);
1605 } else {
1606 load_const_optimized(Z_R1, branch_addr); // CC must not get killed by load_const_optimized.
1607 z_bcr(cond, Z_R1);
1608 }
1609 }
1610
1611 // This version of branch_optimized is good for cases where the target address
1612 // is potentially not yet known at the time the code is emitted.
1613 //
1614 // One very common case is a branch to an unbound label which is handled here.
1615 // The caller might know (or hope) that the branch distance is short enough
1616 // to be encoded in a 16bit relative address. In this case he will pass a
1617 // NearLabel branch_target.
1618 // Care must be taken with unbound labels. Each call to target(label) creates
1619 // an entry in the patch queue for that label to patch all references of the label
1620 // once it gets bound. Those recorded patch locations must be patchable. Otherwise,
1621 // an assertion fires at patch time.
1622 void MacroAssembler::branch_optimized(Assembler::branch_condition cond, Label& branch_target) {
1623 if (branch_target.is_bound()) {
1624 address branch_addr = target(branch_target);
1625 branch_optimized(cond, branch_addr);
1626 } else if (branch_target.is_near()) {
1627 z_brc(cond, branch_target); // Caller assures that the target will be in range for z_brc.
1628 } else {
1629 z_brcl(cond, branch_target); // Let's hope target is in range. Otherwise, we will abort at patch time.
1630 }
1631 }
1632
1633 // Generate an optimal compare and branch to the branch target.
1634 // Optimal means that a relative branch (clgrj, brc or brcl) is used if the
1635 // branch distance is short enough. Loading the target address into a
1636 // register and branching via reg is used as fallback only.
1637 //
1638 // Input:
1639 // r1 - left compare operand
1640 // r2 - right compare operand
1641 void MacroAssembler::compare_and_branch_optimized(Register r1,
1642 Register r2,
1643 Assembler::branch_condition cond,
1644 address branch_addr,
1645 bool len64,
1646 bool has_sign) {
1647 unsigned int casenum = (len64?2:0)+(has_sign?0:1);
1648
1649 address branch_origin = pc();
1650 if (VM_Version::has_CompareBranch() && RelAddr::is_in_range_of_RelAddr16(branch_addr, branch_origin)) {
1651 switch (casenum) {
1652 case 0: z_crj( r1, r2, cond, branch_addr); break;
1653 case 1: z_clrj (r1, r2, cond, branch_addr); break;
1654 case 2: z_cgrj(r1, r2, cond, branch_addr); break;
1655 case 3: z_clgrj(r1, r2, cond, branch_addr); break;
1656 default: ShouldNotReachHere(); break;
1657 }
1658 } else {
1659 switch (casenum) {
1660 case 0: z_cr( r1, r2); break;
1661 case 1: z_clr(r1, r2); break;
1662 case 2: z_cgr(r1, r2); break;
1663 case 3: z_clgr(r1, r2); break;
1664 default: ShouldNotReachHere(); break;
1665 }
1666 branch_optimized(cond, branch_addr);
1667 }
1668 }
1669
1670 // Generate an optimal compare and branch to the branch target.
1671 // Optimal means that a relative branch (clgij, brc or brcl) is used if the
1672 // branch distance is short enough. Loading the target address into a
1673 // register and branching via reg is used as fallback only.
1674 //
1675 // Input:
1676 // r1 - left compare operand (in register)
1677 // x2 - right compare operand (immediate)
1678 void MacroAssembler::compare_and_branch_optimized(Register r1,
1679 jlong x2,
1680 Assembler::branch_condition cond,
1681 Label& branch_target,
1682 bool len64,
1683 bool has_sign) {
1684 address branch_origin = pc();
1685 bool x2_imm8 = (has_sign && Immediate::is_simm8(x2)) || (!has_sign && Immediate::is_uimm8(x2));
1686 bool is_RelAddr16 = branch_target.is_near() ||
1687 (branch_target.is_bound() &&
1688 RelAddr::is_in_range_of_RelAddr16(target(branch_target), branch_origin));
1689 unsigned int casenum = (len64?2:0)+(has_sign?0:1);
1690
1691 if (VM_Version::has_CompareBranch() && is_RelAddr16 && x2_imm8) {
1692 switch (casenum) {
1693 case 0: z_cij( r1, x2, cond, branch_target); break;
1694 case 1: z_clij(r1, x2, cond, branch_target); break;
1695 case 2: z_cgij(r1, x2, cond, branch_target); break;
1696 case 3: z_clgij(r1, x2, cond, branch_target); break;
1697 default: ShouldNotReachHere(); break;
1698 }
1699 return;
1700 }
1701
1702 if (x2 == 0) {
1703 switch (casenum) {
1704 case 0: z_ltr(r1, r1); break;
1705 case 1: z_ltr(r1, r1); break; // Caution: unsigned test only provides zero/notZero indication!
1706 case 2: z_ltgr(r1, r1); break;
1707 case 3: z_ltgr(r1, r1); break; // Caution: unsigned test only provides zero/notZero indication!
1708 default: ShouldNotReachHere(); break;
1709 }
1710 } else {
1711 if ((has_sign && Immediate::is_simm16(x2)) || (!has_sign && Immediate::is_uimm(x2, 15))) {
1712 switch (casenum) {
1713 case 0: z_chi(r1, x2); break;
1714 case 1: z_chi(r1, x2); break; // positive immediate < 2**15
1715 case 2: z_cghi(r1, x2); break;
1716 case 3: z_cghi(r1, x2); break; // positive immediate < 2**15
1717 default: break;
1718 }
1719 } else if ( (has_sign && Immediate::is_simm32(x2)) || (!has_sign && Immediate::is_uimm32(x2)) ) {
1720 switch (casenum) {
1721 case 0: z_cfi( r1, x2); break;
1722 case 1: z_clfi(r1, x2); break;
1723 case 2: z_cgfi(r1, x2); break;
1724 case 3: z_clgfi(r1, x2); break;
1725 default: ShouldNotReachHere(); break;
1726 }
1727 } else {
1728 // No instruction with immediate operand possible, so load into register.
1729 Register scratch = (r1 != Z_R0) ? Z_R0 : Z_R1;
1730 load_const_optimized(scratch, x2);
1731 switch (casenum) {
1732 case 0: z_cr( r1, scratch); break;
1733 case 1: z_clr(r1, scratch); break;
1734 case 2: z_cgr(r1, scratch); break;
1735 case 3: z_clgr(r1, scratch); break;
1736 default: ShouldNotReachHere(); break;
1737 }
1738 }
1739 }
1740 branch_optimized(cond, branch_target);
1741 }
1742
1743 // Generate an optimal compare and branch to the branch target.
1744 // Optimal means that a relative branch (clgrj, brc or brcl) is used if the
1745 // branch distance is short enough. Loading the target address into a
1746 // register and branching via reg is used as fallback only.
1747 //
1748 // Input:
1749 // r1 - left compare operand
1750 // r2 - right compare operand
1751 void MacroAssembler::compare_and_branch_optimized(Register r1,
1752 Register r2,
1753 Assembler::branch_condition cond,
1754 Label& branch_target,
1755 bool len64,
1756 bool has_sign) {
1757 unsigned int casenum = (len64 ? 2 : 0) + (has_sign ? 0 : 1);
1758
1759 if (branch_target.is_bound()) {
1760 address branch_addr = target(branch_target);
1761 compare_and_branch_optimized(r1, r2, cond, branch_addr, len64, has_sign);
1762 } else {
1763 if (VM_Version::has_CompareBranch() && branch_target.is_near()) {
1764 switch (casenum) {
1765 case 0: z_crj( r1, r2, cond, branch_target); break;
1766 case 1: z_clrj( r1, r2, cond, branch_target); break;
1767 case 2: z_cgrj( r1, r2, cond, branch_target); break;
1768 case 3: z_clgrj(r1, r2, cond, branch_target); break;
1769 default: ShouldNotReachHere(); break;
1770 }
1771 } else {
1772 switch (casenum) {
1773 case 0: z_cr( r1, r2); break;
1774 case 1: z_clr(r1, r2); break;
1775 case 2: z_cgr(r1, r2); break;
1776 case 3: z_clgr(r1, r2); break;
1777 default: ShouldNotReachHere(); break;
1778 }
1779 branch_optimized(cond, branch_target);
1780 }
1781 }
1782 }
1783
1784 //===========================================================================
1785 //=== END H I G H E R L E V E L B R A N C H E M I T T E R S ===
1786 //===========================================================================
1787
1788 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
1789 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1790 int index = oop_recorder()->allocate_metadata_index(obj);
1791 RelocationHolder rspec = metadata_Relocation::spec(index);
1792 return AddressLiteral((address)obj, rspec);
1793 }
1794
1795 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
1796 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1797 int index = oop_recorder()->find_index(obj);
1798 RelocationHolder rspec = metadata_Relocation::spec(index);
1799 return AddressLiteral((address)obj, rspec);
1800 }
1801
1802 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
1803 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1804 int oop_index = oop_recorder()->allocate_oop_index(obj);
1805 return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
1806 }
1807
1808 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1809 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1810 int oop_index = oop_recorder()->find_index(obj);
1811 return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
1812 }
1813
1814 // NOTE: destroys r
1815 void MacroAssembler::c2bool(Register r, Register t) {
1816 z_lcr(t, r); // t = -r
1817 z_or(r, t); // r = -r OR r
1818 z_srl(r, 31); // Yields 0 if r was 0, 1 otherwise.
1819 }
1820
1821 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
1822 Register tmp,
1823 int offset) {
1824 intptr_t value = *delayed_value_addr;
1825 if (value != 0) {
1826 return RegisterOrConstant(value + offset);
1827 }
1828
1829 BLOCK_COMMENT("delayed_value {");
1830 // Load indirectly to solve generation ordering problem.
1831 load_absolute_address(tmp, (address) delayed_value_addr); // tmp = a;
1832 z_lg(tmp, 0, tmp); // tmp = *tmp;
1833
1834 #ifdef ASSERT
1835 NearLabel L;
1836 compare64_and_branch(tmp, (intptr_t)0L, Assembler::bcondNotEqual, L);
1837 z_illtrap();
1838 bind(L);
1839 #endif
1840
1841 if (offset != 0) {
1842 z_agfi(tmp, offset); // tmp = tmp + offset;
1843 }
1844
1845 BLOCK_COMMENT("} delayed_value");
1846 return RegisterOrConstant(tmp);
1847 }
1848
1849 // Patch instruction `inst' at offset `inst_pos' to refer to `dest_pos'
1850 // and return the resulting instruction.
1851 // Dest_pos and inst_pos are 32 bit only. These parms can only designate
1852 // relative positions.
1853 // Use correct argument types. Do not pre-calculate distance.
1854 unsigned long MacroAssembler::patched_branch(address dest_pos, unsigned long inst, address inst_pos) {
1855 int c = 0;
1856 unsigned long patched_inst = 0;
1857 if (is_call_pcrelative_short(inst) ||
1858 is_branch_pcrelative_short(inst) ||
1859 is_branchoncount_pcrelative_short(inst) ||
1860 is_branchonindex32_pcrelative_short(inst)) {
1861 c = 1;
1862 int m = fmask(15, 0); // simm16(-1, 16, 32);
1863 int v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 32);
1864 patched_inst = (inst & ~m) | v;
1865 } else if (is_compareandbranch_pcrelative_short(inst)) {
1866 c = 2;
1867 long m = fmask(31, 16); // simm16(-1, 16, 48);
1868 long v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 48);
1869 patched_inst = (inst & ~m) | v;
1870 } else if (is_branchonindex64_pcrelative_short(inst)) {
1871 c = 3;
1872 long m = fmask(31, 16); // simm16(-1, 16, 48);
1873 long v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 48);
1874 patched_inst = (inst & ~m) | v;
1875 } else if (is_call_pcrelative_long(inst) || is_branch_pcrelative_long(inst)) {
1876 c = 4;
1877 long m = fmask(31, 0); // simm32(-1, 16, 48);
1878 long v = simm32(RelAddr::pcrel_off32(dest_pos, inst_pos), 16, 48);
1879 patched_inst = (inst & ~m) | v;
1880 } else if (is_pcrelative_long(inst)) { // These are the non-branch pc-relative instructions.
1881 c = 5;
1882 long m = fmask(31, 0); // simm32(-1, 16, 48);
1883 long v = simm32(RelAddr::pcrel_off32(dest_pos, inst_pos), 16, 48);
1884 patched_inst = (inst & ~m) | v;
1885 } else {
1886 print_dbg_msg(tty, inst, "not a relative branch", 0);
1887 dump_code_range(tty, inst_pos, 32, "not a pcrelative branch");
1888 ShouldNotReachHere();
1889 }
1890
1891 long new_off = get_pcrel_offset(patched_inst);
1892 if (new_off != (dest_pos-inst_pos)) {
1893 tty->print_cr("case %d: dest_pos = %p, inst_pos = %p, disp = %ld(%12.12lx)", c, dest_pos, inst_pos, new_off, new_off);
1894 print_dbg_msg(tty, inst, "<- original instruction: branch patching error", 0);
1895 print_dbg_msg(tty, patched_inst, "<- patched instruction: branch patching error", 0);
1896 #ifdef LUCY_DBG
1897 VM_Version::z_SIGSEGV();
1898 #endif
1899 ShouldNotReachHere();
1900 }
1901 return patched_inst;
1902 }
1903
1904 // Only called when binding labels (share/vm/asm/assembler.cpp)
1905 // Pass arguments as intended. Do not pre-calculate distance.
1906 void MacroAssembler::pd_patch_instruction(address branch, address target) {
1907 unsigned long stub_inst;
1908 int inst_len = get_instruction(branch, &stub_inst);
1909
1910 set_instruction(branch, patched_branch(target, stub_inst, branch), inst_len);
1911 }
1912
1913
1914 // Extract relative address (aka offset).
1915 // inv_simm16 works for 4-byte instructions only.
1916 // compare and branch instructions are 6-byte and have a 16bit offset "in the middle".
1917 long MacroAssembler::get_pcrel_offset(unsigned long inst) {
1918
1919 if (MacroAssembler::is_pcrelative_short(inst)) {
1920 if (((inst&0xFFFFffff00000000UL) == 0) && ((inst&0x00000000FFFF0000UL) != 0)) {
1921 return RelAddr::inv_pcrel_off16(inv_simm16(inst));
1922 } else {
1923 return RelAddr::inv_pcrel_off16(inv_simm16_48(inst));
1924 }
1925 }
1926
1927 if (MacroAssembler::is_pcrelative_long(inst)) {
1928 return RelAddr::inv_pcrel_off32(inv_simm32(inst));
1929 }
1930
1931 print_dbg_msg(tty, inst, "not a pcrelative instruction", 6);
1932 #ifdef LUCY_DBG
1933 VM_Version::z_SIGSEGV();
1934 #else
1935 ShouldNotReachHere();
1936 #endif
1937 return -1;
1938 }
1939
1940 long MacroAssembler::get_pcrel_offset(address pc) {
1941 unsigned long inst;
1942 unsigned int len = get_instruction(pc, &inst);
1943
1944 #ifdef ASSERT
1945 long offset;
1946 if (MacroAssembler::is_pcrelative_short(inst) || MacroAssembler::is_pcrelative_long(inst)) {
1947 offset = get_pcrel_offset(inst);
1948 } else {
1949 offset = -1;
1950 }
1951
1952 if (offset == -1) {
1953 dump_code_range(tty, pc, 32, "not a pcrelative instruction");
1954 #ifdef LUCY_DBG
1955 VM_Version::z_SIGSEGV();
1956 #else
1957 ShouldNotReachHere();
1958 #endif
1959 }
1960 return offset;
1961 #else
1962 return get_pcrel_offset(inst);
1963 #endif // ASSERT
1964 }
1965
1966 // Get target address from pc-relative instructions.
1967 address MacroAssembler::get_target_addr_pcrel(address pc) {
1968 assert(is_pcrelative_long(pc), "not a pcrelative instruction");
1969 return pc + get_pcrel_offset(pc);
1970 }
1971
1972 // Patch pc relative load address.
1973 void MacroAssembler::patch_target_addr_pcrel(address pc, address con) {
1974 unsigned long inst;
1975 // Offset is +/- 2**32 -> use long.
1976 ptrdiff_t distance = con - pc;
1977
1978 get_instruction(pc, &inst);
1979
1980 if (is_pcrelative_short(inst)) {
1981 *(short *)(pc+2) = RelAddr::pcrel_off16(con, pc); // Instructions are at least 2-byte aligned, no test required.
1982
1983 // Some extra safety net.
1984 if (!RelAddr::is_in_range_of_RelAddr16(distance)) {
1985 print_dbg_msg(tty, inst, "distance out of range (16bit)", 4);
1986 dump_code_range(tty, pc, 32, "distance out of range (16bit)");
1987 guarantee(RelAddr::is_in_range_of_RelAddr16(distance), "too far away (more than +/- 2**16");
1988 }
1989 return;
1990 }
1991
1992 if (is_pcrelative_long(inst)) {
1993 *(int *)(pc+2) = RelAddr::pcrel_off32(con, pc);
1994
1995 // Some Extra safety net.
1996 if (!RelAddr::is_in_range_of_RelAddr32(distance)) {
1997 print_dbg_msg(tty, inst, "distance out of range (32bit)", 6);
1998 dump_code_range(tty, pc, 32, "distance out of range (32bit)");
1999 guarantee(RelAddr::is_in_range_of_RelAddr32(distance), "too far away (more than +/- 2**32");
2000 }
2001 return;
2002 }
2003
2004 guarantee(false, "not a pcrelative instruction to patch!");
2005 }
2006
2007 // "Current PC" here means the address just behind the basr instruction.
2008 address MacroAssembler::get_PC(Register result) {
2009 z_basr(result, Z_R0); // Don't branch, just save next instruction address in result.
2010 return pc();
2011 }
2012
2013 // Get current PC + offset.
2014 // Offset given in bytes, must be even!
2015 // "Current PC" here means the address of the larl instruction plus the given offset.
2016 address MacroAssembler::get_PC(Register result, int64_t offset) {
2017 address here = pc();
2018 z_larl(result, offset/2); // Save target instruction address in result.
2019 return here + offset;
2020 }
2021
2022 void MacroAssembler::instr_size(Register size, Register pc) {
2023 // Extract 2 most significant bits of current instruction.
2024 z_llgc(size, Address(pc));
2025 z_srl(size, 6);
2026 // Compute (x+3)&6 which translates 0->2, 1->4, 2->4, 3->6.
2027 z_ahi(size, 3);
2028 z_nill(size, 6);
2029 }
2030
2031 // Resize_frame with SP(new) = SP(old) - [offset].
2032 void MacroAssembler::resize_frame_sub(Register offset, Register fp, bool load_fp)
2033 {
2034 assert_different_registers(offset, fp, Z_SP);
2035 if (load_fp) { z_lg(fp, _z_abi(callers_sp), Z_SP); }
2036
2037 z_sgr(Z_SP, offset);
2038 z_stg(fp, _z_abi(callers_sp), Z_SP);
2039 }
2040
2041 // Resize_frame with SP(new) = [newSP] + offset.
2042 // This emitter is useful if we already have calculated a pointer
2043 // into the to-be-allocated stack space, e.g. with special alignment properties,
2044 // but need some additional space, e.g. for spilling.
2045 // newSP is the pre-calculated pointer. It must not be modified.
2046 // fp holds, or is filled with, the frame pointer.
2047 // offset is the additional increment which is added to addr to form the new SP.
2048 // Note: specify a negative value to reserve more space!
2049 // load_fp == true only indicates that fp is not pre-filled with the frame pointer.
2050 // It does not guarantee that fp contains the frame pointer at the end.
2051 void MacroAssembler::resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp) {
2052 assert_different_registers(newSP, fp, Z_SP);
2053
2054 if (load_fp) {
2055 z_lg(fp, _z_abi(callers_sp), Z_SP);
2056 }
2057
2058 add2reg(Z_SP, offset, newSP);
2059 z_stg(fp, _z_abi(callers_sp), Z_SP);
2060 }
2061
2062 // Resize_frame with SP(new) = [newSP].
2063 // load_fp == true only indicates that fp is not pre-filled with the frame pointer.
2064 // It does not guarantee that fp contains the frame pointer at the end.
2065 void MacroAssembler::resize_frame_absolute(Register newSP, Register fp, bool load_fp) {
2066 assert_different_registers(newSP, fp, Z_SP);
2067
2068 if (load_fp) {
2069 z_lg(fp, _z_abi(callers_sp), Z_SP); // need to use load/store.
2070 }
2071
2072 z_lgr(Z_SP, newSP);
2073 if (newSP != Z_R0) { // make sure we generate correct code, no matter what register newSP uses.
2074 z_stg(fp, _z_abi(callers_sp), newSP);
2075 } else {
2076 z_stg(fp, _z_abi(callers_sp), Z_SP);
2077 }
2078 }
2079
2080 // Resize_frame with SP(new) = SP(old) + offset.
2081 void MacroAssembler::resize_frame(RegisterOrConstant offset, Register fp, bool load_fp) {
2082 assert_different_registers(fp, Z_SP);
2083
2084 if (load_fp) {
2085 z_lg(fp, _z_abi(callers_sp), Z_SP);
2086 }
2087 add64(Z_SP, offset);
2088 z_stg(fp, _z_abi(callers_sp), Z_SP);
2089 }
2090
2091 void MacroAssembler::push_frame(Register bytes, Register old_sp, bool copy_sp, bool bytes_with_inverted_sign) {
2092 #ifdef ASSERT
2093 assert_different_registers(bytes, old_sp, Z_SP);
2094 if (!copy_sp) {
2095 z_cgr(old_sp, Z_SP);
2096 asm_assert_eq("[old_sp]!=[Z_SP]", 0x211);
2097 }
2098 #endif
2099 if (copy_sp) { z_lgr(old_sp, Z_SP); }
2100 if (bytes_with_inverted_sign) {
2101 z_agr(Z_SP, bytes);
2102 } else {
2103 z_sgr(Z_SP, bytes); // Z_sgfr sufficient, but probably not faster.
2104 }
2105 z_stg(old_sp, _z_abi(callers_sp), Z_SP);
2106 }
2107
2108 unsigned int MacroAssembler::push_frame(unsigned int bytes, Register scratch) {
2109 long offset = Assembler::align(bytes, frame::alignment_in_bytes);
2110 assert(offset > 0, "should push a frame with positive size, size = %ld.", offset);
2111 assert(Displacement::is_validDisp(-offset), "frame size out of range, size = %ld", offset);
2112
2113 // We must not write outside the current stack bounds (given by Z_SP).
2114 // Thus, we have to first update Z_SP and then store the previous SP as stack linkage.
2115 // We rely on Z_R0 by default to be available as scratch.
2116 z_lgr(scratch, Z_SP);
2117 add2reg(Z_SP, -offset);
2118 z_stg(scratch, _z_abi(callers_sp), Z_SP);
2119 #ifdef ASSERT
2120 // Just make sure nobody uses the value in the default scratch register.
2121 // When another register is used, the caller might rely on it containing the frame pointer.
2122 if (scratch == Z_R0) {
2123 z_iihf(scratch, 0xbaadbabe);
2124 z_iilf(scratch, 0xdeadbeef);
2125 }
2126 #endif
2127 return offset;
2128 }
2129
2130 // Push a frame of size `bytes' plus abi160 on top.
2131 unsigned int MacroAssembler::push_frame_abi160(unsigned int bytes) {
2132 BLOCK_COMMENT("push_frame_abi160 {");
2133 unsigned int res = push_frame(bytes + frame::z_abi_160_size);
2134 BLOCK_COMMENT("} push_frame_abi160");
2135 return res;
2136 }
2137
2138 // Pop current C frame.
2139 void MacroAssembler::pop_frame() {
2140 BLOCK_COMMENT("pop_frame:");
2141 Assembler::z_lg(Z_SP, _z_abi(callers_sp), Z_SP);
2142 }
2143
2144 // Pop current C frame and restore return PC register (Z_R14).
2145 void MacroAssembler::pop_frame_restore_retPC(int frame_size_in_bytes) {
2146 BLOCK_COMMENT("pop_frame_restore_retPC:");
2147 int retPC_offset = _z_abi16(return_pc) + frame_size_in_bytes;
2148 // If possible, pop frame by add instead of load (a penny saved is a penny got :-).
2149 if (Displacement::is_validDisp(retPC_offset)) {
2150 z_lg(Z_R14, retPC_offset, Z_SP);
2151 add2reg(Z_SP, frame_size_in_bytes);
2152 } else {
2153 add2reg(Z_SP, frame_size_in_bytes);
2154 restore_return_pc();
2155 }
2156 }
2157
2158 void MacroAssembler::call_VM_leaf_base(address entry_point, bool allow_relocation) {
2159 if (allow_relocation) {
2160 call_c(entry_point);
2161 } else {
2162 call_c_static(entry_point);
2163 }
2164 }
2165
2166 void MacroAssembler::call_VM_leaf_base(address entry_point) {
2167 bool allow_relocation = true;
2168 call_VM_leaf_base(entry_point, allow_relocation);
2169 }
2170
2171 void MacroAssembler::call_VM_base(Register oop_result,
2172 Register last_java_sp,
2173 address entry_point,
2174 bool allow_relocation,
2175 bool check_exceptions) { // Defaults to true.
2176 // Allow_relocation indicates, if true, that the generated code shall
2177 // be fit for code relocation or referenced data relocation. In other
2178 // words: all addresses must be considered variable. PC-relative addressing
2179 // is not possible then.
2180 // On the other hand, if (allow_relocation == false), addresses and offsets
2181 // may be considered stable, enabling us to take advantage of some PC-relative
2182 // addressing tweaks. These might improve performance and reduce code size.
2183
2184 // Determine last_java_sp register.
2185 if (!last_java_sp->is_valid()) {
2186 last_java_sp = Z_SP; // Load Z_SP as SP.
2187 }
2188
2189 set_top_ijava_frame_at_SP_as_last_Java_frame(last_java_sp, Z_R1, allow_relocation);
2190
2191 // ARG1 must hold thread address.
2192 z_lgr(Z_ARG1, Z_thread);
2193
2194 address return_pc = NULL;
2195 if (allow_relocation) {
2196 return_pc = call_c(entry_point);
2197 } else {
2198 return_pc = call_c_static(entry_point);
2199 }
2200
2201 reset_last_Java_frame(allow_relocation);
2202
2203 // C++ interp handles this in the interpreter.
2204 check_and_handle_popframe(Z_thread);
2205 check_and_handle_earlyret(Z_thread);
2206
2207 // Check for pending exceptions.
2208 if (check_exceptions) {
2209 // Check for pending exceptions (java_thread is set upon return).
2210 load_and_test_long(Z_R0_scratch, Address(Z_thread, Thread::pending_exception_offset()));
2211
2212 // This used to conditionally jump to forward_exception however it is
2213 // possible if we relocate that the branch will not reach. So we must jump
2214 // around so we can always reach.
2215
2216 Label ok;
2217 z_bre(ok); // Bcondequal is the same as bcondZero.
2218 call_stub(StubRoutines::forward_exception_entry());
2219 bind(ok);
2220 }
2221
2222 // Get oop result if there is one and reset the value in the thread.
2223 if (oop_result->is_valid()) {
2224 get_vm_result(oop_result);
2225 }
2226
2227 _last_calls_return_pc = return_pc; // Wipe out other (error handling) calls.
2228 }
2229
2230 void MacroAssembler::call_VM_base(Register oop_result,
2231 Register last_java_sp,
2232 address entry_point,
2233 bool check_exceptions) { // Defaults to true.
2234 bool allow_relocation = true;
2235 call_VM_base(oop_result, last_java_sp, entry_point, allow_relocation, check_exceptions);
2236 }
2237
2238 // VM calls without explicit last_java_sp.
2239
2240 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
2241 // Call takes possible detour via InterpreterMacroAssembler.
2242 call_VM_base(oop_result, noreg, entry_point, true, check_exceptions);
2243 }
2244
2245 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
2246 // Z_ARG1 is reserved for the thread.
2247 lgr_if_needed(Z_ARG2, arg_1);
2248 call_VM(oop_result, entry_point, check_exceptions);
2249 }
2250
2251 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
2252 // Z_ARG1 is reserved for the thread.
2253 lgr_if_needed(Z_ARG2, arg_1);
2254 assert(arg_2 != Z_ARG2, "smashed argument");
2255 lgr_if_needed(Z_ARG3, arg_2);
2256 call_VM(oop_result, entry_point, check_exceptions);
2257 }
2258
2259 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
2260 Register arg_3, bool check_exceptions) {
2261 // Z_ARG1 is reserved for the thread.
2262 lgr_if_needed(Z_ARG2, arg_1);
2263 assert(arg_2 != Z_ARG2, "smashed argument");
2264 lgr_if_needed(Z_ARG3, arg_2);
2265 assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2266 lgr_if_needed(Z_ARG4, arg_3);
2267 call_VM(oop_result, entry_point, check_exceptions);
2268 }
2269
2270 // VM static calls without explicit last_java_sp.
2271
2272 void MacroAssembler::call_VM_static(Register oop_result, address entry_point, bool check_exceptions) {
2273 // Call takes possible detour via InterpreterMacroAssembler.
2274 call_VM_base(oop_result, noreg, entry_point, false, check_exceptions);
2275 }
2276
2277 void MacroAssembler::call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2,
2278 Register arg_3, bool check_exceptions) {
2279 // Z_ARG1 is reserved for the thread.
2280 lgr_if_needed(Z_ARG2, arg_1);
2281 assert(arg_2 != Z_ARG2, "smashed argument");
2282 lgr_if_needed(Z_ARG3, arg_2);
2283 assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2284 lgr_if_needed(Z_ARG4, arg_3);
2285 call_VM_static(oop_result, entry_point, check_exceptions);
2286 }
2287
2288 // VM calls with explicit last_java_sp.
2289
2290 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions) {
2291 // Call takes possible detour via InterpreterMacroAssembler.
2292 call_VM_base(oop_result, last_java_sp, entry_point, true, check_exceptions);
2293 }
2294
2295 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
2296 // Z_ARG1 is reserved for the thread.
2297 lgr_if_needed(Z_ARG2, arg_1);
2298 call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2299 }
2300
2301 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1,
2302 Register arg_2, bool check_exceptions) {
2303 // Z_ARG1 is reserved for the thread.
2304 lgr_if_needed(Z_ARG2, arg_1);
2305 assert(arg_2 != Z_ARG2, "smashed argument");
2306 lgr_if_needed(Z_ARG3, arg_2);
2307 call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2308 }
2309
2310 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1,
2311 Register arg_2, Register arg_3, bool check_exceptions) {
2312 // Z_ARG1 is reserved for the thread.
2313 lgr_if_needed(Z_ARG2, arg_1);
2314 assert(arg_2 != Z_ARG2, "smashed argument");
2315 lgr_if_needed(Z_ARG3, arg_2);
2316 assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2317 lgr_if_needed(Z_ARG4, arg_3);
2318 call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2319 }
2320
2321 // VM leaf calls.
2322
2323 void MacroAssembler::call_VM_leaf(address entry_point) {
2324 // Call takes possible detour via InterpreterMacroAssembler.
2325 call_VM_leaf_base(entry_point, true);
2326 }
2327
2328 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
2329 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2330 call_VM_leaf(entry_point);
2331 }
2332
2333 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
2334 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2335 assert(arg_2 != Z_ARG1, "smashed argument");
2336 if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2337 call_VM_leaf(entry_point);
2338 }
2339
2340 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
2341 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2342 assert(arg_2 != Z_ARG1, "smashed argument");
2343 if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2344 assert(arg_3 != Z_ARG1 && arg_3 != Z_ARG2, "smashed argument");
2345 if (arg_3 != noreg) lgr_if_needed(Z_ARG3, arg_3);
2346 call_VM_leaf(entry_point);
2347 }
2348
2349 // Static VM leaf calls.
2350 // Really static VM leaf calls are never patched.
2351
2352 void MacroAssembler::call_VM_leaf_static(address entry_point) {
2353 // Call takes possible detour via InterpreterMacroAssembler.
2354 call_VM_leaf_base(entry_point, false);
2355 }
2356
2357 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1) {
2358 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2359 call_VM_leaf_static(entry_point);
2360 }
2361
2362 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2) {
2363 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2364 assert(arg_2 != Z_ARG1, "smashed argument");
2365 if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2366 call_VM_leaf_static(entry_point);
2367 }
2368
2369 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
2370 if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2371 assert(arg_2 != Z_ARG1, "smashed argument");
2372 if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2373 assert(arg_3 != Z_ARG1 && arg_3 != Z_ARG2, "smashed argument");
2374 if (arg_3 != noreg) lgr_if_needed(Z_ARG3, arg_3);
2375 call_VM_leaf_static(entry_point);
2376 }
2377
2378 // Don't use detour via call_c(reg).
2379 address MacroAssembler::call_c(address function_entry) {
2380 load_const(Z_R1, function_entry);
2381 return call(Z_R1);
2382 }
2383
2384 // Variant for really static (non-relocatable) calls which are never patched.
2385 address MacroAssembler::call_c_static(address function_entry) {
2386 load_absolute_address(Z_R1, function_entry);
2387 #if 0 // def ASSERT
2388 // Verify that call site did not move.
2389 load_const_optimized(Z_R0, function_entry);
2390 z_cgr(Z_R1, Z_R0);
2391 z_brc(bcondEqual, 3);
2392 z_illtrap(0xba);
2393 #endif
2394 return call(Z_R1);
2395 }
2396
2397 address MacroAssembler::call_c_opt(address function_entry) {
2398 bool success = call_far_patchable(function_entry, -2 /* emit relocation + constant */);
2399 _last_calls_return_pc = success ? pc() : NULL;
2400 return _last_calls_return_pc;
2401 }
2402
2403 // Identify a call_far_patchable instruction: LARL + LG + BASR
2404 //
2405 // nop ; optionally, if required for alignment
2406 // lgrl rx,A(TOC entry) ; PC-relative access into constant pool
2407 // basr Z_R14,rx ; end of this instruction must be aligned to a word boundary
2408 //
2409 // Code pattern will eventually get patched into variant2 (see below for detection code).
2410 //
2411 bool MacroAssembler::is_call_far_patchable_variant0_at(address instruction_addr) {
2412 address iaddr = instruction_addr;
2413
2414 // Check for the actual load instruction.
2415 if (!is_load_const_from_toc(iaddr)) { return false; }
2416 iaddr += load_const_from_toc_size();
2417
2418 // Check for the call (BASR) instruction, finally.
2419 assert(iaddr-instruction_addr+call_byregister_size() == call_far_patchable_size(), "size mismatch");
2420 return is_call_byregister(iaddr);
2421 }
2422
2423 // Identify a call_far_patchable instruction: BRASL
2424 //
2425 // Code pattern to suits atomic patching:
2426 // nop ; Optionally, if required for alignment.
2427 // nop ... ; Multiple filler nops to compensate for size difference (variant0 is longer).
2428 // nop ; For code pattern detection: Prepend each BRASL with a nop.
2429 // brasl Z_R14,<reladdr> ; End of code must be 4-byte aligned !
2430 bool MacroAssembler::is_call_far_patchable_variant2_at(address instruction_addr) {
2431 const address call_addr = (address)((intptr_t)instruction_addr + call_far_patchable_size() - call_far_pcrelative_size());
2432
2433 // Check for correct number of leading nops.
2434 address iaddr;
2435 for (iaddr = instruction_addr; iaddr < call_addr; iaddr += nop_size()) {
2436 if (!is_z_nop(iaddr)) { return false; }
2437 }
2438 assert(iaddr == call_addr, "sanity");
2439
2440 // --> Check for call instruction.
2441 if (is_call_far_pcrelative(call_addr)) {
2442 assert(call_addr-instruction_addr+call_far_pcrelative_size() == call_far_patchable_size(), "size mismatch");
2443 return true;
2444 }
2445
2446 return false;
2447 }
2448
2449 // Emit a NOT mt-safely patchable 64 bit absolute call.
2450 // If toc_offset == -2, then the destination of the call (= target) is emitted
2451 // to the constant pool and a runtime_call relocation is added
2452 // to the code buffer.
2453 // If toc_offset != -2, target must already be in the constant pool at
2454 // _ctableStart+toc_offset (a caller can retrieve toc_offset
2455 // from the runtime_call relocation).
2456 // Special handling of emitting to scratch buffer when there is no constant pool.
2457 // Slightly changed code pattern. We emit an additional nop if we would
2458 // not end emitting at a word aligned address. This is to ensure
2459 // an atomically patchable displacement in brasl instructions.
2460 //
2461 // A call_far_patchable comes in different flavors:
2462 // - LARL(CP) / LG(CP) / BR (address in constant pool, access via CP register)
2463 // - LGRL(CP) / BR (address in constant pool, pc-relative accesss)
2464 // - BRASL (relative address of call target coded in instruction)
2465 // All flavors occupy the same amount of space. Length differences are compensated
2466 // by leading nops, such that the instruction sequence always ends at the same
2467 // byte offset. This is required to keep the return offset constant.
2468 // Furthermore, the return address (the end of the instruction sequence) is forced
2469 // to be on a 4-byte boundary. This is required for atomic patching, should we ever
2470 // need to patch the call target of the BRASL flavor.
2471 // RETURN value: false, if no constant pool entry could be allocated, true otherwise.
2472 bool MacroAssembler::call_far_patchable(address target, int64_t tocOffset) {
2473 // Get current pc and ensure word alignment for end of instr sequence.
2474 const address start_pc = pc();
2475 const intptr_t start_off = offset();
2476 assert(!call_far_patchable_requires_alignment_nop(start_pc), "call_far_patchable requires aligned address");
2477 const ptrdiff_t dist = (ptrdiff_t)(target - (start_pc + 2)); // Prepend each BRASL with a nop.
2478 const bool emit_target_to_pool = (tocOffset == -2) && !code_section()->scratch_emit();
2479 const bool emit_relative_call = !emit_target_to_pool &&
2480 RelAddr::is_in_range_of_RelAddr32(dist) &&
2481 ReoptimizeCallSequences &&
2482 !code_section()->scratch_emit();
2483
2484 if (emit_relative_call) {
2485 // Add padding to get the same size as below.
2486 const unsigned int padding = call_far_patchable_size() - call_far_pcrelative_size();
2487 unsigned int current_padding;
2488 for (current_padding = 0; current_padding < padding; current_padding += nop_size()) { z_nop(); }
2489 assert(current_padding == padding, "sanity");
2490
2491 // relative call: len = 2(nop) + 6 (brasl)
2492 // CodeBlob resize cannot occur in this case because
2493 // this call is emitted into pre-existing space.
2494 z_nop(); // Prepend each BRASL with a nop.
2495 z_brasl(Z_R14, target);
2496 } else {
2497 // absolute call: Get address from TOC.
2498 // len = (load TOC){6|0} + (load from TOC){6} + (basr){2} = {14|8}
2499 if (emit_target_to_pool) {
2500 // When emitting the call for the first time, we do not need to use
2501 // the pc-relative version. It will be patched anyway, when the code
2502 // buffer is copied.
2503 // Relocation is not needed when !ReoptimizeCallSequences.
2504 relocInfo::relocType rt = ReoptimizeCallSequences ? relocInfo::runtime_call_w_cp_type : relocInfo::none;
2505 AddressLiteral dest(target, rt);
2506 // Store_oop_in_toc() adds dest to the constant table. As side effect, this kills
2507 // inst_mark(). Reset if possible.
2508 bool reset_mark = (inst_mark() == pc());
2509 tocOffset = store_oop_in_toc(dest);
2510 if (reset_mark) { set_inst_mark(); }
2511 if (tocOffset == -1) {
2512 return false; // Couldn't create constant pool entry.
2513 }
2514 }
2515 assert(offset() == start_off, "emit no code before this point!");
2516
2517 address tocPos = pc() + tocOffset;
2518 if (emit_target_to_pool) {
2519 tocPos = code()->consts()->start() + tocOffset;
2520 }
2521 load_long_pcrelative(Z_R14, tocPos);
2522 z_basr(Z_R14, Z_R14);
2523 }
2524
2525 #ifdef ASSERT
2526 // Assert that we can identify the emitted call.
2527 assert(is_call_far_patchable_at(addr_at(start_off)), "can't identify emitted call");
2528 assert(offset() == start_off+call_far_patchable_size(), "wrong size");
2529
2530 if (emit_target_to_pool) {
2531 assert(get_dest_of_call_far_patchable_at(addr_at(start_off), code()->consts()->start()) == target,
2532 "wrong encoding of dest address");
2533 }
2534 #endif
2535 return true; // success
2536 }
2537
2538 // Identify a call_far_patchable instruction.
2539 // For more detailed information see header comment of call_far_patchable.
2540 bool MacroAssembler::is_call_far_patchable_at(address instruction_addr) {
2541 return is_call_far_patchable_variant2_at(instruction_addr) || // short version: BRASL
2542 is_call_far_patchable_variant0_at(instruction_addr); // long version LARL + LG + BASR
2543 }
2544
2545 // Does the call_far_patchable instruction use a pc-relative encoding
2546 // of the call destination?
2547 bool MacroAssembler::is_call_far_patchable_pcrelative_at(address instruction_addr) {
2548 // Variant 2 is pc-relative.
2549 return is_call_far_patchable_variant2_at(instruction_addr);
2550 }
2551
2552 bool MacroAssembler::is_call_far_pcrelative(address instruction_addr) {
2553 // Prepend each BRASL with a nop.
2554 return is_z_nop(instruction_addr) && is_z_brasl(instruction_addr + nop_size()); // Match at position after one nop required.
2555 }
2556
2557 // Set destination address of a call_far_patchable instruction.
2558 void MacroAssembler::set_dest_of_call_far_patchable_at(address instruction_addr, address dest, int64_t tocOffset) {
2559 ResourceMark rm;
2560
2561 // Now that CP entry is verified, patch call to a pc-relative call (if circumstances permit).
2562 int code_size = MacroAssembler::call_far_patchable_size();
2563 CodeBuffer buf(instruction_addr, code_size);
2564 MacroAssembler masm(&buf);
2565 masm.call_far_patchable(dest, tocOffset);
2566 ICache::invalidate_range(instruction_addr, code_size); // Empty on z.
2567 }
2568
2569 // Get dest address of a call_far_patchable instruction.
2570 address MacroAssembler::get_dest_of_call_far_patchable_at(address instruction_addr, address ctable) {
2571 // Dynamic TOC: absolute address in constant pool.
2572 // Check variant2 first, it is more frequent.
2573
2574 // Relative address encoded in call instruction.
2575 if (is_call_far_patchable_variant2_at(instruction_addr)) {
2576 return MacroAssembler::get_target_addr_pcrel(instruction_addr + nop_size()); // Prepend each BRASL with a nop.
2577
2578 // Absolute address in constant pool.
2579 } else if (is_call_far_patchable_variant0_at(instruction_addr)) {
2580 address iaddr = instruction_addr;
2581
2582 long tocOffset = get_load_const_from_toc_offset(iaddr);
2583 address tocLoc = iaddr + tocOffset;
2584 return *(address *)(tocLoc);
2585 } else {
2586 fprintf(stderr, "MacroAssembler::get_dest_of_call_far_patchable_at has a problem at %p:\n", instruction_addr);
2587 fprintf(stderr, "not a call_far_patchable: %16.16lx %16.16lx, len = %d\n",
2588 *(unsigned long*)instruction_addr,
2589 *(unsigned long*)(instruction_addr+8),
2590 call_far_patchable_size());
2591 Disassembler::decode(instruction_addr, instruction_addr+call_far_patchable_size());
2592 ShouldNotReachHere();
2593 return NULL;
2594 }
2595 }
2596
2597 void MacroAssembler::align_call_far_patchable(address pc) {
2598 if (call_far_patchable_requires_alignment_nop(pc)) { z_nop(); }
2599 }
2600
2601 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2602 }
2603
2604 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2605 }
2606
2607 // Read from the polling page.
2608 // Use TM or TMY instruction, depending on read offset.
2609 // offset = 0: Use TM, safepoint polling.
2610 // offset < 0: Use TMY, profiling safepoint polling.
2611 void MacroAssembler::load_from_polling_page(Register polling_page_address, int64_t offset) {
2612 if (Immediate::is_uimm12(offset)) {
2613 z_tm(offset, polling_page_address, mask_safepoint);
2614 } else {
2615 z_tmy(offset, polling_page_address, mask_profiling);
2616 }
2617 }
2618
2619 // Check whether z_instruction is a read access to the polling page
2620 // which was emitted by load_from_polling_page(..).
2621 bool MacroAssembler::is_load_from_polling_page(address instr_loc) {
2622 unsigned long z_instruction;
2623 unsigned int ilen = get_instruction(instr_loc, &z_instruction);
2624
2625 if (ilen == 2) { return false; } // It's none of the allowed instructions.
2626
2627 if (ilen == 4) {
2628 if (!is_z_tm(z_instruction)) { return false; } // It's len=4, but not a z_tm. fail.
2629
2630 int ms = inv_mask(z_instruction,8,32); // mask
2631 int ra = inv_reg(z_instruction,16,32); // base register
2632 int ds = inv_uimm12(z_instruction); // displacement
2633
2634 if (!(ds == 0 && ra != 0 && ms == mask_safepoint)) {
2635 return false; // It's not a z_tm(0, ra, mask_safepoint). Fail.
2636 }
2637
2638 } else { /* if (ilen == 6) */
2639
2640 assert(!is_z_lg(z_instruction), "old form (LG) polling page access. Please fix and use TM(Y).");
2641
2642 if (!is_z_tmy(z_instruction)) { return false; } // It's len=6, but not a z_tmy. fail.
2643
2644 int ms = inv_mask(z_instruction,8,48); // mask
2645 int ra = inv_reg(z_instruction,16,48); // base register
2646 int ds = inv_simm20(z_instruction); // displacement
2647 }
2648
2649 return true;
2650 }
2651
2652 // Extract poll address from instruction and ucontext.
2653 address MacroAssembler::get_poll_address(address instr_loc, void* ucontext) {
2654 assert(ucontext != NULL, "must have ucontext");
2655 ucontext_t* uc = (ucontext_t*) ucontext;
2656 unsigned long z_instruction;
2657 unsigned int ilen = get_instruction(instr_loc, &z_instruction);
2658
2659 if (ilen == 4 && is_z_tm(z_instruction)) {
2660 int ra = inv_reg(z_instruction, 16, 32); // base register
2661 int ds = inv_uimm12(z_instruction); // displacement
2662 address addr = (address)uc->uc_mcontext.gregs[ra];
2663 return addr + ds;
2664 } else if (ilen == 6 && is_z_tmy(z_instruction)) {
2665 int ra = inv_reg(z_instruction, 16, 48); // base register
2666 int ds = inv_simm20(z_instruction); // displacement
2667 address addr = (address)uc->uc_mcontext.gregs[ra];
2668 return addr + ds;
2669 }
2670
2671 ShouldNotReachHere();
2672 return NULL;
2673 }
2674
2675 // Extract poll register from instruction.
2676 uint MacroAssembler::get_poll_register(address instr_loc) {
2677 unsigned long z_instruction;
2678 unsigned int ilen = get_instruction(instr_loc, &z_instruction);
2679
2680 if (ilen == 4 && is_z_tm(z_instruction)) {
2681 return (uint)inv_reg(z_instruction, 16, 32); // base register
2682 } else if (ilen == 6 && is_z_tmy(z_instruction)) {
2683 return (uint)inv_reg(z_instruction, 16, 48); // base register
2684 }
2685
2686 ShouldNotReachHere();
2687 return 0;
2688 }
2689
2690 bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
2691 ShouldNotCallThis();
2692 return false;
2693 }
2694
2695 // Write serialization page so VM thread can do a pseudo remote membar
2696 // We use the current thread pointer to calculate a thread specific
2697 // offset to write to within the page. This minimizes bus traffic
2698 // due to cache line collision.
2699 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
2700 assert_different_registers(tmp1, tmp2);
2701 z_sllg(tmp2, thread, os::get_serialize_page_shift_count());
2702 load_const_optimized(tmp1, (long) os::get_memory_serialize_page());
2703
2704 int mask = os::get_serialize_page_mask();
2705 if (Immediate::is_uimm16(mask)) {
2706 z_nill(tmp2, mask);
2707 z_llghr(tmp2, tmp2);
2708 } else {
2709 z_nilf(tmp2, mask);
2710 z_llgfr(tmp2, tmp2);
2711 }
2712
2713 z_release();
2714 z_st(Z_R0, 0, tmp2, tmp1);
2715 }
2716
2717 void MacroAssembler::safepoint_poll(Label& slow_path, Register temp_reg) {
2718 if (SafepointMechanism::uses_thread_local_poll()) {
2719 const Address poll_byte_addr(Z_thread, in_bytes(Thread::polling_page_offset()) + 7 /* Big Endian */);
2720 // Armed page has poll_bit set.
2721 z_tm(poll_byte_addr, SafepointMechanism::poll_bit());
2722 z_brnaz(slow_path);
2723 } else {
2724 load_const_optimized(temp_reg, SafepointSynchronize::address_of_state());
2725 z_cli(/*SafepointSynchronize::sz_state()*/4-1, temp_reg, SafepointSynchronize::_not_synchronized);
2726 z_brne(slow_path);
2727 }
2728 }
2729
2730 // Don't rely on register locking, always use Z_R1 as scratch register instead.
2731 void MacroAssembler::bang_stack_with_offset(int offset) {
2732 // Stack grows down, caller passes positive offset.
2733 assert(offset > 0, "must bang with positive offset");
2734 if (Displacement::is_validDisp(-offset)) {
2735 z_tmy(-offset, Z_SP, mask_stackbang);
2736 } else {
2737 add2reg(Z_R1, -offset, Z_SP); // Do not destroy Z_SP!!!
2738 z_tm(0, Z_R1, mask_stackbang); // Just banging.
2739 }
2740 }
2741
2742 void MacroAssembler::reserved_stack_check(Register return_pc) {
2743 // Test if reserved zone needs to be enabled.
2744 Label no_reserved_zone_enabling;
2745 assert(return_pc == Z_R14, "Return pc must be in R14 before z_br() to StackOverflow stub.");
2746 BLOCK_COMMENT("reserved_stack_check {");
2747
2748 z_clg(Z_SP, Address(Z_thread, JavaThread::reserved_stack_activation_offset()));
2749 z_brl(no_reserved_zone_enabling);
2750
2751 // Enable reserved zone again, throw stack overflow exception.
2752 save_return_pc();
2753 push_frame_abi160(0);
2754 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), Z_thread);
2755 pop_frame();
2756 restore_return_pc();
2757
2758 load_const_optimized(Z_R1, StubRoutines::throw_delayed_StackOverflowError_entry());
2759 // Don't use call() or z_basr(), they will invalidate Z_R14 which contains the return pc.
2760 z_br(Z_R1);
2761
2762 should_not_reach_here();
2763
2764 bind(no_reserved_zone_enabling);
2765 BLOCK_COMMENT("} reserved_stack_check");
2766 }
2767
2768 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
2769 void MacroAssembler::tlab_allocate(Register obj,
2770 Register var_size_in_bytes,
2771 int con_size_in_bytes,
2772 Register t1,
2773 Label& slow_case) {
2774 assert_different_registers(obj, var_size_in_bytes, t1);
2775 Register end = t1;
2776 Register thread = Z_thread;
2777
2778 z_lg(obj, Address(thread, JavaThread::tlab_top_offset()));
2779 if (var_size_in_bytes == noreg) {
2780 z_lay(end, Address(obj, con_size_in_bytes));
2781 } else {
2782 z_lay(end, Address(obj, var_size_in_bytes));
2783 }
2784 z_cg(end, Address(thread, JavaThread::tlab_end_offset()));
2785 branch_optimized(bcondHigh, slow_case);
2786
2787 // Update the tlab top pointer.
2788 z_stg(end, Address(thread, JavaThread::tlab_top_offset()));
2789
2790 // Recover var_size_in_bytes if necessary.
2791 if (var_size_in_bytes == end) {
2792 z_sgr(var_size_in_bytes, obj);
2793 }
2794 }
2795
2796 // Emitter for interface method lookup.
2797 // input: recv_klass, intf_klass, itable_index
2798 // output: method_result
2799 // kills: itable_index, temp1_reg, Z_R0, Z_R1
2800 // TODO: Temp2_reg is unused. we may use this emitter also in the itable stubs.
2801 // If the register is still not needed then, remove it.
2802 void MacroAssembler::lookup_interface_method(Register recv_klass,
2803 Register intf_klass,
2804 RegisterOrConstant itable_index,
2805 Register method_result,
2806 Register temp1_reg,
2807 Label& no_such_interface,
2808 bool return_method) {
2809
2810 const Register vtable_len = temp1_reg; // Used to compute itable_entry_addr.
2811 const Register itable_entry_addr = Z_R1_scratch;
2812 const Register itable_interface = Z_R0_scratch;
2813
2814 BLOCK_COMMENT("lookup_interface_method {");
2815
2816 // Load start of itable entries into itable_entry_addr.
2817 z_llgf(vtable_len, Address(recv_klass, Klass::vtable_length_offset()));
2818 z_sllg(vtable_len, vtable_len, exact_log2(vtableEntry::size_in_bytes()));
2819
2820 // Loop over all itable entries until desired interfaceOop(Rinterface) found.
2821 const int vtable_base_offset = in_bytes(Klass::vtable_start_offset());
2822
2823 add2reg_with_index(itable_entry_addr,
2824 vtable_base_offset + itableOffsetEntry::interface_offset_in_bytes(),
2825 recv_klass, vtable_len);
2826
2827 const int itable_offset_search_inc = itableOffsetEntry::size() * wordSize;
2828 Label search;
2829
2830 bind(search);
2831
2832 // Handle IncompatibleClassChangeError.
2833 // If the entry is NULL then we've reached the end of the table
2834 // without finding the expected interface, so throw an exception.
2835 load_and_test_long(itable_interface, Address(itable_entry_addr));
2836 z_bre(no_such_interface);
2837
2838 add2reg(itable_entry_addr, itable_offset_search_inc);
2839 z_cgr(itable_interface, intf_klass);
2840 z_brne(search);
2841
2842 // Entry found and itable_entry_addr points to it, get offset of vtable for interface.
2843 if (return_method) {
2844 const int vtable_offset_offset = (itableOffsetEntry::offset_offset_in_bytes() -
2845 itableOffsetEntry::interface_offset_in_bytes()) -
2846 itable_offset_search_inc;
2847
2848 // Compute itableMethodEntry and get method and entry point
2849 // we use addressing with index and displacement, since the formula
2850 // for computing the entry's offset has a fixed and a dynamic part,
2851 // the latter depending on the matched interface entry and on the case,
2852 // that the itable index has been passed as a register, not a constant value.
2853 int method_offset = itableMethodEntry::method_offset_in_bytes();
2854 // Fixed part (displacement), common operand.
2855 Register itable_offset = method_result; // Dynamic part (index register).
2856
2857 if (itable_index.is_register()) {
2858 // Compute the method's offset in that register, for the formula, see the
2859 // else-clause below.
2860 z_sllg(itable_offset, itable_index.as_register(), exact_log2(itableMethodEntry::size() * wordSize));
2861 z_agf(itable_offset, vtable_offset_offset, itable_entry_addr);
2862 } else {
2863 // Displacement increases.
2864 method_offset += itableMethodEntry::size() * wordSize * itable_index.as_constant();
2865
2866 // Load index from itable.
2867 z_llgf(itable_offset, vtable_offset_offset, itable_entry_addr);
2868 }
2869
2870 // Finally load the method's oop.
2871 z_lg(method_result, method_offset, itable_offset, recv_klass);
2872 }
2873 BLOCK_COMMENT("} lookup_interface_method");
2874 }
2875
2876 // Lookup for virtual method invocation.
2877 void MacroAssembler::lookup_virtual_method(Register recv_klass,
2878 RegisterOrConstant vtable_index,
2879 Register method_result) {
2880 assert_different_registers(recv_klass, vtable_index.register_or_noreg());
2881 assert(vtableEntry::size() * wordSize == wordSize,
2882 "else adjust the scaling in the code below");
2883
2884 BLOCK_COMMENT("lookup_virtual_method {");
2885
2886 const int base = in_bytes(Klass::vtable_start_offset());
2887
2888 if (vtable_index.is_constant()) {
2889 // Load with base + disp.
2890 Address vtable_entry_addr(recv_klass,
2891 vtable_index.as_constant() * wordSize +
2892 base +
2893 vtableEntry::method_offset_in_bytes());
2894
2895 z_lg(method_result, vtable_entry_addr);
2896 } else {
2897 // Shift index properly and load with base + index + disp.
2898 Register vindex = vtable_index.as_register();
2899 Address vtable_entry_addr(recv_klass, vindex,
2900 base + vtableEntry::method_offset_in_bytes());
2901
2902 z_sllg(vindex, vindex, exact_log2(wordSize));
2903 z_lg(method_result, vtable_entry_addr);
2904 }
2905 BLOCK_COMMENT("} lookup_virtual_method");
2906 }
2907
2908 // Factor out code to call ic_miss_handler.
2909 // Generate code to call the inline cache miss handler.
2910 //
2911 // In most cases, this code will be generated out-of-line.
2912 // The method parameters are intended to provide some variability.
2913 // ICM - Label which has to be bound to the start of useful code (past any traps).
2914 // trapMarker - Marking byte for the generated illtrap instructions (if any).
2915 // Any value except 0x00 is supported.
2916 // = 0x00 - do not generate illtrap instructions.
2917 // use nops to fill ununsed space.
2918 // requiredSize - required size of the generated code. If the actually
2919 // generated code is smaller, use padding instructions to fill up.
2920 // = 0 - no size requirement, no padding.
2921 // scratch - scratch register to hold branch target address.
2922 //
2923 // The method returns the code offset of the bound label.
2924 unsigned int MacroAssembler::call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch) {
2925 intptr_t startOffset = offset();
2926
2927 // Prevent entry at content_begin().
2928 if (trapMarker != 0) {
2929 z_illtrap(trapMarker);
2930 }
2931
2932 // Load address of inline cache miss code into scratch register
2933 // and branch to cache miss handler.
2934 BLOCK_COMMENT("IC miss handler {");
2935 BIND(ICM);
2936 unsigned int labelOffset = offset();
2937 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
2938
2939 load_const_optimized(scratch, icmiss);
2940 z_br(scratch);
2941
2942 // Fill unused space.
2943 if (requiredSize > 0) {
2944 while ((offset() - startOffset) < requiredSize) {
2945 if (trapMarker == 0) {
2946 z_nop();
2947 } else {
2948 z_illtrap(trapMarker);
2949 }
2950 }
2951 }
2952 BLOCK_COMMENT("} IC miss handler");
2953 return labelOffset;
2954 }
2955
2956 void MacroAssembler::nmethod_UEP(Label& ic_miss) {
2957 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
2958 int klass_offset = oopDesc::klass_offset_in_bytes();
2959 if (!ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(klass_offset)) {
2960 if (VM_Version::has_CompareBranch()) {
2961 z_cgij(Z_ARG1, 0, Assembler::bcondEqual, ic_miss);
2962 } else {
2963 z_ltgr(Z_ARG1, Z_ARG1);
2964 z_bre(ic_miss);
2965 }
2966 }
2967 // Compare cached class against klass from receiver.
2968 compare_klass_ptr(ic_reg, klass_offset, Z_ARG1, false);
2969 z_brne(ic_miss);
2970 }
2971
2972 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2973 Register super_klass,
2974 Register temp1_reg,
2975 Label* L_success,
2976 Label* L_failure,
2977 Label* L_slow_path,
2978 RegisterOrConstant super_check_offset) {
2979
2980 const int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
2981 const int sco_offset = in_bytes(Klass::super_check_offset_offset());
2982
2983 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2984 bool need_slow_path = (must_load_sco ||
2985 super_check_offset.constant_or_zero() == sc_offset);
2986
2987 // Input registers must not overlap.
2988 assert_different_registers(sub_klass, super_klass, temp1_reg);
2989 if (super_check_offset.is_register()) {
2990 assert_different_registers(sub_klass, super_klass,
2991 super_check_offset.as_register());
2992 } else if (must_load_sco) {
2993 assert(temp1_reg != noreg, "supply either a temp or a register offset");
2994 }
2995
2996 const Register Rsuper_check_offset = temp1_reg;
2997
2998 NearLabel L_fallthrough;
2999 int label_nulls = 0;
3000 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3001 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3002 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3003 assert(label_nulls <= 1 ||
3004 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
3005 "at most one NULL in the batch, usually");
3006
3007 BLOCK_COMMENT("check_klass_subtype_fast_path {");
3008 // If the pointers are equal, we are done (e.g., String[] elements).
3009 // This self-check enables sharing of secondary supertype arrays among
3010 // non-primary types such as array-of-interface. Otherwise, each such
3011 // type would need its own customized SSA.
3012 // We move this check to the front of the fast path because many
3013 // type checks are in fact trivially successful in this manner,
3014 // so we get a nicely predicted branch right at the start of the check.
3015 compare64_and_branch(sub_klass, super_klass, bcondEqual, *L_success);
3016
3017 // Check the supertype display, which is uint.
3018 if (must_load_sco) {
3019 z_llgf(Rsuper_check_offset, sco_offset, super_klass);
3020 super_check_offset = RegisterOrConstant(Rsuper_check_offset);
3021 }
3022 Address super_check_addr(sub_klass, super_check_offset, 0);
3023 z_cg(super_klass, super_check_addr); // compare w/ displayed supertype
3024
3025 // This check has worked decisively for primary supers.
3026 // Secondary supers are sought in the super_cache ('super_cache_addr').
3027 // (Secondary supers are interfaces and very deeply nested subtypes.)
3028 // This works in the same check above because of a tricky aliasing
3029 // between the super_cache and the primary super display elements.
3030 // (The 'super_check_addr' can address either, as the case requires.)
3031 // Note that the cache is updated below if it does not help us find
3032 // what we need immediately.
3033 // So if it was a primary super, we can just fail immediately.
3034 // Otherwise, it's the slow path for us (no success at this point).
3035
3036 // Hacked jmp, which may only be used just before L_fallthrough.
3037 #define final_jmp(label) \
3038 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3039 else { branch_optimized(Assembler::bcondAlways, label); } /*omit semicolon*/
3040
3041 if (super_check_offset.is_register()) {
3042 branch_optimized(Assembler::bcondEqual, *L_success);
3043 z_cfi(super_check_offset.as_register(), sc_offset);
3044 if (L_failure == &L_fallthrough) {
3045 branch_optimized(Assembler::bcondEqual, *L_slow_path);
3046 } else {
3047 branch_optimized(Assembler::bcondNotEqual, *L_failure);
3048 final_jmp(*L_slow_path);
3049 }
3050 } else if (super_check_offset.as_constant() == sc_offset) {
3051 // Need a slow path; fast failure is impossible.
3052 if (L_slow_path == &L_fallthrough) {
3053 branch_optimized(Assembler::bcondEqual, *L_success);
3054 } else {
3055 branch_optimized(Assembler::bcondNotEqual, *L_slow_path);
3056 final_jmp(*L_success);
3057 }
3058 } else {
3059 // No slow path; it's a fast decision.
3060 if (L_failure == &L_fallthrough) {
3061 branch_optimized(Assembler::bcondEqual, *L_success);
3062 } else {
3063 branch_optimized(Assembler::bcondNotEqual, *L_failure);
3064 final_jmp(*L_success);
3065 }
3066 }
3067
3068 bind(L_fallthrough);
3069 #undef local_brc
3070 #undef final_jmp
3071 BLOCK_COMMENT("} check_klass_subtype_fast_path");
3072 // fallthru (to slow path)
3073 }
3074
3075 void MacroAssembler::check_klass_subtype_slow_path(Register Rsubklass,
3076 Register Rsuperklass,
3077 Register Rarray_ptr, // tmp
3078 Register Rlength, // tmp
3079 Label* L_success,
3080 Label* L_failure) {
3081 // Input registers must not overlap.
3082 // Also check for R1 which is explicitely used here.
3083 assert_different_registers(Z_R1, Rsubklass, Rsuperklass, Rarray_ptr, Rlength);
3084 NearLabel L_fallthrough, L_loop;
3085 int label_nulls = 0;
3086 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3087 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3088 assert(label_nulls <= 1, "at most one NULL in the batch");
3089
3090 const int ss_offset = in_bytes(Klass::secondary_supers_offset());
3091 const int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3092
3093 const int length_offset = Array<Klass*>::length_offset_in_bytes();
3094 const int base_offset = Array<Klass*>::base_offset_in_bytes();
3095
3096 // Hacked jmp, which may only be used just before L_fallthrough.
3097 #define final_jmp(label) \
3098 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3099 else branch_optimized(Assembler::bcondAlways, label) /*omit semicolon*/
3100
3101 NearLabel loop_iterate, loop_count, match;
3102
3103 BLOCK_COMMENT("check_klass_subtype_slow_path {");
3104 z_lg(Rarray_ptr, ss_offset, Rsubklass);
3105
3106 load_and_test_int(Rlength, Address(Rarray_ptr, length_offset));
3107 branch_optimized(Assembler::bcondZero, *L_failure);
3108
3109 // Oops in table are NO MORE compressed.
3110 z_cg(Rsuperklass, base_offset, Rarray_ptr); // Check array element for match.
3111 z_bre(match); // Shortcut for array length = 1.
3112
3113 // No match yet, so we must walk the array's elements.
3114 z_lngfr(Rlength, Rlength);
3115 z_sllg(Rlength, Rlength, LogBytesPerWord); // -#bytes of cache array
3116 z_llill(Z_R1, BytesPerWord); // Set increment/end index.
3117 add2reg(Rlength, 2 * BytesPerWord); // start index = -(n-2)*BytesPerWord
3118 z_slgr(Rarray_ptr, Rlength); // start addr: += (n-2)*BytesPerWord
3119 z_bru(loop_count);
3120
3121 BIND(loop_iterate);
3122 z_cg(Rsuperklass, base_offset, Rlength, Rarray_ptr); // Check array element for match.
3123 z_bre(match);
3124 BIND(loop_count);
3125 z_brxlg(Rlength, Z_R1, loop_iterate);
3126
3127 // Rsuperklass not found among secondary super classes -> failure.
3128 branch_optimized(Assembler::bcondAlways, *L_failure);
3129
3130 // Got a hit. Return success (zero result). Set cache.
3131 // Cache load doesn't happen here. For speed it is directly emitted by the compiler.
3132
3133 BIND(match);
3134
3135 z_stg(Rsuperklass, sc_offset, Rsubklass); // Save result to cache.
3136
3137 final_jmp(*L_success);
3138
3139 // Exit to the surrounding code.
3140 BIND(L_fallthrough);
3141 #undef local_brc
3142 #undef final_jmp
3143 BLOCK_COMMENT("} check_klass_subtype_slow_path");
3144 }
3145
3146 // Emitter for combining fast and slow path.
3147 void MacroAssembler::check_klass_subtype(Register sub_klass,
3148 Register super_klass,
3149 Register temp1_reg,
3150 Register temp2_reg,
3151 Label& L_success) {
3152 NearLabel failure;
3153 BLOCK_COMMENT(err_msg("check_klass_subtype(%s subclass of %s) {", sub_klass->name(), super_klass->name()));
3154 check_klass_subtype_fast_path(sub_klass, super_klass, temp1_reg,
3155 &L_success, &failure, NULL);
3156 check_klass_subtype_slow_path(sub_klass, super_klass,
3157 temp1_reg, temp2_reg, &L_success, NULL);
3158 BIND(failure);
3159 BLOCK_COMMENT("} check_klass_subtype");
3160 }
3161
3162 // Increment a counter at counter_address when the eq condition code is
3163 // set. Kills registers tmp1_reg and tmp2_reg and preserves the condition code.
3164 void MacroAssembler::increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg) {
3165 Label l;
3166 z_brne(l);
3167 load_const(tmp1_reg, counter_address);
3168 add2mem_32(Address(tmp1_reg), 1, tmp2_reg);
3169 z_cr(tmp1_reg, tmp1_reg); // Set cc to eq.
3170 bind(l);
3171 }
3172
3173 // Semantics are dependent on the slow_case label:
3174 // If the slow_case label is not NULL, failure to biased-lock the object
3175 // transfers control to the location of the slow_case label. If the
3176 // object could be biased-locked, control is transferred to the done label.
3177 // The condition code is unpredictable.
3178 //
3179 // If the slow_case label is NULL, failure to biased-lock the object results
3180 // in a transfer of control to the done label with a condition code of not_equal.
3181 // If the biased-lock could be successfully obtained, control is transfered to
3182 // the done label with a condition code of equal.
3183 // It is mandatory to react on the condition code At the done label.
3184 //
3185 void MacroAssembler::biased_locking_enter(Register obj_reg,
3186 Register mark_reg,
3187 Register temp_reg,
3188 Register temp2_reg, // May be Z_RO!
3189 Label &done,
3190 Label *slow_case) {
3191 assert(UseBiasedLocking, "why call this otherwise?");
3192 assert_different_registers(obj_reg, mark_reg, temp_reg, temp2_reg);
3193
3194 Label cas_label; // Try, if implemented, CAS locking. Fall thru to slow path otherwise.
3195
3196 BLOCK_COMMENT("biased_locking_enter {");
3197
3198 // Biased locking
3199 // See whether the lock is currently biased toward our thread and
3200 // whether the epoch is still valid.
3201 // Note that the runtime guarantees sufficient alignment of JavaThread
3202 // pointers to allow age to be placed into low bits.
3203 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits,
3204 "biased locking makes assumptions about bit layout");
3205 z_lr(temp_reg, mark_reg);
3206 z_nilf(temp_reg, markOopDesc::biased_lock_mask_in_place);
3207 z_chi(temp_reg, markOopDesc::biased_lock_pattern);
3208 z_brne(cas_label); // Try cas if object is not biased, i.e. cannot be biased locked.
3209
3210 load_prototype_header(temp_reg, obj_reg);
3211 load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
3212
3213 z_ogr(temp_reg, Z_thread);
3214 z_xgr(temp_reg, mark_reg);
3215 z_ngr(temp_reg, temp2_reg);
3216 if (PrintBiasedLockingStatistics) {
3217 increment_counter_eq((address) BiasedLocking::biased_lock_entry_count_addr(), mark_reg, temp2_reg);
3218 // Restore mark_reg.
3219 z_lg(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
3220 }
3221 branch_optimized(Assembler::bcondEqual, done); // Biased lock obtained, return success.
3222
3223 Label try_revoke_bias;
3224 Label try_rebias;
3225 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3226
3227 //----------------------------------------------------------------------------
3228 // At this point we know that the header has the bias pattern and
3229 // that we are not the bias owner in the current epoch. We need to
3230 // figure out more details about the state of the header in order to
3231 // know what operations can be legally performed on the object's
3232 // header.
3233
3234 // If the low three bits in the xor result aren't clear, that means
3235 // the prototype header is no longer biased and we have to revoke
3236 // the bias on this object.
3237 z_tmll(temp_reg, markOopDesc::biased_lock_mask_in_place);
3238 z_brnaz(try_revoke_bias);
3239
3240 // Biasing is still enabled for this data type. See whether the
3241 // epoch of the current bias is still valid, meaning that the epoch
3242 // bits of the mark word are equal to the epoch bits of the
3243 // prototype header. (Note that the prototype header's epoch bits
3244 // only change at a safepoint.) If not, attempt to rebias the object
3245 // toward the current thread. Note that we must be absolutely sure
3246 // that the current epoch is invalid in order to do this because
3247 // otherwise the manipulations it performs on the mark word are
3248 // illegal.
3249 z_tmll(temp_reg, markOopDesc::epoch_mask_in_place);
3250 z_brnaz(try_rebias);
3251
3252 //----------------------------------------------------------------------------
3253 // The epoch of the current bias is still valid but we know nothing
3254 // about the owner; it might be set or it might be clear. Try to
3255 // acquire the bias of the object using an atomic operation. If this
3256 // fails we will go in to the runtime to revoke the object's bias.
3257 // Note that we first construct the presumed unbiased header so we
3258 // don't accidentally blow away another thread's valid bias.
3259 z_nilf(mark_reg, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place |
3260 markOopDesc::epoch_mask_in_place);
3261 z_lgr(temp_reg, Z_thread);
3262 z_llgfr(mark_reg, mark_reg);
3263 z_ogr(temp_reg, mark_reg);
3264
3265 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3266
3267 z_csg(mark_reg, temp_reg, 0, obj_reg);
3268
3269 // If the biasing toward our thread failed, this means that
3270 // another thread succeeded in biasing it toward itself and we
3271 // need to revoke that bias. The revocation will occur in the
3272 // interpreter runtime in the slow case.
3273
3274 if (PrintBiasedLockingStatistics) {
3275 increment_counter_eq((address) BiasedLocking::anonymously_biased_lock_entry_count_addr(),
3276 temp_reg, temp2_reg);
3277 }
3278 if (slow_case != NULL) {
3279 branch_optimized(Assembler::bcondNotEqual, *slow_case); // Biased lock not obtained, need to go the long way.
3280 }
3281 branch_optimized(Assembler::bcondAlways, done); // Biased lock status given in condition code.
3282
3283 //----------------------------------------------------------------------------
3284 bind(try_rebias);
3285 // At this point we know the epoch has expired, meaning that the
3286 // current "bias owner", if any, is actually invalid. Under these
3287 // circumstances _only_, we are allowed to use the current header's
3288 // value as the comparison value when doing the cas to acquire the
3289 // bias in the current epoch. In other words, we allow transfer of
3290 // the bias from one thread to another directly in this situation.
3291
3292 z_nilf(mark_reg, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
3293 load_prototype_header(temp_reg, obj_reg);
3294 z_llgfr(mark_reg, mark_reg);
3295
3296 z_ogr(temp_reg, Z_thread);
3297
3298 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3299
3300 z_csg(mark_reg, temp_reg, 0, obj_reg);
3301
3302 // If the biasing toward our thread failed, this means that
3303 // another thread succeeded in biasing it toward itself and we
3304 // need to revoke that bias. The revocation will occur in the
3305 // interpreter runtime in the slow case.
3306
3307 if (PrintBiasedLockingStatistics) {
3308 increment_counter_eq((address) BiasedLocking::rebiased_lock_entry_count_addr(), temp_reg, temp2_reg);
3309 }
3310 if (slow_case != NULL) {
3311 branch_optimized(Assembler::bcondNotEqual, *slow_case); // Biased lock not obtained, need to go the long way.
3312 }
3313 z_bru(done); // Biased lock status given in condition code.
3314
3315 //----------------------------------------------------------------------------
3316 bind(try_revoke_bias);
3317 // The prototype mark in the klass doesn't have the bias bit set any
3318 // more, indicating that objects of this data type are not supposed
3319 // to be biased any more. We are going to try to reset the mark of
3320 // this object to the prototype value and fall through to the
3321 // CAS-based locking scheme. Note that if our CAS fails, it means
3322 // that another thread raced us for the privilege of revoking the
3323 // bias of this particular object, so it's okay to continue in the
3324 // normal locking code.
3325 load_prototype_header(temp_reg, obj_reg);
3326
3327 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3328
3329 z_csg(mark_reg, temp_reg, 0, obj_reg);
3330
3331 // Fall through to the normal CAS-based lock, because no matter what
3332 // the result of the above CAS, some thread must have succeeded in
3333 // removing the bias bit from the object's header.
3334 if (PrintBiasedLockingStatistics) {
3335 // z_cgr(mark_reg, temp2_reg);
3336 increment_counter_eq((address) BiasedLocking::revoked_lock_entry_count_addr(), temp_reg, temp2_reg);
3337 }
3338
3339 bind(cas_label);
3340 BLOCK_COMMENT("} biased_locking_enter");
3341 }
3342
3343 void MacroAssembler::biased_locking_exit(Register mark_addr, Register temp_reg, Label& done) {
3344 // Check for biased locking unlock case, which is a no-op
3345 // Note: we do not have to check the thread ID for two reasons.
3346 // First, the interpreter checks for IllegalMonitorStateException at
3347 // a higher level. Second, if the bias was revoked while we held the
3348 // lock, the object could not be rebiased toward another thread, so
3349 // the bias bit would be clear.
3350 BLOCK_COMMENT("biased_locking_exit {");
3351
3352 z_lg(temp_reg, 0, mark_addr);
3353 z_nilf(temp_reg, markOopDesc::biased_lock_mask_in_place);
3354
3355 z_chi(temp_reg, markOopDesc::biased_lock_pattern);
3356 z_bre(done);
3357 BLOCK_COMMENT("} biased_locking_exit");
3358 }
3359
3360 void MacroAssembler::compiler_fast_lock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias) {
3361 Register displacedHeader = temp1;
3362 Register currentHeader = temp1;
3363 Register temp = temp2;
3364 NearLabel done, object_has_monitor;
3365
3366 BLOCK_COMMENT("compiler_fast_lock_object {");
3367
3368 // Load markOop from oop into mark.
3369 z_lg(displacedHeader, 0, oop);
3370
3371 if (try_bias) {
3372 biased_locking_enter(oop, displacedHeader, temp, Z_R0, done);
3373 }
3374
3375 // Handle existing monitor.
3376 if ((EmitSync & 0x01) == 0) {
3377 // The object has an existing monitor iff (mark & monitor_value) != 0.
3378 guarantee(Immediate::is_uimm16(markOopDesc::monitor_value), "must be half-word");
3379 z_lr(temp, displacedHeader);
3380 z_nill(temp, markOopDesc::monitor_value);
3381 z_brne(object_has_monitor);
3382 }
3383
3384 // Set mark to markOop | markOopDesc::unlocked_value.
3385 z_oill(displacedHeader, markOopDesc::unlocked_value);
3386
3387 // Load Compare Value application register.
3388
3389 // Initialize the box (must happen before we update the object mark).
3390 z_stg(displacedHeader, BasicLock::displaced_header_offset_in_bytes(), box);
3391
3392 // Memory Fence (in cmpxchgd)
3393 // Compare object markOop with mark and if equal exchange scratch1 with object markOop.
3394
3395 // If the compare-and-swap succeeded, then we found an unlocked object and we
3396 // have now locked it.
3397 z_csg(displacedHeader, box, 0, oop);
3398 assert(currentHeader==displacedHeader, "must be same register"); // Identified two registers from z/Architecture.
3399 z_bre(done);
3400
3401 // We did not see an unlocked object so try the fast recursive case.
3402
3403 z_sgr(currentHeader, Z_SP);
3404 load_const_optimized(temp, (~(os::vm_page_size()-1) | markOopDesc::lock_mask_in_place));
3405
3406 z_ngr(currentHeader, temp);
3407 // z_brne(done);
3408 // z_release();
3409 z_stg(currentHeader/*==0 or not 0*/, BasicLock::displaced_header_offset_in_bytes(), box);
3410
3411 z_bru(done);
3412
3413 if ((EmitSync & 0x01) == 0) {
3414 Register zero = temp;
3415 Register monitor_tagged = displacedHeader; // Tagged with markOopDesc::monitor_value.
3416 bind(object_has_monitor);
3417 // The object's monitor m is unlocked iff m->owner == NULL,
3418 // otherwise m->owner may contain a thread or a stack address.
3419 //
3420 // Try to CAS m->owner from NULL to current thread.
3421 z_lghi(zero, 0);
3422 // If m->owner is null, then csg succeeds and sets m->owner=THREAD and CR=EQ.
3423 z_csg(zero, Z_thread, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), monitor_tagged);
3424 // Store a non-null value into the box.
3425 z_stg(box, BasicLock::displaced_header_offset_in_bytes(), box);
3426 #ifdef ASSERT
3427 z_brne(done);
3428 // We've acquired the monitor, check some invariants.
3429 // Invariant 1: _recursions should be 0.
3430 asm_assert_mem8_is_zero(OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions), monitor_tagged,
3431 "monitor->_recursions should be 0", -1);
3432 z_ltgr(zero, zero); // Set CR=EQ.
3433 #endif
3434 }
3435 bind(done);
3436
3437 BLOCK_COMMENT("} compiler_fast_lock_object");
3438 // If locking was successful, CR should indicate 'EQ'.
3439 // The compiler or the native wrapper generates a branch to the runtime call
3440 // _complete_monitor_locking_Java.
3441 }
3442
3443 void MacroAssembler::compiler_fast_unlock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias) {
3444 Register displacedHeader = temp1;
3445 Register currentHeader = temp2;
3446 Register temp = temp1;
3447 Register monitor = temp2;
3448
3449 Label done, object_has_monitor;
3450
3451 BLOCK_COMMENT("compiler_fast_unlock_object {");
3452
3453 if (try_bias) {
3454 biased_locking_exit(oop, currentHeader, done);
3455 }
3456
3457 // Find the lock address and load the displaced header from the stack.
3458 // if the displaced header is zero, we have a recursive unlock.
3459 load_and_test_long(displacedHeader, Address(box, BasicLock::displaced_header_offset_in_bytes()));
3460 z_bre(done);
3461
3462 // Handle existing monitor.
3463 if ((EmitSync & 0x02) == 0) {
3464 // The object has an existing monitor iff (mark & monitor_value) != 0.
3465 z_lg(currentHeader, oopDesc::mark_offset_in_bytes(), oop);
3466 guarantee(Immediate::is_uimm16(markOopDesc::monitor_value), "must be half-word");
3467 z_nill(currentHeader, markOopDesc::monitor_value);
3468 z_brne(object_has_monitor);
3469 }
3470
3471 // Check if it is still a light weight lock, this is true if we see
3472 // the stack address of the basicLock in the markOop of the object
3473 // copy box to currentHeader such that csg does not kill it.
3474 z_lgr(currentHeader, box);
3475 z_csg(currentHeader, displacedHeader, 0, oop);
3476 z_bru(done); // Csg sets CR as desired.
3477
3478 // Handle existing monitor.
3479 if ((EmitSync & 0x02) == 0) {
3480 bind(object_has_monitor);
3481 z_lg(currentHeader, oopDesc::mark_offset_in_bytes(), oop); // CurrentHeader is tagged with monitor_value set.
3482 load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
3483 z_brne(done);
3484 load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3485 z_brne(done);
3486 load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
3487 z_brne(done);
3488 load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
3489 z_brne(done);
3490 z_release();
3491 z_stg(temp/*=0*/, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), currentHeader);
3492 }
3493
3494 bind(done);
3495
3496 BLOCK_COMMENT("} compiler_fast_unlock_object");
3497 // flag == EQ indicates success
3498 // flag == NE indicates failure
3499 }
3500
3501 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3502 BarrierSetAssembler* bs = Universe::heap()->barrier_set()->barrier_set_assembler();
3503 bs->resolve_jobject(this, value, tmp1, tmp2);
3504 }
3505
3506 // Last_Java_sp must comply to the rules in frame_s390.hpp.
3507 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation) {
3508 BLOCK_COMMENT("set_last_Java_frame {");
3509
3510 // Always set last_Java_pc and flags first because once last_Java_sp
3511 // is visible has_last_Java_frame is true and users will look at the
3512 // rest of the fields. (Note: flags should always be zero before we
3513 // get here so doesn't need to be set.)
3514
3515 // Verify that last_Java_pc was zeroed on return to Java.
3516 if (allow_relocation) {
3517 asm_assert_mem8_is_zero(in_bytes(JavaThread::last_Java_pc_offset()),
3518 Z_thread,
3519 "last_Java_pc not zeroed before leaving Java",
3520 0x200);
3521 } else {
3522 asm_assert_mem8_is_zero_static(in_bytes(JavaThread::last_Java_pc_offset()),
3523 Z_thread,
3524 "last_Java_pc not zeroed before leaving Java",
3525 0x200);
3526 }
3527
3528 // When returning from calling out from Java mode the frame anchor's
3529 // last_Java_pc will always be set to NULL. It is set here so that
3530 // if we are doing a call to native (not VM) that we capture the
3531 // known pc and don't have to rely on the native call having a
3532 // standard frame linkage where we can find the pc.
3533 if (last_Java_pc!=noreg) {
3534 z_stg(last_Java_pc, Address(Z_thread, JavaThread::last_Java_pc_offset()));
3535 }
3536
3537 // This membar release is not required on z/Architecture, since the sequence of stores
3538 // in maintained. Nevertheless, we leave it in to document the required ordering.
3539 // The implementation of z_release() should be empty.
3540 // z_release();
3541
3542 z_stg(last_Java_sp, Address(Z_thread, JavaThread::last_Java_sp_offset()));
3543 BLOCK_COMMENT("} set_last_Java_frame");
3544 }
3545
3546 void MacroAssembler::reset_last_Java_frame(bool allow_relocation) {
3547 BLOCK_COMMENT("reset_last_Java_frame {");
3548
3549 if (allow_relocation) {
3550 asm_assert_mem8_isnot_zero(in_bytes(JavaThread::last_Java_sp_offset()),
3551 Z_thread,
3552 "SP was not set, still zero",
3553 0x202);
3554 } else {
3555 asm_assert_mem8_isnot_zero_static(in_bytes(JavaThread::last_Java_sp_offset()),
3556 Z_thread,
3557 "SP was not set, still zero",
3558 0x202);
3559 }
3560
3561 // _last_Java_sp = 0
3562 // Clearing storage must be atomic here, so don't use clear_mem()!
3563 store_const(Address(Z_thread, JavaThread::last_Java_sp_offset()), 0);
3564
3565 // _last_Java_pc = 0
3566 store_const(Address(Z_thread, JavaThread::last_Java_pc_offset()), 0);
3567
3568 BLOCK_COMMENT("} reset_last_Java_frame");
3569 return;
3570 }
3571
3572 void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation) {
3573 assert_different_registers(sp, tmp1);
3574
3575 // We cannot trust that code generated by the C++ compiler saves R14
3576 // to z_abi_160.return_pc, because sometimes it spills R14 using stmg at
3577 // z_abi_160.gpr14 (e.g. InterpreterRuntime::_new()).
3578 // Therefore we load the PC into tmp1 and let set_last_Java_frame() save
3579 // it into the frame anchor.
3580 get_PC(tmp1);
3581 set_last_Java_frame(/*sp=*/sp, /*pc=*/tmp1, allow_relocation);
3582 }
3583
3584 void MacroAssembler::set_thread_state(JavaThreadState new_state) {
3585 z_release();
3586
3587 assert(Immediate::is_uimm16(_thread_max_state), "enum value out of range for instruction");
3588 assert(sizeof(JavaThreadState) == sizeof(int), "enum value must have base type int");
3589 store_const(Address(Z_thread, JavaThread::thread_state_offset()), new_state, Z_R0, false);
3590 }
3591
3592 void MacroAssembler::get_vm_result(Register oop_result) {
3593 verify_thread();
3594
3595 z_lg(oop_result, Address(Z_thread, JavaThread::vm_result_offset()));
3596 clear_mem(Address(Z_thread, JavaThread::vm_result_offset()), sizeof(void*));
3597
3598 verify_oop(oop_result);
3599 }
3600
3601 void MacroAssembler::get_vm_result_2(Register result) {
3602 verify_thread();
3603
3604 z_lg(result, Address(Z_thread, JavaThread::vm_result_2_offset()));
3605 clear_mem(Address(Z_thread, JavaThread::vm_result_2_offset()), sizeof(void*));
3606 }
3607
3608 // We require that C code which does not return a value in vm_result will
3609 // leave it undisturbed.
3610 void MacroAssembler::set_vm_result(Register oop_result) {
3611 z_stg(oop_result, Address(Z_thread, JavaThread::vm_result_offset()));
3612 }
3613
3614 // Explicit null checks (used for method handle code).
3615 void MacroAssembler::null_check(Register reg, Register tmp, int64_t offset) {
3616 if (!ImplicitNullChecks) {
3617 NearLabel ok;
3618
3619 compare64_and_branch(reg, (intptr_t) 0, Assembler::bcondNotEqual, ok);
3620
3621 // We just put the address into reg if it was 0 (tmp==Z_R0 is allowed so we can't use it for the address).
3622 address exception_entry = Interpreter::throw_NullPointerException_entry();
3623 load_absolute_address(reg, exception_entry);
3624 z_br(reg);
3625
3626 bind(ok);
3627 } else {
3628 if (needs_explicit_null_check((intptr_t)offset)) {
3629 // Provoke OS NULL exception if reg = NULL by
3630 // accessing M[reg] w/o changing any registers.
3631 z_lg(tmp, 0, reg);
3632 }
3633 // else
3634 // Nothing to do, (later) access of M[reg + offset]
3635 // will provoke OS NULL exception if reg = NULL.
3636 }
3637 }
3638
3639 //-------------------------------------
3640 // Compressed Klass Pointers
3641 //-------------------------------------
3642
3643 // Klass oop manipulations if compressed.
3644 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3645 Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided. (dst == src) also possible.
3646 address base = Universe::narrow_klass_base();
3647 int shift = Universe::narrow_klass_shift();
3648 assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3649
3650 BLOCK_COMMENT("cKlass encoder {");
3651
3652 #ifdef ASSERT
3653 Label ok;
3654 z_tmll(current, KlassAlignmentInBytes-1); // Check alignment.
3655 z_brc(Assembler::bcondAllZero, ok);
3656 // The plain disassembler does not recognize illtrap. It instead displays
3657 // a 32-bit value. Issueing two illtraps assures the disassembler finds
3658 // the proper beginning of the next instruction.
3659 z_illtrap(0xee);
3660 z_illtrap(0xee);
3661 bind(ok);
3662 #endif
3663
3664 if (base != NULL) {
3665 unsigned int base_h = ((unsigned long)base)>>32;
3666 unsigned int base_l = (unsigned int)((unsigned long)base);
3667 if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3668 lgr_if_needed(dst, current);
3669 z_aih(dst, -((int)base_h)); // Base has no set bits in lower half.
3670 } else if ((base_h == 0) && (base_l != 0)) {
3671 lgr_if_needed(dst, current);
3672 z_agfi(dst, -(int)base_l);
3673 } else {
3674 load_const(Z_R0, base);
3675 lgr_if_needed(dst, current);
3676 z_sgr(dst, Z_R0);
3677 }
3678 current = dst;
3679 }
3680 if (shift != 0) {
3681 assert (LogKlassAlignmentInBytes == shift, "decode alg wrong");
3682 z_srlg(dst, current, shift);
3683 current = dst;
3684 }
3685 lgr_if_needed(dst, current); // Move may be required (if neither base nor shift != 0).
3686
3687 BLOCK_COMMENT("} cKlass encoder");
3688 }
3689
3690 // This function calculates the size of the code generated by
3691 // decode_klass_not_null(register dst, Register src)
3692 // when (Universe::heap() != NULL). Hence, if the instructions
3693 // it generates change, then this method needs to be updated.
3694 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3695 address base = Universe::narrow_klass_base();
3696 int shift_size = Universe::narrow_klass_shift() == 0 ? 0 : 6; /* sllg */
3697 int addbase_size = 0;
3698 assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3699
3700 if (base != NULL) {
3701 unsigned int base_h = ((unsigned long)base)>>32;
3702 unsigned int base_l = (unsigned int)((unsigned long)base);
3703 if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3704 addbase_size += 6; /* aih */
3705 } else if ((base_h == 0) && (base_l != 0)) {
3706 addbase_size += 6; /* algfi */
3707 } else {
3708 addbase_size += load_const_size();
3709 addbase_size += 4; /* algr */
3710 }
3711 }
3712 #ifdef ASSERT
3713 addbase_size += 10;
3714 addbase_size += 2; // Extra sigill.
3715 #endif
3716 return addbase_size + shift_size;
3717 }
3718
3719 // !!! If the instructions that get generated here change
3720 // then function instr_size_for_decode_klass_not_null()
3721 // needs to get updated.
3722 // This variant of decode_klass_not_null() must generate predictable code!
3723 // The code must only depend on globally known parameters.
3724 void MacroAssembler::decode_klass_not_null(Register dst) {
3725 address base = Universe::narrow_klass_base();
3726 int shift = Universe::narrow_klass_shift();
3727 int beg_off = offset();
3728 assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3729
3730 BLOCK_COMMENT("cKlass decoder (const size) {");
3731
3732 if (shift != 0) { // Shift required?
3733 z_sllg(dst, dst, shift);
3734 }
3735 if (base != NULL) {
3736 unsigned int base_h = ((unsigned long)base)>>32;
3737 unsigned int base_l = (unsigned int)((unsigned long)base);
3738 if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3739 z_aih(dst, base_h); // Base has no set bits in lower half.
3740 } else if ((base_h == 0) && (base_l != 0)) {
3741 z_algfi(dst, base_l); // Base has no set bits in upper half.
3742 } else {
3743 load_const(Z_R0, base); // Base has set bits everywhere.
3744 z_algr(dst, Z_R0);
3745 }
3746 }
3747
3748 #ifdef ASSERT
3749 Label ok;
3750 z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
3751 z_brc(Assembler::bcondAllZero, ok);
3752 // The plain disassembler does not recognize illtrap. It instead displays
3753 // a 32-bit value. Issueing two illtraps assures the disassembler finds
3754 // the proper beginning of the next instruction.
3755 z_illtrap(0xd1);
3756 z_illtrap(0xd1);
3757 bind(ok);
3758 #endif
3759 assert(offset() == beg_off + instr_size_for_decode_klass_not_null(), "Code gen mismatch.");
3760
3761 BLOCK_COMMENT("} cKlass decoder (const size)");
3762 }
3763
3764 // This variant of decode_klass_not_null() is for cases where
3765 // 1) the size of the generated instructions may vary
3766 // 2) the result is (potentially) stored in a register different from the source.
3767 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3768 address base = Universe::narrow_klass_base();
3769 int shift = Universe::narrow_klass_shift();
3770 assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3771
3772 BLOCK_COMMENT("cKlass decoder {");
3773
3774 if (src == noreg) src = dst;
3775
3776 if (shift != 0) { // Shift or at least move required?
3777 z_sllg(dst, src, shift);
3778 } else {
3779 lgr_if_needed(dst, src);
3780 }
3781
3782 if (base != NULL) {
3783 unsigned int base_h = ((unsigned long)base)>>32;
3784 unsigned int base_l = (unsigned int)((unsigned long)base);
3785 if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3786 z_aih(dst, base_h); // Base has not set bits in lower half.
3787 } else if ((base_h == 0) && (base_l != 0)) {
3788 z_algfi(dst, base_l); // Base has no set bits in upper half.
3789 } else {
3790 load_const_optimized(Z_R0, base); // Base has set bits everywhere.
3791 z_algr(dst, Z_R0);
3792 }
3793 }
3794
3795 #ifdef ASSERT
3796 Label ok;
3797 z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
3798 z_brc(Assembler::bcondAllZero, ok);
3799 // The plain disassembler does not recognize illtrap. It instead displays
3800 // a 32-bit value. Issueing two illtraps assures the disassembler finds
3801 // the proper beginning of the next instruction.
3802 z_illtrap(0xd2);
3803 z_illtrap(0xd2);
3804 bind(ok);
3805 #endif
3806 BLOCK_COMMENT("} cKlass decoder");
3807 }
3808
3809 void MacroAssembler::load_klass(Register klass, Address mem) {
3810 if (UseCompressedClassPointers) {
3811 z_llgf(klass, mem);
3812 // Attention: no null check here!
3813 decode_klass_not_null(klass);
3814 } else {
3815 z_lg(klass, mem);
3816 }
3817 }
3818
3819 void MacroAssembler::load_klass(Register klass, Register src_oop) {
3820 if (UseCompressedClassPointers) {
3821 z_llgf(klass, oopDesc::klass_offset_in_bytes(), src_oop);
3822 // Attention: no null check here!
3823 decode_klass_not_null(klass);
3824 } else {
3825 z_lg(klass, oopDesc::klass_offset_in_bytes(), src_oop);
3826 }
3827 }
3828
3829 void MacroAssembler::load_prototype_header(Register Rheader, Register Rsrc_oop) {
3830 assert_different_registers(Rheader, Rsrc_oop);
3831 load_klass(Rheader, Rsrc_oop);
3832 z_lg(Rheader, Address(Rheader, Klass::prototype_header_offset()));
3833 }
3834
3835 void MacroAssembler::store_klass(Register klass, Register dst_oop, Register ck) {
3836 if (UseCompressedClassPointers) {
3837 assert_different_registers(dst_oop, klass, Z_R0);
3838 if (ck == noreg) ck = klass;
3839 encode_klass_not_null(ck, klass);
3840 z_st(ck, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
3841 } else {
3842 z_stg(klass, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
3843 }
3844 }
3845
3846 void MacroAssembler::store_klass_gap(Register s, Register d) {
3847 if (UseCompressedClassPointers) {
3848 assert(s != d, "not enough registers");
3849 // Support s = noreg.
3850 if (s != noreg) {
3851 z_st(s, Address(d, oopDesc::klass_gap_offset_in_bytes()));
3852 } else {
3853 z_mvhi(Address(d, oopDesc::klass_gap_offset_in_bytes()), 0);
3854 }
3855 }
3856 }
3857
3858 // Compare klass ptr in memory against klass ptr in register.
3859 //
3860 // Rop1 - klass in register, always uncompressed.
3861 // disp - Offset of klass in memory, compressed/uncompressed, depending on runtime flag.
3862 // Rbase - Base address of cKlass in memory.
3863 // maybeNULL - True if Rop1 possibly is a NULL.
3864 void MacroAssembler::compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL) {
3865
3866 BLOCK_COMMENT("compare klass ptr {");
3867
3868 if (UseCompressedClassPointers) {
3869 const int shift = Universe::narrow_klass_shift();
3870 address base = Universe::narrow_klass_base();
3871
3872 assert((shift == 0) || (shift == LogKlassAlignmentInBytes), "cKlass encoder detected bad shift");
3873 assert_different_registers(Rop1, Z_R0);
3874 assert_different_registers(Rop1, Rbase, Z_R1);
3875
3876 // First encode register oop and then compare with cOop in memory.
3877 // This sequence saves an unnecessary cOop load and decode.
3878 if (base == NULL) {
3879 if (shift == 0) {
3880 z_cl(Rop1, disp, Rbase); // Unscaled
3881 } else {
3882 z_srlg(Z_R0, Rop1, shift); // ZeroBased
3883 z_cl(Z_R0, disp, Rbase);
3884 }
3885 } else { // HeapBased
3886 #ifdef ASSERT
3887 bool used_R0 = true;
3888 bool used_R1 = true;
3889 #endif
3890 Register current = Rop1;
3891 Label done;
3892
3893 if (maybeNULL) { // NULL ptr must be preserved!
3894 z_ltgr(Z_R0, current);
3895 z_bre(done);
3896 current = Z_R0;
3897 }
3898
3899 unsigned int base_h = ((unsigned long)base)>>32;
3900 unsigned int base_l = (unsigned int)((unsigned long)base);
3901 if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3902 lgr_if_needed(Z_R0, current);
3903 z_aih(Z_R0, -((int)base_h)); // Base has no set bits in lower half.
3904 } else if ((base_h == 0) && (base_l != 0)) {
3905 lgr_if_needed(Z_R0, current);
3906 z_agfi(Z_R0, -(int)base_l);
3907 } else {
3908 int pow2_offset = get_oop_base_complement(Z_R1, ((uint64_t)(intptr_t)base));
3909 add2reg_with_index(Z_R0, pow2_offset, Z_R1, Rop1); // Subtract base by adding complement.
3910 }
3911
3912 if (shift != 0) {
3913 z_srlg(Z_R0, Z_R0, shift);
3914 }
3915 bind(done);
3916 z_cl(Z_R0, disp, Rbase);
3917 #ifdef ASSERT
3918 if (used_R0) preset_reg(Z_R0, 0xb05bUL, 2);
3919 if (used_R1) preset_reg(Z_R1, 0xb06bUL, 2);
3920 #endif
3921 }
3922 } else {
3923 z_clg(Rop1, disp, Z_R0, Rbase);
3924 }
3925 BLOCK_COMMENT("} compare klass ptr");
3926 }
3927
3928 //---------------------------
3929 // Compressed oops
3930 //---------------------------
3931
3932 void MacroAssembler::encode_heap_oop(Register oop) {
3933 oop_encoder(oop, oop, true /*maybe null*/);
3934 }
3935
3936 void MacroAssembler::encode_heap_oop_not_null(Register oop) {
3937 oop_encoder(oop, oop, false /*not null*/);
3938 }
3939
3940 // Called with something derived from the oop base. e.g. oop_base>>3.
3941 int MacroAssembler::get_oop_base_pow2_offset(uint64_t oop_base) {
3942 unsigned int oop_base_ll = ((unsigned int)(oop_base >> 0)) & 0xffff;
3943 unsigned int oop_base_lh = ((unsigned int)(oop_base >> 16)) & 0xffff;
3944 unsigned int oop_base_hl = ((unsigned int)(oop_base >> 32)) & 0xffff;
3945 unsigned int oop_base_hh = ((unsigned int)(oop_base >> 48)) & 0xffff;
3946 unsigned int n_notzero_parts = (oop_base_ll == 0 ? 0:1)
3947 + (oop_base_lh == 0 ? 0:1)
3948 + (oop_base_hl == 0 ? 0:1)
3949 + (oop_base_hh == 0 ? 0:1);
3950
3951 assert(oop_base != 0, "This is for HeapBased cOops only");
3952
3953 if (n_notzero_parts != 1) { // Check if oop_base is just a few pages shy of a power of 2.
3954 uint64_t pow2_offset = 0x10000 - oop_base_ll;
3955 if (pow2_offset < 0x8000) { // This might not be necessary.
3956 uint64_t oop_base2 = oop_base + pow2_offset;
3957
3958 oop_base_ll = ((unsigned int)(oop_base2 >> 0)) & 0xffff;
3959 oop_base_lh = ((unsigned int)(oop_base2 >> 16)) & 0xffff;
3960 oop_base_hl = ((unsigned int)(oop_base2 >> 32)) & 0xffff;
3961 oop_base_hh = ((unsigned int)(oop_base2 >> 48)) & 0xffff;
3962 n_notzero_parts = (oop_base_ll == 0 ? 0:1) +
3963 (oop_base_lh == 0 ? 0:1) +
3964 (oop_base_hl == 0 ? 0:1) +
3965 (oop_base_hh == 0 ? 0:1);
3966 if (n_notzero_parts == 1) {
3967 assert(-(int64_t)pow2_offset != (int64_t)-1, "We use -1 to signal uninitialized base register");
3968 return -pow2_offset;
3969 }
3970 }
3971 }
3972 return 0;
3973 }
3974
3975 // If base address is offset from a straight power of two by just a few pages,
3976 // return this offset to the caller for a possible later composite add.
3977 // TODO/FIX: will only work correctly for 4k pages.
3978 int MacroAssembler::get_oop_base(Register Rbase, uint64_t oop_base) {
3979 int pow2_offset = get_oop_base_pow2_offset(oop_base);
3980
3981 load_const_optimized(Rbase, oop_base - pow2_offset); // Best job possible.
3982
3983 return pow2_offset;
3984 }
3985
3986 int MacroAssembler::get_oop_base_complement(Register Rbase, uint64_t oop_base) {
3987 int offset = get_oop_base(Rbase, oop_base);
3988 z_lcgr(Rbase, Rbase);
3989 return -offset;
3990 }
3991
3992 // Compare compressed oop in memory against oop in register.
3993 // Rop1 - Oop in register.
3994 // disp - Offset of cOop in memory.
3995 // Rbase - Base address of cOop in memory.
3996 // maybeNULL - True if Rop1 possibly is a NULL.
3997 // maybeNULLtarget - Branch target for Rop1 == NULL, if flow control shall NOT continue with compare instruction.
3998 void MacroAssembler::compare_heap_oop(Register Rop1, Address mem, bool maybeNULL) {
3999 Register Rbase = mem.baseOrR0();
4000 Register Rindex = mem.indexOrR0();
4001 int64_t disp = mem.disp();
4002
4003 const int shift = Universe::narrow_oop_shift();
4004 address base = Universe::narrow_oop_base();
4005
4006 assert(UseCompressedOops, "must be on to call this method");
4007 assert(Universe::heap() != NULL, "java heap must be initialized to call this method");
4008 assert((shift == 0) || (shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4009 assert_different_registers(Rop1, Z_R0);
4010 assert_different_registers(Rop1, Rbase, Z_R1);
4011 assert_different_registers(Rop1, Rindex, Z_R1);
4012
4013 BLOCK_COMMENT("compare heap oop {");
4014
4015 // First encode register oop and then compare with cOop in memory.
4016 // This sequence saves an unnecessary cOop load and decode.
4017 if (base == NULL) {
4018 if (shift == 0) {
4019 z_cl(Rop1, disp, Rindex, Rbase); // Unscaled
4020 } else {
4021 z_srlg(Z_R0, Rop1, shift); // ZeroBased
4022 z_cl(Z_R0, disp, Rindex, Rbase);
4023 }
4024 } else { // HeapBased
4025 #ifdef ASSERT
4026 bool used_R0 = true;
4027 bool used_R1 = true;
4028 #endif
4029 Label done;
4030 int pow2_offset = get_oop_base_complement(Z_R1, ((uint64_t)(intptr_t)base));
4031
4032 if (maybeNULL) { // NULL ptr must be preserved!
4033 z_ltgr(Z_R0, Rop1);
4034 z_bre(done);
4035 }
4036
4037 add2reg_with_index(Z_R0, pow2_offset, Z_R1, Rop1);
4038 z_srlg(Z_R0, Z_R0, shift);
4039
4040 bind(done);
4041 z_cl(Z_R0, disp, Rindex, Rbase);
4042 #ifdef ASSERT
4043 if (used_R0) preset_reg(Z_R0, 0xb05bUL, 2);
4044 if (used_R1) preset_reg(Z_R1, 0xb06bUL, 2);
4045 #endif
4046 }
4047 BLOCK_COMMENT("} compare heap oop");
4048 }
4049
4050 // Load heap oop and decompress, if necessary.
4051 void MacroAssembler::load_heap_oop(Register dest, const Address &a) {
4052 if (UseCompressedOops) {
4053 z_llgf(dest, a.disp(), a.indexOrR0(), a.baseOrR0());
4054 oop_decoder(dest, dest, true);
4055 } else {
4056 z_lg(dest, a.disp(), a.indexOrR0(), a.baseOrR0());
4057 }
4058 }
4059
4060 // Load heap oop and decompress, if necessary.
4061 void MacroAssembler::load_heap_oop(Register dest, int64_t disp, Register base) {
4062 if (UseCompressedOops) {
4063 z_llgf(dest, disp, base);
4064 oop_decoder(dest, dest, true);
4065 } else {
4066 z_lg(dest, disp, base);
4067 }
4068 }
4069
4070 // Load heap oop and decompress, if necessary.
4071 void MacroAssembler::load_heap_oop_not_null(Register dest, int64_t disp, Register base) {
4072 if (UseCompressedOops) {
4073 z_llgf(dest, disp, base);
4074 oop_decoder(dest, dest, false);
4075 } else {
4076 z_lg(dest, disp, base);
4077 }
4078 }
4079
4080 // Compress, if necessary, and store oop to heap.
4081 void MacroAssembler::store_heap_oop(Register Roop, RegisterOrConstant offset, Register base) {
4082 Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4083 if (UseCompressedOops) {
4084 assert_different_registers(Roop, offset.register_or_noreg(), base);
4085 encode_heap_oop(Roop);
4086 z_st(Roop, offset.constant_or_zero(), Ridx, base);
4087 } else {
4088 z_stg(Roop, offset.constant_or_zero(), Ridx, base);
4089 }
4090 }
4091
4092 // Compress, if necessary, and store oop to heap. Oop is guaranteed to be not NULL.
4093 void MacroAssembler::store_heap_oop_not_null(Register Roop, RegisterOrConstant offset, Register base) {
4094 Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4095 if (UseCompressedOops) {
4096 assert_different_registers(Roop, offset.register_or_noreg(), base);
4097 encode_heap_oop_not_null(Roop);
4098 z_st(Roop, offset.constant_or_zero(), Ridx, base);
4099 } else {
4100 z_stg(Roop, offset.constant_or_zero(), Ridx, base);
4101 }
4102 }
4103
4104 // Store NULL oop to heap.
4105 void MacroAssembler::store_heap_oop_null(Register zero, RegisterOrConstant offset, Register base) {
4106 Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4107 if (UseCompressedOops) {
4108 z_st(zero, offset.constant_or_zero(), Ridx, base);
4109 } else {
4110 z_stg(zero, offset.constant_or_zero(), Ridx, base);
4111 }
4112 }
4113
4114 //-------------------------------------------------
4115 // Encode compressed oop. Generally usable encoder.
4116 //-------------------------------------------------
4117 // Rsrc - contains regular oop on entry. It remains unchanged.
4118 // Rdst - contains compressed oop on exit.
4119 // Rdst and Rsrc may indicate same register, in which case Rsrc does not remain unchanged.
4120 //
4121 // Rdst must not indicate scratch register Z_R1 (Z_R1_scratch) for functionality.
4122 // Rdst should not indicate scratch register Z_R0 (Z_R0_scratch) for performance.
4123 //
4124 // only32bitValid is set, if later code only uses the lower 32 bits. In this
4125 // case we must not fix the upper 32 bits.
4126 void MacroAssembler::oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL,
4127 Register Rbase, int pow2_offset, bool only32bitValid) {
4128
4129 const address oop_base = Universe::narrow_oop_base();
4130 const int oop_shift = Universe::narrow_oop_shift();
4131 const bool disjoint = Universe::narrow_oop_base_disjoint();
4132
4133 assert(UseCompressedOops, "must be on to call this method");
4134 assert(Universe::heap() != NULL, "java heap must be initialized to call this encoder");
4135 assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4136
4137 if (disjoint || (oop_base == NULL)) {
4138 BLOCK_COMMENT("cOop encoder zeroBase {");
4139 if (oop_shift == 0) {
4140 if (oop_base != NULL && !only32bitValid) {
4141 z_llgfr(Rdst, Rsrc); // Clear upper bits in case the register will be decoded again.
4142 } else {
4143 lgr_if_needed(Rdst, Rsrc);
4144 }
4145 } else {
4146 z_srlg(Rdst, Rsrc, oop_shift);
4147 if (oop_base != NULL && !only32bitValid) {
4148 z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4149 }
4150 }
4151 BLOCK_COMMENT("} cOop encoder zeroBase");
4152 return;
4153 }
4154
4155 bool used_R0 = false;
4156 bool used_R1 = false;
4157
4158 BLOCK_COMMENT("cOop encoder general {");
4159 assert_different_registers(Rdst, Z_R1);
4160 assert_different_registers(Rsrc, Rbase);
4161 if (maybeNULL) {
4162 Label done;
4163 // We reorder shifting and subtracting, so that we can compare
4164 // and shift in parallel:
4165 //
4166 // cycle 0: potential LoadN, base = <const>
4167 // cycle 1: base = !base dst = src >> 3, cmp cr = (src != 0)
4168 // cycle 2: if (cr) br, dst = dst + base + offset
4169
4170 // Get oop_base components.
4171 if (pow2_offset == -1) {
4172 if (Rdst == Rbase) {
4173 if (Rdst == Z_R1 || Rsrc == Z_R1) {
4174 Rbase = Z_R0;
4175 used_R0 = true;
4176 } else {
4177 Rdst = Z_R1;
4178 used_R1 = true;
4179 }
4180 }
4181 if (Rbase == Z_R1) {
4182 used_R1 = true;
4183 }
4184 pow2_offset = get_oop_base_complement(Rbase, ((uint64_t)(intptr_t)oop_base) >> oop_shift);
4185 }
4186 assert_different_registers(Rdst, Rbase);
4187
4188 // Check for NULL oop (must be left alone) and shift.
4189 if (oop_shift != 0) { // Shift out alignment bits
4190 if (((intptr_t)oop_base&0xc000000000000000L) == 0L) { // We are sure: no single address will have the leftmost bit set.
4191 z_srag(Rdst, Rsrc, oop_shift); // Arithmetic shift sets the condition code.
4192 } else {
4193 z_srlg(Rdst, Rsrc, oop_shift);
4194 z_ltgr(Rsrc, Rsrc); // This is the recommended way of testing for zero.
4195 // This probably is faster, as it does not write a register. No!
4196 // z_cghi(Rsrc, 0);
4197 }
4198 } else {
4199 z_ltgr(Rdst, Rsrc); // Move NULL to result register.
4200 }
4201 z_bre(done);
4202
4203 // Subtract oop_base components.
4204 if ((Rdst == Z_R0) || (Rbase == Z_R0)) {
4205 z_algr(Rdst, Rbase);
4206 if (pow2_offset != 0) { add2reg(Rdst, pow2_offset); }
4207 } else {
4208 add2reg_with_index(Rdst, pow2_offset, Rbase, Rdst);
4209 }
4210 if (!only32bitValid) {
4211 z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4212 }
4213 bind(done);
4214
4215 } else { // not null
4216 // Get oop_base components.
4217 if (pow2_offset == -1) {
4218 pow2_offset = get_oop_base_complement(Rbase, (uint64_t)(intptr_t)oop_base);
4219 }
4220
4221 // Subtract oop_base components and shift.
4222 if (Rdst == Z_R0 || Rsrc == Z_R0 || Rbase == Z_R0) {
4223 // Don't use lay instruction.
4224 if (Rdst == Rsrc) {
4225 z_algr(Rdst, Rbase);
4226 } else {
4227 lgr_if_needed(Rdst, Rbase);
4228 z_algr(Rdst, Rsrc);
4229 }
4230 if (pow2_offset != 0) add2reg(Rdst, pow2_offset);
4231 } else {
4232 add2reg_with_index(Rdst, pow2_offset, Rbase, Rsrc);
4233 }
4234 if (oop_shift != 0) { // Shift out alignment bits.
4235 z_srlg(Rdst, Rdst, oop_shift);
4236 }
4237 if (!only32bitValid) {
4238 z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4239 }
4240 }
4241 #ifdef ASSERT
4242 if (used_R0 && Rdst != Z_R0 && Rsrc != Z_R0) { preset_reg(Z_R0, 0xb01bUL, 2); }
4243 if (used_R1 && Rdst != Z_R1 && Rsrc != Z_R1) { preset_reg(Z_R1, 0xb02bUL, 2); }
4244 #endif
4245 BLOCK_COMMENT("} cOop encoder general");
4246 }
4247
4248 //-------------------------------------------------
4249 // decode compressed oop. Generally usable decoder.
4250 //-------------------------------------------------
4251 // Rsrc - contains compressed oop on entry.
4252 // Rdst - contains regular oop on exit.
4253 // Rdst and Rsrc may indicate same register.
4254 // Rdst must not be the same register as Rbase, if Rbase was preloaded (before call).
4255 // Rdst can be the same register as Rbase. Then, either Z_R0 or Z_R1 must be available as scratch.
4256 // Rbase - register to use for the base
4257 // pow2_offset - offset of base to nice value. If -1, base must be loaded.
4258 // For performance, it is good to
4259 // - avoid Z_R0 for any of the argument registers.
4260 // - keep Rdst and Rsrc distinct from Rbase. Rdst == Rsrc is ok for performance.
4261 // - avoid Z_R1 for Rdst if Rdst == Rbase.
4262 void MacroAssembler::oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL, Register Rbase, int pow2_offset) {
4263
4264 const address oop_base = Universe::narrow_oop_base();
4265 const int oop_shift = Universe::narrow_oop_shift();
4266 const bool disjoint = Universe::narrow_oop_base_disjoint();
4267
4268 assert(UseCompressedOops, "must be on to call this method");
4269 assert(Universe::heap() != NULL, "java heap must be initialized to call this decoder");
4270 assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes),
4271 "cOop encoder detected bad shift");
4272
4273 // cOops are always loaded zero-extended from memory. No explicit zero-extension necessary.
4274
4275 if (oop_base != NULL) {
4276 unsigned int oop_base_hl = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xffff;
4277 unsigned int oop_base_hh = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 48)) & 0xffff;
4278 unsigned int oop_base_hf = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xFFFFffff;
4279 if (disjoint && (oop_base_hl == 0 || oop_base_hh == 0)) {
4280 BLOCK_COMMENT("cOop decoder disjointBase {");
4281 // We do not need to load the base. Instead, we can install the upper bits
4282 // with an OR instead of an ADD.
4283 Label done;
4284
4285 // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4286 if (maybeNULL) { // NULL ptr must be preserved!
4287 z_slag(Rdst, Rsrc, oop_shift); // Arithmetic shift sets the condition code.
4288 z_bre(done);
4289 } else {
4290 z_sllg(Rdst, Rsrc, oop_shift); // Logical shift leaves condition code alone.
4291 }
4292 if ((oop_base_hl != 0) && (oop_base_hh != 0)) {
4293 z_oihf(Rdst, oop_base_hf);
4294 } else if (oop_base_hl != 0) {
4295 z_oihl(Rdst, oop_base_hl);
4296 } else {
4297 assert(oop_base_hh != 0, "not heapbased mode");
4298 z_oihh(Rdst, oop_base_hh);
4299 }
4300 bind(done);
4301 BLOCK_COMMENT("} cOop decoder disjointBase");
4302 } else {
4303 BLOCK_COMMENT("cOop decoder general {");
4304 // There are three decode steps:
4305 // scale oop offset (shift left)
4306 // get base (in reg) and pow2_offset (constant)
4307 // add base, pow2_offset, and oop offset
4308 // The following register overlap situations may exist:
4309 // Rdst == Rsrc, Rbase any other
4310 // not a problem. Scaling in-place leaves Rbase undisturbed.
4311 // Loading Rbase does not impact the scaled offset.
4312 // Rdst == Rbase, Rsrc any other
4313 // scaling would destroy a possibly preloaded Rbase. Loading Rbase
4314 // would destroy the scaled offset.
4315 // Remedy: use Rdst_tmp if Rbase has been preloaded.
4316 // use Rbase_tmp if base has to be loaded.
4317 // Rsrc == Rbase, Rdst any other
4318 // Only possible without preloaded Rbase.
4319 // Loading Rbase does not destroy compressed oop because it was scaled into Rdst before.
4320 // Rsrc == Rbase, Rdst == Rbase
4321 // Only possible without preloaded Rbase.
4322 // Loading Rbase would destroy compressed oop. Scaling in-place is ok.
4323 // Remedy: use Rbase_tmp.
4324 //
4325 Label done;
4326 Register Rdst_tmp = Rdst;
4327 Register Rbase_tmp = Rbase;
4328 bool used_R0 = false;
4329 bool used_R1 = false;
4330 bool base_preloaded = pow2_offset >= 0;
4331 guarantee(!(base_preloaded && (Rsrc == Rbase)), "Register clash, check caller");
4332 assert(oop_shift != 0, "room for optimization");
4333
4334 // Check if we need to use scratch registers.
4335 if (Rdst == Rbase) {
4336 assert(!(((Rdst == Z_R0) && (Rsrc == Z_R1)) || ((Rdst == Z_R1) && (Rsrc == Z_R0))), "need a scratch reg");
4337 if (Rdst != Rsrc) {
4338 if (base_preloaded) { Rdst_tmp = (Rdst == Z_R1) ? Z_R0 : Z_R1; }
4339 else { Rbase_tmp = (Rdst == Z_R1) ? Z_R0 : Z_R1; }
4340 } else {
4341 Rbase_tmp = (Rdst == Z_R1) ? Z_R0 : Z_R1;
4342 }
4343 }
4344 if (base_preloaded) lgr_if_needed(Rbase_tmp, Rbase);
4345
4346 // Scale oop and check for NULL.
4347 // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4348 if (maybeNULL) { // NULL ptr must be preserved!
4349 z_slag(Rdst_tmp, Rsrc, oop_shift); // Arithmetic shift sets the condition code.
4350 z_bre(done);
4351 } else {
4352 z_sllg(Rdst_tmp, Rsrc, oop_shift); // Logical shift leaves condition code alone.
4353 }
4354
4355 // Get oop_base components.
4356 if (!base_preloaded) {
4357 pow2_offset = get_oop_base(Rbase_tmp, (uint64_t)(intptr_t)oop_base);
4358 }
4359
4360 // Add up all components.
4361 if ((Rbase_tmp == Z_R0) || (Rdst_tmp == Z_R0)) {
4362 z_algr(Rdst_tmp, Rbase_tmp);
4363 if (pow2_offset != 0) { add2reg(Rdst_tmp, pow2_offset); }
4364 } else {
4365 add2reg_with_index(Rdst_tmp, pow2_offset, Rbase_tmp, Rdst_tmp);
4366 }
4367
4368 bind(done);
4369 lgr_if_needed(Rdst, Rdst_tmp);
4370 #ifdef ASSERT
4371 if (used_R0 && Rdst != Z_R0 && Rsrc != Z_R0) { preset_reg(Z_R0, 0xb03bUL, 2); }
4372 if (used_R1 && Rdst != Z_R1 && Rsrc != Z_R1) { preset_reg(Z_R1, 0xb04bUL, 2); }
4373 #endif
4374 BLOCK_COMMENT("} cOop decoder general");
4375 }
4376 } else {
4377 BLOCK_COMMENT("cOop decoder zeroBase {");
4378 if (oop_shift == 0) {
4379 lgr_if_needed(Rdst, Rsrc);
4380 } else {
4381 z_sllg(Rdst, Rsrc, oop_shift);
4382 }
4383 BLOCK_COMMENT("} cOop decoder zeroBase");
4384 }
4385 }
4386
4387 // ((OopHandle)result).resolve();
4388 void MacroAssembler::resolve_oop_handle(Register result) {
4389 // OopHandle::resolve is an indirection.
4390 z_lg(result, 0, result);
4391 }
4392
4393 void MacroAssembler::load_mirror(Register mirror, Register method) {
4394 mem2reg_opt(mirror, Address(method, Method::const_offset()));
4395 mem2reg_opt(mirror, Address(mirror, ConstMethod::constants_offset()));
4396 mem2reg_opt(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
4397 mem2reg_opt(mirror, Address(mirror, Klass::java_mirror_offset()));
4398 resolve_oop_handle(mirror);
4399 }
4400
4401 //---------------------------------------------------------------
4402 //--- Operations on arrays.
4403 //---------------------------------------------------------------
4404
4405 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4406 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4407 // work registers anyway.
4408 // Actually, only r0, r1, and r5 are killed.
4409 unsigned int MacroAssembler::Clear_Array(Register cnt_arg, Register base_pointer_arg, Register src_addr, Register src_len) {
4410 // Src_addr is evenReg.
4411 // Src_len is odd_Reg.
4412
4413 int block_start = offset();
4414 Register tmp_reg = src_len; // Holds target instr addr for EX.
4415 Register dst_len = Z_R1; // Holds dst len for MVCLE.
4416 Register dst_addr = Z_R0; // Holds dst addr for MVCLE.
4417
4418 Label doXC, doMVCLE, done;
4419
4420 BLOCK_COMMENT("Clear_Array {");
4421
4422 // Check for zero len and convert to long.
4423 z_ltgfr(src_len, cnt_arg); // Remember casted value for doSTG case.
4424 z_bre(done); // Nothing to do if len == 0.
4425
4426 // Prefetch data to be cleared.
4427 if (VM_Version::has_Prefetch()) {
4428 z_pfd(0x02, 0, Z_R0, base_pointer_arg);
4429 z_pfd(0x02, 256, Z_R0, base_pointer_arg);
4430 }
4431
4432 z_sllg(dst_len, src_len, 3); // #bytes to clear.
4433 z_cghi(src_len, 32); // Check for len <= 256 bytes (<=32 DW).
4434 z_brnh(doXC); // If so, use executed XC to clear.
4435
4436 // MVCLE: initialize long arrays (general case).
4437 bind(doMVCLE);
4438 z_lgr(dst_addr, base_pointer_arg);
4439 clear_reg(src_len, true, false); // Src len of MVCLE is zero.
4440
4441 MacroAssembler::move_long_ext(dst_addr, src_addr, 0);
4442 z_bru(done);
4443
4444 // XC: initialize short arrays.
4445 Label XC_template; // Instr template, never exec directly!
4446 bind(XC_template);
4447 z_xc(0,0,base_pointer_arg,0,base_pointer_arg);
4448
4449 bind(doXC);
4450 add2reg(dst_len, -1); // Get #bytes-1 for EXECUTE.
4451 if (VM_Version::has_ExecuteExtensions()) {
4452 z_exrl(dst_len, XC_template); // Execute XC with var. len.
4453 } else {
4454 z_larl(tmp_reg, XC_template);
4455 z_ex(dst_len,0,Z_R0,tmp_reg); // Execute XC with var. len.
4456 }
4457 // z_bru(done); // fallthru
4458
4459 bind(done);
4460
4461 BLOCK_COMMENT("} Clear_Array");
4462
4463 int block_end = offset();
4464 return block_end - block_start;
4465 }
4466
4467 // Compiler ensures base is doubleword aligned and cnt is count of doublewords.
4468 // Emitter does not KILL any arguments nor work registers.
4469 // Emitter generates up to 16 XC instructions, depending on the array length.
4470 unsigned int MacroAssembler::Clear_Array_Const(long cnt, Register base) {
4471 int block_start = offset();
4472 int off;
4473 int lineSize_Bytes = AllocatePrefetchStepSize;
4474 int lineSize_DW = AllocatePrefetchStepSize>>LogBytesPerWord;
4475 bool doPrefetch = VM_Version::has_Prefetch();
4476 int XC_maxlen = 256;
4477 int numXCInstr = cnt > 0 ? (cnt*BytesPerWord-1)/XC_maxlen+1 : 0;
4478
4479 BLOCK_COMMENT("Clear_Array_Const {");
4480 assert(cnt*BytesPerWord <= 4096, "ClearArrayConst can handle 4k only");
4481
4482 // Do less prefetching for very short arrays.
4483 if (numXCInstr > 0) {
4484 // Prefetch only some cache lines, then begin clearing.
4485 if (doPrefetch) {
4486 if (cnt*BytesPerWord <= lineSize_Bytes/4) { // If less than 1/4 of a cache line to clear,
4487 z_pfd(0x02, 0, Z_R0, base); // prefetch just the first cache line.
4488 } else {
4489 assert(XC_maxlen == lineSize_Bytes, "ClearArrayConst needs 256B cache lines");
4490 for (off = 0; (off < AllocatePrefetchLines) && (off <= numXCInstr); off ++) {
4491 z_pfd(0x02, off*lineSize_Bytes, Z_R0, base);
4492 }
4493 }
4494 }
4495
4496 for (off=0; off<(numXCInstr-1); off++) {
4497 z_xc(off*XC_maxlen, XC_maxlen-1, base, off*XC_maxlen, base);
4498
4499 // Prefetch some cache lines in advance.
4500 if (doPrefetch && (off <= numXCInstr-AllocatePrefetchLines)) {
4501 z_pfd(0x02, (off+AllocatePrefetchLines)*lineSize_Bytes, Z_R0, base);
4502 }
4503 }
4504 if (off*XC_maxlen < cnt*BytesPerWord) {
4505 z_xc(off*XC_maxlen, (cnt*BytesPerWord-off*XC_maxlen)-1, base, off*XC_maxlen, base);
4506 }
4507 }
4508 BLOCK_COMMENT("} Clear_Array_Const");
4509
4510 int block_end = offset();
4511 return block_end - block_start;
4512 }
4513
4514 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4515 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4516 // work registers anyway.
4517 // Actually, only r0, r1, r4, and r5 (which are work registers) are killed.
4518 //
4519 // For very large arrays, exploit MVCLE H/W support.
4520 // MVCLE instruction automatically exploits H/W-optimized page mover.
4521 // - Bytes up to next page boundary are cleared with a series of XC to self.
4522 // - All full pages are cleared with the page mover H/W assist.
4523 // - Remaining bytes are again cleared by a series of XC to self.
4524 //
4525 unsigned int MacroAssembler::Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register src_addr, Register src_len) {
4526 // Src_addr is evenReg.
4527 // Src_len is odd_Reg.
4528
4529 int block_start = offset();
4530 Register dst_len = Z_R1; // Holds dst len for MVCLE.
4531 Register dst_addr = Z_R0; // Holds dst addr for MVCLE.
4532
4533 BLOCK_COMMENT("Clear_Array_Const_Big {");
4534
4535 // Get len to clear.
4536 load_const_optimized(dst_len, (long)cnt*8L); // in Bytes = #DW*8
4537
4538 // Prepare other args to MVCLE.
4539 z_lgr(dst_addr, base_pointer_arg);
4540 // Indicate unused result.
4541 (void) clear_reg(src_len, true, false); // Src len of MVCLE is zero.
4542
4543 // Clear.
4544 MacroAssembler::move_long_ext(dst_addr, src_addr, 0);
4545 BLOCK_COMMENT("} Clear_Array_Const_Big");
4546
4547 int block_end = offset();
4548 return block_end - block_start;
4549 }
4550
4551 // Allocator.
4552 unsigned int MacroAssembler::CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
4553 Register cnt_reg,
4554 Register tmp1_reg, Register tmp2_reg) {
4555 // Tmp1 is oddReg.
4556 // Tmp2 is evenReg.
4557
4558 int block_start = offset();
4559 Label doMVC, doMVCLE, done, MVC_template;
4560
4561 BLOCK_COMMENT("CopyRawMemory_AlignedDisjoint {");
4562
4563 // Check for zero len and convert to long.
4564 z_ltgfr(cnt_reg, cnt_reg); // Remember casted value for doSTG case.
4565 z_bre(done); // Nothing to do if len == 0.
4566
4567 z_sllg(Z_R1, cnt_reg, 3); // Dst len in bytes. calc early to have the result ready.
4568
4569 z_cghi(cnt_reg, 32); // Check for len <= 256 bytes (<=32 DW).
4570 z_brnh(doMVC); // If so, use executed MVC to clear.
4571
4572 bind(doMVCLE); // A lot of data (more than 256 bytes).
4573 // Prep dest reg pair.
4574 z_lgr(Z_R0, dst_reg); // dst addr
4575 // Dst len already in Z_R1.
4576 // Prep src reg pair.
4577 z_lgr(tmp2_reg, src_reg); // src addr
4578 z_lgr(tmp1_reg, Z_R1); // Src len same as dst len.
4579
4580 // Do the copy.
4581 move_long_ext(Z_R0, tmp2_reg, 0xb0); // Bypass cache.
4582 z_bru(done); // All done.
4583
4584 bind(MVC_template); // Just some data (not more than 256 bytes).
4585 z_mvc(0, 0, dst_reg, 0, src_reg);
4586
4587 bind(doMVC);
4588
4589 if (VM_Version::has_ExecuteExtensions()) {
4590 add2reg(Z_R1, -1);
4591 } else {
4592 add2reg(tmp1_reg, -1, Z_R1);
4593 z_larl(Z_R1, MVC_template);
4594 }
4595
4596 if (VM_Version::has_Prefetch()) {
4597 z_pfd(1, 0,Z_R0,src_reg);
4598 z_pfd(2, 0,Z_R0,dst_reg);
4599 // z_pfd(1,256,Z_R0,src_reg); // Assume very short copy.
4600 // z_pfd(2,256,Z_R0,dst_reg);
4601 }
4602
4603 if (VM_Version::has_ExecuteExtensions()) {
4604 z_exrl(Z_R1, MVC_template);
4605 } else {
4606 z_ex(tmp1_reg, 0, Z_R0, Z_R1);
4607 }
4608
4609 bind(done);
4610
4611 BLOCK_COMMENT("} CopyRawMemory_AlignedDisjoint");
4612
4613 int block_end = offset();
4614 return block_end - block_start;
4615 }
4616
4617 //------------------------------------------------------
4618 // Special String Intrinsics. Implementation
4619 //------------------------------------------------------
4620
4621 // Intrinsics for CompactStrings
4622
4623 // Compress char[] to byte[].
4624 // Restores: src, dst
4625 // Uses: cnt
4626 // Kills: tmp, Z_R0, Z_R1.
4627 // Early clobber: result.
4628 // Note:
4629 // cnt is signed int. Do not rely on high word!
4630 // counts # characters, not bytes.
4631 // The result is the number of characters copied before the first incompatible character was found.
4632 // If precise is true, the processing stops exactly at this point. Otherwise, the result may be off
4633 // by a few bytes. The result always indicates the number of copied characters.
4634 // When used as a character index, the returned value points to the first incompatible character.
4635 //
4636 // Note: Does not behave exactly like package private StringUTF16 compress java implementation in case of failure:
4637 // - Different number of characters may have been written to dead array (if precise is false).
4638 // - Returns a number <cnt instead of 0. (Result gets compared with cnt.)
4639 unsigned int MacroAssembler::string_compress(Register result, Register src, Register dst, Register cnt,
4640 Register tmp, bool precise) {
4641 assert_different_registers(Z_R0, Z_R1, result, src, dst, cnt, tmp);
4642
4643 if (precise) {
4644 BLOCK_COMMENT("encode_iso_array {");
4645 } else {
4646 BLOCK_COMMENT("string_compress {");
4647 }
4648 int block_start = offset();
4649
4650 Register Rsrc = src;
4651 Register Rdst = dst;
4652 Register Rix = tmp;
4653 Register Rcnt = cnt;
4654 Register Rmask = result; // holds incompatibility check mask until result value is stored.
4655 Label ScalarShortcut, AllDone;
4656
4657 z_iilf(Rmask, 0xFF00FF00);
4658 z_iihf(Rmask, 0xFF00FF00);
4659
4660 #if 0 // Sacrifice shortcuts for code compactness
4661 {
4662 //---< shortcuts for short strings (very frequent) >---
4663 // Strings with 4 and 8 characters were fond to occur very frequently.
4664 // Therefore, we handle them right away with minimal overhead.
4665 Label skipShortcut, skip4Shortcut, skip8Shortcut;
4666 Register Rout = Z_R0;
4667 z_chi(Rcnt, 4);
4668 z_brne(skip4Shortcut); // 4 characters are very frequent
4669 z_lg(Z_R0, 0, Rsrc); // Treat exactly 4 characters specially.
4670 if (VM_Version::has_DistinctOpnds()) {
4671 Rout = Z_R0;
4672 z_ngrk(Rix, Z_R0, Rmask);
4673 } else {
4674 Rout = Rix;
4675 z_lgr(Rix, Z_R0);
4676 z_ngr(Z_R0, Rmask);
4677 }
4678 z_brnz(skipShortcut);
4679 z_stcmh(Rout, 5, 0, Rdst);
4680 z_stcm(Rout, 5, 2, Rdst);
4681 z_lgfr(result, Rcnt);
4682 z_bru(AllDone);
4683 bind(skip4Shortcut);
4684
4685 z_chi(Rcnt, 8);
4686 z_brne(skip8Shortcut); // There's more to do...
4687 z_lmg(Z_R0, Z_R1, 0, Rsrc); // Treat exactly 8 characters specially.
4688 if (VM_Version::has_DistinctOpnds()) {
4689 Rout = Z_R0;
4690 z_ogrk(Rix, Z_R0, Z_R1);
4691 z_ngr(Rix, Rmask);
4692 } else {
4693 Rout = Rix;
4694 z_lgr(Rix, Z_R0);
4695 z_ogr(Z_R0, Z_R1);
4696 z_ngr(Z_R0, Rmask);
4697 }
4698 z_brnz(skipShortcut);
4699 z_stcmh(Rout, 5, 0, Rdst);
4700 z_stcm(Rout, 5, 2, Rdst);
4701 z_stcmh(Z_R1, 5, 4, Rdst);
4702 z_stcm(Z_R1, 5, 6, Rdst);
4703 z_lgfr(result, Rcnt);
4704 z_bru(AllDone);
4705
4706 bind(skip8Shortcut);
4707 clear_reg(Z_R0, true, false); // #characters already processed (none). Precond for scalar loop.
4708 z_brl(ScalarShortcut); // Just a few characters
4709
4710 bind(skipShortcut);
4711 }
4712 #endif
4713 clear_reg(Z_R0); // make sure register is properly initialized.
4714
4715 if (VM_Version::has_VectorFacility()) {
4716 const int min_vcnt = 32; // Minimum #characters required to use vector instructions.
4717 // Otherwise just do nothing in vector mode.
4718 // Must be multiple of 2*(vector register length in chars (8 HW = 128 bits)).
4719 const int log_min_vcnt = exact_log2(min_vcnt);
4720 Label VectorLoop, VectorDone, VectorBreak;
4721
4722 VectorRegister Vtmp1 = Z_V16;
4723 VectorRegister Vtmp2 = Z_V17;
4724 VectorRegister Vmask = Z_V18;
4725 VectorRegister Vzero = Z_V19;
4726 VectorRegister Vsrc_first = Z_V20;
4727 VectorRegister Vsrc_last = Z_V23;
4728
4729 assert((Vsrc_last->encoding() - Vsrc_first->encoding() + 1) == min_vcnt/8, "logic error");
4730 assert(VM_Version::has_DistinctOpnds(), "Assumption when has_VectorFacility()");
4731 z_srak(Rix, Rcnt, log_min_vcnt); // # vector loop iterations
4732 z_brz(VectorDone); // not enough data for vector loop
4733
4734 z_vzero(Vzero); // all zeroes
4735 z_vgmh(Vmask, 0, 7); // generate 0xff00 mask for all 2-byte elements
4736 z_sllg(Z_R0, Rix, log_min_vcnt); // remember #chars that will be processed by vector loop
4737
4738 bind(VectorLoop);
4739 z_vlm(Vsrc_first, Vsrc_last, 0, Rsrc);
4740 add2reg(Rsrc, min_vcnt*2);
4741
4742 //---< check for incompatible character >---
4743 z_vo(Vtmp1, Z_V20, Z_V21);
4744 z_vo(Vtmp2, Z_V22, Z_V23);
4745 z_vo(Vtmp1, Vtmp1, Vtmp2);
4746 z_vn(Vtmp1, Vtmp1, Vmask);
4747 z_vceqhs(Vtmp1, Vtmp1, Vzero); // high half of all chars must be zero for successful compress.
4748 z_bvnt(VectorBreak); // break vector loop if not all vector elements compare eq -> incompatible character found.
4749 // re-process data from current iteration in break handler.
4750
4751 //---< pack & store characters >---
4752 z_vpkh(Vtmp1, Z_V20, Z_V21); // pack (src1, src2) -> tmp1
4753 z_vpkh(Vtmp2, Z_V22, Z_V23); // pack (src3, src4) -> tmp2
4754 z_vstm(Vtmp1, Vtmp2, 0, Rdst); // store packed string
4755 add2reg(Rdst, min_vcnt);
4756
4757 z_brct(Rix, VectorLoop);
4758
4759 z_bru(VectorDone);
4760
4761 bind(VectorBreak);
4762 add2reg(Rsrc, -min_vcnt*2); // Fix Rsrc. Rsrc was already updated, but Rdst and Rix are not.
4763 z_sll(Rix, log_min_vcnt); // # chars processed so far in VectorLoop, excl. current iteration.
4764 z_sr(Z_R0, Rix); // correct # chars processed in total.
4765
4766 bind(VectorDone);
4767 }
4768
4769 {
4770 const int min_cnt = 8; // Minimum #characters required to use unrolled loop.
4771 // Otherwise just do nothing in unrolled loop.
4772 // Must be multiple of 8.
4773 const int log_min_cnt = exact_log2(min_cnt);
4774 Label UnrolledLoop, UnrolledDone, UnrolledBreak;
4775
4776 if (VM_Version::has_DistinctOpnds()) {
4777 z_srk(Rix, Rcnt, Z_R0); // remaining # chars to compress in unrolled loop
4778 } else {
4779 z_lr(Rix, Rcnt);
4780 z_sr(Rix, Z_R0);
4781 }
4782 z_sra(Rix, log_min_cnt); // unrolled loop count
4783 z_brz(UnrolledDone);
4784
4785 bind(UnrolledLoop);
4786 z_lmg(Z_R0, Z_R1, 0, Rsrc);
4787 if (precise) {
4788 z_ogr(Z_R1, Z_R0); // check all 8 chars for incompatibility
4789 z_ngr(Z_R1, Rmask);
4790 z_brnz(UnrolledBreak);
4791
4792 z_lg(Z_R1, 8, Rsrc); // reload destroyed register
4793 z_stcmh(Z_R0, 5, 0, Rdst);
4794 z_stcm(Z_R0, 5, 2, Rdst);
4795 } else {
4796 z_stcmh(Z_R0, 5, 0, Rdst);
4797 z_stcm(Z_R0, 5, 2, Rdst);
4798
4799 z_ogr(Z_R0, Z_R1);
4800 z_ngr(Z_R0, Rmask);
4801 z_brnz(UnrolledBreak);
4802 }
4803 z_stcmh(Z_R1, 5, 4, Rdst);
4804 z_stcm(Z_R1, 5, 6, Rdst);
4805
4806 add2reg(Rsrc, min_cnt*2);
4807 add2reg(Rdst, min_cnt);
4808 z_brct(Rix, UnrolledLoop);
4809
4810 z_lgfr(Z_R0, Rcnt); // # chars processed in total after unrolled loop.
4811 z_nilf(Z_R0, ~(min_cnt-1));
4812 z_tmll(Rcnt, min_cnt-1);
4813 z_brnaz(ScalarShortcut); // if all bits zero, there is nothing left to do for scalar loop.
4814 // Rix == 0 in all cases.
4815 z_sllg(Z_R1, Rcnt, 1); // # src bytes already processed. Only lower 32 bits are valid!
4816 // Z_R1 contents must be treated as unsigned operand! For huge strings,
4817 // (Rcnt >= 2**30), the value may spill into the sign bit by sllg.
4818 z_lgfr(result, Rcnt); // all characters processed.
4819 z_slgfr(Rdst, Rcnt); // restore ptr
4820 z_slgfr(Rsrc, Z_R1); // restore ptr, double the element count for Rsrc restore
4821 z_bru(AllDone);
4822
4823 bind(UnrolledBreak);
4824 z_lgfr(Z_R0, Rcnt); // # chars processed in total after unrolled loop
4825 z_nilf(Z_R0, ~(min_cnt-1));
4826 z_sll(Rix, log_min_cnt); // # chars not yet processed in UnrolledLoop (due to break), broken iteration not included.
4827 z_sr(Z_R0, Rix); // fix # chars processed OK so far.
4828 if (!precise) {
4829 z_lgfr(result, Z_R0);
4830 z_sllg(Z_R1, Z_R0, 1); // # src bytes already processed. Only lower 32 bits are valid!
4831 // Z_R1 contents must be treated as unsigned operand! For huge strings,
4832 // (Rcnt >= 2**30), the value may spill into the sign bit by sllg.
4833 z_aghi(result, min_cnt/2); // min_cnt/2 characters have already been written
4834 // but ptrs were not updated yet.
4835 z_slgfr(Rdst, Z_R0); // restore ptr
4836 z_slgfr(Rsrc, Z_R1); // restore ptr, double the element count for Rsrc restore
4837 z_bru(AllDone);
4838 }
4839 bind(UnrolledDone);
4840 }
4841
4842 {
4843 Label ScalarLoop, ScalarDone, ScalarBreak;
4844
4845 bind(ScalarShortcut);
4846 z_ltgfr(result, Rcnt);
4847 z_brz(AllDone);
4848
4849 #if 0 // Sacrifice shortcuts for code compactness
4850 {
4851 //---< Special treatment for very short strings (one or two characters) >---
4852 // For these strings, we are sure that the above code was skipped.
4853 // Thus, no registers were modified, register restore is not required.
4854 Label ScalarDoit, Scalar2Char;
4855 z_chi(Rcnt, 2);
4856 z_brh(ScalarDoit);
4857 z_llh(Z_R1, 0, Z_R0, Rsrc);
4858 z_bre(Scalar2Char);
4859 z_tmll(Z_R1, 0xff00);
4860 z_lghi(result, 0); // cnt == 1, first char invalid, no chars successfully processed
4861 z_brnaz(AllDone);
4862 z_stc(Z_R1, 0, Z_R0, Rdst);
4863 z_lghi(result, 1);
4864 z_bru(AllDone);
4865
4866 bind(Scalar2Char);
4867 z_llh(Z_R0, 2, Z_R0, Rsrc);
4868 z_tmll(Z_R1, 0xff00);
4869 z_lghi(result, 0); // cnt == 2, first char invalid, no chars successfully processed
4870 z_brnaz(AllDone);
4871 z_stc(Z_R1, 0, Z_R0, Rdst);
4872 z_tmll(Z_R0, 0xff00);
4873 z_lghi(result, 1); // cnt == 2, second char invalid, one char successfully processed
4874 z_brnaz(AllDone);
4875 z_stc(Z_R0, 1, Z_R0, Rdst);
4876 z_lghi(result, 2);
4877 z_bru(AllDone);
4878
4879 bind(ScalarDoit);
4880 }
4881 #endif
4882
4883 if (VM_Version::has_DistinctOpnds()) {
4884 z_srk(Rix, Rcnt, Z_R0); // remaining # chars to compress in unrolled loop
4885 } else {
4886 z_lr(Rix, Rcnt);
4887 z_sr(Rix, Z_R0);
4888 }
4889 z_lgfr(result, Rcnt); // # processed characters (if all runs ok).
4890 z_brz(ScalarDone); // uses CC from Rix calculation
4891
4892 bind(ScalarLoop);
4893 z_llh(Z_R1, 0, Z_R0, Rsrc);
4894 z_tmll(Z_R1, 0xff00);
4895 z_brnaz(ScalarBreak);
4896 z_stc(Z_R1, 0, Z_R0, Rdst);
4897 add2reg(Rsrc, 2);
4898 add2reg(Rdst, 1);
4899 z_brct(Rix, ScalarLoop);
4900
4901 z_bru(ScalarDone);
4902
4903 bind(ScalarBreak);
4904 z_sr(result, Rix);
4905
4906 bind(ScalarDone);
4907 z_sgfr(Rdst, result); // restore ptr
4908 z_sgfr(Rsrc, result); // restore ptr, double the element count for Rsrc restore
4909 z_sgfr(Rsrc, result);
4910 }
4911 bind(AllDone);
4912
4913 if (precise) {
4914 BLOCK_COMMENT("} encode_iso_array");
4915 } else {
4916 BLOCK_COMMENT("} string_compress");
4917 }
4918 return offset() - block_start;
4919 }
4920
4921 // Inflate byte[] to char[].
4922 unsigned int MacroAssembler::string_inflate_trot(Register src, Register dst, Register cnt, Register tmp) {
4923 int block_start = offset();
4924
4925 BLOCK_COMMENT("string_inflate {");
4926
4927 Register stop_char = Z_R0;
4928 Register table = Z_R1;
4929 Register src_addr = tmp;
4930
4931 assert_different_registers(Z_R0, Z_R1, tmp, src, dst, cnt);
4932 assert(dst->encoding()%2 == 0, "must be even reg");
4933 assert(cnt->encoding()%2 == 1, "must be odd reg");
4934 assert(cnt->encoding() - dst->encoding() == 1, "must be even/odd pair");
4935
4936 StubRoutines::zarch::generate_load_trot_table_addr(this, table); // kills Z_R0 (if ASSERT)
4937 clear_reg(stop_char); // Stop character. Not used here, but initialized to have a defined value.
4938 lgr_if_needed(src_addr, src);
4939 z_llgfr(cnt, cnt); // # src characters, must be a positive simm32.
4940
4941 translate_ot(dst, src_addr, /* mask = */ 0x0001);
4942
4943 BLOCK_COMMENT("} string_inflate");
4944
4945 return offset() - block_start;
4946 }
4947
4948 // Inflate byte[] to char[].
4949 // Restores: src, dst
4950 // Uses: cnt
4951 // Kills: tmp, Z_R0, Z_R1.
4952 // Note:
4953 // cnt is signed int. Do not rely on high word!
4954 // counts # characters, not bytes.
4955 unsigned int MacroAssembler::string_inflate(Register src, Register dst, Register cnt, Register tmp) {
4956 assert_different_registers(Z_R0, Z_R1, src, dst, cnt, tmp);
4957
4958 BLOCK_COMMENT("string_inflate {");
4959 int block_start = offset();
4960
4961 Register Rcnt = cnt; // # characters (src: bytes, dst: char (2-byte)), remaining after current loop.
4962 Register Rix = tmp; // loop index
4963 Register Rsrc = src; // addr(src array)
4964 Register Rdst = dst; // addr(dst array)
4965 Label ScalarShortcut, AllDone;
4966
4967 #if 0 // Sacrifice shortcuts for code compactness
4968 {
4969 //---< shortcuts for short strings (very frequent) >---
4970 Label skipShortcut, skip4Shortcut;
4971 z_ltr(Rcnt, Rcnt); // absolutely nothing to do for strings of len == 0.
4972 z_brz(AllDone);
4973 clear_reg(Z_R0); // make sure registers are properly initialized.
4974 clear_reg(Z_R1);
4975 z_chi(Rcnt, 4);
4976 z_brne(skip4Shortcut); // 4 characters are very frequent
4977 z_icm(Z_R0, 5, 0, Rsrc); // Treat exactly 4 characters specially.
4978 z_icm(Z_R1, 5, 2, Rsrc);
4979 z_stm(Z_R0, Z_R1, 0, Rdst);
4980 z_bru(AllDone);
4981 bind(skip4Shortcut);
4982
4983 z_chi(Rcnt, 8);
4984 z_brh(skipShortcut); // There's a lot to do...
4985 z_lgfr(Z_R0, Rcnt); // remaining #characters (<= 8). Precond for scalar loop.
4986 // This does not destroy the "register cleared" state of Z_R0.
4987 z_brl(ScalarShortcut); // Just a few characters
4988 z_icmh(Z_R0, 5, 0, Rsrc); // Treat exactly 8 characters specially.
4989 z_icmh(Z_R1, 5, 4, Rsrc);
4990 z_icm(Z_R0, 5, 2, Rsrc);
4991 z_icm(Z_R1, 5, 6, Rsrc);
4992 z_stmg(Z_R0, Z_R1, 0, Rdst);
4993 z_bru(AllDone);
4994 bind(skipShortcut);
4995 }
4996 #endif
4997 clear_reg(Z_R0); // make sure register is properly initialized.
4998
4999 if (VM_Version::has_VectorFacility()) {
5000 const int min_vcnt = 32; // Minimum #characters required to use vector instructions.
5001 // Otherwise just do nothing in vector mode.
5002 // Must be multiple of vector register length (16 bytes = 128 bits).
5003 const int log_min_vcnt = exact_log2(min_vcnt);
5004 Label VectorLoop, VectorDone;
5005
5006 assert(VM_Version::has_DistinctOpnds(), "Assumption when has_VectorFacility()");
5007 z_srak(Rix, Rcnt, log_min_vcnt); // calculate # vector loop iterations
5008 z_brz(VectorDone); // skip if none
5009
5010 z_sllg(Z_R0, Rix, log_min_vcnt); // remember #chars that will be processed by vector loop
5011
5012 bind(VectorLoop);
5013 z_vlm(Z_V20, Z_V21, 0, Rsrc); // get next 32 characters (single-byte)
5014 add2reg(Rsrc, min_vcnt);
5015
5016 z_vuplhb(Z_V22, Z_V20); // V2 <- (expand) V0(high)
5017 z_vupllb(Z_V23, Z_V20); // V3 <- (expand) V0(low)
5018 z_vuplhb(Z_V24, Z_V21); // V4 <- (expand) V1(high)
5019 z_vupllb(Z_V25, Z_V21); // V5 <- (expand) V1(low)
5020 z_vstm(Z_V22, Z_V25, 0, Rdst); // store next 32 bytes
5021 add2reg(Rdst, min_vcnt*2);
5022
5023 z_brct(Rix, VectorLoop);
5024
5025 bind(VectorDone);
5026 }
5027
5028 const int min_cnt = 8; // Minimum #characters required to use unrolled scalar loop.
5029 // Otherwise just do nothing in unrolled scalar mode.
5030 // Must be multiple of 8.
5031 {
5032 const int log_min_cnt = exact_log2(min_cnt);
5033 Label UnrolledLoop, UnrolledDone;
5034
5035
5036 if (VM_Version::has_DistinctOpnds()) {
5037 z_srk(Rix, Rcnt, Z_R0); // remaining # chars to process in unrolled loop
5038 } else {
5039 z_lr(Rix, Rcnt);
5040 z_sr(Rix, Z_R0);
5041 }
5042 z_sra(Rix, log_min_cnt); // unrolled loop count
5043 z_brz(UnrolledDone);
5044
5045 clear_reg(Z_R0);
5046 clear_reg(Z_R1);
5047
5048 bind(UnrolledLoop);
5049 z_icmh(Z_R0, 5, 0, Rsrc);
5050 z_icmh(Z_R1, 5, 4, Rsrc);
5051 z_icm(Z_R0, 5, 2, Rsrc);
5052 z_icm(Z_R1, 5, 6, Rsrc);
5053 add2reg(Rsrc, min_cnt);
5054
5055 z_stmg(Z_R0, Z_R1, 0, Rdst);
5056
5057 add2reg(Rdst, min_cnt*2);
5058 z_brct(Rix, UnrolledLoop);
5059
5060 bind(UnrolledDone);
5061 z_lgfr(Z_R0, Rcnt); // # chars left over after unrolled loop.
5062 z_nilf(Z_R0, min_cnt-1);
5063 z_brnz(ScalarShortcut); // if zero, there is nothing left to do for scalar loop.
5064 // Rix == 0 in all cases.
5065 z_sgfr(Z_R0, Rcnt); // negative # characters the ptrs have been advanced previously.
5066 z_agr(Rdst, Z_R0); // restore ptr, double the element count for Rdst restore.
5067 z_agr(Rdst, Z_R0);
5068 z_agr(Rsrc, Z_R0); // restore ptr.
5069 z_bru(AllDone);
5070 }
5071
5072 {
5073 bind(ScalarShortcut);
5074 // Z_R0 must contain remaining # characters as 64-bit signed int here.
5075 // register contents is preserved over scalar processing (for register fixup).
5076
5077 #if 0 // Sacrifice shortcuts for code compactness
5078 {
5079 Label ScalarDefault;
5080 z_chi(Rcnt, 2);
5081 z_brh(ScalarDefault);
5082 z_llc(Z_R0, 0, Z_R0, Rsrc); // 6 bytes
5083 z_sth(Z_R0, 0, Z_R0, Rdst); // 4 bytes
5084 z_brl(AllDone);
5085 z_llc(Z_R0, 1, Z_R0, Rsrc); // 6 bytes
5086 z_sth(Z_R0, 2, Z_R0, Rdst); // 4 bytes
5087 z_bru(AllDone);
5088 bind(ScalarDefault);
5089 }
5090 #endif
5091
5092 Label CodeTable;
5093 // Some comments on Rix calculation:
5094 // - Rcnt is small, therefore no bits shifted out of low word (sll(g) instructions).
5095 // - high word of both Rix and Rcnt may contain garbage
5096 // - the final lngfr takes care of that garbage, extending the sign to high word
5097 z_sllg(Rix, Z_R0, 2); // calculate 10*Rix = (4*Rix + Rix)*2
5098 z_ar(Rix, Z_R0);
5099 z_larl(Z_R1, CodeTable);
5100 z_sll(Rix, 1);
5101 z_lngfr(Rix, Rix); // ix range: [0..7], after inversion & mult: [-(7*12)..(0*12)].
5102 z_bc(Assembler::bcondAlways, 0, Rix, Z_R1);
5103
5104 z_llc(Z_R1, 6, Z_R0, Rsrc); // 6 bytes
5105 z_sth(Z_R1, 12, Z_R0, Rdst); // 4 bytes
5106
5107 z_llc(Z_R1, 5, Z_R0, Rsrc);
5108 z_sth(Z_R1, 10, Z_R0, Rdst);
5109
5110 z_llc(Z_R1, 4, Z_R0, Rsrc);
5111 z_sth(Z_R1, 8, Z_R0, Rdst);
5112
5113 z_llc(Z_R1, 3, Z_R0, Rsrc);
5114 z_sth(Z_R1, 6, Z_R0, Rdst);
5115
5116 z_llc(Z_R1, 2, Z_R0, Rsrc);
5117 z_sth(Z_R1, 4, Z_R0, Rdst);
5118
5119 z_llc(Z_R1, 1, Z_R0, Rsrc);
5120 z_sth(Z_R1, 2, Z_R0, Rdst);
5121
5122 z_llc(Z_R1, 0, Z_R0, Rsrc);
5123 z_sth(Z_R1, 0, Z_R0, Rdst);
5124 bind(CodeTable);
5125
5126 z_chi(Rcnt, 8); // no fixup for small strings. Rdst, Rsrc were not modified.
5127 z_brl(AllDone);
5128
5129 z_sgfr(Z_R0, Rcnt); // # characters the ptrs have been advanced previously.
5130 z_agr(Rdst, Z_R0); // restore ptr, double the element count for Rdst restore.
5131 z_agr(Rdst, Z_R0);
5132 z_agr(Rsrc, Z_R0); // restore ptr.
5133 }
5134 bind(AllDone);
5135
5136 BLOCK_COMMENT("} string_inflate");
5137 return offset() - block_start;
5138 }
5139
5140 // Inflate byte[] to char[], length known at compile time.
5141 // Restores: src, dst
5142 // Kills: tmp, Z_R0, Z_R1.
5143 // Note:
5144 // len is signed int. Counts # characters, not bytes.
5145 unsigned int MacroAssembler::string_inflate_const(Register src, Register dst, Register tmp, int len) {
5146 assert_different_registers(Z_R0, Z_R1, src, dst, tmp);
5147
5148 BLOCK_COMMENT("string_inflate_const {");
5149 int block_start = offset();
5150
5151 Register Rix = tmp; // loop index
5152 Register Rsrc = src; // addr(src array)
5153 Register Rdst = dst; // addr(dst array)
5154 Label ScalarShortcut, AllDone;
5155 int nprocessed = 0;
5156 int src_off = 0; // compensate for saved (optimized away) ptr advancement.
5157 int dst_off = 0; // compensate for saved (optimized away) ptr advancement.
5158 bool restore_inputs = false;
5159 bool workreg_clear = false;
5160
5161 if ((len >= 32) && VM_Version::has_VectorFacility()) {
5162 const int min_vcnt = 32; // Minimum #characters required to use vector instructions.
5163 // Otherwise just do nothing in vector mode.
5164 // Must be multiple of vector register length (16 bytes = 128 bits).
5165 const int log_min_vcnt = exact_log2(min_vcnt);
5166 const int iterations = (len - nprocessed) >> log_min_vcnt;
5167 nprocessed += iterations << log_min_vcnt;
5168 Label VectorLoop;
5169
5170 if (iterations == 1) {
5171 z_vlm(Z_V20, Z_V21, 0+src_off, Rsrc); // get next 32 characters (single-byte)
5172 z_vuplhb(Z_V22, Z_V20); // V2 <- (expand) V0(high)
5173 z_vupllb(Z_V23, Z_V20); // V3 <- (expand) V0(low)
5174 z_vuplhb(Z_V24, Z_V21); // V4 <- (expand) V1(high)
5175 z_vupllb(Z_V25, Z_V21); // V5 <- (expand) V1(low)
5176 z_vstm(Z_V22, Z_V25, 0+dst_off, Rdst); // store next 32 bytes
5177
5178 src_off += min_vcnt;
5179 dst_off += min_vcnt*2;
5180 } else {
5181 restore_inputs = true;
5182
5183 z_lgfi(Rix, len>>log_min_vcnt);
5184 bind(VectorLoop);
5185 z_vlm(Z_V20, Z_V21, 0, Rsrc); // get next 32 characters (single-byte)
5186 add2reg(Rsrc, min_vcnt);
5187
5188 z_vuplhb(Z_V22, Z_V20); // V2 <- (expand) V0(high)
5189 z_vupllb(Z_V23, Z_V20); // V3 <- (expand) V0(low)
5190 z_vuplhb(Z_V24, Z_V21); // V4 <- (expand) V1(high)
5191 z_vupllb(Z_V25, Z_V21); // V5 <- (expand) V1(low)
5192 z_vstm(Z_V22, Z_V25, 0, Rdst); // store next 32 bytes
5193 add2reg(Rdst, min_vcnt*2);
5194
5195 z_brct(Rix, VectorLoop);
5196 }
5197 }
5198
5199 if (((len-nprocessed) >= 16) && VM_Version::has_VectorFacility()) {
5200 const int min_vcnt = 16; // Minimum #characters required to use vector instructions.
5201 // Otherwise just do nothing in vector mode.
5202 // Must be multiple of vector register length (16 bytes = 128 bits).
5203 const int log_min_vcnt = exact_log2(min_vcnt);
5204 const int iterations = (len - nprocessed) >> log_min_vcnt;
5205 nprocessed += iterations << log_min_vcnt;
5206 assert(iterations == 1, "must be!");
5207
5208 z_vl(Z_V20, 0+src_off, Z_R0, Rsrc); // get next 16 characters (single-byte)
5209 z_vuplhb(Z_V22, Z_V20); // V2 <- (expand) V0(high)
5210 z_vupllb(Z_V23, Z_V20); // V3 <- (expand) V0(low)
5211 z_vstm(Z_V22, Z_V23, 0+dst_off, Rdst); // store next 32 bytes
5212
5213 src_off += min_vcnt;
5214 dst_off += min_vcnt*2;
5215 }
5216
5217 if ((len-nprocessed) > 8) {
5218 const int min_cnt = 8; // Minimum #characters required to use unrolled scalar loop.
5219 // Otherwise just do nothing in unrolled scalar mode.
5220 // Must be multiple of 8.
5221 const int log_min_cnt = exact_log2(min_cnt);
5222 const int iterations = (len - nprocessed) >> log_min_cnt;
5223 nprocessed += iterations << log_min_cnt;
5224
5225 //---< avoid loop overhead/ptr increment for small # iterations >---
5226 if (iterations <= 2) {
5227 clear_reg(Z_R0);
5228 clear_reg(Z_R1);
5229 workreg_clear = true;
5230
5231 z_icmh(Z_R0, 5, 0+src_off, Rsrc);
5232 z_icmh(Z_R1, 5, 4+src_off, Rsrc);
5233 z_icm(Z_R0, 5, 2+src_off, Rsrc);
5234 z_icm(Z_R1, 5, 6+src_off, Rsrc);
5235 z_stmg(Z_R0, Z_R1, 0+dst_off, Rdst);
5236
5237 src_off += min_cnt;
5238 dst_off += min_cnt*2;
5239 }
5240
5241 if (iterations == 2) {
5242 z_icmh(Z_R0, 5, 0+src_off, Rsrc);
5243 z_icmh(Z_R1, 5, 4+src_off, Rsrc);
5244 z_icm(Z_R0, 5, 2+src_off, Rsrc);
5245 z_icm(Z_R1, 5, 6+src_off, Rsrc);
5246 z_stmg(Z_R0, Z_R1, 0+dst_off, Rdst);
5247
5248 src_off += min_cnt;
5249 dst_off += min_cnt*2;
5250 }
5251
5252 if (iterations > 2) {
5253 Label UnrolledLoop;
5254 restore_inputs = true;
5255
5256 clear_reg(Z_R0);
5257 clear_reg(Z_R1);
5258 workreg_clear = true;
5259
5260 z_lgfi(Rix, iterations);
5261 bind(UnrolledLoop);
5262 z_icmh(Z_R0, 5, 0, Rsrc);
5263 z_icmh(Z_R1, 5, 4, Rsrc);
5264 z_icm(Z_R0, 5, 2, Rsrc);
5265 z_icm(Z_R1, 5, 6, Rsrc);
5266 add2reg(Rsrc, min_cnt);
5267
5268 z_stmg(Z_R0, Z_R1, 0, Rdst);
5269 add2reg(Rdst, min_cnt*2);
5270
5271 z_brct(Rix, UnrolledLoop);
5272 }
5273 }
5274
5275 if ((len-nprocessed) > 0) {
5276 switch (len-nprocessed) {
5277 case 8:
5278 if (!workreg_clear) {
5279 clear_reg(Z_R0);
5280 clear_reg(Z_R1);
5281 }
5282 z_icmh(Z_R0, 5, 0+src_off, Rsrc);
5283 z_icmh(Z_R1, 5, 4+src_off, Rsrc);
5284 z_icm(Z_R0, 5, 2+src_off, Rsrc);
5285 z_icm(Z_R1, 5, 6+src_off, Rsrc);
5286 z_stmg(Z_R0, Z_R1, 0+dst_off, Rdst);
5287 break;
5288 case 7:
5289 if (!workreg_clear) {
5290 clear_reg(Z_R0);
5291 clear_reg(Z_R1);
5292 }
5293 clear_reg(Rix);
5294 z_icm(Z_R0, 5, 0+src_off, Rsrc);
5295 z_icm(Z_R1, 5, 2+src_off, Rsrc);
5296 z_icm(Rix, 5, 4+src_off, Rsrc);
5297 z_stm(Z_R0, Z_R1, 0+dst_off, Rdst);
5298 z_llc(Z_R0, 6+src_off, Z_R0, Rsrc);
5299 z_st(Rix, 8+dst_off, Z_R0, Rdst);
5300 z_sth(Z_R0, 12+dst_off, Z_R0, Rdst);
5301 break;
5302 case 6:
5303 if (!workreg_clear) {
5304 clear_reg(Z_R0);
5305 clear_reg(Z_R1);
5306 }
5307 clear_reg(Rix);
5308 z_icm(Z_R0, 5, 0+src_off, Rsrc);
5309 z_icm(Z_R1, 5, 2+src_off, Rsrc);
5310 z_icm(Rix, 5, 4+src_off, Rsrc);
5311 z_stm(Z_R0, Z_R1, 0+dst_off, Rdst);
5312 z_st(Rix, 8+dst_off, Z_R0, Rdst);
5313 break;
5314 case 5:
5315 if (!workreg_clear) {
5316 clear_reg(Z_R0);
5317 clear_reg(Z_R1);
5318 }
5319 z_icm(Z_R0, 5, 0+src_off, Rsrc);
5320 z_icm(Z_R1, 5, 2+src_off, Rsrc);
5321 z_llc(Rix, 4+src_off, Z_R0, Rsrc);
5322 z_stm(Z_R0, Z_R1, 0+dst_off, Rdst);
5323 z_sth(Rix, 8+dst_off, Z_R0, Rdst);
5324 break;
5325 case 4:
5326 if (!workreg_clear) {
5327 clear_reg(Z_R0);
5328 clear_reg(Z_R1);
5329 }
5330 z_icm(Z_R0, 5, 0+src_off, Rsrc);
5331 z_icm(Z_R1, 5, 2+src_off, Rsrc);
5332 z_stm(Z_R0, Z_R1, 0+dst_off, Rdst);
5333 break;
5334 case 3:
5335 if (!workreg_clear) {
5336 clear_reg(Z_R0);
5337 }
5338 z_llc(Z_R1, 2+src_off, Z_R0, Rsrc);
5339 z_icm(Z_R0, 5, 0+src_off, Rsrc);
5340 z_sth(Z_R1, 4+dst_off, Z_R0, Rdst);
5341 z_st(Z_R0, 0+dst_off, Rdst);
5342 break;
5343 case 2:
5344 z_llc(Z_R0, 0+src_off, Z_R0, Rsrc);
5345 z_llc(Z_R1, 1+src_off, Z_R0, Rsrc);
5346 z_sth(Z_R0, 0+dst_off, Z_R0, Rdst);
5347 z_sth(Z_R1, 2+dst_off, Z_R0, Rdst);
5348 break;
5349 case 1:
5350 z_llc(Z_R0, 0+src_off, Z_R0, Rsrc);
5351 z_sth(Z_R0, 0+dst_off, Z_R0, Rdst);
5352 break;
5353 default:
5354 guarantee(false, "Impossible");
5355 break;
5356 }
5357 src_off += len-nprocessed;
5358 dst_off += (len-nprocessed)*2;
5359 nprocessed = len;
5360 }
5361
5362 //---< restore modified input registers >---
5363 if ((nprocessed > 0) && restore_inputs) {
5364 z_agfi(Rsrc, -(nprocessed-src_off));
5365 if (nprocessed < 1000000000) { // avoid int overflow
5366 z_agfi(Rdst, -(nprocessed*2-dst_off));
5367 } else {
5368 z_agfi(Rdst, -(nprocessed-dst_off));
5369 z_agfi(Rdst, -nprocessed);
5370 }
5371 }
5372
5373 BLOCK_COMMENT("} string_inflate_const");
5374 return offset() - block_start;
5375 }
5376
5377 // Kills src.
5378 unsigned int MacroAssembler::has_negatives(Register result, Register src, Register cnt,
5379 Register odd_reg, Register even_reg, Register tmp) {
5380 int block_start = offset();
5381 Label Lloop1, Lloop2, Lslow, Lnotfound, Ldone;
5382 const Register addr = src, mask = tmp;
5383
5384 BLOCK_COMMENT("has_negatives {");
5385
5386 z_llgfr(Z_R1, cnt); // Number of bytes to read. (Must be a positive simm32.)
5387 z_llilf(mask, 0x80808080);
5388 z_lhi(result, 1); // Assume true.
5389 // Last possible addr for fast loop.
5390 z_lay(odd_reg, -16, Z_R1, src);
5391 z_chi(cnt, 16);
5392 z_brl(Lslow);
5393
5394 // ind1: index, even_reg: index increment, odd_reg: index limit
5395 z_iihf(mask, 0x80808080);
5396 z_lghi(even_reg, 16);
5397
5398 bind(Lloop1); // 16 bytes per iteration.
5399 z_lg(Z_R0, Address(addr));
5400 z_lg(Z_R1, Address(addr, 8));
5401 z_ogr(Z_R0, Z_R1);
5402 z_ngr(Z_R0, mask);
5403 z_brne(Ldone); // If found return 1.
5404 z_brxlg(addr, even_reg, Lloop1);
5405
5406 bind(Lslow);
5407 z_aghi(odd_reg, 16-1); // Last possible addr for slow loop.
5408 z_lghi(even_reg, 1);
5409 z_cgr(addr, odd_reg);
5410 z_brh(Lnotfound);
5411
5412 bind(Lloop2); // 1 byte per iteration.
5413 z_cli(Address(addr), 0x80);
5414 z_brnl(Ldone); // If found return 1.
5415 z_brxlg(addr, even_reg, Lloop2);
5416
5417 bind(Lnotfound);
5418 z_lhi(result, 0);
5419
5420 bind(Ldone);
5421
5422 BLOCK_COMMENT("} has_negatives");
5423
5424 return offset() - block_start;
5425 }
5426
5427 // kill: cnt1, cnt2, odd_reg, even_reg; early clobber: result
5428 unsigned int MacroAssembler::string_compare(Register str1, Register str2,
5429 Register cnt1, Register cnt2,
5430 Register odd_reg, Register even_reg, Register result, int ae) {
5431 int block_start = offset();
5432
5433 assert_different_registers(str1, cnt1, cnt2, odd_reg, even_reg, result);
5434 assert_different_registers(str2, cnt1, cnt2, odd_reg, even_reg, result);
5435
5436 // If strings are equal up to min length, return the length difference.
5437 const Register diff = result, // Pre-set result with length difference.
5438 min = cnt1, // min number of bytes
5439 tmp = cnt2;
5440
5441 // Note: Making use of the fact that compareTo(a, b) == -compareTo(b, a)
5442 // we interchange str1 and str2 in the UL case and negate the result.
5443 // Like this, str1 is always latin1 encoded, except for the UU case.
5444 // In addition, we need 0 (or sign which is 0) extend when using 64 bit register.
5445 const bool used_as_LU = (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL);
5446
5447 BLOCK_COMMENT("string_compare {");
5448
5449 if (used_as_LU) {
5450 z_srl(cnt2, 1);
5451 }
5452
5453 // See if the lengths are different, and calculate min in cnt1.
5454 // Save diff in case we need it for a tie-breaker.
5455
5456 // diff = cnt1 - cnt2
5457 if (VM_Version::has_DistinctOpnds()) {
5458 z_srk(diff, cnt1, cnt2);
5459 } else {
5460 z_lr(diff, cnt1);
5461 z_sr(diff, cnt2);
5462 }
5463 if (str1 != str2) {
5464 if (VM_Version::has_LoadStoreConditional()) {
5465 z_locr(min, cnt2, Assembler::bcondHigh);
5466 } else {
5467 Label Lskip;
5468 z_brl(Lskip); // min ok if cnt1 < cnt2
5469 z_lr(min, cnt2); // min = cnt2
5470 bind(Lskip);
5471 }
5472 }
5473
5474 if (ae == StrIntrinsicNode::UU) {
5475 z_sra(diff, 1);
5476 }
5477 if (str1 != str2) {
5478 Label Ldone;
5479 if (used_as_LU) {
5480 // Loop which searches the first difference character by character.
5481 Label Lloop;
5482 const Register ind1 = Z_R1,
5483 ind2 = min;
5484 int stride1 = 1, stride2 = 2; // See comment above.
5485
5486 // ind1: index, even_reg: index increment, odd_reg: index limit
5487 z_llilf(ind1, (unsigned int)(-stride1));
5488 z_lhi(even_reg, stride1);
5489 add2reg(odd_reg, -stride1, min);
5490 clear_reg(ind2); // kills min
5491
5492 bind(Lloop);
5493 z_brxh(ind1, even_reg, Ldone);
5494 z_llc(tmp, Address(str1, ind1));
5495 z_llh(Z_R0, Address(str2, ind2));
5496 z_ahi(ind2, stride2);
5497 z_sr(tmp, Z_R0);
5498 z_bre(Lloop);
5499
5500 z_lr(result, tmp);
5501
5502 } else {
5503 // Use clcle in fast loop (only for same encoding).
5504 z_lgr(Z_R0, str1);
5505 z_lgr(even_reg, str2);
5506 z_llgfr(Z_R1, min);
5507 z_llgfr(odd_reg, min);
5508
5509 if (ae == StrIntrinsicNode::LL) {
5510 compare_long_ext(Z_R0, even_reg, 0);
5511 } else {
5512 compare_long_uni(Z_R0, even_reg, 0);
5513 }
5514 z_bre(Ldone);
5515 z_lgr(Z_R1, Z_R0);
5516 if (ae == StrIntrinsicNode::LL) {
5517 z_llc(Z_R0, Address(even_reg));
5518 z_llc(result, Address(Z_R1));
5519 } else {
5520 z_llh(Z_R0, Address(even_reg));
5521 z_llh(result, Address(Z_R1));
5522 }
5523 z_sr(result, Z_R0);
5524 }
5525
5526 // Otherwise, return the difference between the first mismatched chars.
5527 bind(Ldone);
5528 }
5529
5530 if (ae == StrIntrinsicNode::UL) {
5531 z_lcr(result, result); // Negate result (see note above).
5532 }
5533
5534 BLOCK_COMMENT("} string_compare");
5535
5536 return offset() - block_start;
5537 }
5538
5539 unsigned int MacroAssembler::array_equals(bool is_array_equ, Register ary1, Register ary2, Register limit,
5540 Register odd_reg, Register even_reg, Register result, bool is_byte) {
5541 int block_start = offset();
5542
5543 BLOCK_COMMENT("array_equals {");
5544
5545 assert_different_registers(ary1, limit, odd_reg, even_reg);
5546 assert_different_registers(ary2, limit, odd_reg, even_reg);
5547
5548 Label Ldone, Ldone_true, Ldone_false, Lclcle, CLC_template;
5549 int base_offset = 0;
5550
5551 if (ary1 != ary2) {
5552 if (is_array_equ) {
5553 base_offset = arrayOopDesc::base_offset_in_bytes(is_byte ? T_BYTE : T_CHAR);
5554
5555 // Return true if the same array.
5556 compareU64_and_branch(ary1, ary2, Assembler::bcondEqual, Ldone_true);
5557
5558 // Return false if one of them is NULL.
5559 compareU64_and_branch(ary1, (intptr_t)0, Assembler::bcondEqual, Ldone_false);
5560 compareU64_and_branch(ary2, (intptr_t)0, Assembler::bcondEqual, Ldone_false);
5561
5562 // Load the lengths of arrays.
5563 z_llgf(odd_reg, Address(ary1, arrayOopDesc::length_offset_in_bytes()));
5564
5565 // Return false if the two arrays are not equal length.
5566 z_c(odd_reg, Address(ary2, arrayOopDesc::length_offset_in_bytes()));
5567 z_brne(Ldone_false);
5568
5569 // string len in bytes (right operand)
5570 if (!is_byte) {
5571 z_chi(odd_reg, 128);
5572 z_sll(odd_reg, 1); // preserves flags
5573 z_brh(Lclcle);
5574 } else {
5575 compareU32_and_branch(odd_reg, (intptr_t)256, Assembler::bcondHigh, Lclcle);
5576 }
5577 } else {
5578 z_llgfr(odd_reg, limit); // Need to zero-extend prior to using the value.
5579 compareU32_and_branch(limit, (intptr_t)256, Assembler::bcondHigh, Lclcle);
5580 }
5581
5582
5583 // Use clc instruction for up to 256 bytes.
5584 {
5585 Register str1_reg = ary1,
5586 str2_reg = ary2;
5587 if (is_array_equ) {
5588 str1_reg = Z_R1;
5589 str2_reg = even_reg;
5590 add2reg(str1_reg, base_offset, ary1); // string addr (left operand)
5591 add2reg(str2_reg, base_offset, ary2); // string addr (right operand)
5592 }
5593 z_ahi(odd_reg, -1); // Clc uses decremented limit. Also compare result to 0.
5594 z_brl(Ldone_true);
5595 // Note: We could jump to the template if equal.
5596
5597 assert(VM_Version::has_ExecuteExtensions(), "unsupported hardware");
5598 z_exrl(odd_reg, CLC_template);
5599 z_bre(Ldone_true);
5600 // fall through
5601
5602 bind(Ldone_false);
5603 clear_reg(result);
5604 z_bru(Ldone);
5605
5606 bind(CLC_template);
5607 z_clc(0, 0, str1_reg, 0, str2_reg);
5608 }
5609
5610 // Use clcle instruction.
5611 {
5612 bind(Lclcle);
5613 add2reg(even_reg, base_offset, ary2); // string addr (right operand)
5614 add2reg(Z_R0, base_offset, ary1); // string addr (left operand)
5615
5616 z_lgr(Z_R1, odd_reg); // string len in bytes (left operand)
5617 if (is_byte) {
5618 compare_long_ext(Z_R0, even_reg, 0);
5619 } else {
5620 compare_long_uni(Z_R0, even_reg, 0);
5621 }
5622 z_lghi(result, 0); // Preserve flags.
5623 z_brne(Ldone);
5624 }
5625 }
5626 // fall through
5627
5628 bind(Ldone_true);
5629 z_lghi(result, 1); // All characters are equal.
5630 bind(Ldone);
5631
5632 BLOCK_COMMENT("} array_equals");
5633
5634 return offset() - block_start;
5635 }
5636
5637 // kill: haycnt, needlecnt, odd_reg, even_reg; early clobber: result
5638 unsigned int MacroAssembler::string_indexof(Register result, Register haystack, Register haycnt,
5639 Register needle, Register needlecnt, int needlecntval,
5640 Register odd_reg, Register even_reg, int ae) {
5641 int block_start = offset();
5642
5643 // Ensure 0<needlecnt<=haycnt in ideal graph as prerequisite!
5644 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5645 const int h_csize = (ae == StrIntrinsicNode::LL) ? 1 : 2;
5646 const int n_csize = (ae == StrIntrinsicNode::UU) ? 2 : 1;
5647 Label L_needle1, L_Found, L_NotFound;
5648
5649 BLOCK_COMMENT("string_indexof {");
5650
5651 if (needle == haystack) {
5652 z_lhi(result, 0);
5653 } else {
5654
5655 // Load first character of needle (R0 used by search_string instructions).
5656 if (n_csize == 2) { z_llgh(Z_R0, Address(needle)); } else { z_llgc(Z_R0, Address(needle)); }
5657
5658 // Compute last haystack addr to use if no match gets found.
5659 if (needlecnt != noreg) { // variable needlecnt
5660 z_ahi(needlecnt, -1); // Remaining characters after first one.
5661 z_sr(haycnt, needlecnt); // Compute index succeeding last element to compare.
5662 if (n_csize == 2) { z_sll(needlecnt, 1); } // In bytes.
5663 } else { // constant needlecnt
5664 assert((needlecntval & 0x7fff) == needlecntval, "must be positive simm16 immediate");
5665 // Compute index succeeding last element to compare.
5666 if (needlecntval != 1) { z_ahi(haycnt, 1 - needlecntval); }
5667 }
5668
5669 z_llgfr(haycnt, haycnt); // Clear high half.
5670 z_lgr(result, haystack); // Final result will be computed from needle start pointer.
5671 if (h_csize == 2) { z_sll(haycnt, 1); } // Scale to number of bytes.
5672 z_agr(haycnt, haystack); // Point to address succeeding last element (haystack+scale*(haycnt-needlecnt+1)).
5673
5674 if (h_csize != n_csize) {
5675 assert(ae == StrIntrinsicNode::UL, "Invalid encoding");
5676
5677 if (needlecnt != noreg || needlecntval != 1) {
5678 if (needlecnt != noreg) {
5679 compare32_and_branch(needlecnt, (intptr_t)0, Assembler::bcondEqual, L_needle1);
5680 }
5681
5682 // Main Loop: UL version (now we have at least 2 characters).
5683 Label L_OuterLoop, L_InnerLoop, L_Skip;
5684 bind(L_OuterLoop); // Search for 1st 2 characters.
5685 z_lgr(Z_R1, haycnt);
5686 MacroAssembler::search_string_uni(Z_R1, result);
5687 z_brc(Assembler::bcondNotFound, L_NotFound);
5688 z_lgr(result, Z_R1);
5689
5690 z_lghi(Z_R1, n_csize);
5691 z_lghi(even_reg, h_csize);
5692 bind(L_InnerLoop);
5693 z_llgc(odd_reg, Address(needle, Z_R1));
5694 z_ch(odd_reg, Address(result, even_reg));
5695 z_brne(L_Skip);
5696 if (needlecnt != noreg) { z_cr(Z_R1, needlecnt); } else { z_chi(Z_R1, needlecntval - 1); }
5697 z_brnl(L_Found);
5698 z_aghi(Z_R1, n_csize);
5699 z_aghi(even_reg, h_csize);
5700 z_bru(L_InnerLoop);
5701
5702 bind(L_Skip);
5703 z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5704 z_bru(L_OuterLoop);
5705 }
5706
5707 } else {
5708 const intptr_t needle_bytes = (n_csize == 2) ? ((needlecntval - 1) << 1) : (needlecntval - 1);
5709 Label L_clcle;
5710
5711 if (needlecnt != noreg || (needlecntval != 1 && needle_bytes <= 256)) {
5712 if (needlecnt != noreg) {
5713 compare32_and_branch(needlecnt, 256, Assembler::bcondHigh, L_clcle);
5714 z_ahi(needlecnt, -1); // remaining bytes -1 (for CLC)
5715 z_brl(L_needle1);
5716 }
5717
5718 // Main Loop: clc version (now we have at least 2 characters).
5719 Label L_OuterLoop, CLC_template;
5720 bind(L_OuterLoop); // Search for 1st 2 characters.
5721 z_lgr(Z_R1, haycnt);
5722 if (h_csize == 1) {
5723 MacroAssembler::search_string(Z_R1, result);
5724 } else {
5725 MacroAssembler::search_string_uni(Z_R1, result);
5726 }
5727 z_brc(Assembler::bcondNotFound, L_NotFound);
5728 z_lgr(result, Z_R1);
5729
5730 if (needlecnt != noreg) {
5731 assert(VM_Version::has_ExecuteExtensions(), "unsupported hardware");
5732 z_exrl(needlecnt, CLC_template);
5733 } else {
5734 z_clc(h_csize, needle_bytes -1, Z_R1, n_csize, needle);
5735 }
5736 z_bre(L_Found);
5737 z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5738 z_bru(L_OuterLoop);
5739
5740 if (needlecnt != noreg) {
5741 bind(CLC_template);
5742 z_clc(h_csize, 0, Z_R1, n_csize, needle);
5743 }
5744 }
5745
5746 if (needlecnt != noreg || needle_bytes > 256) {
5747 bind(L_clcle);
5748
5749 // Main Loop: clcle version (now we have at least 256 bytes).
5750 Label L_OuterLoop, CLC_template;
5751 bind(L_OuterLoop); // Search for 1st 2 characters.
5752 z_lgr(Z_R1, haycnt);
5753 if (h_csize == 1) {
5754 MacroAssembler::search_string(Z_R1, result);
5755 } else {
5756 MacroAssembler::search_string_uni(Z_R1, result);
5757 }
5758 z_brc(Assembler::bcondNotFound, L_NotFound);
5759
5760 add2reg(Z_R0, n_csize, needle);
5761 add2reg(even_reg, h_csize, Z_R1);
5762 z_lgr(result, Z_R1);
5763 if (needlecnt != noreg) {
5764 z_llgfr(Z_R1, needlecnt); // needle len in bytes (left operand)
5765 z_llgfr(odd_reg, needlecnt);
5766 } else {
5767 load_const_optimized(Z_R1, needle_bytes);
5768 if (Immediate::is_simm16(needle_bytes)) { z_lghi(odd_reg, needle_bytes); } else { z_lgr(odd_reg, Z_R1); }
5769 }
5770 if (h_csize == 1) {
5771 compare_long_ext(Z_R0, even_reg, 0);
5772 } else {
5773 compare_long_uni(Z_R0, even_reg, 0);
5774 }
5775 z_bre(L_Found);
5776
5777 if (n_csize == 2) { z_llgh(Z_R0, Address(needle)); } else { z_llgc(Z_R0, Address(needle)); } // Reload.
5778 z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5779 z_bru(L_OuterLoop);
5780 }
5781 }
5782
5783 if (needlecnt != noreg || needlecntval == 1) {
5784 bind(L_needle1);
5785
5786 // Single needle character version.
5787 if (h_csize == 1) {
5788 MacroAssembler::search_string(haycnt, result);
5789 } else {
5790 MacroAssembler::search_string_uni(haycnt, result);
5791 }
5792 z_lgr(result, haycnt);
5793 z_brc(Assembler::bcondFound, L_Found);
5794 }
5795
5796 bind(L_NotFound);
5797 add2reg(result, -1, haystack); // Return -1.
5798
5799 bind(L_Found); // Return index (or -1 in fallthrough case).
5800 z_sgr(result, haystack);
5801 if (h_csize == 2) { z_srag(result, result, exact_log2(sizeof(jchar))); }
5802 }
5803 BLOCK_COMMENT("} string_indexof");
5804
5805 return offset() - block_start;
5806 }
5807
5808 // early clobber: result
5809 unsigned int MacroAssembler::string_indexof_char(Register result, Register haystack, Register haycnt,
5810 Register needle, jchar needleChar, Register odd_reg, Register even_reg, bool is_byte) {
5811 int block_start = offset();
5812
5813 BLOCK_COMMENT("string_indexof_char {");
5814
5815 if (needle == haystack) {
5816 z_lhi(result, 0);
5817 } else {
5818
5819 Label Ldone;
5820
5821 z_llgfr(odd_reg, haycnt); // Preset loop ctr/searchrange end.
5822 if (needle == noreg) {
5823 load_const_optimized(Z_R0, (unsigned long)needleChar);
5824 } else {
5825 if (is_byte) {
5826 z_llgcr(Z_R0, needle); // First (and only) needle char.
5827 } else {
5828 z_llghr(Z_R0, needle); // First (and only) needle char.
5829 }
5830 }
5831
5832 if (!is_byte) {
5833 z_agr(odd_reg, odd_reg); // Calc #bytes to be processed with SRSTU.
5834 }
5835
5836 z_lgr(even_reg, haystack); // haystack addr
5837 z_agr(odd_reg, haystack); // First char after range end.
5838 z_lghi(result, -1);
5839
5840 if (is_byte) {
5841 MacroAssembler::search_string(odd_reg, even_reg);
5842 } else {
5843 MacroAssembler::search_string_uni(odd_reg, even_reg);
5844 }
5845 z_brc(Assembler::bcondNotFound, Ldone);
5846 if (is_byte) {
5847 if (VM_Version::has_DistinctOpnds()) {
5848 z_sgrk(result, odd_reg, haystack);
5849 } else {
5850 z_sgr(odd_reg, haystack);
5851 z_lgr(result, odd_reg);
5852 }
5853 } else {
5854 z_slgr(odd_reg, haystack);
5855 z_srlg(result, odd_reg, exact_log2(sizeof(jchar)));
5856 }
5857
5858 bind(Ldone);
5859 }
5860 BLOCK_COMMENT("} string_indexof_char");
5861
5862 return offset() - block_start;
5863 }
5864
5865
5866 //-------------------------------------------------
5867 // Constants (scalar and oop) in constant pool
5868 //-------------------------------------------------
5869
5870 // Add a non-relocated constant to the CP.
5871 int MacroAssembler::store_const_in_toc(AddressLiteral& val) {
5872 long value = val.value();
5873 address tocPos = long_constant(value);
5874
5875 if (tocPos != NULL) {
5876 int tocOffset = (int)(tocPos - code()->consts()->start());
5877 return tocOffset;
5878 }
5879 // Address_constant returned NULL, so no constant entry has been created.
5880 // In that case, we return a "fatal" offset, just in case that subsequently
5881 // generated access code is executed.
5882 return -1;
5883 }
5884
5885 // Returns the TOC offset where the address is stored.
5886 // Add a relocated constant to the CP.
5887 int MacroAssembler::store_oop_in_toc(AddressLiteral& oop) {
5888 // Use RelocationHolder::none for the constant pool entry.
5889 // Otherwise we will end up with a failing NativeCall::verify(x),
5890 // where x is the address of the constant pool entry.
5891 address tocPos = address_constant((address)oop.value(), RelocationHolder::none);
5892
5893 if (tocPos != NULL) {
5894 int tocOffset = (int)(tocPos - code()->consts()->start());
5895 RelocationHolder rsp = oop.rspec();
5896 Relocation *rel = rsp.reloc();
5897
5898 // Store toc_offset in relocation, used by call_far_patchable.
5899 if ((relocInfo::relocType)rel->type() == relocInfo::runtime_call_w_cp_type) {
5900 ((runtime_call_w_cp_Relocation *)(rel))->set_constant_pool_offset(tocOffset);
5901 }
5902 // Relocate at the load's pc.
5903 relocate(rsp);
5904
5905 return tocOffset;
5906 }
5907 // Address_constant returned NULL, so no constant entry has been created
5908 // in that case, we return a "fatal" offset, just in case that subsequently
5909 // generated access code is executed.
5910 return -1;
5911 }
5912
5913 bool MacroAssembler::load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc) {
5914 int tocOffset = store_const_in_toc(a);
5915 if (tocOffset == -1) return false;
5916 address tocPos = tocOffset + code()->consts()->start();
5917 assert((address)code()->consts()->start() != NULL, "Please add CP address");
5918
5919 load_long_pcrelative(dst, tocPos);
5920 return true;
5921 }
5922
5923 bool MacroAssembler::load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc) {
5924 int tocOffset = store_oop_in_toc(a);
5925 if (tocOffset == -1) return false;
5926 address tocPos = tocOffset + code()->consts()->start();
5927 assert((address)code()->consts()->start() != NULL, "Please add CP address");
5928
5929 load_addr_pcrelative(dst, tocPos);
5930 return true;
5931 }
5932
5933 // If the instruction sequence at the given pc is a load_const_from_toc
5934 // sequence, return the value currently stored at the referenced position
5935 // in the TOC.
5936 intptr_t MacroAssembler::get_const_from_toc(address pc) {
5937
5938 assert(is_load_const_from_toc(pc), "must be load_const_from_pool");
5939
5940 long offset = get_load_const_from_toc_offset(pc);
5941 address dataLoc = NULL;
5942 if (is_load_const_from_toc_pcrelative(pc)) {
5943 dataLoc = pc + offset;
5944 } else {
5945 CodeBlob* cb = CodeCache::find_blob_unsafe(pc); // Else we get assertion if nmethod is zombie.
5946 assert(cb && cb->is_nmethod(), "sanity");
5947 nmethod* nm = (nmethod*)cb;
5948 dataLoc = nm->ctable_begin() + offset;
5949 }
5950 return *(intptr_t *)dataLoc;
5951 }
5952
5953 // If the instruction sequence at the given pc is a load_const_from_toc
5954 // sequence, copy the passed-in new_data value into the referenced
5955 // position in the TOC.
5956 void MacroAssembler::set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb) {
5957 assert(is_load_const_from_toc(pc), "must be load_const_from_pool");
5958
5959 long offset = MacroAssembler::get_load_const_from_toc_offset(pc);
5960 address dataLoc = NULL;
5961 if (is_load_const_from_toc_pcrelative(pc)) {
5962 dataLoc = pc+offset;
5963 } else {
5964 nmethod* nm = CodeCache::find_nmethod(pc);
5965 assert((cb == NULL) || (nm == (nmethod*)cb), "instruction address should be in CodeBlob");
5966 dataLoc = nm->ctable_begin() + offset;
5967 }
5968 if (*(unsigned long *)dataLoc != new_data) { // Prevent cache invalidation: update only if necessary.
5969 *(unsigned long *)dataLoc = new_data;
5970 }
5971 }
5972
5973 // Dynamic TOC. Getter must only be called if "a" is a load_const_from_toc
5974 // site. Verify by calling is_load_const_from_toc() before!!
5975 // Offset is +/- 2**32 -> use long.
5976 long MacroAssembler::get_load_const_from_toc_offset(address a) {
5977 assert(is_load_const_from_toc_pcrelative(a), "expected pc relative load");
5978 // expected code sequence:
5979 // z_lgrl(t, simm32); len = 6
5980 unsigned long inst;
5981 unsigned int len = get_instruction(a, &inst);
5982 return get_pcrel_offset(inst);
5983 }
5984
5985 //**********************************************************************************
5986 // inspection of generated instruction sequences for a particular pattern
5987 //**********************************************************************************
5988
5989 bool MacroAssembler::is_load_const_from_toc_pcrelative(address a) {
5990 #ifdef ASSERT
5991 unsigned long inst;
5992 unsigned int len = get_instruction(a+2, &inst);
5993 if ((len == 6) && is_load_pcrelative_long(a) && is_call_pcrelative_long(inst)) {
5994 const int range = 128;
5995 Assembler::dump_code_range(tty, a, range, "instr(a) == z_lgrl && instr(a+2) == z_brasl");
5996 VM_Version::z_SIGSEGV();
5997 }
5998 #endif
5999 // expected code sequence:
6000 // z_lgrl(t, relAddr32); len = 6
6001 //TODO: verify accessed data is in CP, if possible.
6002 return is_load_pcrelative_long(a); // TODO: might be too general. Currently, only lgrl is used.
6003 }
6004
6005 bool MacroAssembler::is_load_const_from_toc_call(address a) {
6006 return is_load_const_from_toc(a) && is_call_byregister(a + load_const_from_toc_size());
6007 }
6008
6009 bool MacroAssembler::is_load_const_call(address a) {
6010 return is_load_const(a) && is_call_byregister(a + load_const_size());
6011 }
6012
6013 //-------------------------------------------------
6014 // Emitters for some really CICS instructions
6015 //-------------------------------------------------
6016
6017 void MacroAssembler::move_long_ext(Register dst, Register src, unsigned int pad) {
6018 assert(dst->encoding()%2==0, "must be an even/odd register pair");
6019 assert(src->encoding()%2==0, "must be an even/odd register pair");
6020 assert(pad<256, "must be a padding BYTE");
6021
6022 Label retry;
6023 bind(retry);
6024 Assembler::z_mvcle(dst, src, pad);
6025 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6026 }
6027
6028 void MacroAssembler::compare_long_ext(Register left, Register right, unsigned int pad) {
6029 assert(left->encoding() % 2 == 0, "must be an even/odd register pair");
6030 assert(right->encoding() % 2 == 0, "must be an even/odd register pair");
6031 assert(pad<256, "must be a padding BYTE");
6032
6033 Label retry;
6034 bind(retry);
6035 Assembler::z_clcle(left, right, pad, Z_R0);
6036 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6037 }
6038
6039 void MacroAssembler::compare_long_uni(Register left, Register right, unsigned int pad) {
6040 assert(left->encoding() % 2 == 0, "must be an even/odd register pair");
6041 assert(right->encoding() % 2 == 0, "must be an even/odd register pair");
6042 assert(pad<=0xfff, "must be a padding HALFWORD");
6043 assert(VM_Version::has_ETF2(), "instruction must be available");
6044
6045 Label retry;
6046 bind(retry);
6047 Assembler::z_clclu(left, right, pad, Z_R0);
6048 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6049 }
6050
6051 void MacroAssembler::search_string(Register end, Register start) {
6052 assert(end->encoding() != 0, "end address must not be in R0");
6053 assert(start->encoding() != 0, "start address must not be in R0");
6054
6055 Label retry;
6056 bind(retry);
6057 Assembler::z_srst(end, start);
6058 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6059 }
6060
6061 void MacroAssembler::search_string_uni(Register end, Register start) {
6062 assert(end->encoding() != 0, "end address must not be in R0");
6063 assert(start->encoding() != 0, "start address must not be in R0");
6064 assert(VM_Version::has_ETF3(), "instruction must be available");
6065
6066 Label retry;
6067 bind(retry);
6068 Assembler::z_srstu(end, start);
6069 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6070 }
6071
6072 void MacroAssembler::kmac(Register srcBuff) {
6073 assert(srcBuff->encoding() != 0, "src buffer address can't be in Z_R0");
6074 assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
6075
6076 Label retry;
6077 bind(retry);
6078 Assembler::z_kmac(Z_R0, srcBuff);
6079 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6080 }
6081
6082 void MacroAssembler::kimd(Register srcBuff) {
6083 assert(srcBuff->encoding() != 0, "src buffer address can't be in Z_R0");
6084 assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
6085
6086 Label retry;
6087 bind(retry);
6088 Assembler::z_kimd(Z_R0, srcBuff);
6089 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6090 }
6091
6092 void MacroAssembler::klmd(Register srcBuff) {
6093 assert(srcBuff->encoding() != 0, "src buffer address can't be in Z_R0");
6094 assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
6095
6096 Label retry;
6097 bind(retry);
6098 Assembler::z_klmd(Z_R0, srcBuff);
6099 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6100 }
6101
6102 void MacroAssembler::km(Register dstBuff, Register srcBuff) {
6103 // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
6104 // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
6105 assert(srcBuff->encoding() != 0, "src buffer address can't be in Z_R0");
6106 assert(dstBuff->encoding() % 2 == 0, "dst buffer addr must be an even register");
6107 assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
6108
6109 Label retry;
6110 bind(retry);
6111 Assembler::z_km(dstBuff, srcBuff);
6112 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6113 }
6114
6115 void MacroAssembler::kmc(Register dstBuff, Register srcBuff) {
6116 // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
6117 // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
6118 assert(srcBuff->encoding() != 0, "src buffer address can't be in Z_R0");
6119 assert(dstBuff->encoding() % 2 == 0, "dst buffer addr must be an even register");
6120 assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
6121
6122 Label retry;
6123 bind(retry);
6124 Assembler::z_kmc(dstBuff, srcBuff);
6125 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6126 }
6127
6128 void MacroAssembler::cksm(Register crcBuff, Register srcBuff) {
6129 assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
6130
6131 Label retry;
6132 bind(retry);
6133 Assembler::z_cksm(crcBuff, srcBuff);
6134 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6135 }
6136
6137 void MacroAssembler::translate_oo(Register r1, Register r2, uint m3) {
6138 assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
6139 assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
6140
6141 Label retry;
6142 bind(retry);
6143 Assembler::z_troo(r1, r2, m3);
6144 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6145 }
6146
6147 void MacroAssembler::translate_ot(Register r1, Register r2, uint m3) {
6148 assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
6149 assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
6150
6151 Label retry;
6152 bind(retry);
6153 Assembler::z_trot(r1, r2, m3);
6154 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6155 }
6156
6157 void MacroAssembler::translate_to(Register r1, Register r2, uint m3) {
6158 assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
6159 assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
6160
6161 Label retry;
6162 bind(retry);
6163 Assembler::z_trto(r1, r2, m3);
6164 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6165 }
6166
6167 void MacroAssembler::translate_tt(Register r1, Register r2, uint m3) {
6168 assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
6169 assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
6170
6171 Label retry;
6172 bind(retry);
6173 Assembler::z_trtt(r1, r2, m3);
6174 Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
6175 }
6176
6177
6178 void MacroAssembler::generate_type_profiling(const Register Rdata,
6179 const Register Rreceiver_klass,
6180 const Register Rwanted_receiver_klass,
6181 const Register Rmatching_row,
6182 bool is_virtual_call) {
6183 const int row_size = in_bytes(ReceiverTypeData::receiver_offset(1)) -
6184 in_bytes(ReceiverTypeData::receiver_offset(0));
6185 const int num_rows = ReceiverTypeData::row_limit();
6186 NearLabel found_free_row;
6187 NearLabel do_increment;
6188 NearLabel found_no_slot;
6189
6190 BLOCK_COMMENT("type profiling {");
6191
6192 // search for:
6193 // a) The type given in Rwanted_receiver_klass.
6194 // b) The *first* empty row.
6195
6196 // First search for a) only, just running over b) with no regard.
6197 // This is possible because
6198 // wanted_receiver_class == receiver_class && wanted_receiver_class == 0
6199 // is never true (receiver_class can't be zero).
6200 for (int row_num = 0; row_num < num_rows; row_num++) {
6201 // Row_offset should be a well-behaved positive number. The generated code relies
6202 // on that wrt constant code size. Add2reg can handle all row_offset values, but
6203 // will have to vary generated code size.
6204 int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num));
6205 assert(Displacement::is_shortDisp(row_offset), "Limitation of generated code");
6206
6207 // Is Rwanted_receiver_klass in this row?
6208 if (VM_Version::has_CompareBranch()) {
6209 z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata);
6210 // Rmatching_row = Rdata + row_offset;
6211 add2reg(Rmatching_row, row_offset, Rdata);
6212 // if (*row_recv == (intptr_t) receiver_klass) goto fill_existing_slot;
6213 compare64_and_branch(Rwanted_receiver_klass, Rreceiver_klass, Assembler::bcondEqual, do_increment);
6214 } else {
6215 add2reg(Rmatching_row, row_offset, Rdata);
6216 z_cg(Rreceiver_klass, row_offset, Z_R0, Rdata);
6217 z_bre(do_increment);
6218 }
6219 }
6220
6221 // Now that we did not find a match, let's search for b).
6222
6223 // We could save the first calculation of Rmatching_row if we woud search for a) in reverse order.
6224 // We would then end up here with Rmatching_row containing the value for row_num == 0.
6225 // We would not see much benefit, if any at all, because the CPU can schedule
6226 // two instructions together with a branch anyway.
6227 for (int row_num = 0; row_num < num_rows; row_num++) {
6228 int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num));
6229
6230 // Has this row a zero receiver_klass, i.e. is it empty?
6231 if (VM_Version::has_CompareBranch()) {
6232 z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata);
6233 // Rmatching_row = Rdata + row_offset
6234 add2reg(Rmatching_row, row_offset, Rdata);
6235 // if (*row_recv == (intptr_t) 0) goto found_free_row
6236 compare64_and_branch(Rwanted_receiver_klass, (intptr_t)0, Assembler::bcondEqual, found_free_row);
6237 } else {
6238 add2reg(Rmatching_row, row_offset, Rdata);
6239 load_and_test_long(Rwanted_receiver_klass, Address(Rdata, row_offset));
6240 z_bre(found_free_row); // zero -> Found a free row.
6241 }
6242 }
6243
6244 // No match, no empty row found.
6245 // Increment total counter to indicate polymorphic case.
6246 if (is_virtual_call) {
6247 add2mem_64(Address(Rdata, CounterData::count_offset()), 1, Rmatching_row);
6248 }
6249 z_bru(found_no_slot);
6250
6251 // Here we found an empty row, but we have not found Rwanted_receiver_klass.
6252 // Rmatching_row holds the address to the first empty row.
6253 bind(found_free_row);
6254 // Store receiver_klass into empty slot.
6255 z_stg(Rreceiver_klass, 0, Z_R0, Rmatching_row);
6256
6257 // Increment the counter of Rmatching_row.
6258 bind(do_increment);
6259 ByteSize counter_offset = ReceiverTypeData::receiver_count_offset(0) - ReceiverTypeData::receiver_offset(0);
6260 add2mem_64(Address(Rmatching_row, counter_offset), 1, Rdata);
6261
6262 bind(found_no_slot);
6263
6264 BLOCK_COMMENT("} type profiling");
6265 }
6266
6267 //---------------------------------------
6268 // Helpers for Intrinsic Emitters
6269 //---------------------------------------
6270
6271 /**
6272 * uint32_t crc;
6273 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6274 */
6275 void MacroAssembler::fold_byte_crc32(Register crc, Register val, Register table, Register tmp) {
6276 assert_different_registers(crc, table, tmp);
6277 assert_different_registers(val, table);
6278 if (crc == val) { // Must rotate first to use the unmodified value.
6279 rotate_then_insert(tmp, val, 56-2, 63-2, 2, true); // Insert byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
6280 z_srl(crc, 8); // Unsigned shift, clear leftmost 8 bits.
6281 } else {
6282 z_srl(crc, 8); // Unsigned shift, clear leftmost 8 bits.
6283 rotate_then_insert(tmp, val, 56-2, 63-2, 2, true); // Insert byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
6284 }
6285 z_x(crc, Address(table, tmp, 0));
6286 }
6287
6288 /**
6289 * uint32_t crc;
6290 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6291 */
6292 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
6293 fold_byte_crc32(crc, crc, table, tmp);
6294 }
6295
6296 /**
6297 * Emits code to update CRC-32 with a byte value according to constants in table.
6298 *
6299 * @param [in,out]crc Register containing the crc.
6300 * @param [in]val Register containing the byte to fold into the CRC.
6301 * @param [in]table Register containing the table of crc constants.
6302 *
6303 * uint32_t crc;
6304 * val = crc_table[(val ^ crc) & 0xFF];
6305 * crc = val ^ (crc >> 8);
6306 */
6307 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6308 z_xr(val, crc);
6309 fold_byte_crc32(crc, val, table, val);
6310 }
6311
6312
6313 /**
6314 * @param crc register containing existing CRC (32-bit)
6315 * @param buf register pointing to input byte buffer (byte*)
6316 * @param len register containing number of bytes
6317 * @param table register pointing to CRC table
6318 */
6319 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, Register data) {
6320 assert_different_registers(crc, buf, len, table, data);
6321
6322 Label L_mainLoop, L_done;
6323 const int mainLoop_stepping = 1;
6324
6325 // Process all bytes in a single-byte loop.
6326 z_ltr(len, len);
6327 z_brnh(L_done);
6328
6329 bind(L_mainLoop);
6330 z_llgc(data, Address(buf, (intptr_t)0));// Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6331 add2reg(buf, mainLoop_stepping); // Advance buffer position.
6332 update_byte_crc32(crc, data, table);
6333 z_brct(len, L_mainLoop); // Iterate.
6334
6335 bind(L_done);
6336 }
6337
6338 /**
6339 * Emits code to update CRC-32 with a 4-byte value according to constants in table.
6340 * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c.
6341 *
6342 */
6343 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
6344 Register t0, Register t1, Register t2, Register t3) {
6345 // This is what we implement (the DOBIG4 part):
6346 //
6347 // #define DOBIG4 c ^= *++buf4; \
6348 // c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
6349 // crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
6350 // #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
6351 // Pre-calculate (constant) column offsets, use columns 4..7 for big-endian.
6352 const int ix0 = 4*(4*CRC32_COLUMN_SIZE);
6353 const int ix1 = 5*(4*CRC32_COLUMN_SIZE);
6354 const int ix2 = 6*(4*CRC32_COLUMN_SIZE);
6355 const int ix3 = 7*(4*CRC32_COLUMN_SIZE);
6356
6357 // XOR crc with next four bytes of buffer.
6358 lgr_if_needed(t0, crc);
6359 z_x(t0, Address(buf, bufDisp));
6360 if (bufInc != 0) {
6361 add2reg(buf, bufInc);
6362 }
6363
6364 // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
6365 rotate_then_insert(t3, t0, 56-2, 63-2, 2, true); // ((c >> 0) & 0xff) << 2
6366 rotate_then_insert(t2, t0, 56-2, 63-2, 2-8, true); // ((c >> 8) & 0xff) << 2
6367 rotate_then_insert(t1, t0, 56-2, 63-2, 2-16, true); // ((c >> 16) & 0xff) << 2
6368 rotate_then_insert(t0, t0, 56-2, 63-2, 2-24, true); // ((c >> 24) & 0xff) << 2
6369
6370 // XOR indexed table values to calculate updated crc.
6371 z_ly(t2, Address(table, t2, (intptr_t)ix1));
6372 z_ly(t0, Address(table, t0, (intptr_t)ix3));
6373 z_xy(t2, Address(table, t3, (intptr_t)ix0));
6374 z_xy(t0, Address(table, t1, (intptr_t)ix2));
6375 z_xr(t0, t2); // Now t0 contains the updated CRC value.
6376 lgr_if_needed(crc, t0);
6377 }
6378
6379 /**
6380 * @param crc register containing existing CRC (32-bit)
6381 * @param buf register pointing to input byte buffer (byte*)
6382 * @param len register containing number of bytes
6383 * @param table register pointing to CRC table
6384 *
6385 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6386 */
6387 void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
6388 Register t0, Register t1, Register t2, Register t3,
6389 bool invertCRC) {
6390 assert_different_registers(crc, buf, len, table);
6391
6392 Label L_mainLoop, L_tail;
6393 Register data = t0;
6394 Register ctr = Z_R0;
6395 const int mainLoop_stepping = 8;
6396 const int tailLoop_stepping = 1;
6397 const int log_stepping = exact_log2(mainLoop_stepping);
6398
6399 // Don't test for len <= 0 here. This pathological case should not occur anyway.
6400 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6401 // The situation itself is detected and handled correctly by the conditional branches
6402 // following aghi(len, -stepping) and aghi(len, +stepping).
6403
6404 if (invertCRC) {
6405 not_(crc, noreg, false); // 1s complement of crc
6406 }
6407
6408 #if 0
6409 {
6410 // Pre-mainLoop alignment did not show any positive effect on performance.
6411 // We leave the code in for reference. Maybe the vector instructions in z13 depend on alignment.
6412
6413 z_cghi(len, mainLoop_stepping); // Alignment is useless for short data streams.
6414 z_brnh(L_tail);
6415
6416 // Align buf to word (4-byte) boundary.
6417 z_lcr(ctr, buf);
6418 rotate_then_insert(ctr, ctr, 62, 63, 0, true); // TODO: should set cc
6419 z_sgfr(len, ctr); // Remaining len after alignment.
6420
6421 update_byteLoop_crc32(crc, buf, ctr, table, data);
6422 }
6423 #endif
6424
6425 // Check for short (<mainLoop_stepping bytes) buffer.
6426 z_srag(ctr, len, log_stepping);
6427 z_brnh(L_tail);
6428
6429 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6430 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6431
6432 BIND(L_mainLoop);
6433 update_1word_crc32(crc, buf, table, 0, 0, crc, t1, t2, t3);
6434 update_1word_crc32(crc, buf, table, 4, mainLoop_stepping, crc, t1, t2, t3);
6435 z_brct(ctr, L_mainLoop); // Iterate.
6436
6437 z_lrvr(crc, crc); // Revert byte order back to original.
6438
6439 // Process last few (<8) bytes of buffer.
6440 BIND(L_tail);
6441 update_byteLoop_crc32(crc, buf, len, table, data);
6442
6443 if (invertCRC) {
6444 not_(crc, noreg, false); // 1s complement of crc
6445 }
6446 }
6447
6448 /**
6449 * @param crc register containing existing CRC (32-bit)
6450 * @param buf register pointing to input byte buffer (byte*)
6451 * @param len register containing number of bytes
6452 * @param table register pointing to CRC table
6453 *
6454 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6455 */
6456 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
6457 Register t0, Register t1, Register t2, Register t3,
6458 bool invertCRC) {
6459 assert_different_registers(crc, buf, len, table);
6460
6461 Label L_mainLoop, L_tail;
6462 Register data = t0;
6463 Register ctr = Z_R0;
6464 const int mainLoop_stepping = 4;
6465 const int log_stepping = exact_log2(mainLoop_stepping);
6466
6467 // Don't test for len <= 0 here. This pathological case should not occur anyway.
6468 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6469 // The situation itself is detected and handled correctly by the conditional branches
6470 // following aghi(len, -stepping) and aghi(len, +stepping).
6471
6472 if (invertCRC) {
6473 not_(crc, noreg, false); // 1s complement of crc
6474 }
6475
6476 // Check for short (<4 bytes) buffer.
6477 z_srag(ctr, len, log_stepping);
6478 z_brnh(L_tail);
6479
6480 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6481 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6482
6483 BIND(L_mainLoop);
6484 update_1word_crc32(crc, buf, table, 0, mainLoop_stepping, crc, t1, t2, t3);
6485 z_brct(ctr, L_mainLoop); // Iterate.
6486
6487 z_lrvr(crc, crc); // Revert byte order back to original.
6488
6489 // Process last few (<8) bytes of buffer.
6490 BIND(L_tail);
6491 update_byteLoop_crc32(crc, buf, len, table, data);
6492
6493 if (invertCRC) {
6494 not_(crc, noreg, false); // 1s complement of crc
6495 }
6496 }
6497
6498 /**
6499 * @param crc register containing existing CRC (32-bit)
6500 * @param buf register pointing to input byte buffer (byte*)
6501 * @param len register containing number of bytes
6502 * @param table register pointing to CRC table
6503 */
6504 void MacroAssembler::kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
6505 Register t0, Register t1, Register t2, Register t3,
6506 bool invertCRC) {
6507 assert_different_registers(crc, buf, len, table);
6508 Register data = t0;
6509
6510 if (invertCRC) {
6511 not_(crc, noreg, false); // 1s complement of crc
6512 }
6513
6514 update_byteLoop_crc32(crc, buf, len, table, data);
6515
6516 if (invertCRC) {
6517 not_(crc, noreg, false); // 1s complement of crc
6518 }
6519 }
6520
6521 void MacroAssembler::kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
6522 bool invertCRC) {
6523 assert_different_registers(crc, buf, len, table, tmp);
6524
6525 if (invertCRC) {
6526 not_(crc, noreg, false); // 1s complement of crc
6527 }
6528
6529 z_llgc(tmp, Address(buf, (intptr_t)0)); // Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6530 update_byte_crc32(crc, tmp, table);
6531
6532 if (invertCRC) {
6533 not_(crc, noreg, false); // 1s complement of crc
6534 }
6535 }
6536
6537 void MacroAssembler::kernel_crc32_singleByteReg(Register crc, Register val, Register table,
6538 bool invertCRC) {
6539 assert_different_registers(crc, val, table);
6540
6541 if (invertCRC) {
6542 not_(crc, noreg, false); // 1s complement of crc
6543 }
6544
6545 update_byte_crc32(crc, val, table);
6546
6547 if (invertCRC) {
6548 not_(crc, noreg, false); // 1s complement of crc
6549 }
6550 }
6551
6552 //
6553 // Code for BigInteger::multiplyToLen() intrinsic.
6554 //
6555
6556 // dest_lo += src1 + src2
6557 // dest_hi += carry1 + carry2
6558 // Z_R7 is destroyed !
6559 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo,
6560 Register src1, Register src2) {
6561 clear_reg(Z_R7);
6562 z_algr(dest_lo, src1);
6563 z_alcgr(dest_hi, Z_R7);
6564 z_algr(dest_lo, src2);
6565 z_alcgr(dest_hi, Z_R7);
6566 }
6567
6568 // Multiply 64 bit by 64 bit first loop.
6569 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart,
6570 Register x_xstart,
6571 Register y, Register y_idx,
6572 Register z,
6573 Register carry,
6574 Register product,
6575 Register idx, Register kdx) {
6576 // jlong carry, x[], y[], z[];
6577 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx--, kdx--) {
6578 // huge_128 product = y[idx] * x[xstart] + carry;
6579 // z[kdx] = (jlong)product;
6580 // carry = (jlong)(product >>> 64);
6581 // }
6582 // z[xstart] = carry;
6583
6584 Label L_first_loop, L_first_loop_exit;
6585 Label L_one_x, L_one_y, L_multiply;
6586
6587 z_aghi(xstart, -1);
6588 z_brl(L_one_x); // Special case: length of x is 1.
6589
6590 // Load next two integers of x.
6591 z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6592 mem2reg_opt(x_xstart, Address(x, Z_R1_scratch, 0));
6593
6594
6595 bind(L_first_loop);
6596
6597 z_aghi(idx, -1);
6598 z_brl(L_first_loop_exit);
6599 z_aghi(idx, -1);
6600 z_brl(L_one_y);
6601
6602 // Load next two integers of y.
6603 z_sllg(Z_R1_scratch, idx, LogBytesPerInt);
6604 mem2reg_opt(y_idx, Address(y, Z_R1_scratch, 0));
6605
6606
6607 bind(L_multiply);
6608
6609 Register multiplicand = product->successor();
6610 Register product_low = multiplicand;
6611
6612 lgr_if_needed(multiplicand, x_xstart);
6613 z_mlgr(product, y_idx); // multiplicand * y_idx -> product::multiplicand
6614 clear_reg(Z_R7);
6615 z_algr(product_low, carry); // Add carry to result.
6616 z_alcgr(product, Z_R7); // Add carry of the last addition.
6617 add2reg(kdx, -2);
6618
6619 // Store result.
6620 z_sllg(Z_R7, kdx, LogBytesPerInt);
6621 reg2mem_opt(product_low, Address(z, Z_R7, 0));
6622 lgr_if_needed(carry, product);
6623 z_bru(L_first_loop);
6624
6625
6626 bind(L_one_y); // Load one 32 bit portion of y as (0,value).
6627
6628 clear_reg(y_idx);
6629 mem2reg_opt(y_idx, Address(y, (intptr_t) 0), false);
6630 z_bru(L_multiply);
6631
6632
6633 bind(L_one_x); // Load one 32 bit portion of x as (0,value).
6634
6635 clear_reg(x_xstart);
6636 mem2reg_opt(x_xstart, Address(x, (intptr_t) 0), false);
6637 z_bru(L_first_loop);
6638
6639 bind(L_first_loop_exit);
6640 }
6641
6642 // Multiply 64 bit by 64 bit and add 128 bit.
6643 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y,
6644 Register z,
6645 Register yz_idx, Register idx,
6646 Register carry, Register product,
6647 int offset) {
6648 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6649 // z[kdx] = (jlong)product;
6650
6651 Register multiplicand = product->successor();
6652 Register product_low = multiplicand;
6653
6654 z_sllg(Z_R7, idx, LogBytesPerInt);
6655 mem2reg_opt(yz_idx, Address(y, Z_R7, offset));
6656
6657 lgr_if_needed(multiplicand, x_xstart);
6658 z_mlgr(product, yz_idx); // multiplicand * yz_idx -> product::multiplicand
6659 mem2reg_opt(yz_idx, Address(z, Z_R7, offset));
6660
6661 add2_with_carry(product, product_low, carry, yz_idx);
6662
6663 z_sllg(Z_R7, idx, LogBytesPerInt);
6664 reg2mem_opt(product_low, Address(z, Z_R7, offset));
6665
6666 }
6667
6668 // Multiply 128 bit by 128 bit. Unrolled inner loop.
6669 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart,
6670 Register y, Register z,
6671 Register yz_idx, Register idx,
6672 Register jdx,
6673 Register carry, Register product,
6674 Register carry2) {
6675 // jlong carry, x[], y[], z[];
6676 // int kdx = ystart+1;
6677 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6678 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6679 // z[kdx+idx+1] = (jlong)product;
6680 // jlong carry2 = (jlong)(product >>> 64);
6681 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6682 // z[kdx+idx] = (jlong)product;
6683 // carry = (jlong)(product >>> 64);
6684 // }
6685 // idx += 2;
6686 // if (idx > 0) {
6687 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6688 // z[kdx+idx] = (jlong)product;
6689 // carry = (jlong)(product >>> 64);
6690 // }
6691
6692 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6693
6694 // scale the index
6695 lgr_if_needed(jdx, idx);
6696 and_imm(jdx, 0xfffffffffffffffcL);
6697 rshift(jdx, 2);
6698
6699
6700 bind(L_third_loop);
6701
6702 z_aghi(jdx, -1);
6703 z_brl(L_third_loop_exit);
6704 add2reg(idx, -4);
6705
6706 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6707 lgr_if_needed(carry2, product);
6708
6709 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6710 lgr_if_needed(carry, product);
6711 z_bru(L_third_loop);
6712
6713
6714 bind(L_third_loop_exit); // Handle any left-over operand parts.
6715
6716 and_imm(idx, 0x3);
6717 z_brz(L_post_third_loop_done);
6718
6719 Label L_check_1;
6720
6721 z_aghi(idx, -2);
6722 z_brl(L_check_1);
6723
6724 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6725 lgr_if_needed(carry, product);
6726
6727
6728 bind(L_check_1);
6729
6730 add2reg(idx, 0x2);
6731 and_imm(idx, 0x1);
6732 z_aghi(idx, -1);
6733 z_brl(L_post_third_loop_done);
6734
6735 Register multiplicand = product->successor();
6736 Register product_low = multiplicand;
6737
6738 z_sllg(Z_R7, idx, LogBytesPerInt);
6739 clear_reg(yz_idx);
6740 mem2reg_opt(yz_idx, Address(y, Z_R7, 0), false);
6741 lgr_if_needed(multiplicand, x_xstart);
6742 z_mlgr(product, yz_idx); // multiplicand * yz_idx -> product::multiplicand
6743 clear_reg(yz_idx);
6744 mem2reg_opt(yz_idx, Address(z, Z_R7, 0), false);
6745
6746 add2_with_carry(product, product_low, yz_idx, carry);
6747
6748 z_sllg(Z_R7, idx, LogBytesPerInt);
6749 reg2mem_opt(product_low, Address(z, Z_R7, 0), false);
6750 rshift(product_low, 32);
6751
6752 lshift(product, 32);
6753 z_ogr(product_low, product);
6754 lgr_if_needed(carry, product_low);
6755
6756 bind(L_post_third_loop_done);
6757 }
6758
6759 void MacroAssembler::multiply_to_len(Register x, Register xlen,
6760 Register y, Register ylen,
6761 Register z,
6762 Register tmp1, Register tmp2,
6763 Register tmp3, Register tmp4,
6764 Register tmp5) {
6765 ShortBranchVerifier sbv(this);
6766
6767 assert_different_registers(x, xlen, y, ylen, z,
6768 tmp1, tmp2, tmp3, tmp4, tmp5, Z_R1_scratch, Z_R7);
6769 assert_different_registers(x, xlen, y, ylen, z,
6770 tmp1, tmp2, tmp3, tmp4, tmp5, Z_R8);
6771
6772 z_stmg(Z_R7, Z_R13, _z_abi(gpr7), Z_SP);
6773
6774 // In openJdk, we store the argument as 32-bit value to slot.
6775 Address zlen(Z_SP, _z_abi(remaining_cargs)); // Int in long on big endian.
6776
6777 const Register idx = tmp1;
6778 const Register kdx = tmp2;
6779 const Register xstart = tmp3;
6780
6781 const Register y_idx = tmp4;
6782 const Register carry = tmp5;
6783 const Register product = Z_R0_scratch;
6784 const Register x_xstart = Z_R8;
6785
6786 // First Loop.
6787 //
6788 // final static long LONG_MASK = 0xffffffffL;
6789 // int xstart = xlen - 1;
6790 // int ystart = ylen - 1;
6791 // long carry = 0;
6792 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6793 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6794 // z[kdx] = (int)product;
6795 // carry = product >>> 32;
6796 // }
6797 // z[xstart] = (int)carry;
6798 //
6799
6800 lgr_if_needed(idx, ylen); // idx = ylen
6801 z_llgf(kdx, zlen); // C2 does not respect int to long conversion for stub calls, thus load zero-extended.
6802 clear_reg(carry); // carry = 0
6803
6804 Label L_done;
6805
6806 lgr_if_needed(xstart, xlen);
6807 z_aghi(xstart, -1);
6808 z_brl(L_done);
6809
6810 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6811
6812 NearLabel L_second_loop;
6813 compare64_and_branch(kdx, RegisterOrConstant((intptr_t) 0), bcondEqual, L_second_loop);
6814
6815 NearLabel L_carry;
6816 z_aghi(kdx, -1);
6817 z_brz(L_carry);
6818
6819 // Store lower 32 bits of carry.
6820 z_sllg(Z_R1_scratch, kdx, LogBytesPerInt);
6821 reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6822 rshift(carry, 32);
6823 z_aghi(kdx, -1);
6824
6825
6826 bind(L_carry);
6827
6828 // Store upper 32 bits of carry.
6829 z_sllg(Z_R1_scratch, kdx, LogBytesPerInt);
6830 reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6831
6832 // Second and third (nested) loops.
6833 //
6834 // for (int i = xstart-1; i >= 0; i--) { // Second loop
6835 // carry = 0;
6836 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6837 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6838 // (z[k] & LONG_MASK) + carry;
6839 // z[k] = (int)product;
6840 // carry = product >>> 32;
6841 // }
6842 // z[i] = (int)carry;
6843 // }
6844 //
6845 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6846
6847 const Register jdx = tmp1;
6848
6849 bind(L_second_loop);
6850
6851 clear_reg(carry); // carry = 0;
6852 lgr_if_needed(jdx, ylen); // j = ystart+1
6853
6854 z_aghi(xstart, -1); // i = xstart-1;
6855 z_brl(L_done);
6856
6857 // Use free slots in the current stackframe instead of push/pop.
6858 Address zsave(Z_SP, _z_abi(carg_1));
6859 reg2mem_opt(z, zsave);
6860
6861
6862 Label L_last_x;
6863
6864 z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6865 load_address(z, Address(z, Z_R1_scratch, 4)); // z = z + k - j
6866 z_aghi(xstart, -1); // i = xstart-1;
6867 z_brl(L_last_x);
6868
6869 z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6870 mem2reg_opt(x_xstart, Address(x, Z_R1_scratch, 0));
6871
6872
6873 Label L_third_loop_prologue;
6874
6875 bind(L_third_loop_prologue);
6876
6877 Address xsave(Z_SP, _z_abi(carg_2));
6878 Address xlensave(Z_SP, _z_abi(carg_3));
6879 Address ylensave(Z_SP, _z_abi(carg_4));
6880
6881 reg2mem_opt(x, xsave);
6882 reg2mem_opt(xstart, xlensave);
6883 reg2mem_opt(ylen, ylensave);
6884
6885
6886 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6887
6888 mem2reg_opt(z, zsave);
6889 mem2reg_opt(x, xsave);
6890 mem2reg_opt(xlen, xlensave); // This is the decrement of the loop counter!
6891 mem2reg_opt(ylen, ylensave);
6892
6893 add2reg(tmp3, 1, xlen);
6894 z_sllg(Z_R1_scratch, tmp3, LogBytesPerInt);
6895 reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6896 z_aghi(tmp3, -1);
6897 z_brl(L_done);
6898
6899 rshift(carry, 32);
6900 z_sllg(Z_R1_scratch, tmp3, LogBytesPerInt);
6901 reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6902 z_bru(L_second_loop);
6903
6904 // Next infrequent code is moved outside loops.
6905 bind(L_last_x);
6906
6907 clear_reg(x_xstart);
6908 mem2reg_opt(x_xstart, Address(x, (intptr_t) 0), false);
6909 z_bru(L_third_loop_prologue);
6910
6911 bind(L_done);
6912
6913 z_lmg(Z_R7, Z_R13, _z_abi(gpr7), Z_SP);
6914 }
6915
6916 #ifndef PRODUCT
6917 // Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false).
6918 void MacroAssembler::asm_assert(bool check_equal, const char *msg, int id) {
6919 Label ok;
6920 if (check_equal) {
6921 z_bre(ok);
6922 } else {
6923 z_brne(ok);
6924 }
6925 stop(msg, id);
6926 bind(ok);
6927 }
6928
6929 // Assert if CC indicates "low".
6930 void MacroAssembler::asm_assert_low(const char *msg, int id) {
6931 Label ok;
6932 z_brnl(ok);
6933 stop(msg, id);
6934 bind(ok);
6935 }
6936
6937 // Assert if CC indicates "high".
6938 void MacroAssembler::asm_assert_high(const char *msg, int id) {
6939 Label ok;
6940 z_brnh(ok);
6941 stop(msg, id);
6942 bind(ok);
6943 }
6944
6945 // Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false)
6946 // generate non-relocatable code.
6947 void MacroAssembler::asm_assert_static(bool check_equal, const char *msg, int id) {
6948 Label ok;
6949 if (check_equal) { z_bre(ok); }
6950 else { z_brne(ok); }
6951 stop_static(msg, id);
6952 bind(ok);
6953 }
6954
6955 void MacroAssembler::asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset,
6956 Register mem_base, const char* msg, int id) {
6957 switch (size) {
6958 case 4:
6959 load_and_test_int(Z_R0, Address(mem_base, mem_offset));
6960 break;
6961 case 8:
6962 load_and_test_long(Z_R0, Address(mem_base, mem_offset));
6963 break;
6964 default:
6965 ShouldNotReachHere();
6966 }
6967 if (allow_relocation) { asm_assert(check_equal, msg, id); }
6968 else { asm_assert_static(check_equal, msg, id); }
6969 }
6970
6971 // Check the condition
6972 // expected_size == FP - SP
6973 // after transformation:
6974 // expected_size - FP + SP == 0
6975 // Destroys Register expected_size if no tmp register is passed.
6976 void MacroAssembler::asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id) {
6977 if (tmp == noreg) {
6978 tmp = expected_size;
6979 } else {
6980 if (tmp != expected_size) {
6981 z_lgr(tmp, expected_size);
6982 }
6983 z_algr(tmp, Z_SP);
6984 z_slg(tmp, 0, Z_R0, Z_SP);
6985 asm_assert_eq(msg, id);
6986 }
6987 }
6988 #endif // !PRODUCT
6989
6990 void MacroAssembler::verify_thread() {
6991 if (VerifyThread) {
6992 unimplemented("", 117);
6993 }
6994 }
6995
6996 // Plausibility check for oops.
6997 void MacroAssembler::verify_oop(Register oop, const char* msg) {
6998 if (!VerifyOops) return;
6999
7000 BLOCK_COMMENT("verify_oop {");
7001 Register tmp = Z_R0;
7002 unsigned int nbytes_save = 5*BytesPerWord;
7003 address entry = StubRoutines::verify_oop_subroutine_entry_address();
7004
7005 save_return_pc();
7006 push_frame_abi160(nbytes_save);
7007 z_stmg(Z_R1, Z_R5, frame::z_abi_160_size, Z_SP);
7008
7009 z_lgr(Z_ARG2, oop);
7010 load_const(Z_ARG1, (address) msg);
7011 load_const(Z_R1, entry);
7012 z_lg(Z_R1, 0, Z_R1);
7013 call_c(Z_R1);
7014
7015 z_lmg(Z_R1, Z_R5, frame::z_abi_160_size, Z_SP);
7016 pop_frame();
7017 restore_return_pc();
7018
7019 BLOCK_COMMENT("} verify_oop ");
7020 }
7021
7022 const char* MacroAssembler::stop_types[] = {
7023 "stop",
7024 "untested",
7025 "unimplemented",
7026 "shouldnotreachhere"
7027 };
7028
7029 static void stop_on_request(const char* tp, const char* msg) {
7030 tty->print("Z assembly code requires stop: (%s) %s\n", tp, msg);
7031 guarantee(false, "Z assembly code requires stop: %s", msg);
7032 }
7033
7034 void MacroAssembler::stop(int type, const char* msg, int id) {
7035 BLOCK_COMMENT(err_msg("stop: %s {", msg));
7036
7037 // Setup arguments.
7038 load_const(Z_ARG1, (void*) stop_types[type%stop_end]);
7039 load_const(Z_ARG2, (void*) msg);
7040 get_PC(Z_R14); // Following code pushes a frame without entering a new function. Use current pc as return address.
7041 save_return_pc(); // Saves return pc Z_R14.
7042 push_frame_abi160(0);
7043 call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
7044 // The plain disassembler does not recognize illtrap. It instead displays
7045 // a 32-bit value. Issueing two illtraps assures the disassembler finds
7046 // the proper beginning of the next instruction.
7047 z_illtrap(); // Illegal instruction.
7048 z_illtrap(); // Illegal instruction.
7049
7050 BLOCK_COMMENT(" } stop");
7051 }
7052
7053 // Special version of stop() for code size reduction.
7054 // Reuses the previously generated call sequence, if any.
7055 // Generates the call sequence on its own, if necessary.
7056 // Note: This code will work only in non-relocatable code!
7057 // The relative address of the data elements (arg1, arg2) must not change.
7058 // The reentry point must not move relative to it's users. This prerequisite
7059 // should be given for "hand-written" code, if all chain calls are in the same code blob.
7060 // Generated code must not undergo any transformation, e.g. ShortenBranches, to be safe.
7061 address MacroAssembler::stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation) {
7062 BLOCK_COMMENT(err_msg("stop_chain(%s,%s): %s {", reentry==NULL?"init":"cont", allow_relocation?"reloc ":"static", msg));
7063
7064 // Setup arguments.
7065 if (allow_relocation) {
7066 // Relocatable version (for comparison purposes). Remove after some time.
7067 load_const(Z_ARG1, (void*) stop_types[type%stop_end]);
7068 load_const(Z_ARG2, (void*) msg);
7069 } else {
7070 load_absolute_address(Z_ARG1, (address)stop_types[type%stop_end]);
7071 load_absolute_address(Z_ARG2, (address)msg);
7072 }
7073 if ((reentry != NULL) && RelAddr::is_in_range_of_RelAddr16(reentry, pc())) {
7074 BLOCK_COMMENT("branch to reentry point:");
7075 z_brc(bcondAlways, reentry);
7076 } else {
7077 BLOCK_COMMENT("reentry point:");
7078 reentry = pc(); // Re-entry point for subsequent stop calls.
7079 save_return_pc(); // Saves return pc Z_R14.
7080 push_frame_abi160(0);
7081 if (allow_relocation) {
7082 reentry = NULL; // Prevent reentry if code relocation is allowed.
7083 call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
7084 } else {
7085 call_VM_leaf_static(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
7086 }
7087 z_illtrap(); // Illegal instruction as emergency stop, should the above call return.
7088 }
7089 BLOCK_COMMENT(" } stop_chain");
7090
7091 return reentry;
7092 }
7093
7094 // Special version of stop() for code size reduction.
7095 // Assumes constant relative addresses for data and runtime call.
7096 void MacroAssembler::stop_static(int type, const char* msg, int id) {
7097 stop_chain(NULL, type, msg, id, false);
7098 }
7099
7100 void MacroAssembler::stop_subroutine() {
7101 unimplemented("stop_subroutine", 710);
7102 }
7103
7104 // Prints msg to stdout from within generated code..
7105 void MacroAssembler::warn(const char* msg) {
7106 RegisterSaver::save_live_registers(this, RegisterSaver::all_registers, Z_R14);
7107 load_absolute_address(Z_R1, (address) warning);
7108 load_absolute_address(Z_ARG1, (address) msg);
7109 (void) call(Z_R1);
7110 RegisterSaver::restore_live_registers(this, RegisterSaver::all_registers);
7111 }
7112
7113 #ifndef PRODUCT
7114
7115 // Write pattern 0x0101010101010101 in region [low-before, high+after].
7116 void MacroAssembler::zap_from_to(Register low, Register high, Register val, Register addr, int before, int after) {
7117 if (!ZapEmptyStackFields) return;
7118 BLOCK_COMMENT("zap memory region {");
7119 load_const_optimized(val, 0x0101010101010101);
7120 int size = before + after;
7121 if (low == high && size < 5 && size > 0) {
7122 int offset = -before*BytesPerWord;
7123 for (int i = 0; i < size; ++i) {
7124 z_stg(val, Address(low, offset));
7125 offset +=(1*BytesPerWord);
7126 }
7127 } else {
7128 add2reg(addr, -before*BytesPerWord, low);
7129 if (after) {
7130 #ifdef ASSERT
7131 jlong check = after * BytesPerWord;
7132 assert(Immediate::is_simm32(check) && Immediate::is_simm32(-check), "value not encodable !");
7133 #endif
7134 add2reg(high, after * BytesPerWord);
7135 }
7136 NearLabel loop;
7137 bind(loop);
7138 z_stg(val, Address(addr));
7139 add2reg(addr, 8);
7140 compare64_and_branch(addr, high, bcondNotHigh, loop);
7141 if (after) {
7142 add2reg(high, -after * BytesPerWord);
7143 }
7144 }
7145 BLOCK_COMMENT("} zap memory region");
7146 }
7147 #endif // !PRODUCT
7148
7149 SkipIfEqual::SkipIfEqual(MacroAssembler* masm, const bool* flag_addr, bool value, Register _rscratch) {
7150 _masm = masm;
7151 _masm->load_absolute_address(_rscratch, (address)flag_addr);
7152 _masm->load_and_test_int(_rscratch, Address(_rscratch));
7153 if (value) {
7154 _masm->z_brne(_label); // Skip if true, i.e. != 0.
7155 } else {
7156 _masm->z_bre(_label); // Skip if false, i.e. == 0.
7157 }
7158 }
7159
7160 SkipIfEqual::~SkipIfEqual() {
7161 _masm->bind(_label);
7162 }