1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71
72 NEEDS_CLEANUP // remove this definitions ?
73 const Register IC_Klass = rax; // where the IC klass is cached
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == NULL) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == NULL) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164
165 void LIR_Assembler::set_24bit_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
167 }
168
169 void LIR_Assembler::reset_FPU() {
170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
171 }
172
173 void LIR_Assembler::fpop() {
174 __ fpop();
175 }
176
177 void LIR_Assembler::fxch(int i) {
178 __ fxch(i);
179 }
180
181 void LIR_Assembler::fld(int i) {
182 __ fld_s(i);
183 }
184
185 void LIR_Assembler::ffree(int i) {
186 __ ffree(i);
187 }
188
189 void LIR_Assembler::breakpoint() {
190 __ int3();
191 }
192
193 void LIR_Assembler::push(LIR_Opr opr) {
194 if (opr->is_single_cpu()) {
195 __ push_reg(opr->as_register());
196 } else if (opr->is_double_cpu()) {
197 NOT_LP64(__ push_reg(opr->as_register_hi()));
198 __ push_reg(opr->as_register_lo());
199 } else if (opr->is_stack()) {
200 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
201 } else if (opr->is_constant()) {
202 LIR_Const* const_opr = opr->as_constant_ptr();
203 if (const_opr->type() == T_OBJECT) {
204 __ push_oop(const_opr->as_jobject());
205 } else if (const_opr->type() == T_INT) {
206 __ push_jint(const_opr->as_jint());
207 } else {
208 ShouldNotReachHere();
209 }
210
211 } else {
212 ShouldNotReachHere();
213 }
214 }
215
216 void LIR_Assembler::pop(LIR_Opr opr) {
217 if (opr->is_single_cpu()) {
218 __ pop_reg(opr->as_register());
219 } else {
220 ShouldNotReachHere();
221 }
222 }
223
224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
225 return addr->base()->is_illegal() && addr->index()->is_illegal();
226 }
227
228 //-------------------------------------------
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr) {
231 return as_Address(addr, rscratch1);
232 }
233
234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
235 if (addr->base()->is_illegal()) {
236 assert(addr->index()->is_illegal(), "must be illegal too");
237 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
238 if (! __ reachable(laddr)) {
239 __ movptr(tmp, laddr.addr());
240 Address res(tmp, 0);
241 return res;
242 } else {
243 return __ as_Address(laddr);
244 }
245 }
246
247 Register base = addr->base()->as_pointer_register();
248
249 if (addr->index()->is_illegal()) {
250 return Address( base, addr->disp());
251 } else if (addr->index()->is_cpu_register()) {
252 Register index = addr->index()->as_pointer_register();
253 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
254 } else if (addr->index()->is_constant()) {
255 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
256 assert(Assembler::is_simm32(addr_offset), "must be");
257
258 return Address(base, addr_offset);
259 } else {
260 Unimplemented();
261 return Address();
262 }
263 }
264
265
266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
267 Address base = as_Address(addr);
268 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
269 }
270
271
272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
273 return as_Address(addr);
274 }
275
276
277 void LIR_Assembler::osr_entry() {
278 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
279 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
280 ValueStack* entry_state = osr_entry->state();
281 int number_of_locks = entry_state->locks_size();
282
283 // we jump here if osr happens with the interpreter
284 // state set up to continue at the beginning of the
285 // loop that triggered osr - in particular, we have
286 // the following registers setup:
287 //
288 // rcx: osr buffer
289 //
290
291 // build frame
292 ciMethod* m = compilation()->method();
293 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
294
295 // OSR buffer is
296 //
297 // locals[nlocals-1..0]
298 // monitors[0..number_of_locks]
299 //
300 // locals is a direct copy of the interpreter frame so in the osr buffer
301 // so first slot in the local array is the last local from the interpreter
302 // and last slot is local[0] (receiver) from the interpreter
303 //
304 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
305 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
306 // in the interpreter frame (the method lock if a sync method)
307
308 // Initialize monitors in the compiled activation.
309 // rcx: pointer to osr buffer
310 //
311 // All other registers are dead at this point and the locals will be
312 // copied into place by code emitted in the IR.
313
314 Register OSR_buf = osrBufferPointer()->as_pointer_register();
315 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
316 int monitor_offset = BytesPerWord * method()->max_locals() +
317 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
318 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
319 // the OSR buffer using 2 word entries: first the lock and then
320 // the oop.
321 for (int i = 0; i < number_of_locks; i++) {
322 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
323 #ifdef ASSERT
324 // verify the interpreter's monitor has a non-null object
325 {
326 Label L;
327 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
328 __ jcc(Assembler::notZero, L);
329 __ stop("locked object is NULL");
330 __ bind(L);
331 }
332 #endif
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
334 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
335 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
336 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
337 }
338 }
339 }
340
341
342 // inline cache check; done before the frame is built.
343 int LIR_Assembler::check_icache() {
344 Register receiver = FrameMap::receiver_opr->as_register();
345 Register ic_klass = IC_Klass;
346 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
347 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
348 if (!do_post_padding) {
349 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
350 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
351 }
352 int offset = __ offset();
353 __ inline_cache_check(receiver, IC_Klass);
354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
355 if (do_post_padding) {
356 // force alignment after the cache check.
357 // It's been verified to be aligned if !VerifyOops
358 __ align(CodeEntryAlignment);
359 }
360 return offset;
361 }
362
363
364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 jobject o = NULL;
366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
367 __ movoop(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
372 Metadata* o = NULL;
373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
374 __ mov_metadata(reg, o);
375 patching_epilog(patch, lir_patch_normal, reg, info);
376 }
377
378 // This specifies the rsp decrement needed to build the frame
379 int LIR_Assembler::initial_frame_size_in_bytes() const {
380 // if rounding, must let FrameMap know!
381
382 // The frame_map records size in slots (32bit word)
383
384 // subtract two words to account for return address and link
385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
386 }
387
388
389 int LIR_Assembler::emit_exception_handler() {
390 // if the last instruction is a call (typically to do a throw which
391 // is coming at the end after block reordering) the return address
392 // must still point into the code area in order to avoid assertion
393 // failures when searching for the corresponding bci => add a nop
394 // (was bug 5/14/1999 - gri)
395 __ nop();
396
397 // generate code for exception handler
398 address handler_base = __ start_a_stub(exception_handler_size());
399 if (handler_base == NULL) {
400 // not enough space left for the handler
401 bailout("exception handler overflow");
402 return -1;
403 }
404
405 int offset = code_offset();
406
407 // the exception oop and pc are in rax, and rdx
408 // no other registers need to be preserved, so invalidate them
409 __ invalidate_registers(false, true, true, false, true, true);
410
411 // check that there is really an exception
412 __ verify_not_null_oop(rax);
413
414 // search an exception handler (rax: exception oop, rdx: throwing pc)
415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
416 __ should_not_reach_here();
417 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
418 __ end_a_stub();
419
420 return offset;
421 }
422
423
424 // Emit the code to remove the frame from the stack in the exception
425 // unwind path.
426 int LIR_Assembler::emit_unwind_handler() {
427 #ifndef PRODUCT
428 if (CommentedAssembly) {
429 _masm->block_comment("Unwind handler");
430 }
431 #endif
432
433 int offset = code_offset();
434
435 // Fetch the exception from TLS and clear out exception related thread state
436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
437 NOT_LP64(__ get_thread(rsi));
438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
441
442 __ bind(_unwind_handler_entry);
443 __ verify_not_null_oop(rax);
444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
446 }
447
448 // Preform needed unlocking
449 MonitorExitStub* stub = NULL;
450 if (method()->is_synchronized()) {
451 monitor_address(0, FrameMap::rax_opr);
452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
453 __ unlock_object(rdi, rsi, rax, *stub->entry());
454 __ bind(*stub->continuation());
455 }
456
457 if (compilation()->env()->dtrace_method_probes()) {
458 #ifdef _LP64
459 __ mov(rdi, r15_thread);
460 __ mov_metadata(rsi, method()->constant_encoding());
461 #else
462 __ get_thread(rax);
463 __ movptr(Address(rsp, 0), rax);
464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
465 #endif
466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
467 }
468
469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
470 __ mov(rax, rbx); // Restore the exception
471 }
472
473 // remove the activation and dispatch to the unwind handler
474 __ remove_frame(initial_frame_size_in_bytes());
475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
476
477 // Emit the slow path assembly
478 if (stub != NULL) {
479 stub->emit_code(this);
480 }
481
482 return offset;
483 }
484
485
486 int LIR_Assembler::emit_deopt_handler() {
487 // if the last instruction is a call (typically to do a throw which
488 // is coming at the end after block reordering) the return address
489 // must still point into the code area in order to avoid assertion
490 // failures when searching for the corresponding bci => add a nop
491 // (was bug 5/14/1999 - gri)
492 __ nop();
493
494 // generate code for exception handler
495 address handler_base = __ start_a_stub(deopt_handler_size());
496 if (handler_base == NULL) {
497 // not enough space left for the handler
498 bailout("deopt handler overflow");
499 return -1;
500 }
501
502 int offset = code_offset();
503 InternalAddress here(__ pc());
504
505 __ pushptr(here.addr());
506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
507 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
508 __ end_a_stub();
509
510 return offset;
511 }
512
513
514 void LIR_Assembler::return_op(LIR_Opr result) {
515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
517 assert(result->fpu() == 0, "result must already be on TOS");
518 }
519
520 // Pop the stack before the safepoint code
521 __ remove_frame(initial_frame_size_in_bytes());
522
523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
524 __ reserved_stack_check();
525 }
526
527 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
528
529 // Note: we do not need to round double result; float result has the right precision
530 // the poll sets the condition code, but no data registers
531
532 if (SafepointMechanism::uses_thread_local_poll()) {
533 #ifdef _LP64
534 const Register poll_addr = rscratch1;
535 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
536 #else
537 const Register poll_addr = rbx;
538 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
539 __ get_thread(poll_addr);
540 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
541 #endif
542 __ relocate(relocInfo::poll_return_type);
543 __ testl(rax, Address(poll_addr, 0));
544 } else {
545 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
546
547 if (Assembler::is_polling_page_far()) {
548 __ lea(rscratch1, polling_page);
549 __ relocate(relocInfo::poll_return_type);
550 __ testl(rax, Address(rscratch1, 0));
551 } else {
552 __ testl(rax, polling_page);
553 }
554 }
555 __ ret(0);
556 }
557
558
559 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
560 guarantee(info != NULL, "Shouldn't be NULL");
561 int offset = __ offset();
562 if (SafepointMechanism::uses_thread_local_poll()) {
563 #ifdef _LP64
564 const Register poll_addr = rscratch1;
565 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
566 #else
567 assert(tmp->is_cpu_register(), "needed");
568 const Register poll_addr = tmp->as_register();
569 __ get_thread(poll_addr);
570 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
571 #endif
572 add_debug_info_for_branch(info);
573 __ relocate(relocInfo::poll_type);
574 address pre_pc = __ pc();
575 __ testl(rax, Address(poll_addr, 0));
576 address post_pc = __ pc();
577 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
578 } else {
579 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
580 if (Assembler::is_polling_page_far()) {
581 __ lea(rscratch1, polling_page);
582 offset = __ offset();
583 add_debug_info_for_branch(info);
584 __ relocate(relocInfo::poll_type);
585 __ testl(rax, Address(rscratch1, 0));
586 } else {
587 add_debug_info_for_branch(info);
588 __ testl(rax, polling_page);
589 }
590 }
591 return offset;
592 }
593
594
595 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
596 if (from_reg != to_reg) __ mov(to_reg, from_reg);
597 }
598
599 void LIR_Assembler::swap_reg(Register a, Register b) {
600 __ xchgptr(a, b);
601 }
602
603
604 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
605 assert(src->is_constant(), "should not call otherwise");
606 assert(dest->is_register(), "should not call otherwise");
607 LIR_Const* c = src->as_constant_ptr();
608
609 switch (c->type()) {
610 case T_INT: {
611 assert(patch_code == lir_patch_none, "no patching handled here");
612 __ movl(dest->as_register(), c->as_jint());
613 break;
614 }
615
616 case T_ADDRESS: {
617 assert(patch_code == lir_patch_none, "no patching handled here");
618 __ movptr(dest->as_register(), c->as_jint());
619 break;
620 }
621
622 case T_LONG: {
623 assert(patch_code == lir_patch_none, "no patching handled here");
624 #ifdef _LP64
625 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
626 #else
627 __ movptr(dest->as_register_lo(), c->as_jint_lo());
628 __ movptr(dest->as_register_hi(), c->as_jint_hi());
629 #endif // _LP64
630 break;
631 }
632
633 case T_OBJECT: {
634 if (patch_code != lir_patch_none) {
635 jobject2reg_with_patching(dest->as_register(), info);
636 } else {
637 __ movoop(dest->as_register(), c->as_jobject());
638 }
639 break;
640 }
641
642 case T_METADATA: {
643 if (patch_code != lir_patch_none) {
644 klass2reg_with_patching(dest->as_register(), info);
645 } else {
646 __ mov_metadata(dest->as_register(), c->as_metadata());
647 }
648 break;
649 }
650
651 case T_FLOAT: {
652 if (dest->is_single_xmm()) {
653 if (c->is_zero_float()) {
654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
655 } else {
656 __ movflt(dest->as_xmm_float_reg(),
657 InternalAddress(float_constant(c->as_jfloat())));
658 }
659 } else {
660 assert(dest->is_single_fpu(), "must be");
661 assert(dest->fpu_regnr() == 0, "dest must be TOS");
662 if (c->is_zero_float()) {
663 __ fldz();
664 } else if (c->is_one_float()) {
665 __ fld1();
666 } else {
667 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
668 }
669 }
670 break;
671 }
672
673 case T_DOUBLE: {
674 if (dest->is_double_xmm()) {
675 if (c->is_zero_double()) {
676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
677 } else {
678 __ movdbl(dest->as_xmm_double_reg(),
679 InternalAddress(double_constant(c->as_jdouble())));
680 }
681 } else {
682 assert(dest->is_double_fpu(), "must be");
683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
684 if (c->is_zero_double()) {
685 __ fldz();
686 } else if (c->is_one_double()) {
687 __ fld1();
688 } else {
689 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
690 }
691 }
692 break;
693 }
694
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
701 assert(src->is_constant(), "should not call otherwise");
702 assert(dest->is_stack(), "should not call otherwise");
703 LIR_Const* c = src->as_constant_ptr();
704
705 switch (c->type()) {
706 case T_INT: // fall through
707 case T_FLOAT:
708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
709 break;
710
711 case T_ADDRESS:
712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
713 break;
714
715 case T_OBJECT:
716 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
717 break;
718
719 case T_LONG: // fall through
720 case T_DOUBLE:
721 #ifdef _LP64
722 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
723 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
724 #else
725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
726 lo_word_offset_in_bytes), c->as_jint_lo_bits());
727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
728 hi_word_offset_in_bytes), c->as_jint_hi_bits());
729 #endif // _LP64
730 break;
731
732 default:
733 ShouldNotReachHere();
734 }
735 }
736
737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
738 assert(src->is_constant(), "should not call otherwise");
739 assert(dest->is_address(), "should not call otherwise");
740 LIR_Const* c = src->as_constant_ptr();
741 LIR_Address* addr = dest->as_address_ptr();
742
743 int null_check_here = code_offset();
744 switch (type) {
745 case T_INT: // fall through
746 case T_FLOAT:
747 __ movl(as_Address(addr), c->as_jint_bits());
748 break;
749
750 case T_ADDRESS:
751 __ movptr(as_Address(addr), c->as_jint_bits());
752 break;
753
754 case T_OBJECT: // fall through
755 case T_ARRAY:
756 if (c->as_jobject() == NULL) {
757 if (UseCompressedOops && !wide) {
758 __ movl(as_Address(addr), (int32_t)NULL_WORD);
759 } else {
760 #ifdef _LP64
761 __ xorptr(rscratch1, rscratch1);
762 null_check_here = code_offset();
763 __ movptr(as_Address(addr), rscratch1);
764 #else
765 __ movptr(as_Address(addr), NULL_WORD);
766 #endif
767 }
768 } else {
769 if (is_literal_address(addr)) {
770 ShouldNotReachHere();
771 __ movoop(as_Address(addr, noreg), c->as_jobject());
772 } else {
773 #ifdef _LP64
774 __ movoop(rscratch1, c->as_jobject());
775 if (UseCompressedOops && !wide) {
776 __ encode_heap_oop(rscratch1);
777 null_check_here = code_offset();
778 __ movl(as_Address_lo(addr), rscratch1);
779 } else {
780 null_check_here = code_offset();
781 __ movptr(as_Address_lo(addr), rscratch1);
782 }
783 #else
784 __ movoop(as_Address(addr), c->as_jobject());
785 #endif
786 }
787 }
788 break;
789
790 case T_LONG: // fall through
791 case T_DOUBLE:
792 #ifdef _LP64
793 if (is_literal_address(addr)) {
794 ShouldNotReachHere();
795 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
796 } else {
797 __ movptr(r10, (intptr_t)c->as_jlong_bits());
798 null_check_here = code_offset();
799 __ movptr(as_Address_lo(addr), r10);
800 }
801 #else
802 // Always reachable in 32bit so this doesn't produce useless move literal
803 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
804 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
805 #endif // _LP64
806 break;
807
808 case T_BOOLEAN: // fall through
809 case T_BYTE:
810 __ movb(as_Address(addr), c->as_jint() & 0xFF);
811 break;
812
813 case T_CHAR: // fall through
814 case T_SHORT:
815 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
816 break;
817
818 default:
819 ShouldNotReachHere();
820 };
821
822 if (info != NULL) {
823 add_debug_info_for_null_check(null_check_here, info);
824 }
825 }
826
827
828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
829 assert(src->is_register(), "should not call otherwise");
830 assert(dest->is_register(), "should not call otherwise");
831
832 // move between cpu-registers
833 if (dest->is_single_cpu()) {
834 #ifdef _LP64
835 if (src->type() == T_LONG) {
836 // Can do LONG -> OBJECT
837 move_regs(src->as_register_lo(), dest->as_register());
838 return;
839 }
840 #endif
841 assert(src->is_single_cpu(), "must match");
842 if (src->type() == T_OBJECT) {
843 __ verify_oop(src->as_register());
844 }
845 move_regs(src->as_register(), dest->as_register());
846
847 } else if (dest->is_double_cpu()) {
848 #ifdef _LP64
849 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
850 // Surprising to me but we can see move of a long to t_object
851 __ verify_oop(src->as_register());
852 move_regs(src->as_register(), dest->as_register_lo());
853 return;
854 }
855 #endif
856 assert(src->is_double_cpu(), "must match");
857 Register f_lo = src->as_register_lo();
858 Register f_hi = src->as_register_hi();
859 Register t_lo = dest->as_register_lo();
860 Register t_hi = dest->as_register_hi();
861 #ifdef _LP64
862 assert(f_hi == f_lo, "must be same");
863 assert(t_hi == t_lo, "must be same");
864 move_regs(f_lo, t_lo);
865 #else
866 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
867
868
869 if (f_lo == t_hi && f_hi == t_lo) {
870 swap_reg(f_lo, f_hi);
871 } else if (f_hi == t_lo) {
872 assert(f_lo != t_hi, "overwriting register");
873 move_regs(f_hi, t_hi);
874 move_regs(f_lo, t_lo);
875 } else {
876 assert(f_hi != t_lo, "overwriting register");
877 move_regs(f_lo, t_lo);
878 move_regs(f_hi, t_hi);
879 }
880 #endif // LP64
881
882 // special moves from fpu-register to xmm-register
883 // necessary for method results
884 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
885 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
886 __ fld_s(Address(rsp, 0));
887 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
888 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
889 __ fld_d(Address(rsp, 0));
890 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
891 __ fstp_s(Address(rsp, 0));
892 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
893 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
894 __ fstp_d(Address(rsp, 0));
895 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
896
897 // move between xmm-registers
898 } else if (dest->is_single_xmm()) {
899 assert(src->is_single_xmm(), "must match");
900 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
901 } else if (dest->is_double_xmm()) {
902 assert(src->is_double_xmm(), "must match");
903 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
904
905 // move between fpu-registers (no instruction necessary because of fpu-stack)
906 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
907 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
908 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
909 } else {
910 ShouldNotReachHere();
911 }
912 }
913
914 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
915 assert(src->is_register(), "should not call otherwise");
916 assert(dest->is_stack(), "should not call otherwise");
917
918 if (src->is_single_cpu()) {
919 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
920 if (type == T_OBJECT || type == T_ARRAY) {
921 __ verify_oop(src->as_register());
922 __ movptr (dst, src->as_register());
923 } else if (type == T_METADATA) {
924 __ movptr (dst, src->as_register());
925 } else {
926 __ movl (dst, src->as_register());
927 }
928
929 } else if (src->is_double_cpu()) {
930 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
931 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
932 __ movptr (dstLO, src->as_register_lo());
933 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
934
935 } else if (src->is_single_xmm()) {
936 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
937 __ movflt(dst_addr, src->as_xmm_float_reg());
938
939 } else if (src->is_double_xmm()) {
940 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
941 __ movdbl(dst_addr, src->as_xmm_double_reg());
942
943 } else if (src->is_single_fpu()) {
944 assert(src->fpu_regnr() == 0, "argument must be on TOS");
945 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
946 if (pop_fpu_stack) __ fstp_s (dst_addr);
947 else __ fst_s (dst_addr);
948
949 } else if (src->is_double_fpu()) {
950 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
951 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
952 if (pop_fpu_stack) __ fstp_d (dst_addr);
953 else __ fst_d (dst_addr);
954
955 } else {
956 ShouldNotReachHere();
957 }
958 }
959
960
961 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
962 LIR_Address* to_addr = dest->as_address_ptr();
963 PatchingStub* patch = NULL;
964 Register compressed_src = rscratch1;
965
966 if (type == T_ARRAY || type == T_OBJECT) {
967 __ verify_oop(src->as_register());
968 #ifdef _LP64
969 if (UseCompressedOops && !wide) {
970 __ movptr(compressed_src, src->as_register());
971 __ encode_heap_oop(compressed_src);
972 if (patch_code != lir_patch_none) {
973 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
974 }
975 }
976 #endif
977 }
978
979 if (patch_code != lir_patch_none) {
980 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
981 Address toa = as_Address(to_addr);
982 assert(toa.disp() != 0, "must have");
983 }
984
985 int null_check_here = code_offset();
986 switch (type) {
987 case T_FLOAT: {
988 if (src->is_single_xmm()) {
989 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
990 } else {
991 assert(src->is_single_fpu(), "must be");
992 assert(src->fpu_regnr() == 0, "argument must be on TOS");
993 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
994 else __ fst_s (as_Address(to_addr));
995 }
996 break;
997 }
998
999 case T_DOUBLE: {
1000 if (src->is_double_xmm()) {
1001 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1002 } else {
1003 assert(src->is_double_fpu(), "must be");
1004 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1005 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1006 else __ fst_d (as_Address(to_addr));
1007 }
1008 break;
1009 }
1010
1011 case T_ARRAY: // fall through
1012 case T_OBJECT: // fall through
1013 if (UseCompressedOops && !wide) {
1014 __ movl(as_Address(to_addr), compressed_src);
1015 } else {
1016 __ movptr(as_Address(to_addr), src->as_register());
1017 }
1018 break;
1019 case T_METADATA:
1020 // We get here to store a method pointer to the stack to pass to
1021 // a dtrace runtime call. This can't work on 64 bit with
1022 // compressed klass ptrs: T_METADATA can be a compressed klass
1023 // ptr or a 64 bit method pointer.
1024 LP64_ONLY(ShouldNotReachHere());
1025 __ movptr(as_Address(to_addr), src->as_register());
1026 break;
1027 case T_ADDRESS:
1028 __ movptr(as_Address(to_addr), src->as_register());
1029 break;
1030 case T_INT:
1031 __ movl(as_Address(to_addr), src->as_register());
1032 break;
1033
1034 case T_LONG: {
1035 Register from_lo = src->as_register_lo();
1036 Register from_hi = src->as_register_hi();
1037 #ifdef _LP64
1038 __ movptr(as_Address_lo(to_addr), from_lo);
1039 #else
1040 Register base = to_addr->base()->as_register();
1041 Register index = noreg;
1042 if (to_addr->index()->is_register()) {
1043 index = to_addr->index()->as_register();
1044 }
1045 if (base == from_lo || index == from_lo) {
1046 assert(base != from_hi, "can't be");
1047 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1048 __ movl(as_Address_hi(to_addr), from_hi);
1049 if (patch != NULL) {
1050 patching_epilog(patch, lir_patch_high, base, info);
1051 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1052 patch_code = lir_patch_low;
1053 }
1054 __ movl(as_Address_lo(to_addr), from_lo);
1055 } else {
1056 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1057 __ movl(as_Address_lo(to_addr), from_lo);
1058 if (patch != NULL) {
1059 patching_epilog(patch, lir_patch_low, base, info);
1060 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1061 patch_code = lir_patch_high;
1062 }
1063 __ movl(as_Address_hi(to_addr), from_hi);
1064 }
1065 #endif // _LP64
1066 break;
1067 }
1068
1069 case T_BYTE: // fall through
1070 case T_BOOLEAN: {
1071 Register src_reg = src->as_register();
1072 Address dst_addr = as_Address(to_addr);
1073 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1074 __ movb(dst_addr, src_reg);
1075 break;
1076 }
1077
1078 case T_CHAR: // fall through
1079 case T_SHORT:
1080 __ movw(as_Address(to_addr), src->as_register());
1081 break;
1082
1083 default:
1084 ShouldNotReachHere();
1085 }
1086 if (info != NULL) {
1087 add_debug_info_for_null_check(null_check_here, info);
1088 }
1089
1090 if (patch_code != lir_patch_none) {
1091 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1092 }
1093 }
1094
1095
1096 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1097 assert(src->is_stack(), "should not call otherwise");
1098 assert(dest->is_register(), "should not call otherwise");
1099
1100 if (dest->is_single_cpu()) {
1101 if (type == T_ARRAY || type == T_OBJECT) {
1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1103 __ verify_oop(dest->as_register());
1104 } else if (type == T_METADATA) {
1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1106 } else {
1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1108 }
1109
1110 } else if (dest->is_double_cpu()) {
1111 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1112 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1113 __ movptr(dest->as_register_lo(), src_addr_LO);
1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1115
1116 } else if (dest->is_single_xmm()) {
1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1118 __ movflt(dest->as_xmm_float_reg(), src_addr);
1119
1120 } else if (dest->is_double_xmm()) {
1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1122 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1123
1124 } else if (dest->is_single_fpu()) {
1125 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1126 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1127 __ fld_s(src_addr);
1128
1129 } else if (dest->is_double_fpu()) {
1130 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1131 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1132 __ fld_d(src_addr);
1133
1134 } else {
1135 ShouldNotReachHere();
1136 }
1137 }
1138
1139
1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1141 if (src->is_single_stack()) {
1142 if (type == T_OBJECT || type == T_ARRAY) {
1143 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1145 } else {
1146 #ifndef _LP64
1147 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1148 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1149 #else
1150 //no pushl on 64bits
1151 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1152 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1153 #endif
1154 }
1155
1156 } else if (src->is_double_stack()) {
1157 #ifdef _LP64
1158 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1159 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1160 #else
1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1162 // push and pop the part at src + wordSize, adding wordSize for the previous push
1163 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1165 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1166 #endif // _LP64
1167
1168 } else {
1169 ShouldNotReachHere();
1170 }
1171 }
1172
1173
1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1175 assert(src->is_address(), "should not call otherwise");
1176 assert(dest->is_register(), "should not call otherwise");
1177
1178 LIR_Address* addr = src->as_address_ptr();
1179 Address from_addr = as_Address(addr);
1180
1181 if (addr->base()->type() == T_OBJECT) {
1182 __ verify_oop(addr->base()->as_pointer_register());
1183 }
1184
1185 switch (type) {
1186 case T_BOOLEAN: // fall through
1187 case T_BYTE: // fall through
1188 case T_CHAR: // fall through
1189 case T_SHORT:
1190 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1191 // on pre P6 processors we may get partial register stalls
1192 // so blow away the value of to_rinfo before loading a
1193 // partial word into it. Do it here so that it precedes
1194 // the potential patch point below.
1195 __ xorptr(dest->as_register(), dest->as_register());
1196 }
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 PatchingStub* patch = NULL;
1203 if (patch_code != lir_patch_none) {
1204 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1205 assert(from_addr.disp() != 0, "must have");
1206 }
1207 if (info != NULL) {
1208 add_debug_info_for_null_check_here(info);
1209 }
1210
1211 switch (type) {
1212 case T_FLOAT: {
1213 if (dest->is_single_xmm()) {
1214 __ movflt(dest->as_xmm_float_reg(), from_addr);
1215 } else {
1216 assert(dest->is_single_fpu(), "must be");
1217 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1218 __ fld_s(from_addr);
1219 }
1220 break;
1221 }
1222
1223 case T_DOUBLE: {
1224 if (dest->is_double_xmm()) {
1225 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226 } else {
1227 assert(dest->is_double_fpu(), "must be");
1228 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1229 __ fld_d(from_addr);
1230 }
1231 break;
1232 }
1233
1234 case T_OBJECT: // fall through
1235 case T_ARRAY: // fall through
1236 if (UseCompressedOops && !wide) {
1237 __ movl(dest->as_register(), from_addr);
1238 } else {
1239 __ movptr(dest->as_register(), from_addr);
1240 }
1241 break;
1242
1243 case T_ADDRESS:
1244 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1245 __ movl(dest->as_register(), from_addr);
1246 } else {
1247 __ movptr(dest->as_register(), from_addr);
1248 }
1249 break;
1250 case T_INT:
1251 __ movl(dest->as_register(), from_addr);
1252 break;
1253
1254 case T_LONG: {
1255 Register to_lo = dest->as_register_lo();
1256 Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258 __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260 Register base = addr->base()->as_register();
1261 Register index = noreg;
1262 if (addr->index()->is_register()) {
1263 index = addr->index()->as_register();
1264 }
1265 if ((base == to_lo && index == to_hi) ||
1266 (base == to_hi && index == to_lo)) {
1267 // addresses with 2 registers are only formed as a result of
1268 // array access so this code will never have to deal with
1269 // patches or null checks.
1270 assert(info == NULL && patch == NULL, "must be");
1271 __ lea(to_hi, as_Address(addr));
1272 __ movl(to_lo, Address(to_hi, 0));
1273 __ movl(to_hi, Address(to_hi, BytesPerWord));
1274 } else if (base == to_lo || index == to_lo) {
1275 assert(base != to_hi, "can't be");
1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277 __ movl(to_hi, as_Address_hi(addr));
1278 if (patch != NULL) {
1279 patching_epilog(patch, lir_patch_high, base, info);
1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281 patch_code = lir_patch_low;
1282 }
1283 __ movl(to_lo, as_Address_lo(addr));
1284 } else {
1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286 __ movl(to_lo, as_Address_lo(addr));
1287 if (patch != NULL) {
1288 patching_epilog(patch, lir_patch_low, base, info);
1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290 patch_code = lir_patch_high;
1291 }
1292 __ movl(to_hi, as_Address_hi(addr));
1293 }
1294 #endif // _LP64
1295 break;
1296 }
1297
1298 case T_BOOLEAN: // fall through
1299 case T_BYTE: {
1300 Register dest_reg = dest->as_register();
1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303 __ movsbl(dest_reg, from_addr);
1304 } else {
1305 __ movb(dest_reg, from_addr);
1306 __ shll(dest_reg, 24);
1307 __ sarl(dest_reg, 24);
1308 }
1309 break;
1310 }
1311
1312 case T_CHAR: {
1313 Register dest_reg = dest->as_register();
1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316 __ movzwl(dest_reg, from_addr);
1317 } else {
1318 __ movw(dest_reg, from_addr);
1319 }
1320 break;
1321 }
1322
1323 case T_SHORT: {
1324 Register dest_reg = dest->as_register();
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movswl(dest_reg, from_addr);
1327 } else {
1328 __ movw(dest_reg, from_addr);
1329 __ shll(dest_reg, 16);
1330 __ sarl(dest_reg, 16);
1331 }
1332 break;
1333 }
1334
1335 default:
1336 ShouldNotReachHere();
1337 }
1338
1339 if (patch != NULL) {
1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341 }
1342
1343 if (type == T_ARRAY || type == T_OBJECT) {
1344 #ifdef _LP64
1345 if (UseCompressedOops && !wide) {
1346 __ decode_heap_oop(dest->as_register());
1347 }
1348 #endif
1349 #if INCLUDE_ZGC
1350 // Load barrier not yet applied, so a verification here would fail
1351 if (!UseZGC)
1352 #endif
1353 {
1354 __ verify_oop(dest->as_register());
1355 }
1356 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1357 #ifdef _LP64
1358 if (UseCompressedClassPointers) {
1359 __ decode_klass_not_null(dest->as_register());
1360 }
1361 #endif
1362 }
1363 }
1364
1365
1366 NEEDS_CLEANUP; // This could be static?
1367 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1368 int elem_size = type2aelembytes(type);
1369 switch (elem_size) {
1370 case 1: return Address::times_1;
1371 case 2: return Address::times_2;
1372 case 4: return Address::times_4;
1373 case 8: return Address::times_8;
1374 }
1375 ShouldNotReachHere();
1376 return Address::no_scale;
1377 }
1378
1379
1380 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1381 switch (op->code()) {
1382 case lir_idiv:
1383 case lir_irem:
1384 arithmetic_idiv(op->code(),
1385 op->in_opr1(),
1386 op->in_opr2(),
1387 op->in_opr3(),
1388 op->result_opr(),
1389 op->info());
1390 break;
1391 case lir_fmad:
1392 __ fmad(op->result_opr()->as_xmm_double_reg(),
1393 op->in_opr1()->as_xmm_double_reg(),
1394 op->in_opr2()->as_xmm_double_reg(),
1395 op->in_opr3()->as_xmm_double_reg());
1396 break;
1397 case lir_fmaf:
1398 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1399 op->in_opr1()->as_xmm_float_reg(),
1400 op->in_opr2()->as_xmm_float_reg(),
1401 op->in_opr3()->as_xmm_float_reg());
1402 break;
1403 default: ShouldNotReachHere(); break;
1404 }
1405 }
1406
1407 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1408 #ifdef ASSERT
1409 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1410 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1411 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1412 #endif
1413
1414 if (op->cond() == lir_cond_always) {
1415 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1416 __ jmp (*(op->label()));
1417 } else {
1418 Assembler::Condition acond = Assembler::zero;
1419 if (op->code() == lir_cond_float_branch) {
1420 assert(op->ublock() != NULL, "must have unordered successor");
1421 __ jcc(Assembler::parity, *(op->ublock()->label()));
1422 switch(op->cond()) {
1423 case lir_cond_equal: acond = Assembler::equal; break;
1424 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1425 case lir_cond_less: acond = Assembler::below; break;
1426 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1427 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1428 case lir_cond_greater: acond = Assembler::above; break;
1429 default: ShouldNotReachHere();
1430 }
1431 } else {
1432 switch (op->cond()) {
1433 case lir_cond_equal: acond = Assembler::equal; break;
1434 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1435 case lir_cond_less: acond = Assembler::less; break;
1436 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1437 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1438 case lir_cond_greater: acond = Assembler::greater; break;
1439 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1440 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1441 default: ShouldNotReachHere();
1442 }
1443 }
1444 __ jcc(acond,*(op->label()));
1445 }
1446 }
1447
1448 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1449 LIR_Opr src = op->in_opr();
1450 LIR_Opr dest = op->result_opr();
1451
1452 switch (op->bytecode()) {
1453 case Bytecodes::_i2l:
1454 #ifdef _LP64
1455 __ movl2ptr(dest->as_register_lo(), src->as_register());
1456 #else
1457 move_regs(src->as_register(), dest->as_register_lo());
1458 move_regs(src->as_register(), dest->as_register_hi());
1459 __ sarl(dest->as_register_hi(), 31);
1460 #endif // LP64
1461 break;
1462
1463 case Bytecodes::_l2i:
1464 #ifdef _LP64
1465 __ movl(dest->as_register(), src->as_register_lo());
1466 #else
1467 move_regs(src->as_register_lo(), dest->as_register());
1468 #endif
1469 break;
1470
1471 case Bytecodes::_i2b:
1472 move_regs(src->as_register(), dest->as_register());
1473 __ sign_extend_byte(dest->as_register());
1474 break;
1475
1476 case Bytecodes::_i2c:
1477 move_regs(src->as_register(), dest->as_register());
1478 __ andl(dest->as_register(), 0xFFFF);
1479 break;
1480
1481 case Bytecodes::_i2s:
1482 move_regs(src->as_register(), dest->as_register());
1483 __ sign_extend_short(dest->as_register());
1484 break;
1485
1486
1487 case Bytecodes::_f2d:
1488 case Bytecodes::_d2f:
1489 if (dest->is_single_xmm()) {
1490 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1491 } else if (dest->is_double_xmm()) {
1492 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1493 } else {
1494 assert(src->fpu() == dest->fpu(), "register must be equal");
1495 // do nothing (float result is rounded later through spilling)
1496 }
1497 break;
1498
1499 case Bytecodes::_i2f:
1500 case Bytecodes::_i2d:
1501 if (dest->is_single_xmm()) {
1502 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1503 } else if (dest->is_double_xmm()) {
1504 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1505 } else {
1506 assert(dest->fpu() == 0, "result must be on TOS");
1507 __ movl(Address(rsp, 0), src->as_register());
1508 __ fild_s(Address(rsp, 0));
1509 }
1510 break;
1511
1512 case Bytecodes::_f2i:
1513 case Bytecodes::_d2i:
1514 if (src->is_single_xmm()) {
1515 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1516 } else if (src->is_double_xmm()) {
1517 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1518 } else {
1519 assert(src->fpu() == 0, "input must be on TOS");
1520 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1521 __ fist_s(Address(rsp, 0));
1522 __ movl(dest->as_register(), Address(rsp, 0));
1523 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1524 }
1525
1526 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1527 assert(op->stub() != NULL, "stub required");
1528 __ cmpl(dest->as_register(), 0x80000000);
1529 __ jcc(Assembler::equal, *op->stub()->entry());
1530 __ bind(*op->stub()->continuation());
1531 break;
1532
1533 case Bytecodes::_l2f:
1534 case Bytecodes::_l2d:
1535 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1536 assert(dest->fpu() == 0, "result must be on TOS");
1537
1538 __ movptr(Address(rsp, 0), src->as_register_lo());
1539 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1540 __ fild_d(Address(rsp, 0));
1541 // float result is rounded later through spilling
1542 break;
1543
1544 case Bytecodes::_f2l:
1545 case Bytecodes::_d2l:
1546 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1547 assert(src->fpu() == 0, "input must be on TOS");
1548 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1549
1550 // instruction sequence too long to inline it here
1551 {
1552 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1553 }
1554 break;
1555
1556 default: ShouldNotReachHere();
1557 }
1558 }
1559
1560 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1561 if (op->init_check()) {
1562 add_debug_info_for_null_check_here(op->stub()->info());
1563 __ cmpb(Address(op->klass()->as_register(),
1564 InstanceKlass::init_state_offset()),
1565 InstanceKlass::fully_initialized);
1566 __ jcc(Assembler::notEqual, *op->stub()->entry());
1567 }
1568 __ allocate_object(op->obj()->as_register(),
1569 op->tmp1()->as_register(),
1570 op->tmp2()->as_register(),
1571 op->header_size(),
1572 op->object_size(),
1573 op->klass()->as_register(),
1574 *op->stub()->entry());
1575 __ bind(*op->stub()->continuation());
1576 }
1577
1578 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1579 Register len = op->len()->as_register();
1580 LP64_ONLY( __ movslq(len, len); )
1581
1582 if (UseSlowPath ||
1583 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1584 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1585 __ jmp(*op->stub()->entry());
1586 } else {
1587 Register tmp1 = op->tmp1()->as_register();
1588 Register tmp2 = op->tmp2()->as_register();
1589 Register tmp3 = op->tmp3()->as_register();
1590 if (len == tmp1) {
1591 tmp1 = tmp3;
1592 } else if (len == tmp2) {
1593 tmp2 = tmp3;
1594 } else if (len == tmp3) {
1595 // everything is ok
1596 } else {
1597 __ mov(tmp3, len);
1598 }
1599 __ allocate_array(op->obj()->as_register(),
1600 len,
1601 tmp1,
1602 tmp2,
1603 arrayOopDesc::header_size(op->type()),
1604 array_element_size(op->type()),
1605 op->klass()->as_register(),
1606 *op->stub()->entry());
1607 }
1608 __ bind(*op->stub()->continuation());
1609 }
1610
1611 void LIR_Assembler::type_profile_helper(Register mdo,
1612 ciMethodData *md, ciProfileData *data,
1613 Register recv, Label* update_done) {
1614 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1615 Label next_test;
1616 // See if the receiver is receiver[n].
1617 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1618 __ jccb(Assembler::notEqual, next_test);
1619 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1620 __ addptr(data_addr, DataLayout::counter_increment);
1621 __ jmp(*update_done);
1622 __ bind(next_test);
1623 }
1624
1625 // Didn't find receiver; find next empty slot and fill it in
1626 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1627 Label next_test;
1628 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1629 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1630 __ jccb(Assembler::notEqual, next_test);
1631 __ movptr(recv_addr, recv);
1632 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1633 __ jmp(*update_done);
1634 __ bind(next_test);
1635 }
1636 }
1637
1638 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1639 // we always need a stub for the failure case.
1640 CodeStub* stub = op->stub();
1641 Register obj = op->object()->as_register();
1642 Register k_RInfo = op->tmp1()->as_register();
1643 Register klass_RInfo = op->tmp2()->as_register();
1644 Register dst = op->result_opr()->as_register();
1645 ciKlass* k = op->klass();
1646 Register Rtmp1 = noreg;
1647
1648 // check if it needs to be profiled
1649 ciMethodData* md = NULL;
1650 ciProfileData* data = NULL;
1651
1652 if (op->should_profile()) {
1653 ciMethod* method = op->profiled_method();
1654 assert(method != NULL, "Should have method");
1655 int bci = op->profiled_bci();
1656 md = method->method_data_or_null();
1657 assert(md != NULL, "Sanity");
1658 data = md->bci_to_data(bci);
1659 assert(data != NULL, "need data for type check");
1660 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1661 }
1662 Label profile_cast_success, profile_cast_failure;
1663 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1664 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1665
1666 if (obj == k_RInfo) {
1667 k_RInfo = dst;
1668 } else if (obj == klass_RInfo) {
1669 klass_RInfo = dst;
1670 }
1671 if (k->is_loaded() && !UseCompressedClassPointers) {
1672 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1673 } else {
1674 Rtmp1 = op->tmp3()->as_register();
1675 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1676 }
1677
1678 assert_different_registers(obj, k_RInfo, klass_RInfo);
1679
1680 __ cmpptr(obj, (int32_t)NULL_WORD);
1681 if (op->should_profile()) {
1682 Label not_null;
1683 __ jccb(Assembler::notEqual, not_null);
1684 // Object is null; update MDO and exit
1685 Register mdo = klass_RInfo;
1686 __ mov_metadata(mdo, md->constant_encoding());
1687 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1688 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1689 __ orl(data_addr, header_bits);
1690 __ jmp(*obj_is_null);
1691 __ bind(not_null);
1692 } else {
1693 __ jcc(Assembler::equal, *obj_is_null);
1694 }
1695
1696 if (!k->is_loaded()) {
1697 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1698 } else {
1699 #ifdef _LP64
1700 __ mov_metadata(k_RInfo, k->constant_encoding());
1701 #endif // _LP64
1702 }
1703 __ verify_oop(obj);
1704
1705 if (op->fast_check()) {
1706 // get object class
1707 // not a safepoint as obj null check happens earlier
1708 #ifdef _LP64
1709 if (UseCompressedClassPointers) {
1710 __ load_klass(Rtmp1, obj);
1711 __ cmpptr(k_RInfo, Rtmp1);
1712 } else {
1713 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1714 }
1715 #else
1716 if (k->is_loaded()) {
1717 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1718 } else {
1719 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1720 }
1721 #endif
1722 __ jcc(Assembler::notEqual, *failure_target);
1723 // successful cast, fall through to profile or jump
1724 } else {
1725 // get object class
1726 // not a safepoint as obj null check happens earlier
1727 __ load_klass(klass_RInfo, obj);
1728 if (k->is_loaded()) {
1729 // See if we get an immediate positive hit
1730 #ifdef _LP64
1731 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1732 #else
1733 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1734 #endif // _LP64
1735 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1736 __ jcc(Assembler::notEqual, *failure_target);
1737 // successful cast, fall through to profile or jump
1738 } else {
1739 // See if we get an immediate positive hit
1740 __ jcc(Assembler::equal, *success_target);
1741 // check for self
1742 #ifdef _LP64
1743 __ cmpptr(klass_RInfo, k_RInfo);
1744 #else
1745 __ cmpklass(klass_RInfo, k->constant_encoding());
1746 #endif // _LP64
1747 __ jcc(Assembler::equal, *success_target);
1748
1749 __ push(klass_RInfo);
1750 #ifdef _LP64
1751 __ push(k_RInfo);
1752 #else
1753 __ pushklass(k->constant_encoding());
1754 #endif // _LP64
1755 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1756 __ pop(klass_RInfo);
1757 __ pop(klass_RInfo);
1758 // result is a boolean
1759 __ cmpl(klass_RInfo, 0);
1760 __ jcc(Assembler::equal, *failure_target);
1761 // successful cast, fall through to profile or jump
1762 }
1763 } else {
1764 // perform the fast part of the checking logic
1765 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1766 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1767 __ push(klass_RInfo);
1768 __ push(k_RInfo);
1769 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1770 __ pop(klass_RInfo);
1771 __ pop(k_RInfo);
1772 // result is a boolean
1773 __ cmpl(k_RInfo, 0);
1774 __ jcc(Assembler::equal, *failure_target);
1775 // successful cast, fall through to profile or jump
1776 }
1777 }
1778 if (op->should_profile()) {
1779 Register mdo = klass_RInfo, recv = k_RInfo;
1780 __ bind(profile_cast_success);
1781 __ mov_metadata(mdo, md->constant_encoding());
1782 __ load_klass(recv, obj);
1783 Label update_done;
1784 type_profile_helper(mdo, md, data, recv, success);
1785 __ jmp(*success);
1786
1787 __ bind(profile_cast_failure);
1788 __ mov_metadata(mdo, md->constant_encoding());
1789 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1790 __ subptr(counter_addr, DataLayout::counter_increment);
1791 __ jmp(*failure);
1792 }
1793 __ jmp(*success);
1794 }
1795
1796
1797 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1798 LIR_Code code = op->code();
1799 if (code == lir_store_check) {
1800 Register value = op->object()->as_register();
1801 Register array = op->array()->as_register();
1802 Register k_RInfo = op->tmp1()->as_register();
1803 Register klass_RInfo = op->tmp2()->as_register();
1804 Register Rtmp1 = op->tmp3()->as_register();
1805
1806 CodeStub* stub = op->stub();
1807
1808 // check if it needs to be profiled
1809 ciMethodData* md = NULL;
1810 ciProfileData* data = NULL;
1811
1812 if (op->should_profile()) {
1813 ciMethod* method = op->profiled_method();
1814 assert(method != NULL, "Should have method");
1815 int bci = op->profiled_bci();
1816 md = method->method_data_or_null();
1817 assert(md != NULL, "Sanity");
1818 data = md->bci_to_data(bci);
1819 assert(data != NULL, "need data for type check");
1820 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1821 }
1822 Label profile_cast_success, profile_cast_failure, done;
1823 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1824 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1825
1826 __ cmpptr(value, (int32_t)NULL_WORD);
1827 if (op->should_profile()) {
1828 Label not_null;
1829 __ jccb(Assembler::notEqual, not_null);
1830 // Object is null; update MDO and exit
1831 Register mdo = klass_RInfo;
1832 __ mov_metadata(mdo, md->constant_encoding());
1833 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1834 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1835 __ orl(data_addr, header_bits);
1836 __ jmp(done);
1837 __ bind(not_null);
1838 } else {
1839 __ jcc(Assembler::equal, done);
1840 }
1841
1842 add_debug_info_for_null_check_here(op->info_for_exception());
1843 __ load_klass(k_RInfo, array);
1844 __ load_klass(klass_RInfo, value);
1845
1846 // get instance klass (it's already uncompressed)
1847 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1848 // perform the fast part of the checking logic
1849 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1850 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1851 __ push(klass_RInfo);
1852 __ push(k_RInfo);
1853 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1854 __ pop(klass_RInfo);
1855 __ pop(k_RInfo);
1856 // result is a boolean
1857 __ cmpl(k_RInfo, 0);
1858 __ jcc(Assembler::equal, *failure_target);
1859 // fall through to the success case
1860
1861 if (op->should_profile()) {
1862 Register mdo = klass_RInfo, recv = k_RInfo;
1863 __ bind(profile_cast_success);
1864 __ mov_metadata(mdo, md->constant_encoding());
1865 __ load_klass(recv, value);
1866 Label update_done;
1867 type_profile_helper(mdo, md, data, recv, &done);
1868 __ jmpb(done);
1869
1870 __ bind(profile_cast_failure);
1871 __ mov_metadata(mdo, md->constant_encoding());
1872 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1873 __ subptr(counter_addr, DataLayout::counter_increment);
1874 __ jmp(*stub->entry());
1875 }
1876
1877 __ bind(done);
1878 } else
1879 if (code == lir_checkcast) {
1880 Register obj = op->object()->as_register();
1881 Register dst = op->result_opr()->as_register();
1882 Label success;
1883 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1884 __ bind(success);
1885 if (dst != obj) {
1886 __ mov(dst, obj);
1887 }
1888 } else
1889 if (code == lir_instanceof) {
1890 Register obj = op->object()->as_register();
1891 Register dst = op->result_opr()->as_register();
1892 Label success, failure, done;
1893 emit_typecheck_helper(op, &success, &failure, &failure);
1894 __ bind(failure);
1895 __ xorptr(dst, dst);
1896 __ jmpb(done);
1897 __ bind(success);
1898 __ movptr(dst, 1);
1899 __ bind(done);
1900 } else {
1901 ShouldNotReachHere();
1902 }
1903
1904 }
1905
1906
1907 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1908 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1909 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1910 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1911 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1912 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1913 Register addr = op->addr()->as_register();
1914 if (os::is_MP()) {
1915 __ lock();
1916 }
1917 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1918
1919 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1920 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1921 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1922 Register newval = op->new_value()->as_register();
1923 Register cmpval = op->cmp_value()->as_register();
1924 assert(cmpval == rax, "wrong register");
1925 assert(newval != NULL, "new val must be register");
1926 assert(cmpval != newval, "cmp and new values must be in different registers");
1927 assert(cmpval != addr, "cmp and addr must be in different registers");
1928 assert(newval != addr, "new value and addr must be in different registers");
1929
1930 if ( op->code() == lir_cas_obj) {
1931 #ifdef _LP64
1932 if (UseCompressedOops) {
1933 __ encode_heap_oop(cmpval);
1934 __ mov(rscratch1, newval);
1935 __ encode_heap_oop(rscratch1);
1936 if (os::is_MP()) {
1937 __ lock();
1938 }
1939 // cmpval (rax) is implicitly used by this instruction
1940 __ cmpxchgl(rscratch1, Address(addr, 0));
1941 } else
1942 #endif
1943 {
1944 if (os::is_MP()) {
1945 __ lock();
1946 }
1947 __ cmpxchgptr(newval, Address(addr, 0));
1948 }
1949 } else {
1950 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1951 if (os::is_MP()) {
1952 __ lock();
1953 }
1954 __ cmpxchgl(newval, Address(addr, 0));
1955 }
1956 #ifdef _LP64
1957 } else if (op->code() == lir_cas_long) {
1958 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1959 Register newval = op->new_value()->as_register_lo();
1960 Register cmpval = op->cmp_value()->as_register_lo();
1961 assert(cmpval == rax, "wrong register");
1962 assert(newval != NULL, "new val must be register");
1963 assert(cmpval != newval, "cmp and new values must be in different registers");
1964 assert(cmpval != addr, "cmp and addr must be in different registers");
1965 assert(newval != addr, "new value and addr must be in different registers");
1966 if (os::is_MP()) {
1967 __ lock();
1968 }
1969 __ cmpxchgq(newval, Address(addr, 0));
1970 #endif // _LP64
1971 } else {
1972 Unimplemented();
1973 }
1974 }
1975
1976 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1977 Assembler::Condition acond, ncond;
1978 switch (condition) {
1979 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1980 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1981 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1982 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1983 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1984 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1985 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1986 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1987 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1988 ShouldNotReachHere();
1989 }
1990
1991 if (opr1->is_cpu_register()) {
1992 reg2reg(opr1, result);
1993 } else if (opr1->is_stack()) {
1994 stack2reg(opr1, result, result->type());
1995 } else if (opr1->is_constant()) {
1996 const2reg(opr1, result, lir_patch_none, NULL);
1997 } else {
1998 ShouldNotReachHere();
1999 }
2000
2001 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2002 // optimized version that does not require a branch
2003 if (opr2->is_single_cpu()) {
2004 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2005 __ cmov(ncond, result->as_register(), opr2->as_register());
2006 } else if (opr2->is_double_cpu()) {
2007 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2008 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2009 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2011 } else if (opr2->is_single_stack()) {
2012 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2013 } else if (opr2->is_double_stack()) {
2014 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2015 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2016 } else {
2017 ShouldNotReachHere();
2018 }
2019
2020 } else {
2021 Label skip;
2022 __ jcc (acond, skip);
2023 if (opr2->is_cpu_register()) {
2024 reg2reg(opr2, result);
2025 } else if (opr2->is_stack()) {
2026 stack2reg(opr2, result, result->type());
2027 } else if (opr2->is_constant()) {
2028 const2reg(opr2, result, lir_patch_none, NULL);
2029 } else {
2030 ShouldNotReachHere();
2031 }
2032 __ bind(skip);
2033 }
2034 }
2035
2036
2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2038 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2039
2040 if (left->is_single_cpu()) {
2041 assert(left == dest, "left and dest must be equal");
2042 Register lreg = left->as_register();
2043
2044 if (right->is_single_cpu()) {
2045 // cpu register - cpu register
2046 Register rreg = right->as_register();
2047 switch (code) {
2048 case lir_add: __ addl (lreg, rreg); break;
2049 case lir_sub: __ subl (lreg, rreg); break;
2050 case lir_mul: __ imull(lreg, rreg); break;
2051 default: ShouldNotReachHere();
2052 }
2053
2054 } else if (right->is_stack()) {
2055 // cpu register - stack
2056 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2057 switch (code) {
2058 case lir_add: __ addl(lreg, raddr); break;
2059 case lir_sub: __ subl(lreg, raddr); break;
2060 default: ShouldNotReachHere();
2061 }
2062
2063 } else if (right->is_constant()) {
2064 // cpu register - constant
2065 jint c = right->as_constant_ptr()->as_jint();
2066 switch (code) {
2067 case lir_add: {
2068 __ incrementl(lreg, c);
2069 break;
2070 }
2071 case lir_sub: {
2072 __ decrementl(lreg, c);
2073 break;
2074 }
2075 default: ShouldNotReachHere();
2076 }
2077
2078 } else {
2079 ShouldNotReachHere();
2080 }
2081
2082 } else if (left->is_double_cpu()) {
2083 assert(left == dest, "left and dest must be equal");
2084 Register lreg_lo = left->as_register_lo();
2085 Register lreg_hi = left->as_register_hi();
2086
2087 if (right->is_double_cpu()) {
2088 // cpu register - cpu register
2089 Register rreg_lo = right->as_register_lo();
2090 Register rreg_hi = right->as_register_hi();
2091 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2092 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2093 switch (code) {
2094 case lir_add:
2095 __ addptr(lreg_lo, rreg_lo);
2096 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2097 break;
2098 case lir_sub:
2099 __ subptr(lreg_lo, rreg_lo);
2100 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2101 break;
2102 case lir_mul:
2103 #ifdef _LP64
2104 __ imulq(lreg_lo, rreg_lo);
2105 #else
2106 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2107 __ imull(lreg_hi, rreg_lo);
2108 __ imull(rreg_hi, lreg_lo);
2109 __ addl (rreg_hi, lreg_hi);
2110 __ mull (rreg_lo);
2111 __ addl (lreg_hi, rreg_hi);
2112 #endif // _LP64
2113 break;
2114 default:
2115 ShouldNotReachHere();
2116 }
2117
2118 } else if (right->is_constant()) {
2119 // cpu register - constant
2120 #ifdef _LP64
2121 jlong c = right->as_constant_ptr()->as_jlong_bits();
2122 __ movptr(r10, (intptr_t) c);
2123 switch (code) {
2124 case lir_add:
2125 __ addptr(lreg_lo, r10);
2126 break;
2127 case lir_sub:
2128 __ subptr(lreg_lo, r10);
2129 break;
2130 default:
2131 ShouldNotReachHere();
2132 }
2133 #else
2134 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2135 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2136 switch (code) {
2137 case lir_add:
2138 __ addptr(lreg_lo, c_lo);
2139 __ adcl(lreg_hi, c_hi);
2140 break;
2141 case lir_sub:
2142 __ subptr(lreg_lo, c_lo);
2143 __ sbbl(lreg_hi, c_hi);
2144 break;
2145 default:
2146 ShouldNotReachHere();
2147 }
2148 #endif // _LP64
2149
2150 } else {
2151 ShouldNotReachHere();
2152 }
2153
2154 } else if (left->is_single_xmm()) {
2155 assert(left == dest, "left and dest must be equal");
2156 XMMRegister lreg = left->as_xmm_float_reg();
2157
2158 if (right->is_single_xmm()) {
2159 XMMRegister rreg = right->as_xmm_float_reg();
2160 switch (code) {
2161 case lir_add: __ addss(lreg, rreg); break;
2162 case lir_sub: __ subss(lreg, rreg); break;
2163 case lir_mul_strictfp: // fall through
2164 case lir_mul: __ mulss(lreg, rreg); break;
2165 case lir_div_strictfp: // fall through
2166 case lir_div: __ divss(lreg, rreg); break;
2167 default: ShouldNotReachHere();
2168 }
2169 } else {
2170 Address raddr;
2171 if (right->is_single_stack()) {
2172 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2173 } else if (right->is_constant()) {
2174 // hack for now
2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2176 } else {
2177 ShouldNotReachHere();
2178 }
2179 switch (code) {
2180 case lir_add: __ addss(lreg, raddr); break;
2181 case lir_sub: __ subss(lreg, raddr); break;
2182 case lir_mul_strictfp: // fall through
2183 case lir_mul: __ mulss(lreg, raddr); break;
2184 case lir_div_strictfp: // fall through
2185 case lir_div: __ divss(lreg, raddr); break;
2186 default: ShouldNotReachHere();
2187 }
2188 }
2189
2190 } else if (left->is_double_xmm()) {
2191 assert(left == dest, "left and dest must be equal");
2192
2193 XMMRegister lreg = left->as_xmm_double_reg();
2194 if (right->is_double_xmm()) {
2195 XMMRegister rreg = right->as_xmm_double_reg();
2196 switch (code) {
2197 case lir_add: __ addsd(lreg, rreg); break;
2198 case lir_sub: __ subsd(lreg, rreg); break;
2199 case lir_mul_strictfp: // fall through
2200 case lir_mul: __ mulsd(lreg, rreg); break;
2201 case lir_div_strictfp: // fall through
2202 case lir_div: __ divsd(lreg, rreg); break;
2203 default: ShouldNotReachHere();
2204 }
2205 } else {
2206 Address raddr;
2207 if (right->is_double_stack()) {
2208 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2209 } else if (right->is_constant()) {
2210 // hack for now
2211 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2212 } else {
2213 ShouldNotReachHere();
2214 }
2215 switch (code) {
2216 case lir_add: __ addsd(lreg, raddr); break;
2217 case lir_sub: __ subsd(lreg, raddr); break;
2218 case lir_mul_strictfp: // fall through
2219 case lir_mul: __ mulsd(lreg, raddr); break;
2220 case lir_div_strictfp: // fall through
2221 case lir_div: __ divsd(lreg, raddr); break;
2222 default: ShouldNotReachHere();
2223 }
2224 }
2225
2226 } else if (left->is_single_fpu()) {
2227 assert(dest->is_single_fpu(), "fpu stack allocation required");
2228
2229 if (right->is_single_fpu()) {
2230 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2231
2232 } else {
2233 assert(left->fpu_regnr() == 0, "left must be on TOS");
2234 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2235
2236 Address raddr;
2237 if (right->is_single_stack()) {
2238 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2239 } else if (right->is_constant()) {
2240 address const_addr = float_constant(right->as_jfloat());
2241 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2242 // hack for now
2243 raddr = __ as_Address(InternalAddress(const_addr));
2244 } else {
2245 ShouldNotReachHere();
2246 }
2247
2248 switch (code) {
2249 case lir_add: __ fadd_s(raddr); break;
2250 case lir_sub: __ fsub_s(raddr); break;
2251 case lir_mul_strictfp: // fall through
2252 case lir_mul: __ fmul_s(raddr); break;
2253 case lir_div_strictfp: // fall through
2254 case lir_div: __ fdiv_s(raddr); break;
2255 default: ShouldNotReachHere();
2256 }
2257 }
2258
2259 } else if (left->is_double_fpu()) {
2260 assert(dest->is_double_fpu(), "fpu stack allocation required");
2261
2262 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2263 // Double values require special handling for strictfp mul/div on x86
2264 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2265 __ fmulp(left->fpu_regnrLo() + 1);
2266 }
2267
2268 if (right->is_double_fpu()) {
2269 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2270
2271 } else {
2272 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2273 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2274
2275 Address raddr;
2276 if (right->is_double_stack()) {
2277 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2278 } else if (right->is_constant()) {
2279 // hack for now
2280 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2281 } else {
2282 ShouldNotReachHere();
2283 }
2284
2285 switch (code) {
2286 case lir_add: __ fadd_d(raddr); break;
2287 case lir_sub: __ fsub_d(raddr); break;
2288 case lir_mul_strictfp: // fall through
2289 case lir_mul: __ fmul_d(raddr); break;
2290 case lir_div_strictfp: // fall through
2291 case lir_div: __ fdiv_d(raddr); break;
2292 default: ShouldNotReachHere();
2293 }
2294 }
2295
2296 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2297 // Double values require special handling for strictfp mul/div on x86
2298 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2299 __ fmulp(dest->fpu_regnrLo() + 1);
2300 }
2301
2302 } else if (left->is_single_stack() || left->is_address()) {
2303 assert(left == dest, "left and dest must be equal");
2304
2305 Address laddr;
2306 if (left->is_single_stack()) {
2307 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2308 } else if (left->is_address()) {
2309 laddr = as_Address(left->as_address_ptr());
2310 } else {
2311 ShouldNotReachHere();
2312 }
2313
2314 if (right->is_single_cpu()) {
2315 Register rreg = right->as_register();
2316 switch (code) {
2317 case lir_add: __ addl(laddr, rreg); break;
2318 case lir_sub: __ subl(laddr, rreg); break;
2319 default: ShouldNotReachHere();
2320 }
2321 } else if (right->is_constant()) {
2322 jint c = right->as_constant_ptr()->as_jint();
2323 switch (code) {
2324 case lir_add: {
2325 __ incrementl(laddr, c);
2326 break;
2327 }
2328 case lir_sub: {
2329 __ decrementl(laddr, c);
2330 break;
2331 }
2332 default: ShouldNotReachHere();
2333 }
2334 } else {
2335 ShouldNotReachHere();
2336 }
2337
2338 } else {
2339 ShouldNotReachHere();
2340 }
2341 }
2342
2343 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2344 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2345 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2346 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2347
2348 bool left_is_tos = (left_index == 0);
2349 bool dest_is_tos = (dest_index == 0);
2350 int non_tos_index = (left_is_tos ? right_index : left_index);
2351
2352 switch (code) {
2353 case lir_add:
2354 if (pop_fpu_stack) __ faddp(non_tos_index);
2355 else if (dest_is_tos) __ fadd (non_tos_index);
2356 else __ fadda(non_tos_index);
2357 break;
2358
2359 case lir_sub:
2360 if (left_is_tos) {
2361 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2362 else if (dest_is_tos) __ fsub (non_tos_index);
2363 else __ fsubra(non_tos_index);
2364 } else {
2365 if (pop_fpu_stack) __ fsubp (non_tos_index);
2366 else if (dest_is_tos) __ fsubr (non_tos_index);
2367 else __ fsuba (non_tos_index);
2368 }
2369 break;
2370
2371 case lir_mul_strictfp: // fall through
2372 case lir_mul:
2373 if (pop_fpu_stack) __ fmulp(non_tos_index);
2374 else if (dest_is_tos) __ fmul (non_tos_index);
2375 else __ fmula(non_tos_index);
2376 break;
2377
2378 case lir_div_strictfp: // fall through
2379 case lir_div:
2380 if (left_is_tos) {
2381 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2382 else if (dest_is_tos) __ fdiv (non_tos_index);
2383 else __ fdivra(non_tos_index);
2384 } else {
2385 if (pop_fpu_stack) __ fdivp (non_tos_index);
2386 else if (dest_is_tos) __ fdivr (non_tos_index);
2387 else __ fdiva (non_tos_index);
2388 }
2389 break;
2390
2391 case lir_rem:
2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2393 __ fremr(noreg);
2394 break;
2395
2396 default:
2397 ShouldNotReachHere();
2398 }
2399 }
2400
2401
2402 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2403 if (value->is_double_xmm()) {
2404 switch(code) {
2405 case lir_abs :
2406 {
2407 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2408 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2409 }
2410 __ andpd(dest->as_xmm_double_reg(),
2411 ExternalAddress((address)double_signmask_pool));
2412 }
2413 break;
2414
2415 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2416 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2417 default : ShouldNotReachHere();
2418 }
2419
2420 } else if (value->is_double_fpu()) {
2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2422 switch(code) {
2423 case lir_abs : __ fabs() ; break;
2424 case lir_sqrt : __ fsqrt(); break;
2425 default : ShouldNotReachHere();
2426 }
2427 } else {
2428 Unimplemented();
2429 }
2430 }
2431
2432 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2433 // assert(left->destroys_register(), "check");
2434 if (left->is_single_cpu()) {
2435 Register reg = left->as_register();
2436 if (right->is_constant()) {
2437 int val = right->as_constant_ptr()->as_jint();
2438 switch (code) {
2439 case lir_logic_and: __ andl (reg, val); break;
2440 case lir_logic_or: __ orl (reg, val); break;
2441 case lir_logic_xor: __ xorl (reg, val); break;
2442 default: ShouldNotReachHere();
2443 }
2444 } else if (right->is_stack()) {
2445 // added support for stack operands
2446 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2447 switch (code) {
2448 case lir_logic_and: __ andl (reg, raddr); break;
2449 case lir_logic_or: __ orl (reg, raddr); break;
2450 case lir_logic_xor: __ xorl (reg, raddr); break;
2451 default: ShouldNotReachHere();
2452 }
2453 } else {
2454 Register rright = right->as_register();
2455 switch (code) {
2456 case lir_logic_and: __ andptr (reg, rright); break;
2457 case lir_logic_or : __ orptr (reg, rright); break;
2458 case lir_logic_xor: __ xorptr (reg, rright); break;
2459 default: ShouldNotReachHere();
2460 }
2461 }
2462 move_regs(reg, dst->as_register());
2463 } else {
2464 Register l_lo = left->as_register_lo();
2465 Register l_hi = left->as_register_hi();
2466 if (right->is_constant()) {
2467 #ifdef _LP64
2468 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2469 switch (code) {
2470 case lir_logic_and:
2471 __ andq(l_lo, rscratch1);
2472 break;
2473 case lir_logic_or:
2474 __ orq(l_lo, rscratch1);
2475 break;
2476 case lir_logic_xor:
2477 __ xorq(l_lo, rscratch1);
2478 break;
2479 default: ShouldNotReachHere();
2480 }
2481 #else
2482 int r_lo = right->as_constant_ptr()->as_jint_lo();
2483 int r_hi = right->as_constant_ptr()->as_jint_hi();
2484 switch (code) {
2485 case lir_logic_and:
2486 __ andl(l_lo, r_lo);
2487 __ andl(l_hi, r_hi);
2488 break;
2489 case lir_logic_or:
2490 __ orl(l_lo, r_lo);
2491 __ orl(l_hi, r_hi);
2492 break;
2493 case lir_logic_xor:
2494 __ xorl(l_lo, r_lo);
2495 __ xorl(l_hi, r_hi);
2496 break;
2497 default: ShouldNotReachHere();
2498 }
2499 #endif // _LP64
2500 } else {
2501 #ifdef _LP64
2502 Register r_lo;
2503 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2504 r_lo = right->as_register();
2505 } else {
2506 r_lo = right->as_register_lo();
2507 }
2508 #else
2509 Register r_lo = right->as_register_lo();
2510 Register r_hi = right->as_register_hi();
2511 assert(l_lo != r_hi, "overwriting registers");
2512 #endif
2513 switch (code) {
2514 case lir_logic_and:
2515 __ andptr(l_lo, r_lo);
2516 NOT_LP64(__ andptr(l_hi, r_hi);)
2517 break;
2518 case lir_logic_or:
2519 __ orptr(l_lo, r_lo);
2520 NOT_LP64(__ orptr(l_hi, r_hi);)
2521 break;
2522 case lir_logic_xor:
2523 __ xorptr(l_lo, r_lo);
2524 NOT_LP64(__ xorptr(l_hi, r_hi);)
2525 break;
2526 default: ShouldNotReachHere();
2527 }
2528 }
2529
2530 Register dst_lo = dst->as_register_lo();
2531 Register dst_hi = dst->as_register_hi();
2532
2533 #ifdef _LP64
2534 move_regs(l_lo, dst_lo);
2535 #else
2536 if (dst_lo == l_hi) {
2537 assert(dst_hi != l_lo, "overwriting registers");
2538 move_regs(l_hi, dst_hi);
2539 move_regs(l_lo, dst_lo);
2540 } else {
2541 assert(dst_lo != l_hi, "overwriting registers");
2542 move_regs(l_lo, dst_lo);
2543 move_regs(l_hi, dst_hi);
2544 }
2545 #endif // _LP64
2546 }
2547 }
2548
2549
2550 // we assume that rax, and rdx can be overwritten
2551 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2552
2553 assert(left->is_single_cpu(), "left must be register");
2554 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2555 assert(result->is_single_cpu(), "result must be register");
2556
2557 // assert(left->destroys_register(), "check");
2558 // assert(right->destroys_register(), "check");
2559
2560 Register lreg = left->as_register();
2561 Register dreg = result->as_register();
2562
2563 if (right->is_constant()) {
2564 int divisor = right->as_constant_ptr()->as_jint();
2565 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2566 if (code == lir_idiv) {
2567 assert(lreg == rax, "must be rax,");
2568 assert(temp->as_register() == rdx, "tmp register must be rdx");
2569 __ cdql(); // sign extend into rdx:rax
2570 if (divisor == 2) {
2571 __ subl(lreg, rdx);
2572 } else {
2573 __ andl(rdx, divisor - 1);
2574 __ addl(lreg, rdx);
2575 }
2576 __ sarl(lreg, log2_intptr(divisor));
2577 move_regs(lreg, dreg);
2578 } else if (code == lir_irem) {
2579 Label done;
2580 __ mov(dreg, lreg);
2581 __ andl(dreg, 0x80000000 | (divisor - 1));
2582 __ jcc(Assembler::positive, done);
2583 __ decrement(dreg);
2584 __ orl(dreg, ~(divisor - 1));
2585 __ increment(dreg);
2586 __ bind(done);
2587 } else {
2588 ShouldNotReachHere();
2589 }
2590 } else {
2591 Register rreg = right->as_register();
2592 assert(lreg == rax, "left register must be rax,");
2593 assert(rreg != rdx, "right register must not be rdx");
2594 assert(temp->as_register() == rdx, "tmp register must be rdx");
2595
2596 move_regs(lreg, rax);
2597
2598 int idivl_offset = __ corrected_idivl(rreg);
2599 if (ImplicitDiv0Checks) {
2600 add_debug_info_for_div0(idivl_offset, info);
2601 }
2602 if (code == lir_irem) {
2603 move_regs(rdx, dreg); // result is in rdx
2604 } else {
2605 move_regs(rax, dreg);
2606 }
2607 }
2608 }
2609
2610
2611 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2612 if (opr1->is_single_cpu()) {
2613 Register reg1 = opr1->as_register();
2614 if (opr2->is_single_cpu()) {
2615 // cpu register - cpu register
2616 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2617 __ cmpoop(reg1, opr2->as_register());
2618 } else {
2619 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2620 __ cmpl(reg1, opr2->as_register());
2621 }
2622 } else if (opr2->is_stack()) {
2623 // cpu register - stack
2624 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2625 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2626 } else {
2627 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2628 }
2629 } else if (opr2->is_constant()) {
2630 // cpu register - constant
2631 LIR_Const* c = opr2->as_constant_ptr();
2632 if (c->type() == T_INT) {
2633 __ cmpl(reg1, c->as_jint());
2634 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2635 // In 64bit oops are single register
2636 jobject o = c->as_jobject();
2637 if (o == NULL) {
2638 __ cmpptr(reg1, (int32_t)NULL_WORD);
2639 } else {
2640 __ cmpoop(reg1, o);
2641 }
2642 } else {
2643 fatal("unexpected type: %s", basictype_to_str(c->type()));
2644 }
2645 // cpu register - address
2646 } else if (opr2->is_address()) {
2647 if (op->info() != NULL) {
2648 add_debug_info_for_null_check_here(op->info());
2649 }
2650 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2651 } else {
2652 ShouldNotReachHere();
2653 }
2654
2655 } else if(opr1->is_double_cpu()) {
2656 Register xlo = opr1->as_register_lo();
2657 Register xhi = opr1->as_register_hi();
2658 if (opr2->is_double_cpu()) {
2659 #ifdef _LP64
2660 __ cmpptr(xlo, opr2->as_register_lo());
2661 #else
2662 // cpu register - cpu register
2663 Register ylo = opr2->as_register_lo();
2664 Register yhi = opr2->as_register_hi();
2665 __ subl(xlo, ylo);
2666 __ sbbl(xhi, yhi);
2667 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2668 __ orl(xhi, xlo);
2669 }
2670 #endif // _LP64
2671 } else if (opr2->is_constant()) {
2672 // cpu register - constant 0
2673 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2674 #ifdef _LP64
2675 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2676 #else
2677 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2678 __ orl(xhi, xlo);
2679 #endif // _LP64
2680 } else {
2681 ShouldNotReachHere();
2682 }
2683
2684 } else if (opr1->is_single_xmm()) {
2685 XMMRegister reg1 = opr1->as_xmm_float_reg();
2686 if (opr2->is_single_xmm()) {
2687 // xmm register - xmm register
2688 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2689 } else if (opr2->is_stack()) {
2690 // xmm register - stack
2691 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2692 } else if (opr2->is_constant()) {
2693 // xmm register - constant
2694 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2695 } else if (opr2->is_address()) {
2696 // xmm register - address
2697 if (op->info() != NULL) {
2698 add_debug_info_for_null_check_here(op->info());
2699 }
2700 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2701 } else {
2702 ShouldNotReachHere();
2703 }
2704
2705 } else if (opr1->is_double_xmm()) {
2706 XMMRegister reg1 = opr1->as_xmm_double_reg();
2707 if (opr2->is_double_xmm()) {
2708 // xmm register - xmm register
2709 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2710 } else if (opr2->is_stack()) {
2711 // xmm register - stack
2712 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2713 } else if (opr2->is_constant()) {
2714 // xmm register - constant
2715 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2716 } else if (opr2->is_address()) {
2717 // xmm register - address
2718 if (op->info() != NULL) {
2719 add_debug_info_for_null_check_here(op->info());
2720 }
2721 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2722 } else {
2723 ShouldNotReachHere();
2724 }
2725
2726 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2727 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2728 assert(opr2->is_fpu_register(), "both must be registers");
2729 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2730
2731 } else if (opr1->is_address() && opr2->is_constant()) {
2732 LIR_Const* c = opr2->as_constant_ptr();
2733 #ifdef _LP64
2734 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2735 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2736 __ movoop(rscratch1, c->as_jobject());
2737 }
2738 #endif // LP64
2739 if (op->info() != NULL) {
2740 add_debug_info_for_null_check_here(op->info());
2741 }
2742 // special case: address - constant
2743 LIR_Address* addr = opr1->as_address_ptr();
2744 if (c->type() == T_INT) {
2745 __ cmpl(as_Address(addr), c->as_jint());
2746 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2747 #ifdef _LP64
2748 // %%% Make this explode if addr isn't reachable until we figure out a
2749 // better strategy by giving noreg as the temp for as_Address
2750 __ cmpoop(rscratch1, as_Address(addr, noreg));
2751 #else
2752 __ cmpoop(as_Address(addr), c->as_jobject());
2753 #endif // _LP64
2754 } else {
2755 ShouldNotReachHere();
2756 }
2757
2758 } else {
2759 ShouldNotReachHere();
2760 }
2761 }
2762
2763 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2764 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2765 if (left->is_single_xmm()) {
2766 assert(right->is_single_xmm(), "must match");
2767 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2768 } else if (left->is_double_xmm()) {
2769 assert(right->is_double_xmm(), "must match");
2770 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2771
2772 } else {
2773 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2774 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2775
2776 assert(left->fpu() == 0, "left must be on TOS");
2777 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2778 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2779 }
2780 } else {
2781 assert(code == lir_cmp_l2i, "check");
2782 #ifdef _LP64
2783 Label done;
2784 Register dest = dst->as_register();
2785 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2786 __ movl(dest, -1);
2787 __ jccb(Assembler::less, done);
2788 __ set_byte_if_not_zero(dest);
2789 __ movzbl(dest, dest);
2790 __ bind(done);
2791 #else
2792 __ lcmp2int(left->as_register_hi(),
2793 left->as_register_lo(),
2794 right->as_register_hi(),
2795 right->as_register_lo());
2796 move_regs(left->as_register_hi(), dst->as_register());
2797 #endif // _LP64
2798 }
2799 }
2800
2801
2802 void LIR_Assembler::align_call(LIR_Code code) {
2803 if (os::is_MP()) {
2804 // make sure that the displacement word of the call ends up word aligned
2805 int offset = __ offset();
2806 switch (code) {
2807 case lir_static_call:
2808 case lir_optvirtual_call:
2809 case lir_dynamic_call:
2810 offset += NativeCall::displacement_offset;
2811 break;
2812 case lir_icvirtual_call:
2813 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2814 break;
2815 case lir_virtual_call: // currently, sparc-specific for niagara
2816 default: ShouldNotReachHere();
2817 }
2818 __ align(BytesPerWord, offset);
2819 }
2820 }
2821
2822
2823 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2824 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2825 "must be aligned");
2826 __ call(AddressLiteral(op->addr(), rtype));
2827 add_call_info(code_offset(), op->info());
2828 }
2829
2830
2831 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2832 __ ic_call(op->addr());
2833 add_call_info(code_offset(), op->info());
2834 assert(!os::is_MP() ||
2835 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2836 "must be aligned");
2837 }
2838
2839
2840 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2841 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2842 ShouldNotReachHere();
2843 }
2844
2845
2846 void LIR_Assembler::emit_static_call_stub() {
2847 address call_pc = __ pc();
2848 address stub = __ start_a_stub(call_stub_size());
2849 if (stub == NULL) {
2850 bailout("static call stub overflow");
2851 return;
2852 }
2853
2854 int start = __ offset();
2855 if (os::is_MP()) {
2856 // make sure that the displacement word of the call ends up word aligned
2857 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2858 }
2859 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2860 __ mov_metadata(rbx, (Metadata*)NULL);
2861 // must be set to -1 at code generation time
2862 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2863 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2864 __ jump(RuntimeAddress(__ pc()));
2865
2866 if (UseAOT) {
2867 // Trampoline to aot code
2868 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2869 #ifdef _LP64
2870 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2871 #else
2872 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2873 #endif
2874 __ jmp(rax);
2875 }
2876 assert(__ offset() - start <= call_stub_size(), "stub too big");
2877 __ end_a_stub();
2878 }
2879
2880
2881 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2882 assert(exceptionOop->as_register() == rax, "must match");
2883 assert(exceptionPC->as_register() == rdx, "must match");
2884
2885 // exception object is not added to oop map by LinearScan
2886 // (LinearScan assumes that no oops are in fixed registers)
2887 info->add_register_oop(exceptionOop);
2888 Runtime1::StubID unwind_id;
2889
2890 // get current pc information
2891 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2892 int pc_for_athrow_offset = __ offset();
2893 InternalAddress pc_for_athrow(__ pc());
2894 __ lea(exceptionPC->as_register(), pc_for_athrow);
2895 add_call_info(pc_for_athrow_offset, info); // for exception handler
2896
2897 __ verify_not_null_oop(rax);
2898 // search an exception handler (rax: exception oop, rdx: throwing pc)
2899 if (compilation()->has_fpu_code()) {
2900 unwind_id = Runtime1::handle_exception_id;
2901 } else {
2902 unwind_id = Runtime1::handle_exception_nofpu_id;
2903 }
2904 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2905
2906 // enough room for two byte trap
2907 __ nop();
2908 }
2909
2910
2911 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2912 assert(exceptionOop->as_register() == rax, "must match");
2913
2914 __ jmp(_unwind_handler_entry);
2915 }
2916
2917
2918 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2919
2920 // optimized version for linear scan:
2921 // * count must be already in ECX (guaranteed by LinearScan)
2922 // * left and dest must be equal
2923 // * tmp must be unused
2924 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2925 assert(left == dest, "left and dest must be equal");
2926 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2927
2928 if (left->is_single_cpu()) {
2929 Register value = left->as_register();
2930 assert(value != SHIFT_count, "left cannot be ECX");
2931
2932 switch (code) {
2933 case lir_shl: __ shll(value); break;
2934 case lir_shr: __ sarl(value); break;
2935 case lir_ushr: __ shrl(value); break;
2936 default: ShouldNotReachHere();
2937 }
2938 } else if (left->is_double_cpu()) {
2939 Register lo = left->as_register_lo();
2940 Register hi = left->as_register_hi();
2941 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2942 #ifdef _LP64
2943 switch (code) {
2944 case lir_shl: __ shlptr(lo); break;
2945 case lir_shr: __ sarptr(lo); break;
2946 case lir_ushr: __ shrptr(lo); break;
2947 default: ShouldNotReachHere();
2948 }
2949 #else
2950
2951 switch (code) {
2952 case lir_shl: __ lshl(hi, lo); break;
2953 case lir_shr: __ lshr(hi, lo, true); break;
2954 case lir_ushr: __ lshr(hi, lo, false); break;
2955 default: ShouldNotReachHere();
2956 }
2957 #endif // LP64
2958 } else {
2959 ShouldNotReachHere();
2960 }
2961 }
2962
2963
2964 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2965 if (dest->is_single_cpu()) {
2966 // first move left into dest so that left is not destroyed by the shift
2967 Register value = dest->as_register();
2968 count = count & 0x1F; // Java spec
2969
2970 move_regs(left->as_register(), value);
2971 switch (code) {
2972 case lir_shl: __ shll(value, count); break;
2973 case lir_shr: __ sarl(value, count); break;
2974 case lir_ushr: __ shrl(value, count); break;
2975 default: ShouldNotReachHere();
2976 }
2977 } else if (dest->is_double_cpu()) {
2978 #ifndef _LP64
2979 Unimplemented();
2980 #else
2981 // first move left into dest so that left is not destroyed by the shift
2982 Register value = dest->as_register_lo();
2983 count = count & 0x1F; // Java spec
2984
2985 move_regs(left->as_register_lo(), value);
2986 switch (code) {
2987 case lir_shl: __ shlptr(value, count); break;
2988 case lir_shr: __ sarptr(value, count); break;
2989 case lir_ushr: __ shrptr(value, count); break;
2990 default: ShouldNotReachHere();
2991 }
2992 #endif // _LP64
2993 } else {
2994 ShouldNotReachHere();
2995 }
2996 }
2997
2998
2999 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3000 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3001 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3002 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3003 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3004 }
3005
3006
3007 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3008 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3009 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3010 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3011 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3012 }
3013
3014
3015 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3016 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3017 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3018 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3019 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3020 }
3021
3022
3023 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3024 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3025 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3026 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3027 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3028 }
3029
3030
3031 // This code replaces a call to arraycopy; no exception may
3032 // be thrown in this code, they must be thrown in the System.arraycopy
3033 // activation frame; we could save some checks if this would not be the case
3034 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3035 ciArrayKlass* default_type = op->expected_type();
3036 Register src = op->src()->as_register();
3037 Register dst = op->dst()->as_register();
3038 Register src_pos = op->src_pos()->as_register();
3039 Register dst_pos = op->dst_pos()->as_register();
3040 Register length = op->length()->as_register();
3041 Register tmp = op->tmp()->as_register();
3042
3043 CodeStub* stub = op->stub();
3044 int flags = op->flags();
3045 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3046 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3047
3048 // if we don't know anything, just go through the generic arraycopy
3049 if (default_type == NULL) {
3050 Label done;
3051 // save outgoing arguments on stack in case call to System.arraycopy is needed
3052 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3053 // for interpreter calling conventions. Now we have to do it in new style conventions.
3054 // For the moment until C1 gets the new register allocator I just force all the
3055 // args to the right place (except the register args) and then on the back side
3056 // reload the register args properly if we go slow path. Yuck
3057
3058 // These are proper for the calling convention
3059 store_parameter(length, 2);
3060 store_parameter(dst_pos, 1);
3061 store_parameter(dst, 0);
3062
3063 // these are just temporary placements until we need to reload
3064 store_parameter(src_pos, 3);
3065 store_parameter(src, 4);
3066 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3067
3068 address copyfunc_addr = StubRoutines::generic_arraycopy();
3069 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3070
3071 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3072 #ifdef _LP64
3073 // The arguments are in java calling convention so we can trivially shift them to C
3074 // convention
3075 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3076 __ mov(c_rarg0, j_rarg0);
3077 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3078 __ mov(c_rarg1, j_rarg1);
3079 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3080 __ mov(c_rarg2, j_rarg2);
3081 assert_different_registers(c_rarg3, j_rarg4);
3082 __ mov(c_rarg3, j_rarg3);
3083 #ifdef _WIN64
3084 // Allocate abi space for args but be sure to keep stack aligned
3085 __ subptr(rsp, 6*wordSize);
3086 store_parameter(j_rarg4, 4);
3087 #ifndef PRODUCT
3088 if (PrintC1Statistics) {
3089 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3090 }
3091 #endif
3092 __ call(RuntimeAddress(copyfunc_addr));
3093 __ addptr(rsp, 6*wordSize);
3094 #else
3095 __ mov(c_rarg4, j_rarg4);
3096 #ifndef PRODUCT
3097 if (PrintC1Statistics) {
3098 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3099 }
3100 #endif
3101 __ call(RuntimeAddress(copyfunc_addr));
3102 #endif // _WIN64
3103 #else
3104 __ push(length);
3105 __ push(dst_pos);
3106 __ push(dst);
3107 __ push(src_pos);
3108 __ push(src);
3109
3110 #ifndef PRODUCT
3111 if (PrintC1Statistics) {
3112 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3113 }
3114 #endif
3115 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3116
3117 #endif // _LP64
3118
3119 __ cmpl(rax, 0);
3120 __ jcc(Assembler::equal, *stub->continuation());
3121
3122 __ mov(tmp, rax);
3123 __ xorl(tmp, -1);
3124
3125 // Reload values from the stack so they are where the stub
3126 // expects them.
3127 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3128 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3129 __ movptr (length, Address(rsp, 2*BytesPerWord));
3130 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3131 __ movptr (src, Address(rsp, 4*BytesPerWord));
3132
3133 __ subl(length, tmp);
3134 __ addl(src_pos, tmp);
3135 __ addl(dst_pos, tmp);
3136 __ jmp(*stub->entry());
3137
3138 __ bind(*stub->continuation());
3139 return;
3140 }
3141
3142 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3143
3144 int elem_size = type2aelembytes(basic_type);
3145 Address::ScaleFactor scale;
3146
3147 switch (elem_size) {
3148 case 1 :
3149 scale = Address::times_1;
3150 break;
3151 case 2 :
3152 scale = Address::times_2;
3153 break;
3154 case 4 :
3155 scale = Address::times_4;
3156 break;
3157 case 8 :
3158 scale = Address::times_8;
3159 break;
3160 default:
3161 scale = Address::no_scale;
3162 ShouldNotReachHere();
3163 }
3164
3165 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3166 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3167 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3168 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3169
3170 // length and pos's are all sign extended at this point on 64bit
3171
3172 // test for NULL
3173 if (flags & LIR_OpArrayCopy::src_null_check) {
3174 __ testptr(src, src);
3175 __ jcc(Assembler::zero, *stub->entry());
3176 }
3177 if (flags & LIR_OpArrayCopy::dst_null_check) {
3178 __ testptr(dst, dst);
3179 __ jcc(Assembler::zero, *stub->entry());
3180 }
3181
3182 // If the compiler was not able to prove that exact type of the source or the destination
3183 // of the arraycopy is an array type, check at runtime if the source or the destination is
3184 // an instance type.
3185 if (flags & LIR_OpArrayCopy::type_check) {
3186 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3187 __ load_klass(tmp, dst);
3188 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3189 __ jcc(Assembler::greaterEqual, *stub->entry());
3190 }
3191
3192 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3193 __ load_klass(tmp, src);
3194 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3195 __ jcc(Assembler::greaterEqual, *stub->entry());
3196 }
3197 }
3198
3199 // check if negative
3200 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3201 __ testl(src_pos, src_pos);
3202 __ jcc(Assembler::less, *stub->entry());
3203 }
3204 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3205 __ testl(dst_pos, dst_pos);
3206 __ jcc(Assembler::less, *stub->entry());
3207 }
3208
3209 if (flags & LIR_OpArrayCopy::src_range_check) {
3210 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3211 __ cmpl(tmp, src_length_addr);
3212 __ jcc(Assembler::above, *stub->entry());
3213 }
3214 if (flags & LIR_OpArrayCopy::dst_range_check) {
3215 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3216 __ cmpl(tmp, dst_length_addr);
3217 __ jcc(Assembler::above, *stub->entry());
3218 }
3219
3220 if (flags & LIR_OpArrayCopy::length_positive_check) {
3221 __ testl(length, length);
3222 __ jcc(Assembler::less, *stub->entry());
3223 }
3224
3225 #ifdef _LP64
3226 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3227 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3228 #endif
3229
3230 if (flags & LIR_OpArrayCopy::type_check) {
3231 // We don't know the array types are compatible
3232 if (basic_type != T_OBJECT) {
3233 // Simple test for basic type arrays
3234 if (UseCompressedClassPointers) {
3235 __ movl(tmp, src_klass_addr);
3236 __ cmpl(tmp, dst_klass_addr);
3237 } else {
3238 __ movptr(tmp, src_klass_addr);
3239 __ cmpptr(tmp, dst_klass_addr);
3240 }
3241 __ jcc(Assembler::notEqual, *stub->entry());
3242 } else {
3243 // For object arrays, if src is a sub class of dst then we can
3244 // safely do the copy.
3245 Label cont, slow;
3246
3247 __ push(src);
3248 __ push(dst);
3249
3250 __ load_klass(src, src);
3251 __ load_klass(dst, dst);
3252
3253 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3254
3255 __ push(src);
3256 __ push(dst);
3257 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3258 __ pop(dst);
3259 __ pop(src);
3260
3261 __ cmpl(src, 0);
3262 __ jcc(Assembler::notEqual, cont);
3263
3264 __ bind(slow);
3265 __ pop(dst);
3266 __ pop(src);
3267
3268 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3269 if (copyfunc_addr != NULL) { // use stub if available
3270 // src is not a sub class of dst so we have to do a
3271 // per-element check.
3272
3273 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3274 if ((flags & mask) != mask) {
3275 // Check that at least both of them object arrays.
3276 assert(flags & mask, "one of the two should be known to be an object array");
3277
3278 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3279 __ load_klass(tmp, src);
3280 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3281 __ load_klass(tmp, dst);
3282 }
3283 int lh_offset = in_bytes(Klass::layout_helper_offset());
3284 Address klass_lh_addr(tmp, lh_offset);
3285 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3286 __ cmpl(klass_lh_addr, objArray_lh);
3287 __ jcc(Assembler::notEqual, *stub->entry());
3288 }
3289
3290 // Spill because stubs can use any register they like and it's
3291 // easier to restore just those that we care about.
3292 store_parameter(dst, 0);
3293 store_parameter(dst_pos, 1);
3294 store_parameter(length, 2);
3295 store_parameter(src_pos, 3);
3296 store_parameter(src, 4);
3297
3298 #ifndef _LP64
3299 __ movptr(tmp, dst_klass_addr);
3300 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3301 __ push(tmp);
3302 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3303 __ push(tmp);
3304 __ push(length);
3305 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3306 __ push(tmp);
3307 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3308 __ push(tmp);
3309
3310 __ call_VM_leaf(copyfunc_addr, 5);
3311 #else
3312 __ movl2ptr(length, length); //higher 32bits must be null
3313
3314 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3315 assert_different_registers(c_rarg0, dst, dst_pos, length);
3316 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3317 assert_different_registers(c_rarg1, dst, length);
3318
3319 __ mov(c_rarg2, length);
3320 assert_different_registers(c_rarg2, dst);
3321
3322 #ifdef _WIN64
3323 // Allocate abi space for args but be sure to keep stack aligned
3324 __ subptr(rsp, 6*wordSize);
3325 __ load_klass(c_rarg3, dst);
3326 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3327 store_parameter(c_rarg3, 4);
3328 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3329 __ call(RuntimeAddress(copyfunc_addr));
3330 __ addptr(rsp, 6*wordSize);
3331 #else
3332 __ load_klass(c_rarg4, dst);
3333 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3334 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3335 __ call(RuntimeAddress(copyfunc_addr));
3336 #endif
3337
3338 #endif
3339
3340 #ifndef PRODUCT
3341 if (PrintC1Statistics) {
3342 Label failed;
3343 __ testl(rax, rax);
3344 __ jcc(Assembler::notZero, failed);
3345 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3346 __ bind(failed);
3347 }
3348 #endif
3349
3350 __ testl(rax, rax);
3351 __ jcc(Assembler::zero, *stub->continuation());
3352
3353 #ifndef PRODUCT
3354 if (PrintC1Statistics) {
3355 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3356 }
3357 #endif
3358
3359 __ mov(tmp, rax);
3360
3361 __ xorl(tmp, -1);
3362
3363 // Restore previously spilled arguments
3364 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3365 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3366 __ movptr (length, Address(rsp, 2*BytesPerWord));
3367 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3368 __ movptr (src, Address(rsp, 4*BytesPerWord));
3369
3370
3371 __ subl(length, tmp);
3372 __ addl(src_pos, tmp);
3373 __ addl(dst_pos, tmp);
3374 }
3375
3376 __ jmp(*stub->entry());
3377
3378 __ bind(cont);
3379 __ pop(dst);
3380 __ pop(src);
3381 }
3382 }
3383
3384 #ifdef ASSERT
3385 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3386 // Sanity check the known type with the incoming class. For the
3387 // primitive case the types must match exactly with src.klass and
3388 // dst.klass each exactly matching the default type. For the
3389 // object array case, if no type check is needed then either the
3390 // dst type is exactly the expected type and the src type is a
3391 // subtype which we can't check or src is the same array as dst
3392 // but not necessarily exactly of type default_type.
3393 Label known_ok, halt;
3394 __ mov_metadata(tmp, default_type->constant_encoding());
3395 #ifdef _LP64
3396 if (UseCompressedClassPointers) {
3397 __ encode_klass_not_null(tmp);
3398 }
3399 #endif
3400
3401 if (basic_type != T_OBJECT) {
3402
3403 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3404 else __ cmpptr(tmp, dst_klass_addr);
3405 __ jcc(Assembler::notEqual, halt);
3406 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3407 else __ cmpptr(tmp, src_klass_addr);
3408 __ jcc(Assembler::equal, known_ok);
3409 } else {
3410 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3411 else __ cmpptr(tmp, dst_klass_addr);
3412 __ jcc(Assembler::equal, known_ok);
3413 __ cmpptr(src, dst);
3414 __ jcc(Assembler::equal, known_ok);
3415 }
3416 __ bind(halt);
3417 __ stop("incorrect type information in arraycopy");
3418 __ bind(known_ok);
3419 }
3420 #endif
3421
3422 #ifndef PRODUCT
3423 if (PrintC1Statistics) {
3424 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3425 }
3426 #endif
3427
3428 #ifdef _LP64
3429 assert_different_registers(c_rarg0, dst, dst_pos, length);
3430 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3431 assert_different_registers(c_rarg1, length);
3432 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3433 __ mov(c_rarg2, length);
3434
3435 #else
3436 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3437 store_parameter(tmp, 0);
3438 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3439 store_parameter(tmp, 1);
3440 store_parameter(length, 2);
3441 #endif // _LP64
3442
3443 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3444 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3445 const char *name;
3446 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3447 __ call_VM_leaf(entry, 0);
3448
3449 __ bind(*stub->continuation());
3450 }
3451
3452 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3453 assert(op->crc()->is_single_cpu(), "crc must be register");
3454 assert(op->val()->is_single_cpu(), "byte value must be register");
3455 assert(op->result_opr()->is_single_cpu(), "result must be register");
3456 Register crc = op->crc()->as_register();
3457 Register val = op->val()->as_register();
3458 Register res = op->result_opr()->as_register();
3459
3460 assert_different_registers(val, crc, res);
3461
3462 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3463 __ notl(crc); // ~crc
3464 __ update_byte_crc32(crc, val, res);
3465 __ notl(crc); // ~crc
3466 __ mov(res, crc);
3467 }
3468
3469 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3470 Register obj = op->obj_opr()->as_register(); // may not be an oop
3471 Register hdr = op->hdr_opr()->as_register();
3472 Register lock = op->lock_opr()->as_register();
3473 if (!UseFastLocking) {
3474 __ jmp(*op->stub()->entry());
3475 } else if (op->code() == lir_lock) {
3476 Register scratch = noreg;
3477 if (UseBiasedLocking) {
3478 scratch = op->scratch_opr()->as_register();
3479 }
3480 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3481 // add debug info for NullPointerException only if one is possible
3482 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3483 if (op->info() != NULL) {
3484 add_debug_info_for_null_check(null_check_offset, op->info());
3485 }
3486 // done
3487 } else if (op->code() == lir_unlock) {
3488 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3489 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3490 } else {
3491 Unimplemented();
3492 }
3493 __ bind(*op->stub()->continuation());
3494 }
3495
3496
3497 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3498 ciMethod* method = op->profiled_method();
3499 int bci = op->profiled_bci();
3500 ciMethod* callee = op->profiled_callee();
3501
3502 // Update counter for all call types
3503 ciMethodData* md = method->method_data_or_null();
3504 assert(md != NULL, "Sanity");
3505 ciProfileData* data = md->bci_to_data(bci);
3506 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3507 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3508 Register mdo = op->mdo()->as_register();
3509 __ mov_metadata(mdo, md->constant_encoding());
3510 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3511 // Perform additional virtual call profiling for invokevirtual and
3512 // invokeinterface bytecodes
3513 if (op->should_profile_receiver_type()) {
3514 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3515 Register recv = op->recv()->as_register();
3516 assert_different_registers(mdo, recv);
3517 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3518 ciKlass* known_klass = op->known_holder();
3519 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3520 // We know the type that will be seen at this call site; we can
3521 // statically update the MethodData* rather than needing to do
3522 // dynamic tests on the receiver type
3523
3524 // NOTE: we should probably put a lock around this search to
3525 // avoid collisions by concurrent compilations
3526 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3527 uint i;
3528 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3529 ciKlass* receiver = vc_data->receiver(i);
3530 if (known_klass->equals(receiver)) {
3531 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3532 __ addptr(data_addr, DataLayout::counter_increment);
3533 return;
3534 }
3535 }
3536
3537 // Receiver type not found in profile data; select an empty slot
3538
3539 // Note that this is less efficient than it should be because it
3540 // always does a write to the receiver part of the
3541 // VirtualCallData rather than just the first time
3542 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3543 ciKlass* receiver = vc_data->receiver(i);
3544 if (receiver == NULL) {
3545 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3546 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3547 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3548 __ addptr(data_addr, DataLayout::counter_increment);
3549 return;
3550 }
3551 }
3552 } else {
3553 __ load_klass(recv, recv);
3554 Label update_done;
3555 type_profile_helper(mdo, md, data, recv, &update_done);
3556 // Receiver did not match any saved receiver and there is no empty row for it.
3557 // Increment total counter to indicate polymorphic case.
3558 __ addptr(counter_addr, DataLayout::counter_increment);
3559
3560 __ bind(update_done);
3561 }
3562 } else {
3563 // Static call
3564 __ addptr(counter_addr, DataLayout::counter_increment);
3565 }
3566 }
3567
3568 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3569 Register obj = op->obj()->as_register();
3570 Register tmp = op->tmp()->as_pointer_register();
3571 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3572 ciKlass* exact_klass = op->exact_klass();
3573 intptr_t current_klass = op->current_klass();
3574 bool not_null = op->not_null();
3575 bool no_conflict = op->no_conflict();
3576
3577 Label update, next, none;
3578
3579 bool do_null = !not_null;
3580 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3581 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3582
3583 assert(do_null || do_update, "why are we here?");
3584 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3585
3586 __ verify_oop(obj);
3587
3588 if (tmp != obj) {
3589 __ mov(tmp, obj);
3590 }
3591 if (do_null) {
3592 __ testptr(tmp, tmp);
3593 __ jccb(Assembler::notZero, update);
3594 if (!TypeEntries::was_null_seen(current_klass)) {
3595 __ orptr(mdo_addr, TypeEntries::null_seen);
3596 }
3597 if (do_update) {
3598 #ifndef ASSERT
3599 __ jmpb(next);
3600 }
3601 #else
3602 __ jmp(next);
3603 }
3604 } else {
3605 __ testptr(tmp, tmp);
3606 __ jccb(Assembler::notZero, update);
3607 __ stop("unexpect null obj");
3608 #endif
3609 }
3610
3611 __ bind(update);
3612
3613 if (do_update) {
3614 #ifdef ASSERT
3615 if (exact_klass != NULL) {
3616 Label ok;
3617 __ load_klass(tmp, tmp);
3618 __ push(tmp);
3619 __ mov_metadata(tmp, exact_klass->constant_encoding());
3620 __ cmpptr(tmp, Address(rsp, 0));
3621 __ jccb(Assembler::equal, ok);
3622 __ stop("exact klass and actual klass differ");
3623 __ bind(ok);
3624 __ pop(tmp);
3625 }
3626 #endif
3627 if (!no_conflict) {
3628 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3629 if (exact_klass != NULL) {
3630 __ mov_metadata(tmp, exact_klass->constant_encoding());
3631 } else {
3632 __ load_klass(tmp, tmp);
3633 }
3634
3635 __ xorptr(tmp, mdo_addr);
3636 __ testptr(tmp, TypeEntries::type_klass_mask);
3637 // klass seen before, nothing to do. The unknown bit may have been
3638 // set already but no need to check.
3639 __ jccb(Assembler::zero, next);
3640
3641 __ testptr(tmp, TypeEntries::type_unknown);
3642 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3643
3644 if (TypeEntries::is_type_none(current_klass)) {
3645 __ cmpptr(mdo_addr, 0);
3646 __ jccb(Assembler::equal, none);
3647 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3648 __ jccb(Assembler::equal, none);
3649 // There is a chance that the checks above (re-reading profiling
3650 // data from memory) fail if another thread has just set the
3651 // profiling to this obj's klass
3652 __ xorptr(tmp, mdo_addr);
3653 __ testptr(tmp, TypeEntries::type_klass_mask);
3654 __ jccb(Assembler::zero, next);
3655 }
3656 } else {
3657 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3658 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3659
3660 __ movptr(tmp, mdo_addr);
3661 __ testptr(tmp, TypeEntries::type_unknown);
3662 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3663 }
3664
3665 // different than before. Cannot keep accurate profile.
3666 __ orptr(mdo_addr, TypeEntries::type_unknown);
3667
3668 if (TypeEntries::is_type_none(current_klass)) {
3669 __ jmpb(next);
3670
3671 __ bind(none);
3672 // first time here. Set profile type.
3673 __ movptr(mdo_addr, tmp);
3674 }
3675 } else {
3676 // There's a single possible klass at this profile point
3677 assert(exact_klass != NULL, "should be");
3678 if (TypeEntries::is_type_none(current_klass)) {
3679 __ mov_metadata(tmp, exact_klass->constant_encoding());
3680 __ xorptr(tmp, mdo_addr);
3681 __ testptr(tmp, TypeEntries::type_klass_mask);
3682 #ifdef ASSERT
3683 __ jcc(Assembler::zero, next);
3684
3685 {
3686 Label ok;
3687 __ push(tmp);
3688 __ cmpptr(mdo_addr, 0);
3689 __ jcc(Assembler::equal, ok);
3690 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3691 __ jcc(Assembler::equal, ok);
3692 // may have been set by another thread
3693 __ mov_metadata(tmp, exact_klass->constant_encoding());
3694 __ xorptr(tmp, mdo_addr);
3695 __ testptr(tmp, TypeEntries::type_mask);
3696 __ jcc(Assembler::zero, ok);
3697
3698 __ stop("unexpected profiling mismatch");
3699 __ bind(ok);
3700 __ pop(tmp);
3701 }
3702 #else
3703 __ jccb(Assembler::zero, next);
3704 #endif
3705 // first time here. Set profile type.
3706 __ movptr(mdo_addr, tmp);
3707 } else {
3708 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3709 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3710
3711 __ movptr(tmp, mdo_addr);
3712 __ testptr(tmp, TypeEntries::type_unknown);
3713 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3714
3715 __ orptr(mdo_addr, TypeEntries::type_unknown);
3716 }
3717 }
3718
3719 __ bind(next);
3720 }
3721 }
3722
3723 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3724 Unimplemented();
3725 }
3726
3727
3728 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3729 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3730 }
3731
3732
3733 void LIR_Assembler::align_backward_branch_target() {
3734 __ align(BytesPerWord);
3735 }
3736
3737
3738 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3739 if (left->is_single_cpu()) {
3740 __ negl(left->as_register());
3741 move_regs(left->as_register(), dest->as_register());
3742
3743 } else if (left->is_double_cpu()) {
3744 Register lo = left->as_register_lo();
3745 #ifdef _LP64
3746 Register dst = dest->as_register_lo();
3747 __ movptr(dst, lo);
3748 __ negptr(dst);
3749 #else
3750 Register hi = left->as_register_hi();
3751 __ lneg(hi, lo);
3752 if (dest->as_register_lo() == hi) {
3753 assert(dest->as_register_hi() != lo, "destroying register");
3754 move_regs(hi, dest->as_register_hi());
3755 move_regs(lo, dest->as_register_lo());
3756 } else {
3757 move_regs(lo, dest->as_register_lo());
3758 move_regs(hi, dest->as_register_hi());
3759 }
3760 #endif // _LP64
3761
3762 } else if (dest->is_single_xmm()) {
3763 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3764 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3765 }
3766 if (UseAVX > 0) {
3767 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3768 ExternalAddress((address)float_signflip_pool));
3769 } else {
3770 __ xorps(dest->as_xmm_float_reg(),
3771 ExternalAddress((address)float_signflip_pool));
3772 }
3773 } else if (dest->is_double_xmm()) {
3774 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3775 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3776 }
3777 if (UseAVX > 0) {
3778 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3779 ExternalAddress((address)double_signflip_pool));
3780 } else {
3781 __ xorpd(dest->as_xmm_double_reg(),
3782 ExternalAddress((address)double_signflip_pool));
3783 }
3784 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3785 assert(left->fpu() == 0, "arg must be on TOS");
3786 assert(dest->fpu() == 0, "dest must be TOS");
3787 __ fchs();
3788
3789 } else {
3790 ShouldNotReachHere();
3791 }
3792 }
3793
3794
3795 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3796 assert(src->is_address(), "must be an address");
3797 assert(dest->is_register(), "must be a register");
3798
3799 PatchingStub* patch = NULL;
3800 if (patch_code != lir_patch_none) {
3801 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3802 }
3803
3804 Register reg = dest->as_pointer_register();
3805 LIR_Address* addr = src->as_address_ptr();
3806 __ lea(reg, as_Address(addr));
3807
3808 if (patch != NULL) {
3809 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3810 }
3811 }
3812
3813
3814
3815 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3816 assert(!tmp->is_valid(), "don't need temporary");
3817 __ call(RuntimeAddress(dest));
3818 if (info != NULL) {
3819 add_call_info_here(info);
3820 }
3821 }
3822
3823
3824 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3825 assert(type == T_LONG, "only for volatile long fields");
3826
3827 if (info != NULL) {
3828 add_debug_info_for_null_check_here(info);
3829 }
3830
3831 if (src->is_double_xmm()) {
3832 if (dest->is_double_cpu()) {
3833 #ifdef _LP64
3834 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3835 #else
3836 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3837 __ psrlq(src->as_xmm_double_reg(), 32);
3838 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3839 #endif // _LP64
3840 } else if (dest->is_double_stack()) {
3841 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3842 } else if (dest->is_address()) {
3843 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3844 } else {
3845 ShouldNotReachHere();
3846 }
3847
3848 } else if (dest->is_double_xmm()) {
3849 if (src->is_double_stack()) {
3850 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3851 } else if (src->is_address()) {
3852 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3853 } else {
3854 ShouldNotReachHere();
3855 }
3856
3857 } else if (src->is_double_fpu()) {
3858 assert(src->fpu_regnrLo() == 0, "must be TOS");
3859 if (dest->is_double_stack()) {
3860 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3861 } else if (dest->is_address()) {
3862 __ fistp_d(as_Address(dest->as_address_ptr()));
3863 } else {
3864 ShouldNotReachHere();
3865 }
3866
3867 } else if (dest->is_double_fpu()) {
3868 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3869 if (src->is_double_stack()) {
3870 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3871 } else if (src->is_address()) {
3872 __ fild_d(as_Address(src->as_address_ptr()));
3873 } else {
3874 ShouldNotReachHere();
3875 }
3876 } else {
3877 ShouldNotReachHere();
3878 }
3879 }
3880
3881 #ifdef ASSERT
3882 // emit run-time assertion
3883 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3884 assert(op->code() == lir_assert, "must be");
3885
3886 if (op->in_opr1()->is_valid()) {
3887 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3888 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3889 } else {
3890 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3891 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3892 }
3893
3894 Label ok;
3895 if (op->condition() != lir_cond_always) {
3896 Assembler::Condition acond = Assembler::zero;
3897 switch (op->condition()) {
3898 case lir_cond_equal: acond = Assembler::equal; break;
3899 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3900 case lir_cond_less: acond = Assembler::less; break;
3901 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3902 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3903 case lir_cond_greater: acond = Assembler::greater; break;
3904 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3905 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3906 default: ShouldNotReachHere();
3907 }
3908 __ jcc(acond, ok);
3909 }
3910 if (op->halt()) {
3911 const char* str = __ code_string(op->msg());
3912 __ stop(str);
3913 } else {
3914 breakpoint();
3915 }
3916 __ bind(ok);
3917 }
3918 #endif
3919
3920 void LIR_Assembler::membar() {
3921 // QQQ sparc TSO uses this,
3922 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3923 }
3924
3925 void LIR_Assembler::membar_acquire() {
3926 // No x86 machines currently require load fences
3927 }
3928
3929 void LIR_Assembler::membar_release() {
3930 // No x86 machines currently require store fences
3931 }
3932
3933 void LIR_Assembler::membar_loadload() {
3934 // no-op
3935 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3936 }
3937
3938 void LIR_Assembler::membar_storestore() {
3939 // no-op
3940 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3941 }
3942
3943 void LIR_Assembler::membar_loadstore() {
3944 // no-op
3945 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3946 }
3947
3948 void LIR_Assembler::membar_storeload() {
3949 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3950 }
3951
3952 void LIR_Assembler::on_spin_wait() {
3953 __ pause ();
3954 }
3955
3956 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3957 assert(result_reg->is_register(), "check");
3958 #ifdef _LP64
3959 // __ get_thread(result_reg->as_register_lo());
3960 __ mov(result_reg->as_register(), r15_thread);
3961 #else
3962 __ get_thread(result_reg->as_register());
3963 #endif // _LP64
3964 }
3965
3966
3967 void LIR_Assembler::peephole(LIR_List*) {
3968 // do nothing for now
3969 }
3970
3971 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3972 assert(data == dest, "xchg/xadd uses only 2 operands");
3973
3974 if (data->type() == T_INT) {
3975 if (code == lir_xadd) {
3976 if (os::is_MP()) {
3977 __ lock();
3978 }
3979 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3980 } else {
3981 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3982 }
3983 } else if (data->is_oop()) {
3984 assert (code == lir_xchg, "xadd for oops");
3985 Register obj = data->as_register();
3986 #ifdef _LP64
3987 if (UseCompressedOops) {
3988 __ encode_heap_oop(obj);
3989 __ xchgl(obj, as_Address(src->as_address_ptr()));
3990 __ decode_heap_oop(obj);
3991 } else {
3992 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3993 }
3994 #else
3995 __ xchgl(obj, as_Address(src->as_address_ptr()));
3996 #endif
3997 } else if (data->type() == T_LONG) {
3998 #ifdef _LP64
3999 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4000 if (code == lir_xadd) {
4001 if (os::is_MP()) {
4002 __ lock();
4003 }
4004 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4005 } else {
4006 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4007 }
4008 #else
4009 ShouldNotReachHere();
4010 #endif
4011 } else {
4012 ShouldNotReachHere();
4013 }
4014 }
4015
4016 #undef __