1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableBarrierSet.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/frame.inline.hpp" 41 #include "runtime/safepointMechanism.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 #include "vmreg_x86.inline.hpp" 44 45 46 // These masks are used to provide 128-bit aligned bitmasks to the XMM 47 // instructions, to allow sign-masking or sign-bit flipping. They allow 48 // fast versions of NegF/NegD and AbsF/AbsD. 49 50 // Note: 'double' and 'long long' have 32-bits alignment on x86. 51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 53 // of 128-bits operands for SSE instructions. 54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 55 // Store the value to a 128-bits operand. 56 operand[0] = lo; 57 operand[1] = hi; 58 return operand; 59 } 60 61 // Buffer for 128-bits masks used by SSE instructions. 62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 63 64 // Static initialization during VM startup. 65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 69 70 71 72 NEEDS_CLEANUP // remove this definitions ? 73 const Register IC_Klass = rax; // where the IC klass is cached 74 const Register SYNC_header = rax; // synchronization header 75 const Register SHIFT_count = rcx; // where count for shift operations must be 76 77 #define __ _masm-> 78 79 80 static void select_different_registers(Register preserve, 81 Register extra, 82 Register &tmp1, 83 Register &tmp2) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, extra); 89 tmp2 = extra; 90 } 91 assert_different_registers(preserve, tmp1, tmp2); 92 } 93 94 95 96 static void select_different_registers(Register preserve, 97 Register extra, 98 Register &tmp1, 99 Register &tmp2, 100 Register &tmp3) { 101 if (tmp1 == preserve) { 102 assert_different_registers(tmp1, tmp2, tmp3, extra); 103 tmp1 = extra; 104 } else if (tmp2 == preserve) { 105 assert_different_registers(tmp1, tmp2, tmp3, extra); 106 tmp2 = extra; 107 } else if (tmp3 == preserve) { 108 assert_different_registers(tmp1, tmp2, tmp3, extra); 109 tmp3 = extra; 110 } 111 assert_different_registers(preserve, tmp1, tmp2, tmp3); 112 } 113 114 115 116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 117 if (opr->is_constant()) { 118 LIR_Const* constant = opr->as_constant_ptr(); 119 switch (constant->type()) { 120 case T_INT: { 121 return true; 122 } 123 124 default: 125 return false; 126 } 127 } 128 return false; 129 } 130 131 132 LIR_Opr LIR_Assembler::receiverOpr() { 133 return FrameMap::receiver_opr; 134 } 135 136 LIR_Opr LIR_Assembler::osrBufferPointer() { 137 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 138 } 139 140 //--------------fpu register translations----------------------- 141 142 143 address LIR_Assembler::float_constant(float f) { 144 address const_addr = __ float_constant(f); 145 if (const_addr == NULL) { 146 bailout("const section overflow"); 147 return __ code()->consts()->start(); 148 } else { 149 return const_addr; 150 } 151 } 152 153 154 address LIR_Assembler::double_constant(double d) { 155 address const_addr = __ double_constant(d); 156 if (const_addr == NULL) { 157 bailout("const section overflow"); 158 return __ code()->consts()->start(); 159 } else { 160 return const_addr; 161 } 162 } 163 164 165 void LIR_Assembler::set_24bit_FPU() { 166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 167 } 168 169 void LIR_Assembler::reset_FPU() { 170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 171 } 172 173 void LIR_Assembler::fpop() { 174 __ fpop(); 175 } 176 177 void LIR_Assembler::fxch(int i) { 178 __ fxch(i); 179 } 180 181 void LIR_Assembler::fld(int i) { 182 __ fld_s(i); 183 } 184 185 void LIR_Assembler::ffree(int i) { 186 __ ffree(i); 187 } 188 189 void LIR_Assembler::breakpoint() { 190 __ int3(); 191 } 192 193 void LIR_Assembler::push(LIR_Opr opr) { 194 if (opr->is_single_cpu()) { 195 __ push_reg(opr->as_register()); 196 } else if (opr->is_double_cpu()) { 197 NOT_LP64(__ push_reg(opr->as_register_hi())); 198 __ push_reg(opr->as_register_lo()); 199 } else if (opr->is_stack()) { 200 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 201 } else if (opr->is_constant()) { 202 LIR_Const* const_opr = opr->as_constant_ptr(); 203 if (const_opr->type() == T_OBJECT) { 204 __ push_oop(const_opr->as_jobject()); 205 } else if (const_opr->type() == T_INT) { 206 __ push_jint(const_opr->as_jint()); 207 } else { 208 ShouldNotReachHere(); 209 } 210 211 } else { 212 ShouldNotReachHere(); 213 } 214 } 215 216 void LIR_Assembler::pop(LIR_Opr opr) { 217 if (opr->is_single_cpu()) { 218 __ pop_reg(opr->as_register()); 219 } else { 220 ShouldNotReachHere(); 221 } 222 } 223 224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 225 return addr->base()->is_illegal() && addr->index()->is_illegal(); 226 } 227 228 //------------------------------------------- 229 230 Address LIR_Assembler::as_Address(LIR_Address* addr) { 231 return as_Address(addr, rscratch1); 232 } 233 234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 235 if (addr->base()->is_illegal()) { 236 assert(addr->index()->is_illegal(), "must be illegal too"); 237 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 238 if (! __ reachable(laddr)) { 239 __ movptr(tmp, laddr.addr()); 240 Address res(tmp, 0); 241 return res; 242 } else { 243 return __ as_Address(laddr); 244 } 245 } 246 247 Register base = addr->base()->as_pointer_register(); 248 249 if (addr->index()->is_illegal()) { 250 return Address( base, addr->disp()); 251 } else if (addr->index()->is_cpu_register()) { 252 Register index = addr->index()->as_pointer_register(); 253 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 254 } else if (addr->index()->is_constant()) { 255 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 256 assert(Assembler::is_simm32(addr_offset), "must be"); 257 258 return Address(base, addr_offset); 259 } else { 260 Unimplemented(); 261 return Address(); 262 } 263 } 264 265 266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 267 Address base = as_Address(addr); 268 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 269 } 270 271 272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 273 return as_Address(addr); 274 } 275 276 277 void LIR_Assembler::osr_entry() { 278 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 279 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 280 ValueStack* entry_state = osr_entry->state(); 281 int number_of_locks = entry_state->locks_size(); 282 283 // we jump here if osr happens with the interpreter 284 // state set up to continue at the beginning of the 285 // loop that triggered osr - in particular, we have 286 // the following registers setup: 287 // 288 // rcx: osr buffer 289 // 290 291 // build frame 292 ciMethod* m = compilation()->method(); 293 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 294 295 // OSR buffer is 296 // 297 // locals[nlocals-1..0] 298 // monitors[0..number_of_locks] 299 // 300 // locals is a direct copy of the interpreter frame so in the osr buffer 301 // so first slot in the local array is the last local from the interpreter 302 // and last slot is local[0] (receiver) from the interpreter 303 // 304 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 305 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 306 // in the interpreter frame (the method lock if a sync method) 307 308 // Initialize monitors in the compiled activation. 309 // rcx: pointer to osr buffer 310 // 311 // All other registers are dead at this point and the locals will be 312 // copied into place by code emitted in the IR. 313 314 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 315 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 316 int monitor_offset = BytesPerWord * method()->max_locals() + 317 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 318 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 319 // the OSR buffer using 2 word entries: first the lock and then 320 // the oop. 321 for (int i = 0; i < number_of_locks; i++) { 322 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 323 #ifdef ASSERT 324 // verify the interpreter's monitor has a non-null object 325 { 326 Label L; 327 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 328 __ jcc(Assembler::notZero, L); 329 __ stop("locked object is NULL"); 330 __ bind(L); 331 } 332 #endif 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 334 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 335 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 336 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 337 } 338 } 339 } 340 341 342 // inline cache check; done before the frame is built. 343 int LIR_Assembler::check_icache() { 344 Register receiver = FrameMap::receiver_opr->as_register(); 345 Register ic_klass = IC_Klass; 346 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 347 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 348 if (!do_post_padding) { 349 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 350 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 351 } 352 int offset = __ offset(); 353 __ inline_cache_check(receiver, IC_Klass); 354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 355 if (do_post_padding) { 356 // force alignment after the cache check. 357 // It's been verified to be aligned if !VerifyOops 358 __ align(CodeEntryAlignment); 359 } 360 return offset; 361 } 362 363 364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 365 jobject o = NULL; 366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 367 __ movoop(reg, o); 368 patching_epilog(patch, lir_patch_normal, reg, info); 369 } 370 371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 372 Metadata* o = NULL; 373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 374 __ mov_metadata(reg, o); 375 patching_epilog(patch, lir_patch_normal, reg, info); 376 } 377 378 // This specifies the rsp decrement needed to build the frame 379 int LIR_Assembler::initial_frame_size_in_bytes() const { 380 // if rounding, must let FrameMap know! 381 382 // The frame_map records size in slots (32bit word) 383 384 // subtract two words to account for return address and link 385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 386 } 387 388 389 int LIR_Assembler::emit_exception_handler() { 390 // if the last instruction is a call (typically to do a throw which 391 // is coming at the end after block reordering) the return address 392 // must still point into the code area in order to avoid assertion 393 // failures when searching for the corresponding bci => add a nop 394 // (was bug 5/14/1999 - gri) 395 __ nop(); 396 397 // generate code for exception handler 398 address handler_base = __ start_a_stub(exception_handler_size()); 399 if (handler_base == NULL) { 400 // not enough space left for the handler 401 bailout("exception handler overflow"); 402 return -1; 403 } 404 405 int offset = code_offset(); 406 407 // the exception oop and pc are in rax, and rdx 408 // no other registers need to be preserved, so invalidate them 409 __ invalidate_registers(false, true, true, false, true, true); 410 411 // check that there is really an exception 412 __ verify_not_null_oop(rax); 413 414 // search an exception handler (rax: exception oop, rdx: throwing pc) 415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 416 __ should_not_reach_here(); 417 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 418 __ end_a_stub(); 419 420 return offset; 421 } 422 423 424 // Emit the code to remove the frame from the stack in the exception 425 // unwind path. 426 int LIR_Assembler::emit_unwind_handler() { 427 #ifndef PRODUCT 428 if (CommentedAssembly) { 429 _masm->block_comment("Unwind handler"); 430 } 431 #endif 432 433 int offset = code_offset(); 434 435 // Fetch the exception from TLS and clear out exception related thread state 436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 437 NOT_LP64(__ get_thread(rsi)); 438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 441 442 __ bind(_unwind_handler_entry); 443 __ verify_not_null_oop(rax); 444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 446 } 447 448 // Preform needed unlocking 449 MonitorExitStub* stub = NULL; 450 if (method()->is_synchronized()) { 451 monitor_address(0, FrameMap::rax_opr); 452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 453 __ unlock_object(rdi, rsi, rax, *stub->entry()); 454 __ bind(*stub->continuation()); 455 } 456 457 if (compilation()->env()->dtrace_method_probes()) { 458 #ifdef _LP64 459 __ mov(rdi, r15_thread); 460 __ mov_metadata(rsi, method()->constant_encoding()); 461 #else 462 __ get_thread(rax); 463 __ movptr(Address(rsp, 0), rax); 464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 465 #endif 466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 467 } 468 469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 470 __ mov(rax, rbx); // Restore the exception 471 } 472 473 // remove the activation and dispatch to the unwind handler 474 __ remove_frame(initial_frame_size_in_bytes()); 475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 476 477 // Emit the slow path assembly 478 if (stub != NULL) { 479 stub->emit_code(this); 480 } 481 482 return offset; 483 } 484 485 486 int LIR_Assembler::emit_deopt_handler() { 487 // if the last instruction is a call (typically to do a throw which 488 // is coming at the end after block reordering) the return address 489 // must still point into the code area in order to avoid assertion 490 // failures when searching for the corresponding bci => add a nop 491 // (was bug 5/14/1999 - gri) 492 __ nop(); 493 494 // generate code for exception handler 495 address handler_base = __ start_a_stub(deopt_handler_size()); 496 if (handler_base == NULL) { 497 // not enough space left for the handler 498 bailout("deopt handler overflow"); 499 return -1; 500 } 501 502 int offset = code_offset(); 503 InternalAddress here(__ pc()); 504 505 __ pushptr(here.addr()); 506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 507 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 508 __ end_a_stub(); 509 510 return offset; 511 } 512 513 514 void LIR_Assembler::return_op(LIR_Opr result) { 515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 517 assert(result->fpu() == 0, "result must already be on TOS"); 518 } 519 520 // Pop the stack before the safepoint code 521 __ remove_frame(initial_frame_size_in_bytes()); 522 523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 524 __ reserved_stack_check(); 525 } 526 527 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 528 529 // Note: we do not need to round double result; float result has the right precision 530 // the poll sets the condition code, but no data registers 531 532 if (SafepointMechanism::uses_thread_local_poll()) { 533 #ifdef _LP64 534 const Register poll_addr = rscratch1; 535 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 536 #else 537 const Register poll_addr = rbx; 538 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite"); 539 __ get_thread(poll_addr); 540 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset())); 541 #endif 542 __ relocate(relocInfo::poll_return_type); 543 __ testl(rax, Address(poll_addr, 0)); 544 } else { 545 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 546 547 if (Assembler::is_polling_page_far()) { 548 __ lea(rscratch1, polling_page); 549 __ relocate(relocInfo::poll_return_type); 550 __ testl(rax, Address(rscratch1, 0)); 551 } else { 552 __ testl(rax, polling_page); 553 } 554 } 555 __ ret(0); 556 } 557 558 559 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 560 guarantee(info != NULL, "Shouldn't be NULL"); 561 int offset = __ offset(); 562 if (SafepointMechanism::uses_thread_local_poll()) { 563 #ifdef _LP64 564 const Register poll_addr = rscratch1; 565 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 566 #else 567 assert(tmp->is_cpu_register(), "needed"); 568 const Register poll_addr = tmp->as_register(); 569 __ get_thread(poll_addr); 570 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset()))); 571 #endif 572 add_debug_info_for_branch(info); 573 __ relocate(relocInfo::poll_type); 574 address pre_pc = __ pc(); 575 __ testl(rax, Address(poll_addr, 0)); 576 address post_pc = __ pc(); 577 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 578 } else { 579 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 580 if (Assembler::is_polling_page_far()) { 581 __ lea(rscratch1, polling_page); 582 offset = __ offset(); 583 add_debug_info_for_branch(info); 584 __ relocate(relocInfo::poll_type); 585 __ testl(rax, Address(rscratch1, 0)); 586 } else { 587 add_debug_info_for_branch(info); 588 __ testl(rax, polling_page); 589 } 590 } 591 return offset; 592 } 593 594 595 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 596 if (from_reg != to_reg) __ mov(to_reg, from_reg); 597 } 598 599 void LIR_Assembler::swap_reg(Register a, Register b) { 600 __ xchgptr(a, b); 601 } 602 603 604 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 605 assert(src->is_constant(), "should not call otherwise"); 606 assert(dest->is_register(), "should not call otherwise"); 607 LIR_Const* c = src->as_constant_ptr(); 608 609 switch (c->type()) { 610 case T_INT: { 611 assert(patch_code == lir_patch_none, "no patching handled here"); 612 __ movl(dest->as_register(), c->as_jint()); 613 break; 614 } 615 616 case T_ADDRESS: { 617 assert(patch_code == lir_patch_none, "no patching handled here"); 618 __ movptr(dest->as_register(), c->as_jint()); 619 break; 620 } 621 622 case T_LONG: { 623 assert(patch_code == lir_patch_none, "no patching handled here"); 624 #ifdef _LP64 625 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 626 #else 627 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 628 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 629 #endif // _LP64 630 break; 631 } 632 633 case T_OBJECT: { 634 if (patch_code != lir_patch_none) { 635 jobject2reg_with_patching(dest->as_register(), info); 636 } else { 637 __ movoop(dest->as_register(), c->as_jobject()); 638 } 639 break; 640 } 641 642 case T_METADATA: { 643 if (patch_code != lir_patch_none) { 644 klass2reg_with_patching(dest->as_register(), info); 645 } else { 646 __ mov_metadata(dest->as_register(), c->as_metadata()); 647 } 648 break; 649 } 650 651 case T_FLOAT: { 652 if (dest->is_single_xmm()) { 653 if (c->is_zero_float()) { 654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 655 } else { 656 __ movflt(dest->as_xmm_float_reg(), 657 InternalAddress(float_constant(c->as_jfloat()))); 658 } 659 } else { 660 assert(dest->is_single_fpu(), "must be"); 661 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 662 if (c->is_zero_float()) { 663 __ fldz(); 664 } else if (c->is_one_float()) { 665 __ fld1(); 666 } else { 667 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 668 } 669 } 670 break; 671 } 672 673 case T_DOUBLE: { 674 if (dest->is_double_xmm()) { 675 if (c->is_zero_double()) { 676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 677 } else { 678 __ movdbl(dest->as_xmm_double_reg(), 679 InternalAddress(double_constant(c->as_jdouble()))); 680 } 681 } else { 682 assert(dest->is_double_fpu(), "must be"); 683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 684 if (c->is_zero_double()) { 685 __ fldz(); 686 } else if (c->is_one_double()) { 687 __ fld1(); 688 } else { 689 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 690 } 691 } 692 break; 693 } 694 695 default: 696 ShouldNotReachHere(); 697 } 698 } 699 700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 701 assert(src->is_constant(), "should not call otherwise"); 702 assert(dest->is_stack(), "should not call otherwise"); 703 LIR_Const* c = src->as_constant_ptr(); 704 705 switch (c->type()) { 706 case T_INT: // fall through 707 case T_FLOAT: 708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 709 break; 710 711 case T_ADDRESS: 712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 713 break; 714 715 case T_OBJECT: 716 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 717 break; 718 719 case T_LONG: // fall through 720 case T_DOUBLE: 721 #ifdef _LP64 722 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 723 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 724 #else 725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 726 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 728 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 729 #endif // _LP64 730 break; 731 732 default: 733 ShouldNotReachHere(); 734 } 735 } 736 737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 738 assert(src->is_constant(), "should not call otherwise"); 739 assert(dest->is_address(), "should not call otherwise"); 740 LIR_Const* c = src->as_constant_ptr(); 741 LIR_Address* addr = dest->as_address_ptr(); 742 743 int null_check_here = code_offset(); 744 switch (type) { 745 case T_INT: // fall through 746 case T_FLOAT: 747 __ movl(as_Address(addr), c->as_jint_bits()); 748 break; 749 750 case T_ADDRESS: 751 __ movptr(as_Address(addr), c->as_jint_bits()); 752 break; 753 754 case T_OBJECT: // fall through 755 case T_ARRAY: 756 if (c->as_jobject() == NULL) { 757 if (UseCompressedOops && !wide) { 758 __ movl(as_Address(addr), (int32_t)NULL_WORD); 759 } else { 760 #ifdef _LP64 761 __ xorptr(rscratch1, rscratch1); 762 null_check_here = code_offset(); 763 __ movptr(as_Address(addr), rscratch1); 764 #else 765 __ movptr(as_Address(addr), NULL_WORD); 766 #endif 767 } 768 } else { 769 if (is_literal_address(addr)) { 770 ShouldNotReachHere(); 771 __ movoop(as_Address(addr, noreg), c->as_jobject()); 772 } else { 773 #ifdef _LP64 774 __ movoop(rscratch1, c->as_jobject()); 775 if (UseCompressedOops && !wide) { 776 __ encode_heap_oop(rscratch1); 777 null_check_here = code_offset(); 778 __ movl(as_Address_lo(addr), rscratch1); 779 } else { 780 null_check_here = code_offset(); 781 __ movptr(as_Address_lo(addr), rscratch1); 782 } 783 #else 784 __ movoop(as_Address(addr), c->as_jobject()); 785 #endif 786 } 787 } 788 break; 789 790 case T_LONG: // fall through 791 case T_DOUBLE: 792 #ifdef _LP64 793 if (is_literal_address(addr)) { 794 ShouldNotReachHere(); 795 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 796 } else { 797 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 798 null_check_here = code_offset(); 799 __ movptr(as_Address_lo(addr), r10); 800 } 801 #else 802 // Always reachable in 32bit so this doesn't produce useless move literal 803 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 804 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 805 #endif // _LP64 806 break; 807 808 case T_BOOLEAN: // fall through 809 case T_BYTE: 810 __ movb(as_Address(addr), c->as_jint() & 0xFF); 811 break; 812 813 case T_CHAR: // fall through 814 case T_SHORT: 815 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 816 break; 817 818 default: 819 ShouldNotReachHere(); 820 }; 821 822 if (info != NULL) { 823 add_debug_info_for_null_check(null_check_here, info); 824 } 825 } 826 827 828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 829 assert(src->is_register(), "should not call otherwise"); 830 assert(dest->is_register(), "should not call otherwise"); 831 832 // move between cpu-registers 833 if (dest->is_single_cpu()) { 834 #ifdef _LP64 835 if (src->type() == T_LONG) { 836 // Can do LONG -> OBJECT 837 move_regs(src->as_register_lo(), dest->as_register()); 838 return; 839 } 840 #endif 841 assert(src->is_single_cpu(), "must match"); 842 if (src->type() == T_OBJECT) { 843 __ verify_oop(src->as_register()); 844 } 845 move_regs(src->as_register(), dest->as_register()); 846 847 } else if (dest->is_double_cpu()) { 848 #ifdef _LP64 849 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 850 // Surprising to me but we can see move of a long to t_object 851 __ verify_oop(src->as_register()); 852 move_regs(src->as_register(), dest->as_register_lo()); 853 return; 854 } 855 #endif 856 assert(src->is_double_cpu(), "must match"); 857 Register f_lo = src->as_register_lo(); 858 Register f_hi = src->as_register_hi(); 859 Register t_lo = dest->as_register_lo(); 860 Register t_hi = dest->as_register_hi(); 861 #ifdef _LP64 862 assert(f_hi == f_lo, "must be same"); 863 assert(t_hi == t_lo, "must be same"); 864 move_regs(f_lo, t_lo); 865 #else 866 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 867 868 869 if (f_lo == t_hi && f_hi == t_lo) { 870 swap_reg(f_lo, f_hi); 871 } else if (f_hi == t_lo) { 872 assert(f_lo != t_hi, "overwriting register"); 873 move_regs(f_hi, t_hi); 874 move_regs(f_lo, t_lo); 875 } else { 876 assert(f_hi != t_lo, "overwriting register"); 877 move_regs(f_lo, t_lo); 878 move_regs(f_hi, t_hi); 879 } 880 #endif // LP64 881 882 // special moves from fpu-register to xmm-register 883 // necessary for method results 884 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 885 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 886 __ fld_s(Address(rsp, 0)); 887 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 888 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 889 __ fld_d(Address(rsp, 0)); 890 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 891 __ fstp_s(Address(rsp, 0)); 892 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 893 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 894 __ fstp_d(Address(rsp, 0)); 895 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 896 897 // move between xmm-registers 898 } else if (dest->is_single_xmm()) { 899 assert(src->is_single_xmm(), "must match"); 900 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 901 } else if (dest->is_double_xmm()) { 902 assert(src->is_double_xmm(), "must match"); 903 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 904 905 // move between fpu-registers (no instruction necessary because of fpu-stack) 906 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 907 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 908 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 909 } else { 910 ShouldNotReachHere(); 911 } 912 } 913 914 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 915 assert(src->is_register(), "should not call otherwise"); 916 assert(dest->is_stack(), "should not call otherwise"); 917 918 if (src->is_single_cpu()) { 919 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 920 if (type == T_OBJECT || type == T_ARRAY) { 921 __ verify_oop(src->as_register()); 922 __ movptr (dst, src->as_register()); 923 } else if (type == T_METADATA) { 924 __ movptr (dst, src->as_register()); 925 } else { 926 __ movl (dst, src->as_register()); 927 } 928 929 } else if (src->is_double_cpu()) { 930 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 931 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 932 __ movptr (dstLO, src->as_register_lo()); 933 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 934 935 } else if (src->is_single_xmm()) { 936 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 937 __ movflt(dst_addr, src->as_xmm_float_reg()); 938 939 } else if (src->is_double_xmm()) { 940 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 941 __ movdbl(dst_addr, src->as_xmm_double_reg()); 942 943 } else if (src->is_single_fpu()) { 944 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 945 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 946 if (pop_fpu_stack) __ fstp_s (dst_addr); 947 else __ fst_s (dst_addr); 948 949 } else if (src->is_double_fpu()) { 950 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 951 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 952 if (pop_fpu_stack) __ fstp_d (dst_addr); 953 else __ fst_d (dst_addr); 954 955 } else { 956 ShouldNotReachHere(); 957 } 958 } 959 960 961 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 962 LIR_Address* to_addr = dest->as_address_ptr(); 963 PatchingStub* patch = NULL; 964 Register compressed_src = rscratch1; 965 966 if (type == T_ARRAY || type == T_OBJECT) { 967 __ verify_oop(src->as_register()); 968 #ifdef _LP64 969 if (UseCompressedOops && !wide) { 970 __ movptr(compressed_src, src->as_register()); 971 __ encode_heap_oop(compressed_src); 972 if (patch_code != lir_patch_none) { 973 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 974 } 975 } 976 #endif 977 } 978 979 if (patch_code != lir_patch_none) { 980 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 981 Address toa = as_Address(to_addr); 982 assert(toa.disp() != 0, "must have"); 983 } 984 985 int null_check_here = code_offset(); 986 switch (type) { 987 case T_FLOAT: { 988 if (src->is_single_xmm()) { 989 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 990 } else { 991 assert(src->is_single_fpu(), "must be"); 992 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 993 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 994 else __ fst_s (as_Address(to_addr)); 995 } 996 break; 997 } 998 999 case T_DOUBLE: { 1000 if (src->is_double_xmm()) { 1001 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1002 } else { 1003 assert(src->is_double_fpu(), "must be"); 1004 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1005 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1006 else __ fst_d (as_Address(to_addr)); 1007 } 1008 break; 1009 } 1010 1011 case T_ARRAY: // fall through 1012 case T_OBJECT: // fall through 1013 if (UseCompressedOops && !wide) { 1014 __ movl(as_Address(to_addr), compressed_src); 1015 } else { 1016 __ movptr(as_Address(to_addr), src->as_register()); 1017 } 1018 break; 1019 case T_METADATA: 1020 // We get here to store a method pointer to the stack to pass to 1021 // a dtrace runtime call. This can't work on 64 bit with 1022 // compressed klass ptrs: T_METADATA can be a compressed klass 1023 // ptr or a 64 bit method pointer. 1024 LP64_ONLY(ShouldNotReachHere()); 1025 __ movptr(as_Address(to_addr), src->as_register()); 1026 break; 1027 case T_ADDRESS: 1028 __ movptr(as_Address(to_addr), src->as_register()); 1029 break; 1030 case T_INT: 1031 __ movl(as_Address(to_addr), src->as_register()); 1032 break; 1033 1034 case T_LONG: { 1035 Register from_lo = src->as_register_lo(); 1036 Register from_hi = src->as_register_hi(); 1037 #ifdef _LP64 1038 __ movptr(as_Address_lo(to_addr), from_lo); 1039 #else 1040 Register base = to_addr->base()->as_register(); 1041 Register index = noreg; 1042 if (to_addr->index()->is_register()) { 1043 index = to_addr->index()->as_register(); 1044 } 1045 if (base == from_lo || index == from_lo) { 1046 assert(base != from_hi, "can't be"); 1047 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1048 __ movl(as_Address_hi(to_addr), from_hi); 1049 if (patch != NULL) { 1050 patching_epilog(patch, lir_patch_high, base, info); 1051 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1052 patch_code = lir_patch_low; 1053 } 1054 __ movl(as_Address_lo(to_addr), from_lo); 1055 } else { 1056 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1057 __ movl(as_Address_lo(to_addr), from_lo); 1058 if (patch != NULL) { 1059 patching_epilog(patch, lir_patch_low, base, info); 1060 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1061 patch_code = lir_patch_high; 1062 } 1063 __ movl(as_Address_hi(to_addr), from_hi); 1064 } 1065 #endif // _LP64 1066 break; 1067 } 1068 1069 case T_BYTE: // fall through 1070 case T_BOOLEAN: { 1071 Register src_reg = src->as_register(); 1072 Address dst_addr = as_Address(to_addr); 1073 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1074 __ movb(dst_addr, src_reg); 1075 break; 1076 } 1077 1078 case T_CHAR: // fall through 1079 case T_SHORT: 1080 __ movw(as_Address(to_addr), src->as_register()); 1081 break; 1082 1083 default: 1084 ShouldNotReachHere(); 1085 } 1086 if (info != NULL) { 1087 add_debug_info_for_null_check(null_check_here, info); 1088 } 1089 1090 if (patch_code != lir_patch_none) { 1091 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1092 } 1093 } 1094 1095 1096 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1097 assert(src->is_stack(), "should not call otherwise"); 1098 assert(dest->is_register(), "should not call otherwise"); 1099 1100 if (dest->is_single_cpu()) { 1101 if (type == T_ARRAY || type == T_OBJECT) { 1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1103 __ verify_oop(dest->as_register()); 1104 } else if (type == T_METADATA) { 1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1106 } else { 1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1108 } 1109 1110 } else if (dest->is_double_cpu()) { 1111 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1112 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1113 __ movptr(dest->as_register_lo(), src_addr_LO); 1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1115 1116 } else if (dest->is_single_xmm()) { 1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1118 __ movflt(dest->as_xmm_float_reg(), src_addr); 1119 1120 } else if (dest->is_double_xmm()) { 1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1122 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1123 1124 } else if (dest->is_single_fpu()) { 1125 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1126 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1127 __ fld_s(src_addr); 1128 1129 } else if (dest->is_double_fpu()) { 1130 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1131 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1132 __ fld_d(src_addr); 1133 1134 } else { 1135 ShouldNotReachHere(); 1136 } 1137 } 1138 1139 1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1141 if (src->is_single_stack()) { 1142 if (type == T_OBJECT || type == T_ARRAY) { 1143 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1144 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1145 } else { 1146 #ifndef _LP64 1147 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1148 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1149 #else 1150 //no pushl on 64bits 1151 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1152 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1153 #endif 1154 } 1155 1156 } else if (src->is_double_stack()) { 1157 #ifdef _LP64 1158 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1159 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1160 #else 1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1162 // push and pop the part at src + wordSize, adding wordSize for the previous push 1163 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1165 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1166 #endif // _LP64 1167 1168 } else { 1169 ShouldNotReachHere(); 1170 } 1171 } 1172 1173 1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1175 assert(src->is_address(), "should not call otherwise"); 1176 assert(dest->is_register(), "should not call otherwise"); 1177 1178 LIR_Address* addr = src->as_address_ptr(); 1179 Address from_addr = as_Address(addr); 1180 1181 if (addr->base()->type() == T_OBJECT) { 1182 __ verify_oop(addr->base()->as_pointer_register()); 1183 } 1184 1185 switch (type) { 1186 case T_BOOLEAN: // fall through 1187 case T_BYTE: // fall through 1188 case T_CHAR: // fall through 1189 case T_SHORT: 1190 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1191 // on pre P6 processors we may get partial register stalls 1192 // so blow away the value of to_rinfo before loading a 1193 // partial word into it. Do it here so that it precedes 1194 // the potential patch point below. 1195 __ xorptr(dest->as_register(), dest->as_register()); 1196 } 1197 break; 1198 default: 1199 break; 1200 } 1201 1202 PatchingStub* patch = NULL; 1203 if (patch_code != lir_patch_none) { 1204 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1205 assert(from_addr.disp() != 0, "must have"); 1206 } 1207 if (info != NULL) { 1208 add_debug_info_for_null_check_here(info); 1209 } 1210 1211 switch (type) { 1212 case T_FLOAT: { 1213 if (dest->is_single_xmm()) { 1214 __ movflt(dest->as_xmm_float_reg(), from_addr); 1215 } else { 1216 assert(dest->is_single_fpu(), "must be"); 1217 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1218 __ fld_s(from_addr); 1219 } 1220 break; 1221 } 1222 1223 case T_DOUBLE: { 1224 if (dest->is_double_xmm()) { 1225 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1226 } else { 1227 assert(dest->is_double_fpu(), "must be"); 1228 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1229 __ fld_d(from_addr); 1230 } 1231 break; 1232 } 1233 1234 case T_OBJECT: // fall through 1235 case T_ARRAY: // fall through 1236 if (UseCompressedOops && !wide) { 1237 __ movl(dest->as_register(), from_addr); 1238 } else { 1239 __ movptr(dest->as_register(), from_addr); 1240 } 1241 break; 1242 1243 case T_ADDRESS: 1244 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1245 __ movl(dest->as_register(), from_addr); 1246 } else { 1247 __ movptr(dest->as_register(), from_addr); 1248 } 1249 break; 1250 case T_INT: 1251 __ movl(dest->as_register(), from_addr); 1252 break; 1253 1254 case T_LONG: { 1255 Register to_lo = dest->as_register_lo(); 1256 Register to_hi = dest->as_register_hi(); 1257 #ifdef _LP64 1258 __ movptr(to_lo, as_Address_lo(addr)); 1259 #else 1260 Register base = addr->base()->as_register(); 1261 Register index = noreg; 1262 if (addr->index()->is_register()) { 1263 index = addr->index()->as_register(); 1264 } 1265 if ((base == to_lo && index == to_hi) || 1266 (base == to_hi && index == to_lo)) { 1267 // addresses with 2 registers are only formed as a result of 1268 // array access so this code will never have to deal with 1269 // patches or null checks. 1270 assert(info == NULL && patch == NULL, "must be"); 1271 __ lea(to_hi, as_Address(addr)); 1272 __ movl(to_lo, Address(to_hi, 0)); 1273 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1274 } else if (base == to_lo || index == to_lo) { 1275 assert(base != to_hi, "can't be"); 1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1277 __ movl(to_hi, as_Address_hi(addr)); 1278 if (patch != NULL) { 1279 patching_epilog(patch, lir_patch_high, base, info); 1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1281 patch_code = lir_patch_low; 1282 } 1283 __ movl(to_lo, as_Address_lo(addr)); 1284 } else { 1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1286 __ movl(to_lo, as_Address_lo(addr)); 1287 if (patch != NULL) { 1288 patching_epilog(patch, lir_patch_low, base, info); 1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1290 patch_code = lir_patch_high; 1291 } 1292 __ movl(to_hi, as_Address_hi(addr)); 1293 } 1294 #endif // _LP64 1295 break; 1296 } 1297 1298 case T_BOOLEAN: // fall through 1299 case T_BYTE: { 1300 Register dest_reg = dest->as_register(); 1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1303 __ movsbl(dest_reg, from_addr); 1304 } else { 1305 __ movb(dest_reg, from_addr); 1306 __ shll(dest_reg, 24); 1307 __ sarl(dest_reg, 24); 1308 } 1309 break; 1310 } 1311 1312 case T_CHAR: { 1313 Register dest_reg = dest->as_register(); 1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1316 __ movzwl(dest_reg, from_addr); 1317 } else { 1318 __ movw(dest_reg, from_addr); 1319 } 1320 break; 1321 } 1322 1323 case T_SHORT: { 1324 Register dest_reg = dest->as_register(); 1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1326 __ movswl(dest_reg, from_addr); 1327 } else { 1328 __ movw(dest_reg, from_addr); 1329 __ shll(dest_reg, 16); 1330 __ sarl(dest_reg, 16); 1331 } 1332 break; 1333 } 1334 1335 default: 1336 ShouldNotReachHere(); 1337 } 1338 1339 if (patch != NULL) { 1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1341 } 1342 1343 if (type == T_ARRAY || type == T_OBJECT) { 1344 #ifdef _LP64 1345 if (UseCompressedOops && !wide) { 1346 __ decode_heap_oop(dest->as_register()); 1347 } 1348 #endif 1349 __ verify_oop(dest->as_register()); 1350 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1351 #ifdef _LP64 1352 if (UseCompressedClassPointers) { 1353 __ decode_klass_not_null(dest->as_register()); 1354 } 1355 #endif 1356 } 1357 } 1358 1359 1360 NEEDS_CLEANUP; // This could be static? 1361 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1362 int elem_size = type2aelembytes(type); 1363 switch (elem_size) { 1364 case 1: return Address::times_1; 1365 case 2: return Address::times_2; 1366 case 4: return Address::times_4; 1367 case 8: return Address::times_8; 1368 } 1369 ShouldNotReachHere(); 1370 return Address::no_scale; 1371 } 1372 1373 1374 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1375 switch (op->code()) { 1376 case lir_idiv: 1377 case lir_irem: 1378 arithmetic_idiv(op->code(), 1379 op->in_opr1(), 1380 op->in_opr2(), 1381 op->in_opr3(), 1382 op->result_opr(), 1383 op->info()); 1384 break; 1385 case lir_fmad: 1386 __ fmad(op->result_opr()->as_xmm_double_reg(), 1387 op->in_opr1()->as_xmm_double_reg(), 1388 op->in_opr2()->as_xmm_double_reg(), 1389 op->in_opr3()->as_xmm_double_reg()); 1390 break; 1391 case lir_fmaf: 1392 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1393 op->in_opr1()->as_xmm_float_reg(), 1394 op->in_opr2()->as_xmm_float_reg(), 1395 op->in_opr3()->as_xmm_float_reg()); 1396 break; 1397 default: ShouldNotReachHere(); break; 1398 } 1399 } 1400 1401 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1402 #ifdef ASSERT 1403 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1404 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1405 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1406 #endif 1407 1408 if (op->cond() == lir_cond_always) { 1409 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1410 __ jmp (*(op->label())); 1411 } else { 1412 Assembler::Condition acond = Assembler::zero; 1413 if (op->code() == lir_cond_float_branch) { 1414 assert(op->ublock() != NULL, "must have unordered successor"); 1415 __ jcc(Assembler::parity, *(op->ublock()->label())); 1416 switch(op->cond()) { 1417 case lir_cond_equal: acond = Assembler::equal; break; 1418 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1419 case lir_cond_less: acond = Assembler::below; break; 1420 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1421 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1422 case lir_cond_greater: acond = Assembler::above; break; 1423 default: ShouldNotReachHere(); 1424 } 1425 } else { 1426 switch (op->cond()) { 1427 case lir_cond_equal: acond = Assembler::equal; break; 1428 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1429 case lir_cond_less: acond = Assembler::less; break; 1430 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1431 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1432 case lir_cond_greater: acond = Assembler::greater; break; 1433 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1434 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1435 default: ShouldNotReachHere(); 1436 } 1437 } 1438 __ jcc(acond,*(op->label())); 1439 } 1440 } 1441 1442 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1443 LIR_Opr src = op->in_opr(); 1444 LIR_Opr dest = op->result_opr(); 1445 1446 switch (op->bytecode()) { 1447 case Bytecodes::_i2l: 1448 #ifdef _LP64 1449 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1450 #else 1451 move_regs(src->as_register(), dest->as_register_lo()); 1452 move_regs(src->as_register(), dest->as_register_hi()); 1453 __ sarl(dest->as_register_hi(), 31); 1454 #endif // LP64 1455 break; 1456 1457 case Bytecodes::_l2i: 1458 #ifdef _LP64 1459 __ movl(dest->as_register(), src->as_register_lo()); 1460 #else 1461 move_regs(src->as_register_lo(), dest->as_register()); 1462 #endif 1463 break; 1464 1465 case Bytecodes::_i2b: 1466 move_regs(src->as_register(), dest->as_register()); 1467 __ sign_extend_byte(dest->as_register()); 1468 break; 1469 1470 case Bytecodes::_i2c: 1471 move_regs(src->as_register(), dest->as_register()); 1472 __ andl(dest->as_register(), 0xFFFF); 1473 break; 1474 1475 case Bytecodes::_i2s: 1476 move_regs(src->as_register(), dest->as_register()); 1477 __ sign_extend_short(dest->as_register()); 1478 break; 1479 1480 1481 case Bytecodes::_f2d: 1482 case Bytecodes::_d2f: 1483 if (dest->is_single_xmm()) { 1484 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1485 } else if (dest->is_double_xmm()) { 1486 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1487 } else { 1488 assert(src->fpu() == dest->fpu(), "register must be equal"); 1489 // do nothing (float result is rounded later through spilling) 1490 } 1491 break; 1492 1493 case Bytecodes::_i2f: 1494 case Bytecodes::_i2d: 1495 if (dest->is_single_xmm()) { 1496 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1497 } else if (dest->is_double_xmm()) { 1498 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1499 } else { 1500 assert(dest->fpu() == 0, "result must be on TOS"); 1501 __ movl(Address(rsp, 0), src->as_register()); 1502 __ fild_s(Address(rsp, 0)); 1503 } 1504 break; 1505 1506 case Bytecodes::_f2i: 1507 case Bytecodes::_d2i: 1508 if (src->is_single_xmm()) { 1509 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1510 } else if (src->is_double_xmm()) { 1511 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1512 } else { 1513 assert(src->fpu() == 0, "input must be on TOS"); 1514 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1515 __ fist_s(Address(rsp, 0)); 1516 __ movl(dest->as_register(), Address(rsp, 0)); 1517 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1518 } 1519 1520 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1521 assert(op->stub() != NULL, "stub required"); 1522 __ cmpl(dest->as_register(), 0x80000000); 1523 __ jcc(Assembler::equal, *op->stub()->entry()); 1524 __ bind(*op->stub()->continuation()); 1525 break; 1526 1527 case Bytecodes::_l2f: 1528 case Bytecodes::_l2d: 1529 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1530 assert(dest->fpu() == 0, "result must be on TOS"); 1531 1532 __ movptr(Address(rsp, 0), src->as_register_lo()); 1533 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1534 __ fild_d(Address(rsp, 0)); 1535 // float result is rounded later through spilling 1536 break; 1537 1538 case Bytecodes::_f2l: 1539 case Bytecodes::_d2l: 1540 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1541 assert(src->fpu() == 0, "input must be on TOS"); 1542 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1543 1544 // instruction sequence too long to inline it here 1545 { 1546 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1547 } 1548 break; 1549 1550 default: ShouldNotReachHere(); 1551 } 1552 } 1553 1554 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1555 if (op->init_check()) { 1556 add_debug_info_for_null_check_here(op->stub()->info()); 1557 __ cmpb(Address(op->klass()->as_register(), 1558 InstanceKlass::init_state_offset()), 1559 InstanceKlass::fully_initialized); 1560 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1561 } 1562 __ allocate_object(op->obj()->as_register(), 1563 op->tmp1()->as_register(), 1564 op->tmp2()->as_register(), 1565 op->header_size(), 1566 op->object_size(), 1567 op->klass()->as_register(), 1568 *op->stub()->entry()); 1569 __ bind(*op->stub()->continuation()); 1570 } 1571 1572 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1573 Register len = op->len()->as_register(); 1574 LP64_ONLY( __ movslq(len, len); ) 1575 1576 if (UseSlowPath || 1577 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1578 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1579 __ jmp(*op->stub()->entry()); 1580 } else { 1581 Register tmp1 = op->tmp1()->as_register(); 1582 Register tmp2 = op->tmp2()->as_register(); 1583 Register tmp3 = op->tmp3()->as_register(); 1584 if (len == tmp1) { 1585 tmp1 = tmp3; 1586 } else if (len == tmp2) { 1587 tmp2 = tmp3; 1588 } else if (len == tmp3) { 1589 // everything is ok 1590 } else { 1591 __ mov(tmp3, len); 1592 } 1593 __ allocate_array(op->obj()->as_register(), 1594 len, 1595 tmp1, 1596 tmp2, 1597 arrayOopDesc::header_size(op->type()), 1598 array_element_size(op->type()), 1599 op->klass()->as_register(), 1600 *op->stub()->entry()); 1601 } 1602 __ bind(*op->stub()->continuation()); 1603 } 1604 1605 void LIR_Assembler::type_profile_helper(Register mdo, 1606 ciMethodData *md, ciProfileData *data, 1607 Register recv, Label* update_done) { 1608 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1609 Label next_test; 1610 // See if the receiver is receiver[n]. 1611 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1612 __ jccb(Assembler::notEqual, next_test); 1613 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1614 __ addptr(data_addr, DataLayout::counter_increment); 1615 __ jmp(*update_done); 1616 __ bind(next_test); 1617 } 1618 1619 // Didn't find receiver; find next empty slot and fill it in 1620 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1621 Label next_test; 1622 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1623 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1624 __ jccb(Assembler::notEqual, next_test); 1625 __ movptr(recv_addr, recv); 1626 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1627 __ jmp(*update_done); 1628 __ bind(next_test); 1629 } 1630 } 1631 1632 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1633 // we always need a stub for the failure case. 1634 CodeStub* stub = op->stub(); 1635 Register obj = op->object()->as_register(); 1636 Register k_RInfo = op->tmp1()->as_register(); 1637 Register klass_RInfo = op->tmp2()->as_register(); 1638 Register dst = op->result_opr()->as_register(); 1639 ciKlass* k = op->klass(); 1640 Register Rtmp1 = noreg; 1641 1642 // check if it needs to be profiled 1643 ciMethodData* md = NULL; 1644 ciProfileData* data = NULL; 1645 1646 if (op->should_profile()) { 1647 ciMethod* method = op->profiled_method(); 1648 assert(method != NULL, "Should have method"); 1649 int bci = op->profiled_bci(); 1650 md = method->method_data_or_null(); 1651 assert(md != NULL, "Sanity"); 1652 data = md->bci_to_data(bci); 1653 assert(data != NULL, "need data for type check"); 1654 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1655 } 1656 Label profile_cast_success, profile_cast_failure; 1657 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1658 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1659 1660 if (obj == k_RInfo) { 1661 k_RInfo = dst; 1662 } else if (obj == klass_RInfo) { 1663 klass_RInfo = dst; 1664 } 1665 if (k->is_loaded() && !UseCompressedClassPointers) { 1666 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1667 } else { 1668 Rtmp1 = op->tmp3()->as_register(); 1669 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1670 } 1671 1672 assert_different_registers(obj, k_RInfo, klass_RInfo); 1673 1674 __ cmpptr(obj, (int32_t)NULL_WORD); 1675 if (op->should_profile()) { 1676 Label not_null; 1677 __ jccb(Assembler::notEqual, not_null); 1678 // Object is null; update MDO and exit 1679 Register mdo = klass_RInfo; 1680 __ mov_metadata(mdo, md->constant_encoding()); 1681 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1682 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1683 __ orl(data_addr, header_bits); 1684 __ jmp(*obj_is_null); 1685 __ bind(not_null); 1686 } else { 1687 __ jcc(Assembler::equal, *obj_is_null); 1688 } 1689 1690 if (!k->is_loaded()) { 1691 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1692 } else { 1693 #ifdef _LP64 1694 __ mov_metadata(k_RInfo, k->constant_encoding()); 1695 #endif // _LP64 1696 } 1697 __ verify_oop(obj); 1698 1699 if (op->fast_check()) { 1700 // get object class 1701 // not a safepoint as obj null check happens earlier 1702 #ifdef _LP64 1703 if (UseCompressedClassPointers) { 1704 __ load_klass(Rtmp1, obj); 1705 __ cmpptr(k_RInfo, Rtmp1); 1706 } else { 1707 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1708 } 1709 #else 1710 if (k->is_loaded()) { 1711 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1712 } else { 1713 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1714 } 1715 #endif 1716 __ jcc(Assembler::notEqual, *failure_target); 1717 // successful cast, fall through to profile or jump 1718 } else { 1719 // get object class 1720 // not a safepoint as obj null check happens earlier 1721 __ load_klass(klass_RInfo, obj); 1722 if (k->is_loaded()) { 1723 // See if we get an immediate positive hit 1724 #ifdef _LP64 1725 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1726 #else 1727 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1728 #endif // _LP64 1729 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1730 __ jcc(Assembler::notEqual, *failure_target); 1731 // successful cast, fall through to profile or jump 1732 } else { 1733 // See if we get an immediate positive hit 1734 __ jcc(Assembler::equal, *success_target); 1735 // check for self 1736 #ifdef _LP64 1737 __ cmpptr(klass_RInfo, k_RInfo); 1738 #else 1739 __ cmpklass(klass_RInfo, k->constant_encoding()); 1740 #endif // _LP64 1741 __ jcc(Assembler::equal, *success_target); 1742 1743 __ push(klass_RInfo); 1744 #ifdef _LP64 1745 __ push(k_RInfo); 1746 #else 1747 __ pushklass(k->constant_encoding()); 1748 #endif // _LP64 1749 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1750 __ pop(klass_RInfo); 1751 __ pop(klass_RInfo); 1752 // result is a boolean 1753 __ cmpl(klass_RInfo, 0); 1754 __ jcc(Assembler::equal, *failure_target); 1755 // successful cast, fall through to profile or jump 1756 } 1757 } else { 1758 // perform the fast part of the checking logic 1759 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1760 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1761 __ push(klass_RInfo); 1762 __ push(k_RInfo); 1763 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1764 __ pop(klass_RInfo); 1765 __ pop(k_RInfo); 1766 // result is a boolean 1767 __ cmpl(k_RInfo, 0); 1768 __ jcc(Assembler::equal, *failure_target); 1769 // successful cast, fall through to profile or jump 1770 } 1771 } 1772 if (op->should_profile()) { 1773 Register mdo = klass_RInfo, recv = k_RInfo; 1774 __ bind(profile_cast_success); 1775 __ mov_metadata(mdo, md->constant_encoding()); 1776 __ load_klass(recv, obj); 1777 Label update_done; 1778 type_profile_helper(mdo, md, data, recv, success); 1779 __ jmp(*success); 1780 1781 __ bind(profile_cast_failure); 1782 __ mov_metadata(mdo, md->constant_encoding()); 1783 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1784 __ subptr(counter_addr, DataLayout::counter_increment); 1785 __ jmp(*failure); 1786 } 1787 __ jmp(*success); 1788 } 1789 1790 1791 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1792 LIR_Code code = op->code(); 1793 if (code == lir_store_check) { 1794 Register value = op->object()->as_register(); 1795 Register array = op->array()->as_register(); 1796 Register k_RInfo = op->tmp1()->as_register(); 1797 Register klass_RInfo = op->tmp2()->as_register(); 1798 Register Rtmp1 = op->tmp3()->as_register(); 1799 1800 CodeStub* stub = op->stub(); 1801 1802 // check if it needs to be profiled 1803 ciMethodData* md = NULL; 1804 ciProfileData* data = NULL; 1805 1806 if (op->should_profile()) { 1807 ciMethod* method = op->profiled_method(); 1808 assert(method != NULL, "Should have method"); 1809 int bci = op->profiled_bci(); 1810 md = method->method_data_or_null(); 1811 assert(md != NULL, "Sanity"); 1812 data = md->bci_to_data(bci); 1813 assert(data != NULL, "need data for type check"); 1814 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1815 } 1816 Label profile_cast_success, profile_cast_failure, done; 1817 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1818 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1819 1820 __ cmpptr(value, (int32_t)NULL_WORD); 1821 if (op->should_profile()) { 1822 Label not_null; 1823 __ jccb(Assembler::notEqual, not_null); 1824 // Object is null; update MDO and exit 1825 Register mdo = klass_RInfo; 1826 __ mov_metadata(mdo, md->constant_encoding()); 1827 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1828 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1829 __ orl(data_addr, header_bits); 1830 __ jmp(done); 1831 __ bind(not_null); 1832 } else { 1833 __ jcc(Assembler::equal, done); 1834 } 1835 1836 add_debug_info_for_null_check_here(op->info_for_exception()); 1837 __ load_klass(k_RInfo, array); 1838 __ load_klass(klass_RInfo, value); 1839 1840 // get instance klass (it's already uncompressed) 1841 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1842 // perform the fast part of the checking logic 1843 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1844 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1845 __ push(klass_RInfo); 1846 __ push(k_RInfo); 1847 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1848 __ pop(klass_RInfo); 1849 __ pop(k_RInfo); 1850 // result is a boolean 1851 __ cmpl(k_RInfo, 0); 1852 __ jcc(Assembler::equal, *failure_target); 1853 // fall through to the success case 1854 1855 if (op->should_profile()) { 1856 Register mdo = klass_RInfo, recv = k_RInfo; 1857 __ bind(profile_cast_success); 1858 __ mov_metadata(mdo, md->constant_encoding()); 1859 __ load_klass(recv, value); 1860 Label update_done; 1861 type_profile_helper(mdo, md, data, recv, &done); 1862 __ jmpb(done); 1863 1864 __ bind(profile_cast_failure); 1865 __ mov_metadata(mdo, md->constant_encoding()); 1866 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1867 __ subptr(counter_addr, DataLayout::counter_increment); 1868 __ jmp(*stub->entry()); 1869 } 1870 1871 __ bind(done); 1872 } else 1873 if (code == lir_checkcast) { 1874 Register obj = op->object()->as_register(); 1875 Register dst = op->result_opr()->as_register(); 1876 Label success; 1877 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1878 __ bind(success); 1879 if (dst != obj) { 1880 __ mov(dst, obj); 1881 } 1882 } else 1883 if (code == lir_instanceof) { 1884 Register obj = op->object()->as_register(); 1885 Register dst = op->result_opr()->as_register(); 1886 Label success, failure, done; 1887 emit_typecheck_helper(op, &success, &failure, &failure); 1888 __ bind(failure); 1889 __ xorptr(dst, dst); 1890 __ jmpb(done); 1891 __ bind(success); 1892 __ movptr(dst, 1); 1893 __ bind(done); 1894 } else { 1895 ShouldNotReachHere(); 1896 } 1897 1898 } 1899 1900 1901 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1902 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1903 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1904 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1905 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1906 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1907 Register addr = op->addr()->as_register(); 1908 if (os::is_MP()) { 1909 __ lock(); 1910 } 1911 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1912 1913 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1914 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1915 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1916 Register newval = op->new_value()->as_register(); 1917 Register cmpval = op->cmp_value()->as_register(); 1918 assert(cmpval == rax, "wrong register"); 1919 assert(newval != NULL, "new val must be register"); 1920 assert(cmpval != newval, "cmp and new values must be in different registers"); 1921 assert(cmpval != addr, "cmp and addr must be in different registers"); 1922 assert(newval != addr, "new value and addr must be in different registers"); 1923 1924 if ( op->code() == lir_cas_obj) { 1925 #ifdef _LP64 1926 if (UseCompressedOops) { 1927 __ encode_heap_oop(cmpval); 1928 __ mov(rscratch1, newval); 1929 __ encode_heap_oop(rscratch1); 1930 if (os::is_MP()) { 1931 __ lock(); 1932 } 1933 // cmpval (rax) is implicitly used by this instruction 1934 __ cmpxchgl(rscratch1, Address(addr, 0)); 1935 } else 1936 #endif 1937 { 1938 if (os::is_MP()) { 1939 __ lock(); 1940 } 1941 __ cmpxchgptr(newval, Address(addr, 0)); 1942 } 1943 } else { 1944 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1945 if (os::is_MP()) { 1946 __ lock(); 1947 } 1948 __ cmpxchgl(newval, Address(addr, 0)); 1949 } 1950 #ifdef _LP64 1951 } else if (op->code() == lir_cas_long) { 1952 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1953 Register newval = op->new_value()->as_register_lo(); 1954 Register cmpval = op->cmp_value()->as_register_lo(); 1955 assert(cmpval == rax, "wrong register"); 1956 assert(newval != NULL, "new val must be register"); 1957 assert(cmpval != newval, "cmp and new values must be in different registers"); 1958 assert(cmpval != addr, "cmp and addr must be in different registers"); 1959 assert(newval != addr, "new value and addr must be in different registers"); 1960 if (os::is_MP()) { 1961 __ lock(); 1962 } 1963 __ cmpxchgq(newval, Address(addr, 0)); 1964 #endif // _LP64 1965 } else { 1966 Unimplemented(); 1967 } 1968 } 1969 1970 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1971 Assembler::Condition acond, ncond; 1972 switch (condition) { 1973 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1974 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1975 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1976 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1977 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1978 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1979 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1980 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1981 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1982 ShouldNotReachHere(); 1983 } 1984 1985 if (opr1->is_cpu_register()) { 1986 reg2reg(opr1, result); 1987 } else if (opr1->is_stack()) { 1988 stack2reg(opr1, result, result->type()); 1989 } else if (opr1->is_constant()) { 1990 const2reg(opr1, result, lir_patch_none, NULL); 1991 } else { 1992 ShouldNotReachHere(); 1993 } 1994 1995 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1996 // optimized version that does not require a branch 1997 if (opr2->is_single_cpu()) { 1998 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1999 __ cmov(ncond, result->as_register(), opr2->as_register()); 2000 } else if (opr2->is_double_cpu()) { 2001 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2002 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2003 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2004 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2005 } else if (opr2->is_single_stack()) { 2006 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2007 } else if (opr2->is_double_stack()) { 2008 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2009 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2010 } else { 2011 ShouldNotReachHere(); 2012 } 2013 2014 } else { 2015 Label skip; 2016 __ jcc (acond, skip); 2017 if (opr2->is_cpu_register()) { 2018 reg2reg(opr2, result); 2019 } else if (opr2->is_stack()) { 2020 stack2reg(opr2, result, result->type()); 2021 } else if (opr2->is_constant()) { 2022 const2reg(opr2, result, lir_patch_none, NULL); 2023 } else { 2024 ShouldNotReachHere(); 2025 } 2026 __ bind(skip); 2027 } 2028 } 2029 2030 2031 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2032 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2033 2034 if (left->is_single_cpu()) { 2035 assert(left == dest, "left and dest must be equal"); 2036 Register lreg = left->as_register(); 2037 2038 if (right->is_single_cpu()) { 2039 // cpu register - cpu register 2040 Register rreg = right->as_register(); 2041 switch (code) { 2042 case lir_add: __ addl (lreg, rreg); break; 2043 case lir_sub: __ subl (lreg, rreg); break; 2044 case lir_mul: __ imull(lreg, rreg); break; 2045 default: ShouldNotReachHere(); 2046 } 2047 2048 } else if (right->is_stack()) { 2049 // cpu register - stack 2050 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2051 switch (code) { 2052 case lir_add: __ addl(lreg, raddr); break; 2053 case lir_sub: __ subl(lreg, raddr); break; 2054 default: ShouldNotReachHere(); 2055 } 2056 2057 } else if (right->is_constant()) { 2058 // cpu register - constant 2059 jint c = right->as_constant_ptr()->as_jint(); 2060 switch (code) { 2061 case lir_add: { 2062 __ incrementl(lreg, c); 2063 break; 2064 } 2065 case lir_sub: { 2066 __ decrementl(lreg, c); 2067 break; 2068 } 2069 default: ShouldNotReachHere(); 2070 } 2071 2072 } else { 2073 ShouldNotReachHere(); 2074 } 2075 2076 } else if (left->is_double_cpu()) { 2077 assert(left == dest, "left and dest must be equal"); 2078 Register lreg_lo = left->as_register_lo(); 2079 Register lreg_hi = left->as_register_hi(); 2080 2081 if (right->is_double_cpu()) { 2082 // cpu register - cpu register 2083 Register rreg_lo = right->as_register_lo(); 2084 Register rreg_hi = right->as_register_hi(); 2085 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2086 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2087 switch (code) { 2088 case lir_add: 2089 __ addptr(lreg_lo, rreg_lo); 2090 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2091 break; 2092 case lir_sub: 2093 __ subptr(lreg_lo, rreg_lo); 2094 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2095 break; 2096 case lir_mul: 2097 #ifdef _LP64 2098 __ imulq(lreg_lo, rreg_lo); 2099 #else 2100 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2101 __ imull(lreg_hi, rreg_lo); 2102 __ imull(rreg_hi, lreg_lo); 2103 __ addl (rreg_hi, lreg_hi); 2104 __ mull (rreg_lo); 2105 __ addl (lreg_hi, rreg_hi); 2106 #endif // _LP64 2107 break; 2108 default: 2109 ShouldNotReachHere(); 2110 } 2111 2112 } else if (right->is_constant()) { 2113 // cpu register - constant 2114 #ifdef _LP64 2115 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2116 __ movptr(r10, (intptr_t) c); 2117 switch (code) { 2118 case lir_add: 2119 __ addptr(lreg_lo, r10); 2120 break; 2121 case lir_sub: 2122 __ subptr(lreg_lo, r10); 2123 break; 2124 default: 2125 ShouldNotReachHere(); 2126 } 2127 #else 2128 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2129 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2130 switch (code) { 2131 case lir_add: 2132 __ addptr(lreg_lo, c_lo); 2133 __ adcl(lreg_hi, c_hi); 2134 break; 2135 case lir_sub: 2136 __ subptr(lreg_lo, c_lo); 2137 __ sbbl(lreg_hi, c_hi); 2138 break; 2139 default: 2140 ShouldNotReachHere(); 2141 } 2142 #endif // _LP64 2143 2144 } else { 2145 ShouldNotReachHere(); 2146 } 2147 2148 } else if (left->is_single_xmm()) { 2149 assert(left == dest, "left and dest must be equal"); 2150 XMMRegister lreg = left->as_xmm_float_reg(); 2151 2152 if (right->is_single_xmm()) { 2153 XMMRegister rreg = right->as_xmm_float_reg(); 2154 switch (code) { 2155 case lir_add: __ addss(lreg, rreg); break; 2156 case lir_sub: __ subss(lreg, rreg); break; 2157 case lir_mul_strictfp: // fall through 2158 case lir_mul: __ mulss(lreg, rreg); break; 2159 case lir_div_strictfp: // fall through 2160 case lir_div: __ divss(lreg, rreg); break; 2161 default: ShouldNotReachHere(); 2162 } 2163 } else { 2164 Address raddr; 2165 if (right->is_single_stack()) { 2166 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2167 } else if (right->is_constant()) { 2168 // hack for now 2169 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2170 } else { 2171 ShouldNotReachHere(); 2172 } 2173 switch (code) { 2174 case lir_add: __ addss(lreg, raddr); break; 2175 case lir_sub: __ subss(lreg, raddr); break; 2176 case lir_mul_strictfp: // fall through 2177 case lir_mul: __ mulss(lreg, raddr); break; 2178 case lir_div_strictfp: // fall through 2179 case lir_div: __ divss(lreg, raddr); break; 2180 default: ShouldNotReachHere(); 2181 } 2182 } 2183 2184 } else if (left->is_double_xmm()) { 2185 assert(left == dest, "left and dest must be equal"); 2186 2187 XMMRegister lreg = left->as_xmm_double_reg(); 2188 if (right->is_double_xmm()) { 2189 XMMRegister rreg = right->as_xmm_double_reg(); 2190 switch (code) { 2191 case lir_add: __ addsd(lreg, rreg); break; 2192 case lir_sub: __ subsd(lreg, rreg); break; 2193 case lir_mul_strictfp: // fall through 2194 case lir_mul: __ mulsd(lreg, rreg); break; 2195 case lir_div_strictfp: // fall through 2196 case lir_div: __ divsd(lreg, rreg); break; 2197 default: ShouldNotReachHere(); 2198 } 2199 } else { 2200 Address raddr; 2201 if (right->is_double_stack()) { 2202 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2203 } else if (right->is_constant()) { 2204 // hack for now 2205 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2206 } else { 2207 ShouldNotReachHere(); 2208 } 2209 switch (code) { 2210 case lir_add: __ addsd(lreg, raddr); break; 2211 case lir_sub: __ subsd(lreg, raddr); break; 2212 case lir_mul_strictfp: // fall through 2213 case lir_mul: __ mulsd(lreg, raddr); break; 2214 case lir_div_strictfp: // fall through 2215 case lir_div: __ divsd(lreg, raddr); break; 2216 default: ShouldNotReachHere(); 2217 } 2218 } 2219 2220 } else if (left->is_single_fpu()) { 2221 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2222 2223 if (right->is_single_fpu()) { 2224 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2225 2226 } else { 2227 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2228 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2229 2230 Address raddr; 2231 if (right->is_single_stack()) { 2232 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2233 } else if (right->is_constant()) { 2234 address const_addr = float_constant(right->as_jfloat()); 2235 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2236 // hack for now 2237 raddr = __ as_Address(InternalAddress(const_addr)); 2238 } else { 2239 ShouldNotReachHere(); 2240 } 2241 2242 switch (code) { 2243 case lir_add: __ fadd_s(raddr); break; 2244 case lir_sub: __ fsub_s(raddr); break; 2245 case lir_mul_strictfp: // fall through 2246 case lir_mul: __ fmul_s(raddr); break; 2247 case lir_div_strictfp: // fall through 2248 case lir_div: __ fdiv_s(raddr); break; 2249 default: ShouldNotReachHere(); 2250 } 2251 } 2252 2253 } else if (left->is_double_fpu()) { 2254 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2255 2256 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2257 // Double values require special handling for strictfp mul/div on x86 2258 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2259 __ fmulp(left->fpu_regnrLo() + 1); 2260 } 2261 2262 if (right->is_double_fpu()) { 2263 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2264 2265 } else { 2266 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2267 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2268 2269 Address raddr; 2270 if (right->is_double_stack()) { 2271 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2272 } else if (right->is_constant()) { 2273 // hack for now 2274 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2275 } else { 2276 ShouldNotReachHere(); 2277 } 2278 2279 switch (code) { 2280 case lir_add: __ fadd_d(raddr); break; 2281 case lir_sub: __ fsub_d(raddr); break; 2282 case lir_mul_strictfp: // fall through 2283 case lir_mul: __ fmul_d(raddr); break; 2284 case lir_div_strictfp: // fall through 2285 case lir_div: __ fdiv_d(raddr); break; 2286 default: ShouldNotReachHere(); 2287 } 2288 } 2289 2290 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2291 // Double values require special handling for strictfp mul/div on x86 2292 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2293 __ fmulp(dest->fpu_regnrLo() + 1); 2294 } 2295 2296 } else if (left->is_single_stack() || left->is_address()) { 2297 assert(left == dest, "left and dest must be equal"); 2298 2299 Address laddr; 2300 if (left->is_single_stack()) { 2301 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2302 } else if (left->is_address()) { 2303 laddr = as_Address(left->as_address_ptr()); 2304 } else { 2305 ShouldNotReachHere(); 2306 } 2307 2308 if (right->is_single_cpu()) { 2309 Register rreg = right->as_register(); 2310 switch (code) { 2311 case lir_add: __ addl(laddr, rreg); break; 2312 case lir_sub: __ subl(laddr, rreg); break; 2313 default: ShouldNotReachHere(); 2314 } 2315 } else if (right->is_constant()) { 2316 jint c = right->as_constant_ptr()->as_jint(); 2317 switch (code) { 2318 case lir_add: { 2319 __ incrementl(laddr, c); 2320 break; 2321 } 2322 case lir_sub: { 2323 __ decrementl(laddr, c); 2324 break; 2325 } 2326 default: ShouldNotReachHere(); 2327 } 2328 } else { 2329 ShouldNotReachHere(); 2330 } 2331 2332 } else { 2333 ShouldNotReachHere(); 2334 } 2335 } 2336 2337 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2338 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2339 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2340 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2341 2342 bool left_is_tos = (left_index == 0); 2343 bool dest_is_tos = (dest_index == 0); 2344 int non_tos_index = (left_is_tos ? right_index : left_index); 2345 2346 switch (code) { 2347 case lir_add: 2348 if (pop_fpu_stack) __ faddp(non_tos_index); 2349 else if (dest_is_tos) __ fadd (non_tos_index); 2350 else __ fadda(non_tos_index); 2351 break; 2352 2353 case lir_sub: 2354 if (left_is_tos) { 2355 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2356 else if (dest_is_tos) __ fsub (non_tos_index); 2357 else __ fsubra(non_tos_index); 2358 } else { 2359 if (pop_fpu_stack) __ fsubp (non_tos_index); 2360 else if (dest_is_tos) __ fsubr (non_tos_index); 2361 else __ fsuba (non_tos_index); 2362 } 2363 break; 2364 2365 case lir_mul_strictfp: // fall through 2366 case lir_mul: 2367 if (pop_fpu_stack) __ fmulp(non_tos_index); 2368 else if (dest_is_tos) __ fmul (non_tos_index); 2369 else __ fmula(non_tos_index); 2370 break; 2371 2372 case lir_div_strictfp: // fall through 2373 case lir_div: 2374 if (left_is_tos) { 2375 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2376 else if (dest_is_tos) __ fdiv (non_tos_index); 2377 else __ fdivra(non_tos_index); 2378 } else { 2379 if (pop_fpu_stack) __ fdivp (non_tos_index); 2380 else if (dest_is_tos) __ fdivr (non_tos_index); 2381 else __ fdiva (non_tos_index); 2382 } 2383 break; 2384 2385 case lir_rem: 2386 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2387 __ fremr(noreg); 2388 break; 2389 2390 default: 2391 ShouldNotReachHere(); 2392 } 2393 } 2394 2395 2396 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2397 if (value->is_double_xmm()) { 2398 switch(code) { 2399 case lir_abs : 2400 { 2401 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2402 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2403 } 2404 __ andpd(dest->as_xmm_double_reg(), 2405 ExternalAddress((address)double_signmask_pool)); 2406 } 2407 break; 2408 2409 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2410 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2411 default : ShouldNotReachHere(); 2412 } 2413 2414 } else if (value->is_double_fpu()) { 2415 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2416 switch(code) { 2417 case lir_abs : __ fabs() ; break; 2418 case lir_sqrt : __ fsqrt(); break; 2419 default : ShouldNotReachHere(); 2420 } 2421 } else { 2422 Unimplemented(); 2423 } 2424 } 2425 2426 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2427 // assert(left->destroys_register(), "check"); 2428 if (left->is_single_cpu()) { 2429 Register reg = left->as_register(); 2430 if (right->is_constant()) { 2431 int val = right->as_constant_ptr()->as_jint(); 2432 switch (code) { 2433 case lir_logic_and: __ andl (reg, val); break; 2434 case lir_logic_or: __ orl (reg, val); break; 2435 case lir_logic_xor: __ xorl (reg, val); break; 2436 default: ShouldNotReachHere(); 2437 } 2438 } else if (right->is_stack()) { 2439 // added support for stack operands 2440 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2441 switch (code) { 2442 case lir_logic_and: __ andl (reg, raddr); break; 2443 case lir_logic_or: __ orl (reg, raddr); break; 2444 case lir_logic_xor: __ xorl (reg, raddr); break; 2445 default: ShouldNotReachHere(); 2446 } 2447 } else { 2448 Register rright = right->as_register(); 2449 switch (code) { 2450 case lir_logic_and: __ andptr (reg, rright); break; 2451 case lir_logic_or : __ orptr (reg, rright); break; 2452 case lir_logic_xor: __ xorptr (reg, rright); break; 2453 default: ShouldNotReachHere(); 2454 } 2455 } 2456 move_regs(reg, dst->as_register()); 2457 } else { 2458 Register l_lo = left->as_register_lo(); 2459 Register l_hi = left->as_register_hi(); 2460 if (right->is_constant()) { 2461 #ifdef _LP64 2462 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2463 switch (code) { 2464 case lir_logic_and: 2465 __ andq(l_lo, rscratch1); 2466 break; 2467 case lir_logic_or: 2468 __ orq(l_lo, rscratch1); 2469 break; 2470 case lir_logic_xor: 2471 __ xorq(l_lo, rscratch1); 2472 break; 2473 default: ShouldNotReachHere(); 2474 } 2475 #else 2476 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2477 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2478 switch (code) { 2479 case lir_logic_and: 2480 __ andl(l_lo, r_lo); 2481 __ andl(l_hi, r_hi); 2482 break; 2483 case lir_logic_or: 2484 __ orl(l_lo, r_lo); 2485 __ orl(l_hi, r_hi); 2486 break; 2487 case lir_logic_xor: 2488 __ xorl(l_lo, r_lo); 2489 __ xorl(l_hi, r_hi); 2490 break; 2491 default: ShouldNotReachHere(); 2492 } 2493 #endif // _LP64 2494 } else { 2495 #ifdef _LP64 2496 Register r_lo; 2497 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2498 r_lo = right->as_register(); 2499 } else { 2500 r_lo = right->as_register_lo(); 2501 } 2502 #else 2503 Register r_lo = right->as_register_lo(); 2504 Register r_hi = right->as_register_hi(); 2505 assert(l_lo != r_hi, "overwriting registers"); 2506 #endif 2507 switch (code) { 2508 case lir_logic_and: 2509 __ andptr(l_lo, r_lo); 2510 NOT_LP64(__ andptr(l_hi, r_hi);) 2511 break; 2512 case lir_logic_or: 2513 __ orptr(l_lo, r_lo); 2514 NOT_LP64(__ orptr(l_hi, r_hi);) 2515 break; 2516 case lir_logic_xor: 2517 __ xorptr(l_lo, r_lo); 2518 NOT_LP64(__ xorptr(l_hi, r_hi);) 2519 break; 2520 default: ShouldNotReachHere(); 2521 } 2522 } 2523 2524 Register dst_lo = dst->as_register_lo(); 2525 Register dst_hi = dst->as_register_hi(); 2526 2527 #ifdef _LP64 2528 move_regs(l_lo, dst_lo); 2529 #else 2530 if (dst_lo == l_hi) { 2531 assert(dst_hi != l_lo, "overwriting registers"); 2532 move_regs(l_hi, dst_hi); 2533 move_regs(l_lo, dst_lo); 2534 } else { 2535 assert(dst_lo != l_hi, "overwriting registers"); 2536 move_regs(l_lo, dst_lo); 2537 move_regs(l_hi, dst_hi); 2538 } 2539 #endif // _LP64 2540 } 2541 } 2542 2543 2544 // we assume that rax, and rdx can be overwritten 2545 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2546 2547 assert(left->is_single_cpu(), "left must be register"); 2548 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2549 assert(result->is_single_cpu(), "result must be register"); 2550 2551 // assert(left->destroys_register(), "check"); 2552 // assert(right->destroys_register(), "check"); 2553 2554 Register lreg = left->as_register(); 2555 Register dreg = result->as_register(); 2556 2557 if (right->is_constant()) { 2558 int divisor = right->as_constant_ptr()->as_jint(); 2559 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2560 if (code == lir_idiv) { 2561 assert(lreg == rax, "must be rax,"); 2562 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2563 __ cdql(); // sign extend into rdx:rax 2564 if (divisor == 2) { 2565 __ subl(lreg, rdx); 2566 } else { 2567 __ andl(rdx, divisor - 1); 2568 __ addl(lreg, rdx); 2569 } 2570 __ sarl(lreg, log2_intptr(divisor)); 2571 move_regs(lreg, dreg); 2572 } else if (code == lir_irem) { 2573 Label done; 2574 __ mov(dreg, lreg); 2575 __ andl(dreg, 0x80000000 | (divisor - 1)); 2576 __ jcc(Assembler::positive, done); 2577 __ decrement(dreg); 2578 __ orl(dreg, ~(divisor - 1)); 2579 __ increment(dreg); 2580 __ bind(done); 2581 } else { 2582 ShouldNotReachHere(); 2583 } 2584 } else { 2585 Register rreg = right->as_register(); 2586 assert(lreg == rax, "left register must be rax,"); 2587 assert(rreg != rdx, "right register must not be rdx"); 2588 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2589 2590 move_regs(lreg, rax); 2591 2592 int idivl_offset = __ corrected_idivl(rreg); 2593 if (ImplicitDiv0Checks) { 2594 add_debug_info_for_div0(idivl_offset, info); 2595 } 2596 if (code == lir_irem) { 2597 move_regs(rdx, dreg); // result is in rdx 2598 } else { 2599 move_regs(rax, dreg); 2600 } 2601 } 2602 } 2603 2604 2605 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2606 if (opr1->is_single_cpu()) { 2607 Register reg1 = opr1->as_register(); 2608 if (opr2->is_single_cpu()) { 2609 // cpu register - cpu register 2610 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2611 __ cmpoop(reg1, opr2->as_register()); 2612 } else { 2613 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2614 __ cmpl(reg1, opr2->as_register()); 2615 } 2616 } else if (opr2->is_stack()) { 2617 // cpu register - stack 2618 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2619 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2620 } else { 2621 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2622 } 2623 } else if (opr2->is_constant()) { 2624 // cpu register - constant 2625 LIR_Const* c = opr2->as_constant_ptr(); 2626 if (c->type() == T_INT) { 2627 __ cmpl(reg1, c->as_jint()); 2628 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2629 // In 64bit oops are single register 2630 jobject o = c->as_jobject(); 2631 if (o == NULL) { 2632 __ cmpptr(reg1, (int32_t)NULL_WORD); 2633 } else { 2634 __ cmpoop(reg1, o); 2635 } 2636 } else { 2637 fatal("unexpected type: %s", basictype_to_str(c->type())); 2638 } 2639 // cpu register - address 2640 } else if (opr2->is_address()) { 2641 if (op->info() != NULL) { 2642 add_debug_info_for_null_check_here(op->info()); 2643 } 2644 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2645 } else { 2646 ShouldNotReachHere(); 2647 } 2648 2649 } else if(opr1->is_double_cpu()) { 2650 Register xlo = opr1->as_register_lo(); 2651 Register xhi = opr1->as_register_hi(); 2652 if (opr2->is_double_cpu()) { 2653 #ifdef _LP64 2654 __ cmpptr(xlo, opr2->as_register_lo()); 2655 #else 2656 // cpu register - cpu register 2657 Register ylo = opr2->as_register_lo(); 2658 Register yhi = opr2->as_register_hi(); 2659 __ subl(xlo, ylo); 2660 __ sbbl(xhi, yhi); 2661 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2662 __ orl(xhi, xlo); 2663 } 2664 #endif // _LP64 2665 } else if (opr2->is_constant()) { 2666 // cpu register - constant 0 2667 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2668 #ifdef _LP64 2669 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2670 #else 2671 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2672 __ orl(xhi, xlo); 2673 #endif // _LP64 2674 } else { 2675 ShouldNotReachHere(); 2676 } 2677 2678 } else if (opr1->is_single_xmm()) { 2679 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2680 if (opr2->is_single_xmm()) { 2681 // xmm register - xmm register 2682 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2683 } else if (opr2->is_stack()) { 2684 // xmm register - stack 2685 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2686 } else if (opr2->is_constant()) { 2687 // xmm register - constant 2688 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2689 } else if (opr2->is_address()) { 2690 // xmm register - address 2691 if (op->info() != NULL) { 2692 add_debug_info_for_null_check_here(op->info()); 2693 } 2694 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2695 } else { 2696 ShouldNotReachHere(); 2697 } 2698 2699 } else if (opr1->is_double_xmm()) { 2700 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2701 if (opr2->is_double_xmm()) { 2702 // xmm register - xmm register 2703 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2704 } else if (opr2->is_stack()) { 2705 // xmm register - stack 2706 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2707 } else if (opr2->is_constant()) { 2708 // xmm register - constant 2709 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2710 } else if (opr2->is_address()) { 2711 // xmm register - address 2712 if (op->info() != NULL) { 2713 add_debug_info_for_null_check_here(op->info()); 2714 } 2715 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2716 } else { 2717 ShouldNotReachHere(); 2718 } 2719 2720 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2721 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2722 assert(opr2->is_fpu_register(), "both must be registers"); 2723 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2724 2725 } else if (opr1->is_address() && opr2->is_constant()) { 2726 LIR_Const* c = opr2->as_constant_ptr(); 2727 #ifdef _LP64 2728 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2729 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2730 __ movoop(rscratch1, c->as_jobject()); 2731 } 2732 #endif // LP64 2733 if (op->info() != NULL) { 2734 add_debug_info_for_null_check_here(op->info()); 2735 } 2736 // special case: address - constant 2737 LIR_Address* addr = opr1->as_address_ptr(); 2738 if (c->type() == T_INT) { 2739 __ cmpl(as_Address(addr), c->as_jint()); 2740 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2741 #ifdef _LP64 2742 // %%% Make this explode if addr isn't reachable until we figure out a 2743 // better strategy by giving noreg as the temp for as_Address 2744 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2745 #else 2746 __ cmpoop(as_Address(addr), c->as_jobject()); 2747 #endif // _LP64 2748 } else { 2749 ShouldNotReachHere(); 2750 } 2751 2752 } else { 2753 ShouldNotReachHere(); 2754 } 2755 } 2756 2757 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2758 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2759 if (left->is_single_xmm()) { 2760 assert(right->is_single_xmm(), "must match"); 2761 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2762 } else if (left->is_double_xmm()) { 2763 assert(right->is_double_xmm(), "must match"); 2764 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2765 2766 } else { 2767 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2768 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2769 2770 assert(left->fpu() == 0, "left must be on TOS"); 2771 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2772 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2773 } 2774 } else { 2775 assert(code == lir_cmp_l2i, "check"); 2776 #ifdef _LP64 2777 Label done; 2778 Register dest = dst->as_register(); 2779 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2780 __ movl(dest, -1); 2781 __ jccb(Assembler::less, done); 2782 __ set_byte_if_not_zero(dest); 2783 __ movzbl(dest, dest); 2784 __ bind(done); 2785 #else 2786 __ lcmp2int(left->as_register_hi(), 2787 left->as_register_lo(), 2788 right->as_register_hi(), 2789 right->as_register_lo()); 2790 move_regs(left->as_register_hi(), dst->as_register()); 2791 #endif // _LP64 2792 } 2793 } 2794 2795 2796 void LIR_Assembler::align_call(LIR_Code code) { 2797 if (os::is_MP()) { 2798 // make sure that the displacement word of the call ends up word aligned 2799 int offset = __ offset(); 2800 switch (code) { 2801 case lir_static_call: 2802 case lir_optvirtual_call: 2803 case lir_dynamic_call: 2804 offset += NativeCall::displacement_offset; 2805 break; 2806 case lir_icvirtual_call: 2807 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2808 break; 2809 case lir_virtual_call: // currently, sparc-specific for niagara 2810 default: ShouldNotReachHere(); 2811 } 2812 __ align(BytesPerWord, offset); 2813 } 2814 } 2815 2816 2817 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2818 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2819 "must be aligned"); 2820 __ call(AddressLiteral(op->addr(), rtype)); 2821 add_call_info(code_offset(), op->info()); 2822 } 2823 2824 2825 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2826 __ ic_call(op->addr()); 2827 add_call_info(code_offset(), op->info()); 2828 assert(!os::is_MP() || 2829 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2830 "must be aligned"); 2831 } 2832 2833 2834 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2835 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2836 ShouldNotReachHere(); 2837 } 2838 2839 2840 void LIR_Assembler::emit_static_call_stub() { 2841 address call_pc = __ pc(); 2842 address stub = __ start_a_stub(call_stub_size()); 2843 if (stub == NULL) { 2844 bailout("static call stub overflow"); 2845 return; 2846 } 2847 2848 int start = __ offset(); 2849 if (os::is_MP()) { 2850 // make sure that the displacement word of the call ends up word aligned 2851 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2852 } 2853 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2854 __ mov_metadata(rbx, (Metadata*)NULL); 2855 // must be set to -1 at code generation time 2856 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2857 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2858 __ jump(RuntimeAddress(__ pc())); 2859 2860 if (UseAOT) { 2861 // Trampoline to aot code 2862 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2863 #ifdef _LP64 2864 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2865 #else 2866 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2867 #endif 2868 __ jmp(rax); 2869 } 2870 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2871 __ end_a_stub(); 2872 } 2873 2874 2875 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2876 assert(exceptionOop->as_register() == rax, "must match"); 2877 assert(exceptionPC->as_register() == rdx, "must match"); 2878 2879 // exception object is not added to oop map by LinearScan 2880 // (LinearScan assumes that no oops are in fixed registers) 2881 info->add_register_oop(exceptionOop); 2882 Runtime1::StubID unwind_id; 2883 2884 // get current pc information 2885 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2886 int pc_for_athrow_offset = __ offset(); 2887 InternalAddress pc_for_athrow(__ pc()); 2888 __ lea(exceptionPC->as_register(), pc_for_athrow); 2889 add_call_info(pc_for_athrow_offset, info); // for exception handler 2890 2891 __ verify_not_null_oop(rax); 2892 // search an exception handler (rax: exception oop, rdx: throwing pc) 2893 if (compilation()->has_fpu_code()) { 2894 unwind_id = Runtime1::handle_exception_id; 2895 } else { 2896 unwind_id = Runtime1::handle_exception_nofpu_id; 2897 } 2898 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2899 2900 // enough room for two byte trap 2901 __ nop(); 2902 } 2903 2904 2905 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2906 assert(exceptionOop->as_register() == rax, "must match"); 2907 2908 __ jmp(_unwind_handler_entry); 2909 } 2910 2911 2912 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2913 2914 // optimized version for linear scan: 2915 // * count must be already in ECX (guaranteed by LinearScan) 2916 // * left and dest must be equal 2917 // * tmp must be unused 2918 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2919 assert(left == dest, "left and dest must be equal"); 2920 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2921 2922 if (left->is_single_cpu()) { 2923 Register value = left->as_register(); 2924 assert(value != SHIFT_count, "left cannot be ECX"); 2925 2926 switch (code) { 2927 case lir_shl: __ shll(value); break; 2928 case lir_shr: __ sarl(value); break; 2929 case lir_ushr: __ shrl(value); break; 2930 default: ShouldNotReachHere(); 2931 } 2932 } else if (left->is_double_cpu()) { 2933 Register lo = left->as_register_lo(); 2934 Register hi = left->as_register_hi(); 2935 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2936 #ifdef _LP64 2937 switch (code) { 2938 case lir_shl: __ shlptr(lo); break; 2939 case lir_shr: __ sarptr(lo); break; 2940 case lir_ushr: __ shrptr(lo); break; 2941 default: ShouldNotReachHere(); 2942 } 2943 #else 2944 2945 switch (code) { 2946 case lir_shl: __ lshl(hi, lo); break; 2947 case lir_shr: __ lshr(hi, lo, true); break; 2948 case lir_ushr: __ lshr(hi, lo, false); break; 2949 default: ShouldNotReachHere(); 2950 } 2951 #endif // LP64 2952 } else { 2953 ShouldNotReachHere(); 2954 } 2955 } 2956 2957 2958 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2959 if (dest->is_single_cpu()) { 2960 // first move left into dest so that left is not destroyed by the shift 2961 Register value = dest->as_register(); 2962 count = count & 0x1F; // Java spec 2963 2964 move_regs(left->as_register(), value); 2965 switch (code) { 2966 case lir_shl: __ shll(value, count); break; 2967 case lir_shr: __ sarl(value, count); break; 2968 case lir_ushr: __ shrl(value, count); break; 2969 default: ShouldNotReachHere(); 2970 } 2971 } else if (dest->is_double_cpu()) { 2972 #ifndef _LP64 2973 Unimplemented(); 2974 #else 2975 // first move left into dest so that left is not destroyed by the shift 2976 Register value = dest->as_register_lo(); 2977 count = count & 0x1F; // Java spec 2978 2979 move_regs(left->as_register_lo(), value); 2980 switch (code) { 2981 case lir_shl: __ shlptr(value, count); break; 2982 case lir_shr: __ sarptr(value, count); break; 2983 case lir_ushr: __ shrptr(value, count); break; 2984 default: ShouldNotReachHere(); 2985 } 2986 #endif // _LP64 2987 } else { 2988 ShouldNotReachHere(); 2989 } 2990 } 2991 2992 2993 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2994 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2995 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2996 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2997 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2998 } 2999 3000 3001 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3002 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3003 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3004 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3005 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3006 } 3007 3008 3009 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3010 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3011 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3012 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3013 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3014 } 3015 3016 3017 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3018 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3019 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3020 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3021 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3022 } 3023 3024 3025 // This code replaces a call to arraycopy; no exception may 3026 // be thrown in this code, they must be thrown in the System.arraycopy 3027 // activation frame; we could save some checks if this would not be the case 3028 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3029 ciArrayKlass* default_type = op->expected_type(); 3030 Register src = op->src()->as_register(); 3031 Register dst = op->dst()->as_register(); 3032 Register src_pos = op->src_pos()->as_register(); 3033 Register dst_pos = op->dst_pos()->as_register(); 3034 Register length = op->length()->as_register(); 3035 Register tmp = op->tmp()->as_register(); 3036 3037 CodeStub* stub = op->stub(); 3038 int flags = op->flags(); 3039 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3040 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3041 3042 // if we don't know anything, just go through the generic arraycopy 3043 if (default_type == NULL) { 3044 Label done; 3045 // save outgoing arguments on stack in case call to System.arraycopy is needed 3046 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3047 // for interpreter calling conventions. Now we have to do it in new style conventions. 3048 // For the moment until C1 gets the new register allocator I just force all the 3049 // args to the right place (except the register args) and then on the back side 3050 // reload the register args properly if we go slow path. Yuck 3051 3052 // These are proper for the calling convention 3053 store_parameter(length, 2); 3054 store_parameter(dst_pos, 1); 3055 store_parameter(dst, 0); 3056 3057 // these are just temporary placements until we need to reload 3058 store_parameter(src_pos, 3); 3059 store_parameter(src, 4); 3060 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3061 3062 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3063 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 3064 3065 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3066 #ifdef _LP64 3067 // The arguments are in java calling convention so we can trivially shift them to C 3068 // convention 3069 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3070 __ mov(c_rarg0, j_rarg0); 3071 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3072 __ mov(c_rarg1, j_rarg1); 3073 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3074 __ mov(c_rarg2, j_rarg2); 3075 assert_different_registers(c_rarg3, j_rarg4); 3076 __ mov(c_rarg3, j_rarg3); 3077 #ifdef _WIN64 3078 // Allocate abi space for args but be sure to keep stack aligned 3079 __ subptr(rsp, 6*wordSize); 3080 store_parameter(j_rarg4, 4); 3081 #ifndef PRODUCT 3082 if (PrintC1Statistics) { 3083 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3084 } 3085 #endif 3086 __ call(RuntimeAddress(copyfunc_addr)); 3087 __ addptr(rsp, 6*wordSize); 3088 #else 3089 __ mov(c_rarg4, j_rarg4); 3090 #ifndef PRODUCT 3091 if (PrintC1Statistics) { 3092 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3093 } 3094 #endif 3095 __ call(RuntimeAddress(copyfunc_addr)); 3096 #endif // _WIN64 3097 #else 3098 __ push(length); 3099 __ push(dst_pos); 3100 __ push(dst); 3101 __ push(src_pos); 3102 __ push(src); 3103 3104 #ifndef PRODUCT 3105 if (PrintC1Statistics) { 3106 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3107 } 3108 #endif 3109 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3110 3111 #endif // _LP64 3112 3113 __ cmpl(rax, 0); 3114 __ jcc(Assembler::equal, *stub->continuation()); 3115 3116 __ mov(tmp, rax); 3117 __ xorl(tmp, -1); 3118 3119 // Reload values from the stack so they are where the stub 3120 // expects them. 3121 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3122 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3123 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3124 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3125 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3126 3127 __ subl(length, tmp); 3128 __ addl(src_pos, tmp); 3129 __ addl(dst_pos, tmp); 3130 __ jmp(*stub->entry()); 3131 3132 __ bind(*stub->continuation()); 3133 return; 3134 } 3135 3136 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3137 3138 int elem_size = type2aelembytes(basic_type); 3139 Address::ScaleFactor scale; 3140 3141 switch (elem_size) { 3142 case 1 : 3143 scale = Address::times_1; 3144 break; 3145 case 2 : 3146 scale = Address::times_2; 3147 break; 3148 case 4 : 3149 scale = Address::times_4; 3150 break; 3151 case 8 : 3152 scale = Address::times_8; 3153 break; 3154 default: 3155 scale = Address::no_scale; 3156 ShouldNotReachHere(); 3157 } 3158 3159 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3160 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3161 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3162 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3163 3164 // length and pos's are all sign extended at this point on 64bit 3165 3166 // test for NULL 3167 if (flags & LIR_OpArrayCopy::src_null_check) { 3168 __ testptr(src, src); 3169 __ jcc(Assembler::zero, *stub->entry()); 3170 } 3171 if (flags & LIR_OpArrayCopy::dst_null_check) { 3172 __ testptr(dst, dst); 3173 __ jcc(Assembler::zero, *stub->entry()); 3174 } 3175 3176 // If the compiler was not able to prove that exact type of the source or the destination 3177 // of the arraycopy is an array type, check at runtime if the source or the destination is 3178 // an instance type. 3179 if (flags & LIR_OpArrayCopy::type_check) { 3180 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3181 __ load_klass(tmp, dst); 3182 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3183 __ jcc(Assembler::greaterEqual, *stub->entry()); 3184 } 3185 3186 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3187 __ load_klass(tmp, src); 3188 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3189 __ jcc(Assembler::greaterEqual, *stub->entry()); 3190 } 3191 } 3192 3193 // check if negative 3194 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3195 __ testl(src_pos, src_pos); 3196 __ jcc(Assembler::less, *stub->entry()); 3197 } 3198 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3199 __ testl(dst_pos, dst_pos); 3200 __ jcc(Assembler::less, *stub->entry()); 3201 } 3202 3203 if (flags & LIR_OpArrayCopy::src_range_check) { 3204 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3205 __ cmpl(tmp, src_length_addr); 3206 __ jcc(Assembler::above, *stub->entry()); 3207 } 3208 if (flags & LIR_OpArrayCopy::dst_range_check) { 3209 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3210 __ cmpl(tmp, dst_length_addr); 3211 __ jcc(Assembler::above, *stub->entry()); 3212 } 3213 3214 if (flags & LIR_OpArrayCopy::length_positive_check) { 3215 __ testl(length, length); 3216 __ jcc(Assembler::less, *stub->entry()); 3217 } 3218 3219 #ifdef _LP64 3220 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3221 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3222 #endif 3223 3224 if (flags & LIR_OpArrayCopy::type_check) { 3225 // We don't know the array types are compatible 3226 if (basic_type != T_OBJECT) { 3227 // Simple test for basic type arrays 3228 if (UseCompressedClassPointers) { 3229 __ movl(tmp, src_klass_addr); 3230 __ cmpl(tmp, dst_klass_addr); 3231 } else { 3232 __ movptr(tmp, src_klass_addr); 3233 __ cmpptr(tmp, dst_klass_addr); 3234 } 3235 __ jcc(Assembler::notEqual, *stub->entry()); 3236 } else { 3237 // For object arrays, if src is a sub class of dst then we can 3238 // safely do the copy. 3239 Label cont, slow; 3240 3241 __ push(src); 3242 __ push(dst); 3243 3244 __ load_klass(src, src); 3245 __ load_klass(dst, dst); 3246 3247 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3248 3249 __ push(src); 3250 __ push(dst); 3251 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3252 __ pop(dst); 3253 __ pop(src); 3254 3255 __ cmpl(src, 0); 3256 __ jcc(Assembler::notEqual, cont); 3257 3258 __ bind(slow); 3259 __ pop(dst); 3260 __ pop(src); 3261 3262 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3263 if (copyfunc_addr != NULL) { // use stub if available 3264 // src is not a sub class of dst so we have to do a 3265 // per-element check. 3266 3267 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3268 if ((flags & mask) != mask) { 3269 // Check that at least both of them object arrays. 3270 assert(flags & mask, "one of the two should be known to be an object array"); 3271 3272 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3273 __ load_klass(tmp, src); 3274 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3275 __ load_klass(tmp, dst); 3276 } 3277 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3278 Address klass_lh_addr(tmp, lh_offset); 3279 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3280 __ cmpl(klass_lh_addr, objArray_lh); 3281 __ jcc(Assembler::notEqual, *stub->entry()); 3282 } 3283 3284 // Spill because stubs can use any register they like and it's 3285 // easier to restore just those that we care about. 3286 store_parameter(dst, 0); 3287 store_parameter(dst_pos, 1); 3288 store_parameter(length, 2); 3289 store_parameter(src_pos, 3); 3290 store_parameter(src, 4); 3291 3292 #ifndef _LP64 3293 __ movptr(tmp, dst_klass_addr); 3294 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3295 __ push(tmp); 3296 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3297 __ push(tmp); 3298 __ push(length); 3299 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3300 __ push(tmp); 3301 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3302 __ push(tmp); 3303 3304 __ call_VM_leaf(copyfunc_addr, 5); 3305 #else 3306 __ movl2ptr(length, length); //higher 32bits must be null 3307 3308 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3309 assert_different_registers(c_rarg0, dst, dst_pos, length); 3310 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3311 assert_different_registers(c_rarg1, dst, length); 3312 3313 __ mov(c_rarg2, length); 3314 assert_different_registers(c_rarg2, dst); 3315 3316 #ifdef _WIN64 3317 // Allocate abi space for args but be sure to keep stack aligned 3318 __ subptr(rsp, 6*wordSize); 3319 __ load_klass(c_rarg3, dst); 3320 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3321 store_parameter(c_rarg3, 4); 3322 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3323 __ call(RuntimeAddress(copyfunc_addr)); 3324 __ addptr(rsp, 6*wordSize); 3325 #else 3326 __ load_klass(c_rarg4, dst); 3327 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3328 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3329 __ call(RuntimeAddress(copyfunc_addr)); 3330 #endif 3331 3332 #endif 3333 3334 #ifndef PRODUCT 3335 if (PrintC1Statistics) { 3336 Label failed; 3337 __ testl(rax, rax); 3338 __ jcc(Assembler::notZero, failed); 3339 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3340 __ bind(failed); 3341 } 3342 #endif 3343 3344 __ testl(rax, rax); 3345 __ jcc(Assembler::zero, *stub->continuation()); 3346 3347 #ifndef PRODUCT 3348 if (PrintC1Statistics) { 3349 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3350 } 3351 #endif 3352 3353 __ mov(tmp, rax); 3354 3355 __ xorl(tmp, -1); 3356 3357 // Restore previously spilled arguments 3358 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3359 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3360 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3361 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3362 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3363 3364 3365 __ subl(length, tmp); 3366 __ addl(src_pos, tmp); 3367 __ addl(dst_pos, tmp); 3368 } 3369 3370 __ jmp(*stub->entry()); 3371 3372 __ bind(cont); 3373 __ pop(dst); 3374 __ pop(src); 3375 } 3376 } 3377 3378 #ifdef ASSERT 3379 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3380 // Sanity check the known type with the incoming class. For the 3381 // primitive case the types must match exactly with src.klass and 3382 // dst.klass each exactly matching the default type. For the 3383 // object array case, if no type check is needed then either the 3384 // dst type is exactly the expected type and the src type is a 3385 // subtype which we can't check or src is the same array as dst 3386 // but not necessarily exactly of type default_type. 3387 Label known_ok, halt; 3388 __ mov_metadata(tmp, default_type->constant_encoding()); 3389 #ifdef _LP64 3390 if (UseCompressedClassPointers) { 3391 __ encode_klass_not_null(tmp); 3392 } 3393 #endif 3394 3395 if (basic_type != T_OBJECT) { 3396 3397 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3398 else __ cmpptr(tmp, dst_klass_addr); 3399 __ jcc(Assembler::notEqual, halt); 3400 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3401 else __ cmpptr(tmp, src_klass_addr); 3402 __ jcc(Assembler::equal, known_ok); 3403 } else { 3404 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3405 else __ cmpptr(tmp, dst_klass_addr); 3406 __ jcc(Assembler::equal, known_ok); 3407 __ cmpptr(src, dst); 3408 __ jcc(Assembler::equal, known_ok); 3409 } 3410 __ bind(halt); 3411 __ stop("incorrect type information in arraycopy"); 3412 __ bind(known_ok); 3413 } 3414 #endif 3415 3416 #ifndef PRODUCT 3417 if (PrintC1Statistics) { 3418 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3419 } 3420 #endif 3421 3422 #ifdef _LP64 3423 assert_different_registers(c_rarg0, dst, dst_pos, length); 3424 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3425 assert_different_registers(c_rarg1, length); 3426 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3427 __ mov(c_rarg2, length); 3428 3429 #else 3430 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3431 store_parameter(tmp, 0); 3432 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3433 store_parameter(tmp, 1); 3434 store_parameter(length, 2); 3435 #endif // _LP64 3436 3437 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3438 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3439 const char *name; 3440 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3441 __ call_VM_leaf(entry, 0); 3442 3443 __ bind(*stub->continuation()); 3444 } 3445 3446 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3447 assert(op->crc()->is_single_cpu(), "crc must be register"); 3448 assert(op->val()->is_single_cpu(), "byte value must be register"); 3449 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3450 Register crc = op->crc()->as_register(); 3451 Register val = op->val()->as_register(); 3452 Register res = op->result_opr()->as_register(); 3453 3454 assert_different_registers(val, crc, res); 3455 3456 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3457 __ notl(crc); // ~crc 3458 __ update_byte_crc32(crc, val, res); 3459 __ notl(crc); // ~crc 3460 __ mov(res, crc); 3461 } 3462 3463 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3464 Register obj = op->obj_opr()->as_register(); // may not be an oop 3465 Register hdr = op->hdr_opr()->as_register(); 3466 Register lock = op->lock_opr()->as_register(); 3467 if (!UseFastLocking) { 3468 __ jmp(*op->stub()->entry()); 3469 } else if (op->code() == lir_lock) { 3470 Register scratch = noreg; 3471 if (UseBiasedLocking) { 3472 scratch = op->scratch_opr()->as_register(); 3473 } 3474 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3475 // add debug info for NullPointerException only if one is possible 3476 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3477 if (op->info() != NULL) { 3478 add_debug_info_for_null_check(null_check_offset, op->info()); 3479 } 3480 // done 3481 } else if (op->code() == lir_unlock) { 3482 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3483 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3484 } else { 3485 Unimplemented(); 3486 } 3487 __ bind(*op->stub()->continuation()); 3488 } 3489 3490 3491 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3492 ciMethod* method = op->profiled_method(); 3493 int bci = op->profiled_bci(); 3494 ciMethod* callee = op->profiled_callee(); 3495 3496 // Update counter for all call types 3497 ciMethodData* md = method->method_data_or_null(); 3498 assert(md != NULL, "Sanity"); 3499 ciProfileData* data = md->bci_to_data(bci); 3500 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 3501 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3502 Register mdo = op->mdo()->as_register(); 3503 __ mov_metadata(mdo, md->constant_encoding()); 3504 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3505 // Perform additional virtual call profiling for invokevirtual and 3506 // invokeinterface bytecodes 3507 if (op->should_profile_receiver_type()) { 3508 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3509 Register recv = op->recv()->as_register(); 3510 assert_different_registers(mdo, recv); 3511 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3512 ciKlass* known_klass = op->known_holder(); 3513 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3514 // We know the type that will be seen at this call site; we can 3515 // statically update the MethodData* rather than needing to do 3516 // dynamic tests on the receiver type 3517 3518 // NOTE: we should probably put a lock around this search to 3519 // avoid collisions by concurrent compilations 3520 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3521 uint i; 3522 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3523 ciKlass* receiver = vc_data->receiver(i); 3524 if (known_klass->equals(receiver)) { 3525 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3526 __ addptr(data_addr, DataLayout::counter_increment); 3527 return; 3528 } 3529 } 3530 3531 // Receiver type not found in profile data; select an empty slot 3532 3533 // Note that this is less efficient than it should be because it 3534 // always does a write to the receiver part of the 3535 // VirtualCallData rather than just the first time 3536 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3537 ciKlass* receiver = vc_data->receiver(i); 3538 if (receiver == NULL) { 3539 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3540 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3541 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3542 __ addptr(data_addr, DataLayout::counter_increment); 3543 return; 3544 } 3545 } 3546 } else { 3547 __ load_klass(recv, recv); 3548 Label update_done; 3549 type_profile_helper(mdo, md, data, recv, &update_done); 3550 // Receiver did not match any saved receiver and there is no empty row for it. 3551 // Increment total counter to indicate polymorphic case. 3552 __ addptr(counter_addr, DataLayout::counter_increment); 3553 3554 __ bind(update_done); 3555 } 3556 } else { 3557 // Static call 3558 __ addptr(counter_addr, DataLayout::counter_increment); 3559 } 3560 } 3561 3562 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3563 Register obj = op->obj()->as_register(); 3564 Register tmp = op->tmp()->as_pointer_register(); 3565 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3566 ciKlass* exact_klass = op->exact_klass(); 3567 intptr_t current_klass = op->current_klass(); 3568 bool not_null = op->not_null(); 3569 bool no_conflict = op->no_conflict(); 3570 3571 Label update, next, none; 3572 3573 bool do_null = !not_null; 3574 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3575 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3576 3577 assert(do_null || do_update, "why are we here?"); 3578 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3579 3580 __ verify_oop(obj); 3581 3582 if (tmp != obj) { 3583 __ mov(tmp, obj); 3584 } 3585 if (do_null) { 3586 __ testptr(tmp, tmp); 3587 __ jccb(Assembler::notZero, update); 3588 if (!TypeEntries::was_null_seen(current_klass)) { 3589 __ orptr(mdo_addr, TypeEntries::null_seen); 3590 } 3591 if (do_update) { 3592 #ifndef ASSERT 3593 __ jmpb(next); 3594 } 3595 #else 3596 __ jmp(next); 3597 } 3598 } else { 3599 __ testptr(tmp, tmp); 3600 __ jccb(Assembler::notZero, update); 3601 __ stop("unexpect null obj"); 3602 #endif 3603 } 3604 3605 __ bind(update); 3606 3607 if (do_update) { 3608 #ifdef ASSERT 3609 if (exact_klass != NULL) { 3610 Label ok; 3611 __ load_klass(tmp, tmp); 3612 __ push(tmp); 3613 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3614 __ cmpptr(tmp, Address(rsp, 0)); 3615 __ jccb(Assembler::equal, ok); 3616 __ stop("exact klass and actual klass differ"); 3617 __ bind(ok); 3618 __ pop(tmp); 3619 } 3620 #endif 3621 if (!no_conflict) { 3622 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3623 if (exact_klass != NULL) { 3624 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3625 } else { 3626 __ load_klass(tmp, tmp); 3627 } 3628 3629 __ xorptr(tmp, mdo_addr); 3630 __ testptr(tmp, TypeEntries::type_klass_mask); 3631 // klass seen before, nothing to do. The unknown bit may have been 3632 // set already but no need to check. 3633 __ jccb(Assembler::zero, next); 3634 3635 __ testptr(tmp, TypeEntries::type_unknown); 3636 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3637 3638 if (TypeEntries::is_type_none(current_klass)) { 3639 __ cmpptr(mdo_addr, 0); 3640 __ jccb(Assembler::equal, none); 3641 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3642 __ jccb(Assembler::equal, none); 3643 // There is a chance that the checks above (re-reading profiling 3644 // data from memory) fail if another thread has just set the 3645 // profiling to this obj's klass 3646 __ xorptr(tmp, mdo_addr); 3647 __ testptr(tmp, TypeEntries::type_klass_mask); 3648 __ jccb(Assembler::zero, next); 3649 } 3650 } else { 3651 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3652 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3653 3654 __ movptr(tmp, mdo_addr); 3655 __ testptr(tmp, TypeEntries::type_unknown); 3656 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3657 } 3658 3659 // different than before. Cannot keep accurate profile. 3660 __ orptr(mdo_addr, TypeEntries::type_unknown); 3661 3662 if (TypeEntries::is_type_none(current_klass)) { 3663 __ jmpb(next); 3664 3665 __ bind(none); 3666 // first time here. Set profile type. 3667 __ movptr(mdo_addr, tmp); 3668 } 3669 } else { 3670 // There's a single possible klass at this profile point 3671 assert(exact_klass != NULL, "should be"); 3672 if (TypeEntries::is_type_none(current_klass)) { 3673 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3674 __ xorptr(tmp, mdo_addr); 3675 __ testptr(tmp, TypeEntries::type_klass_mask); 3676 #ifdef ASSERT 3677 __ jcc(Assembler::zero, next); 3678 3679 { 3680 Label ok; 3681 __ push(tmp); 3682 __ cmpptr(mdo_addr, 0); 3683 __ jcc(Assembler::equal, ok); 3684 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3685 __ jcc(Assembler::equal, ok); 3686 // may have been set by another thread 3687 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3688 __ xorptr(tmp, mdo_addr); 3689 __ testptr(tmp, TypeEntries::type_mask); 3690 __ jcc(Assembler::zero, ok); 3691 3692 __ stop("unexpected profiling mismatch"); 3693 __ bind(ok); 3694 __ pop(tmp); 3695 } 3696 #else 3697 __ jccb(Assembler::zero, next); 3698 #endif 3699 // first time here. Set profile type. 3700 __ movptr(mdo_addr, tmp); 3701 } else { 3702 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3703 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3704 3705 __ movptr(tmp, mdo_addr); 3706 __ testptr(tmp, TypeEntries::type_unknown); 3707 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3708 3709 __ orptr(mdo_addr, TypeEntries::type_unknown); 3710 } 3711 } 3712 3713 __ bind(next); 3714 } 3715 } 3716 3717 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3718 Unimplemented(); 3719 } 3720 3721 3722 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3723 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3724 } 3725 3726 3727 void LIR_Assembler::align_backward_branch_target() { 3728 __ align(BytesPerWord); 3729 } 3730 3731 3732 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3733 if (left->is_single_cpu()) { 3734 __ negl(left->as_register()); 3735 move_regs(left->as_register(), dest->as_register()); 3736 3737 } else if (left->is_double_cpu()) { 3738 Register lo = left->as_register_lo(); 3739 #ifdef _LP64 3740 Register dst = dest->as_register_lo(); 3741 __ movptr(dst, lo); 3742 __ negptr(dst); 3743 #else 3744 Register hi = left->as_register_hi(); 3745 __ lneg(hi, lo); 3746 if (dest->as_register_lo() == hi) { 3747 assert(dest->as_register_hi() != lo, "destroying register"); 3748 move_regs(hi, dest->as_register_hi()); 3749 move_regs(lo, dest->as_register_lo()); 3750 } else { 3751 move_regs(lo, dest->as_register_lo()); 3752 move_regs(hi, dest->as_register_hi()); 3753 } 3754 #endif // _LP64 3755 3756 } else if (dest->is_single_xmm()) { 3757 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3758 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3759 } 3760 if (UseAVX > 0) { 3761 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3762 ExternalAddress((address)float_signflip_pool)); 3763 } else { 3764 __ xorps(dest->as_xmm_float_reg(), 3765 ExternalAddress((address)float_signflip_pool)); 3766 } 3767 } else if (dest->is_double_xmm()) { 3768 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3769 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3770 } 3771 if (UseAVX > 0) { 3772 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3773 ExternalAddress((address)double_signflip_pool)); 3774 } else { 3775 __ xorpd(dest->as_xmm_double_reg(), 3776 ExternalAddress((address)double_signflip_pool)); 3777 } 3778 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3779 assert(left->fpu() == 0, "arg must be on TOS"); 3780 assert(dest->fpu() == 0, "dest must be TOS"); 3781 __ fchs(); 3782 3783 } else { 3784 ShouldNotReachHere(); 3785 } 3786 } 3787 3788 3789 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3790 assert(src->is_address(), "must be an address"); 3791 assert(dest->is_register(), "must be a register"); 3792 3793 PatchingStub* patch = NULL; 3794 if (patch_code != lir_patch_none) { 3795 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 3796 } 3797 3798 Register reg = dest->as_pointer_register(); 3799 LIR_Address* addr = src->as_address_ptr(); 3800 __ lea(reg, as_Address(addr)); 3801 3802 if (patch != NULL) { 3803 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 3804 } 3805 } 3806 3807 3808 3809 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3810 assert(!tmp->is_valid(), "don't need temporary"); 3811 __ call(RuntimeAddress(dest)); 3812 if (info != NULL) { 3813 add_call_info_here(info); 3814 } 3815 } 3816 3817 3818 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3819 assert(type == T_LONG, "only for volatile long fields"); 3820 3821 if (info != NULL) { 3822 add_debug_info_for_null_check_here(info); 3823 } 3824 3825 if (src->is_double_xmm()) { 3826 if (dest->is_double_cpu()) { 3827 #ifdef _LP64 3828 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3829 #else 3830 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3831 __ psrlq(src->as_xmm_double_reg(), 32); 3832 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3833 #endif // _LP64 3834 } else if (dest->is_double_stack()) { 3835 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3836 } else if (dest->is_address()) { 3837 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3838 } else { 3839 ShouldNotReachHere(); 3840 } 3841 3842 } else if (dest->is_double_xmm()) { 3843 if (src->is_double_stack()) { 3844 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3845 } else if (src->is_address()) { 3846 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3847 } else { 3848 ShouldNotReachHere(); 3849 } 3850 3851 } else if (src->is_double_fpu()) { 3852 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3853 if (dest->is_double_stack()) { 3854 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3855 } else if (dest->is_address()) { 3856 __ fistp_d(as_Address(dest->as_address_ptr())); 3857 } else { 3858 ShouldNotReachHere(); 3859 } 3860 3861 } else if (dest->is_double_fpu()) { 3862 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3863 if (src->is_double_stack()) { 3864 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3865 } else if (src->is_address()) { 3866 __ fild_d(as_Address(src->as_address_ptr())); 3867 } else { 3868 ShouldNotReachHere(); 3869 } 3870 } else { 3871 ShouldNotReachHere(); 3872 } 3873 } 3874 3875 #ifdef ASSERT 3876 // emit run-time assertion 3877 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3878 assert(op->code() == lir_assert, "must be"); 3879 3880 if (op->in_opr1()->is_valid()) { 3881 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3882 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3883 } else { 3884 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3885 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3886 } 3887 3888 Label ok; 3889 if (op->condition() != lir_cond_always) { 3890 Assembler::Condition acond = Assembler::zero; 3891 switch (op->condition()) { 3892 case lir_cond_equal: acond = Assembler::equal; break; 3893 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3894 case lir_cond_less: acond = Assembler::less; break; 3895 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3896 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3897 case lir_cond_greater: acond = Assembler::greater; break; 3898 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3899 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3900 default: ShouldNotReachHere(); 3901 } 3902 __ jcc(acond, ok); 3903 } 3904 if (op->halt()) { 3905 const char* str = __ code_string(op->msg()); 3906 __ stop(str); 3907 } else { 3908 breakpoint(); 3909 } 3910 __ bind(ok); 3911 } 3912 #endif 3913 3914 void LIR_Assembler::membar() { 3915 // QQQ sparc TSO uses this, 3916 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3917 } 3918 3919 void LIR_Assembler::membar_acquire() { 3920 // No x86 machines currently require load fences 3921 } 3922 3923 void LIR_Assembler::membar_release() { 3924 // No x86 machines currently require store fences 3925 } 3926 3927 void LIR_Assembler::membar_loadload() { 3928 // no-op 3929 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3930 } 3931 3932 void LIR_Assembler::membar_storestore() { 3933 // no-op 3934 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3935 } 3936 3937 void LIR_Assembler::membar_loadstore() { 3938 // no-op 3939 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3940 } 3941 3942 void LIR_Assembler::membar_storeload() { 3943 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3944 } 3945 3946 void LIR_Assembler::on_spin_wait() { 3947 __ pause (); 3948 } 3949 3950 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3951 assert(result_reg->is_register(), "check"); 3952 #ifdef _LP64 3953 // __ get_thread(result_reg->as_register_lo()); 3954 __ mov(result_reg->as_register(), r15_thread); 3955 #else 3956 __ get_thread(result_reg->as_register()); 3957 #endif // _LP64 3958 } 3959 3960 3961 void LIR_Assembler::peephole(LIR_List*) { 3962 // do nothing for now 3963 } 3964 3965 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3966 assert(data == dest, "xchg/xadd uses only 2 operands"); 3967 3968 if (data->type() == T_INT) { 3969 if (code == lir_xadd) { 3970 if (os::is_MP()) { 3971 __ lock(); 3972 } 3973 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3974 } else { 3975 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3976 } 3977 } else if (data->is_oop()) { 3978 assert (code == lir_xchg, "xadd for oops"); 3979 Register obj = data->as_register(); 3980 #ifdef _LP64 3981 if (UseCompressedOops) { 3982 __ encode_heap_oop(obj); 3983 __ xchgl(obj, as_Address(src->as_address_ptr())); 3984 __ decode_heap_oop(obj); 3985 } else { 3986 __ xchgptr(obj, as_Address(src->as_address_ptr())); 3987 } 3988 #else 3989 __ xchgl(obj, as_Address(src->as_address_ptr())); 3990 #endif 3991 } else if (data->type() == T_LONG) { 3992 #ifdef _LP64 3993 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 3994 if (code == lir_xadd) { 3995 if (os::is_MP()) { 3996 __ lock(); 3997 } 3998 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 3999 } else { 4000 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4001 } 4002 #else 4003 ShouldNotReachHere(); 4004 #endif 4005 } else { 4006 ShouldNotReachHere(); 4007 } 4008 } 4009 4010 #undef __