--- old/src/hotspot/cpu/x86/x86_64.ad	2018-12-19 12:55:50.215788980 +0100
+++ new/src/hotspot/cpu/x86/x86_64.ad	2018-12-19 12:55:49.969778456 +0100
@@ -4265,132 +4265,196 @@
 
 // Operands for bound floating pointer register arguments
 operand rxmm0() %{
-  constraint(ALLOC_IN_RC(xmm0_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX<= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm0_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm1() %{
-  constraint(ALLOC_IN_RC(xmm1_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm1_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm2() %{
-  constraint(ALLOC_IN_RC(xmm2_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm2_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm3() %{
-  constraint(ALLOC_IN_RC(xmm3_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm3_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm4() %{
-  constraint(ALLOC_IN_RC(xmm4_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm4_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm5() %{
-  constraint(ALLOC_IN_RC(xmm5_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm5_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm6() %{
-  constraint(ALLOC_IN_RC(xmm6_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm6_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm7() %{
-  constraint(ALLOC_IN_RC(xmm7_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm7_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm8() %{
-  constraint(ALLOC_IN_RC(xmm8_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm8_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm9() %{
-  constraint(ALLOC_IN_RC(xmm9_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm9_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm10() %{
-  constraint(ALLOC_IN_RC(xmm10_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm10_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm11() %{
-  constraint(ALLOC_IN_RC(xmm11_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm11_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm12() %{
-  constraint(ALLOC_IN_RC(xmm12_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm12_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm13() %{
-  constraint(ALLOC_IN_RC(xmm13_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm13_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm14() %{
-  constraint(ALLOC_IN_RC(xmm14_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm14_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm15() %{
-  constraint(ALLOC_IN_RC(xmm15_reg));  match(VecX);
-  predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm15_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm16() %{
-  constraint(ALLOC_IN_RC(xmm16_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm16_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm17() %{
-  constraint(ALLOC_IN_RC(xmm17_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm17_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm18() %{
-  constraint(ALLOC_IN_RC(xmm18_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm18_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm19() %{
-  constraint(ALLOC_IN_RC(xmm19_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm19_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm20() %{
-  constraint(ALLOC_IN_RC(xmm20_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm20_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm21() %{
-  constraint(ALLOC_IN_RC(xmm21_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm21_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm22() %{
-  constraint(ALLOC_IN_RC(xmm22_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm22_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm23() %{
-  constraint(ALLOC_IN_RC(xmm23_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm23_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm24() %{
-  constraint(ALLOC_IN_RC(xmm24_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm24_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm25() %{
-  constraint(ALLOC_IN_RC(xmm25_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm25_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm26() %{
-  constraint(ALLOC_IN_RC(xmm26_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm26_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm27() %{
-  constraint(ALLOC_IN_RC(xmm27_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm27_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm28() %{
-  constraint(ALLOC_IN_RC(xmm28_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm28_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm29() %{
-  constraint(ALLOC_IN_RC(xmm29_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm29_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm30() %{
-  constraint(ALLOC_IN_RC(xmm30_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm30_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 operand rxmm31() %{
-  constraint(ALLOC_IN_RC(xmm31_reg));  match(VecX);
-  predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
+  constraint(ALLOC_IN_RC(xmm31_reg));
+  match(VecX);
+  format%{%}
+  interface(REG_INTER);
 %}
 
 //----------OPERAND CLASSES----------------------------------------------------
@@ -12651,33 +12715,6 @@
 // Execute ZGC load barrier (strong) slow path
 //
 
-// When running without XMM regs
-instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
-
-  match(Set dst (LoadBarrierSlowReg mem));
-  predicate(MaxVectorSize < 16);
-
-  effect(DEF dst, KILL cr);
-
-  format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
-  ins_encode %{
-#if INCLUDE_ZGC
-    Register d = $dst$$Register;
-    ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
-
-    assert(d != r12, "Can't be R12!");
-    assert(d != r15, "Can't be R15!");
-    assert(d != rsp, "Can't be RSP!");
-
-    __ lea(d, $mem$$Address);
-    __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
-#else
-    ShouldNotReachHere();
-#endif
-  %}
-  ins_pipe(pipe_slow);
-%}
-
 // For XMM and YMM enabled processors
 instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
                                      rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
@@ -12686,7 +12723,7 @@
                                      rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
 
   match(Set dst (LoadBarrierSlowReg mem));
-  predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
+  predicate(UseAVX <= 2);
 
   effect(DEF dst, KILL cr,
          KILL x0, KILL x1, KILL x2, KILL x3,
@@ -12694,7 +12731,7 @@
          KILL x8, KILL x9, KILL x10, KILL x11,
          KILL x12, KILL x13, KILL x14, KILL x15);
 
-  format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
+  format %{"LoadBarrierSlowRegXmmAndYmm $dst, $mem" %}
   ins_encode %{
 #if INCLUDE_ZGC
     Register d = $dst$$Register;
@@ -12725,7 +12762,7 @@
                                rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
 
   match(Set dst (LoadBarrierSlowReg mem));
-  predicate((UseAVX == 3) && (MaxVectorSize >= 16));
+  predicate(UseAVX == 3);
 
   effect(DEF dst, KILL cr,
          KILL x0, KILL x1, KILL x2, KILL x3,
@@ -12760,33 +12797,6 @@
 // Execute ZGC load barrier (weak) slow path
 //
 
-// When running without XMM regs
-instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
-
-  match(Set dst (LoadBarrierSlowReg mem));
-  predicate(MaxVectorSize < 16);
-
-  effect(DEF dst, KILL cr);
-
-  format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
-  ins_encode %{
-#if INCLUDE_ZGC
-    Register d = $dst$$Register;
-    ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
-
-    assert(d != r12, "Can't be R12!");
-    assert(d != r15, "Can't be R15!");
-    assert(d != rsp, "Can't be RSP!");
-
-    __ lea(d, $mem$$Address);
-    __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
-#else
-    ShouldNotReachHere();
-#endif
-  %}
-  ins_pipe(pipe_slow);
-%}
-
 // For XMM and YMM enabled processors
 instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
                                          rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
@@ -12795,7 +12805,7 @@
                                          rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
 
   match(Set dst (LoadBarrierWeakSlowReg mem));
-  predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
+  predicate(UseAVX <= 2);
 
   effect(DEF dst, KILL cr,
          KILL x0, KILL x1, KILL x2, KILL x3,
@@ -12803,7 +12813,7 @@
          KILL x8, KILL x9, KILL x10, KILL x11,
          KILL x12, KILL x13, KILL x14, KILL x15);
 
-  format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
+  format %{"LoadBarrierWeakSlowRegXmmAndYmm $dst, $mem" %}
   ins_encode %{
 #if INCLUDE_ZGC
     Register d = $dst$$Register;
@@ -12834,7 +12844,7 @@
                                    rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
 
   match(Set dst (LoadBarrierWeakSlowReg mem));
-  predicate((UseAVX == 3) && (MaxVectorSize >= 16));
+  predicate(UseAVX == 3);
 
   effect(DEF dst, KILL cr,
          KILL x0, KILL x1, KILL x2, KILL x3,