1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 public:
41 using Assembler::mov;
42 using Assembler::movi;
43
44 protected:
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments, // the number of arguments to pop after the call
54 Label *retaddr = NULL
55 );
56
57 virtual void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label &retaddr) {
61 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
62 }
63
64 // This is the base routine called by the different versions of call_VM. The interpreter
65 // may customize this version by overriding it for its purposes (e.g., to save/restore
66 // additional registers when doing a VM call).
67 //
68 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
69 // returns the register which contains the thread upon return. If a thread register has been
70 // specified, the return value will correspond to that register. If no last_java_sp is specified
71 // (noreg) than rsp will be used instead.
72 virtual void call_VM_base( // returns the register containing the thread upon return
73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
74 Register java_thread, // the thread if computed before ; use noreg otherwise
75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
76 address entry_point, // the entry point
77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
78 bool check_exceptions // whether to check for pending exceptions after return
79 );
80
81 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
82
83 // True if an XOR can be used to expand narrow klass references.
84 bool use_XOR_for_compressed_class_base;
85
86 public:
87 MacroAssembler(CodeBuffer* code) : Assembler(code) {
88 use_XOR_for_compressed_class_base
89 = operand_valid_for_logical_immediate
90 (/*is32*/false, (uint64_t)CompressedKlassPointers::base())
91 && ((uint64_t)CompressedKlassPointers::base()
92 > (1UL << log2_intptr(CompressedKlassPointers::range())));
93 }
94
95 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
96 // The implementation is only non-empty for the InterpreterMacroAssembler,
97 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
98 virtual void check_and_handle_popframe(Register java_thread);
99 virtual void check_and_handle_earlyret(Register java_thread);
100
101 void safepoint_poll(Label& slow_path);
102 void safepoint_poll_acquire(Label& slow_path);
103
104 // Biased locking support
105 // lock_reg and obj_reg must be loaded up with the appropriate values.
106 // swap_reg is killed.
107 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
108 // Optional slow case is for implementations (interpreter and C1) which branch to
109 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
110 // Returns offset of first potentially-faulting instruction for null
111 // check info (currently consumed only by C1). If
112 // swap_reg_contains_mark is true then returns -1 as it is assumed
113 // the calling code has already passed any potential faults.
114 int biased_locking_enter(Register lock_reg, Register obj_reg,
115 Register swap_reg, Register tmp_reg,
116 bool swap_reg_contains_mark,
117 Label& done, Label* slow_case = NULL,
118 BiasedLockingCounters* counters = NULL);
119 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
120
121
122 // Helper functions for statistics gathering.
123 // Unconditional atomic increment.
124 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
125 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
126 lea(tmp1, counter_addr);
127 atomic_incw(tmp1, tmp2, tmp3);
128 }
129 // Load Effective Address
130 void lea(Register r, const Address &a) {
131 InstructionMark im(this);
132 code_section()->relocate(inst_mark(), a.rspec());
133 a.lea(this, r);
134 }
135
136 void addmw(Address a, Register incr, Register scratch) {
137 ldrw(scratch, a);
138 addw(scratch, scratch, incr);
139 strw(scratch, a);
140 }
141
142 // Add constant to memory word
143 void addmw(Address a, int imm, Register scratch) {
144 ldrw(scratch, a);
145 if (imm > 0)
146 addw(scratch, scratch, (unsigned)imm);
147 else
148 subw(scratch, scratch, (unsigned)-imm);
149 strw(scratch, a);
150 }
151
152 void bind(Label& L) {
153 Assembler::bind(L);
154 code()->clear_last_insn();
155 }
156
157 void membar(Membar_mask_bits order_constraint);
158
159 using Assembler::ldr;
160 using Assembler::str;
161
162 void ldr(Register Rx, const Address &adr);
163 void ldrw(Register Rw, const Address &adr);
164 void str(Register Rx, const Address &adr);
165 void strw(Register Rx, const Address &adr);
166
167 // Frame creation and destruction shared between JITs.
168 void build_frame(int framesize);
169 void remove_frame(int framesize);
170
171 virtual void _call_Unimplemented(address call_site) {
172 mov(rscratch2, call_site);
173 }
174
175 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
176
177 // aliases defined in AARCH64 spec
178
179 template<class T>
180 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
181
182 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
183 inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
184
185 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
186 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
187
188 void cset(Register Rd, Assembler::Condition cond) {
189 csinc(Rd, zr, zr, ~cond);
190 }
191 void csetw(Register Rd, Assembler::Condition cond) {
192 csincw(Rd, zr, zr, ~cond);
193 }
194
195 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
196 csneg(Rd, Rn, Rn, ~cond);
197 }
198 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
199 csnegw(Rd, Rn, Rn, ~cond);
200 }
201
202 inline void movw(Register Rd, Register Rn) {
203 if (Rd == sp || Rn == sp) {
204 addw(Rd, Rn, 0U);
205 } else {
206 orrw(Rd, zr, Rn);
207 }
208 }
209 inline void mov(Register Rd, Register Rn) {
210 assert(Rd != r31_sp && Rn != r31_sp, "should be");
211 if (Rd == Rn) {
212 } else if (Rd == sp || Rn == sp) {
213 add(Rd, Rn, 0U);
214 } else {
215 orr(Rd, zr, Rn);
216 }
217 }
218
219 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
220 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
221
222 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
223 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
224
225 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
226 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
227
228 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
230 }
231 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
233 }
234
235 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 bfmw(Rd, Rn, lsb, (lsb + width - 1));
237 }
238 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 bfm(Rd, Rn, lsb , (lsb + width - 1));
240 }
241
242 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
244 }
245 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
247 }
248
249 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
251 }
252 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 sbfm(Rd, Rn, lsb , (lsb + width - 1));
254 }
255
256 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
257 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
258 }
259 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
261 }
262
263 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
264 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
265 }
266 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 ubfm(Rd, Rn, lsb , (lsb + width - 1));
268 }
269
270 inline void asrw(Register Rd, Register Rn, unsigned imm) {
271 sbfmw(Rd, Rn, imm, 31);
272 }
273
274 inline void asr(Register Rd, Register Rn, unsigned imm) {
275 sbfm(Rd, Rn, imm, 63);
276 }
277
278 inline void lslw(Register Rd, Register Rn, unsigned imm) {
279 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
280 }
281
282 inline void lsl(Register Rd, Register Rn, unsigned imm) {
283 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
284 }
285
286 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
287 ubfmw(Rd, Rn, imm, 31);
288 }
289
290 inline void lsr(Register Rd, Register Rn, unsigned imm) {
291 ubfm(Rd, Rn, imm, 63);
292 }
293
294 inline void rorw(Register Rd, Register Rn, unsigned imm) {
295 extrw(Rd, Rn, Rn, imm);
296 }
297
298 inline void ror(Register Rd, Register Rn, unsigned imm) {
299 extr(Rd, Rn, Rn, imm);
300 }
301
302 inline void sxtbw(Register Rd, Register Rn) {
303 sbfmw(Rd, Rn, 0, 7);
304 }
305 inline void sxthw(Register Rd, Register Rn) {
306 sbfmw(Rd, Rn, 0, 15);
307 }
308 inline void sxtb(Register Rd, Register Rn) {
309 sbfm(Rd, Rn, 0, 7);
310 }
311 inline void sxth(Register Rd, Register Rn) {
312 sbfm(Rd, Rn, 0, 15);
313 }
314 inline void sxtw(Register Rd, Register Rn) {
315 sbfm(Rd, Rn, 0, 31);
316 }
317
318 inline void uxtbw(Register Rd, Register Rn) {
319 ubfmw(Rd, Rn, 0, 7);
320 }
321 inline void uxthw(Register Rd, Register Rn) {
322 ubfmw(Rd, Rn, 0, 15);
323 }
324 inline void uxtb(Register Rd, Register Rn) {
325 ubfm(Rd, Rn, 0, 7);
326 }
327 inline void uxth(Register Rd, Register Rn) {
328 ubfm(Rd, Rn, 0, 15);
329 }
330 inline void uxtw(Register Rd, Register Rn) {
331 ubfm(Rd, Rn, 0, 31);
332 }
333
334 inline void cmnw(Register Rn, Register Rm) {
335 addsw(zr, Rn, Rm);
336 }
337 inline void cmn(Register Rn, Register Rm) {
338 adds(zr, Rn, Rm);
339 }
340
341 inline void cmpw(Register Rn, Register Rm) {
342 subsw(zr, Rn, Rm);
343 }
344 inline void cmp(Register Rn, Register Rm) {
345 subs(zr, Rn, Rm);
346 }
347
348 inline void negw(Register Rd, Register Rn) {
349 subw(Rd, zr, Rn);
350 }
351
352 inline void neg(Register Rd, Register Rn) {
353 sub(Rd, zr, Rn);
354 }
355
356 inline void negsw(Register Rd, Register Rn) {
357 subsw(Rd, zr, Rn);
358 }
359
360 inline void negs(Register Rd, Register Rn) {
361 subs(Rd, zr, Rn);
362 }
363
364 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
365 addsw(zr, Rn, Rm, kind, shift);
366 }
367 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 adds(zr, Rn, Rm, kind, shift);
369 }
370
371 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
372 subsw(zr, Rn, Rm, kind, shift);
373 }
374 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
375 subs(zr, Rn, Rm, kind, shift);
376 }
377
378 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
379 subw(Rd, zr, Rn, kind, shift);
380 }
381
382 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
383 sub(Rd, zr, Rn, kind, shift);
384 }
385
386 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
387 subsw(Rd, zr, Rn, kind, shift);
388 }
389
390 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
391 subs(Rd, zr, Rn, kind, shift);
392 }
393
394 inline void mnegw(Register Rd, Register Rn, Register Rm) {
395 msubw(Rd, Rn, Rm, zr);
396 }
397 inline void mneg(Register Rd, Register Rn, Register Rm) {
398 msub(Rd, Rn, Rm, zr);
399 }
400
401 inline void mulw(Register Rd, Register Rn, Register Rm) {
402 maddw(Rd, Rn, Rm, zr);
403 }
404 inline void mul(Register Rd, Register Rn, Register Rm) {
405 madd(Rd, Rn, Rm, zr);
406 }
407
408 inline void smnegl(Register Rd, Register Rn, Register Rm) {
409 smsubl(Rd, Rn, Rm, zr);
410 }
411 inline void smull(Register Rd, Register Rn, Register Rm) {
412 smaddl(Rd, Rn, Rm, zr);
413 }
414
415 inline void umnegl(Register Rd, Register Rn, Register Rm) {
416 umsubl(Rd, Rn, Rm, zr);
417 }
418 inline void umull(Register Rd, Register Rn, Register Rm) {
419 umaddl(Rd, Rn, Rm, zr);
420 }
421
422 #define WRAP(INSN) \
423 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
424 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
425 nop(); \
426 Assembler::INSN(Rd, Rn, Rm, Ra); \
427 }
428
429 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
430 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
431 #undef WRAP
432
433
434 // macro assembly operations needed for aarch64
435
436 // first two private routines for loading 32 bit or 64 bit constants
437 private:
438
439 void mov_immediate64(Register dst, u_int64_t imm64);
440 void mov_immediate32(Register dst, u_int32_t imm32);
441
442 int push(unsigned int bitset, Register stack);
443 int pop(unsigned int bitset, Register stack);
444
445 void mov(Register dst, Address a);
446
447 public:
448 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
449 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
450
451 // Push and pop everything that might be clobbered by a native
452 // runtime call except rscratch1 and rscratch2. (They are always
453 // scratch, so we don't have to protect them.) Only save the lower
454 // 64 bits of each vector register.
455 void push_call_clobbered_registers();
456 void pop_call_clobbered_registers();
457
458 // now mov instructions for loading absolute addresses and 32 or
459 // 64 bit integers
460
461 inline void mov(Register dst, address addr)
462 {
463 mov_immediate64(dst, (u_int64_t)addr);
464 }
465
466 inline void mov(Register dst, u_int64_t imm64)
467 {
468 mov_immediate64(dst, imm64);
469 }
470
471 inline void movw(Register dst, u_int32_t imm32)
472 {
473 mov_immediate32(dst, imm32);
474 }
475
476 inline void mov(Register dst, long l)
477 {
478 mov(dst, (u_int64_t)l);
479 }
480
481 inline void mov(Register dst, int i)
482 {
483 mov(dst, (long)i);
484 }
485
486 void mov(Register dst, RegisterOrConstant src) {
487 if (src.is_register())
488 mov(dst, src.as_register());
489 else
490 mov(dst, src.as_constant());
491 }
492
493 void movptr(Register r, uintptr_t imm64);
494
495 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
496
497 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
498 orr(Vd, T, Vn, Vn);
499 }
500
501 public:
502
503 // Generalized Test Bit And Branch, including a "far" variety which
504 // spans more than 32KiB.
505 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
506 assert(cond == EQ || cond == NE, "must be");
507
508 if (far)
509 cond = ~cond;
510
511 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
512 if (cond == Assembler::EQ)
513 branch = &Assembler::tbz;
514 else
515 branch = &Assembler::tbnz;
516
517 if (far) {
518 Label L;
519 (this->*branch)(Rt, bitpos, L);
520 b(dest);
521 bind(L);
522 } else {
523 (this->*branch)(Rt, bitpos, dest);
524 }
525 }
526
527 // macro instructions for accessing and updating floating point
528 // status register
529 //
530 // FPSR : op1 == 011
531 // CRn == 0100
532 // CRm == 0100
533 // op2 == 001
534
535 inline void get_fpsr(Register reg)
536 {
537 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
538 }
539
540 inline void set_fpsr(Register reg)
541 {
542 msr(0b011, 0b0100, 0b0100, 0b001, reg);
543 }
544
545 inline void clear_fpsr()
546 {
547 msr(0b011, 0b0100, 0b0100, 0b001, zr);
548 }
549
550 // DCZID_EL0: op1 == 011
551 // CRn == 0000
552 // CRm == 0000
553 // op2 == 111
554 inline void get_dczid_el0(Register reg)
555 {
556 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
557 }
558
559 // CTR_EL0: op1 == 011
560 // CRn == 0000
561 // CRm == 0000
562 // op2 == 001
563 inline void get_ctr_el0(Register reg)
564 {
565 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
566 }
567
568 // idiv variant which deals with MINLONG as dividend and -1 as divisor
569 int corrected_idivl(Register result, Register ra, Register rb,
570 bool want_remainder, Register tmp = rscratch1);
571 int corrected_idivq(Register result, Register ra, Register rb,
572 bool want_remainder, Register tmp = rscratch1);
573
574 // Support for NULL-checks
575 //
576 // Generates code that causes a NULL OS exception if the content of reg is NULL.
577 // If the accessed location is M[reg + offset] and the offset is known, provide the
578 // offset. No explicit code generation is needed if the offset is within a certain
579 // range (0 <= offset <= page_size).
580
581 virtual void null_check(Register reg, int offset = -1);
582 static bool needs_explicit_null_check(intptr_t offset);
583 static bool uses_implicit_null_check(void* address);
584
585 static address target_addr_for_insn(address insn_addr, unsigned insn);
586 static address target_addr_for_insn(address insn_addr) {
587 unsigned insn = *(unsigned*)insn_addr;
588 return target_addr_for_insn(insn_addr, insn);
589 }
590
591 // Required platform-specific helpers for Label::patch_instructions.
592 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
593 static int pd_patch_instruction_size(address branch, address target);
594 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
595 pd_patch_instruction_size(branch, target);
596 }
597 static address pd_call_destination(address branch) {
598 return target_addr_for_insn(branch);
599 }
600 #ifndef PRODUCT
601 static void pd_print_patched_instruction(address branch);
602 #endif
603
604 static int patch_oop(address insn_addr, address o);
605 static int patch_narrow_klass(address insn_addr, narrowKlass n);
606
607 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
608 void emit_static_call_stub();
609
610 // The following 4 methods return the offset of the appropriate move instruction
611
612 // Support for fast byte/short loading with zero extension (depending on particular CPU)
613 int load_unsigned_byte(Register dst, Address src);
614 int load_unsigned_short(Register dst, Address src);
615
616 // Support for fast byte/short loading with sign extension (depending on particular CPU)
617 int load_signed_byte(Register dst, Address src);
618 int load_signed_short(Register dst, Address src);
619
620 int load_signed_byte32(Register dst, Address src);
621 int load_signed_short32(Register dst, Address src);
622
623 // Support for sign-extension (hi:lo = extend_sign(lo))
624 void extend_sign(Register hi, Register lo);
625
626 // Load and store values by size and signed-ness
627 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
628 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
629
630 // Support for inc/dec with optimal instruction selection depending on value
631
632 // x86_64 aliases an unqualified register/address increment and
633 // decrement to call incrementq and decrementq but also supports
634 // explicitly sized calls to incrementq/decrementq or
635 // incrementl/decrementl
636
637 // for aarch64 the proper convention would be to use
638 // increment/decrement for 64 bit operatons and
639 // incrementw/decrementw for 32 bit operations. so when porting
640 // x86_64 code we can leave calls to increment/decrement as is,
641 // replace incrementq/decrementq with increment/decrement and
642 // replace incrementl/decrementl with incrementw/decrementw.
643
644 // n.b. increment/decrement calls with an Address destination will
645 // need to use a scratch register to load the value to be
646 // incremented. increment/decrement calls which add or subtract a
647 // constant value greater than 2^12 will need to use a 2nd scratch
648 // register to hold the constant. so, a register increment/decrement
649 // may trash rscratch2 and an address increment/decrement trash
650 // rscratch and rscratch2
651
652 void decrementw(Address dst, int value = 1);
653 void decrementw(Register reg, int value = 1);
654
655 void decrement(Register reg, int value = 1);
656 void decrement(Address dst, int value = 1);
657
658 void incrementw(Address dst, int value = 1);
659 void incrementw(Register reg, int value = 1);
660
661 void increment(Register reg, int value = 1);
662 void increment(Address dst, int value = 1);
663
664
665 // Alignment
666 void align(int modulus);
667
668 // Stack frame creation/removal
669 void enter()
670 {
671 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
672 mov(rfp, sp);
673 }
674 void leave()
675 {
676 mov(sp, rfp);
677 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
678 }
679
680 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
681 // The pointer will be loaded into the thread register.
682 void get_thread(Register thread);
683
684
685 // Support for VM calls
686 //
687 // It is imperative that all calls into the VM are handled via the call_VM macros.
688 // They make sure that the stack linkage is setup correctly. call_VM's correspond
689 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
690
691
692 void call_VM(Register oop_result,
693 address entry_point,
694 bool check_exceptions = true);
695 void call_VM(Register oop_result,
696 address entry_point,
697 Register arg_1,
698 bool check_exceptions = true);
699 void call_VM(Register oop_result,
700 address entry_point,
701 Register arg_1, Register arg_2,
702 bool check_exceptions = true);
703 void call_VM(Register oop_result,
704 address entry_point,
705 Register arg_1, Register arg_2, Register arg_3,
706 bool check_exceptions = true);
707
708 // Overloadings with last_Java_sp
709 void call_VM(Register oop_result,
710 Register last_java_sp,
711 address entry_point,
712 int number_of_arguments = 0,
713 bool check_exceptions = true);
714 void call_VM(Register oop_result,
715 Register last_java_sp,
716 address entry_point,
717 Register arg_1, bool
718 check_exceptions = true);
719 void call_VM(Register oop_result,
720 Register last_java_sp,
721 address entry_point,
722 Register arg_1, Register arg_2,
723 bool check_exceptions = true);
724 void call_VM(Register oop_result,
725 Register last_java_sp,
726 address entry_point,
727 Register arg_1, Register arg_2, Register arg_3,
728 bool check_exceptions = true);
729
730 void get_vm_result (Register oop_result, Register thread);
731 void get_vm_result_2(Register metadata_result, Register thread);
732
733 // These always tightly bind to MacroAssembler::call_VM_base
734 // bypassing the virtual implementation
735 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
736 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
737 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
738 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
739 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
740
741 void call_VM_leaf(address entry_point,
742 int number_of_arguments = 0);
743 void call_VM_leaf(address entry_point,
744 Register arg_1);
745 void call_VM_leaf(address entry_point,
746 Register arg_1, Register arg_2);
747 void call_VM_leaf(address entry_point,
748 Register arg_1, Register arg_2, Register arg_3);
749
750 // These always tightly bind to MacroAssembler::call_VM_leaf_base
751 // bypassing the virtual implementation
752 void super_call_VM_leaf(address entry_point);
753 void super_call_VM_leaf(address entry_point, Register arg_1);
754 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
755 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
756 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
757
758 // last Java Frame (fills frame anchor)
759 void set_last_Java_frame(Register last_java_sp,
760 Register last_java_fp,
761 address last_java_pc,
762 Register scratch);
763
764 void set_last_Java_frame(Register last_java_sp,
765 Register last_java_fp,
766 Label &last_java_pc,
767 Register scratch);
768
769 void set_last_Java_frame(Register last_java_sp,
770 Register last_java_fp,
771 Register last_java_pc,
772 Register scratch);
773
774 void reset_last_Java_frame(Register thread);
775
776 // thread in the default location (rthread)
777 void reset_last_Java_frame(bool clear_fp);
778
779 // Stores
780 void store_check(Register obj); // store check for obj - register is destroyed afterwards
781 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
782
783 void resolve_jobject(Register value, Register thread, Register tmp);
784
785 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
786 void c2bool(Register x);
787
788 void load_method_holder(Register holder, Register method);
789
790 // oop manipulations
791 void load_klass(Register dst, Register src);
792 void store_klass(Register dst, Register src);
793 void cmp_klass(Register oop, Register trial_klass, Register tmp);
794
795 void resolve_oop_handle(Register result, Register tmp = r5);
796 void load_mirror(Register dst, Register method, Register tmp = r5);
797
798 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
799 Register tmp1, Register tmp_thread);
800
801 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
802 Register tmp1, Register tmp_thread);
803
804 // Resolves obj for access. Result is placed in the same register.
805 // All other registers are preserved.
806 void resolve(DecoratorSet decorators, Register obj);
807
808 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
809 Register thread_tmp = noreg, DecoratorSet decorators = 0);
810
811 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
812 Register thread_tmp = noreg, DecoratorSet decorators = 0);
813 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
814 Register tmp_thread = noreg, DecoratorSet decorators = 0);
815
816 // currently unimplemented
817 // Used for storing NULL. All other oop constants should be
818 // stored using routines that take a jobject.
819 void store_heap_oop_null(Address dst);
820
821 void load_prototype_header(Register dst, Register src);
822
823 void store_klass_gap(Register dst, Register src);
824
825 // This dummy is to prevent a call to store_heap_oop from
826 // converting a zero (like NULL) into a Register by giving
827 // the compiler two choices it can't resolve
828
829 void store_heap_oop(Address dst, void* dummy);
830
831 void encode_heap_oop(Register d, Register s);
832 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
833 void decode_heap_oop(Register d, Register s);
834 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
835 void encode_heap_oop_not_null(Register r);
836 void decode_heap_oop_not_null(Register r);
837 void encode_heap_oop_not_null(Register dst, Register src);
838 void decode_heap_oop_not_null(Register dst, Register src);
839
840 void set_narrow_oop(Register dst, jobject obj);
841
842 void encode_klass_not_null(Register r);
843 void decode_klass_not_null(Register r);
844 void encode_klass_not_null(Register dst, Register src);
845 void decode_klass_not_null(Register dst, Register src);
846
847 void set_narrow_klass(Register dst, Klass* k);
848
849 // if heap base register is used - reinit it with the correct value
850 void reinit_heapbase();
851
852 DEBUG_ONLY(void verify_heapbase(const char* msg);)
853
854 void push_CPU_state(bool save_vectors = false);
855 void pop_CPU_state(bool restore_vectors = false) ;
856
857 // Round up to a power of two
858 void round_to(Register reg, int modulus);
859
860 // allocation
861 void eden_allocate(
862 Register obj, // result: pointer to object after successful allocation
863 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
864 int con_size_in_bytes, // object size in bytes if known at compile time
865 Register t1, // temp register
866 Label& slow_case // continuation point if fast allocation fails
867 );
868 void tlab_allocate(
869 Register obj, // result: pointer to object after successful allocation
870 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
871 int con_size_in_bytes, // object size in bytes if known at compile time
872 Register t1, // temp register
873 Register t2, // temp register
874 Label& slow_case // continuation point if fast allocation fails
875 );
876 void zero_memory(Register addr, Register len, Register t1);
877 void verify_tlab();
878
879 // interface method calling
880 void lookup_interface_method(Register recv_klass,
881 Register intf_klass,
882 RegisterOrConstant itable_index,
883 Register method_result,
884 Register scan_temp,
885 Label& no_such_interface,
886 bool return_method = true);
887
888 // virtual method calling
889 // n.b. x86 allows RegisterOrConstant for vtable_index
890 void lookup_virtual_method(Register recv_klass,
891 RegisterOrConstant vtable_index,
892 Register method_result);
893
894 // Test sub_klass against super_klass, with fast and slow paths.
895
896 // The fast path produces a tri-state answer: yes / no / maybe-slow.
897 // One of the three labels can be NULL, meaning take the fall-through.
898 // If super_check_offset is -1, the value is loaded up from super_klass.
899 // No registers are killed, except temp_reg.
900 void check_klass_subtype_fast_path(Register sub_klass,
901 Register super_klass,
902 Register temp_reg,
903 Label* L_success,
904 Label* L_failure,
905 Label* L_slow_path,
906 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
907
908 // The rest of the type check; must be wired to a corresponding fast path.
909 // It does not repeat the fast path logic, so don't use it standalone.
910 // The temp_reg and temp2_reg can be noreg, if no temps are available.
911 // Updates the sub's secondary super cache as necessary.
912 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
913 void check_klass_subtype_slow_path(Register sub_klass,
914 Register super_klass,
915 Register temp_reg,
916 Register temp2_reg,
917 Label* L_success,
918 Label* L_failure,
919 bool set_cond_codes = false);
920
921 // Simplified, combined version, good for typical uses.
922 // Falls through on failure.
923 void check_klass_subtype(Register sub_klass,
924 Register super_klass,
925 Register temp_reg,
926 Label& L_success);
927
928 void clinit_barrier(Register klass,
929 Register thread,
930 Label* L_fast_path = NULL,
931 Label* L_slow_path = NULL);
932
933 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
934
935
936 // Debugging
937
938 // only if +VerifyOops
939 void verify_oop(Register reg, const char* s = "broken oop");
940 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
941
942 // TODO: verify method and klass metadata (compare against vptr?)
943 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
944 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
945
946 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
947 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
948
949 // only if +VerifyFPU
950 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
951
952 // prints msg, dumps registers and stops execution
953 void stop(const char* msg);
954
955 // prints msg and continues
956 void warn(const char* msg);
957
958 static void debug64(char* msg, int64_t pc, int64_t regs[]);
959
960 void untested() { stop("untested"); }
961
962 void unimplemented(const char* what = "");
963
964 void should_not_reach_here() { stop("should not reach here"); }
965
966 // Stack overflow checking
967 void bang_stack_with_offset(int offset) {
968 // stack grows down, caller passes positive offset
969 assert(offset > 0, "must bang with negative offset");
970 sub(rscratch2, sp, offset);
971 str(zr, Address(rscratch2));
972 }
973
974 // Writes to stack successive pages until offset reached to check for
975 // stack overflow + shadow pages. Also, clobbers tmp
976 void bang_stack_size(Register size, Register tmp);
977
978 // Check for reserved stack access in method being exited (for JIT)
979 void reserved_stack_check();
980
981 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
982 Register tmp,
983 int offset);
984
985 // Arithmetics
986
987 void addptr(const Address &dst, int32_t src);
988 void cmpptr(Register src1, Address src2);
989
990 void cmpoop(Register obj1, Register obj2);
991
992 // Various forms of CAS
993
994 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
995 Label &suceed, Label *fail);
996 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
997 Label &suceed, Label *fail);
998
999 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1000 Label &suceed, Label *fail);
1001
1002 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1003 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1004 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1005 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1006
1007 void atomic_xchg(Register prev, Register newv, Register addr);
1008 void atomic_xchgw(Register prev, Register newv, Register addr);
1009 void atomic_xchgal(Register prev, Register newv, Register addr);
1010 void atomic_xchgalw(Register prev, Register newv, Register addr);
1011
1012 void orptr(Address adr, RegisterOrConstant src) {
1013 ldr(rscratch1, adr);
1014 if (src.is_register())
1015 orr(rscratch1, rscratch1, src.as_register());
1016 else
1017 orr(rscratch1, rscratch1, src.as_constant());
1018 str(rscratch1, adr);
1019 }
1020
1021 // A generic CAS; success or failure is in the EQ flag.
1022 // Clobbers rscratch1
1023 void cmpxchg(Register addr, Register expected, Register new_val,
1024 enum operand_size size,
1025 bool acquire, bool release, bool weak,
1026 Register result);
1027 private:
1028 void compare_eq(Register rn, Register rm, enum operand_size size);
1029
1030 public:
1031 // Calls
1032
1033 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1034
1035 static bool far_branches() {
1036 return ReservedCodeCacheSize > branch_range || UseAOT;
1037 }
1038
1039 // Jumps that can reach anywhere in the code cache.
1040 // Trashes tmp.
1041 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1042 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1043
1044 static int far_branch_size() {
1045 if (far_branches()) {
1046 return 3 * 4; // adrp, add, br
1047 } else {
1048 return 4;
1049 }
1050 }
1051
1052 // Emit the CompiledIC call idiom
1053 address ic_call(address entry, jint method_index = 0);
1054
1055 public:
1056
1057 // Data
1058
1059 void mov_metadata(Register dst, Metadata* obj);
1060 Address allocate_metadata_address(Metadata* obj);
1061 Address constant_oop_address(jobject obj);
1062
1063 void movoop(Register dst, jobject obj, bool immediate = false);
1064
1065 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1066 void kernel_crc32(Register crc, Register buf, Register len,
1067 Register table0, Register table1, Register table2, Register table3,
1068 Register tmp, Register tmp2, Register tmp3);
1069 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1070 void kernel_crc32c(Register crc, Register buf, Register len,
1071 Register table0, Register table1, Register table2, Register table3,
1072 Register tmp, Register tmp2, Register tmp3);
1073
1074 // Stack push and pop individual 64 bit registers
1075 void push(Register src);
1076 void pop(Register dst);
1077
1078 // push all registers onto the stack
1079 void pusha();
1080 void popa();
1081
1082 void repne_scan(Register addr, Register value, Register count,
1083 Register scratch);
1084 void repne_scanw(Register addr, Register value, Register count,
1085 Register scratch);
1086
1087 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1088 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1089
1090 // If a constant does not fit in an immediate field, generate some
1091 // number of MOV instructions and then perform the operation
1092 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1093 add_sub_imm_insn insn1,
1094 add_sub_reg_insn insn2);
1095 // Seperate vsn which sets the flags
1096 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1097 add_sub_imm_insn insn1,
1098 add_sub_reg_insn insn2);
1099
1100 #define WRAP(INSN) \
1101 void INSN(Register Rd, Register Rn, unsigned imm) { \
1102 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1103 } \
1104 \
1105 void INSN(Register Rd, Register Rn, Register Rm, \
1106 enum shift_kind kind, unsigned shift = 0) { \
1107 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1108 } \
1109 \
1110 void INSN(Register Rd, Register Rn, Register Rm) { \
1111 Assembler::INSN(Rd, Rn, Rm); \
1112 } \
1113 \
1114 void INSN(Register Rd, Register Rn, Register Rm, \
1115 ext::operation option, int amount = 0) { \
1116 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1117 }
1118
1119 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1120
1121 #undef WRAP
1122 #define WRAP(INSN) \
1123 void INSN(Register Rd, Register Rn, unsigned imm) { \
1124 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1125 } \
1126 \
1127 void INSN(Register Rd, Register Rn, Register Rm, \
1128 enum shift_kind kind, unsigned shift = 0) { \
1129 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1130 } \
1131 \
1132 void INSN(Register Rd, Register Rn, Register Rm) { \
1133 Assembler::INSN(Rd, Rn, Rm); \
1134 } \
1135 \
1136 void INSN(Register Rd, Register Rn, Register Rm, \
1137 ext::operation option, int amount = 0) { \
1138 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1139 }
1140
1141 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1142
1143 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1144 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1145 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1146 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1147
1148 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1149
1150 void tableswitch(Register index, jint lowbound, jint highbound,
1151 Label &jumptable, Label &jumptable_end, int stride = 1) {
1152 adr(rscratch1, jumptable);
1153 subsw(rscratch2, index, lowbound);
1154 subsw(zr, rscratch2, highbound - lowbound);
1155 br(Assembler::HS, jumptable_end);
1156 add(rscratch1, rscratch1, rscratch2,
1157 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1158 br(rscratch1);
1159 }
1160
1161 // Form an address from base + offset in Rd. Rd may or may not
1162 // actually be used: you must use the Address that is returned. It
1163 // is up to you to ensure that the shift provided matches the size
1164 // of your data.
1165 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1166
1167 // Return true iff an address is within the 48-bit AArch64 address
1168 // space.
1169 bool is_valid_AArch64_address(address a) {
1170 return ((uint64_t)a >> 48) == 0;
1171 }
1172
1173 // Load the base of the cardtable byte map into reg.
1174 void load_byte_map_base(Register reg);
1175
1176 // Prolog generator routines to support switch between x86 code and
1177 // generated ARM code
1178
1179 // routine to generate an x86 prolog for a stub function which
1180 // bootstraps into the generated ARM code which directly follows the
1181 // stub
1182 //
1183
1184 public:
1185
1186 void ldr_constant(Register dest, const Address &const_addr) {
1187 if (NearCpool) {
1188 ldr(dest, const_addr);
1189 } else {
1190 unsigned long offset;
1191 adrp(dest, InternalAddress(const_addr.target()), offset);
1192 ldr(dest, Address(dest, offset));
1193 }
1194 }
1195
1196 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1197 address read_polling_page(Register r, relocInfo::relocType rtype);
1198 void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1199
1200 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1201 void update_byte_crc32(Register crc, Register val, Register table);
1202 void update_word_crc32(Register crc, Register v, Register tmp,
1203 Register table0, Register table1, Register table2, Register table3,
1204 bool upper = false);
1205
1206 void string_compare(Register str1, Register str2,
1207 Register cnt1, Register cnt2, Register result,
1208 Register tmp1, Register tmp2, FloatRegister vtmp1,
1209 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1210
1211 void has_negatives(Register ary1, Register len, Register result);
1212
1213 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1214 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1215
1216 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1217 int elem_size);
1218
1219 void fill_words(Register base, Register cnt, Register value);
1220 void zero_words(Register base, u_int64_t cnt);
1221 void zero_words(Register ptr, Register cnt);
1222 void zero_dcache_blocks(Register base, Register cnt);
1223
1224 static const int zero_words_block_size;
1225
1226 void byte_array_inflate(Register src, Register dst, Register len,
1227 FloatRegister vtmp1, FloatRegister vtmp2,
1228 FloatRegister vtmp3, Register tmp4);
1229
1230 void char_array_compress(Register src, Register dst, Register len,
1231 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1232 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1233 Register result);
1234
1235 void encode_iso_array(Register src, Register dst,
1236 Register len, Register result,
1237 FloatRegister Vtmp1, FloatRegister Vtmp2,
1238 FloatRegister Vtmp3, FloatRegister Vtmp4);
1239 void string_indexof(Register str1, Register str2,
1240 Register cnt1, Register cnt2,
1241 Register tmp1, Register tmp2,
1242 Register tmp3, Register tmp4,
1243 Register tmp5, Register tmp6,
1244 int int_cnt1, Register result, int ae);
1245 void string_indexof_char(Register str1, Register cnt1,
1246 Register ch, Register result,
1247 Register tmp1, Register tmp2, Register tmp3);
1248 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1249 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1250 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1251 FloatRegister tmpC4, Register tmp1, Register tmp2,
1252 Register tmp3, Register tmp4, Register tmp5);
1253 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1254 address pio2, address dsin_coef, address dcos_coef);
1255 private:
1256 // begin trigonometric functions support block
1257 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1258 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1259 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1260 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1261 // end trigonometric functions support block
1262 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1263 Register src1, Register src2);
1264 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1265 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1266 }
1267 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1268 Register y, Register y_idx, Register z,
1269 Register carry, Register product,
1270 Register idx, Register kdx);
1271 void multiply_128_x_128_loop(Register y, Register z,
1272 Register carry, Register carry2,
1273 Register idx, Register jdx,
1274 Register yz_idx1, Register yz_idx2,
1275 Register tmp, Register tmp3, Register tmp4,
1276 Register tmp7, Register product_hi);
1277 void kernel_crc32_using_crc32(Register crc, Register buf,
1278 Register len, Register tmp0, Register tmp1, Register tmp2,
1279 Register tmp3);
1280 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1281 Register len, Register tmp0, Register tmp1, Register tmp2,
1282 Register tmp3);
1283 public:
1284 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1285 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1286 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1287 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1288 // ISB may be needed because of a safepoint
1289 void maybe_isb() { isb(); }
1290
1291 private:
1292 // Return the effective address r + (r1 << ext) + offset.
1293 // Uses rscratch2.
1294 Address offsetted_address(Register r, Register r1, Address::extend ext,
1295 int offset, int size);
1296
1297 private:
1298 // Returns an address on the stack which is reachable with a ldr/str of size
1299 // Uses rscratch2 if the address is not directly reachable
1300 Address spill_address(int size, int offset, Register tmp=rscratch2);
1301
1302 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1303
1304 // Check whether two loads/stores can be merged into ldp/stp.
1305 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1306
1307 // Merge current load/store with previous load/store into ldp/stp.
1308 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1309
1310 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1311 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1312
1313 public:
1314 void spill(Register Rx, bool is64, int offset) {
1315 if (is64) {
1316 str(Rx, spill_address(8, offset));
1317 } else {
1318 strw(Rx, spill_address(4, offset));
1319 }
1320 }
1321 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1322 str(Vx, T, spill_address(1 << (int)T, offset));
1323 }
1324 void unspill(Register Rx, bool is64, int offset) {
1325 if (is64) {
1326 ldr(Rx, spill_address(8, offset));
1327 } else {
1328 ldrw(Rx, spill_address(4, offset));
1329 }
1330 }
1331 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1332 ldr(Vx, T, spill_address(1 << (int)T, offset));
1333 }
1334 void spill_copy128(int src_offset, int dst_offset,
1335 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1336 if (src_offset < 512 && (src_offset & 7) == 0 &&
1337 dst_offset < 512 && (dst_offset & 7) == 0) {
1338 ldp(tmp1, tmp2, Address(sp, src_offset));
1339 stp(tmp1, tmp2, Address(sp, dst_offset));
1340 } else {
1341 unspill(tmp1, true, src_offset);
1342 spill(tmp1, true, dst_offset);
1343 unspill(tmp1, true, src_offset+8);
1344 spill(tmp1, true, dst_offset+8);
1345 }
1346 }
1347
1348 void cache_wb(Address line);
1349 void cache_wbsync(bool is_pre);
1350 };
1351
1352 #ifdef ASSERT
1353 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1354 #endif
1355
1356 /**
1357 * class SkipIfEqual:
1358 *
1359 * Instantiating this class will result in assembly code being output that will
1360 * jump around any code emitted between the creation of the instance and it's
1361 * automatic destruction at the end of a scope block, depending on the value of
1362 * the flag passed to the constructor, which will be checked at run-time.
1363 */
1364 class SkipIfEqual {
1365 private:
1366 MacroAssembler* _masm;
1367 Label _label;
1368
1369 public:
1370 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1371 ~SkipIfEqual();
1372 };
1373
1374 struct tableswitch {
1375 Register _reg;
1376 int _insn_index; jint _first_key; jint _last_key;
1377 Label _after;
1378 Label _branches;
1379 };
1380
1381 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP