1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 public:
41 using Assembler::mov;
42 using Assembler::movi;
43
44 protected:
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments, // the number of arguments to pop after the call
54 Label *retaddr = NULL
55 );
56
57 virtual void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label &retaddr) {
61 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
62 }
63
64 // This is the base routine called by the different versions of call_VM. The interpreter
65 // may customize this version by overriding it for its purposes (e.g., to save/restore
66 // additional registers when doing a VM call).
67 //
68 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
69 // returns the register which contains the thread upon return. If a thread register has been
70 // specified, the return value will correspond to that register. If no last_java_sp is specified
71 // (noreg) than rsp will be used instead.
72 virtual void call_VM_base( // returns the register containing the thread upon return
73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
74 Register java_thread, // the thread if computed before ; use noreg otherwise
75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
76 address entry_point, // the entry point
77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
78 bool check_exceptions // whether to check for pending exceptions after return
79 );
80
81 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
82
83 // True if an XOR can be used to expand narrow klass references.
84 bool use_XOR_for_compressed_class_base;
85
86 public:
87 MacroAssembler(CodeBuffer* code) : Assembler(code) {
88 use_XOR_for_compressed_class_base
89 = operand_valid_for_logical_immediate
90 (/*is32*/false, (uint64_t)CompressedKlassPointers::base())
91 && ((uint64_t)CompressedKlassPointers::base()
92 > (1UL << log2_intptr(CompressedKlassPointers::range())));
93 }
94
95 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
96 // The implementation is only non-empty for the InterpreterMacroAssembler,
97 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
98 virtual void check_and_handle_popframe(Register java_thread);
99 virtual void check_and_handle_earlyret(Register java_thread);
100
101 void safepoint_poll(Label& slow_path);
102 void safepoint_poll_acquire(Label& slow_path);
103
104 // Biased locking support
105 // lock_reg and obj_reg must be loaded up with the appropriate values.
106 // swap_reg is killed.
107 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
108 // Optional slow case is for implementations (interpreter and C1) which branch to
109 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
110 // Returns offset of first potentially-faulting instruction for null
111 // check info (currently consumed only by C1). If
112 // swap_reg_contains_mark is true then returns -1 as it is assumed
113 // the calling code has already passed any potential faults.
114 int biased_locking_enter(Register lock_reg, Register obj_reg,
115 Register swap_reg, Register tmp_reg,
116 bool swap_reg_contains_mark,
117 Label& done, Label* slow_case = NULL,
118 BiasedLockingCounters* counters = NULL);
119 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
120
121
122 // Helper functions for statistics gathering.
123 // Unconditional atomic increment.
124 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
125 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
126 lea(tmp1, counter_addr);
127 atomic_incw(tmp1, tmp2, tmp3);
128 }
129 // Load Effective Address
130 void lea(Register r, const Address &a) {
131 InstructionMark im(this);
132 code_section()->relocate(inst_mark(), a.rspec());
133 a.lea(this, r);
134 }
135
136 void addmw(Address a, Register incr, Register scratch) {
137 ldrw(scratch, a);
138 addw(scratch, scratch, incr);
139 strw(scratch, a);
140 }
141
142 // Add constant to memory word
143 void addmw(Address a, int imm, Register scratch) {
144 ldrw(scratch, a);
145 if (imm > 0)
146 addw(scratch, scratch, (unsigned)imm);
147 else
148 subw(scratch, scratch, (unsigned)-imm);
149 strw(scratch, a);
150 }
151
152 void bind(Label& L) {
153 Assembler::bind(L);
154 code()->clear_last_insn();
155 }
156
157 void membar(Membar_mask_bits order_constraint);
158
159 using Assembler::ldr;
160 using Assembler::str;
161
162 void ldr(Register Rx, const Address &adr);
163 void ldrw(Register Rw, const Address &adr);
164 void str(Register Rx, const Address &adr);
165 void strw(Register Rx, const Address &adr);
166
167 // Frame creation and destruction shared between JITs.
168 void build_frame(int framesize);
169 void remove_frame(int framesize);
170
171 virtual void _call_Unimplemented(address call_site) {
172 mov(rscratch2, call_site);
173 }
174
175 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
176
177 // aliases defined in AARCH64 spec
178
179 template<class T>
180 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
181
182 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
183 inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
184
185 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
186 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
187
188 void cset(Register Rd, Assembler::Condition cond) {
189 csinc(Rd, zr, zr, ~cond);
190 }
191 void csetw(Register Rd, Assembler::Condition cond) {
192 csincw(Rd, zr, zr, ~cond);
193 }
194
195 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
196 csneg(Rd, Rn, Rn, ~cond);
197 }
198 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
199 csnegw(Rd, Rn, Rn, ~cond);
200 }
201
202 inline void movw(Register Rd, Register Rn) {
203 if (Rd == sp || Rn == sp) {
204 addw(Rd, Rn, 0U);
205 } else {
206 orrw(Rd, zr, Rn);
207 }
208 }
209 inline void mov(Register Rd, Register Rn) {
210 assert(Rd != r31_sp && Rn != r31_sp, "should be");
211 if (Rd == Rn) {
212 } else if (Rd == sp || Rn == sp) {
213 add(Rd, Rn, 0U);
214 } else {
215 orr(Rd, zr, Rn);
216 }
217 }
218
219 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
220 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
221
222 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
223 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
224
225 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
226 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
227
228 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
230 }
231 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
233 }
234
235 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 bfmw(Rd, Rn, lsb, (lsb + width - 1));
237 }
238 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 bfm(Rd, Rn, lsb , (lsb + width - 1));
240 }
241
242 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
244 }
245 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
247 }
248
249 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
251 }
252 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 sbfm(Rd, Rn, lsb , (lsb + width - 1));
254 }
255
256 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
257 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
258 }
259 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
261 }
262
263 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
264 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
265 }
266 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 ubfm(Rd, Rn, lsb , (lsb + width - 1));
268 }
269
270 inline void asrw(Register Rd, Register Rn, unsigned imm) {
271 sbfmw(Rd, Rn, imm, 31);
272 }
273
274 inline void asr(Register Rd, Register Rn, unsigned imm) {
275 sbfm(Rd, Rn, imm, 63);
276 }
277
278 inline void lslw(Register Rd, Register Rn, unsigned imm) {
279 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
280 }
281
282 inline void lsl(Register Rd, Register Rn, unsigned imm) {
283 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
284 }
285
286 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
287 ubfmw(Rd, Rn, imm, 31);
288 }
289
290 inline void lsr(Register Rd, Register Rn, unsigned imm) {
291 ubfm(Rd, Rn, imm, 63);
292 }
293
294 inline void rorw(Register Rd, Register Rn, unsigned imm) {
295 extrw(Rd, Rn, Rn, imm);
296 }
297
298 inline void ror(Register Rd, Register Rn, unsigned imm) {
299 extr(Rd, Rn, Rn, imm);
300 }
301
302 inline void sxtbw(Register Rd, Register Rn) {
303 sbfmw(Rd, Rn, 0, 7);
304 }
305 inline void sxthw(Register Rd, Register Rn) {
306 sbfmw(Rd, Rn, 0, 15);
307 }
308 inline void sxtb(Register Rd, Register Rn) {
309 sbfm(Rd, Rn, 0, 7);
310 }
311 inline void sxth(Register Rd, Register Rn) {
312 sbfm(Rd, Rn, 0, 15);
313 }
314 inline void sxtw(Register Rd, Register Rn) {
315 sbfm(Rd, Rn, 0, 31);
316 }
317
318 inline void uxtbw(Register Rd, Register Rn) {
319 ubfmw(Rd, Rn, 0, 7);
320 }
321 inline void uxthw(Register Rd, Register Rn) {
322 ubfmw(Rd, Rn, 0, 15);
323 }
324 inline void uxtb(Register Rd, Register Rn) {
325 ubfm(Rd, Rn, 0, 7);
326 }
327 inline void uxth(Register Rd, Register Rn) {
328 ubfm(Rd, Rn, 0, 15);
329 }
330 inline void uxtw(Register Rd, Register Rn) {
331 ubfm(Rd, Rn, 0, 31);
332 }
333
334 inline void cmnw(Register Rn, Register Rm) {
335 addsw(zr, Rn, Rm);
336 }
337 inline void cmn(Register Rn, Register Rm) {
338 adds(zr, Rn, Rm);
339 }
340
341 inline void cmpw(Register Rn, Register Rm) {
342 subsw(zr, Rn, Rm);
343 }
344 inline void cmp(Register Rn, Register Rm) {
345 subs(zr, Rn, Rm);
346 }
347
348 inline void negw(Register Rd, Register Rn) {
349 subw(Rd, zr, Rn);
350 }
351
352 inline void neg(Register Rd, Register Rn) {
353 sub(Rd, zr, Rn);
354 }
355
356 inline void negsw(Register Rd, Register Rn) {
357 subsw(Rd, zr, Rn);
358 }
359
360 inline void negs(Register Rd, Register Rn) {
361 subs(Rd, zr, Rn);
362 }
363
364 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
365 addsw(zr, Rn, Rm, kind, shift);
366 }
367 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 adds(zr, Rn, Rm, kind, shift);
369 }
370
371 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
372 subsw(zr, Rn, Rm, kind, shift);
373 }
374 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
375 subs(zr, Rn, Rm, kind, shift);
376 }
377
378 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
379 subw(Rd, zr, Rn, kind, shift);
380 }
381
382 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
383 sub(Rd, zr, Rn, kind, shift);
384 }
385
386 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
387 subsw(Rd, zr, Rn, kind, shift);
388 }
389
390 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
391 subs(Rd, zr, Rn, kind, shift);
392 }
393
394 inline void mnegw(Register Rd, Register Rn, Register Rm) {
395 msubw(Rd, Rn, Rm, zr);
396 }
397 inline void mneg(Register Rd, Register Rn, Register Rm) {
398 msub(Rd, Rn, Rm, zr);
399 }
400
401 inline void mulw(Register Rd, Register Rn, Register Rm) {
402 maddw(Rd, Rn, Rm, zr);
403 }
404 inline void mul(Register Rd, Register Rn, Register Rm) {
405 madd(Rd, Rn, Rm, zr);
406 }
407
408 inline void smnegl(Register Rd, Register Rn, Register Rm) {
409 smsubl(Rd, Rn, Rm, zr);
410 }
411 inline void smull(Register Rd, Register Rn, Register Rm) {
412 smaddl(Rd, Rn, Rm, zr);
413 }
414
415 inline void umnegl(Register Rd, Register Rn, Register Rm) {
416 umsubl(Rd, Rn, Rm, zr);
417 }
418 inline void umull(Register Rd, Register Rn, Register Rm) {
419 umaddl(Rd, Rn, Rm, zr);
420 }
421
422 #define WRAP(INSN) \
423 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
424 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
425 nop(); \
426 Assembler::INSN(Rd, Rn, Rm, Ra); \
427 }
428
429 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
430 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
431 #undef WRAP
432
433
434 // macro assembly operations needed for aarch64
435
436 // first two private routines for loading 32 bit or 64 bit constants
437 private:
438
439 void mov_immediate64(Register dst, u_int64_t imm64);
440 void mov_immediate32(Register dst, u_int32_t imm32);
441
442 int push(unsigned int bitset, Register stack);
443 int pop(unsigned int bitset, Register stack);
444
445 int push_fp(unsigned int bitset, Register stack);
446 int pop_fp(unsigned int bitset, Register stack);
447
448 void mov(Register dst, Address a);
449
450 public:
451 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
452 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
453
454 void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
455 void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
456
457 // Push and pop everything that might be clobbered by a native
458 // runtime call except rscratch1 and rscratch2. (They are always
459 // scratch, so we don't have to protect them.) Only save the lower
460 // 64 bits of each vector register.
461 void push_call_clobbered_registers();
462 void pop_call_clobbered_registers();
463
464 // now mov instructions for loading absolute addresses and 32 or
465 // 64 bit integers
466
467 inline void mov(Register dst, address addr)
468 {
469 mov_immediate64(dst, (u_int64_t)addr);
470 }
471
472 inline void mov(Register dst, u_int64_t imm64)
473 {
474 mov_immediate64(dst, imm64);
475 }
476
477 inline void movw(Register dst, u_int32_t imm32)
478 {
479 mov_immediate32(dst, imm32);
480 }
481
482 inline void mov(Register dst, long l)
483 {
484 mov(dst, (u_int64_t)l);
485 }
486
487 inline void mov(Register dst, int i)
488 {
489 mov(dst, (long)i);
490 }
491
492 void mov(Register dst, RegisterOrConstant src) {
493 if (src.is_register())
494 mov(dst, src.as_register());
495 else
496 mov(dst, src.as_constant());
497 }
498
499 void movptr(Register r, uintptr_t imm64);
500
501 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
502
503 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
504 orr(Vd, T, Vn, Vn);
505 }
506
507 public:
508
509 // Generalized Test Bit And Branch, including a "far" variety which
510 // spans more than 32KiB.
511 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
512 assert(cond == EQ || cond == NE, "must be");
513
514 if (far)
515 cond = ~cond;
516
517 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
518 if (cond == Assembler::EQ)
519 branch = &Assembler::tbz;
520 else
521 branch = &Assembler::tbnz;
522
523 if (far) {
524 Label L;
525 (this->*branch)(Rt, bitpos, L);
526 b(dest);
527 bind(L);
528 } else {
529 (this->*branch)(Rt, bitpos, dest);
530 }
531 }
532
533 // macro instructions for accessing and updating floating point
534 // status register
535 //
536 // FPSR : op1 == 011
537 // CRn == 0100
538 // CRm == 0100
539 // op2 == 001
540
541 inline void get_fpsr(Register reg)
542 {
543 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
544 }
545
546 inline void set_fpsr(Register reg)
547 {
548 msr(0b011, 0b0100, 0b0100, 0b001, reg);
549 }
550
551 inline void clear_fpsr()
552 {
553 msr(0b011, 0b0100, 0b0100, 0b001, zr);
554 }
555
556 // DCZID_EL0: op1 == 011
557 // CRn == 0000
558 // CRm == 0000
559 // op2 == 111
560 inline void get_dczid_el0(Register reg)
561 {
562 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
563 }
564
565 // CTR_EL0: op1 == 011
566 // CRn == 0000
567 // CRm == 0000
568 // op2 == 001
569 inline void get_ctr_el0(Register reg)
570 {
571 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
572 }
573
574 // idiv variant which deals with MINLONG as dividend and -1 as divisor
575 int corrected_idivl(Register result, Register ra, Register rb,
576 bool want_remainder, Register tmp = rscratch1);
577 int corrected_idivq(Register result, Register ra, Register rb,
578 bool want_remainder, Register tmp = rscratch1);
579
580 // Support for NULL-checks
581 //
582 // Generates code that causes a NULL OS exception if the content of reg is NULL.
583 // If the accessed location is M[reg + offset] and the offset is known, provide the
584 // offset. No explicit code generation is needed if the offset is within a certain
585 // range (0 <= offset <= page_size).
586
587 virtual void null_check(Register reg, int offset = -1);
588 static bool needs_explicit_null_check(intptr_t offset);
589 static bool uses_implicit_null_check(void* address);
590
591 static address target_addr_for_insn(address insn_addr, unsigned insn);
592 static address target_addr_for_insn(address insn_addr) {
593 unsigned insn = *(unsigned*)insn_addr;
594 return target_addr_for_insn(insn_addr, insn);
595 }
596
597 // Required platform-specific helpers for Label::patch_instructions.
598 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
599 static int pd_patch_instruction_size(address branch, address target);
600 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
601 pd_patch_instruction_size(branch, target);
602 }
603 static address pd_call_destination(address branch) {
604 return target_addr_for_insn(branch);
605 }
606 #ifndef PRODUCT
607 static void pd_print_patched_instruction(address branch);
608 #endif
609
610 static int patch_oop(address insn_addr, address o);
611 static int patch_narrow_klass(address insn_addr, narrowKlass n);
612
613 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
614 void emit_static_call_stub();
615
616 // The following 4 methods return the offset of the appropriate move instruction
617
618 // Support for fast byte/short loading with zero extension (depending on particular CPU)
619 int load_unsigned_byte(Register dst, Address src);
620 int load_unsigned_short(Register dst, Address src);
621
622 // Support for fast byte/short loading with sign extension (depending on particular CPU)
623 int load_signed_byte(Register dst, Address src);
624 int load_signed_short(Register dst, Address src);
625
626 int load_signed_byte32(Register dst, Address src);
627 int load_signed_short32(Register dst, Address src);
628
629 // Support for sign-extension (hi:lo = extend_sign(lo))
630 void extend_sign(Register hi, Register lo);
631
632 // Load and store values by size and signed-ness
633 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
634 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
635
636 // Support for inc/dec with optimal instruction selection depending on value
637
638 // x86_64 aliases an unqualified register/address increment and
639 // decrement to call incrementq and decrementq but also supports
640 // explicitly sized calls to incrementq/decrementq or
641 // incrementl/decrementl
642
643 // for aarch64 the proper convention would be to use
644 // increment/decrement for 64 bit operatons and
645 // incrementw/decrementw for 32 bit operations. so when porting
646 // x86_64 code we can leave calls to increment/decrement as is,
647 // replace incrementq/decrementq with increment/decrement and
648 // replace incrementl/decrementl with incrementw/decrementw.
649
650 // n.b. increment/decrement calls with an Address destination will
651 // need to use a scratch register to load the value to be
652 // incremented. increment/decrement calls which add or subtract a
653 // constant value greater than 2^12 will need to use a 2nd scratch
654 // register to hold the constant. so, a register increment/decrement
655 // may trash rscratch2 and an address increment/decrement trash
656 // rscratch and rscratch2
657
658 void decrementw(Address dst, int value = 1);
659 void decrementw(Register reg, int value = 1);
660
661 void decrement(Register reg, int value = 1);
662 void decrement(Address dst, int value = 1);
663
664 void incrementw(Address dst, int value = 1);
665 void incrementw(Register reg, int value = 1);
666
667 void increment(Register reg, int value = 1);
668 void increment(Address dst, int value = 1);
669
670
671 // Alignment
672 void align(int modulus);
673
674 // Stack frame creation/removal
675 void enter()
676 {
677 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
678 mov(rfp, sp);
679 }
680 void leave()
681 {
682 mov(sp, rfp);
683 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
684 }
685
686 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
687 // The pointer will be loaded into the thread register.
688 void get_thread(Register thread);
689
690
691 // Support for VM calls
692 //
693 // It is imperative that all calls into the VM are handled via the call_VM macros.
694 // They make sure that the stack linkage is setup correctly. call_VM's correspond
695 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
696
697
698 void call_VM(Register oop_result,
699 address entry_point,
700 bool check_exceptions = true);
701 void call_VM(Register oop_result,
702 address entry_point,
703 Register arg_1,
704 bool check_exceptions = true);
705 void call_VM(Register oop_result,
706 address entry_point,
707 Register arg_1, Register arg_2,
708 bool check_exceptions = true);
709 void call_VM(Register oop_result,
710 address entry_point,
711 Register arg_1, Register arg_2, Register arg_3,
712 bool check_exceptions = true);
713
714 // Overloadings with last_Java_sp
715 void call_VM(Register oop_result,
716 Register last_java_sp,
717 address entry_point,
718 int number_of_arguments = 0,
719 bool check_exceptions = true);
720 void call_VM(Register oop_result,
721 Register last_java_sp,
722 address entry_point,
723 Register arg_1, bool
724 check_exceptions = true);
725 void call_VM(Register oop_result,
726 Register last_java_sp,
727 address entry_point,
728 Register arg_1, Register arg_2,
729 bool check_exceptions = true);
730 void call_VM(Register oop_result,
731 Register last_java_sp,
732 address entry_point,
733 Register arg_1, Register arg_2, Register arg_3,
734 bool check_exceptions = true);
735
736 void get_vm_result (Register oop_result, Register thread);
737 void get_vm_result_2(Register metadata_result, Register thread);
738
739 // These always tightly bind to MacroAssembler::call_VM_base
740 // bypassing the virtual implementation
741 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
742 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
743 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
744 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
745 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
746
747 void call_VM_leaf(address entry_point,
748 int number_of_arguments = 0);
749 void call_VM_leaf(address entry_point,
750 Register arg_1);
751 void call_VM_leaf(address entry_point,
752 Register arg_1, Register arg_2);
753 void call_VM_leaf(address entry_point,
754 Register arg_1, Register arg_2, Register arg_3);
755
756 // These always tightly bind to MacroAssembler::call_VM_leaf_base
757 // bypassing the virtual implementation
758 void super_call_VM_leaf(address entry_point);
759 void super_call_VM_leaf(address entry_point, Register arg_1);
760 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
761 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
762 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
763
764 // last Java Frame (fills frame anchor)
765 void set_last_Java_frame(Register last_java_sp,
766 Register last_java_fp,
767 address last_java_pc,
768 Register scratch);
769
770 void set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 Label &last_java_pc,
773 Register scratch);
774
775 void set_last_Java_frame(Register last_java_sp,
776 Register last_java_fp,
777 Register last_java_pc,
778 Register scratch);
779
780 void reset_last_Java_frame(Register thread);
781
782 // thread in the default location (rthread)
783 void reset_last_Java_frame(bool clear_fp);
784
785 // Stores
786 void store_check(Register obj); // store check for obj - register is destroyed afterwards
787 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
788
789 void resolve_jobject(Register value, Register thread, Register tmp);
790
791 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
792 void c2bool(Register x);
793
794 void load_method_holder(Register holder, Register method);
795
796 // oop manipulations
797 void load_klass(Register dst, Register src);
798 void store_klass(Register dst, Register src);
799 void cmp_klass(Register oop, Register trial_klass, Register tmp);
800
801 void resolve_oop_handle(Register result, Register tmp = r5);
802 void load_mirror(Register dst, Register method, Register tmp = r5);
803
804 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
805 Register tmp1, Register tmp_thread);
806
807 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
808 Register tmp1, Register tmp_thread);
809
810 // Resolves obj for access. Result is placed in the same register.
811 // All other registers are preserved.
812 void resolve(DecoratorSet decorators, Register obj);
813
814 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
815 Register thread_tmp = noreg, DecoratorSet decorators = 0);
816
817 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
818 Register thread_tmp = noreg, DecoratorSet decorators = 0);
819 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
820 Register tmp_thread = noreg, DecoratorSet decorators = 0);
821
822 // currently unimplemented
823 // Used for storing NULL. All other oop constants should be
824 // stored using routines that take a jobject.
825 void store_heap_oop_null(Address dst);
826
827 void load_prototype_header(Register dst, Register src);
828
829 void store_klass_gap(Register dst, Register src);
830
831 // This dummy is to prevent a call to store_heap_oop from
832 // converting a zero (like NULL) into a Register by giving
833 // the compiler two choices it can't resolve
834
835 void store_heap_oop(Address dst, void* dummy);
836
837 void encode_heap_oop(Register d, Register s);
838 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
839 void decode_heap_oop(Register d, Register s);
840 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
841 void encode_heap_oop_not_null(Register r);
842 void decode_heap_oop_not_null(Register r);
843 void encode_heap_oop_not_null(Register dst, Register src);
844 void decode_heap_oop_not_null(Register dst, Register src);
845
846 void set_narrow_oop(Register dst, jobject obj);
847
848 void encode_klass_not_null(Register r);
849 void decode_klass_not_null(Register r);
850 void encode_klass_not_null(Register dst, Register src);
851 void decode_klass_not_null(Register dst, Register src);
852
853 void set_narrow_klass(Register dst, Klass* k);
854
855 // if heap base register is used - reinit it with the correct value
856 void reinit_heapbase();
857
858 DEBUG_ONLY(void verify_heapbase(const char* msg);)
859
860 void push_CPU_state(bool save_vectors = false);
861 void pop_CPU_state(bool restore_vectors = false) ;
862
863 // Round up to a power of two
864 void round_to(Register reg, int modulus);
865
866 // allocation
867 void eden_allocate(
868 Register obj, // result: pointer to object after successful allocation
869 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
870 int con_size_in_bytes, // object size in bytes if known at compile time
871 Register t1, // temp register
872 Label& slow_case // continuation point if fast allocation fails
873 );
874 void tlab_allocate(
875 Register obj, // result: pointer to object after successful allocation
876 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
877 int con_size_in_bytes, // object size in bytes if known at compile time
878 Register t1, // temp register
879 Register t2, // temp register
880 Label& slow_case // continuation point if fast allocation fails
881 );
882 void zero_memory(Register addr, Register len, Register t1);
883 void verify_tlab();
884
885 // interface method calling
886 void lookup_interface_method(Register recv_klass,
887 Register intf_klass,
888 RegisterOrConstant itable_index,
889 Register method_result,
890 Register scan_temp,
891 Label& no_such_interface,
892 bool return_method = true);
893
894 // virtual method calling
895 // n.b. x86 allows RegisterOrConstant for vtable_index
896 void lookup_virtual_method(Register recv_klass,
897 RegisterOrConstant vtable_index,
898 Register method_result);
899
900 // Test sub_klass against super_klass, with fast and slow paths.
901
902 // The fast path produces a tri-state answer: yes / no / maybe-slow.
903 // One of the three labels can be NULL, meaning take the fall-through.
904 // If super_check_offset is -1, the value is loaded up from super_klass.
905 // No registers are killed, except temp_reg.
906 void check_klass_subtype_fast_path(Register sub_klass,
907 Register super_klass,
908 Register temp_reg,
909 Label* L_success,
910 Label* L_failure,
911 Label* L_slow_path,
912 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
913
914 // The rest of the type check; must be wired to a corresponding fast path.
915 // It does not repeat the fast path logic, so don't use it standalone.
916 // The temp_reg and temp2_reg can be noreg, if no temps are available.
917 // Updates the sub's secondary super cache as necessary.
918 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
919 void check_klass_subtype_slow_path(Register sub_klass,
920 Register super_klass,
921 Register temp_reg,
922 Register temp2_reg,
923 Label* L_success,
924 Label* L_failure,
925 bool set_cond_codes = false);
926
927 // Simplified, combined version, good for typical uses.
928 // Falls through on failure.
929 void check_klass_subtype(Register sub_klass,
930 Register super_klass,
931 Register temp_reg,
932 Label& L_success);
933
934 void clinit_barrier(Register klass,
935 Register thread,
936 Label* L_fast_path = NULL,
937 Label* L_slow_path = NULL);
938
939 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
940
941
942 // Debugging
943
944 // only if +VerifyOops
945 void verify_oop(Register reg, const char* s = "broken oop");
946 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
947
948 // TODO: verify method and klass metadata (compare against vptr?)
949 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
950 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
951
952 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
953 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
954
955 // only if +VerifyFPU
956 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
957
958 // prints msg, dumps registers and stops execution
959 void stop(const char* msg);
960
961 // prints msg and continues
962 void warn(const char* msg);
963
964 static void debug64(char* msg, int64_t pc, int64_t regs[]);
965
966 void untested() { stop("untested"); }
967
968 void unimplemented(const char* what = "");
969
970 void should_not_reach_here() { stop("should not reach here"); }
971
972 // Stack overflow checking
973 void bang_stack_with_offset(int offset) {
974 // stack grows down, caller passes positive offset
975 assert(offset > 0, "must bang with negative offset");
976 sub(rscratch2, sp, offset);
977 str(zr, Address(rscratch2));
978 }
979
980 // Writes to stack successive pages until offset reached to check for
981 // stack overflow + shadow pages. Also, clobbers tmp
982 void bang_stack_size(Register size, Register tmp);
983
984 // Check for reserved stack access in method being exited (for JIT)
985 void reserved_stack_check();
986
987 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
988 Register tmp,
989 int offset);
990
991 // Arithmetics
992
993 void addptr(const Address &dst, int32_t src);
994 void cmpptr(Register src1, Address src2);
995
996 void cmpoop(Register obj1, Register obj2);
997
998 // Various forms of CAS
999
1000 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1001 Label &suceed, Label *fail);
1002 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1003 Label &suceed, Label *fail);
1004
1005 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1006 Label &suceed, Label *fail);
1007
1008 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1009 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1010 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1011 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1012
1013 void atomic_xchg(Register prev, Register newv, Register addr);
1014 void atomic_xchgw(Register prev, Register newv, Register addr);
1015 void atomic_xchgal(Register prev, Register newv, Register addr);
1016 void atomic_xchgalw(Register prev, Register newv, Register addr);
1017
1018 void orptr(Address adr, RegisterOrConstant src) {
1019 ldr(rscratch1, adr);
1020 if (src.is_register())
1021 orr(rscratch1, rscratch1, src.as_register());
1022 else
1023 orr(rscratch1, rscratch1, src.as_constant());
1024 str(rscratch1, adr);
1025 }
1026
1027 // A generic CAS; success or failure is in the EQ flag.
1028 // Clobbers rscratch1
1029 void cmpxchg(Register addr, Register expected, Register new_val,
1030 enum operand_size size,
1031 bool acquire, bool release, bool weak,
1032 Register result);
1033 private:
1034 void compare_eq(Register rn, Register rm, enum operand_size size);
1035
1036 public:
1037 // Calls
1038
1039 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1040
1041 static bool far_branches() {
1042 return ReservedCodeCacheSize > branch_range || UseAOT;
1043 }
1044
1045 // Jumps that can reach anywhere in the code cache.
1046 // Trashes tmp.
1047 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1048 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1049
1050 static int far_branch_size() {
1051 if (far_branches()) {
1052 return 3 * 4; // adrp, add, br
1053 } else {
1054 return 4;
1055 }
1056 }
1057
1058 // Emit the CompiledIC call idiom
1059 address ic_call(address entry, jint method_index = 0);
1060
1061 public:
1062
1063 // Data
1064
1065 void mov_metadata(Register dst, Metadata* obj);
1066 Address allocate_metadata_address(Metadata* obj);
1067 Address constant_oop_address(jobject obj);
1068
1069 void movoop(Register dst, jobject obj, bool immediate = false);
1070
1071 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1072 void kernel_crc32(Register crc, Register buf, Register len,
1073 Register table0, Register table1, Register table2, Register table3,
1074 Register tmp, Register tmp2, Register tmp3);
1075 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1076 void kernel_crc32c(Register crc, Register buf, Register len,
1077 Register table0, Register table1, Register table2, Register table3,
1078 Register tmp, Register tmp2, Register tmp3);
1079
1080 // Stack push and pop individual 64 bit registers
1081 void push(Register src);
1082 void pop(Register dst);
1083
1084 // push all registers onto the stack
1085 void pusha();
1086 void popa();
1087
1088 void repne_scan(Register addr, Register value, Register count,
1089 Register scratch);
1090 void repne_scanw(Register addr, Register value, Register count,
1091 Register scratch);
1092
1093 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1094 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1095
1096 // If a constant does not fit in an immediate field, generate some
1097 // number of MOV instructions and then perform the operation
1098 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1099 add_sub_imm_insn insn1,
1100 add_sub_reg_insn insn2);
1101 // Seperate vsn which sets the flags
1102 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1103 add_sub_imm_insn insn1,
1104 add_sub_reg_insn insn2);
1105
1106 #define WRAP(INSN) \
1107 void INSN(Register Rd, Register Rn, unsigned imm) { \
1108 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1109 } \
1110 \
1111 void INSN(Register Rd, Register Rn, Register Rm, \
1112 enum shift_kind kind, unsigned shift = 0) { \
1113 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1114 } \
1115 \
1116 void INSN(Register Rd, Register Rn, Register Rm) { \
1117 Assembler::INSN(Rd, Rn, Rm); \
1118 } \
1119 \
1120 void INSN(Register Rd, Register Rn, Register Rm, \
1121 ext::operation option, int amount = 0) { \
1122 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1123 }
1124
1125 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1126
1127 #undef WRAP
1128 #define WRAP(INSN) \
1129 void INSN(Register Rd, Register Rn, unsigned imm) { \
1130 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1131 } \
1132 \
1133 void INSN(Register Rd, Register Rn, Register Rm, \
1134 enum shift_kind kind, unsigned shift = 0) { \
1135 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1136 } \
1137 \
1138 void INSN(Register Rd, Register Rn, Register Rm) { \
1139 Assembler::INSN(Rd, Rn, Rm); \
1140 } \
1141 \
1142 void INSN(Register Rd, Register Rn, Register Rm, \
1143 ext::operation option, int amount = 0) { \
1144 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1145 }
1146
1147 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1148
1149 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1150 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1151 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1152 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1153
1154 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1155
1156 void tableswitch(Register index, jint lowbound, jint highbound,
1157 Label &jumptable, Label &jumptable_end, int stride = 1) {
1158 adr(rscratch1, jumptable);
1159 subsw(rscratch2, index, lowbound);
1160 subsw(zr, rscratch2, highbound - lowbound);
1161 br(Assembler::HS, jumptable_end);
1162 add(rscratch1, rscratch1, rscratch2,
1163 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1164 br(rscratch1);
1165 }
1166
1167 // Form an address from base + offset in Rd. Rd may or may not
1168 // actually be used: you must use the Address that is returned. It
1169 // is up to you to ensure that the shift provided matches the size
1170 // of your data.
1171 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1172
1173 // Return true iff an address is within the 48-bit AArch64 address
1174 // space.
1175 bool is_valid_AArch64_address(address a) {
1176 return ((uint64_t)a >> 48) == 0;
1177 }
1178
1179 // Load the base of the cardtable byte map into reg.
1180 void load_byte_map_base(Register reg);
1181
1182 // Prolog generator routines to support switch between x86 code and
1183 // generated ARM code
1184
1185 // routine to generate an x86 prolog for a stub function which
1186 // bootstraps into the generated ARM code which directly follows the
1187 // stub
1188 //
1189
1190 public:
1191
1192 void ldr_constant(Register dest, const Address &const_addr) {
1193 if (NearCpool) {
1194 ldr(dest, const_addr);
1195 } else {
1196 unsigned long offset;
1197 adrp(dest, InternalAddress(const_addr.target()), offset);
1198 ldr(dest, Address(dest, offset));
1199 }
1200 }
1201
1202 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1203 address read_polling_page(Register r, relocInfo::relocType rtype);
1204 void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1205
1206 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1207 void update_byte_crc32(Register crc, Register val, Register table);
1208 void update_word_crc32(Register crc, Register v, Register tmp,
1209 Register table0, Register table1, Register table2, Register table3,
1210 bool upper = false);
1211
1212 void string_compare(Register str1, Register str2,
1213 Register cnt1, Register cnt2, Register result,
1214 Register tmp1, Register tmp2, FloatRegister vtmp1,
1215 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1216
1217 void has_negatives(Register ary1, Register len, Register result);
1218
1219 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1220 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1221
1222 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1223 int elem_size);
1224
1225 void fill_words(Register base, Register cnt, Register value);
1226 void zero_words(Register base, u_int64_t cnt);
1227 void zero_words(Register ptr, Register cnt);
1228 void zero_dcache_blocks(Register base, Register cnt);
1229
1230 static const int zero_words_block_size;
1231
1232 void byte_array_inflate(Register src, Register dst, Register len,
1233 FloatRegister vtmp1, FloatRegister vtmp2,
1234 FloatRegister vtmp3, Register tmp4);
1235
1236 void char_array_compress(Register src, Register dst, Register len,
1237 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1238 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1239 Register result);
1240
1241 void encode_iso_array(Register src, Register dst,
1242 Register len, Register result,
1243 FloatRegister Vtmp1, FloatRegister Vtmp2,
1244 FloatRegister Vtmp3, FloatRegister Vtmp4);
1245 void string_indexof(Register str1, Register str2,
1246 Register cnt1, Register cnt2,
1247 Register tmp1, Register tmp2,
1248 Register tmp3, Register tmp4,
1249 Register tmp5, Register tmp6,
1250 int int_cnt1, Register result, int ae);
1251 void string_indexof_char(Register str1, Register cnt1,
1252 Register ch, Register result,
1253 Register tmp1, Register tmp2, Register tmp3);
1254 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1255 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1256 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1257 FloatRegister tmpC4, Register tmp1, Register tmp2,
1258 Register tmp3, Register tmp4, Register tmp5);
1259 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1260 address pio2, address dsin_coef, address dcos_coef);
1261 private:
1262 // begin trigonometric functions support block
1263 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1264 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1265 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1266 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1267 // end trigonometric functions support block
1268 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1269 Register src1, Register src2);
1270 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1271 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1272 }
1273 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1274 Register y, Register y_idx, Register z,
1275 Register carry, Register product,
1276 Register idx, Register kdx);
1277 void multiply_128_x_128_loop(Register y, Register z,
1278 Register carry, Register carry2,
1279 Register idx, Register jdx,
1280 Register yz_idx1, Register yz_idx2,
1281 Register tmp, Register tmp3, Register tmp4,
1282 Register tmp7, Register product_hi);
1283 void kernel_crc32_using_crc32(Register crc, Register buf,
1284 Register len, Register tmp0, Register tmp1, Register tmp2,
1285 Register tmp3);
1286 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1287 Register len, Register tmp0, Register tmp1, Register tmp2,
1288 Register tmp3);
1289 public:
1290 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1291 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1292 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1293 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1294 // ISB may be needed because of a safepoint
1295 void maybe_isb() { isb(); }
1296
1297 private:
1298 // Return the effective address r + (r1 << ext) + offset.
1299 // Uses rscratch2.
1300 Address offsetted_address(Register r, Register r1, Address::extend ext,
1301 int offset, int size);
1302
1303 private:
1304 // Returns an address on the stack which is reachable with a ldr/str of size
1305 // Uses rscratch2 if the address is not directly reachable
1306 Address spill_address(int size, int offset, Register tmp=rscratch2);
1307
1308 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1309
1310 // Check whether two loads/stores can be merged into ldp/stp.
1311 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1312
1313 // Merge current load/store with previous load/store into ldp/stp.
1314 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1315
1316 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1317 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1318
1319 public:
1320 void spill(Register Rx, bool is64, int offset) {
1321 if (is64) {
1322 str(Rx, spill_address(8, offset));
1323 } else {
1324 strw(Rx, spill_address(4, offset));
1325 }
1326 }
1327 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1328 str(Vx, T, spill_address(1 << (int)T, offset));
1329 }
1330 void unspill(Register Rx, bool is64, int offset) {
1331 if (is64) {
1332 ldr(Rx, spill_address(8, offset));
1333 } else {
1334 ldrw(Rx, spill_address(4, offset));
1335 }
1336 }
1337 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1338 ldr(Vx, T, spill_address(1 << (int)T, offset));
1339 }
1340 void spill_copy128(int src_offset, int dst_offset,
1341 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1342 if (src_offset < 512 && (src_offset & 7) == 0 &&
1343 dst_offset < 512 && (dst_offset & 7) == 0) {
1344 ldp(tmp1, tmp2, Address(sp, src_offset));
1345 stp(tmp1, tmp2, Address(sp, dst_offset));
1346 } else {
1347 unspill(tmp1, true, src_offset);
1348 spill(tmp1, true, dst_offset);
1349 unspill(tmp1, true, src_offset+8);
1350 spill(tmp1, true, dst_offset+8);
1351 }
1352 }
1353
1354 void cache_wb(Address line);
1355 void cache_wbsync(bool is_pre);
1356 };
1357
1358 #ifdef ASSERT
1359 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1360 #endif
1361
1362 /**
1363 * class SkipIfEqual:
1364 *
1365 * Instantiating this class will result in assembly code being output that will
1366 * jump around any code emitted between the creation of the instance and it's
1367 * automatic destruction at the end of a scope block, depending on the value of
1368 * the flag passed to the constructor, which will be checked at run-time.
1369 */
1370 class SkipIfEqual {
1371 private:
1372 MacroAssembler* _masm;
1373 Label _label;
1374
1375 public:
1376 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1377 ~SkipIfEqual();
1378 };
1379
1380 struct tableswitch {
1381 Register _reg;
1382 int _insn_index; jint _first_key; jint _last_key;
1383 Label _after;
1384 Label _branches;
1385 };
1386
1387 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP