1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer/long registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all int registers
191 reg_class all_int_reg(RAX
192 RDX,
193 RBP,
194 RDI,
195 RSI,
196 RCX,
197 RBX,
198 R8,
199 R9,
200 R10,
201 R11,
202 R12,
203 R13,
204 R14);
205
206 // Class for all pointer registers
207 reg_class any_reg %{
208 return _ANY_REG_mask;
209 %}
210
211 // Class for all pointer registers (excluding RSP)
212 reg_class ptr_reg %{
213 return _PTR_REG_mask;
214 %}
215
216 // Class for all pointer registers (excluding RSP and RBP)
217 reg_class ptr_reg_no_rbp %{
218 return _PTR_REG_NO_RBP_mask;
219 %}
220
221 // Class for all pointer registers (excluding RAX and RSP)
222 reg_class ptr_no_rax_reg %{
223 return _PTR_NO_RAX_REG_mask;
224 %}
225
226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
227 reg_class ptr_no_rax_rbx_reg %{
228 return _PTR_NO_RAX_RBX_REG_mask;
229 %}
230
231 // Class for all long registers (excluding RSP)
232 reg_class long_reg %{
233 return _LONG_REG_mask;
234 %}
235
236 // Class for all long registers (excluding RAX, RDX and RSP)
237 reg_class long_no_rax_rdx_reg %{
238 return _LONG_NO_RAX_RDX_REG_mask;
239 %}
240
241 // Class for all long registers (excluding RCX and RSP)
242 reg_class long_no_rcx_reg %{
243 return _LONG_NO_RCX_REG_mask;
244 %}
245
246 // Class for all int registers (excluding RSP)
247 reg_class int_reg %{
248 return _INT_REG_mask;
249 %}
250
251 // Class for all int registers (excluding RAX, RDX, and RSP)
252 reg_class int_no_rax_rdx_reg %{
253 return _INT_NO_RAX_RDX_REG_mask;
254 %}
255
256 // Class for all int registers (excluding RCX and RSP)
257 reg_class int_no_rcx_reg %{
258 return _INT_NO_RCX_REG_mask;
259 %}
260
261 // Singleton class for RAX pointer register
262 reg_class ptr_rax_reg(RAX, RAX_H);
263
264 // Singleton class for RBX pointer register
265 reg_class ptr_rbx_reg(RBX, RBX_H);
266
267 // Singleton class for RSI pointer register
268 reg_class ptr_rsi_reg(RSI, RSI_H);
269
270 // Singleton class for RDI pointer register
271 reg_class ptr_rdi_reg(RDI, RDI_H);
272
273 // Singleton class for stack pointer
274 reg_class ptr_rsp_reg(RSP, RSP_H);
275
276 // Singleton class for TLS pointer
277 reg_class ptr_r15_reg(R15, R15_H);
278
279 // Singleton class for RAX long register
280 reg_class long_rax_reg(RAX, RAX_H);
281
282 // Singleton class for RCX long register
283 reg_class long_rcx_reg(RCX, RCX_H);
284
285 // Singleton class for RDX long register
286 reg_class long_rdx_reg(RDX, RDX_H);
287
288 // Singleton class for RAX int register
289 reg_class int_rax_reg(RAX);
290
291 // Singleton class for RBX int register
292 reg_class int_rbx_reg(RBX);
293
294 // Singleton class for RCX int register
295 reg_class int_rcx_reg(RCX);
296
297 // Singleton class for RCX int register
298 reg_class int_rdx_reg(RDX);
299
300 // Singleton class for RCX int register
301 reg_class int_rdi_reg(RDI);
302
303 // Singleton class for instruction pointer
304 // reg_class ip_reg(RIP);
305
306 %}
307
308 //----------SOURCE BLOCK-------------------------------------------------------
309 // This is a block of C++ code which provides values, functions, and
310 // definitions necessary in the rest of the architecture description
311 source_hpp %{
312
313 extern RegMask _ANY_REG_mask;
314 extern RegMask _PTR_REG_mask;
315 extern RegMask _PTR_REG_NO_RBP_mask;
316 extern RegMask _PTR_NO_RAX_REG_mask;
317 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
318 extern RegMask _LONG_REG_mask;
319 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
320 extern RegMask _LONG_NO_RCX_REG_mask;
321 extern RegMask _INT_REG_mask;
322 extern RegMask _INT_NO_RAX_RDX_REG_mask;
323 extern RegMask _INT_NO_RCX_REG_mask;
324
325 extern RegMask _STACK_OR_PTR_REG_mask;
326 extern RegMask _STACK_OR_LONG_REG_mask;
327 extern RegMask _STACK_OR_INT_REG_mask;
328
329 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
330 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
331 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
332
333 %}
334
335 source %{
336 #define RELOC_IMM64 Assembler::imm_operand
337 #define RELOC_DISP32 Assembler::disp32_operand
338
339 #define __ _masm.
340
341 RegMask _ANY_REG_mask;
342 RegMask _PTR_REG_mask;
343 RegMask _PTR_REG_NO_RBP_mask;
344 RegMask _PTR_NO_RAX_REG_mask;
345 RegMask _PTR_NO_RAX_RBX_REG_mask;
346 RegMask _LONG_REG_mask;
347 RegMask _LONG_NO_RAX_RDX_REG_mask;
348 RegMask _LONG_NO_RCX_REG_mask;
349 RegMask _INT_REG_mask;
350 RegMask _INT_NO_RAX_RDX_REG_mask;
351 RegMask _INT_NO_RCX_REG_mask;
352 RegMask _STACK_OR_PTR_REG_mask;
353 RegMask _STACK_OR_LONG_REG_mask;
354 RegMask _STACK_OR_INT_REG_mask;
355
356 static bool need_r12_heapbase() {
357 return UseCompressedOops || UseCompressedClassPointers;
358 }
359
360 void reg_mask_init() {
361 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
362 // We derive a number of subsets from it.
363 _ANY_REG_mask = _ALL_REG_mask;
364
365 if (PreserveFramePointer) {
366 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
368 }
369 if (need_r12_heapbase()) {
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
372 }
373
374 _PTR_REG_mask = _ANY_REG_mask;
375 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
379
380 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
381 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
382
383 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
384 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
386
387 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
388 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
390
391 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
392 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
394
395 _LONG_REG_mask = _PTR_REG_mask;
396 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
397 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
398
399 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
400 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
404
405 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
406 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
408
409 _INT_REG_mask = _ALL_INT_REG_mask;
410 if (PreserveFramePointer) {
411 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
412 }
413 if (need_r12_heapbase()) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
415 }
416
417 _STACK_OR_INT_REG_mask = _INT_REG_mask;
418 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
419
420 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
421 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
423
424 _INT_NO_RCX_REG_mask = _INT_REG_mask;
425 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
426 }
427
428 static bool generate_vzeroupper(Compile* C) {
429 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
430 }
431
432 static int clear_avx_size() {
433 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
434 }
435
436 // !!!!! Special hack to get all types of calls to specify the byte offset
437 // from the start of the call to the point where the return address
438 // will point.
439 int MachCallStaticJavaNode::ret_addr_offset()
440 {
441 int offset = 5; // 5 bytes from start of call to where return address points
442 offset += clear_avx_size();
443 return offset;
444 }
445
446 int MachCallDynamicJavaNode::ret_addr_offset()
447 {
448 int offset = 15; // 15 bytes from start of call to where return address points
449 offset += clear_avx_size();
450 return offset;
451 }
452
453 int MachCallRuntimeNode::ret_addr_offset() {
454 int offset = 13; // movq r10,#addr; callq (r10)
455 offset += clear_avx_size();
456 return offset;
457 }
458
459 // Indicate if the safepoint node needs the polling page as an input,
460 // it does if the polling page is more than disp32 away.
461 bool SafePointNode::needs_polling_address_input()
462 {
463 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
464 }
465
466 //
467 // Compute padding required for nodes which need alignment
468 //
469
470 // The address of the call instruction needs to be 4-byte aligned to
471 // ensure that it does not span a cache line so that it can be patched.
472 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
473 {
474 current_offset += clear_avx_size(); // skip vzeroupper
475 current_offset += 1; // skip call opcode byte
476 return align_up(current_offset, alignment_required()) - current_offset;
477 }
478
479 // The address of the call instruction needs to be 4-byte aligned to
480 // ensure that it does not span a cache line so that it can be patched.
481 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
482 {
483 current_offset += clear_avx_size(); // skip vzeroupper
484 current_offset += 11; // skip movq instruction + call opcode byte
485 return align_up(current_offset, alignment_required()) - current_offset;
486 }
487
488 // EMIT_RM()
489 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
490 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
491 cbuf.insts()->emit_int8(c);
492 }
493
494 // EMIT_CC()
495 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
496 unsigned char c = (unsigned char) (f1 | f2);
497 cbuf.insts()->emit_int8(c);
498 }
499
500 // EMIT_OPCODE()
501 void emit_opcode(CodeBuffer &cbuf, int code) {
502 cbuf.insts()->emit_int8((unsigned char) code);
503 }
504
505 // EMIT_OPCODE() w/ relocation information
506 void emit_opcode(CodeBuffer &cbuf,
507 int code, relocInfo::relocType reloc, int offset, int format)
508 {
509 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
510 emit_opcode(cbuf, code);
511 }
512
513 // EMIT_D8()
514 void emit_d8(CodeBuffer &cbuf, int d8) {
515 cbuf.insts()->emit_int8((unsigned char) d8);
516 }
517
518 // EMIT_D16()
519 void emit_d16(CodeBuffer &cbuf, int d16) {
520 cbuf.insts()->emit_int16(d16);
521 }
522
523 // EMIT_D32()
524 void emit_d32(CodeBuffer &cbuf, int d32) {
525 cbuf.insts()->emit_int32(d32);
526 }
527
528 // EMIT_D64()
529 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
530 cbuf.insts()->emit_int64(d64);
531 }
532
533 // emit 32 bit value and construct relocation entry from relocInfo::relocType
534 void emit_d32_reloc(CodeBuffer& cbuf,
535 int d32,
536 relocInfo::relocType reloc,
537 int format)
538 {
539 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
540 cbuf.relocate(cbuf.insts_mark(), reloc, format);
541 cbuf.insts()->emit_int32(d32);
542 }
543
544 // emit 32 bit value and construct relocation entry from RelocationHolder
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
546 #ifdef ASSERT
547 if (rspec.reloc()->type() == relocInfo::oop_type &&
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
549 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
551 }
552 #endif
553 cbuf.relocate(cbuf.insts_mark(), rspec, format);
554 cbuf.insts()->emit_int32(d32);
555 }
556
557 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
558 address next_ip = cbuf.insts_end() + 4;
559 emit_d32_reloc(cbuf, (int) (addr - next_ip),
560 external_word_Relocation::spec(addr),
561 RELOC_DISP32);
562 }
563
564
565 // emit 64 bit value and construct relocation entry from relocInfo::relocType
566 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
567 cbuf.relocate(cbuf.insts_mark(), reloc, format);
568 cbuf.insts()->emit_int64(d64);
569 }
570
571 // emit 64 bit value and construct relocation entry from RelocationHolder
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
573 #ifdef ASSERT
574 if (rspec.reloc()->type() == relocInfo::oop_type &&
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
576 assert(Universe::heap()->is_in((address)d64), "should be real oop");
577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
578 }
579 #endif
580 cbuf.relocate(cbuf.insts_mark(), rspec, format);
581 cbuf.insts()->emit_int64(d64);
582 }
583
584 // Access stack slot for load or store
585 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
586 {
587 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
588 if (-0x80 <= disp && disp < 0x80) {
589 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
590 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
591 emit_d8(cbuf, disp); // Displacement // R/M byte
592 } else {
593 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
594 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
595 emit_d32(cbuf, disp); // Displacement // R/M byte
596 }
597 }
598
599 // rRegI ereg, memory mem) %{ // emit_reg_mem
600 void encode_RegMem(CodeBuffer &cbuf,
601 int reg,
602 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
603 {
604 assert(disp_reloc == relocInfo::none, "cannot have disp");
605 int regenc = reg & 7;
606 int baseenc = base & 7;
607 int indexenc = index & 7;
608
609 // There is no index & no scale, use form without SIB byte
610 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
611 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
612 if (disp == 0 && base != RBP_enc && base != R13_enc) {
613 emit_rm(cbuf, 0x0, regenc, baseenc); // *
614 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
615 // If 8-bit displacement, mode 0x1
616 emit_rm(cbuf, 0x1, regenc, baseenc); // *
617 emit_d8(cbuf, disp);
618 } else {
619 // If 32-bit displacement
620 if (base == -1) { // Special flag for absolute address
621 emit_rm(cbuf, 0x0, regenc, 0x5); // *
622 if (disp_reloc != relocInfo::none) {
623 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
624 } else {
625 emit_d32(cbuf, disp);
626 }
627 } else {
628 // Normal base + offset
629 emit_rm(cbuf, 0x2, regenc, baseenc); // *
630 if (disp_reloc != relocInfo::none) {
631 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
632 } else {
633 emit_d32(cbuf, disp);
634 }
635 }
636 }
637 } else {
638 // Else, encode with the SIB byte
639 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
640 if (disp == 0 && base != RBP_enc && base != R13_enc) {
641 // If no displacement
642 emit_rm(cbuf, 0x0, regenc, 0x4); // *
643 emit_rm(cbuf, scale, indexenc, baseenc);
644 } else {
645 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
646 // If 8-bit displacement, mode 0x1
647 emit_rm(cbuf, 0x1, regenc, 0x4); // *
648 emit_rm(cbuf, scale, indexenc, baseenc);
649 emit_d8(cbuf, disp);
650 } else {
651 // If 32-bit displacement
652 if (base == 0x04 ) {
653 emit_rm(cbuf, 0x2, regenc, 0x4);
654 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
655 } else {
656 emit_rm(cbuf, 0x2, regenc, 0x4);
657 emit_rm(cbuf, scale, indexenc, baseenc); // *
658 }
659 if (disp_reloc != relocInfo::none) {
660 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
661 } else {
662 emit_d32(cbuf, disp);
663 }
664 }
665 }
666 }
667 }
668
669 // This could be in MacroAssembler but it's fairly C2 specific
670 void emit_cmpfp_fixup(MacroAssembler& _masm) {
671 Label exit;
672 __ jccb(Assembler::noParity, exit);
673 __ pushf();
674 //
675 // comiss/ucomiss instructions set ZF,PF,CF flags and
676 // zero OF,AF,SF for NaN values.
677 // Fixup flags by zeroing ZF,PF so that compare of NaN
678 // values returns 'less than' result (CF is set).
679 // Leave the rest of flags unchanged.
680 //
681 // 7 6 5 4 3 2 1 0
682 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
683 // 0 0 1 0 1 0 1 1 (0x2B)
684 //
685 __ andq(Address(rsp, 0), 0xffffff2b);
686 __ popf();
687 __ bind(exit);
688 }
689
690 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
691 Label done;
692 __ movl(dst, -1);
693 __ jcc(Assembler::parity, done);
694 __ jcc(Assembler::below, done);
695 __ setb(Assembler::notEqual, dst);
696 __ movzbl(dst, dst);
697 __ bind(done);
698 }
699
700 // Math.min() # Math.max()
701 // --------------------------
702 // ucomis[s/d] #
703 // ja -> b # a
704 // jp -> NaN # NaN
705 // jb -> a # b
706 // je #
707 // |-jz -> a | b # a & b
708 // | -> a #
709 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
710 XMMRegister a, XMMRegister b,
711 XMMRegister xmmt, Register rt,
712 bool min, bool single) {
713
714 Label nan, zero, below, above, done;
715
716 if (single)
717 __ ucomiss(a, b);
718 else
719 __ ucomisd(a, b);
720
721 if (dst->encoding() != (min ? b : a)->encoding())
722 __ jccb(Assembler::above, above); // CF=0 & ZF=0
723 else
724 __ jccb(Assembler::above, done);
725
726 __ jccb(Assembler::parity, nan); // PF=1
727 __ jccb(Assembler::below, below); // CF=1
728
729 // equal
730 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
731 if (single) {
732 __ ucomiss(a, xmmt);
733 __ jccb(Assembler::equal, zero);
734
735 __ movflt(dst, a);
736 __ jmp(done);
737 }
738 else {
739 __ ucomisd(a, xmmt);
740 __ jccb(Assembler::equal, zero);
741
742 __ movdbl(dst, a);
743 __ jmp(done);
744 }
745
746 __ bind(zero);
747 if (min)
748 __ vpor(dst, a, b, Assembler::AVX_128bit);
749 else
750 __ vpand(dst, a, b, Assembler::AVX_128bit);
751
752 __ jmp(done);
753
754 __ bind(above);
755 if (single)
756 __ movflt(dst, min ? b : a);
757 else
758 __ movdbl(dst, min ? b : a);
759
760 __ jmp(done);
761
762 __ bind(nan);
763 if (single) {
764 __ movl(rt, 0x7fc00000); // Float.NaN
765 __ movdl(dst, rt);
766 }
767 else {
768 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
769 __ movdq(dst, rt);
770 }
771 __ jmp(done);
772
773 __ bind(below);
774 if (single)
775 __ movflt(dst, min ? a : b);
776 else
777 __ movdbl(dst, min ? a : b);
778
779 __ bind(done);
780 }
781
782 //=============================================================================
783 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
784
785 int Compile::ConstantTable::calculate_table_base_offset() const {
786 return 0; // absolute addressing, no offset
787 }
788
789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
791 ShouldNotReachHere();
792 }
793
794 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
795 // Empty encoding
796 }
797
798 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
799 return 0;
800 }
801
802 #ifndef PRODUCT
803 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
804 st->print("# MachConstantBaseNode (empty encoding)");
805 }
806 #endif
807
808
809 //=============================================================================
810 #ifndef PRODUCT
811 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
812 Compile* C = ra_->C;
813
814 int framesize = C->frame_size_in_bytes();
815 int bangsize = C->bang_size_in_bytes();
816 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
817 // Remove wordSize for return addr which is already pushed.
818 framesize -= wordSize;
819
820 if (C->need_stack_bang(bangsize)) {
821 framesize -= wordSize;
822 st->print("# stack bang (%d bytes)", bangsize);
823 st->print("\n\t");
824 st->print("pushq rbp\t# Save rbp");
825 if (PreserveFramePointer) {
826 st->print("\n\t");
827 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
828 }
829 if (framesize) {
830 st->print("\n\t");
831 st->print("subq rsp, #%d\t# Create frame",framesize);
832 }
833 } else {
834 st->print("subq rsp, #%d\t# Create frame",framesize);
835 st->print("\n\t");
836 framesize -= wordSize;
837 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
838 if (PreserveFramePointer) {
839 st->print("\n\t");
840 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
841 if (framesize > 0) {
842 st->print("\n\t");
843 st->print("addq rbp, #%d", framesize);
844 }
845 }
846 }
847
848 if (VerifyStackAtCalls) {
849 st->print("\n\t");
850 framesize -= wordSize;
851 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
852 #ifdef ASSERT
853 st->print("\n\t");
854 st->print("# stack alignment check");
855 #endif
856 }
857 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
858 st->print("\n\t");
859 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
860 st->print("\n\t");
861 st->print("je fast_entry\t");
862 st->print("\n\t");
863 st->print("call #nmethod_entry_barrier_stub\t");
864 st->print("\n\tfast_entry:");
865 }
866 st->cr();
867 }
868 #endif
869
870 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
871 Compile* C = ra_->C;
872 MacroAssembler _masm(&cbuf);
873
874 int framesize = C->frame_size_in_bytes();
875 int bangsize = C->bang_size_in_bytes();
876
877 if (C->clinit_barrier_on_entry()) {
878 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
879 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
880
881 Label L_skip_barrier;
882 Register klass = rscratch1;
883
884 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
885 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
886
887 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
888
889 __ bind(L_skip_barrier);
890 }
891
892 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
893
894 C->set_frame_complete(cbuf.insts_size());
895
896 if (C->has_mach_constant_base_node()) {
897 // NOTE: We set the table base offset here because users might be
898 // emitted before MachConstantBaseNode.
899 Compile::ConstantTable& constant_table = C->constant_table();
900 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
901 }
902 }
903
904 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
905 {
906 return MachNode::size(ra_); // too many variables; just compute it
907 // the hard way
908 }
909
910 int MachPrologNode::reloc() const
911 {
912 return 0; // a large enough number
913 }
914
915 //=============================================================================
916 #ifndef PRODUCT
917 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
918 {
919 Compile* C = ra_->C;
920 if (generate_vzeroupper(C)) {
921 st->print("vzeroupper");
922 st->cr(); st->print("\t");
923 }
924
925 int framesize = C->frame_size_in_bytes();
926 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
927 // Remove word for return adr already pushed
928 // and RBP
929 framesize -= 2*wordSize;
930
931 if (framesize) {
932 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
933 st->print("\t");
934 }
935
936 st->print_cr("popq rbp");
937 if (do_polling() && C->is_method_compilation()) {
938 st->print("\t");
939 if (SafepointMechanism::uses_thread_local_poll()) {
940 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
941 "testl rax, [rscratch1]\t"
942 "# Safepoint: poll for GC");
943 } else if (Assembler::is_polling_page_far()) {
944 st->print_cr("movq rscratch1, #polling_page_address\n\t"
945 "testl rax, [rscratch1]\t"
946 "# Safepoint: poll for GC");
947 } else {
948 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
949 "# Safepoint: poll for GC");
950 }
951 }
952 }
953 #endif
954
955 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
956 {
957 Compile* C = ra_->C;
958 MacroAssembler _masm(&cbuf);
959
960 if (generate_vzeroupper(C)) {
961 // Clear upper bits of YMM registers when current compiled code uses
962 // wide vectors to avoid AVX <-> SSE transition penalty during call.
963 __ vzeroupper();
964 }
965
966 int framesize = C->frame_size_in_bytes();
967 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
968 // Remove word for return adr already pushed
969 // and RBP
970 framesize -= 2*wordSize;
971
972 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
973
974 if (framesize) {
975 emit_opcode(cbuf, Assembler::REX_W);
976 if (framesize < 0x80) {
977 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
978 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
979 emit_d8(cbuf, framesize);
980 } else {
981 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
982 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
983 emit_d32(cbuf, framesize);
984 }
985 }
986
987 // popq rbp
988 emit_opcode(cbuf, 0x58 | RBP_enc);
989
990 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
991 __ reserved_stack_check();
992 }
993
994 if (do_polling() && C->is_method_compilation()) {
995 MacroAssembler _masm(&cbuf);
996 if (SafepointMechanism::uses_thread_local_poll()) {
997 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
998 __ relocate(relocInfo::poll_return_type);
999 __ testl(rax, Address(rscratch1, 0));
1000 } else {
1001 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1002 if (Assembler::is_polling_page_far()) {
1003 __ lea(rscratch1, polling_page);
1004 __ relocate(relocInfo::poll_return_type);
1005 __ testl(rax, Address(rscratch1, 0));
1006 } else {
1007 __ testl(rax, polling_page);
1008 }
1009 }
1010 }
1011 }
1012
1013 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1014 {
1015 return MachNode::size(ra_); // too many variables; just compute it
1016 // the hard way
1017 }
1018
1019 int MachEpilogNode::reloc() const
1020 {
1021 return 2; // a large enough number
1022 }
1023
1024 const Pipeline* MachEpilogNode::pipeline() const
1025 {
1026 return MachNode::pipeline_class();
1027 }
1028
1029 int MachEpilogNode::safepoint_offset() const
1030 {
1031 return 0;
1032 }
1033
1034 //=============================================================================
1035
1036 enum RC {
1037 rc_bad,
1038 rc_int,
1039 rc_float,
1040 rc_stack
1041 };
1042
1043 static enum RC rc_class(OptoReg::Name reg)
1044 {
1045 if( !OptoReg::is_valid(reg) ) return rc_bad;
1046
1047 if (OptoReg::is_stack(reg)) return rc_stack;
1048
1049 VMReg r = OptoReg::as_VMReg(reg);
1050
1051 if (r->is_Register()) return rc_int;
1052
1053 assert(r->is_XMMRegister(), "must be");
1054 return rc_float;
1055 }
1056
1057 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1058 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1059 int src_hi, int dst_hi, uint ireg, outputStream* st);
1060
1061 int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1062 int stack_offset, int reg, uint ireg, outputStream* st);
1063
1064 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1065 int dst_offset, uint ireg, outputStream* st) {
1066 if (cbuf) {
1067 MacroAssembler _masm(cbuf);
1068 switch (ireg) {
1069 case Op_VecS:
1070 __ movq(Address(rsp, -8), rax);
1071 __ movl(rax, Address(rsp, src_offset));
1072 __ movl(Address(rsp, dst_offset), rax);
1073 __ movq(rax, Address(rsp, -8));
1074 break;
1075 case Op_VecD:
1076 __ pushq(Address(rsp, src_offset));
1077 __ popq (Address(rsp, dst_offset));
1078 break;
1079 case Op_VecX:
1080 __ pushq(Address(rsp, src_offset));
1081 __ popq (Address(rsp, dst_offset));
1082 __ pushq(Address(rsp, src_offset+8));
1083 __ popq (Address(rsp, dst_offset+8));
1084 break;
1085 case Op_VecY:
1086 __ vmovdqu(Address(rsp, -32), xmm0);
1087 __ vmovdqu(xmm0, Address(rsp, src_offset));
1088 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1089 __ vmovdqu(xmm0, Address(rsp, -32));
1090 break;
1091 case Op_VecZ:
1092 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1093 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1094 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1095 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1096 break;
1097 default:
1098 ShouldNotReachHere();
1099 }
1100 #ifndef PRODUCT
1101 } else {
1102 switch (ireg) {
1103 case Op_VecS:
1104 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1105 "movl rax, [rsp + #%d]\n\t"
1106 "movl [rsp + #%d], rax\n\t"
1107 "movq rax, [rsp - #8]",
1108 src_offset, dst_offset);
1109 break;
1110 case Op_VecD:
1111 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1112 "popq [rsp + #%d]",
1113 src_offset, dst_offset);
1114 break;
1115 case Op_VecX:
1116 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1117 "popq [rsp + #%d]\n\t"
1118 "pushq [rsp + #%d]\n\t"
1119 "popq [rsp + #%d]",
1120 src_offset, dst_offset, src_offset+8, dst_offset+8);
1121 break;
1122 case Op_VecY:
1123 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1124 "vmovdqu xmm0, [rsp + #%d]\n\t"
1125 "vmovdqu [rsp + #%d], xmm0\n\t"
1126 "vmovdqu xmm0, [rsp - #32]",
1127 src_offset, dst_offset);
1128 break;
1129 case Op_VecZ:
1130 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1131 "vmovdqu xmm0, [rsp + #%d]\n\t"
1132 "vmovdqu [rsp + #%d], xmm0\n\t"
1133 "vmovdqu xmm0, [rsp - #64]",
1134 src_offset, dst_offset);
1135 break;
1136 default:
1137 ShouldNotReachHere();
1138 }
1139 #endif
1140 }
1141 }
1142
1143 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1144 PhaseRegAlloc* ra_,
1145 bool do_size,
1146 outputStream* st) const {
1147 assert(cbuf != NULL || st != NULL, "sanity");
1148 // Get registers to move
1149 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1150 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1151 OptoReg::Name dst_second = ra_->get_reg_second(this);
1152 OptoReg::Name dst_first = ra_->get_reg_first(this);
1153
1154 enum RC src_second_rc = rc_class(src_second);
1155 enum RC src_first_rc = rc_class(src_first);
1156 enum RC dst_second_rc = rc_class(dst_second);
1157 enum RC dst_first_rc = rc_class(dst_first);
1158
1159 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1160 "must move at least 1 register" );
1161
1162 if (src_first == dst_first && src_second == dst_second) {
1163 // Self copy, no move
1164 return 0;
1165 }
1166 if (bottom_type()->isa_vect() != NULL) {
1167 uint ireg = ideal_reg();
1168 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1169 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1170 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1171 // mem -> mem
1172 int src_offset = ra_->reg2offset(src_first);
1173 int dst_offset = ra_->reg2offset(dst_first);
1174 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1175 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1176 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1177 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1178 int stack_offset = ra_->reg2offset(dst_first);
1179 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1180 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1181 int stack_offset = ra_->reg2offset(src_first);
1182 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1183 } else {
1184 ShouldNotReachHere();
1185 }
1186 return 0;
1187 }
1188 if (src_first_rc == rc_stack) {
1189 // mem ->
1190 if (dst_first_rc == rc_stack) {
1191 // mem -> mem
1192 assert(src_second != dst_first, "overlap");
1193 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1194 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1195 // 64-bit
1196 int src_offset = ra_->reg2offset(src_first);
1197 int dst_offset = ra_->reg2offset(dst_first);
1198 if (cbuf) {
1199 MacroAssembler _masm(cbuf);
1200 __ pushq(Address(rsp, src_offset));
1201 __ popq (Address(rsp, dst_offset));
1202 #ifndef PRODUCT
1203 } else {
1204 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1205 "popq [rsp + #%d]",
1206 src_offset, dst_offset);
1207 #endif
1208 }
1209 } else {
1210 // 32-bit
1211 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1212 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1213 // No pushl/popl, so:
1214 int src_offset = ra_->reg2offset(src_first);
1215 int dst_offset = ra_->reg2offset(dst_first);
1216 if (cbuf) {
1217 MacroAssembler _masm(cbuf);
1218 __ movq(Address(rsp, -8), rax);
1219 __ movl(rax, Address(rsp, src_offset));
1220 __ movl(Address(rsp, dst_offset), rax);
1221 __ movq(rax, Address(rsp, -8));
1222 #ifndef PRODUCT
1223 } else {
1224 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1225 "movl rax, [rsp + #%d]\n\t"
1226 "movl [rsp + #%d], rax\n\t"
1227 "movq rax, [rsp - #8]",
1228 src_offset, dst_offset);
1229 #endif
1230 }
1231 }
1232 return 0;
1233 } else if (dst_first_rc == rc_int) {
1234 // mem -> gpr
1235 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1236 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1237 // 64-bit
1238 int offset = ra_->reg2offset(src_first);
1239 if (cbuf) {
1240 MacroAssembler _masm(cbuf);
1241 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1242 #ifndef PRODUCT
1243 } else {
1244 st->print("movq %s, [rsp + #%d]\t# spill",
1245 Matcher::regName[dst_first],
1246 offset);
1247 #endif
1248 }
1249 } else {
1250 // 32-bit
1251 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1252 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1253 int offset = ra_->reg2offset(src_first);
1254 if (cbuf) {
1255 MacroAssembler _masm(cbuf);
1256 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1257 #ifndef PRODUCT
1258 } else {
1259 st->print("movl %s, [rsp + #%d]\t# spill",
1260 Matcher::regName[dst_first],
1261 offset);
1262 #endif
1263 }
1264 }
1265 return 0;
1266 } else if (dst_first_rc == rc_float) {
1267 // mem-> xmm
1268 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1269 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1270 // 64-bit
1271 int offset = ra_->reg2offset(src_first);
1272 if (cbuf) {
1273 MacroAssembler _masm(cbuf);
1274 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1275 #ifndef PRODUCT
1276 } else {
1277 st->print("%s %s, [rsp + #%d]\t# spill",
1278 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1279 Matcher::regName[dst_first],
1280 offset);
1281 #endif
1282 }
1283 } else {
1284 // 32-bit
1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1287 int offset = ra_->reg2offset(src_first);
1288 if (cbuf) {
1289 MacroAssembler _masm(cbuf);
1290 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1291 #ifndef PRODUCT
1292 } else {
1293 st->print("movss %s, [rsp + #%d]\t# spill",
1294 Matcher::regName[dst_first],
1295 offset);
1296 #endif
1297 }
1298 }
1299 return 0;
1300 }
1301 } else if (src_first_rc == rc_int) {
1302 // gpr ->
1303 if (dst_first_rc == rc_stack) {
1304 // gpr -> mem
1305 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1306 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1307 // 64-bit
1308 int offset = ra_->reg2offset(dst_first);
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1312 #ifndef PRODUCT
1313 } else {
1314 st->print("movq [rsp + #%d], %s\t# spill",
1315 offset,
1316 Matcher::regName[src_first]);
1317 #endif
1318 }
1319 } else {
1320 // 32-bit
1321 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1322 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1323 int offset = ra_->reg2offset(dst_first);
1324 if (cbuf) {
1325 MacroAssembler _masm(cbuf);
1326 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1327 #ifndef PRODUCT
1328 } else {
1329 st->print("movl [rsp + #%d], %s\t# spill",
1330 offset,
1331 Matcher::regName[src_first]);
1332 #endif
1333 }
1334 }
1335 return 0;
1336 } else if (dst_first_rc == rc_int) {
1337 // gpr -> gpr
1338 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1339 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1340 // 64-bit
1341 if (cbuf) {
1342 MacroAssembler _masm(cbuf);
1343 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1344 as_Register(Matcher::_regEncode[src_first]));
1345 #ifndef PRODUCT
1346 } else {
1347 st->print("movq %s, %s\t# spill",
1348 Matcher::regName[dst_first],
1349 Matcher::regName[src_first]);
1350 #endif
1351 }
1352 return 0;
1353 } else {
1354 // 32-bit
1355 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1356 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1357 if (cbuf) {
1358 MacroAssembler _masm(cbuf);
1359 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1360 as_Register(Matcher::_regEncode[src_first]));
1361 #ifndef PRODUCT
1362 } else {
1363 st->print("movl %s, %s\t# spill",
1364 Matcher::regName[dst_first],
1365 Matcher::regName[src_first]);
1366 #endif
1367 }
1368 return 0;
1369 }
1370 } else if (dst_first_rc == rc_float) {
1371 // gpr -> xmm
1372 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1373 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1374 // 64-bit
1375 if (cbuf) {
1376 MacroAssembler _masm(cbuf);
1377 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1378 #ifndef PRODUCT
1379 } else {
1380 st->print("movdq %s, %s\t# spill",
1381 Matcher::regName[dst_first],
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 } else {
1386 // 32-bit
1387 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1388 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1389 if (cbuf) {
1390 MacroAssembler _masm(cbuf);
1391 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1392 #ifndef PRODUCT
1393 } else {
1394 st->print("movdl %s, %s\t# spill",
1395 Matcher::regName[dst_first],
1396 Matcher::regName[src_first]);
1397 #endif
1398 }
1399 }
1400 return 0;
1401 }
1402 } else if (src_first_rc == rc_float) {
1403 // xmm ->
1404 if (dst_first_rc == rc_stack) {
1405 // xmm -> mem
1406 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1407 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1408 // 64-bit
1409 int offset = ra_->reg2offset(dst_first);
1410 if (cbuf) {
1411 MacroAssembler _masm(cbuf);
1412 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1413 #ifndef PRODUCT
1414 } else {
1415 st->print("movsd [rsp + #%d], %s\t# spill",
1416 offset,
1417 Matcher::regName[src_first]);
1418 #endif
1419 }
1420 } else {
1421 // 32-bit
1422 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1423 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1424 int offset = ra_->reg2offset(dst_first);
1425 if (cbuf) {
1426 MacroAssembler _masm(cbuf);
1427 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1428 #ifndef PRODUCT
1429 } else {
1430 st->print("movss [rsp + #%d], %s\t# spill",
1431 offset,
1432 Matcher::regName[src_first]);
1433 #endif
1434 }
1435 }
1436 return 0;
1437 } else if (dst_first_rc == rc_int) {
1438 // xmm -> gpr
1439 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1440 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1441 // 64-bit
1442 if (cbuf) {
1443 MacroAssembler _masm(cbuf);
1444 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1445 #ifndef PRODUCT
1446 } else {
1447 st->print("movdq %s, %s\t# spill",
1448 Matcher::regName[dst_first],
1449 Matcher::regName[src_first]);
1450 #endif
1451 }
1452 } else {
1453 // 32-bit
1454 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1455 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1456 if (cbuf) {
1457 MacroAssembler _masm(cbuf);
1458 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1459 #ifndef PRODUCT
1460 } else {
1461 st->print("movdl %s, %s\t# spill",
1462 Matcher::regName[dst_first],
1463 Matcher::regName[src_first]);
1464 #endif
1465 }
1466 }
1467 return 0;
1468 } else if (dst_first_rc == rc_float) {
1469 // xmm -> xmm
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1471 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1472 // 64-bit
1473 if (cbuf) {
1474 MacroAssembler _masm(cbuf);
1475 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1476 #ifndef PRODUCT
1477 } else {
1478 st->print("%s %s, %s\t# spill",
1479 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1480 Matcher::regName[dst_first],
1481 Matcher::regName[src_first]);
1482 #endif
1483 }
1484 } else {
1485 // 32-bit
1486 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1487 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1488 if (cbuf) {
1489 MacroAssembler _masm(cbuf);
1490 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1491 #ifndef PRODUCT
1492 } else {
1493 st->print("%s %s, %s\t# spill",
1494 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1495 Matcher::regName[dst_first],
1496 Matcher::regName[src_first]);
1497 #endif
1498 }
1499 }
1500 return 0;
1501 }
1502 }
1503
1504 assert(0," foo ");
1505 Unimplemented();
1506 return 0;
1507 }
1508
1509 #ifndef PRODUCT
1510 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1511 implementation(NULL, ra_, false, st);
1512 }
1513 #endif
1514
1515 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1516 implementation(&cbuf, ra_, false, NULL);
1517 }
1518
1519 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1520 return MachNode::size(ra_);
1521 }
1522
1523 //=============================================================================
1524 #ifndef PRODUCT
1525 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1526 {
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1528 int reg = ra_->get_reg_first(this);
1529 st->print("leaq %s, [rsp + #%d]\t# box lock",
1530 Matcher::regName[reg], offset);
1531 }
1532 #endif
1533
1534 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1535 {
1536 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1537 int reg = ra_->get_encode(this);
1538 if (offset >= 0x80) {
1539 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1540 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1541 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1542 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1543 emit_d32(cbuf, offset);
1544 } else {
1545 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1546 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1547 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1548 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1549 emit_d8(cbuf, offset);
1550 }
1551 }
1552
1553 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1554 {
1555 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1556 return (offset < 0x80) ? 5 : 8; // REX
1557 }
1558
1559 //=============================================================================
1560 #ifndef PRODUCT
1561 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1562 {
1563 if (UseCompressedClassPointers) {
1564 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1565 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1566 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1567 } else {
1568 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1569 "# Inline cache check");
1570 }
1571 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1572 st->print_cr("\tnop\t# nops to align entry point");
1573 }
1574 #endif
1575
1576 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1577 {
1578 MacroAssembler masm(&cbuf);
1579 uint insts_size = cbuf.insts_size();
1580 if (UseCompressedClassPointers) {
1581 masm.load_klass(rscratch1, j_rarg0);
1582 masm.cmpptr(rax, rscratch1);
1583 } else {
1584 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1585 }
1586
1587 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1588
1589 /* WARNING these NOPs are critical so that verified entry point is properly
1590 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1591 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1592 if (OptoBreakpoint) {
1593 // Leave space for int3
1594 nops_cnt -= 1;
1595 }
1596 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1597 if (nops_cnt > 0)
1598 masm.nop(nops_cnt);
1599 }
1600
1601 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1602 {
1603 return MachNode::size(ra_); // too many variables; just compute it
1604 // the hard way
1605 }
1606
1607
1608 //=============================================================================
1609
1610 int Matcher::regnum_to_fpu_offset(int regnum)
1611 {
1612 return regnum - 32; // The FP registers are in the second chunk
1613 }
1614
1615 // This is UltraSparc specific, true just means we have fast l2f conversion
1616 const bool Matcher::convL2FSupported(void) {
1617 return true;
1618 }
1619
1620 // Is this branch offset short enough that a short branch can be used?
1621 //
1622 // NOTE: If the platform does not provide any short branch variants, then
1623 // this method should return false for offset 0.
1624 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1625 // The passed offset is relative to address of the branch.
1626 // On 86 a branch displacement is calculated relative to address
1627 // of a next instruction.
1628 offset -= br_size;
1629
1630 // the short version of jmpConUCF2 contains multiple branches,
1631 // making the reach slightly less
1632 if (rule == jmpConUCF2_rule)
1633 return (-126 <= offset && offset <= 125);
1634 return (-128 <= offset && offset <= 127);
1635 }
1636
1637 const bool Matcher::isSimpleConstant64(jlong value) {
1638 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1639 //return value == (int) value; // Cf. storeImmL and immL32.
1640
1641 // Probably always true, even if a temp register is required.
1642 return true;
1643 }
1644
1645 // The ecx parameter to rep stosq for the ClearArray node is in words.
1646 const bool Matcher::init_array_count_is_in_bytes = false;
1647
1648 // No additional cost for CMOVL.
1649 const int Matcher::long_cmove_cost() { return 0; }
1650
1651 // No CMOVF/CMOVD with SSE2
1652 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1653
1654 // Does the CPU require late expand (see block.cpp for description of late expand)?
1655 const bool Matcher::require_postalloc_expand = false;
1656
1657 // Do we need to mask the count passed to shift instructions or does
1658 // the cpu only look at the lower 5/6 bits anyway?
1659 const bool Matcher::need_masked_shift_count = false;
1660
1661 bool Matcher::narrow_oop_use_complex_address() {
1662 assert(UseCompressedOops, "only for compressed oops code");
1663 return (LogMinObjAlignmentInBytes <= 3);
1664 }
1665
1666 bool Matcher::narrow_klass_use_complex_address() {
1667 assert(UseCompressedClassPointers, "only for compressed klass code");
1668 return (LogKlassAlignmentInBytes <= 3);
1669 }
1670
1671 bool Matcher::const_oop_prefer_decode() {
1672 // Prefer ConN+DecodeN over ConP.
1673 return true;
1674 }
1675
1676 bool Matcher::const_klass_prefer_decode() {
1677 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1678 // or condisider the following:
1679 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1680 //return CompressedKlassPointers::base() == NULL;
1681 return true;
1682 }
1683
1684 // Is it better to copy float constants, or load them directly from
1685 // memory? Intel can load a float constant from a direct address,
1686 // requiring no extra registers. Most RISCs will have to materialize
1687 // an address into a register first, so they would do better to copy
1688 // the constant from stack.
1689 const bool Matcher::rematerialize_float_constants = true; // XXX
1690
1691 // If CPU can load and store mis-aligned doubles directly then no
1692 // fixup is needed. Else we split the double into 2 integer pieces
1693 // and move it piece-by-piece. Only happens when passing doubles into
1694 // C code as the Java calling convention forces doubles to be aligned.
1695 const bool Matcher::misaligned_doubles_ok = true;
1696
1697 // No-op on amd64
1698 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1699
1700 // Advertise here if the CPU requires explicit rounding operations to
1701 // implement the UseStrictFP mode.
1702 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1703
1704 // Are floats conerted to double when stored to stack during deoptimization?
1705 // On x64 it is stored without convertion so we can use normal access.
1706 bool Matcher::float_in_double() { return false; }
1707
1708 // Do ints take an entire long register or just half?
1709 const bool Matcher::int_in_long = true;
1710
1711 // Return whether or not this register is ever used as an argument.
1712 // This function is used on startup to build the trampoline stubs in
1713 // generateOptoStub. Registers not mentioned will be killed by the VM
1714 // call in the trampoline, and arguments in those registers not be
1715 // available to the callee.
1716 bool Matcher::can_be_java_arg(int reg)
1717 {
1718 return
1719 reg == RDI_num || reg == RDI_H_num ||
1720 reg == RSI_num || reg == RSI_H_num ||
1721 reg == RDX_num || reg == RDX_H_num ||
1722 reg == RCX_num || reg == RCX_H_num ||
1723 reg == R8_num || reg == R8_H_num ||
1724 reg == R9_num || reg == R9_H_num ||
1725 reg == R12_num || reg == R12_H_num ||
1726 reg == XMM0_num || reg == XMM0b_num ||
1727 reg == XMM1_num || reg == XMM1b_num ||
1728 reg == XMM2_num || reg == XMM2b_num ||
1729 reg == XMM3_num || reg == XMM3b_num ||
1730 reg == XMM4_num || reg == XMM4b_num ||
1731 reg == XMM5_num || reg == XMM5b_num ||
1732 reg == XMM6_num || reg == XMM6b_num ||
1733 reg == XMM7_num || reg == XMM7b_num;
1734 }
1735
1736 bool Matcher::is_spillable_arg(int reg)
1737 {
1738 return can_be_java_arg(reg);
1739 }
1740
1741 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1742 // In 64 bit mode a code which use multiply when
1743 // devisor is constant is faster than hardware
1744 // DIV instruction (it uses MulHiL).
1745 return false;
1746 }
1747
1748 // Register for DIVI projection of divmodI
1749 RegMask Matcher::divI_proj_mask() {
1750 return INT_RAX_REG_mask();
1751 }
1752
1753 // Register for MODI projection of divmodI
1754 RegMask Matcher::modI_proj_mask() {
1755 return INT_RDX_REG_mask();
1756 }
1757
1758 // Register for DIVL projection of divmodL
1759 RegMask Matcher::divL_proj_mask() {
1760 return LONG_RAX_REG_mask();
1761 }
1762
1763 // Register for MODL projection of divmodL
1764 RegMask Matcher::modL_proj_mask() {
1765 return LONG_RDX_REG_mask();
1766 }
1767
1768 // Register for saving SP into on method handle invokes. Not used on x86_64.
1769 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1770 return NO_REG_mask();
1771 }
1772
1773 %}
1774
1775 //----------ENCODING BLOCK-----------------------------------------------------
1776 // This block specifies the encoding classes used by the compiler to
1777 // output byte streams. Encoding classes are parameterized macros
1778 // used by Machine Instruction Nodes in order to generate the bit
1779 // encoding of the instruction. Operands specify their base encoding
1780 // interface with the interface keyword. There are currently
1781 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1782 // COND_INTER. REG_INTER causes an operand to generate a function
1783 // which returns its register number when queried. CONST_INTER causes
1784 // an operand to generate a function which returns the value of the
1785 // constant when queried. MEMORY_INTER causes an operand to generate
1786 // four functions which return the Base Register, the Index Register,
1787 // the Scale Value, and the Offset Value of the operand when queried.
1788 // COND_INTER causes an operand to generate six functions which return
1789 // the encoding code (ie - encoding bits for the instruction)
1790 // associated with each basic boolean condition for a conditional
1791 // instruction.
1792 //
1793 // Instructions specify two basic values for encoding. Again, a
1794 // function is available to check if the constant displacement is an
1795 // oop. They use the ins_encode keyword to specify their encoding
1796 // classes (which must be a sequence of enc_class names, and their
1797 // parameters, specified in the encoding block), and they use the
1798 // opcode keyword to specify, in order, their primary, secondary, and
1799 // tertiary opcode. Only the opcode sections which a particular
1800 // instruction needs for encoding need to be specified.
1801 encode %{
1802 // Build emit functions for each basic byte or larger field in the
1803 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1804 // from C++ code in the enc_class source block. Emit functions will
1805 // live in the main source block for now. In future, we can
1806 // generalize this by adding a syntax that specifies the sizes of
1807 // fields in an order, so that the adlc can build the emit functions
1808 // automagically
1809
1810 // Emit primary opcode
1811 enc_class OpcP
1812 %{
1813 emit_opcode(cbuf, $primary);
1814 %}
1815
1816 // Emit secondary opcode
1817 enc_class OpcS
1818 %{
1819 emit_opcode(cbuf, $secondary);
1820 %}
1821
1822 // Emit tertiary opcode
1823 enc_class OpcT
1824 %{
1825 emit_opcode(cbuf, $tertiary);
1826 %}
1827
1828 // Emit opcode directly
1829 enc_class Opcode(immI d8)
1830 %{
1831 emit_opcode(cbuf, $d8$$constant);
1832 %}
1833
1834 // Emit size prefix
1835 enc_class SizePrefix
1836 %{
1837 emit_opcode(cbuf, 0x66);
1838 %}
1839
1840 enc_class reg(rRegI reg)
1841 %{
1842 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1843 %}
1844
1845 enc_class reg_reg(rRegI dst, rRegI src)
1846 %{
1847 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1848 %}
1849
1850 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1851 %{
1852 emit_opcode(cbuf, $opcode$$constant);
1853 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1854 %}
1855
1856 enc_class cdql_enc(no_rax_rdx_RegI div)
1857 %{
1858 // Full implementation of Java idiv and irem; checks for
1859 // special case as described in JVM spec., p.243 & p.271.
1860 //
1861 // normal case special case
1862 //
1863 // input : rax: dividend min_int
1864 // reg: divisor -1
1865 //
1866 // output: rax: quotient (= rax idiv reg) min_int
1867 // rdx: remainder (= rax irem reg) 0
1868 //
1869 // Code sequnce:
1870 //
1871 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1872 // 5: 75 07/08 jne e <normal>
1873 // 7: 33 d2 xor %edx,%edx
1874 // [div >= 8 -> offset + 1]
1875 // [REX_B]
1876 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1877 // c: 74 03/04 je 11 <done>
1878 // 000000000000000e <normal>:
1879 // e: 99 cltd
1880 // [div >= 8 -> offset + 1]
1881 // [REX_B]
1882 // f: f7 f9 idiv $div
1883 // 0000000000000011 <done>:
1884
1885 // cmp $0x80000000,%eax
1886 emit_opcode(cbuf, 0x3d);
1887 emit_d8(cbuf, 0x00);
1888 emit_d8(cbuf, 0x00);
1889 emit_d8(cbuf, 0x00);
1890 emit_d8(cbuf, 0x80);
1891
1892 // jne e <normal>
1893 emit_opcode(cbuf, 0x75);
1894 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1895
1896 // xor %edx,%edx
1897 emit_opcode(cbuf, 0x33);
1898 emit_d8(cbuf, 0xD2);
1899
1900 // cmp $0xffffffffffffffff,%ecx
1901 if ($div$$reg >= 8) {
1902 emit_opcode(cbuf, Assembler::REX_B);
1903 }
1904 emit_opcode(cbuf, 0x83);
1905 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1906 emit_d8(cbuf, 0xFF);
1907
1908 // je 11 <done>
1909 emit_opcode(cbuf, 0x74);
1910 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1911
1912 // <normal>
1913 // cltd
1914 emit_opcode(cbuf, 0x99);
1915
1916 // idivl (note: must be emitted by the user of this rule)
1917 // <done>
1918 %}
1919
1920 enc_class cdqq_enc(no_rax_rdx_RegL div)
1921 %{
1922 // Full implementation of Java ldiv and lrem; checks for
1923 // special case as described in JVM spec., p.243 & p.271.
1924 //
1925 // normal case special case
1926 //
1927 // input : rax: dividend min_long
1928 // reg: divisor -1
1929 //
1930 // output: rax: quotient (= rax idiv reg) min_long
1931 // rdx: remainder (= rax irem reg) 0
1932 //
1933 // Code sequnce:
1934 //
1935 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1936 // 7: 00 00 80
1937 // a: 48 39 d0 cmp %rdx,%rax
1938 // d: 75 08 jne 17 <normal>
1939 // f: 33 d2 xor %edx,%edx
1940 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1941 // 15: 74 05 je 1c <done>
1942 // 0000000000000017 <normal>:
1943 // 17: 48 99 cqto
1944 // 19: 48 f7 f9 idiv $div
1945 // 000000000000001c <done>:
1946
1947 // mov $0x8000000000000000,%rdx
1948 emit_opcode(cbuf, Assembler::REX_W);
1949 emit_opcode(cbuf, 0xBA);
1950 emit_d8(cbuf, 0x00);
1951 emit_d8(cbuf, 0x00);
1952 emit_d8(cbuf, 0x00);
1953 emit_d8(cbuf, 0x00);
1954 emit_d8(cbuf, 0x00);
1955 emit_d8(cbuf, 0x00);
1956 emit_d8(cbuf, 0x00);
1957 emit_d8(cbuf, 0x80);
1958
1959 // cmp %rdx,%rax
1960 emit_opcode(cbuf, Assembler::REX_W);
1961 emit_opcode(cbuf, 0x39);
1962 emit_d8(cbuf, 0xD0);
1963
1964 // jne 17 <normal>
1965 emit_opcode(cbuf, 0x75);
1966 emit_d8(cbuf, 0x08);
1967
1968 // xor %edx,%edx
1969 emit_opcode(cbuf, 0x33);
1970 emit_d8(cbuf, 0xD2);
1971
1972 // cmp $0xffffffffffffffff,$div
1973 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1974 emit_opcode(cbuf, 0x83);
1975 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1976 emit_d8(cbuf, 0xFF);
1977
1978 // je 1e <done>
1979 emit_opcode(cbuf, 0x74);
1980 emit_d8(cbuf, 0x05);
1981
1982 // <normal>
1983 // cqto
1984 emit_opcode(cbuf, Assembler::REX_W);
1985 emit_opcode(cbuf, 0x99);
1986
1987 // idivq (note: must be emitted by the user of this rule)
1988 // <done>
1989 %}
1990
1991 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1992 enc_class OpcSE(immI imm)
1993 %{
1994 // Emit primary opcode and set sign-extend bit
1995 // Check for 8-bit immediate, and set sign extend bit in opcode
1996 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1997 emit_opcode(cbuf, $primary | 0x02);
1998 } else {
1999 // 32-bit immediate
2000 emit_opcode(cbuf, $primary);
2001 }
2002 %}
2003
2004 enc_class OpcSErm(rRegI dst, immI imm)
2005 %{
2006 // OpcSEr/m
2007 int dstenc = $dst$$reg;
2008 if (dstenc >= 8) {
2009 emit_opcode(cbuf, Assembler::REX_B);
2010 dstenc -= 8;
2011 }
2012 // Emit primary opcode and set sign-extend bit
2013 // Check for 8-bit immediate, and set sign extend bit in opcode
2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2015 emit_opcode(cbuf, $primary | 0x02);
2016 } else {
2017 // 32-bit immediate
2018 emit_opcode(cbuf, $primary);
2019 }
2020 // Emit r/m byte with secondary opcode, after primary opcode.
2021 emit_rm(cbuf, 0x3, $secondary, dstenc);
2022 %}
2023
2024 enc_class OpcSErm_wide(rRegL dst, immI imm)
2025 %{
2026 // OpcSEr/m
2027 int dstenc = $dst$$reg;
2028 if (dstenc < 8) {
2029 emit_opcode(cbuf, Assembler::REX_W);
2030 } else {
2031 emit_opcode(cbuf, Assembler::REX_WB);
2032 dstenc -= 8;
2033 }
2034 // Emit primary opcode and set sign-extend bit
2035 // Check for 8-bit immediate, and set sign extend bit in opcode
2036 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2037 emit_opcode(cbuf, $primary | 0x02);
2038 } else {
2039 // 32-bit immediate
2040 emit_opcode(cbuf, $primary);
2041 }
2042 // Emit r/m byte with secondary opcode, after primary opcode.
2043 emit_rm(cbuf, 0x3, $secondary, dstenc);
2044 %}
2045
2046 enc_class Con8or32(immI imm)
2047 %{
2048 // Check for 8-bit immediate, and set sign extend bit in opcode
2049 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2050 $$$emit8$imm$$constant;
2051 } else {
2052 // 32-bit immediate
2053 $$$emit32$imm$$constant;
2054 }
2055 %}
2056
2057 enc_class opc2_reg(rRegI dst)
2058 %{
2059 // BSWAP
2060 emit_cc(cbuf, $secondary, $dst$$reg);
2061 %}
2062
2063 enc_class opc3_reg(rRegI dst)
2064 %{
2065 // BSWAP
2066 emit_cc(cbuf, $tertiary, $dst$$reg);
2067 %}
2068
2069 enc_class reg_opc(rRegI div)
2070 %{
2071 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2072 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2073 %}
2074
2075 enc_class enc_cmov(cmpOp cop)
2076 %{
2077 // CMOV
2078 $$$emit8$primary;
2079 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2080 %}
2081
2082 enc_class enc_PartialSubtypeCheck()
2083 %{
2084 Register Rrdi = as_Register(RDI_enc); // result register
2085 Register Rrax = as_Register(RAX_enc); // super class
2086 Register Rrcx = as_Register(RCX_enc); // killed
2087 Register Rrsi = as_Register(RSI_enc); // sub class
2088 Label miss;
2089 const bool set_cond_codes = true;
2090
2091 MacroAssembler _masm(&cbuf);
2092 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2093 NULL, &miss,
2094 /*set_cond_codes:*/ true);
2095 if ($primary) {
2096 __ xorptr(Rrdi, Rrdi);
2097 }
2098 __ bind(miss);
2099 %}
2100
2101 enc_class clear_avx %{
2102 debug_only(int off0 = cbuf.insts_size());
2103 if (generate_vzeroupper(Compile::current())) {
2104 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2105 // Clear upper bits of YMM registers when current compiled code uses
2106 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2107 MacroAssembler _masm(&cbuf);
2108 __ vzeroupper();
2109 }
2110 debug_only(int off1 = cbuf.insts_size());
2111 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2112 %}
2113
2114 enc_class Java_To_Runtime(method meth) %{
2115 // No relocation needed
2116 MacroAssembler _masm(&cbuf);
2117 __ mov64(r10, (int64_t) $meth$$method);
2118 __ call(r10);
2119 %}
2120
2121 enc_class Java_To_Interpreter(method meth)
2122 %{
2123 // CALL Java_To_Interpreter
2124 // This is the instruction starting address for relocation info.
2125 cbuf.set_insts_mark();
2126 $$$emit8$primary;
2127 // CALL directly to the runtime
2128 emit_d32_reloc(cbuf,
2129 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2130 runtime_call_Relocation::spec(),
2131 RELOC_DISP32);
2132 %}
2133
2134 enc_class Java_Static_Call(method meth)
2135 %{
2136 // JAVA STATIC CALL
2137 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2138 // determine who we intended to call.
2139 cbuf.set_insts_mark();
2140 $$$emit8$primary;
2141
2142 if (!_method) {
2143 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2144 runtime_call_Relocation::spec(),
2145 RELOC_DISP32);
2146 } else {
2147 int method_index = resolved_method_index(cbuf);
2148 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2149 : static_call_Relocation::spec(method_index);
2150 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2151 rspec, RELOC_DISP32);
2152 // Emit stubs for static call.
2153 address mark = cbuf.insts_mark();
2154 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2155 if (stub == NULL) {
2156 ciEnv::current()->record_failure("CodeCache is full");
2157 return;
2158 }
2159 #if INCLUDE_AOT
2160 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2161 #endif
2162 }
2163 %}
2164
2165 enc_class Java_Dynamic_Call(method meth) %{
2166 MacroAssembler _masm(&cbuf);
2167 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2168 %}
2169
2170 enc_class Java_Compiled_Call(method meth)
2171 %{
2172 // JAVA COMPILED CALL
2173 int disp = in_bytes(Method:: from_compiled_offset());
2174
2175 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2176 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2177
2178 // callq *disp(%rax)
2179 cbuf.set_insts_mark();
2180 $$$emit8$primary;
2181 if (disp < 0x80) {
2182 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2183 emit_d8(cbuf, disp); // Displacement
2184 } else {
2185 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2186 emit_d32(cbuf, disp); // Displacement
2187 }
2188 %}
2189
2190 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2191 %{
2192 // SAL, SAR, SHR
2193 int dstenc = $dst$$reg;
2194 if (dstenc >= 8) {
2195 emit_opcode(cbuf, Assembler::REX_B);
2196 dstenc -= 8;
2197 }
2198 $$$emit8$primary;
2199 emit_rm(cbuf, 0x3, $secondary, dstenc);
2200 $$$emit8$shift$$constant;
2201 %}
2202
2203 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2204 %{
2205 // SAL, SAR, SHR
2206 int dstenc = $dst$$reg;
2207 if (dstenc < 8) {
2208 emit_opcode(cbuf, Assembler::REX_W);
2209 } else {
2210 emit_opcode(cbuf, Assembler::REX_WB);
2211 dstenc -= 8;
2212 }
2213 $$$emit8$primary;
2214 emit_rm(cbuf, 0x3, $secondary, dstenc);
2215 $$$emit8$shift$$constant;
2216 %}
2217
2218 enc_class load_immI(rRegI dst, immI src)
2219 %{
2220 int dstenc = $dst$$reg;
2221 if (dstenc >= 8) {
2222 emit_opcode(cbuf, Assembler::REX_B);
2223 dstenc -= 8;
2224 }
2225 emit_opcode(cbuf, 0xB8 | dstenc);
2226 $$$emit32$src$$constant;
2227 %}
2228
2229 enc_class load_immL(rRegL dst, immL src)
2230 %{
2231 int dstenc = $dst$$reg;
2232 if (dstenc < 8) {
2233 emit_opcode(cbuf, Assembler::REX_W);
2234 } else {
2235 emit_opcode(cbuf, Assembler::REX_WB);
2236 dstenc -= 8;
2237 }
2238 emit_opcode(cbuf, 0xB8 | dstenc);
2239 emit_d64(cbuf, $src$$constant);
2240 %}
2241
2242 enc_class load_immUL32(rRegL dst, immUL32 src)
2243 %{
2244 // same as load_immI, but this time we care about zeroes in the high word
2245 int dstenc = $dst$$reg;
2246 if (dstenc >= 8) {
2247 emit_opcode(cbuf, Assembler::REX_B);
2248 dstenc -= 8;
2249 }
2250 emit_opcode(cbuf, 0xB8 | dstenc);
2251 $$$emit32$src$$constant;
2252 %}
2253
2254 enc_class load_immL32(rRegL dst, immL32 src)
2255 %{
2256 int dstenc = $dst$$reg;
2257 if (dstenc < 8) {
2258 emit_opcode(cbuf, Assembler::REX_W);
2259 } else {
2260 emit_opcode(cbuf, Assembler::REX_WB);
2261 dstenc -= 8;
2262 }
2263 emit_opcode(cbuf, 0xC7);
2264 emit_rm(cbuf, 0x03, 0x00, dstenc);
2265 $$$emit32$src$$constant;
2266 %}
2267
2268 enc_class load_immP31(rRegP dst, immP32 src)
2269 %{
2270 // same as load_immI, but this time we care about zeroes in the high word
2271 int dstenc = $dst$$reg;
2272 if (dstenc >= 8) {
2273 emit_opcode(cbuf, Assembler::REX_B);
2274 dstenc -= 8;
2275 }
2276 emit_opcode(cbuf, 0xB8 | dstenc);
2277 $$$emit32$src$$constant;
2278 %}
2279
2280 enc_class load_immP(rRegP dst, immP src)
2281 %{
2282 int dstenc = $dst$$reg;
2283 if (dstenc < 8) {
2284 emit_opcode(cbuf, Assembler::REX_W);
2285 } else {
2286 emit_opcode(cbuf, Assembler::REX_WB);
2287 dstenc -= 8;
2288 }
2289 emit_opcode(cbuf, 0xB8 | dstenc);
2290 // This next line should be generated from ADLC
2291 if ($src->constant_reloc() != relocInfo::none) {
2292 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2293 } else {
2294 emit_d64(cbuf, $src$$constant);
2295 }
2296 %}
2297
2298 enc_class Con32(immI src)
2299 %{
2300 // Output immediate
2301 $$$emit32$src$$constant;
2302 %}
2303
2304 enc_class Con32F_as_bits(immF src)
2305 %{
2306 // Output Float immediate bits
2307 jfloat jf = $src$$constant;
2308 jint jf_as_bits = jint_cast(jf);
2309 emit_d32(cbuf, jf_as_bits);
2310 %}
2311
2312 enc_class Con16(immI src)
2313 %{
2314 // Output immediate
2315 $$$emit16$src$$constant;
2316 %}
2317
2318 // How is this different from Con32??? XXX
2319 enc_class Con_d32(immI src)
2320 %{
2321 emit_d32(cbuf,$src$$constant);
2322 %}
2323
2324 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2325 // Output immediate memory reference
2326 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2327 emit_d32(cbuf, 0x00);
2328 %}
2329
2330 enc_class lock_prefix()
2331 %{
2332 emit_opcode(cbuf, 0xF0); // lock
2333 %}
2334
2335 enc_class REX_mem(memory mem)
2336 %{
2337 if ($mem$$base >= 8) {
2338 if ($mem$$index < 8) {
2339 emit_opcode(cbuf, Assembler::REX_B);
2340 } else {
2341 emit_opcode(cbuf, Assembler::REX_XB);
2342 }
2343 } else {
2344 if ($mem$$index >= 8) {
2345 emit_opcode(cbuf, Assembler::REX_X);
2346 }
2347 }
2348 %}
2349
2350 enc_class REX_mem_wide(memory mem)
2351 %{
2352 if ($mem$$base >= 8) {
2353 if ($mem$$index < 8) {
2354 emit_opcode(cbuf, Assembler::REX_WB);
2355 } else {
2356 emit_opcode(cbuf, Assembler::REX_WXB);
2357 }
2358 } else {
2359 if ($mem$$index < 8) {
2360 emit_opcode(cbuf, Assembler::REX_W);
2361 } else {
2362 emit_opcode(cbuf, Assembler::REX_WX);
2363 }
2364 }
2365 %}
2366
2367 // for byte regs
2368 enc_class REX_breg(rRegI reg)
2369 %{
2370 if ($reg$$reg >= 4) {
2371 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2372 }
2373 %}
2374
2375 // for byte regs
2376 enc_class REX_reg_breg(rRegI dst, rRegI src)
2377 %{
2378 if ($dst$$reg < 8) {
2379 if ($src$$reg >= 4) {
2380 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2381 }
2382 } else {
2383 if ($src$$reg < 8) {
2384 emit_opcode(cbuf, Assembler::REX_R);
2385 } else {
2386 emit_opcode(cbuf, Assembler::REX_RB);
2387 }
2388 }
2389 %}
2390
2391 // for byte regs
2392 enc_class REX_breg_mem(rRegI reg, memory mem)
2393 %{
2394 if ($reg$$reg < 8) {
2395 if ($mem$$base < 8) {
2396 if ($mem$$index >= 8) {
2397 emit_opcode(cbuf, Assembler::REX_X);
2398 } else if ($reg$$reg >= 4) {
2399 emit_opcode(cbuf, Assembler::REX);
2400 }
2401 } else {
2402 if ($mem$$index < 8) {
2403 emit_opcode(cbuf, Assembler::REX_B);
2404 } else {
2405 emit_opcode(cbuf, Assembler::REX_XB);
2406 }
2407 }
2408 } else {
2409 if ($mem$$base < 8) {
2410 if ($mem$$index < 8) {
2411 emit_opcode(cbuf, Assembler::REX_R);
2412 } else {
2413 emit_opcode(cbuf, Assembler::REX_RX);
2414 }
2415 } else {
2416 if ($mem$$index < 8) {
2417 emit_opcode(cbuf, Assembler::REX_RB);
2418 } else {
2419 emit_opcode(cbuf, Assembler::REX_RXB);
2420 }
2421 }
2422 }
2423 %}
2424
2425 enc_class REX_reg(rRegI reg)
2426 %{
2427 if ($reg$$reg >= 8) {
2428 emit_opcode(cbuf, Assembler::REX_B);
2429 }
2430 %}
2431
2432 enc_class REX_reg_wide(rRegI reg)
2433 %{
2434 if ($reg$$reg < 8) {
2435 emit_opcode(cbuf, Assembler::REX_W);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_WB);
2438 }
2439 %}
2440
2441 enc_class REX_reg_reg(rRegI dst, rRegI src)
2442 %{
2443 if ($dst$$reg < 8) {
2444 if ($src$$reg >= 8) {
2445 emit_opcode(cbuf, Assembler::REX_B);
2446 }
2447 } else {
2448 if ($src$$reg < 8) {
2449 emit_opcode(cbuf, Assembler::REX_R);
2450 } else {
2451 emit_opcode(cbuf, Assembler::REX_RB);
2452 }
2453 }
2454 %}
2455
2456 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2457 %{
2458 if ($dst$$reg < 8) {
2459 if ($src$$reg < 8) {
2460 emit_opcode(cbuf, Assembler::REX_W);
2461 } else {
2462 emit_opcode(cbuf, Assembler::REX_WB);
2463 }
2464 } else {
2465 if ($src$$reg < 8) {
2466 emit_opcode(cbuf, Assembler::REX_WR);
2467 } else {
2468 emit_opcode(cbuf, Assembler::REX_WRB);
2469 }
2470 }
2471 %}
2472
2473 enc_class REX_reg_mem(rRegI reg, memory mem)
2474 %{
2475 if ($reg$$reg < 8) {
2476 if ($mem$$base < 8) {
2477 if ($mem$$index >= 8) {
2478 emit_opcode(cbuf, Assembler::REX_X);
2479 }
2480 } else {
2481 if ($mem$$index < 8) {
2482 emit_opcode(cbuf, Assembler::REX_B);
2483 } else {
2484 emit_opcode(cbuf, Assembler::REX_XB);
2485 }
2486 }
2487 } else {
2488 if ($mem$$base < 8) {
2489 if ($mem$$index < 8) {
2490 emit_opcode(cbuf, Assembler::REX_R);
2491 } else {
2492 emit_opcode(cbuf, Assembler::REX_RX);
2493 }
2494 } else {
2495 if ($mem$$index < 8) {
2496 emit_opcode(cbuf, Assembler::REX_RB);
2497 } else {
2498 emit_opcode(cbuf, Assembler::REX_RXB);
2499 }
2500 }
2501 }
2502 %}
2503
2504 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2505 %{
2506 if ($reg$$reg < 8) {
2507 if ($mem$$base < 8) {
2508 if ($mem$$index < 8) {
2509 emit_opcode(cbuf, Assembler::REX_W);
2510 } else {
2511 emit_opcode(cbuf, Assembler::REX_WX);
2512 }
2513 } else {
2514 if ($mem$$index < 8) {
2515 emit_opcode(cbuf, Assembler::REX_WB);
2516 } else {
2517 emit_opcode(cbuf, Assembler::REX_WXB);
2518 }
2519 }
2520 } else {
2521 if ($mem$$base < 8) {
2522 if ($mem$$index < 8) {
2523 emit_opcode(cbuf, Assembler::REX_WR);
2524 } else {
2525 emit_opcode(cbuf, Assembler::REX_WRX);
2526 }
2527 } else {
2528 if ($mem$$index < 8) {
2529 emit_opcode(cbuf, Assembler::REX_WRB);
2530 } else {
2531 emit_opcode(cbuf, Assembler::REX_WRXB);
2532 }
2533 }
2534 }
2535 %}
2536
2537 enc_class reg_mem(rRegI ereg, memory mem)
2538 %{
2539 // High registers handle in encode_RegMem
2540 int reg = $ereg$$reg;
2541 int base = $mem$$base;
2542 int index = $mem$$index;
2543 int scale = $mem$$scale;
2544 int disp = $mem$$disp;
2545 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2546
2547 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2548 %}
2549
2550 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2551 %{
2552 int rm_byte_opcode = $rm_opcode$$constant;
2553
2554 // High registers handle in encode_RegMem
2555 int base = $mem$$base;
2556 int index = $mem$$index;
2557 int scale = $mem$$scale;
2558 int displace = $mem$$disp;
2559
2560 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2561 // working with static
2562 // globals
2563 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2564 disp_reloc);
2565 %}
2566
2567 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2568 %{
2569 int reg_encoding = $dst$$reg;
2570 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2571 int index = 0x04; // 0x04 indicates no index
2572 int scale = 0x00; // 0x00 indicates no scale
2573 int displace = $src1$$constant; // 0x00 indicates no displacement
2574 relocInfo::relocType disp_reloc = relocInfo::none;
2575 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2576 disp_reloc);
2577 %}
2578
2579 enc_class neg_reg(rRegI dst)
2580 %{
2581 int dstenc = $dst$$reg;
2582 if (dstenc >= 8) {
2583 emit_opcode(cbuf, Assembler::REX_B);
2584 dstenc -= 8;
2585 }
2586 // NEG $dst
2587 emit_opcode(cbuf, 0xF7);
2588 emit_rm(cbuf, 0x3, 0x03, dstenc);
2589 %}
2590
2591 enc_class neg_reg_wide(rRegI dst)
2592 %{
2593 int dstenc = $dst$$reg;
2594 if (dstenc < 8) {
2595 emit_opcode(cbuf, Assembler::REX_W);
2596 } else {
2597 emit_opcode(cbuf, Assembler::REX_WB);
2598 dstenc -= 8;
2599 }
2600 // NEG $dst
2601 emit_opcode(cbuf, 0xF7);
2602 emit_rm(cbuf, 0x3, 0x03, dstenc);
2603 %}
2604
2605 enc_class setLT_reg(rRegI dst)
2606 %{
2607 int dstenc = $dst$$reg;
2608 if (dstenc >= 8) {
2609 emit_opcode(cbuf, Assembler::REX_B);
2610 dstenc -= 8;
2611 } else if (dstenc >= 4) {
2612 emit_opcode(cbuf, Assembler::REX);
2613 }
2614 // SETLT $dst
2615 emit_opcode(cbuf, 0x0F);
2616 emit_opcode(cbuf, 0x9C);
2617 emit_rm(cbuf, 0x3, 0x0, dstenc);
2618 %}
2619
2620 enc_class setNZ_reg(rRegI dst)
2621 %{
2622 int dstenc = $dst$$reg;
2623 if (dstenc >= 8) {
2624 emit_opcode(cbuf, Assembler::REX_B);
2625 dstenc -= 8;
2626 } else if (dstenc >= 4) {
2627 emit_opcode(cbuf, Assembler::REX);
2628 }
2629 // SETNZ $dst
2630 emit_opcode(cbuf, 0x0F);
2631 emit_opcode(cbuf, 0x95);
2632 emit_rm(cbuf, 0x3, 0x0, dstenc);
2633 %}
2634
2635
2636 // Compare the lonogs and set -1, 0, or 1 into dst
2637 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2638 %{
2639 int src1enc = $src1$$reg;
2640 int src2enc = $src2$$reg;
2641 int dstenc = $dst$$reg;
2642
2643 // cmpq $src1, $src2
2644 if (src1enc < 8) {
2645 if (src2enc < 8) {
2646 emit_opcode(cbuf, Assembler::REX_W);
2647 } else {
2648 emit_opcode(cbuf, Assembler::REX_WB);
2649 }
2650 } else {
2651 if (src2enc < 8) {
2652 emit_opcode(cbuf, Assembler::REX_WR);
2653 } else {
2654 emit_opcode(cbuf, Assembler::REX_WRB);
2655 }
2656 }
2657 emit_opcode(cbuf, 0x3B);
2658 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2659
2660 // movl $dst, -1
2661 if (dstenc >= 8) {
2662 emit_opcode(cbuf, Assembler::REX_B);
2663 }
2664 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2665 emit_d32(cbuf, -1);
2666
2667 // jl,s done
2668 emit_opcode(cbuf, 0x7C);
2669 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2670
2671 // setne $dst
2672 if (dstenc >= 4) {
2673 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2674 }
2675 emit_opcode(cbuf, 0x0F);
2676 emit_opcode(cbuf, 0x95);
2677 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2678
2679 // movzbl $dst, $dst
2680 if (dstenc >= 4) {
2681 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2682 }
2683 emit_opcode(cbuf, 0x0F);
2684 emit_opcode(cbuf, 0xB6);
2685 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2686 %}
2687
2688 enc_class Push_ResultXD(regD dst) %{
2689 MacroAssembler _masm(&cbuf);
2690 __ fstp_d(Address(rsp, 0));
2691 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2692 __ addptr(rsp, 8);
2693 %}
2694
2695 enc_class Push_SrcXD(regD src) %{
2696 MacroAssembler _masm(&cbuf);
2697 __ subptr(rsp, 8);
2698 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2699 __ fld_d(Address(rsp, 0));
2700 %}
2701
2702
2703 enc_class enc_rethrow()
2704 %{
2705 cbuf.set_insts_mark();
2706 emit_opcode(cbuf, 0xE9); // jmp entry
2707 emit_d32_reloc(cbuf,
2708 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2709 runtime_call_Relocation::spec(),
2710 RELOC_DISP32);
2711 %}
2712
2713 %}
2714
2715
2716
2717 //----------FRAME--------------------------------------------------------------
2718 // Definition of frame structure and management information.
2719 //
2720 // S T A C K L A Y O U T Allocators stack-slot number
2721 // | (to get allocators register number
2722 // G Owned by | | v add OptoReg::stack0())
2723 // r CALLER | |
2724 // o | +--------+ pad to even-align allocators stack-slot
2725 // w V | pad0 | numbers; owned by CALLER
2726 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2727 // h ^ | in | 5
2728 // | | args | 4 Holes in incoming args owned by SELF
2729 // | | | | 3
2730 // | | +--------+
2731 // V | | old out| Empty on Intel, window on Sparc
2732 // | old |preserve| Must be even aligned.
2733 // | SP-+--------+----> Matcher::_old_SP, even aligned
2734 // | | in | 3 area for Intel ret address
2735 // Owned by |preserve| Empty on Sparc.
2736 // SELF +--------+
2737 // | | pad2 | 2 pad to align old SP
2738 // | +--------+ 1
2739 // | | locks | 0
2740 // | +--------+----> OptoReg::stack0(), even aligned
2741 // | | pad1 | 11 pad to align new SP
2742 // | +--------+
2743 // | | | 10
2744 // | | spills | 9 spills
2745 // V | | 8 (pad0 slot for callee)
2746 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2747 // ^ | out | 7
2748 // | | args | 6 Holes in outgoing args owned by CALLEE
2749 // Owned by +--------+
2750 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2751 // | new |preserve| Must be even-aligned.
2752 // | SP-+--------+----> Matcher::_new_SP, even aligned
2753 // | | |
2754 //
2755 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2756 // known from SELF's arguments and the Java calling convention.
2757 // Region 6-7 is determined per call site.
2758 // Note 2: If the calling convention leaves holes in the incoming argument
2759 // area, those holes are owned by SELF. Holes in the outgoing area
2760 // are owned by the CALLEE. Holes should not be nessecary in the
2761 // incoming area, as the Java calling convention is completely under
2762 // the control of the AD file. Doubles can be sorted and packed to
2763 // avoid holes. Holes in the outgoing arguments may be nessecary for
2764 // varargs C calling conventions.
2765 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2766 // even aligned with pad0 as needed.
2767 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2768 // region 6-11 is even aligned; it may be padded out more so that
2769 // the region from SP to FP meets the minimum stack alignment.
2770 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2771 // alignment. Region 11, pad1, may be dynamically extended so that
2772 // SP meets the minimum alignment.
2773
2774 frame
2775 %{
2776 // What direction does stack grow in (assumed to be same for C & Java)
2777 stack_direction(TOWARDS_LOW);
2778
2779 // These three registers define part of the calling convention
2780 // between compiled code and the interpreter.
2781 inline_cache_reg(RAX); // Inline Cache Register
2782 interpreter_method_oop_reg(RBX); // Method Oop Register when
2783 // calling interpreter
2784
2785 // Optional: name the operand used by cisc-spilling to access
2786 // [stack_pointer + offset]
2787 cisc_spilling_operand_name(indOffset32);
2788
2789 // Number of stack slots consumed by locking an object
2790 sync_stack_slots(2);
2791
2792 // Compiled code's Frame Pointer
2793 frame_pointer(RSP);
2794
2795 // Interpreter stores its frame pointer in a register which is
2796 // stored to the stack by I2CAdaptors.
2797 // I2CAdaptors convert from interpreted java to compiled java.
2798 interpreter_frame_pointer(RBP);
2799
2800 // Stack alignment requirement
2801 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2802
2803 // Number of stack slots between incoming argument block and the start of
2804 // a new frame. The PROLOG must add this many slots to the stack. The
2805 // EPILOG must remove this many slots. amd64 needs two slots for
2806 // return address.
2807 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2808
2809 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2810 // for calls to C. Supports the var-args backing area for register parms.
2811 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2812
2813 // The after-PROLOG location of the return address. Location of
2814 // return address specifies a type (REG or STACK) and a number
2815 // representing the register number (i.e. - use a register name) or
2816 // stack slot.
2817 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2818 // Otherwise, it is above the locks and verification slot and alignment word
2819 return_addr(STACK - 2 +
2820 align_up((Compile::current()->in_preserve_stack_slots() +
2821 Compile::current()->fixed_slots()),
2822 stack_alignment_in_slots()));
2823
2824 // Body of function which returns an integer array locating
2825 // arguments either in registers or in stack slots. Passed an array
2826 // of ideal registers called "sig" and a "length" count. Stack-slot
2827 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2828 // arguments for a CALLEE. Incoming stack arguments are
2829 // automatically biased by the preserve_stack_slots field above.
2830
2831 calling_convention
2832 %{
2833 // No difference between ingoing/outgoing just pass false
2834 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2835 %}
2836
2837 c_calling_convention
2838 %{
2839 // This is obviously always outgoing
2840 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2841 %}
2842
2843 // Location of compiled Java return values. Same as C for now.
2844 return_value
2845 %{
2846 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2847 "only return normal values");
2848
2849 static const int lo[Op_RegL + 1] = {
2850 0,
2851 0,
2852 RAX_num, // Op_RegN
2853 RAX_num, // Op_RegI
2854 RAX_num, // Op_RegP
2855 XMM0_num, // Op_RegF
2856 XMM0_num, // Op_RegD
2857 RAX_num // Op_RegL
2858 };
2859 static const int hi[Op_RegL + 1] = {
2860 0,
2861 0,
2862 OptoReg::Bad, // Op_RegN
2863 OptoReg::Bad, // Op_RegI
2864 RAX_H_num, // Op_RegP
2865 OptoReg::Bad, // Op_RegF
2866 XMM0b_num, // Op_RegD
2867 RAX_H_num // Op_RegL
2868 };
2869 // Excluded flags and vector registers.
2870 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2871 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2872 %}
2873 %}
2874
2875 //----------ATTRIBUTES---------------------------------------------------------
2876 //----------Operand Attributes-------------------------------------------------
2877 op_attrib op_cost(0); // Required cost attribute
2878
2879 //----------Instruction Attributes---------------------------------------------
2880 ins_attrib ins_cost(100); // Required cost attribute
2881 ins_attrib ins_size(8); // Required size attribute (in bits)
2882 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2883 // a non-matching short branch variant
2884 // of some long branch?
2885 ins_attrib ins_alignment(1); // Required alignment attribute (must
2886 // be a power of 2) specifies the
2887 // alignment that some part of the
2888 // instruction (not necessarily the
2889 // start) requires. If > 1, a
2890 // compute_padding() function must be
2891 // provided for the instruction
2892
2893 //----------OPERANDS-----------------------------------------------------------
2894 // Operand definitions must precede instruction definitions for correct parsing
2895 // in the ADLC because operands constitute user defined types which are used in
2896 // instruction definitions.
2897
2898 //----------Simple Operands----------------------------------------------------
2899 // Immediate Operands
2900 // Integer Immediate
2901 operand immI()
2902 %{
2903 match(ConI);
2904
2905 op_cost(10);
2906 format %{ %}
2907 interface(CONST_INTER);
2908 %}
2909
2910 // Constant for test vs zero
2911 operand immI0()
2912 %{
2913 predicate(n->get_int() == 0);
2914 match(ConI);
2915
2916 op_cost(0);
2917 format %{ %}
2918 interface(CONST_INTER);
2919 %}
2920
2921 // Constant for increment
2922 operand immI1()
2923 %{
2924 predicate(n->get_int() == 1);
2925 match(ConI);
2926
2927 op_cost(0);
2928 format %{ %}
2929 interface(CONST_INTER);
2930 %}
2931
2932 // Constant for decrement
2933 operand immI_M1()
2934 %{
2935 predicate(n->get_int() == -1);
2936 match(ConI);
2937
2938 op_cost(0);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 // Valid scale values for addressing modes
2944 operand immI2()
2945 %{
2946 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2947 match(ConI);
2948
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 operand immI8()
2954 %{
2955 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2956 match(ConI);
2957
2958 op_cost(5);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 operand immU8()
2964 %{
2965 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2966 match(ConI);
2967
2968 op_cost(5);
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immI16()
2974 %{
2975 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2976 match(ConI);
2977
2978 op_cost(10);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 // Int Immediate non-negative
2984 operand immU31()
2985 %{
2986 predicate(n->get_int() >= 0);
2987 match(ConI);
2988
2989 op_cost(0);
2990 format %{ %}
2991 interface(CONST_INTER);
2992 %}
2993
2994 // Constant for long shifts
2995 operand immI_32()
2996 %{
2997 predicate( n->get_int() == 32 );
2998 match(ConI);
2999
3000 op_cost(0);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Constant for long shifts
3006 operand immI_64()
3007 %{
3008 predicate( n->get_int() == 64 );
3009 match(ConI);
3010
3011 op_cost(0);
3012 format %{ %}
3013 interface(CONST_INTER);
3014 %}
3015
3016 // Pointer Immediate
3017 operand immP()
3018 %{
3019 match(ConP);
3020
3021 op_cost(10);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // NULL Pointer Immediate
3027 operand immP0()
3028 %{
3029 predicate(n->get_ptr() == 0);
3030 match(ConP);
3031
3032 op_cost(5);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Pointer Immediate
3038 operand immN() %{
3039 match(ConN);
3040
3041 op_cost(10);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 operand immNKlass() %{
3047 match(ConNKlass);
3048
3049 op_cost(10);
3050 format %{ %}
3051 interface(CONST_INTER);
3052 %}
3053
3054 // NULL Pointer Immediate
3055 operand immN0() %{
3056 predicate(n->get_narrowcon() == 0);
3057 match(ConN);
3058
3059 op_cost(5);
3060 format %{ %}
3061 interface(CONST_INTER);
3062 %}
3063
3064 operand immP31()
3065 %{
3066 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3067 && (n->get_ptr() >> 31) == 0);
3068 match(ConP);
3069
3070 op_cost(5);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075
3076 // Long Immediate
3077 operand immL()
3078 %{
3079 match(ConL);
3080
3081 op_cost(20);
3082 format %{ %}
3083 interface(CONST_INTER);
3084 %}
3085
3086 // Long Immediate 8-bit
3087 operand immL8()
3088 %{
3089 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3090 match(ConL);
3091
3092 op_cost(5);
3093 format %{ %}
3094 interface(CONST_INTER);
3095 %}
3096
3097 // Long Immediate 32-bit unsigned
3098 operand immUL32()
3099 %{
3100 predicate(n->get_long() == (unsigned int) (n->get_long()));
3101 match(ConL);
3102
3103 op_cost(10);
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3107
3108 // Long Immediate 32-bit signed
3109 operand immL32()
3110 %{
3111 predicate(n->get_long() == (int) (n->get_long()));
3112 match(ConL);
3113
3114 op_cost(15);
3115 format %{ %}
3116 interface(CONST_INTER);
3117 %}
3118
3119 // Long Immediate zero
3120 operand immL0()
3121 %{
3122 predicate(n->get_long() == 0L);
3123 match(ConL);
3124
3125 op_cost(10);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3129
3130 // Constant for increment
3131 operand immL1()
3132 %{
3133 predicate(n->get_long() == 1);
3134 match(ConL);
3135
3136 format %{ %}
3137 interface(CONST_INTER);
3138 %}
3139
3140 // Constant for decrement
3141 operand immL_M1()
3142 %{
3143 predicate(n->get_long() == -1);
3144 match(ConL);
3145
3146 format %{ %}
3147 interface(CONST_INTER);
3148 %}
3149
3150 // Long Immediate: the value 10
3151 operand immL10()
3152 %{
3153 predicate(n->get_long() == 10);
3154 match(ConL);
3155
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // Long immediate from 0 to 127.
3161 // Used for a shorter form of long mul by 10.
3162 operand immL_127()
3163 %{
3164 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3165 match(ConL);
3166
3167 op_cost(10);
3168 format %{ %}
3169 interface(CONST_INTER);
3170 %}
3171
3172 // Long Immediate: low 32-bit mask
3173 operand immL_32bits()
3174 %{
3175 predicate(n->get_long() == 0xFFFFFFFFL);
3176 match(ConL);
3177 op_cost(20);
3178
3179 format %{ %}
3180 interface(CONST_INTER);
3181 %}
3182
3183 // Float Immediate zero
3184 operand immF0()
3185 %{
3186 predicate(jint_cast(n->getf()) == 0);
3187 match(ConF);
3188
3189 op_cost(5);
3190 format %{ %}
3191 interface(CONST_INTER);
3192 %}
3193
3194 // Float Immediate
3195 operand immF()
3196 %{
3197 match(ConF);
3198
3199 op_cost(15);
3200 format %{ %}
3201 interface(CONST_INTER);
3202 %}
3203
3204 // Double Immediate zero
3205 operand immD0()
3206 %{
3207 predicate(jlong_cast(n->getd()) == 0);
3208 match(ConD);
3209
3210 op_cost(5);
3211 format %{ %}
3212 interface(CONST_INTER);
3213 %}
3214
3215 // Double Immediate
3216 operand immD()
3217 %{
3218 match(ConD);
3219
3220 op_cost(15);
3221 format %{ %}
3222 interface(CONST_INTER);
3223 %}
3224
3225 // Immediates for special shifts (sign extend)
3226
3227 // Constants for increment
3228 operand immI_16()
3229 %{
3230 predicate(n->get_int() == 16);
3231 match(ConI);
3232
3233 format %{ %}
3234 interface(CONST_INTER);
3235 %}
3236
3237 operand immI_24()
3238 %{
3239 predicate(n->get_int() == 24);
3240 match(ConI);
3241
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3245
3246 // Constant for byte-wide masking
3247 operand immI_255()
3248 %{
3249 predicate(n->get_int() == 255);
3250 match(ConI);
3251
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3255
3256 // Constant for short-wide masking
3257 operand immI_65535()
3258 %{
3259 predicate(n->get_int() == 65535);
3260 match(ConI);
3261
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Constant for byte-wide masking
3267 operand immL_255()
3268 %{
3269 predicate(n->get_long() == 255);
3270 match(ConL);
3271
3272 format %{ %}
3273 interface(CONST_INTER);
3274 %}
3275
3276 // Constant for short-wide masking
3277 operand immL_65535()
3278 %{
3279 predicate(n->get_long() == 65535);
3280 match(ConL);
3281
3282 format %{ %}
3283 interface(CONST_INTER);
3284 %}
3285
3286 // Register Operands
3287 // Integer Register
3288 operand rRegI()
3289 %{
3290 constraint(ALLOC_IN_RC(int_reg));
3291 match(RegI);
3292
3293 match(rax_RegI);
3294 match(rbx_RegI);
3295 match(rcx_RegI);
3296 match(rdx_RegI);
3297 match(rdi_RegI);
3298
3299 format %{ %}
3300 interface(REG_INTER);
3301 %}
3302
3303 // Special Registers
3304 operand rax_RegI()
3305 %{
3306 constraint(ALLOC_IN_RC(int_rax_reg));
3307 match(RegI);
3308 match(rRegI);
3309
3310 format %{ "RAX" %}
3311 interface(REG_INTER);
3312 %}
3313
3314 // Special Registers
3315 operand rbx_RegI()
3316 %{
3317 constraint(ALLOC_IN_RC(int_rbx_reg));
3318 match(RegI);
3319 match(rRegI);
3320
3321 format %{ "RBX" %}
3322 interface(REG_INTER);
3323 %}
3324
3325 operand rcx_RegI()
3326 %{
3327 constraint(ALLOC_IN_RC(int_rcx_reg));
3328 match(RegI);
3329 match(rRegI);
3330
3331 format %{ "RCX" %}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand rdx_RegI()
3336 %{
3337 constraint(ALLOC_IN_RC(int_rdx_reg));
3338 match(RegI);
3339 match(rRegI);
3340
3341 format %{ "RDX" %}
3342 interface(REG_INTER);
3343 %}
3344
3345 operand rdi_RegI()
3346 %{
3347 constraint(ALLOC_IN_RC(int_rdi_reg));
3348 match(RegI);
3349 match(rRegI);
3350
3351 format %{ "RDI" %}
3352 interface(REG_INTER);
3353 %}
3354
3355 operand no_rcx_RegI()
3356 %{
3357 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3358 match(RegI);
3359 match(rax_RegI);
3360 match(rbx_RegI);
3361 match(rdx_RegI);
3362 match(rdi_RegI);
3363
3364 format %{ %}
3365 interface(REG_INTER);
3366 %}
3367
3368 operand no_rax_rdx_RegI()
3369 %{
3370 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3371 match(RegI);
3372 match(rbx_RegI);
3373 match(rcx_RegI);
3374 match(rdi_RegI);
3375
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 // Pointer Register
3381 operand any_RegP()
3382 %{
3383 constraint(ALLOC_IN_RC(any_reg));
3384 match(RegP);
3385 match(rax_RegP);
3386 match(rbx_RegP);
3387 match(rdi_RegP);
3388 match(rsi_RegP);
3389 match(rbp_RegP);
3390 match(r15_RegP);
3391 match(rRegP);
3392
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand rRegP()
3398 %{
3399 constraint(ALLOC_IN_RC(ptr_reg));
3400 match(RegP);
3401 match(rax_RegP);
3402 match(rbx_RegP);
3403 match(rdi_RegP);
3404 match(rsi_RegP);
3405 match(rbp_RegP); // See Q&A below about
3406 match(r15_RegP); // r15_RegP and rbp_RegP.
3407
3408 format %{ %}
3409 interface(REG_INTER);
3410 %}
3411
3412 operand rRegN() %{
3413 constraint(ALLOC_IN_RC(int_reg));
3414 match(RegN);
3415
3416 format %{ %}
3417 interface(REG_INTER);
3418 %}
3419
3420 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3421 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3422 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3423 // The output of an instruction is controlled by the allocator, which respects
3424 // register class masks, not match rules. Unless an instruction mentions
3425 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3426 // by the allocator as an input.
3427 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3428 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3429 // result, RBP is not included in the output of the instruction either.
3430
3431 operand no_rax_RegP()
3432 %{
3433 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3434 match(RegP);
3435 match(rbx_RegP);
3436 match(rsi_RegP);
3437 match(rdi_RegP);
3438
3439 format %{ %}
3440 interface(REG_INTER);
3441 %}
3442
3443 // This operand is not allowed to use RBP even if
3444 // RBP is not used to hold the frame pointer.
3445 operand no_rbp_RegP()
3446 %{
3447 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3448 match(RegP);
3449 match(rbx_RegP);
3450 match(rsi_RegP);
3451 match(rdi_RegP);
3452
3453 format %{ %}
3454 interface(REG_INTER);
3455 %}
3456
3457 operand no_rax_rbx_RegP()
3458 %{
3459 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3460 match(RegP);
3461 match(rsi_RegP);
3462 match(rdi_RegP);
3463
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 // Special Registers
3469 // Return a pointer value
3470 operand rax_RegP()
3471 %{
3472 constraint(ALLOC_IN_RC(ptr_rax_reg));
3473 match(RegP);
3474 match(rRegP);
3475
3476 format %{ %}
3477 interface(REG_INTER);
3478 %}
3479
3480 // Special Registers
3481 // Return a compressed pointer value
3482 operand rax_RegN()
3483 %{
3484 constraint(ALLOC_IN_RC(int_rax_reg));
3485 match(RegN);
3486 match(rRegN);
3487
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 // Used in AtomicAdd
3493 operand rbx_RegP()
3494 %{
3495 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3496 match(RegP);
3497 match(rRegP);
3498
3499 format %{ %}
3500 interface(REG_INTER);
3501 %}
3502
3503 operand rsi_RegP()
3504 %{
3505 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3506 match(RegP);
3507 match(rRegP);
3508
3509 format %{ %}
3510 interface(REG_INTER);
3511 %}
3512
3513 // Used in rep stosq
3514 operand rdi_RegP()
3515 %{
3516 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3517 match(RegP);
3518 match(rRegP);
3519
3520 format %{ %}
3521 interface(REG_INTER);
3522 %}
3523
3524 operand r15_RegP()
3525 %{
3526 constraint(ALLOC_IN_RC(ptr_r15_reg));
3527 match(RegP);
3528 match(rRegP);
3529
3530 format %{ %}
3531 interface(REG_INTER);
3532 %}
3533
3534 operand rRegL()
3535 %{
3536 constraint(ALLOC_IN_RC(long_reg));
3537 match(RegL);
3538 match(rax_RegL);
3539 match(rdx_RegL);
3540
3541 format %{ %}
3542 interface(REG_INTER);
3543 %}
3544
3545 // Special Registers
3546 operand no_rax_rdx_RegL()
3547 %{
3548 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3549 match(RegL);
3550 match(rRegL);
3551
3552 format %{ %}
3553 interface(REG_INTER);
3554 %}
3555
3556 operand no_rax_RegL()
3557 %{
3558 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3559 match(RegL);
3560 match(rRegL);
3561 match(rdx_RegL);
3562
3563 format %{ %}
3564 interface(REG_INTER);
3565 %}
3566
3567 operand no_rcx_RegL()
3568 %{
3569 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3570 match(RegL);
3571 match(rRegL);
3572
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 operand rax_RegL()
3578 %{
3579 constraint(ALLOC_IN_RC(long_rax_reg));
3580 match(RegL);
3581 match(rRegL);
3582
3583 format %{ "RAX" %}
3584 interface(REG_INTER);
3585 %}
3586
3587 operand rcx_RegL()
3588 %{
3589 constraint(ALLOC_IN_RC(long_rcx_reg));
3590 match(RegL);
3591 match(rRegL);
3592
3593 format %{ %}
3594 interface(REG_INTER);
3595 %}
3596
3597 operand rdx_RegL()
3598 %{
3599 constraint(ALLOC_IN_RC(long_rdx_reg));
3600 match(RegL);
3601 match(rRegL);
3602
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3606
3607 // Flags register, used as output of compare instructions
3608 operand rFlagsReg()
3609 %{
3610 constraint(ALLOC_IN_RC(int_flags));
3611 match(RegFlags);
3612
3613 format %{ "RFLAGS" %}
3614 interface(REG_INTER);
3615 %}
3616
3617 // Flags register, used as output of FLOATING POINT compare instructions
3618 operand rFlagsRegU()
3619 %{
3620 constraint(ALLOC_IN_RC(int_flags));
3621 match(RegFlags);
3622
3623 format %{ "RFLAGS_U" %}
3624 interface(REG_INTER);
3625 %}
3626
3627 operand rFlagsRegUCF() %{
3628 constraint(ALLOC_IN_RC(int_flags));
3629 match(RegFlags);
3630 predicate(false);
3631
3632 format %{ "RFLAGS_U_CF" %}
3633 interface(REG_INTER);
3634 %}
3635
3636 // Float register operands
3637 operand regF() %{
3638 constraint(ALLOC_IN_RC(float_reg));
3639 match(RegF);
3640
3641 format %{ %}
3642 interface(REG_INTER);
3643 %}
3644
3645 // Float register operands
3646 operand legRegF() %{
3647 constraint(ALLOC_IN_RC(float_reg_legacy));
3648 match(RegF);
3649
3650 format %{ %}
3651 interface(REG_INTER);
3652 %}
3653
3654 // Float register operands
3655 operand vlRegF() %{
3656 constraint(ALLOC_IN_RC(float_reg_vl));
3657 match(RegF);
3658
3659 format %{ %}
3660 interface(REG_INTER);
3661 %}
3662
3663 // Double register operands
3664 operand regD() %{
3665 constraint(ALLOC_IN_RC(double_reg));
3666 match(RegD);
3667
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3671
3672 // Double register operands
3673 operand legRegD() %{
3674 constraint(ALLOC_IN_RC(double_reg_legacy));
3675 match(RegD);
3676
3677 format %{ %}
3678 interface(REG_INTER);
3679 %}
3680
3681 // Double register operands
3682 operand vlRegD() %{
3683 constraint(ALLOC_IN_RC(double_reg_vl));
3684 match(RegD);
3685
3686 format %{ %}
3687 interface(REG_INTER);
3688 %}
3689
3690 // Vectors
3691 operand vecS() %{
3692 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3693 match(VecS);
3694
3695 format %{ %}
3696 interface(REG_INTER);
3697 %}
3698
3699 // Vectors
3700 operand legVecS() %{
3701 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3702 match(VecS);
3703
3704 format %{ %}
3705 interface(REG_INTER);
3706 %}
3707
3708 operand vecD() %{
3709 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3710 match(VecD);
3711
3712 format %{ %}
3713 interface(REG_INTER);
3714 %}
3715
3716 operand legVecD() %{
3717 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3718 match(VecD);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand vecX() %{
3725 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3726 match(VecX);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand legVecX() %{
3733 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3734 match(VecX);
3735
3736 format %{ %}
3737 interface(REG_INTER);
3738 %}
3739
3740 operand vecY() %{
3741 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3742 match(VecY);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 operand legVecY() %{
3749 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3750 match(VecY);
3751
3752 format %{ %}
3753 interface(REG_INTER);
3754 %}
3755
3756 //----------Memory Operands----------------------------------------------------
3757 // Direct Memory Operand
3758 // operand direct(immP addr)
3759 // %{
3760 // match(addr);
3761
3762 // format %{ "[$addr]" %}
3763 // interface(MEMORY_INTER) %{
3764 // base(0xFFFFFFFF);
3765 // index(0x4);
3766 // scale(0x0);
3767 // disp($addr);
3768 // %}
3769 // %}
3770
3771 // Indirect Memory Operand
3772 operand indirect(any_RegP reg)
3773 %{
3774 constraint(ALLOC_IN_RC(ptr_reg));
3775 match(reg);
3776
3777 format %{ "[$reg]" %}
3778 interface(MEMORY_INTER) %{
3779 base($reg);
3780 index(0x4);
3781 scale(0x0);
3782 disp(0x0);
3783 %}
3784 %}
3785
3786 // Indirect Memory Plus Short Offset Operand
3787 operand indOffset8(any_RegP reg, immL8 off)
3788 %{
3789 constraint(ALLOC_IN_RC(ptr_reg));
3790 match(AddP reg off);
3791
3792 format %{ "[$reg + $off (8-bit)]" %}
3793 interface(MEMORY_INTER) %{
3794 base($reg);
3795 index(0x4);
3796 scale(0x0);
3797 disp($off);
3798 %}
3799 %}
3800
3801 // Indirect Memory Plus Long Offset Operand
3802 operand indOffset32(any_RegP reg, immL32 off)
3803 %{
3804 constraint(ALLOC_IN_RC(ptr_reg));
3805 match(AddP reg off);
3806
3807 format %{ "[$reg + $off (32-bit)]" %}
3808 interface(MEMORY_INTER) %{
3809 base($reg);
3810 index(0x4);
3811 scale(0x0);
3812 disp($off);
3813 %}
3814 %}
3815
3816 // Indirect Memory Plus Index Register Plus Offset Operand
3817 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3818 %{
3819 constraint(ALLOC_IN_RC(ptr_reg));
3820 match(AddP (AddP reg lreg) off);
3821
3822 op_cost(10);
3823 format %{"[$reg + $off + $lreg]" %}
3824 interface(MEMORY_INTER) %{
3825 base($reg);
3826 index($lreg);
3827 scale(0x0);
3828 disp($off);
3829 %}
3830 %}
3831
3832 // Indirect Memory Plus Index Register Plus Offset Operand
3833 operand indIndex(any_RegP reg, rRegL lreg)
3834 %{
3835 constraint(ALLOC_IN_RC(ptr_reg));
3836 match(AddP reg lreg);
3837
3838 op_cost(10);
3839 format %{"[$reg + $lreg]" %}
3840 interface(MEMORY_INTER) %{
3841 base($reg);
3842 index($lreg);
3843 scale(0x0);
3844 disp(0x0);
3845 %}
3846 %}
3847
3848 // Indirect Memory Times Scale Plus Index Register
3849 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3850 %{
3851 constraint(ALLOC_IN_RC(ptr_reg));
3852 match(AddP reg (LShiftL lreg scale));
3853
3854 op_cost(10);
3855 format %{"[$reg + $lreg << $scale]" %}
3856 interface(MEMORY_INTER) %{
3857 base($reg);
3858 index($lreg);
3859 scale($scale);
3860 disp(0x0);
3861 %}
3862 %}
3863
3864 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3865 %{
3866 constraint(ALLOC_IN_RC(ptr_reg));
3867 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3868 match(AddP reg (LShiftL (ConvI2L idx) scale));
3869
3870 op_cost(10);
3871 format %{"[$reg + pos $idx << $scale]" %}
3872 interface(MEMORY_INTER) %{
3873 base($reg);
3874 index($idx);
3875 scale($scale);
3876 disp(0x0);
3877 %}
3878 %}
3879
3880 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3881 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3882 %{
3883 constraint(ALLOC_IN_RC(ptr_reg));
3884 match(AddP (AddP reg (LShiftL lreg scale)) off);
3885
3886 op_cost(10);
3887 format %{"[$reg + $off + $lreg << $scale]" %}
3888 interface(MEMORY_INTER) %{
3889 base($reg);
3890 index($lreg);
3891 scale($scale);
3892 disp($off);
3893 %}
3894 %}
3895
3896 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3897 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3898 %{
3899 constraint(ALLOC_IN_RC(ptr_reg));
3900 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3901 match(AddP (AddP reg (ConvI2L idx)) off);
3902
3903 op_cost(10);
3904 format %{"[$reg + $off + $idx]" %}
3905 interface(MEMORY_INTER) %{
3906 base($reg);
3907 index($idx);
3908 scale(0x0);
3909 disp($off);
3910 %}
3911 %}
3912
3913 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3914 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3915 %{
3916 constraint(ALLOC_IN_RC(ptr_reg));
3917 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3918 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3919
3920 op_cost(10);
3921 format %{"[$reg + $off + $idx << $scale]" %}
3922 interface(MEMORY_INTER) %{
3923 base($reg);
3924 index($idx);
3925 scale($scale);
3926 disp($off);
3927 %}
3928 %}
3929
3930 // Indirect Narrow Oop Plus Offset Operand
3931 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3932 // we can't free r12 even with CompressedOops::base() == NULL.
3933 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3934 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3935 constraint(ALLOC_IN_RC(ptr_reg));
3936 match(AddP (DecodeN reg) off);
3937
3938 op_cost(10);
3939 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3940 interface(MEMORY_INTER) %{
3941 base(0xc); // R12
3942 index($reg);
3943 scale(0x3);
3944 disp($off);
3945 %}
3946 %}
3947
3948 // Indirect Memory Operand
3949 operand indirectNarrow(rRegN reg)
3950 %{
3951 predicate(CompressedOops::shift() == 0);
3952 constraint(ALLOC_IN_RC(ptr_reg));
3953 match(DecodeN reg);
3954
3955 format %{ "[$reg]" %}
3956 interface(MEMORY_INTER) %{
3957 base($reg);
3958 index(0x4);
3959 scale(0x0);
3960 disp(0x0);
3961 %}
3962 %}
3963
3964 // Indirect Memory Plus Short Offset Operand
3965 operand indOffset8Narrow(rRegN reg, immL8 off)
3966 %{
3967 predicate(CompressedOops::shift() == 0);
3968 constraint(ALLOC_IN_RC(ptr_reg));
3969 match(AddP (DecodeN reg) off);
3970
3971 format %{ "[$reg + $off (8-bit)]" %}
3972 interface(MEMORY_INTER) %{
3973 base($reg);
3974 index(0x4);
3975 scale(0x0);
3976 disp($off);
3977 %}
3978 %}
3979
3980 // Indirect Memory Plus Long Offset Operand
3981 operand indOffset32Narrow(rRegN reg, immL32 off)
3982 %{
3983 predicate(CompressedOops::shift() == 0);
3984 constraint(ALLOC_IN_RC(ptr_reg));
3985 match(AddP (DecodeN reg) off);
3986
3987 format %{ "[$reg + $off (32-bit)]" %}
3988 interface(MEMORY_INTER) %{
3989 base($reg);
3990 index(0x4);
3991 scale(0x0);
3992 disp($off);
3993 %}
3994 %}
3995
3996 // Indirect Memory Plus Index Register Plus Offset Operand
3997 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3998 %{
3999 predicate(CompressedOops::shift() == 0);
4000 constraint(ALLOC_IN_RC(ptr_reg));
4001 match(AddP (AddP (DecodeN reg) lreg) off);
4002
4003 op_cost(10);
4004 format %{"[$reg + $off + $lreg]" %}
4005 interface(MEMORY_INTER) %{
4006 base($reg);
4007 index($lreg);
4008 scale(0x0);
4009 disp($off);
4010 %}
4011 %}
4012
4013 // Indirect Memory Plus Index Register Plus Offset Operand
4014 operand indIndexNarrow(rRegN reg, rRegL lreg)
4015 %{
4016 predicate(CompressedOops::shift() == 0);
4017 constraint(ALLOC_IN_RC(ptr_reg));
4018 match(AddP (DecodeN reg) lreg);
4019
4020 op_cost(10);
4021 format %{"[$reg + $lreg]" %}
4022 interface(MEMORY_INTER) %{
4023 base($reg);
4024 index($lreg);
4025 scale(0x0);
4026 disp(0x0);
4027 %}
4028 %}
4029
4030 // Indirect Memory Times Scale Plus Index Register
4031 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4032 %{
4033 predicate(CompressedOops::shift() == 0);
4034 constraint(ALLOC_IN_RC(ptr_reg));
4035 match(AddP (DecodeN reg) (LShiftL lreg scale));
4036
4037 op_cost(10);
4038 format %{"[$reg + $lreg << $scale]" %}
4039 interface(MEMORY_INTER) %{
4040 base($reg);
4041 index($lreg);
4042 scale($scale);
4043 disp(0x0);
4044 %}
4045 %}
4046
4047 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4048 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4049 %{
4050 predicate(CompressedOops::shift() == 0);
4051 constraint(ALLOC_IN_RC(ptr_reg));
4052 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4053
4054 op_cost(10);
4055 format %{"[$reg + $off + $lreg << $scale]" %}
4056 interface(MEMORY_INTER) %{
4057 base($reg);
4058 index($lreg);
4059 scale($scale);
4060 disp($off);
4061 %}
4062 %}
4063
4064 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4065 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4066 %{
4067 constraint(ALLOC_IN_RC(ptr_reg));
4068 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4069 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4070
4071 op_cost(10);
4072 format %{"[$reg + $off + $idx]" %}
4073 interface(MEMORY_INTER) %{
4074 base($reg);
4075 index($idx);
4076 scale(0x0);
4077 disp($off);
4078 %}
4079 %}
4080
4081 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4082 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4083 %{
4084 constraint(ALLOC_IN_RC(ptr_reg));
4085 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4086 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4087
4088 op_cost(10);
4089 format %{"[$reg + $off + $idx << $scale]" %}
4090 interface(MEMORY_INTER) %{
4091 base($reg);
4092 index($idx);
4093 scale($scale);
4094 disp($off);
4095 %}
4096 %}
4097
4098 //----------Special Memory Operands--------------------------------------------
4099 // Stack Slot Operand - This operand is used for loading and storing temporary
4100 // values on the stack where a match requires a value to
4101 // flow through memory.
4102 operand stackSlotP(sRegP reg)
4103 %{
4104 constraint(ALLOC_IN_RC(stack_slots));
4105 // No match rule because this operand is only generated in matching
4106
4107 format %{ "[$reg]" %}
4108 interface(MEMORY_INTER) %{
4109 base(0x4); // RSP
4110 index(0x4); // No Index
4111 scale(0x0); // No Scale
4112 disp($reg); // Stack Offset
4113 %}
4114 %}
4115
4116 operand stackSlotI(sRegI reg)
4117 %{
4118 constraint(ALLOC_IN_RC(stack_slots));
4119 // No match rule because this operand is only generated in matching
4120
4121 format %{ "[$reg]" %}
4122 interface(MEMORY_INTER) %{
4123 base(0x4); // RSP
4124 index(0x4); // No Index
4125 scale(0x0); // No Scale
4126 disp($reg); // Stack Offset
4127 %}
4128 %}
4129
4130 operand stackSlotF(sRegF reg)
4131 %{
4132 constraint(ALLOC_IN_RC(stack_slots));
4133 // No match rule because this operand is only generated in matching
4134
4135 format %{ "[$reg]" %}
4136 interface(MEMORY_INTER) %{
4137 base(0x4); // RSP
4138 index(0x4); // No Index
4139 scale(0x0); // No Scale
4140 disp($reg); // Stack Offset
4141 %}
4142 %}
4143
4144 operand stackSlotD(sRegD reg)
4145 %{
4146 constraint(ALLOC_IN_RC(stack_slots));
4147 // No match rule because this operand is only generated in matching
4148
4149 format %{ "[$reg]" %}
4150 interface(MEMORY_INTER) %{
4151 base(0x4); // RSP
4152 index(0x4); // No Index
4153 scale(0x0); // No Scale
4154 disp($reg); // Stack Offset
4155 %}
4156 %}
4157 operand stackSlotL(sRegL reg)
4158 %{
4159 constraint(ALLOC_IN_RC(stack_slots));
4160 // No match rule because this operand is only generated in matching
4161
4162 format %{ "[$reg]" %}
4163 interface(MEMORY_INTER) %{
4164 base(0x4); // RSP
4165 index(0x4); // No Index
4166 scale(0x0); // No Scale
4167 disp($reg); // Stack Offset
4168 %}
4169 %}
4170
4171 //----------Conditional Branch Operands----------------------------------------
4172 // Comparison Op - This is the operation of the comparison, and is limited to
4173 // the following set of codes:
4174 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4175 //
4176 // Other attributes of the comparison, such as unsignedness, are specified
4177 // by the comparison instruction that sets a condition code flags register.
4178 // That result is represented by a flags operand whose subtype is appropriate
4179 // to the unsignedness (etc.) of the comparison.
4180 //
4181 // Later, the instruction which matches both the Comparison Op (a Bool) and
4182 // the flags (produced by the Cmp) specifies the coding of the comparison op
4183 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4184
4185 // Comparision Code
4186 operand cmpOp()
4187 %{
4188 match(Bool);
4189
4190 format %{ "" %}
4191 interface(COND_INTER) %{
4192 equal(0x4, "e");
4193 not_equal(0x5, "ne");
4194 less(0xC, "l");
4195 greater_equal(0xD, "ge");
4196 less_equal(0xE, "le");
4197 greater(0xF, "g");
4198 overflow(0x0, "o");
4199 no_overflow(0x1, "no");
4200 %}
4201 %}
4202
4203 // Comparison Code, unsigned compare. Used by FP also, with
4204 // C2 (unordered) turned into GT or LT already. The other bits
4205 // C0 and C3 are turned into Carry & Zero flags.
4206 operand cmpOpU()
4207 %{
4208 match(Bool);
4209
4210 format %{ "" %}
4211 interface(COND_INTER) %{
4212 equal(0x4, "e");
4213 not_equal(0x5, "ne");
4214 less(0x2, "b");
4215 greater_equal(0x3, "nb");
4216 less_equal(0x6, "be");
4217 greater(0x7, "nbe");
4218 overflow(0x0, "o");
4219 no_overflow(0x1, "no");
4220 %}
4221 %}
4222
4223
4224 // Floating comparisons that don't require any fixup for the unordered case
4225 operand cmpOpUCF() %{
4226 match(Bool);
4227 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4228 n->as_Bool()->_test._test == BoolTest::ge ||
4229 n->as_Bool()->_test._test == BoolTest::le ||
4230 n->as_Bool()->_test._test == BoolTest::gt);
4231 format %{ "" %}
4232 interface(COND_INTER) %{
4233 equal(0x4, "e");
4234 not_equal(0x5, "ne");
4235 less(0x2, "b");
4236 greater_equal(0x3, "nb");
4237 less_equal(0x6, "be");
4238 greater(0x7, "nbe");
4239 overflow(0x0, "o");
4240 no_overflow(0x1, "no");
4241 %}
4242 %}
4243
4244
4245 // Floating comparisons that can be fixed up with extra conditional jumps
4246 operand cmpOpUCF2() %{
4247 match(Bool);
4248 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4249 n->as_Bool()->_test._test == BoolTest::eq);
4250 format %{ "" %}
4251 interface(COND_INTER) %{
4252 equal(0x4, "e");
4253 not_equal(0x5, "ne");
4254 less(0x2, "b");
4255 greater_equal(0x3, "nb");
4256 less_equal(0x6, "be");
4257 greater(0x7, "nbe");
4258 overflow(0x0, "o");
4259 no_overflow(0x1, "no");
4260 %}
4261 %}
4262
4263 //----------OPERAND CLASSES----------------------------------------------------
4264 // Operand Classes are groups of operands that are used as to simplify
4265 // instruction definitions by not requiring the AD writer to specify separate
4266 // instructions for every form of operand when the instruction accepts
4267 // multiple operand types with the same basic encoding and format. The classic
4268 // case of this is memory operands.
4269
4270 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4271 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4272 indCompressedOopOffset,
4273 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4274 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4275 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4276
4277 //----------PIPELINE-----------------------------------------------------------
4278 // Rules which define the behavior of the target architectures pipeline.
4279 pipeline %{
4280
4281 //----------ATTRIBUTES---------------------------------------------------------
4282 attributes %{
4283 variable_size_instructions; // Fixed size instructions
4284 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4285 instruction_unit_size = 1; // An instruction is 1 bytes long
4286 instruction_fetch_unit_size = 16; // The processor fetches one line
4287 instruction_fetch_units = 1; // of 16 bytes
4288
4289 // List of nop instructions
4290 nops( MachNop );
4291 %}
4292
4293 //----------RESOURCES----------------------------------------------------------
4294 // Resources are the functional units available to the machine
4295
4296 // Generic P2/P3 pipeline
4297 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4298 // 3 instructions decoded per cycle.
4299 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4300 // 3 ALU op, only ALU0 handles mul instructions.
4301 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4302 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4303 BR, FPU,
4304 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4305
4306 //----------PIPELINE DESCRIPTION-----------------------------------------------
4307 // Pipeline Description specifies the stages in the machine's pipeline
4308
4309 // Generic P2/P3 pipeline
4310 pipe_desc(S0, S1, S2, S3, S4, S5);
4311
4312 //----------PIPELINE CLASSES---------------------------------------------------
4313 // Pipeline Classes describe the stages in which input and output are
4314 // referenced by the hardware pipeline.
4315
4316 // Naming convention: ialu or fpu
4317 // Then: _reg
4318 // Then: _reg if there is a 2nd register
4319 // Then: _long if it's a pair of instructions implementing a long
4320 // Then: _fat if it requires the big decoder
4321 // Or: _mem if it requires the big decoder and a memory unit.
4322
4323 // Integer ALU reg operation
4324 pipe_class ialu_reg(rRegI dst)
4325 %{
4326 single_instruction;
4327 dst : S4(write);
4328 dst : S3(read);
4329 DECODE : S0; // any decoder
4330 ALU : S3; // any alu
4331 %}
4332
4333 // Long ALU reg operation
4334 pipe_class ialu_reg_long(rRegL dst)
4335 %{
4336 instruction_count(2);
4337 dst : S4(write);
4338 dst : S3(read);
4339 DECODE : S0(2); // any 2 decoders
4340 ALU : S3(2); // both alus
4341 %}
4342
4343 // Integer ALU reg operation using big decoder
4344 pipe_class ialu_reg_fat(rRegI dst)
4345 %{
4346 single_instruction;
4347 dst : S4(write);
4348 dst : S3(read);
4349 D0 : S0; // big decoder only
4350 ALU : S3; // any alu
4351 %}
4352
4353 // Long ALU reg operation using big decoder
4354 pipe_class ialu_reg_long_fat(rRegL dst)
4355 %{
4356 instruction_count(2);
4357 dst : S4(write);
4358 dst : S3(read);
4359 D0 : S0(2); // big decoder only; twice
4360 ALU : S3(2); // any 2 alus
4361 %}
4362
4363 // Integer ALU reg-reg operation
4364 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4365 %{
4366 single_instruction;
4367 dst : S4(write);
4368 src : S3(read);
4369 DECODE : S0; // any decoder
4370 ALU : S3; // any alu
4371 %}
4372
4373 // Long ALU reg-reg operation
4374 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4375 %{
4376 instruction_count(2);
4377 dst : S4(write);
4378 src : S3(read);
4379 DECODE : S0(2); // any 2 decoders
4380 ALU : S3(2); // both alus
4381 %}
4382
4383 // Integer ALU reg-reg operation
4384 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4385 %{
4386 single_instruction;
4387 dst : S4(write);
4388 src : S3(read);
4389 D0 : S0; // big decoder only
4390 ALU : S3; // any alu
4391 %}
4392
4393 // Long ALU reg-reg operation
4394 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4395 %{
4396 instruction_count(2);
4397 dst : S4(write);
4398 src : S3(read);
4399 D0 : S0(2); // big decoder only; twice
4400 ALU : S3(2); // both alus
4401 %}
4402
4403 // Integer ALU reg-mem operation
4404 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4405 %{
4406 single_instruction;
4407 dst : S5(write);
4408 mem : S3(read);
4409 D0 : S0; // big decoder only
4410 ALU : S4; // any alu
4411 MEM : S3; // any mem
4412 %}
4413
4414 // Integer mem operation (prefetch)
4415 pipe_class ialu_mem(memory mem)
4416 %{
4417 single_instruction;
4418 mem : S3(read);
4419 D0 : S0; // big decoder only
4420 MEM : S3; // any mem
4421 %}
4422
4423 // Integer Store to Memory
4424 pipe_class ialu_mem_reg(memory mem, rRegI src)
4425 %{
4426 single_instruction;
4427 mem : S3(read);
4428 src : S5(read);
4429 D0 : S0; // big decoder only
4430 ALU : S4; // any alu
4431 MEM : S3;
4432 %}
4433
4434 // // Long Store to Memory
4435 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4436 // %{
4437 // instruction_count(2);
4438 // mem : S3(read);
4439 // src : S5(read);
4440 // D0 : S0(2); // big decoder only; twice
4441 // ALU : S4(2); // any 2 alus
4442 // MEM : S3(2); // Both mems
4443 // %}
4444
4445 // Integer Store to Memory
4446 pipe_class ialu_mem_imm(memory mem)
4447 %{
4448 single_instruction;
4449 mem : S3(read);
4450 D0 : S0; // big decoder only
4451 ALU : S4; // any alu
4452 MEM : S3;
4453 %}
4454
4455 // Integer ALU0 reg-reg operation
4456 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4457 %{
4458 single_instruction;
4459 dst : S4(write);
4460 src : S3(read);
4461 D0 : S0; // Big decoder only
4462 ALU0 : S3; // only alu0
4463 %}
4464
4465 // Integer ALU0 reg-mem operation
4466 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4467 %{
4468 single_instruction;
4469 dst : S5(write);
4470 mem : S3(read);
4471 D0 : S0; // big decoder only
4472 ALU0 : S4; // ALU0 only
4473 MEM : S3; // any mem
4474 %}
4475
4476 // Integer ALU reg-reg operation
4477 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4478 %{
4479 single_instruction;
4480 cr : S4(write);
4481 src1 : S3(read);
4482 src2 : S3(read);
4483 DECODE : S0; // any decoder
4484 ALU : S3; // any alu
4485 %}
4486
4487 // Integer ALU reg-imm operation
4488 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4489 %{
4490 single_instruction;
4491 cr : S4(write);
4492 src1 : S3(read);
4493 DECODE : S0; // any decoder
4494 ALU : S3; // any alu
4495 %}
4496
4497 // Integer ALU reg-mem operation
4498 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4499 %{
4500 single_instruction;
4501 cr : S4(write);
4502 src1 : S3(read);
4503 src2 : S3(read);
4504 D0 : S0; // big decoder only
4505 ALU : S4; // any alu
4506 MEM : S3;
4507 %}
4508
4509 // Conditional move reg-reg
4510 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4511 %{
4512 instruction_count(4);
4513 y : S4(read);
4514 q : S3(read);
4515 p : S3(read);
4516 DECODE : S0(4); // any decoder
4517 %}
4518
4519 // Conditional move reg-reg
4520 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4521 %{
4522 single_instruction;
4523 dst : S4(write);
4524 src : S3(read);
4525 cr : S3(read);
4526 DECODE : S0; // any decoder
4527 %}
4528
4529 // Conditional move reg-mem
4530 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4531 %{
4532 single_instruction;
4533 dst : S4(write);
4534 src : S3(read);
4535 cr : S3(read);
4536 DECODE : S0; // any decoder
4537 MEM : S3;
4538 %}
4539
4540 // Conditional move reg-reg long
4541 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4542 %{
4543 single_instruction;
4544 dst : S4(write);
4545 src : S3(read);
4546 cr : S3(read);
4547 DECODE : S0(2); // any 2 decoders
4548 %}
4549
4550 // XXX
4551 // // Conditional move double reg-reg
4552 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4553 // %{
4554 // single_instruction;
4555 // dst : S4(write);
4556 // src : S3(read);
4557 // cr : S3(read);
4558 // DECODE : S0; // any decoder
4559 // %}
4560
4561 // Float reg-reg operation
4562 pipe_class fpu_reg(regD dst)
4563 %{
4564 instruction_count(2);
4565 dst : S3(read);
4566 DECODE : S0(2); // any 2 decoders
4567 FPU : S3;
4568 %}
4569
4570 // Float reg-reg operation
4571 pipe_class fpu_reg_reg(regD dst, regD src)
4572 %{
4573 instruction_count(2);
4574 dst : S4(write);
4575 src : S3(read);
4576 DECODE : S0(2); // any 2 decoders
4577 FPU : S3;
4578 %}
4579
4580 // Float reg-reg operation
4581 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4582 %{
4583 instruction_count(3);
4584 dst : S4(write);
4585 src1 : S3(read);
4586 src2 : S3(read);
4587 DECODE : S0(3); // any 3 decoders
4588 FPU : S3(2);
4589 %}
4590
4591 // Float reg-reg operation
4592 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4593 %{
4594 instruction_count(4);
4595 dst : S4(write);
4596 src1 : S3(read);
4597 src2 : S3(read);
4598 src3 : S3(read);
4599 DECODE : S0(4); // any 3 decoders
4600 FPU : S3(2);
4601 %}
4602
4603 // Float reg-reg operation
4604 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4605 %{
4606 instruction_count(4);
4607 dst : S4(write);
4608 src1 : S3(read);
4609 src2 : S3(read);
4610 src3 : S3(read);
4611 DECODE : S1(3); // any 3 decoders
4612 D0 : S0; // Big decoder only
4613 FPU : S3(2);
4614 MEM : S3;
4615 %}
4616
4617 // Float reg-mem operation
4618 pipe_class fpu_reg_mem(regD dst, memory mem)
4619 %{
4620 instruction_count(2);
4621 dst : S5(write);
4622 mem : S3(read);
4623 D0 : S0; // big decoder only
4624 DECODE : S1; // any decoder for FPU POP
4625 FPU : S4;
4626 MEM : S3; // any mem
4627 %}
4628
4629 // Float reg-mem operation
4630 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4631 %{
4632 instruction_count(3);
4633 dst : S5(write);
4634 src1 : S3(read);
4635 mem : S3(read);
4636 D0 : S0; // big decoder only
4637 DECODE : S1(2); // any decoder for FPU POP
4638 FPU : S4;
4639 MEM : S3; // any mem
4640 %}
4641
4642 // Float mem-reg operation
4643 pipe_class fpu_mem_reg(memory mem, regD src)
4644 %{
4645 instruction_count(2);
4646 src : S5(read);
4647 mem : S3(read);
4648 DECODE : S0; // any decoder for FPU PUSH
4649 D0 : S1; // big decoder only
4650 FPU : S4;
4651 MEM : S3; // any mem
4652 %}
4653
4654 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4655 %{
4656 instruction_count(3);
4657 src1 : S3(read);
4658 src2 : S3(read);
4659 mem : S3(read);
4660 DECODE : S0(2); // any decoder for FPU PUSH
4661 D0 : S1; // big decoder only
4662 FPU : S4;
4663 MEM : S3; // any mem
4664 %}
4665
4666 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4667 %{
4668 instruction_count(3);
4669 src1 : S3(read);
4670 src2 : S3(read);
4671 mem : S4(read);
4672 DECODE : S0; // any decoder for FPU PUSH
4673 D0 : S0(2); // big decoder only
4674 FPU : S4;
4675 MEM : S3(2); // any mem
4676 %}
4677
4678 pipe_class fpu_mem_mem(memory dst, memory src1)
4679 %{
4680 instruction_count(2);
4681 src1 : S3(read);
4682 dst : S4(read);
4683 D0 : S0(2); // big decoder only
4684 MEM : S3(2); // any mem
4685 %}
4686
4687 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4688 %{
4689 instruction_count(3);
4690 src1 : S3(read);
4691 src2 : S3(read);
4692 dst : S4(read);
4693 D0 : S0(3); // big decoder only
4694 FPU : S4;
4695 MEM : S3(3); // any mem
4696 %}
4697
4698 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4699 %{
4700 instruction_count(3);
4701 src1 : S4(read);
4702 mem : S4(read);
4703 DECODE : S0; // any decoder for FPU PUSH
4704 D0 : S0(2); // big decoder only
4705 FPU : S4;
4706 MEM : S3(2); // any mem
4707 %}
4708
4709 // Float load constant
4710 pipe_class fpu_reg_con(regD dst)
4711 %{
4712 instruction_count(2);
4713 dst : S5(write);
4714 D0 : S0; // big decoder only for the load
4715 DECODE : S1; // any decoder for FPU POP
4716 FPU : S4;
4717 MEM : S3; // any mem
4718 %}
4719
4720 // Float load constant
4721 pipe_class fpu_reg_reg_con(regD dst, regD src)
4722 %{
4723 instruction_count(3);
4724 dst : S5(write);
4725 src : S3(read);
4726 D0 : S0; // big decoder only for the load
4727 DECODE : S1(2); // any decoder for FPU POP
4728 FPU : S4;
4729 MEM : S3; // any mem
4730 %}
4731
4732 // UnConditional branch
4733 pipe_class pipe_jmp(label labl)
4734 %{
4735 single_instruction;
4736 BR : S3;
4737 %}
4738
4739 // Conditional branch
4740 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4741 %{
4742 single_instruction;
4743 cr : S1(read);
4744 BR : S3;
4745 %}
4746
4747 // Allocation idiom
4748 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4749 %{
4750 instruction_count(1); force_serialization;
4751 fixed_latency(6);
4752 heap_ptr : S3(read);
4753 DECODE : S0(3);
4754 D0 : S2;
4755 MEM : S3;
4756 ALU : S3(2);
4757 dst : S5(write);
4758 BR : S5;
4759 %}
4760
4761 // Generic big/slow expanded idiom
4762 pipe_class pipe_slow()
4763 %{
4764 instruction_count(10); multiple_bundles; force_serialization;
4765 fixed_latency(100);
4766 D0 : S0(2);
4767 MEM : S3(2);
4768 %}
4769
4770 // The real do-nothing guy
4771 pipe_class empty()
4772 %{
4773 instruction_count(0);
4774 %}
4775
4776 // Define the class for the Nop node
4777 define
4778 %{
4779 MachNop = empty;
4780 %}
4781
4782 %}
4783
4784 //----------INSTRUCTIONS-------------------------------------------------------
4785 //
4786 // match -- States which machine-independent subtree may be replaced
4787 // by this instruction.
4788 // ins_cost -- The estimated cost of this instruction is used by instruction
4789 // selection to identify a minimum cost tree of machine
4790 // instructions that matches a tree of machine-independent
4791 // instructions.
4792 // format -- A string providing the disassembly for this instruction.
4793 // The value of an instruction's operand may be inserted
4794 // by referring to it with a '$' prefix.
4795 // opcode -- Three instruction opcodes may be provided. These are referred
4796 // to within an encode class as $primary, $secondary, and $tertiary
4797 // rrspectively. The primary opcode is commonly used to
4798 // indicate the type of machine instruction, while secondary
4799 // and tertiary are often used for prefix options or addressing
4800 // modes.
4801 // ins_encode -- A list of encode classes with parameters. The encode class
4802 // name must have been defined in an 'enc_class' specification
4803 // in the encode section of the architecture description.
4804
4805
4806 //----------Load/Store/Move Instructions---------------------------------------
4807 //----------Load Instructions--------------------------------------------------
4808
4809 // Load Byte (8 bit signed)
4810 instruct loadB(rRegI dst, memory mem)
4811 %{
4812 match(Set dst (LoadB mem));
4813
4814 ins_cost(125);
4815 format %{ "movsbl $dst, $mem\t# byte" %}
4816
4817 ins_encode %{
4818 __ movsbl($dst$$Register, $mem$$Address);
4819 %}
4820
4821 ins_pipe(ialu_reg_mem);
4822 %}
4823
4824 // Load Byte (8 bit signed) into Long Register
4825 instruct loadB2L(rRegL dst, memory mem)
4826 %{
4827 match(Set dst (ConvI2L (LoadB mem)));
4828
4829 ins_cost(125);
4830 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4831
4832 ins_encode %{
4833 __ movsbq($dst$$Register, $mem$$Address);
4834 %}
4835
4836 ins_pipe(ialu_reg_mem);
4837 %}
4838
4839 // Load Unsigned Byte (8 bit UNsigned)
4840 instruct loadUB(rRegI dst, memory mem)
4841 %{
4842 match(Set dst (LoadUB mem));
4843
4844 ins_cost(125);
4845 format %{ "movzbl $dst, $mem\t# ubyte" %}
4846
4847 ins_encode %{
4848 __ movzbl($dst$$Register, $mem$$Address);
4849 %}
4850
4851 ins_pipe(ialu_reg_mem);
4852 %}
4853
4854 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4855 instruct loadUB2L(rRegL dst, memory mem)
4856 %{
4857 match(Set dst (ConvI2L (LoadUB mem)));
4858
4859 ins_cost(125);
4860 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4861
4862 ins_encode %{
4863 __ movzbq($dst$$Register, $mem$$Address);
4864 %}
4865
4866 ins_pipe(ialu_reg_mem);
4867 %}
4868
4869 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4870 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4871 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4872 effect(KILL cr);
4873
4874 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4875 "andl $dst, right_n_bits($mask, 8)" %}
4876 ins_encode %{
4877 Register Rdst = $dst$$Register;
4878 __ movzbq(Rdst, $mem$$Address);
4879 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4880 %}
4881 ins_pipe(ialu_reg_mem);
4882 %}
4883
4884 // Load Short (16 bit signed)
4885 instruct loadS(rRegI dst, memory mem)
4886 %{
4887 match(Set dst (LoadS mem));
4888
4889 ins_cost(125);
4890 format %{ "movswl $dst, $mem\t# short" %}
4891
4892 ins_encode %{
4893 __ movswl($dst$$Register, $mem$$Address);
4894 %}
4895
4896 ins_pipe(ialu_reg_mem);
4897 %}
4898
4899 // Load Short (16 bit signed) to Byte (8 bit signed)
4900 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4901 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4902
4903 ins_cost(125);
4904 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4905 ins_encode %{
4906 __ movsbl($dst$$Register, $mem$$Address);
4907 %}
4908 ins_pipe(ialu_reg_mem);
4909 %}
4910
4911 // Load Short (16 bit signed) into Long Register
4912 instruct loadS2L(rRegL dst, memory mem)
4913 %{
4914 match(Set dst (ConvI2L (LoadS mem)));
4915
4916 ins_cost(125);
4917 format %{ "movswq $dst, $mem\t# short -> long" %}
4918
4919 ins_encode %{
4920 __ movswq($dst$$Register, $mem$$Address);
4921 %}
4922
4923 ins_pipe(ialu_reg_mem);
4924 %}
4925
4926 // Load Unsigned Short/Char (16 bit UNsigned)
4927 instruct loadUS(rRegI dst, memory mem)
4928 %{
4929 match(Set dst (LoadUS mem));
4930
4931 ins_cost(125);
4932 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4933
4934 ins_encode %{
4935 __ movzwl($dst$$Register, $mem$$Address);
4936 %}
4937
4938 ins_pipe(ialu_reg_mem);
4939 %}
4940
4941 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4942 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4943 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4944
4945 ins_cost(125);
4946 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4947 ins_encode %{
4948 __ movsbl($dst$$Register, $mem$$Address);
4949 %}
4950 ins_pipe(ialu_reg_mem);
4951 %}
4952
4953 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4954 instruct loadUS2L(rRegL dst, memory mem)
4955 %{
4956 match(Set dst (ConvI2L (LoadUS mem)));
4957
4958 ins_cost(125);
4959 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4960
4961 ins_encode %{
4962 __ movzwq($dst$$Register, $mem$$Address);
4963 %}
4964
4965 ins_pipe(ialu_reg_mem);
4966 %}
4967
4968 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4969 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4970 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4971
4972 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4973 ins_encode %{
4974 __ movzbq($dst$$Register, $mem$$Address);
4975 %}
4976 ins_pipe(ialu_reg_mem);
4977 %}
4978
4979 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4980 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4981 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4982 effect(KILL cr);
4983
4984 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4985 "andl $dst, right_n_bits($mask, 16)" %}
4986 ins_encode %{
4987 Register Rdst = $dst$$Register;
4988 __ movzwq(Rdst, $mem$$Address);
4989 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4990 %}
4991 ins_pipe(ialu_reg_mem);
4992 %}
4993
4994 // Load Integer
4995 instruct loadI(rRegI dst, memory mem)
4996 %{
4997 match(Set dst (LoadI mem));
4998
4999 ins_cost(125);
5000 format %{ "movl $dst, $mem\t# int" %}
5001
5002 ins_encode %{
5003 __ movl($dst$$Register, $mem$$Address);
5004 %}
5005
5006 ins_pipe(ialu_reg_mem);
5007 %}
5008
5009 // Load Integer (32 bit signed) to Byte (8 bit signed)
5010 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5011 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5012
5013 ins_cost(125);
5014 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5015 ins_encode %{
5016 __ movsbl($dst$$Register, $mem$$Address);
5017 %}
5018 ins_pipe(ialu_reg_mem);
5019 %}
5020
5021 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5022 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5023 match(Set dst (AndI (LoadI mem) mask));
5024
5025 ins_cost(125);
5026 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5027 ins_encode %{
5028 __ movzbl($dst$$Register, $mem$$Address);
5029 %}
5030 ins_pipe(ialu_reg_mem);
5031 %}
5032
5033 // Load Integer (32 bit signed) to Short (16 bit signed)
5034 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5035 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5036
5037 ins_cost(125);
5038 format %{ "movswl $dst, $mem\t# int -> short" %}
5039 ins_encode %{
5040 __ movswl($dst$$Register, $mem$$Address);
5041 %}
5042 ins_pipe(ialu_reg_mem);
5043 %}
5044
5045 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5046 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5047 match(Set dst (AndI (LoadI mem) mask));
5048
5049 ins_cost(125);
5050 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5051 ins_encode %{
5052 __ movzwl($dst$$Register, $mem$$Address);
5053 %}
5054 ins_pipe(ialu_reg_mem);
5055 %}
5056
5057 // Load Integer into Long Register
5058 instruct loadI2L(rRegL dst, memory mem)
5059 %{
5060 match(Set dst (ConvI2L (LoadI mem)));
5061
5062 ins_cost(125);
5063 format %{ "movslq $dst, $mem\t# int -> long" %}
5064
5065 ins_encode %{
5066 __ movslq($dst$$Register, $mem$$Address);
5067 %}
5068
5069 ins_pipe(ialu_reg_mem);
5070 %}
5071
5072 // Load Integer with mask 0xFF into Long Register
5073 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5074 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5075
5076 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5077 ins_encode %{
5078 __ movzbq($dst$$Register, $mem$$Address);
5079 %}
5080 ins_pipe(ialu_reg_mem);
5081 %}
5082
5083 // Load Integer with mask 0xFFFF into Long Register
5084 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5085 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5086
5087 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5088 ins_encode %{
5089 __ movzwq($dst$$Register, $mem$$Address);
5090 %}
5091 ins_pipe(ialu_reg_mem);
5092 %}
5093
5094 // Load Integer with a 31-bit mask into Long Register
5095 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5096 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5097 effect(KILL cr);
5098
5099 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5100 "andl $dst, $mask" %}
5101 ins_encode %{
5102 Register Rdst = $dst$$Register;
5103 __ movl(Rdst, $mem$$Address);
5104 __ andl(Rdst, $mask$$constant);
5105 %}
5106 ins_pipe(ialu_reg_mem);
5107 %}
5108
5109 // Load Unsigned Integer into Long Register
5110 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5111 %{
5112 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5113
5114 ins_cost(125);
5115 format %{ "movl $dst, $mem\t# uint -> long" %}
5116
5117 ins_encode %{
5118 __ movl($dst$$Register, $mem$$Address);
5119 %}
5120
5121 ins_pipe(ialu_reg_mem);
5122 %}
5123
5124 // Load Long
5125 instruct loadL(rRegL dst, memory mem)
5126 %{
5127 match(Set dst (LoadL mem));
5128
5129 ins_cost(125);
5130 format %{ "movq $dst, $mem\t# long" %}
5131
5132 ins_encode %{
5133 __ movq($dst$$Register, $mem$$Address);
5134 %}
5135
5136 ins_pipe(ialu_reg_mem); // XXX
5137 %}
5138
5139 // Load Range
5140 instruct loadRange(rRegI dst, memory mem)
5141 %{
5142 match(Set dst (LoadRange mem));
5143
5144 ins_cost(125); // XXX
5145 format %{ "movl $dst, $mem\t# range" %}
5146 opcode(0x8B);
5147 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5148 ins_pipe(ialu_reg_mem);
5149 %}
5150
5151 // Load Pointer
5152 instruct loadP(rRegP dst, memory mem)
5153 %{
5154 match(Set dst (LoadP mem));
5155 predicate(n->as_Load()->barrier_data() == 0);
5156
5157 ins_cost(125); // XXX
5158 format %{ "movq $dst, $mem\t# ptr" %}
5159 opcode(0x8B);
5160 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5161 ins_pipe(ialu_reg_mem); // XXX
5162 %}
5163
5164 // Load Compressed Pointer
5165 instruct loadN(rRegN dst, memory mem)
5166 %{
5167 match(Set dst (LoadN mem));
5168
5169 ins_cost(125); // XXX
5170 format %{ "movl $dst, $mem\t# compressed ptr" %}
5171 ins_encode %{
5172 __ movl($dst$$Register, $mem$$Address);
5173 %}
5174 ins_pipe(ialu_reg_mem); // XXX
5175 %}
5176
5177
5178 // Load Klass Pointer
5179 instruct loadKlass(rRegP dst, memory mem)
5180 %{
5181 match(Set dst (LoadKlass mem));
5182
5183 ins_cost(125); // XXX
5184 format %{ "movq $dst, $mem\t# class" %}
5185 opcode(0x8B);
5186 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5187 ins_pipe(ialu_reg_mem); // XXX
5188 %}
5189
5190 // Load narrow Klass Pointer
5191 instruct loadNKlass(rRegN dst, memory mem)
5192 %{
5193 match(Set dst (LoadNKlass mem));
5194
5195 ins_cost(125); // XXX
5196 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5197 ins_encode %{
5198 __ movl($dst$$Register, $mem$$Address);
5199 %}
5200 ins_pipe(ialu_reg_mem); // XXX
5201 %}
5202
5203 // Load Float
5204 instruct loadF(regF dst, memory mem)
5205 %{
5206 match(Set dst (LoadF mem));
5207
5208 ins_cost(145); // XXX
5209 format %{ "movss $dst, $mem\t# float" %}
5210 ins_encode %{
5211 __ movflt($dst$$XMMRegister, $mem$$Address);
5212 %}
5213 ins_pipe(pipe_slow); // XXX
5214 %}
5215
5216 // Load Float
5217 instruct MoveF2VL(vlRegF dst, regF src) %{
5218 match(Set dst src);
5219 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5220 ins_encode %{
5221 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5222 %}
5223 ins_pipe( fpu_reg_reg );
5224 %}
5225
5226 // Load Float
5227 instruct MoveF2LEG(legRegF dst, regF src) %{
5228 match(Set dst src);
5229 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5230 ins_encode %{
5231 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5232 %}
5233 ins_pipe( fpu_reg_reg );
5234 %}
5235
5236 // Load Float
5237 instruct MoveVL2F(regF dst, vlRegF src) %{
5238 match(Set dst src);
5239 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5240 ins_encode %{
5241 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5242 %}
5243 ins_pipe( fpu_reg_reg );
5244 %}
5245
5246 // Load Float
5247 instruct MoveLEG2F(regF dst, legRegF src) %{
5248 match(Set dst src);
5249 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5250 ins_encode %{
5251 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5252 %}
5253 ins_pipe( fpu_reg_reg );
5254 %}
5255
5256 // Load Double
5257 instruct loadD_partial(regD dst, memory mem)
5258 %{
5259 predicate(!UseXmmLoadAndClearUpper);
5260 match(Set dst (LoadD mem));
5261
5262 ins_cost(145); // XXX
5263 format %{ "movlpd $dst, $mem\t# double" %}
5264 ins_encode %{
5265 __ movdbl($dst$$XMMRegister, $mem$$Address);
5266 %}
5267 ins_pipe(pipe_slow); // XXX
5268 %}
5269
5270 instruct loadD(regD dst, memory mem)
5271 %{
5272 predicate(UseXmmLoadAndClearUpper);
5273 match(Set dst (LoadD mem));
5274
5275 ins_cost(145); // XXX
5276 format %{ "movsd $dst, $mem\t# double" %}
5277 ins_encode %{
5278 __ movdbl($dst$$XMMRegister, $mem$$Address);
5279 %}
5280 ins_pipe(pipe_slow); // XXX
5281 %}
5282
5283 // Load Double
5284 instruct MoveD2VL(vlRegD dst, regD src) %{
5285 match(Set dst src);
5286 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5287 ins_encode %{
5288 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5289 %}
5290 ins_pipe( fpu_reg_reg );
5291 %}
5292
5293 // Load Double
5294 instruct MoveD2LEG(legRegD dst, regD src) %{
5295 match(Set dst src);
5296 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5297 ins_encode %{
5298 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5299 %}
5300 ins_pipe( fpu_reg_reg );
5301 %}
5302
5303 // Load Double
5304 instruct MoveVL2D(regD dst, vlRegD src) %{
5305 match(Set dst src);
5306 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5307 ins_encode %{
5308 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5309 %}
5310 ins_pipe( fpu_reg_reg );
5311 %}
5312
5313 // Load Double
5314 instruct MoveLEG2D(regD dst, legRegD src) %{
5315 match(Set dst src);
5316 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5317 ins_encode %{
5318 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5319 %}
5320 ins_pipe( fpu_reg_reg );
5321 %}
5322
5323 // Following pseudo code describes the algorithm for max[FD]:
5324 // Min algorithm is on similar lines
5325 // btmp = (b < +0.0) ? a : b
5326 // atmp = (b < +0.0) ? b : a
5327 // Tmp = Max_Float(atmp , btmp)
5328 // Res = (atmp == NaN) ? atmp : Tmp
5329
5330 // max = java.lang.Math.max(float a, float b)
5331 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5332 predicate(UseAVX > 0 && !n->is_reduction());
5333 match(Set dst (MaxF a b));
5334 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5335 format %{
5336 "blendvps $btmp,$b,$a,$b \n\t"
5337 "blendvps $atmp,$a,$b,$b \n\t"
5338 "vmaxss $tmp,$atmp,$btmp \n\t"
5339 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5340 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5341 %}
5342 ins_encode %{
5343 int vector_len = Assembler::AVX_128bit;
5344 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5345 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5346 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5347 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5348 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5349 %}
5350 ins_pipe( pipe_slow );
5351 %}
5352
5353 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5354 predicate(UseAVX > 0 && n->is_reduction());
5355 match(Set dst (MaxF a b));
5356 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5357
5358 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5359 ins_encode %{
5360 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5361 false /*min*/, true /*single*/);
5362 %}
5363 ins_pipe( pipe_slow );
5364 %}
5365
5366 // max = java.lang.Math.max(double a, double b)
5367 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5368 predicate(UseAVX > 0 && !n->is_reduction());
5369 match(Set dst (MaxD a b));
5370 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5371 format %{
5372 "blendvpd $btmp,$b,$a,$b \n\t"
5373 "blendvpd $atmp,$a,$b,$b \n\t"
5374 "vmaxsd $tmp,$atmp,$btmp \n\t"
5375 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5376 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5377 %}
5378 ins_encode %{
5379 int vector_len = Assembler::AVX_128bit;
5380 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5381 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5382 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5383 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5384 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5385 %}
5386 ins_pipe( pipe_slow );
5387 %}
5388
5389 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5390 predicate(UseAVX > 0 && n->is_reduction());
5391 match(Set dst (MaxD a b));
5392 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5393
5394 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5395 ins_encode %{
5396 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5397 false /*min*/, false /*single*/);
5398 %}
5399 ins_pipe( pipe_slow );
5400 %}
5401
5402 // min = java.lang.Math.min(float a, float b)
5403 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5404 predicate(UseAVX > 0 && !n->is_reduction());
5405 match(Set dst (MinF a b));
5406 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5407 format %{
5408 "blendvps $atmp,$a,$b,$a \n\t"
5409 "blendvps $btmp,$b,$a,$a \n\t"
5410 "vminss $tmp,$atmp,$btmp \n\t"
5411 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5412 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5413 %}
5414 ins_encode %{
5415 int vector_len = Assembler::AVX_128bit;
5416 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5417 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5418 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5419 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5420 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5421 %}
5422 ins_pipe( pipe_slow );
5423 %}
5424
5425 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5426 predicate(UseAVX > 0 && n->is_reduction());
5427 match(Set dst (MinF a b));
5428 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5429
5430 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5431 ins_encode %{
5432 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5433 true /*min*/, true /*single*/);
5434 %}
5435 ins_pipe( pipe_slow );
5436 %}
5437
5438 // min = java.lang.Math.min(double a, double b)
5439 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5440 predicate(UseAVX > 0 && !n->is_reduction());
5441 match(Set dst (MinD a b));
5442 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5443 format %{
5444 "blendvpd $atmp,$a,$b,$a \n\t"
5445 "blendvpd $btmp,$b,$a,$a \n\t"
5446 "vminsd $tmp,$atmp,$btmp \n\t"
5447 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5448 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5449 %}
5450 ins_encode %{
5451 int vector_len = Assembler::AVX_128bit;
5452 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5453 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5454 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5455 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5456 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5457 %}
5458 ins_pipe( pipe_slow );
5459 %}
5460
5461 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5462 predicate(UseAVX > 0 && n->is_reduction());
5463 match(Set dst (MinD a b));
5464 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5465
5466 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5467 ins_encode %{
5468 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5469 true /*min*/, false /*single*/);
5470 %}
5471 ins_pipe( pipe_slow );
5472 %}
5473
5474 // Load Effective Address
5475 instruct leaP8(rRegP dst, indOffset8 mem)
5476 %{
5477 match(Set dst mem);
5478
5479 ins_cost(110); // XXX
5480 format %{ "leaq $dst, $mem\t# ptr 8" %}
5481 opcode(0x8D);
5482 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5483 ins_pipe(ialu_reg_reg_fat);
5484 %}
5485
5486 instruct leaP32(rRegP dst, indOffset32 mem)
5487 %{
5488 match(Set dst mem);
5489
5490 ins_cost(110);
5491 format %{ "leaq $dst, $mem\t# ptr 32" %}
5492 opcode(0x8D);
5493 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5494 ins_pipe(ialu_reg_reg_fat);
5495 %}
5496
5497 // instruct leaPIdx(rRegP dst, indIndex mem)
5498 // %{
5499 // match(Set dst mem);
5500
5501 // ins_cost(110);
5502 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5503 // opcode(0x8D);
5504 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5505 // ins_pipe(ialu_reg_reg_fat);
5506 // %}
5507
5508 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5509 %{
5510 match(Set dst mem);
5511
5512 ins_cost(110);
5513 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5514 opcode(0x8D);
5515 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5516 ins_pipe(ialu_reg_reg_fat);
5517 %}
5518
5519 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5520 %{
5521 match(Set dst mem);
5522
5523 ins_cost(110);
5524 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5525 opcode(0x8D);
5526 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5527 ins_pipe(ialu_reg_reg_fat);
5528 %}
5529
5530 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5531 %{
5532 match(Set dst mem);
5533
5534 ins_cost(110);
5535 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5536 opcode(0x8D);
5537 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5538 ins_pipe(ialu_reg_reg_fat);
5539 %}
5540
5541 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5542 %{
5543 match(Set dst mem);
5544
5545 ins_cost(110);
5546 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5547 opcode(0x8D);
5548 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5549 ins_pipe(ialu_reg_reg_fat);
5550 %}
5551
5552 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5553 %{
5554 match(Set dst mem);
5555
5556 ins_cost(110);
5557 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5558 opcode(0x8D);
5559 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5560 ins_pipe(ialu_reg_reg_fat);
5561 %}
5562
5563 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5564 %{
5565 match(Set dst mem);
5566
5567 ins_cost(110);
5568 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5569 opcode(0x8D);
5570 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5571 ins_pipe(ialu_reg_reg_fat);
5572 %}
5573
5574 // Load Effective Address which uses Narrow (32-bits) oop
5575 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5576 %{
5577 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5578 match(Set dst mem);
5579
5580 ins_cost(110);
5581 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5582 opcode(0x8D);
5583 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5584 ins_pipe(ialu_reg_reg_fat);
5585 %}
5586
5587 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5588 %{
5589 predicate(CompressedOops::shift() == 0);
5590 match(Set dst mem);
5591
5592 ins_cost(110); // XXX
5593 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5594 opcode(0x8D);
5595 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5596 ins_pipe(ialu_reg_reg_fat);
5597 %}
5598
5599 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5600 %{
5601 predicate(CompressedOops::shift() == 0);
5602 match(Set dst mem);
5603
5604 ins_cost(110);
5605 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5606 opcode(0x8D);
5607 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5608 ins_pipe(ialu_reg_reg_fat);
5609 %}
5610
5611 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5612 %{
5613 predicate(CompressedOops::shift() == 0);
5614 match(Set dst mem);
5615
5616 ins_cost(110);
5617 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5618 opcode(0x8D);
5619 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5620 ins_pipe(ialu_reg_reg_fat);
5621 %}
5622
5623 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5624 %{
5625 predicate(CompressedOops::shift() == 0);
5626 match(Set dst mem);
5627
5628 ins_cost(110);
5629 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5630 opcode(0x8D);
5631 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5632 ins_pipe(ialu_reg_reg_fat);
5633 %}
5634
5635 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5636 %{
5637 predicate(CompressedOops::shift() == 0);
5638 match(Set dst mem);
5639
5640 ins_cost(110);
5641 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5642 opcode(0x8D);
5643 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5644 ins_pipe(ialu_reg_reg_fat);
5645 %}
5646
5647 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5648 %{
5649 predicate(CompressedOops::shift() == 0);
5650 match(Set dst mem);
5651
5652 ins_cost(110);
5653 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5654 opcode(0x8D);
5655 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5656 ins_pipe(ialu_reg_reg_fat);
5657 %}
5658
5659 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5660 %{
5661 predicate(CompressedOops::shift() == 0);
5662 match(Set dst mem);
5663
5664 ins_cost(110);
5665 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5666 opcode(0x8D);
5667 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5668 ins_pipe(ialu_reg_reg_fat);
5669 %}
5670
5671 instruct loadConI(rRegI dst, immI src)
5672 %{
5673 match(Set dst src);
5674
5675 format %{ "movl $dst, $src\t# int" %}
5676 ins_encode(load_immI(dst, src));
5677 ins_pipe(ialu_reg_fat); // XXX
5678 %}
5679
5680 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5681 %{
5682 match(Set dst src);
5683 effect(KILL cr);
5684
5685 ins_cost(50);
5686 format %{ "xorl $dst, $dst\t# int" %}
5687 opcode(0x33); /* + rd */
5688 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5689 ins_pipe(ialu_reg);
5690 %}
5691
5692 instruct loadConL(rRegL dst, immL src)
5693 %{
5694 match(Set dst src);
5695
5696 ins_cost(150);
5697 format %{ "movq $dst, $src\t# long" %}
5698 ins_encode(load_immL(dst, src));
5699 ins_pipe(ialu_reg);
5700 %}
5701
5702 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5703 %{
5704 match(Set dst src);
5705 effect(KILL cr);
5706
5707 ins_cost(50);
5708 format %{ "xorl $dst, $dst\t# long" %}
5709 opcode(0x33); /* + rd */
5710 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5711 ins_pipe(ialu_reg); // XXX
5712 %}
5713
5714 instruct loadConUL32(rRegL dst, immUL32 src)
5715 %{
5716 match(Set dst src);
5717
5718 ins_cost(60);
5719 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5720 ins_encode(load_immUL32(dst, src));
5721 ins_pipe(ialu_reg);
5722 %}
5723
5724 instruct loadConL32(rRegL dst, immL32 src)
5725 %{
5726 match(Set dst src);
5727
5728 ins_cost(70);
5729 format %{ "movq $dst, $src\t# long (32-bit)" %}
5730 ins_encode(load_immL32(dst, src));
5731 ins_pipe(ialu_reg);
5732 %}
5733
5734 instruct loadConP(rRegP dst, immP con) %{
5735 match(Set dst con);
5736
5737 format %{ "movq $dst, $con\t# ptr" %}
5738 ins_encode(load_immP(dst, con));
5739 ins_pipe(ialu_reg_fat); // XXX
5740 %}
5741
5742 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5743 %{
5744 match(Set dst src);
5745 effect(KILL cr);
5746
5747 ins_cost(50);
5748 format %{ "xorl $dst, $dst\t# ptr" %}
5749 opcode(0x33); /* + rd */
5750 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5751 ins_pipe(ialu_reg);
5752 %}
5753
5754 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5755 %{
5756 match(Set dst src);
5757 effect(KILL cr);
5758
5759 ins_cost(60);
5760 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5761 ins_encode(load_immP31(dst, src));
5762 ins_pipe(ialu_reg);
5763 %}
5764
5765 instruct loadConF(regF dst, immF con) %{
5766 match(Set dst con);
5767 ins_cost(125);
5768 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5769 ins_encode %{
5770 __ movflt($dst$$XMMRegister, $constantaddress($con));
5771 %}
5772 ins_pipe(pipe_slow);
5773 %}
5774
5775 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5776 match(Set dst src);
5777 effect(KILL cr);
5778 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5779 ins_encode %{
5780 __ xorq($dst$$Register, $dst$$Register);
5781 %}
5782 ins_pipe(ialu_reg);
5783 %}
5784
5785 instruct loadConN(rRegN dst, immN src) %{
5786 match(Set dst src);
5787
5788 ins_cost(125);
5789 format %{ "movl $dst, $src\t# compressed ptr" %}
5790 ins_encode %{
5791 address con = (address)$src$$constant;
5792 if (con == NULL) {
5793 ShouldNotReachHere();
5794 } else {
5795 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5796 }
5797 %}
5798 ins_pipe(ialu_reg_fat); // XXX
5799 %}
5800
5801 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5802 match(Set dst src);
5803
5804 ins_cost(125);
5805 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5806 ins_encode %{
5807 address con = (address)$src$$constant;
5808 if (con == NULL) {
5809 ShouldNotReachHere();
5810 } else {
5811 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5812 }
5813 %}
5814 ins_pipe(ialu_reg_fat); // XXX
5815 %}
5816
5817 instruct loadConF0(regF dst, immF0 src)
5818 %{
5819 match(Set dst src);
5820 ins_cost(100);
5821
5822 format %{ "xorps $dst, $dst\t# float 0.0" %}
5823 ins_encode %{
5824 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5825 %}
5826 ins_pipe(pipe_slow);
5827 %}
5828
5829 // Use the same format since predicate() can not be used here.
5830 instruct loadConD(regD dst, immD con) %{
5831 match(Set dst con);
5832 ins_cost(125);
5833 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5834 ins_encode %{
5835 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5836 %}
5837 ins_pipe(pipe_slow);
5838 %}
5839
5840 instruct loadConD0(regD dst, immD0 src)
5841 %{
5842 match(Set dst src);
5843 ins_cost(100);
5844
5845 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5846 ins_encode %{
5847 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5848 %}
5849 ins_pipe(pipe_slow);
5850 %}
5851
5852 instruct loadSSI(rRegI dst, stackSlotI src)
5853 %{
5854 match(Set dst src);
5855
5856 ins_cost(125);
5857 format %{ "movl $dst, $src\t# int stk" %}
5858 opcode(0x8B);
5859 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5860 ins_pipe(ialu_reg_mem);
5861 %}
5862
5863 instruct loadSSL(rRegL dst, stackSlotL src)
5864 %{
5865 match(Set dst src);
5866
5867 ins_cost(125);
5868 format %{ "movq $dst, $src\t# long stk" %}
5869 opcode(0x8B);
5870 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5871 ins_pipe(ialu_reg_mem);
5872 %}
5873
5874 instruct loadSSP(rRegP dst, stackSlotP src)
5875 %{
5876 match(Set dst src);
5877
5878 ins_cost(125);
5879 format %{ "movq $dst, $src\t# ptr stk" %}
5880 opcode(0x8B);
5881 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5882 ins_pipe(ialu_reg_mem);
5883 %}
5884
5885 instruct loadSSF(regF dst, stackSlotF src)
5886 %{
5887 match(Set dst src);
5888
5889 ins_cost(125);
5890 format %{ "movss $dst, $src\t# float stk" %}
5891 ins_encode %{
5892 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5893 %}
5894 ins_pipe(pipe_slow); // XXX
5895 %}
5896
5897 // Use the same format since predicate() can not be used here.
5898 instruct loadSSD(regD dst, stackSlotD src)
5899 %{
5900 match(Set dst src);
5901
5902 ins_cost(125);
5903 format %{ "movsd $dst, $src\t# double stk" %}
5904 ins_encode %{
5905 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5906 %}
5907 ins_pipe(pipe_slow); // XXX
5908 %}
5909
5910 // Prefetch instructions for allocation.
5911 // Must be safe to execute with invalid address (cannot fault).
5912
5913 instruct prefetchAlloc( memory mem ) %{
5914 predicate(AllocatePrefetchInstr==3);
5915 match(PrefetchAllocation mem);
5916 ins_cost(125);
5917
5918 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5919 ins_encode %{
5920 __ prefetchw($mem$$Address);
5921 %}
5922 ins_pipe(ialu_mem);
5923 %}
5924
5925 instruct prefetchAllocNTA( memory mem ) %{
5926 predicate(AllocatePrefetchInstr==0);
5927 match(PrefetchAllocation mem);
5928 ins_cost(125);
5929
5930 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5931 ins_encode %{
5932 __ prefetchnta($mem$$Address);
5933 %}
5934 ins_pipe(ialu_mem);
5935 %}
5936
5937 instruct prefetchAllocT0( memory mem ) %{
5938 predicate(AllocatePrefetchInstr==1);
5939 match(PrefetchAllocation mem);
5940 ins_cost(125);
5941
5942 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5943 ins_encode %{
5944 __ prefetcht0($mem$$Address);
5945 %}
5946 ins_pipe(ialu_mem);
5947 %}
5948
5949 instruct prefetchAllocT2( memory mem ) %{
5950 predicate(AllocatePrefetchInstr==2);
5951 match(PrefetchAllocation mem);
5952 ins_cost(125);
5953
5954 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5955 ins_encode %{
5956 __ prefetcht2($mem$$Address);
5957 %}
5958 ins_pipe(ialu_mem);
5959 %}
5960
5961 //----------Store Instructions-------------------------------------------------
5962
5963 // Store Byte
5964 instruct storeB(memory mem, rRegI src)
5965 %{
5966 match(Set mem (StoreB mem src));
5967
5968 ins_cost(125); // XXX
5969 format %{ "movb $mem, $src\t# byte" %}
5970 opcode(0x88);
5971 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5972 ins_pipe(ialu_mem_reg);
5973 %}
5974
5975 // Store Char/Short
5976 instruct storeC(memory mem, rRegI src)
5977 %{
5978 match(Set mem (StoreC mem src));
5979
5980 ins_cost(125); // XXX
5981 format %{ "movw $mem, $src\t# char/short" %}
5982 opcode(0x89);
5983 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5984 ins_pipe(ialu_mem_reg);
5985 %}
5986
5987 // Store Integer
5988 instruct storeI(memory mem, rRegI src)
5989 %{
5990 match(Set mem (StoreI mem src));
5991
5992 ins_cost(125); // XXX
5993 format %{ "movl $mem, $src\t# int" %}
5994 opcode(0x89);
5995 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5996 ins_pipe(ialu_mem_reg);
5997 %}
5998
5999 // Store Long
6000 instruct storeL(memory mem, rRegL src)
6001 %{
6002 match(Set mem (StoreL mem src));
6003
6004 ins_cost(125); // XXX
6005 format %{ "movq $mem, $src\t# long" %}
6006 opcode(0x89);
6007 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6008 ins_pipe(ialu_mem_reg); // XXX
6009 %}
6010
6011 // Store Pointer
6012 instruct storeP(memory mem, any_RegP src)
6013 %{
6014 match(Set mem (StoreP mem src));
6015
6016 ins_cost(125); // XXX
6017 format %{ "movq $mem, $src\t# ptr" %}
6018 opcode(0x89);
6019 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6020 ins_pipe(ialu_mem_reg);
6021 %}
6022
6023 instruct storeImmP0(memory mem, immP0 zero)
6024 %{
6025 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6026 match(Set mem (StoreP mem zero));
6027
6028 ins_cost(125); // XXX
6029 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6030 ins_encode %{
6031 __ movq($mem$$Address, r12);
6032 %}
6033 ins_pipe(ialu_mem_reg);
6034 %}
6035
6036 // Store NULL Pointer, mark word, or other simple pointer constant.
6037 instruct storeImmP(memory mem, immP31 src)
6038 %{
6039 match(Set mem (StoreP mem src));
6040
6041 ins_cost(150); // XXX
6042 format %{ "movq $mem, $src\t# ptr" %}
6043 opcode(0xC7); /* C7 /0 */
6044 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6045 ins_pipe(ialu_mem_imm);
6046 %}
6047
6048 // Store Compressed Pointer
6049 instruct storeN(memory mem, rRegN src)
6050 %{
6051 match(Set mem (StoreN mem src));
6052
6053 ins_cost(125); // XXX
6054 format %{ "movl $mem, $src\t# compressed ptr" %}
6055 ins_encode %{
6056 __ movl($mem$$Address, $src$$Register);
6057 %}
6058 ins_pipe(ialu_mem_reg);
6059 %}
6060
6061 instruct storeNKlass(memory mem, rRegN src)
6062 %{
6063 match(Set mem (StoreNKlass mem src));
6064
6065 ins_cost(125); // XXX
6066 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6067 ins_encode %{
6068 __ movl($mem$$Address, $src$$Register);
6069 %}
6070 ins_pipe(ialu_mem_reg);
6071 %}
6072
6073 instruct storeImmN0(memory mem, immN0 zero)
6074 %{
6075 predicate(CompressedOops::base() == NULL && CompressedKlassPointers::base() == NULL);
6076 match(Set mem (StoreN mem zero));
6077
6078 ins_cost(125); // XXX
6079 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6080 ins_encode %{
6081 __ movl($mem$$Address, r12);
6082 %}
6083 ins_pipe(ialu_mem_reg);
6084 %}
6085
6086 instruct storeImmN(memory mem, immN src)
6087 %{
6088 match(Set mem (StoreN mem src));
6089
6090 ins_cost(150); // XXX
6091 format %{ "movl $mem, $src\t# compressed ptr" %}
6092 ins_encode %{
6093 address con = (address)$src$$constant;
6094 if (con == NULL) {
6095 __ movl($mem$$Address, (int32_t)0);
6096 } else {
6097 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6098 }
6099 %}
6100 ins_pipe(ialu_mem_imm);
6101 %}
6102
6103 instruct storeImmNKlass(memory mem, immNKlass src)
6104 %{
6105 match(Set mem (StoreNKlass mem src));
6106
6107 ins_cost(150); // XXX
6108 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6109 ins_encode %{
6110 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6111 %}
6112 ins_pipe(ialu_mem_imm);
6113 %}
6114
6115 // Store Integer Immediate
6116 instruct storeImmI0(memory mem, immI0 zero)
6117 %{
6118 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6119 match(Set mem (StoreI mem zero));
6120
6121 ins_cost(125); // XXX
6122 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6123 ins_encode %{
6124 __ movl($mem$$Address, r12);
6125 %}
6126 ins_pipe(ialu_mem_reg);
6127 %}
6128
6129 instruct storeImmI(memory mem, immI src)
6130 %{
6131 match(Set mem (StoreI mem src));
6132
6133 ins_cost(150);
6134 format %{ "movl $mem, $src\t# int" %}
6135 opcode(0xC7); /* C7 /0 */
6136 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6137 ins_pipe(ialu_mem_imm);
6138 %}
6139
6140 // Store Long Immediate
6141 instruct storeImmL0(memory mem, immL0 zero)
6142 %{
6143 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6144 match(Set mem (StoreL mem zero));
6145
6146 ins_cost(125); // XXX
6147 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6148 ins_encode %{
6149 __ movq($mem$$Address, r12);
6150 %}
6151 ins_pipe(ialu_mem_reg);
6152 %}
6153
6154 instruct storeImmL(memory mem, immL32 src)
6155 %{
6156 match(Set mem (StoreL mem src));
6157
6158 ins_cost(150);
6159 format %{ "movq $mem, $src\t# long" %}
6160 opcode(0xC7); /* C7 /0 */
6161 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6162 ins_pipe(ialu_mem_imm);
6163 %}
6164
6165 // Store Short/Char Immediate
6166 instruct storeImmC0(memory mem, immI0 zero)
6167 %{
6168 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6169 match(Set mem (StoreC mem zero));
6170
6171 ins_cost(125); // XXX
6172 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6173 ins_encode %{
6174 __ movw($mem$$Address, r12);
6175 %}
6176 ins_pipe(ialu_mem_reg);
6177 %}
6178
6179 instruct storeImmI16(memory mem, immI16 src)
6180 %{
6181 predicate(UseStoreImmI16);
6182 match(Set mem (StoreC mem src));
6183
6184 ins_cost(150);
6185 format %{ "movw $mem, $src\t# short/char" %}
6186 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6187 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6188 ins_pipe(ialu_mem_imm);
6189 %}
6190
6191 // Store Byte Immediate
6192 instruct storeImmB0(memory mem, immI0 zero)
6193 %{
6194 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6195 match(Set mem (StoreB mem zero));
6196
6197 ins_cost(125); // XXX
6198 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6199 ins_encode %{
6200 __ movb($mem$$Address, r12);
6201 %}
6202 ins_pipe(ialu_mem_reg);
6203 %}
6204
6205 instruct storeImmB(memory mem, immI8 src)
6206 %{
6207 match(Set mem (StoreB mem src));
6208
6209 ins_cost(150); // XXX
6210 format %{ "movb $mem, $src\t# byte" %}
6211 opcode(0xC6); /* C6 /0 */
6212 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6213 ins_pipe(ialu_mem_imm);
6214 %}
6215
6216 // Store CMS card-mark Immediate
6217 instruct storeImmCM0_reg(memory mem, immI0 zero)
6218 %{
6219 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6220 match(Set mem (StoreCM mem zero));
6221
6222 ins_cost(125); // XXX
6223 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6224 ins_encode %{
6225 __ movb($mem$$Address, r12);
6226 %}
6227 ins_pipe(ialu_mem_reg);
6228 %}
6229
6230 instruct storeImmCM0(memory mem, immI0 src)
6231 %{
6232 match(Set mem (StoreCM mem src));
6233
6234 ins_cost(150); // XXX
6235 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6236 opcode(0xC6); /* C6 /0 */
6237 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6238 ins_pipe(ialu_mem_imm);
6239 %}
6240
6241 // Store Float
6242 instruct storeF(memory mem, regF src)
6243 %{
6244 match(Set mem (StoreF mem src));
6245
6246 ins_cost(95); // XXX
6247 format %{ "movss $mem, $src\t# float" %}
6248 ins_encode %{
6249 __ movflt($mem$$Address, $src$$XMMRegister);
6250 %}
6251 ins_pipe(pipe_slow); // XXX
6252 %}
6253
6254 // Store immediate Float value (it is faster than store from XMM register)
6255 instruct storeF0(memory mem, immF0 zero)
6256 %{
6257 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6258 match(Set mem (StoreF mem zero));
6259
6260 ins_cost(25); // XXX
6261 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6262 ins_encode %{
6263 __ movl($mem$$Address, r12);
6264 %}
6265 ins_pipe(ialu_mem_reg);
6266 %}
6267
6268 instruct storeF_imm(memory mem, immF src)
6269 %{
6270 match(Set mem (StoreF mem src));
6271
6272 ins_cost(50);
6273 format %{ "movl $mem, $src\t# float" %}
6274 opcode(0xC7); /* C7 /0 */
6275 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6276 ins_pipe(ialu_mem_imm);
6277 %}
6278
6279 // Store Double
6280 instruct storeD(memory mem, regD src)
6281 %{
6282 match(Set mem (StoreD mem src));
6283
6284 ins_cost(95); // XXX
6285 format %{ "movsd $mem, $src\t# double" %}
6286 ins_encode %{
6287 __ movdbl($mem$$Address, $src$$XMMRegister);
6288 %}
6289 ins_pipe(pipe_slow); // XXX
6290 %}
6291
6292 // Store immediate double 0.0 (it is faster than store from XMM register)
6293 instruct storeD0_imm(memory mem, immD0 src)
6294 %{
6295 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6296 match(Set mem (StoreD mem src));
6297
6298 ins_cost(50);
6299 format %{ "movq $mem, $src\t# double 0." %}
6300 opcode(0xC7); /* C7 /0 */
6301 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6302 ins_pipe(ialu_mem_imm);
6303 %}
6304
6305 instruct storeD0(memory mem, immD0 zero)
6306 %{
6307 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6308 match(Set mem (StoreD mem zero));
6309
6310 ins_cost(25); // XXX
6311 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6312 ins_encode %{
6313 __ movq($mem$$Address, r12);
6314 %}
6315 ins_pipe(ialu_mem_reg);
6316 %}
6317
6318 instruct storeSSI(stackSlotI dst, rRegI src)
6319 %{
6320 match(Set dst src);
6321
6322 ins_cost(100);
6323 format %{ "movl $dst, $src\t# int stk" %}
6324 opcode(0x89);
6325 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6326 ins_pipe( ialu_mem_reg );
6327 %}
6328
6329 instruct storeSSL(stackSlotL dst, rRegL src)
6330 %{
6331 match(Set dst src);
6332
6333 ins_cost(100);
6334 format %{ "movq $dst, $src\t# long stk" %}
6335 opcode(0x89);
6336 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6337 ins_pipe(ialu_mem_reg);
6338 %}
6339
6340 instruct storeSSP(stackSlotP dst, rRegP src)
6341 %{
6342 match(Set dst src);
6343
6344 ins_cost(100);
6345 format %{ "movq $dst, $src\t# ptr stk" %}
6346 opcode(0x89);
6347 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6348 ins_pipe(ialu_mem_reg);
6349 %}
6350
6351 instruct storeSSF(stackSlotF dst, regF src)
6352 %{
6353 match(Set dst src);
6354
6355 ins_cost(95); // XXX
6356 format %{ "movss $dst, $src\t# float stk" %}
6357 ins_encode %{
6358 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6359 %}
6360 ins_pipe(pipe_slow); // XXX
6361 %}
6362
6363 instruct storeSSD(stackSlotD dst, regD src)
6364 %{
6365 match(Set dst src);
6366
6367 ins_cost(95); // XXX
6368 format %{ "movsd $dst, $src\t# double stk" %}
6369 ins_encode %{
6370 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6371 %}
6372 ins_pipe(pipe_slow); // XXX
6373 %}
6374
6375 instruct cacheWB(indirect addr)
6376 %{
6377 predicate(VM_Version::supports_data_cache_line_flush());
6378 match(CacheWB addr);
6379
6380 ins_cost(100);
6381 format %{"cache wb $addr" %}
6382 ins_encode %{
6383 assert($addr->index_position() < 0, "should be");
6384 assert($addr$$disp == 0, "should be");
6385 __ cache_wb(Address($addr$$base$$Register, 0));
6386 %}
6387 ins_pipe(pipe_slow); // XXX
6388 %}
6389
6390 instruct cacheWBPreSync()
6391 %{
6392 predicate(VM_Version::supports_data_cache_line_flush());
6393 match(CacheWBPreSync);
6394
6395 ins_cost(100);
6396 format %{"cache wb presync" %}
6397 ins_encode %{
6398 __ cache_wbsync(true);
6399 %}
6400 ins_pipe(pipe_slow); // XXX
6401 %}
6402
6403 instruct cacheWBPostSync()
6404 %{
6405 predicate(VM_Version::supports_data_cache_line_flush());
6406 match(CacheWBPostSync);
6407
6408 ins_cost(100);
6409 format %{"cache wb postsync" %}
6410 ins_encode %{
6411 __ cache_wbsync(false);
6412 %}
6413 ins_pipe(pipe_slow); // XXX
6414 %}
6415
6416 //----------BSWAP Instructions-------------------------------------------------
6417 instruct bytes_reverse_int(rRegI dst) %{
6418 match(Set dst (ReverseBytesI dst));
6419
6420 format %{ "bswapl $dst" %}
6421 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6422 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6423 ins_pipe( ialu_reg );
6424 %}
6425
6426 instruct bytes_reverse_long(rRegL dst) %{
6427 match(Set dst (ReverseBytesL dst));
6428
6429 format %{ "bswapq $dst" %}
6430 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6431 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6432 ins_pipe( ialu_reg);
6433 %}
6434
6435 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6436 match(Set dst (ReverseBytesUS dst));
6437 effect(KILL cr);
6438
6439 format %{ "bswapl $dst\n\t"
6440 "shrl $dst,16\n\t" %}
6441 ins_encode %{
6442 __ bswapl($dst$$Register);
6443 __ shrl($dst$$Register, 16);
6444 %}
6445 ins_pipe( ialu_reg );
6446 %}
6447
6448 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6449 match(Set dst (ReverseBytesS dst));
6450 effect(KILL cr);
6451
6452 format %{ "bswapl $dst\n\t"
6453 "sar $dst,16\n\t" %}
6454 ins_encode %{
6455 __ bswapl($dst$$Register);
6456 __ sarl($dst$$Register, 16);
6457 %}
6458 ins_pipe( ialu_reg );
6459 %}
6460
6461 //---------- Zeros Count Instructions ------------------------------------------
6462
6463 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6464 predicate(UseCountLeadingZerosInstruction);
6465 match(Set dst (CountLeadingZerosI src));
6466 effect(KILL cr);
6467
6468 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6469 ins_encode %{
6470 __ lzcntl($dst$$Register, $src$$Register);
6471 %}
6472 ins_pipe(ialu_reg);
6473 %}
6474
6475 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6476 predicate(!UseCountLeadingZerosInstruction);
6477 match(Set dst (CountLeadingZerosI src));
6478 effect(KILL cr);
6479
6480 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6481 "jnz skip\n\t"
6482 "movl $dst, -1\n"
6483 "skip:\n\t"
6484 "negl $dst\n\t"
6485 "addl $dst, 31" %}
6486 ins_encode %{
6487 Register Rdst = $dst$$Register;
6488 Register Rsrc = $src$$Register;
6489 Label skip;
6490 __ bsrl(Rdst, Rsrc);
6491 __ jccb(Assembler::notZero, skip);
6492 __ movl(Rdst, -1);
6493 __ bind(skip);
6494 __ negl(Rdst);
6495 __ addl(Rdst, BitsPerInt - 1);
6496 %}
6497 ins_pipe(ialu_reg);
6498 %}
6499
6500 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6501 predicate(UseCountLeadingZerosInstruction);
6502 match(Set dst (CountLeadingZerosL src));
6503 effect(KILL cr);
6504
6505 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6506 ins_encode %{
6507 __ lzcntq($dst$$Register, $src$$Register);
6508 %}
6509 ins_pipe(ialu_reg);
6510 %}
6511
6512 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6513 predicate(!UseCountLeadingZerosInstruction);
6514 match(Set dst (CountLeadingZerosL src));
6515 effect(KILL cr);
6516
6517 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6518 "jnz skip\n\t"
6519 "movl $dst, -1\n"
6520 "skip:\n\t"
6521 "negl $dst\n\t"
6522 "addl $dst, 63" %}
6523 ins_encode %{
6524 Register Rdst = $dst$$Register;
6525 Register Rsrc = $src$$Register;
6526 Label skip;
6527 __ bsrq(Rdst, Rsrc);
6528 __ jccb(Assembler::notZero, skip);
6529 __ movl(Rdst, -1);
6530 __ bind(skip);
6531 __ negl(Rdst);
6532 __ addl(Rdst, BitsPerLong - 1);
6533 %}
6534 ins_pipe(ialu_reg);
6535 %}
6536
6537 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6538 predicate(UseCountTrailingZerosInstruction);
6539 match(Set dst (CountTrailingZerosI src));
6540 effect(KILL cr);
6541
6542 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6543 ins_encode %{
6544 __ tzcntl($dst$$Register, $src$$Register);
6545 %}
6546 ins_pipe(ialu_reg);
6547 %}
6548
6549 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6550 predicate(!UseCountTrailingZerosInstruction);
6551 match(Set dst (CountTrailingZerosI src));
6552 effect(KILL cr);
6553
6554 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6555 "jnz done\n\t"
6556 "movl $dst, 32\n"
6557 "done:" %}
6558 ins_encode %{
6559 Register Rdst = $dst$$Register;
6560 Label done;
6561 __ bsfl(Rdst, $src$$Register);
6562 __ jccb(Assembler::notZero, done);
6563 __ movl(Rdst, BitsPerInt);
6564 __ bind(done);
6565 %}
6566 ins_pipe(ialu_reg);
6567 %}
6568
6569 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6570 predicate(UseCountTrailingZerosInstruction);
6571 match(Set dst (CountTrailingZerosL src));
6572 effect(KILL cr);
6573
6574 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6575 ins_encode %{
6576 __ tzcntq($dst$$Register, $src$$Register);
6577 %}
6578 ins_pipe(ialu_reg);
6579 %}
6580
6581 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6582 predicate(!UseCountTrailingZerosInstruction);
6583 match(Set dst (CountTrailingZerosL src));
6584 effect(KILL cr);
6585
6586 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6587 "jnz done\n\t"
6588 "movl $dst, 64\n"
6589 "done:" %}
6590 ins_encode %{
6591 Register Rdst = $dst$$Register;
6592 Label done;
6593 __ bsfq(Rdst, $src$$Register);
6594 __ jccb(Assembler::notZero, done);
6595 __ movl(Rdst, BitsPerLong);
6596 __ bind(done);
6597 %}
6598 ins_pipe(ialu_reg);
6599 %}
6600
6601
6602 //---------- Population Count Instructions -------------------------------------
6603
6604 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6605 predicate(UsePopCountInstruction);
6606 match(Set dst (PopCountI src));
6607 effect(KILL cr);
6608
6609 format %{ "popcnt $dst, $src" %}
6610 ins_encode %{
6611 __ popcntl($dst$$Register, $src$$Register);
6612 %}
6613 ins_pipe(ialu_reg);
6614 %}
6615
6616 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6617 predicate(UsePopCountInstruction);
6618 match(Set dst (PopCountI (LoadI mem)));
6619 effect(KILL cr);
6620
6621 format %{ "popcnt $dst, $mem" %}
6622 ins_encode %{
6623 __ popcntl($dst$$Register, $mem$$Address);
6624 %}
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 // Note: Long.bitCount(long) returns an int.
6629 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6630 predicate(UsePopCountInstruction);
6631 match(Set dst (PopCountL src));
6632 effect(KILL cr);
6633
6634 format %{ "popcnt $dst, $src" %}
6635 ins_encode %{
6636 __ popcntq($dst$$Register, $src$$Register);
6637 %}
6638 ins_pipe(ialu_reg);
6639 %}
6640
6641 // Note: Long.bitCount(long) returns an int.
6642 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6643 predicate(UsePopCountInstruction);
6644 match(Set dst (PopCountL (LoadL mem)));
6645 effect(KILL cr);
6646
6647 format %{ "popcnt $dst, $mem" %}
6648 ins_encode %{
6649 __ popcntq($dst$$Register, $mem$$Address);
6650 %}
6651 ins_pipe(ialu_reg);
6652 %}
6653
6654
6655 //----------MemBar Instructions-----------------------------------------------
6656 // Memory barrier flavors
6657
6658 instruct membar_acquire()
6659 %{
6660 match(MemBarAcquire);
6661 match(LoadFence);
6662 ins_cost(0);
6663
6664 size(0);
6665 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6666 ins_encode();
6667 ins_pipe(empty);
6668 %}
6669
6670 instruct membar_acquire_lock()
6671 %{
6672 match(MemBarAcquireLock);
6673 ins_cost(0);
6674
6675 size(0);
6676 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6677 ins_encode();
6678 ins_pipe(empty);
6679 %}
6680
6681 instruct membar_release()
6682 %{
6683 match(MemBarRelease);
6684 match(StoreFence);
6685 ins_cost(0);
6686
6687 size(0);
6688 format %{ "MEMBAR-release ! (empty encoding)" %}
6689 ins_encode();
6690 ins_pipe(empty);
6691 %}
6692
6693 instruct membar_release_lock()
6694 %{
6695 match(MemBarReleaseLock);
6696 ins_cost(0);
6697
6698 size(0);
6699 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6700 ins_encode();
6701 ins_pipe(empty);
6702 %}
6703
6704 instruct membar_volatile(rFlagsReg cr) %{
6705 match(MemBarVolatile);
6706 effect(KILL cr);
6707 ins_cost(400);
6708
6709 format %{
6710 $$template
6711 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6712 %}
6713 ins_encode %{
6714 __ membar(Assembler::StoreLoad);
6715 %}
6716 ins_pipe(pipe_slow);
6717 %}
6718
6719 instruct unnecessary_membar_volatile()
6720 %{
6721 match(MemBarVolatile);
6722 predicate(Matcher::post_store_load_barrier(n));
6723 ins_cost(0);
6724
6725 size(0);
6726 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6727 ins_encode();
6728 ins_pipe(empty);
6729 %}
6730
6731 instruct membar_storestore() %{
6732 match(MemBarStoreStore);
6733 ins_cost(0);
6734
6735 size(0);
6736 format %{ "MEMBAR-storestore (empty encoding)" %}
6737 ins_encode( );
6738 ins_pipe(empty);
6739 %}
6740
6741 //----------Move Instructions--------------------------------------------------
6742
6743 instruct castX2P(rRegP dst, rRegL src)
6744 %{
6745 match(Set dst (CastX2P src));
6746
6747 format %{ "movq $dst, $src\t# long->ptr" %}
6748 ins_encode %{
6749 if ($dst$$reg != $src$$reg) {
6750 __ movptr($dst$$Register, $src$$Register);
6751 }
6752 %}
6753 ins_pipe(ialu_reg_reg); // XXX
6754 %}
6755
6756 instruct castP2X(rRegL dst, rRegP src)
6757 %{
6758 match(Set dst (CastP2X src));
6759
6760 format %{ "movq $dst, $src\t# ptr -> long" %}
6761 ins_encode %{
6762 if ($dst$$reg != $src$$reg) {
6763 __ movptr($dst$$Register, $src$$Register);
6764 }
6765 %}
6766 ins_pipe(ialu_reg_reg); // XXX
6767 %}
6768
6769 // Convert oop into int for vectors alignment masking
6770 instruct convP2I(rRegI dst, rRegP src)
6771 %{
6772 match(Set dst (ConvL2I (CastP2X src)));
6773
6774 format %{ "movl $dst, $src\t# ptr -> int" %}
6775 ins_encode %{
6776 __ movl($dst$$Register, $src$$Register);
6777 %}
6778 ins_pipe(ialu_reg_reg); // XXX
6779 %}
6780
6781 // Convert compressed oop into int for vectors alignment masking
6782 // in case of 32bit oops (heap < 4Gb).
6783 instruct convN2I(rRegI dst, rRegN src)
6784 %{
6785 predicate(CompressedOops::shift() == 0);
6786 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6787
6788 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6789 ins_encode %{
6790 __ movl($dst$$Register, $src$$Register);
6791 %}
6792 ins_pipe(ialu_reg_reg); // XXX
6793 %}
6794
6795 // Convert oop pointer into compressed form
6796 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6797 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6798 match(Set dst (EncodeP src));
6799 effect(KILL cr);
6800 format %{ "encode_heap_oop $dst,$src" %}
6801 ins_encode %{
6802 Register s = $src$$Register;
6803 Register d = $dst$$Register;
6804 if (s != d) {
6805 __ movq(d, s);
6806 }
6807 __ encode_heap_oop(d);
6808 %}
6809 ins_pipe(ialu_reg_long);
6810 %}
6811
6812 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6813 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6814 match(Set dst (EncodeP src));
6815 effect(KILL cr);
6816 format %{ "encode_heap_oop_not_null $dst,$src" %}
6817 ins_encode %{
6818 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6819 %}
6820 ins_pipe(ialu_reg_long);
6821 %}
6822
6823 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6824 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6825 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6826 match(Set dst (DecodeN src));
6827 effect(KILL cr);
6828 format %{ "decode_heap_oop $dst,$src" %}
6829 ins_encode %{
6830 Register s = $src$$Register;
6831 Register d = $dst$$Register;
6832 if (s != d) {
6833 __ movq(d, s);
6834 }
6835 __ decode_heap_oop(d);
6836 %}
6837 ins_pipe(ialu_reg_long);
6838 %}
6839
6840 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6841 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6842 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6843 match(Set dst (DecodeN src));
6844 effect(KILL cr);
6845 format %{ "decode_heap_oop_not_null $dst,$src" %}
6846 ins_encode %{
6847 Register s = $src$$Register;
6848 Register d = $dst$$Register;
6849 if (s != d) {
6850 __ decode_heap_oop_not_null(d, s);
6851 } else {
6852 __ decode_heap_oop_not_null(d);
6853 }
6854 %}
6855 ins_pipe(ialu_reg_long);
6856 %}
6857
6858 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6859 match(Set dst (EncodePKlass src));
6860 effect(KILL cr);
6861 format %{ "encode_klass_not_null $dst,$src" %}
6862 ins_encode %{
6863 __ encode_klass_not_null($dst$$Register, $src$$Register);
6864 %}
6865 ins_pipe(ialu_reg_long);
6866 %}
6867
6868 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6869 match(Set dst (DecodeNKlass src));
6870 effect(KILL cr);
6871 format %{ "decode_klass_not_null $dst,$src" %}
6872 ins_encode %{
6873 Register s = $src$$Register;
6874 Register d = $dst$$Register;
6875 if (s != d) {
6876 __ decode_klass_not_null(d, s);
6877 } else {
6878 __ decode_klass_not_null(d);
6879 }
6880 %}
6881 ins_pipe(ialu_reg_long);
6882 %}
6883
6884
6885 //----------Conditional Move---------------------------------------------------
6886 // Jump
6887 // dummy instruction for generating temp registers
6888 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6889 match(Jump (LShiftL switch_val shift));
6890 ins_cost(350);
6891 predicate(false);
6892 effect(TEMP dest);
6893
6894 format %{ "leaq $dest, [$constantaddress]\n\t"
6895 "jmp [$dest + $switch_val << $shift]\n\t" %}
6896 ins_encode %{
6897 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6898 // to do that and the compiler is using that register as one it can allocate.
6899 // So we build it all by hand.
6900 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6901 // ArrayAddress dispatch(table, index);
6902 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6903 __ lea($dest$$Register, $constantaddress);
6904 __ jmp(dispatch);
6905 %}
6906 ins_pipe(pipe_jmp);
6907 %}
6908
6909 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6910 match(Jump (AddL (LShiftL switch_val shift) offset));
6911 ins_cost(350);
6912 effect(TEMP dest);
6913
6914 format %{ "leaq $dest, [$constantaddress]\n\t"
6915 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6916 ins_encode %{
6917 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6918 // to do that and the compiler is using that register as one it can allocate.
6919 // So we build it all by hand.
6920 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6921 // ArrayAddress dispatch(table, index);
6922 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6923 __ lea($dest$$Register, $constantaddress);
6924 __ jmp(dispatch);
6925 %}
6926 ins_pipe(pipe_jmp);
6927 %}
6928
6929 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6930 match(Jump switch_val);
6931 ins_cost(350);
6932 effect(TEMP dest);
6933
6934 format %{ "leaq $dest, [$constantaddress]\n\t"
6935 "jmp [$dest + $switch_val]\n\t" %}
6936 ins_encode %{
6937 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6938 // to do that and the compiler is using that register as one it can allocate.
6939 // So we build it all by hand.
6940 // Address index(noreg, switch_reg, Address::times_1);
6941 // ArrayAddress dispatch(table, index);
6942 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6943 __ lea($dest$$Register, $constantaddress);
6944 __ jmp(dispatch);
6945 %}
6946 ins_pipe(pipe_jmp);
6947 %}
6948
6949 // Conditional move
6950 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6951 %{
6952 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6953
6954 ins_cost(200); // XXX
6955 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6956 opcode(0x0F, 0x40);
6957 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6958 ins_pipe(pipe_cmov_reg);
6959 %}
6960
6961 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6962 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6963
6964 ins_cost(200); // XXX
6965 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6966 opcode(0x0F, 0x40);
6967 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6968 ins_pipe(pipe_cmov_reg);
6969 %}
6970
6971 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6972 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6973 ins_cost(200);
6974 expand %{
6975 cmovI_regU(cop, cr, dst, src);
6976 %}
6977 %}
6978
6979 // Conditional move
6980 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6981 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6982
6983 ins_cost(250); // XXX
6984 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6985 opcode(0x0F, 0x40);
6986 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6987 ins_pipe(pipe_cmov_mem);
6988 %}
6989
6990 // Conditional move
6991 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6992 %{
6993 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6994
6995 ins_cost(250); // XXX
6996 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6997 opcode(0x0F, 0x40);
6998 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6999 ins_pipe(pipe_cmov_mem);
7000 %}
7001
7002 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7003 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7004 ins_cost(250);
7005 expand %{
7006 cmovI_memU(cop, cr, dst, src);
7007 %}
7008 %}
7009
7010 // Conditional move
7011 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7012 %{
7013 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7014
7015 ins_cost(200); // XXX
7016 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7017 opcode(0x0F, 0x40);
7018 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7019 ins_pipe(pipe_cmov_reg);
7020 %}
7021
7022 // Conditional move
7023 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7024 %{
7025 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7026
7027 ins_cost(200); // XXX
7028 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7029 opcode(0x0F, 0x40);
7030 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7031 ins_pipe(pipe_cmov_reg);
7032 %}
7033
7034 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7035 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7036 ins_cost(200);
7037 expand %{
7038 cmovN_regU(cop, cr, dst, src);
7039 %}
7040 %}
7041
7042 // Conditional move
7043 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7044 %{
7045 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7046
7047 ins_cost(200); // XXX
7048 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7049 opcode(0x0F, 0x40);
7050 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7051 ins_pipe(pipe_cmov_reg); // XXX
7052 %}
7053
7054 // Conditional move
7055 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7056 %{
7057 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7058
7059 ins_cost(200); // XXX
7060 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7061 opcode(0x0F, 0x40);
7062 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7063 ins_pipe(pipe_cmov_reg); // XXX
7064 %}
7065
7066 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7067 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7068 ins_cost(200);
7069 expand %{
7070 cmovP_regU(cop, cr, dst, src);
7071 %}
7072 %}
7073
7074 // DISABLED: Requires the ADLC to emit a bottom_type call that
7075 // correctly meets the two pointer arguments; one is an incoming
7076 // register but the other is a memory operand. ALSO appears to
7077 // be buggy with implicit null checks.
7078 //
7079 //// Conditional move
7080 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7081 //%{
7082 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7083 // ins_cost(250);
7084 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7085 // opcode(0x0F,0x40);
7086 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7087 // ins_pipe( pipe_cmov_mem );
7088 //%}
7089 //
7090 //// Conditional move
7091 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7092 //%{
7093 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7094 // ins_cost(250);
7095 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7096 // opcode(0x0F,0x40);
7097 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7098 // ins_pipe( pipe_cmov_mem );
7099 //%}
7100
7101 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7102 %{
7103 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7104
7105 ins_cost(200); // XXX
7106 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7107 opcode(0x0F, 0x40);
7108 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7109 ins_pipe(pipe_cmov_reg); // XXX
7110 %}
7111
7112 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7113 %{
7114 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7115
7116 ins_cost(200); // XXX
7117 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7118 opcode(0x0F, 0x40);
7119 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7120 ins_pipe(pipe_cmov_mem); // XXX
7121 %}
7122
7123 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7124 %{
7125 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7126
7127 ins_cost(200); // XXX
7128 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7129 opcode(0x0F, 0x40);
7130 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7131 ins_pipe(pipe_cmov_reg); // XXX
7132 %}
7133
7134 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7135 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7136 ins_cost(200);
7137 expand %{
7138 cmovL_regU(cop, cr, dst, src);
7139 %}
7140 %}
7141
7142 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7143 %{
7144 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7145
7146 ins_cost(200); // XXX
7147 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7148 opcode(0x0F, 0x40);
7149 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7150 ins_pipe(pipe_cmov_mem); // XXX
7151 %}
7152
7153 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7154 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7155 ins_cost(200);
7156 expand %{
7157 cmovL_memU(cop, cr, dst, src);
7158 %}
7159 %}
7160
7161 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7162 %{
7163 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7164
7165 ins_cost(200); // XXX
7166 format %{ "jn$cop skip\t# signed cmove float\n\t"
7167 "movss $dst, $src\n"
7168 "skip:" %}
7169 ins_encode %{
7170 Label Lskip;
7171 // Invert sense of branch from sense of CMOV
7172 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7173 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7174 __ bind(Lskip);
7175 %}
7176 ins_pipe(pipe_slow);
7177 %}
7178
7179 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7180 // %{
7181 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7182
7183 // ins_cost(200); // XXX
7184 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7185 // "movss $dst, $src\n"
7186 // "skip:" %}
7187 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7188 // ins_pipe(pipe_slow);
7189 // %}
7190
7191 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7192 %{
7193 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7194
7195 ins_cost(200); // XXX
7196 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7197 "movss $dst, $src\n"
7198 "skip:" %}
7199 ins_encode %{
7200 Label Lskip;
7201 // Invert sense of branch from sense of CMOV
7202 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7203 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7204 __ bind(Lskip);
7205 %}
7206 ins_pipe(pipe_slow);
7207 %}
7208
7209 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7210 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7211 ins_cost(200);
7212 expand %{
7213 cmovF_regU(cop, cr, dst, src);
7214 %}
7215 %}
7216
7217 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7218 %{
7219 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7220
7221 ins_cost(200); // XXX
7222 format %{ "jn$cop skip\t# signed cmove double\n\t"
7223 "movsd $dst, $src\n"
7224 "skip:" %}
7225 ins_encode %{
7226 Label Lskip;
7227 // Invert sense of branch from sense of CMOV
7228 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7229 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7230 __ bind(Lskip);
7231 %}
7232 ins_pipe(pipe_slow);
7233 %}
7234
7235 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7236 %{
7237 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7238
7239 ins_cost(200); // XXX
7240 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7241 "movsd $dst, $src\n"
7242 "skip:" %}
7243 ins_encode %{
7244 Label Lskip;
7245 // Invert sense of branch from sense of CMOV
7246 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7247 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7248 __ bind(Lskip);
7249 %}
7250 ins_pipe(pipe_slow);
7251 %}
7252
7253 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7254 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7255 ins_cost(200);
7256 expand %{
7257 cmovD_regU(cop, cr, dst, src);
7258 %}
7259 %}
7260
7261 //----------Arithmetic Instructions--------------------------------------------
7262 //----------Addition Instructions----------------------------------------------
7263
7264 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7265 %{
7266 match(Set dst (AddI dst src));
7267 effect(KILL cr);
7268
7269 format %{ "addl $dst, $src\t# int" %}
7270 opcode(0x03);
7271 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7272 ins_pipe(ialu_reg_reg);
7273 %}
7274
7275 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7276 %{
7277 match(Set dst (AddI dst src));
7278 effect(KILL cr);
7279
7280 format %{ "addl $dst, $src\t# int" %}
7281 opcode(0x81, 0x00); /* /0 id */
7282 ins_encode(OpcSErm(dst, src), Con8or32(src));
7283 ins_pipe( ialu_reg );
7284 %}
7285
7286 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7287 %{
7288 match(Set dst (AddI dst (LoadI src)));
7289 effect(KILL cr);
7290
7291 ins_cost(125); // XXX
7292 format %{ "addl $dst, $src\t# int" %}
7293 opcode(0x03);
7294 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7295 ins_pipe(ialu_reg_mem);
7296 %}
7297
7298 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7299 %{
7300 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7301 effect(KILL cr);
7302
7303 ins_cost(150); // XXX
7304 format %{ "addl $dst, $src\t# int" %}
7305 opcode(0x01); /* Opcode 01 /r */
7306 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7307 ins_pipe(ialu_mem_reg);
7308 %}
7309
7310 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7311 %{
7312 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7313 effect(KILL cr);
7314
7315 ins_cost(125); // XXX
7316 format %{ "addl $dst, $src\t# int" %}
7317 opcode(0x81); /* Opcode 81 /0 id */
7318 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7319 ins_pipe(ialu_mem_imm);
7320 %}
7321
7322 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7323 %{
7324 predicate(UseIncDec);
7325 match(Set dst (AddI dst src));
7326 effect(KILL cr);
7327
7328 format %{ "incl $dst\t# int" %}
7329 opcode(0xFF, 0x00); // FF /0
7330 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7331 ins_pipe(ialu_reg);
7332 %}
7333
7334 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7335 %{
7336 predicate(UseIncDec);
7337 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7338 effect(KILL cr);
7339
7340 ins_cost(125); // XXX
7341 format %{ "incl $dst\t# int" %}
7342 opcode(0xFF); /* Opcode FF /0 */
7343 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7344 ins_pipe(ialu_mem_imm);
7345 %}
7346
7347 // XXX why does that use AddI
7348 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7349 %{
7350 predicate(UseIncDec);
7351 match(Set dst (AddI dst src));
7352 effect(KILL cr);
7353
7354 format %{ "decl $dst\t# int" %}
7355 opcode(0xFF, 0x01); // FF /1
7356 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7357 ins_pipe(ialu_reg);
7358 %}
7359
7360 // XXX why does that use AddI
7361 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7362 %{
7363 predicate(UseIncDec);
7364 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7365 effect(KILL cr);
7366
7367 ins_cost(125); // XXX
7368 format %{ "decl $dst\t# int" %}
7369 opcode(0xFF); /* Opcode FF /1 */
7370 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7371 ins_pipe(ialu_mem_imm);
7372 %}
7373
7374 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7375 %{
7376 match(Set dst (AddI src0 src1));
7377
7378 ins_cost(110);
7379 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7380 opcode(0x8D); /* 0x8D /r */
7381 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7382 ins_pipe(ialu_reg_reg);
7383 %}
7384
7385 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7386 %{
7387 match(Set dst (AddL dst src));
7388 effect(KILL cr);
7389
7390 format %{ "addq $dst, $src\t# long" %}
7391 opcode(0x03);
7392 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7393 ins_pipe(ialu_reg_reg);
7394 %}
7395
7396 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7397 %{
7398 match(Set dst (AddL dst src));
7399 effect(KILL cr);
7400
7401 format %{ "addq $dst, $src\t# long" %}
7402 opcode(0x81, 0x00); /* /0 id */
7403 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7404 ins_pipe( ialu_reg );
7405 %}
7406
7407 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7408 %{
7409 match(Set dst (AddL dst (LoadL src)));
7410 effect(KILL cr);
7411
7412 ins_cost(125); // XXX
7413 format %{ "addq $dst, $src\t# long" %}
7414 opcode(0x03);
7415 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7416 ins_pipe(ialu_reg_mem);
7417 %}
7418
7419 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7420 %{
7421 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7422 effect(KILL cr);
7423
7424 ins_cost(150); // XXX
7425 format %{ "addq $dst, $src\t# long" %}
7426 opcode(0x01); /* Opcode 01 /r */
7427 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7428 ins_pipe(ialu_mem_reg);
7429 %}
7430
7431 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7432 %{
7433 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7434 effect(KILL cr);
7435
7436 ins_cost(125); // XXX
7437 format %{ "addq $dst, $src\t# long" %}
7438 opcode(0x81); /* Opcode 81 /0 id */
7439 ins_encode(REX_mem_wide(dst),
7440 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7441 ins_pipe(ialu_mem_imm);
7442 %}
7443
7444 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7445 %{
7446 predicate(UseIncDec);
7447 match(Set dst (AddL dst src));
7448 effect(KILL cr);
7449
7450 format %{ "incq $dst\t# long" %}
7451 opcode(0xFF, 0x00); // FF /0
7452 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7453 ins_pipe(ialu_reg);
7454 %}
7455
7456 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7457 %{
7458 predicate(UseIncDec);
7459 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7460 effect(KILL cr);
7461
7462 ins_cost(125); // XXX
7463 format %{ "incq $dst\t# long" %}
7464 opcode(0xFF); /* Opcode FF /0 */
7465 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7466 ins_pipe(ialu_mem_imm);
7467 %}
7468
7469 // XXX why does that use AddL
7470 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7471 %{
7472 predicate(UseIncDec);
7473 match(Set dst (AddL dst src));
7474 effect(KILL cr);
7475
7476 format %{ "decq $dst\t# long" %}
7477 opcode(0xFF, 0x01); // FF /1
7478 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7479 ins_pipe(ialu_reg);
7480 %}
7481
7482 // XXX why does that use AddL
7483 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7484 %{
7485 predicate(UseIncDec);
7486 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7487 effect(KILL cr);
7488
7489 ins_cost(125); // XXX
7490 format %{ "decq $dst\t# long" %}
7491 opcode(0xFF); /* Opcode FF /1 */
7492 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7493 ins_pipe(ialu_mem_imm);
7494 %}
7495
7496 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7497 %{
7498 match(Set dst (AddL src0 src1));
7499
7500 ins_cost(110);
7501 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7502 opcode(0x8D); /* 0x8D /r */
7503 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7504 ins_pipe(ialu_reg_reg);
7505 %}
7506
7507 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7508 %{
7509 match(Set dst (AddP dst src));
7510 effect(KILL cr);
7511
7512 format %{ "addq $dst, $src\t# ptr" %}
7513 opcode(0x03);
7514 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7515 ins_pipe(ialu_reg_reg);
7516 %}
7517
7518 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7519 %{
7520 match(Set dst (AddP dst src));
7521 effect(KILL cr);
7522
7523 format %{ "addq $dst, $src\t# ptr" %}
7524 opcode(0x81, 0x00); /* /0 id */
7525 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7526 ins_pipe( ialu_reg );
7527 %}
7528
7529 // XXX addP mem ops ????
7530
7531 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7532 %{
7533 match(Set dst (AddP src0 src1));
7534
7535 ins_cost(110);
7536 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7537 opcode(0x8D); /* 0x8D /r */
7538 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7539 ins_pipe(ialu_reg_reg);
7540 %}
7541
7542 instruct checkCastPP(rRegP dst)
7543 %{
7544 match(Set dst (CheckCastPP dst));
7545
7546 size(0);
7547 format %{ "# checkcastPP of $dst" %}
7548 ins_encode(/* empty encoding */);
7549 ins_pipe(empty);
7550 %}
7551
7552 instruct castPP(rRegP dst)
7553 %{
7554 match(Set dst (CastPP dst));
7555
7556 size(0);
7557 format %{ "# castPP of $dst" %}
7558 ins_encode(/* empty encoding */);
7559 ins_pipe(empty);
7560 %}
7561
7562 instruct castII(rRegI dst)
7563 %{
7564 match(Set dst (CastII dst));
7565
7566 size(0);
7567 format %{ "# castII of $dst" %}
7568 ins_encode(/* empty encoding */);
7569 ins_cost(0);
7570 ins_pipe(empty);
7571 %}
7572
7573 instruct castLL(rRegL dst)
7574 %{
7575 match(Set dst (CastLL dst));
7576
7577 size(0);
7578 format %{ "# castLL of $dst" %}
7579 ins_encode(/* empty encoding */);
7580 ins_cost(0);
7581 ins_pipe(empty);
7582 %}
7583
7584 // LoadP-locked same as a regular LoadP when used with compare-swap
7585 instruct loadPLocked(rRegP dst, memory mem)
7586 %{
7587 match(Set dst (LoadPLocked mem));
7588
7589 ins_cost(125); // XXX
7590 format %{ "movq $dst, $mem\t# ptr locked" %}
7591 opcode(0x8B);
7592 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7593 ins_pipe(ialu_reg_mem); // XXX
7594 %}
7595
7596 // Conditional-store of the updated heap-top.
7597 // Used during allocation of the shared heap.
7598 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7599
7600 instruct storePConditional(memory heap_top_ptr,
7601 rax_RegP oldval, rRegP newval,
7602 rFlagsReg cr)
7603 %{
7604 predicate(n->as_LoadStore()->barrier_data() == 0);
7605 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7606
7607 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7608 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7609 opcode(0x0F, 0xB1);
7610 ins_encode(lock_prefix,
7611 REX_reg_mem_wide(newval, heap_top_ptr),
7612 OpcP, OpcS,
7613 reg_mem(newval, heap_top_ptr));
7614 ins_pipe(pipe_cmpxchg);
7615 %}
7616
7617 // Conditional-store of an int value.
7618 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7619 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7620 %{
7621 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7622 effect(KILL oldval);
7623
7624 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7625 opcode(0x0F, 0xB1);
7626 ins_encode(lock_prefix,
7627 REX_reg_mem(newval, mem),
7628 OpcP, OpcS,
7629 reg_mem(newval, mem));
7630 ins_pipe(pipe_cmpxchg);
7631 %}
7632
7633 // Conditional-store of a long value.
7634 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7635 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7636 %{
7637 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7638 effect(KILL oldval);
7639
7640 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7641 opcode(0x0F, 0xB1);
7642 ins_encode(lock_prefix,
7643 REX_reg_mem_wide(newval, mem),
7644 OpcP, OpcS,
7645 reg_mem(newval, mem));
7646 ins_pipe(pipe_cmpxchg);
7647 %}
7648
7649
7650 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7651 instruct compareAndSwapP(rRegI res,
7652 memory mem_ptr,
7653 rax_RegP oldval, rRegP newval,
7654 rFlagsReg cr)
7655 %{
7656 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7657 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7658 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7659 effect(KILL cr, KILL oldval);
7660
7661 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7662 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7663 "sete $res\n\t"
7664 "movzbl $res, $res" %}
7665 opcode(0x0F, 0xB1);
7666 ins_encode(lock_prefix,
7667 REX_reg_mem_wide(newval, mem_ptr),
7668 OpcP, OpcS,
7669 reg_mem(newval, mem_ptr),
7670 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7671 REX_reg_breg(res, res), // movzbl
7672 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7673 ins_pipe( pipe_cmpxchg );
7674 %}
7675
7676 instruct compareAndSwapL(rRegI res,
7677 memory mem_ptr,
7678 rax_RegL oldval, rRegL newval,
7679 rFlagsReg cr)
7680 %{
7681 predicate(VM_Version::supports_cx8());
7682 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7683 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7684 effect(KILL cr, KILL oldval);
7685
7686 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7687 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7688 "sete $res\n\t"
7689 "movzbl $res, $res" %}
7690 opcode(0x0F, 0xB1);
7691 ins_encode(lock_prefix,
7692 REX_reg_mem_wide(newval, mem_ptr),
7693 OpcP, OpcS,
7694 reg_mem(newval, mem_ptr),
7695 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7696 REX_reg_breg(res, res), // movzbl
7697 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7698 ins_pipe( pipe_cmpxchg );
7699 %}
7700
7701 instruct compareAndSwapI(rRegI res,
7702 memory mem_ptr,
7703 rax_RegI oldval, rRegI newval,
7704 rFlagsReg cr)
7705 %{
7706 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7707 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7708 effect(KILL cr, KILL oldval);
7709
7710 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7711 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7712 "sete $res\n\t"
7713 "movzbl $res, $res" %}
7714 opcode(0x0F, 0xB1);
7715 ins_encode(lock_prefix,
7716 REX_reg_mem(newval, mem_ptr),
7717 OpcP, OpcS,
7718 reg_mem(newval, mem_ptr),
7719 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7720 REX_reg_breg(res, res), // movzbl
7721 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7722 ins_pipe( pipe_cmpxchg );
7723 %}
7724
7725 instruct compareAndSwapB(rRegI res,
7726 memory mem_ptr,
7727 rax_RegI oldval, rRegI newval,
7728 rFlagsReg cr)
7729 %{
7730 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7731 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7732 effect(KILL cr, KILL oldval);
7733
7734 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7735 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7736 "sete $res\n\t"
7737 "movzbl $res, $res" %}
7738 opcode(0x0F, 0xB0);
7739 ins_encode(lock_prefix,
7740 REX_breg_mem(newval, mem_ptr),
7741 OpcP, OpcS,
7742 reg_mem(newval, mem_ptr),
7743 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7744 REX_reg_breg(res, res), // movzbl
7745 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7746 ins_pipe( pipe_cmpxchg );
7747 %}
7748
7749 instruct compareAndSwapS(rRegI res,
7750 memory mem_ptr,
7751 rax_RegI oldval, rRegI newval,
7752 rFlagsReg cr)
7753 %{
7754 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7755 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7756 effect(KILL cr, KILL oldval);
7757
7758 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7759 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7760 "sete $res\n\t"
7761 "movzbl $res, $res" %}
7762 opcode(0x0F, 0xB1);
7763 ins_encode(lock_prefix,
7764 SizePrefix,
7765 REX_reg_mem(newval, mem_ptr),
7766 OpcP, OpcS,
7767 reg_mem(newval, mem_ptr),
7768 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7769 REX_reg_breg(res, res), // movzbl
7770 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7771 ins_pipe( pipe_cmpxchg );
7772 %}
7773
7774 instruct compareAndSwapN(rRegI res,
7775 memory mem_ptr,
7776 rax_RegN oldval, rRegN newval,
7777 rFlagsReg cr) %{
7778 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7779 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7780 effect(KILL cr, KILL oldval);
7781
7782 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7783 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7784 "sete $res\n\t"
7785 "movzbl $res, $res" %}
7786 opcode(0x0F, 0xB1);
7787 ins_encode(lock_prefix,
7788 REX_reg_mem(newval, mem_ptr),
7789 OpcP, OpcS,
7790 reg_mem(newval, mem_ptr),
7791 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7792 REX_reg_breg(res, res), // movzbl
7793 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7794 ins_pipe( pipe_cmpxchg );
7795 %}
7796
7797 instruct compareAndExchangeB(
7798 memory mem_ptr,
7799 rax_RegI oldval, rRegI newval,
7800 rFlagsReg cr)
7801 %{
7802 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7803 effect(KILL cr);
7804
7805 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7806 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7807 opcode(0x0F, 0xB0);
7808 ins_encode(lock_prefix,
7809 REX_breg_mem(newval, mem_ptr),
7810 OpcP, OpcS,
7811 reg_mem(newval, mem_ptr) // lock cmpxchg
7812 );
7813 ins_pipe( pipe_cmpxchg );
7814 %}
7815
7816 instruct compareAndExchangeS(
7817 memory mem_ptr,
7818 rax_RegI oldval, rRegI newval,
7819 rFlagsReg cr)
7820 %{
7821 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7822 effect(KILL cr);
7823
7824 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7825 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7826 opcode(0x0F, 0xB1);
7827 ins_encode(lock_prefix,
7828 SizePrefix,
7829 REX_reg_mem(newval, mem_ptr),
7830 OpcP, OpcS,
7831 reg_mem(newval, mem_ptr) // lock cmpxchg
7832 );
7833 ins_pipe( pipe_cmpxchg );
7834 %}
7835
7836 instruct compareAndExchangeI(
7837 memory mem_ptr,
7838 rax_RegI oldval, rRegI newval,
7839 rFlagsReg cr)
7840 %{
7841 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7842 effect(KILL cr);
7843
7844 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7845 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7846 opcode(0x0F, 0xB1);
7847 ins_encode(lock_prefix,
7848 REX_reg_mem(newval, mem_ptr),
7849 OpcP, OpcS,
7850 reg_mem(newval, mem_ptr) // lock cmpxchg
7851 );
7852 ins_pipe( pipe_cmpxchg );
7853 %}
7854
7855 instruct compareAndExchangeL(
7856 memory mem_ptr,
7857 rax_RegL oldval, rRegL newval,
7858 rFlagsReg cr)
7859 %{
7860 predicate(VM_Version::supports_cx8());
7861 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7862 effect(KILL cr);
7863
7864 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7865 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7866 opcode(0x0F, 0xB1);
7867 ins_encode(lock_prefix,
7868 REX_reg_mem_wide(newval, mem_ptr),
7869 OpcP, OpcS,
7870 reg_mem(newval, mem_ptr) // lock cmpxchg
7871 );
7872 ins_pipe( pipe_cmpxchg );
7873 %}
7874
7875 instruct compareAndExchangeN(
7876 memory mem_ptr,
7877 rax_RegN oldval, rRegN newval,
7878 rFlagsReg cr) %{
7879 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7880 effect(KILL cr);
7881
7882 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7883 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7884 opcode(0x0F, 0xB1);
7885 ins_encode(lock_prefix,
7886 REX_reg_mem(newval, mem_ptr),
7887 OpcP, OpcS,
7888 reg_mem(newval, mem_ptr) // lock cmpxchg
7889 );
7890 ins_pipe( pipe_cmpxchg );
7891 %}
7892
7893 instruct compareAndExchangeP(
7894 memory mem_ptr,
7895 rax_RegP oldval, rRegP newval,
7896 rFlagsReg cr)
7897 %{
7898 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7899 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7900 effect(KILL cr);
7901
7902 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7903 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7904 opcode(0x0F, 0xB1);
7905 ins_encode(lock_prefix,
7906 REX_reg_mem_wide(newval, mem_ptr),
7907 OpcP, OpcS,
7908 reg_mem(newval, mem_ptr) // lock cmpxchg
7909 );
7910 ins_pipe( pipe_cmpxchg );
7911 %}
7912
7913 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7914 predicate(n->as_LoadStore()->result_not_used());
7915 match(Set dummy (GetAndAddB mem add));
7916 effect(KILL cr);
7917 format %{ "ADDB [$mem],$add" %}
7918 ins_encode %{
7919 __ lock();
7920 __ addb($mem$$Address, $add$$constant);
7921 %}
7922 ins_pipe( pipe_cmpxchg );
7923 %}
7924
7925 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7926 match(Set newval (GetAndAddB mem newval));
7927 effect(KILL cr);
7928 format %{ "XADDB [$mem],$newval" %}
7929 ins_encode %{
7930 __ lock();
7931 __ xaddb($mem$$Address, $newval$$Register);
7932 %}
7933 ins_pipe( pipe_cmpxchg );
7934 %}
7935
7936 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7937 predicate(n->as_LoadStore()->result_not_used());
7938 match(Set dummy (GetAndAddS mem add));
7939 effect(KILL cr);
7940 format %{ "ADDW [$mem],$add" %}
7941 ins_encode %{
7942 __ lock();
7943 __ addw($mem$$Address, $add$$constant);
7944 %}
7945 ins_pipe( pipe_cmpxchg );
7946 %}
7947
7948 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7949 match(Set newval (GetAndAddS mem newval));
7950 effect(KILL cr);
7951 format %{ "XADDW [$mem],$newval" %}
7952 ins_encode %{
7953 __ lock();
7954 __ xaddw($mem$$Address, $newval$$Register);
7955 %}
7956 ins_pipe( pipe_cmpxchg );
7957 %}
7958
7959 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7960 predicate(n->as_LoadStore()->result_not_used());
7961 match(Set dummy (GetAndAddI mem add));
7962 effect(KILL cr);
7963 format %{ "ADDL [$mem],$add" %}
7964 ins_encode %{
7965 __ lock();
7966 __ addl($mem$$Address, $add$$constant);
7967 %}
7968 ins_pipe( pipe_cmpxchg );
7969 %}
7970
7971 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7972 match(Set newval (GetAndAddI mem newval));
7973 effect(KILL cr);
7974 format %{ "XADDL [$mem],$newval" %}
7975 ins_encode %{
7976 __ lock();
7977 __ xaddl($mem$$Address, $newval$$Register);
7978 %}
7979 ins_pipe( pipe_cmpxchg );
7980 %}
7981
7982 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7983 predicate(n->as_LoadStore()->result_not_used());
7984 match(Set dummy (GetAndAddL mem add));
7985 effect(KILL cr);
7986 format %{ "ADDQ [$mem],$add" %}
7987 ins_encode %{
7988 __ lock();
7989 __ addq($mem$$Address, $add$$constant);
7990 %}
7991 ins_pipe( pipe_cmpxchg );
7992 %}
7993
7994 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7995 match(Set newval (GetAndAddL mem newval));
7996 effect(KILL cr);
7997 format %{ "XADDQ [$mem],$newval" %}
7998 ins_encode %{
7999 __ lock();
8000 __ xaddq($mem$$Address, $newval$$Register);
8001 %}
8002 ins_pipe( pipe_cmpxchg );
8003 %}
8004
8005 instruct xchgB( memory mem, rRegI newval) %{
8006 match(Set newval (GetAndSetB mem newval));
8007 format %{ "XCHGB $newval,[$mem]" %}
8008 ins_encode %{
8009 __ xchgb($newval$$Register, $mem$$Address);
8010 %}
8011 ins_pipe( pipe_cmpxchg );
8012 %}
8013
8014 instruct xchgS( memory mem, rRegI newval) %{
8015 match(Set newval (GetAndSetS mem newval));
8016 format %{ "XCHGW $newval,[$mem]" %}
8017 ins_encode %{
8018 __ xchgw($newval$$Register, $mem$$Address);
8019 %}
8020 ins_pipe( pipe_cmpxchg );
8021 %}
8022
8023 instruct xchgI( memory mem, rRegI newval) %{
8024 match(Set newval (GetAndSetI mem newval));
8025 format %{ "XCHGL $newval,[$mem]" %}
8026 ins_encode %{
8027 __ xchgl($newval$$Register, $mem$$Address);
8028 %}
8029 ins_pipe( pipe_cmpxchg );
8030 %}
8031
8032 instruct xchgL( memory mem, rRegL newval) %{
8033 match(Set newval (GetAndSetL mem newval));
8034 format %{ "XCHGL $newval,[$mem]" %}
8035 ins_encode %{
8036 __ xchgq($newval$$Register, $mem$$Address);
8037 %}
8038 ins_pipe( pipe_cmpxchg );
8039 %}
8040
8041 instruct xchgP( memory mem, rRegP newval) %{
8042 match(Set newval (GetAndSetP mem newval));
8043 predicate(n->as_LoadStore()->barrier_data() == 0);
8044 format %{ "XCHGQ $newval,[$mem]" %}
8045 ins_encode %{
8046 __ xchgq($newval$$Register, $mem$$Address);
8047 %}
8048 ins_pipe( pipe_cmpxchg );
8049 %}
8050
8051 instruct xchgN( memory mem, rRegN newval) %{
8052 match(Set newval (GetAndSetN mem newval));
8053 format %{ "XCHGL $newval,$mem]" %}
8054 ins_encode %{
8055 __ xchgl($newval$$Register, $mem$$Address);
8056 %}
8057 ins_pipe( pipe_cmpxchg );
8058 %}
8059
8060 //----------Abs Instructions-------------------------------------------
8061
8062 // Integer Absolute Instructions
8063 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8064 %{
8065 match(Set dst (AbsI src));
8066 effect(TEMP dst, TEMP tmp, KILL cr);
8067 format %{ "movl $tmp, $src\n\t"
8068 "sarl $tmp, 31\n\t"
8069 "movl $dst, $src\n\t"
8070 "xorl $dst, $tmp\n\t"
8071 "subl $dst, $tmp\n"
8072 %}
8073 ins_encode %{
8074 __ movl($tmp$$Register, $src$$Register);
8075 __ sarl($tmp$$Register, 31);
8076 __ movl($dst$$Register, $src$$Register);
8077 __ xorl($dst$$Register, $tmp$$Register);
8078 __ subl($dst$$Register, $tmp$$Register);
8079 %}
8080
8081 ins_pipe(ialu_reg_reg);
8082 %}
8083
8084 // Long Absolute Instructions
8085 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8086 %{
8087 match(Set dst (AbsL src));
8088 effect(TEMP dst, TEMP tmp, KILL cr);
8089 format %{ "movq $tmp, $src\n\t"
8090 "sarq $tmp, 63\n\t"
8091 "movq $dst, $src\n\t"
8092 "xorq $dst, $tmp\n\t"
8093 "subq $dst, $tmp\n"
8094 %}
8095 ins_encode %{
8096 __ movq($tmp$$Register, $src$$Register);
8097 __ sarq($tmp$$Register, 63);
8098 __ movq($dst$$Register, $src$$Register);
8099 __ xorq($dst$$Register, $tmp$$Register);
8100 __ subq($dst$$Register, $tmp$$Register);
8101 %}
8102
8103 ins_pipe(ialu_reg_reg);
8104 %}
8105
8106 //----------Subtraction Instructions-------------------------------------------
8107
8108 // Integer Subtraction Instructions
8109 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8110 %{
8111 match(Set dst (SubI dst src));
8112 effect(KILL cr);
8113
8114 format %{ "subl $dst, $src\t# int" %}
8115 opcode(0x2B);
8116 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8117 ins_pipe(ialu_reg_reg);
8118 %}
8119
8120 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8121 %{
8122 match(Set dst (SubI dst src));
8123 effect(KILL cr);
8124
8125 format %{ "subl $dst, $src\t# int" %}
8126 opcode(0x81, 0x05); /* Opcode 81 /5 */
8127 ins_encode(OpcSErm(dst, src), Con8or32(src));
8128 ins_pipe(ialu_reg);
8129 %}
8130
8131 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8132 %{
8133 match(Set dst (SubI dst (LoadI src)));
8134 effect(KILL cr);
8135
8136 ins_cost(125);
8137 format %{ "subl $dst, $src\t# int" %}
8138 opcode(0x2B);
8139 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8140 ins_pipe(ialu_reg_mem);
8141 %}
8142
8143 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8144 %{
8145 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8146 effect(KILL cr);
8147
8148 ins_cost(150);
8149 format %{ "subl $dst, $src\t# int" %}
8150 opcode(0x29); /* Opcode 29 /r */
8151 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8152 ins_pipe(ialu_mem_reg);
8153 %}
8154
8155 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8156 %{
8157 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8158 effect(KILL cr);
8159
8160 ins_cost(125); // XXX
8161 format %{ "subl $dst, $src\t# int" %}
8162 opcode(0x81); /* Opcode 81 /5 id */
8163 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8164 ins_pipe(ialu_mem_imm);
8165 %}
8166
8167 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8168 %{
8169 match(Set dst (SubL dst src));
8170 effect(KILL cr);
8171
8172 format %{ "subq $dst, $src\t# long" %}
8173 opcode(0x2B);
8174 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8175 ins_pipe(ialu_reg_reg);
8176 %}
8177
8178 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8179 %{
8180 match(Set dst (SubL dst src));
8181 effect(KILL cr);
8182
8183 format %{ "subq $dst, $src\t# long" %}
8184 opcode(0x81, 0x05); /* Opcode 81 /5 */
8185 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8186 ins_pipe(ialu_reg);
8187 %}
8188
8189 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8190 %{
8191 match(Set dst (SubL dst (LoadL src)));
8192 effect(KILL cr);
8193
8194 ins_cost(125);
8195 format %{ "subq $dst, $src\t# long" %}
8196 opcode(0x2B);
8197 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8198 ins_pipe(ialu_reg_mem);
8199 %}
8200
8201 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8202 %{
8203 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8204 effect(KILL cr);
8205
8206 ins_cost(150);
8207 format %{ "subq $dst, $src\t# long" %}
8208 opcode(0x29); /* Opcode 29 /r */
8209 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8210 ins_pipe(ialu_mem_reg);
8211 %}
8212
8213 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8214 %{
8215 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8216 effect(KILL cr);
8217
8218 ins_cost(125); // XXX
8219 format %{ "subq $dst, $src\t# long" %}
8220 opcode(0x81); /* Opcode 81 /5 id */
8221 ins_encode(REX_mem_wide(dst),
8222 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8223 ins_pipe(ialu_mem_imm);
8224 %}
8225
8226 // Subtract from a pointer
8227 // XXX hmpf???
8228 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8229 %{
8230 match(Set dst (AddP dst (SubI zero src)));
8231 effect(KILL cr);
8232
8233 format %{ "subq $dst, $src\t# ptr - int" %}
8234 opcode(0x2B);
8235 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8236 ins_pipe(ialu_reg_reg);
8237 %}
8238
8239 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8240 %{
8241 match(Set dst (SubI zero dst));
8242 effect(KILL cr);
8243
8244 format %{ "negl $dst\t# int" %}
8245 opcode(0xF7, 0x03); // Opcode F7 /3
8246 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8247 ins_pipe(ialu_reg);
8248 %}
8249
8250 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8251 %{
8252 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8253 effect(KILL cr);
8254
8255 format %{ "negl $dst\t# int" %}
8256 opcode(0xF7, 0x03); // Opcode F7 /3
8257 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8258 ins_pipe(ialu_reg);
8259 %}
8260
8261 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8262 %{
8263 match(Set dst (SubL zero dst));
8264 effect(KILL cr);
8265
8266 format %{ "negq $dst\t# long" %}
8267 opcode(0xF7, 0x03); // Opcode F7 /3
8268 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8269 ins_pipe(ialu_reg);
8270 %}
8271
8272 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8273 %{
8274 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8275 effect(KILL cr);
8276
8277 format %{ "negq $dst\t# long" %}
8278 opcode(0xF7, 0x03); // Opcode F7 /3
8279 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8280 ins_pipe(ialu_reg);
8281 %}
8282
8283 //----------Multiplication/Division Instructions-------------------------------
8284 // Integer Multiplication Instructions
8285 // Multiply Register
8286
8287 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8288 %{
8289 match(Set dst (MulI dst src));
8290 effect(KILL cr);
8291
8292 ins_cost(300);
8293 format %{ "imull $dst, $src\t# int" %}
8294 opcode(0x0F, 0xAF);
8295 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8296 ins_pipe(ialu_reg_reg_alu0);
8297 %}
8298
8299 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8300 %{
8301 match(Set dst (MulI src imm));
8302 effect(KILL cr);
8303
8304 ins_cost(300);
8305 format %{ "imull $dst, $src, $imm\t# int" %}
8306 opcode(0x69); /* 69 /r id */
8307 ins_encode(REX_reg_reg(dst, src),
8308 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8309 ins_pipe(ialu_reg_reg_alu0);
8310 %}
8311
8312 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8313 %{
8314 match(Set dst (MulI dst (LoadI src)));
8315 effect(KILL cr);
8316
8317 ins_cost(350);
8318 format %{ "imull $dst, $src\t# int" %}
8319 opcode(0x0F, 0xAF);
8320 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8321 ins_pipe(ialu_reg_mem_alu0);
8322 %}
8323
8324 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8325 %{
8326 match(Set dst (MulI (LoadI src) imm));
8327 effect(KILL cr);
8328
8329 ins_cost(300);
8330 format %{ "imull $dst, $src, $imm\t# int" %}
8331 opcode(0x69); /* 69 /r id */
8332 ins_encode(REX_reg_mem(dst, src),
8333 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8334 ins_pipe(ialu_reg_mem_alu0);
8335 %}
8336
8337 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8338 %{
8339 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8340 effect(KILL cr, KILL src2);
8341
8342 expand %{ mulI_rReg(dst, src1, cr);
8343 mulI_rReg(src2, src3, cr);
8344 addI_rReg(dst, src2, cr); %}
8345 %}
8346
8347 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8348 %{
8349 match(Set dst (MulL dst src));
8350 effect(KILL cr);
8351
8352 ins_cost(300);
8353 format %{ "imulq $dst, $src\t# long" %}
8354 opcode(0x0F, 0xAF);
8355 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8356 ins_pipe(ialu_reg_reg_alu0);
8357 %}
8358
8359 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8360 %{
8361 match(Set dst (MulL src imm));
8362 effect(KILL cr);
8363
8364 ins_cost(300);
8365 format %{ "imulq $dst, $src, $imm\t# long" %}
8366 opcode(0x69); /* 69 /r id */
8367 ins_encode(REX_reg_reg_wide(dst, src),
8368 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8369 ins_pipe(ialu_reg_reg_alu0);
8370 %}
8371
8372 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8373 %{
8374 match(Set dst (MulL dst (LoadL src)));
8375 effect(KILL cr);
8376
8377 ins_cost(350);
8378 format %{ "imulq $dst, $src\t# long" %}
8379 opcode(0x0F, 0xAF);
8380 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8381 ins_pipe(ialu_reg_mem_alu0);
8382 %}
8383
8384 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8385 %{
8386 match(Set dst (MulL (LoadL src) imm));
8387 effect(KILL cr);
8388
8389 ins_cost(300);
8390 format %{ "imulq $dst, $src, $imm\t# long" %}
8391 opcode(0x69); /* 69 /r id */
8392 ins_encode(REX_reg_mem_wide(dst, src),
8393 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8394 ins_pipe(ialu_reg_mem_alu0);
8395 %}
8396
8397 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8398 %{
8399 match(Set dst (MulHiL src rax));
8400 effect(USE_KILL rax, KILL cr);
8401
8402 ins_cost(300);
8403 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8404 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8405 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8406 ins_pipe(ialu_reg_reg_alu0);
8407 %}
8408
8409 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8410 rFlagsReg cr)
8411 %{
8412 match(Set rax (DivI rax div));
8413 effect(KILL rdx, KILL cr);
8414
8415 ins_cost(30*100+10*100); // XXX
8416 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8417 "jne,s normal\n\t"
8418 "xorl rdx, rdx\n\t"
8419 "cmpl $div, -1\n\t"
8420 "je,s done\n"
8421 "normal: cdql\n\t"
8422 "idivl $div\n"
8423 "done:" %}
8424 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8425 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8426 ins_pipe(ialu_reg_reg_alu0);
8427 %}
8428
8429 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8430 rFlagsReg cr)
8431 %{
8432 match(Set rax (DivL rax div));
8433 effect(KILL rdx, KILL cr);
8434
8435 ins_cost(30*100+10*100); // XXX
8436 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8437 "cmpq rax, rdx\n\t"
8438 "jne,s normal\n\t"
8439 "xorl rdx, rdx\n\t"
8440 "cmpq $div, -1\n\t"
8441 "je,s done\n"
8442 "normal: cdqq\n\t"
8443 "idivq $div\n"
8444 "done:" %}
8445 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8446 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8447 ins_pipe(ialu_reg_reg_alu0);
8448 %}
8449
8450 // Integer DIVMOD with Register, both quotient and mod results
8451 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8452 rFlagsReg cr)
8453 %{
8454 match(DivModI rax div);
8455 effect(KILL cr);
8456
8457 ins_cost(30*100+10*100); // XXX
8458 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8459 "jne,s normal\n\t"
8460 "xorl rdx, rdx\n\t"
8461 "cmpl $div, -1\n\t"
8462 "je,s done\n"
8463 "normal: cdql\n\t"
8464 "idivl $div\n"
8465 "done:" %}
8466 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8467 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8468 ins_pipe(pipe_slow);
8469 %}
8470
8471 // Long DIVMOD with Register, both quotient and mod results
8472 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8473 rFlagsReg cr)
8474 %{
8475 match(DivModL rax div);
8476 effect(KILL cr);
8477
8478 ins_cost(30*100+10*100); // XXX
8479 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8480 "cmpq rax, rdx\n\t"
8481 "jne,s normal\n\t"
8482 "xorl rdx, rdx\n\t"
8483 "cmpq $div, -1\n\t"
8484 "je,s done\n"
8485 "normal: cdqq\n\t"
8486 "idivq $div\n"
8487 "done:" %}
8488 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8489 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8490 ins_pipe(pipe_slow);
8491 %}
8492
8493 //----------- DivL-By-Constant-Expansions--------------------------------------
8494 // DivI cases are handled by the compiler
8495
8496 // Magic constant, reciprocal of 10
8497 instruct loadConL_0x6666666666666667(rRegL dst)
8498 %{
8499 effect(DEF dst);
8500
8501 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8502 ins_encode(load_immL(dst, 0x6666666666666667));
8503 ins_pipe(ialu_reg);
8504 %}
8505
8506 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8507 %{
8508 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8509
8510 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8511 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8512 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8513 ins_pipe(ialu_reg_reg_alu0);
8514 %}
8515
8516 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8517 %{
8518 effect(USE_DEF dst, KILL cr);
8519
8520 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8521 opcode(0xC1, 0x7); /* C1 /7 ib */
8522 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8523 ins_pipe(ialu_reg);
8524 %}
8525
8526 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8527 %{
8528 effect(USE_DEF dst, KILL cr);
8529
8530 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8531 opcode(0xC1, 0x7); /* C1 /7 ib */
8532 ins_encode(reg_opc_imm_wide(dst, 0x2));
8533 ins_pipe(ialu_reg);
8534 %}
8535
8536 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8537 %{
8538 match(Set dst (DivL src div));
8539
8540 ins_cost((5+8)*100);
8541 expand %{
8542 rax_RegL rax; // Killed temp
8543 rFlagsReg cr; // Killed
8544 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8545 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8546 sarL_rReg_63(src, cr); // sarq src, 63
8547 sarL_rReg_2(dst, cr); // sarq rdx, 2
8548 subL_rReg(dst, src, cr); // subl rdx, src
8549 %}
8550 %}
8551
8552 //-----------------------------------------------------------------------------
8553
8554 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8555 rFlagsReg cr)
8556 %{
8557 match(Set rdx (ModI rax div));
8558 effect(KILL rax, KILL cr);
8559
8560 ins_cost(300); // XXX
8561 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8562 "jne,s normal\n\t"
8563 "xorl rdx, rdx\n\t"
8564 "cmpl $div, -1\n\t"
8565 "je,s done\n"
8566 "normal: cdql\n\t"
8567 "idivl $div\n"
8568 "done:" %}
8569 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8570 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8571 ins_pipe(ialu_reg_reg_alu0);
8572 %}
8573
8574 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8575 rFlagsReg cr)
8576 %{
8577 match(Set rdx (ModL rax div));
8578 effect(KILL rax, KILL cr);
8579
8580 ins_cost(300); // XXX
8581 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8582 "cmpq rax, rdx\n\t"
8583 "jne,s normal\n\t"
8584 "xorl rdx, rdx\n\t"
8585 "cmpq $div, -1\n\t"
8586 "je,s done\n"
8587 "normal: cdqq\n\t"
8588 "idivq $div\n"
8589 "done:" %}
8590 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8591 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8592 ins_pipe(ialu_reg_reg_alu0);
8593 %}
8594
8595 // Integer Shift Instructions
8596 // Shift Left by one
8597 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8598 %{
8599 match(Set dst (LShiftI dst shift));
8600 effect(KILL cr);
8601
8602 format %{ "sall $dst, $shift" %}
8603 opcode(0xD1, 0x4); /* D1 /4 */
8604 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8605 ins_pipe(ialu_reg);
8606 %}
8607
8608 // Shift Left by one
8609 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8610 %{
8611 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8612 effect(KILL cr);
8613
8614 format %{ "sall $dst, $shift\t" %}
8615 opcode(0xD1, 0x4); /* D1 /4 */
8616 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8617 ins_pipe(ialu_mem_imm);
8618 %}
8619
8620 // Shift Left by 8-bit immediate
8621 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8622 %{
8623 match(Set dst (LShiftI dst shift));
8624 effect(KILL cr);
8625
8626 format %{ "sall $dst, $shift" %}
8627 opcode(0xC1, 0x4); /* C1 /4 ib */
8628 ins_encode(reg_opc_imm(dst, shift));
8629 ins_pipe(ialu_reg);
8630 %}
8631
8632 // Shift Left by 8-bit immediate
8633 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8634 %{
8635 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8636 effect(KILL cr);
8637
8638 format %{ "sall $dst, $shift" %}
8639 opcode(0xC1, 0x4); /* C1 /4 ib */
8640 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8641 ins_pipe(ialu_mem_imm);
8642 %}
8643
8644 // Shift Left by variable
8645 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8646 %{
8647 match(Set dst (LShiftI dst shift));
8648 effect(KILL cr);
8649
8650 format %{ "sall $dst, $shift" %}
8651 opcode(0xD3, 0x4); /* D3 /4 */
8652 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8653 ins_pipe(ialu_reg_reg);
8654 %}
8655
8656 // Shift Left by variable
8657 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8658 %{
8659 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8660 effect(KILL cr);
8661
8662 format %{ "sall $dst, $shift" %}
8663 opcode(0xD3, 0x4); /* D3 /4 */
8664 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8665 ins_pipe(ialu_mem_reg);
8666 %}
8667
8668 // Arithmetic shift right by one
8669 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8670 %{
8671 match(Set dst (RShiftI dst shift));
8672 effect(KILL cr);
8673
8674 format %{ "sarl $dst, $shift" %}
8675 opcode(0xD1, 0x7); /* D1 /7 */
8676 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8677 ins_pipe(ialu_reg);
8678 %}
8679
8680 // Arithmetic shift right by one
8681 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8682 %{
8683 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8684 effect(KILL cr);
8685
8686 format %{ "sarl $dst, $shift" %}
8687 opcode(0xD1, 0x7); /* D1 /7 */
8688 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8689 ins_pipe(ialu_mem_imm);
8690 %}
8691
8692 // Arithmetic Shift Right by 8-bit immediate
8693 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8694 %{
8695 match(Set dst (RShiftI dst shift));
8696 effect(KILL cr);
8697
8698 format %{ "sarl $dst, $shift" %}
8699 opcode(0xC1, 0x7); /* C1 /7 ib */
8700 ins_encode(reg_opc_imm(dst, shift));
8701 ins_pipe(ialu_mem_imm);
8702 %}
8703
8704 // Arithmetic Shift Right by 8-bit immediate
8705 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8706 %{
8707 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8708 effect(KILL cr);
8709
8710 format %{ "sarl $dst, $shift" %}
8711 opcode(0xC1, 0x7); /* C1 /7 ib */
8712 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8713 ins_pipe(ialu_mem_imm);
8714 %}
8715
8716 // Arithmetic Shift Right by variable
8717 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8718 %{
8719 match(Set dst (RShiftI dst shift));
8720 effect(KILL cr);
8721
8722 format %{ "sarl $dst, $shift" %}
8723 opcode(0xD3, 0x7); /* D3 /7 */
8724 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8725 ins_pipe(ialu_reg_reg);
8726 %}
8727
8728 // Arithmetic Shift Right by variable
8729 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8730 %{
8731 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8732 effect(KILL cr);
8733
8734 format %{ "sarl $dst, $shift" %}
8735 opcode(0xD3, 0x7); /* D3 /7 */
8736 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8737 ins_pipe(ialu_mem_reg);
8738 %}
8739
8740 // Logical shift right by one
8741 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8742 %{
8743 match(Set dst (URShiftI dst shift));
8744 effect(KILL cr);
8745
8746 format %{ "shrl $dst, $shift" %}
8747 opcode(0xD1, 0x5); /* D1 /5 */
8748 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8749 ins_pipe(ialu_reg);
8750 %}
8751
8752 // Logical shift right by one
8753 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8754 %{
8755 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8756 effect(KILL cr);
8757
8758 format %{ "shrl $dst, $shift" %}
8759 opcode(0xD1, 0x5); /* D1 /5 */
8760 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8761 ins_pipe(ialu_mem_imm);
8762 %}
8763
8764 // Logical Shift Right by 8-bit immediate
8765 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8766 %{
8767 match(Set dst (URShiftI dst shift));
8768 effect(KILL cr);
8769
8770 format %{ "shrl $dst, $shift" %}
8771 opcode(0xC1, 0x5); /* C1 /5 ib */
8772 ins_encode(reg_opc_imm(dst, shift));
8773 ins_pipe(ialu_reg);
8774 %}
8775
8776 // Logical Shift Right by 8-bit immediate
8777 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8778 %{
8779 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8780 effect(KILL cr);
8781
8782 format %{ "shrl $dst, $shift" %}
8783 opcode(0xC1, 0x5); /* C1 /5 ib */
8784 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8785 ins_pipe(ialu_mem_imm);
8786 %}
8787
8788 // Logical Shift Right by variable
8789 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8790 %{
8791 match(Set dst (URShiftI dst shift));
8792 effect(KILL cr);
8793
8794 format %{ "shrl $dst, $shift" %}
8795 opcode(0xD3, 0x5); /* D3 /5 */
8796 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8797 ins_pipe(ialu_reg_reg);
8798 %}
8799
8800 // Logical Shift Right by variable
8801 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8802 %{
8803 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8804 effect(KILL cr);
8805
8806 format %{ "shrl $dst, $shift" %}
8807 opcode(0xD3, 0x5); /* D3 /5 */
8808 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8809 ins_pipe(ialu_mem_reg);
8810 %}
8811
8812 // Long Shift Instructions
8813 // Shift Left by one
8814 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8815 %{
8816 match(Set dst (LShiftL dst shift));
8817 effect(KILL cr);
8818
8819 format %{ "salq $dst, $shift" %}
8820 opcode(0xD1, 0x4); /* D1 /4 */
8821 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8822 ins_pipe(ialu_reg);
8823 %}
8824
8825 // Shift Left by one
8826 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8827 %{
8828 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8829 effect(KILL cr);
8830
8831 format %{ "salq $dst, $shift" %}
8832 opcode(0xD1, 0x4); /* D1 /4 */
8833 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8834 ins_pipe(ialu_mem_imm);
8835 %}
8836
8837 // Shift Left by 8-bit immediate
8838 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8839 %{
8840 match(Set dst (LShiftL dst shift));
8841 effect(KILL cr);
8842
8843 format %{ "salq $dst, $shift" %}
8844 opcode(0xC1, 0x4); /* C1 /4 ib */
8845 ins_encode(reg_opc_imm_wide(dst, shift));
8846 ins_pipe(ialu_reg);
8847 %}
8848
8849 // Shift Left by 8-bit immediate
8850 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8851 %{
8852 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8853 effect(KILL cr);
8854
8855 format %{ "salq $dst, $shift" %}
8856 opcode(0xC1, 0x4); /* C1 /4 ib */
8857 ins_encode(REX_mem_wide(dst), OpcP,
8858 RM_opc_mem(secondary, dst), Con8or32(shift));
8859 ins_pipe(ialu_mem_imm);
8860 %}
8861
8862 // Shift Left by variable
8863 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8864 %{
8865 match(Set dst (LShiftL dst shift));
8866 effect(KILL cr);
8867
8868 format %{ "salq $dst, $shift" %}
8869 opcode(0xD3, 0x4); /* D3 /4 */
8870 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8871 ins_pipe(ialu_reg_reg);
8872 %}
8873
8874 // Shift Left by variable
8875 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8876 %{
8877 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8878 effect(KILL cr);
8879
8880 format %{ "salq $dst, $shift" %}
8881 opcode(0xD3, 0x4); /* D3 /4 */
8882 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8883 ins_pipe(ialu_mem_reg);
8884 %}
8885
8886 // Arithmetic shift right by one
8887 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8888 %{
8889 match(Set dst (RShiftL dst shift));
8890 effect(KILL cr);
8891
8892 format %{ "sarq $dst, $shift" %}
8893 opcode(0xD1, 0x7); /* D1 /7 */
8894 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8895 ins_pipe(ialu_reg);
8896 %}
8897
8898 // Arithmetic shift right by one
8899 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8900 %{
8901 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8902 effect(KILL cr);
8903
8904 format %{ "sarq $dst, $shift" %}
8905 opcode(0xD1, 0x7); /* D1 /7 */
8906 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8907 ins_pipe(ialu_mem_imm);
8908 %}
8909
8910 // Arithmetic Shift Right by 8-bit immediate
8911 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8912 %{
8913 match(Set dst (RShiftL dst shift));
8914 effect(KILL cr);
8915
8916 format %{ "sarq $dst, $shift" %}
8917 opcode(0xC1, 0x7); /* C1 /7 ib */
8918 ins_encode(reg_opc_imm_wide(dst, shift));
8919 ins_pipe(ialu_mem_imm);
8920 %}
8921
8922 // Arithmetic Shift Right by 8-bit immediate
8923 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8924 %{
8925 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8926 effect(KILL cr);
8927
8928 format %{ "sarq $dst, $shift" %}
8929 opcode(0xC1, 0x7); /* C1 /7 ib */
8930 ins_encode(REX_mem_wide(dst), OpcP,
8931 RM_opc_mem(secondary, dst), Con8or32(shift));
8932 ins_pipe(ialu_mem_imm);
8933 %}
8934
8935 // Arithmetic Shift Right by variable
8936 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8937 %{
8938 match(Set dst (RShiftL dst shift));
8939 effect(KILL cr);
8940
8941 format %{ "sarq $dst, $shift" %}
8942 opcode(0xD3, 0x7); /* D3 /7 */
8943 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8944 ins_pipe(ialu_reg_reg);
8945 %}
8946
8947 // Arithmetic Shift Right by variable
8948 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8949 %{
8950 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8951 effect(KILL cr);
8952
8953 format %{ "sarq $dst, $shift" %}
8954 opcode(0xD3, 0x7); /* D3 /7 */
8955 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8956 ins_pipe(ialu_mem_reg);
8957 %}
8958
8959 // Logical shift right by one
8960 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8961 %{
8962 match(Set dst (URShiftL dst shift));
8963 effect(KILL cr);
8964
8965 format %{ "shrq $dst, $shift" %}
8966 opcode(0xD1, 0x5); /* D1 /5 */
8967 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8968 ins_pipe(ialu_reg);
8969 %}
8970
8971 // Logical shift right by one
8972 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8973 %{
8974 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8975 effect(KILL cr);
8976
8977 format %{ "shrq $dst, $shift" %}
8978 opcode(0xD1, 0x5); /* D1 /5 */
8979 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8980 ins_pipe(ialu_mem_imm);
8981 %}
8982
8983 // Logical Shift Right by 8-bit immediate
8984 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8985 %{
8986 match(Set dst (URShiftL dst shift));
8987 effect(KILL cr);
8988
8989 format %{ "shrq $dst, $shift" %}
8990 opcode(0xC1, 0x5); /* C1 /5 ib */
8991 ins_encode(reg_opc_imm_wide(dst, shift));
8992 ins_pipe(ialu_reg);
8993 %}
8994
8995
8996 // Logical Shift Right by 8-bit immediate
8997 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8998 %{
8999 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9000 effect(KILL cr);
9001
9002 format %{ "shrq $dst, $shift" %}
9003 opcode(0xC1, 0x5); /* C1 /5 ib */
9004 ins_encode(REX_mem_wide(dst), OpcP,
9005 RM_opc_mem(secondary, dst), Con8or32(shift));
9006 ins_pipe(ialu_mem_imm);
9007 %}
9008
9009 // Logical Shift Right by variable
9010 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9011 %{
9012 match(Set dst (URShiftL dst shift));
9013 effect(KILL cr);
9014
9015 format %{ "shrq $dst, $shift" %}
9016 opcode(0xD3, 0x5); /* D3 /5 */
9017 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9018 ins_pipe(ialu_reg_reg);
9019 %}
9020
9021 // Logical Shift Right by variable
9022 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9023 %{
9024 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9025 effect(KILL cr);
9026
9027 format %{ "shrq $dst, $shift" %}
9028 opcode(0xD3, 0x5); /* D3 /5 */
9029 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9030 ins_pipe(ialu_mem_reg);
9031 %}
9032
9033 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9034 // This idiom is used by the compiler for the i2b bytecode.
9035 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9036 %{
9037 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9038
9039 format %{ "movsbl $dst, $src\t# i2b" %}
9040 opcode(0x0F, 0xBE);
9041 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9042 ins_pipe(ialu_reg_reg);
9043 %}
9044
9045 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9046 // This idiom is used by the compiler the i2s bytecode.
9047 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9048 %{
9049 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9050
9051 format %{ "movswl $dst, $src\t# i2s" %}
9052 opcode(0x0F, 0xBF);
9053 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9054 ins_pipe(ialu_reg_reg);
9055 %}
9056
9057 // ROL/ROR instructions
9058
9059 // ROL expand
9060 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9061 effect(KILL cr, USE_DEF dst);
9062
9063 format %{ "roll $dst" %}
9064 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9065 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9066 ins_pipe(ialu_reg);
9067 %}
9068
9069 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9070 effect(USE_DEF dst, USE shift, KILL cr);
9071
9072 format %{ "roll $dst, $shift" %}
9073 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9074 ins_encode( reg_opc_imm(dst, shift) );
9075 ins_pipe(ialu_reg);
9076 %}
9077
9078 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9079 %{
9080 effect(USE_DEF dst, USE shift, KILL cr);
9081
9082 format %{ "roll $dst, $shift" %}
9083 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9084 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9085 ins_pipe(ialu_reg_reg);
9086 %}
9087 // end of ROL expand
9088
9089 // Rotate Left by one
9090 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9091 %{
9092 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9093
9094 expand %{
9095 rolI_rReg_imm1(dst, cr);
9096 %}
9097 %}
9098
9099 // Rotate Left by 8-bit immediate
9100 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9101 %{
9102 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9103 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9104
9105 expand %{
9106 rolI_rReg_imm8(dst, lshift, cr);
9107 %}
9108 %}
9109
9110 // Rotate Left by variable
9111 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9112 %{
9113 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9114
9115 expand %{
9116 rolI_rReg_CL(dst, shift, cr);
9117 %}
9118 %}
9119
9120 // Rotate Left by variable
9121 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9122 %{
9123 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9124
9125 expand %{
9126 rolI_rReg_CL(dst, shift, cr);
9127 %}
9128 %}
9129
9130 // ROR expand
9131 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9132 %{
9133 effect(USE_DEF dst, KILL cr);
9134
9135 format %{ "rorl $dst" %}
9136 opcode(0xD1, 0x1); /* D1 /1 */
9137 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9138 ins_pipe(ialu_reg);
9139 %}
9140
9141 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9142 %{
9143 effect(USE_DEF dst, USE shift, KILL cr);
9144
9145 format %{ "rorl $dst, $shift" %}
9146 opcode(0xC1, 0x1); /* C1 /1 ib */
9147 ins_encode(reg_opc_imm(dst, shift));
9148 ins_pipe(ialu_reg);
9149 %}
9150
9151 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9152 %{
9153 effect(USE_DEF dst, USE shift, KILL cr);
9154
9155 format %{ "rorl $dst, $shift" %}
9156 opcode(0xD3, 0x1); /* D3 /1 */
9157 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9158 ins_pipe(ialu_reg_reg);
9159 %}
9160 // end of ROR expand
9161
9162 // Rotate Right by one
9163 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9164 %{
9165 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9166
9167 expand %{
9168 rorI_rReg_imm1(dst, cr);
9169 %}
9170 %}
9171
9172 // Rotate Right by 8-bit immediate
9173 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9174 %{
9175 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9176 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9177
9178 expand %{
9179 rorI_rReg_imm8(dst, rshift, cr);
9180 %}
9181 %}
9182
9183 // Rotate Right by variable
9184 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9185 %{
9186 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9187
9188 expand %{
9189 rorI_rReg_CL(dst, shift, cr);
9190 %}
9191 %}
9192
9193 // Rotate Right by variable
9194 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9195 %{
9196 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9197
9198 expand %{
9199 rorI_rReg_CL(dst, shift, cr);
9200 %}
9201 %}
9202
9203 // for long rotate
9204 // ROL expand
9205 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9206 effect(USE_DEF dst, KILL cr);
9207
9208 format %{ "rolq $dst" %}
9209 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9210 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9211 ins_pipe(ialu_reg);
9212 %}
9213
9214 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9215 effect(USE_DEF dst, USE shift, KILL cr);
9216
9217 format %{ "rolq $dst, $shift" %}
9218 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9219 ins_encode( reg_opc_imm_wide(dst, shift) );
9220 ins_pipe(ialu_reg);
9221 %}
9222
9223 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9224 %{
9225 effect(USE_DEF dst, USE shift, KILL cr);
9226
9227 format %{ "rolq $dst, $shift" %}
9228 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9229 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9230 ins_pipe(ialu_reg_reg);
9231 %}
9232 // end of ROL expand
9233
9234 // Rotate Left by one
9235 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9236 %{
9237 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9238
9239 expand %{
9240 rolL_rReg_imm1(dst, cr);
9241 %}
9242 %}
9243
9244 // Rotate Left by 8-bit immediate
9245 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9246 %{
9247 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9248 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9249
9250 expand %{
9251 rolL_rReg_imm8(dst, lshift, cr);
9252 %}
9253 %}
9254
9255 // Rotate Left by variable
9256 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9257 %{
9258 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9259
9260 expand %{
9261 rolL_rReg_CL(dst, shift, cr);
9262 %}
9263 %}
9264
9265 // Rotate Left by variable
9266 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9267 %{
9268 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9269
9270 expand %{
9271 rolL_rReg_CL(dst, shift, cr);
9272 %}
9273 %}
9274
9275 // ROR expand
9276 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9277 %{
9278 effect(USE_DEF dst, KILL cr);
9279
9280 format %{ "rorq $dst" %}
9281 opcode(0xD1, 0x1); /* D1 /1 */
9282 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9283 ins_pipe(ialu_reg);
9284 %}
9285
9286 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9287 %{
9288 effect(USE_DEF dst, USE shift, KILL cr);
9289
9290 format %{ "rorq $dst, $shift" %}
9291 opcode(0xC1, 0x1); /* C1 /1 ib */
9292 ins_encode(reg_opc_imm_wide(dst, shift));
9293 ins_pipe(ialu_reg);
9294 %}
9295
9296 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9297 %{
9298 effect(USE_DEF dst, USE shift, KILL cr);
9299
9300 format %{ "rorq $dst, $shift" %}
9301 opcode(0xD3, 0x1); /* D3 /1 */
9302 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9303 ins_pipe(ialu_reg_reg);
9304 %}
9305 // end of ROR expand
9306
9307 // Rotate Right by one
9308 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9309 %{
9310 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9311
9312 expand %{
9313 rorL_rReg_imm1(dst, cr);
9314 %}
9315 %}
9316
9317 // Rotate Right by 8-bit immediate
9318 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9319 %{
9320 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9321 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9322
9323 expand %{
9324 rorL_rReg_imm8(dst, rshift, cr);
9325 %}
9326 %}
9327
9328 // Rotate Right by variable
9329 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9330 %{
9331 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9332
9333 expand %{
9334 rorL_rReg_CL(dst, shift, cr);
9335 %}
9336 %}
9337
9338 // Rotate Right by variable
9339 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9340 %{
9341 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9342
9343 expand %{
9344 rorL_rReg_CL(dst, shift, cr);
9345 %}
9346 %}
9347
9348 // Logical Instructions
9349
9350 // Integer Logical Instructions
9351
9352 // And Instructions
9353 // And Register with Register
9354 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9355 %{
9356 match(Set dst (AndI dst src));
9357 effect(KILL cr);
9358
9359 format %{ "andl $dst, $src\t# int" %}
9360 opcode(0x23);
9361 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9362 ins_pipe(ialu_reg_reg);
9363 %}
9364
9365 // And Register with Immediate 255
9366 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9367 %{
9368 match(Set dst (AndI dst src));
9369
9370 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9371 opcode(0x0F, 0xB6);
9372 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9373 ins_pipe(ialu_reg);
9374 %}
9375
9376 // And Register with Immediate 255 and promote to long
9377 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9378 %{
9379 match(Set dst (ConvI2L (AndI src mask)));
9380
9381 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9382 opcode(0x0F, 0xB6);
9383 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9384 ins_pipe(ialu_reg);
9385 %}
9386
9387 // And Register with Immediate 65535
9388 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9389 %{
9390 match(Set dst (AndI dst src));
9391
9392 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9393 opcode(0x0F, 0xB7);
9394 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9395 ins_pipe(ialu_reg);
9396 %}
9397
9398 // And Register with Immediate 65535 and promote to long
9399 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9400 %{
9401 match(Set dst (ConvI2L (AndI src mask)));
9402
9403 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9404 opcode(0x0F, 0xB7);
9405 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9406 ins_pipe(ialu_reg);
9407 %}
9408
9409 // And Register with Immediate
9410 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9411 %{
9412 match(Set dst (AndI dst src));
9413 effect(KILL cr);
9414
9415 format %{ "andl $dst, $src\t# int" %}
9416 opcode(0x81, 0x04); /* Opcode 81 /4 */
9417 ins_encode(OpcSErm(dst, src), Con8or32(src));
9418 ins_pipe(ialu_reg);
9419 %}
9420
9421 // And Register with Memory
9422 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9423 %{
9424 match(Set dst (AndI dst (LoadI src)));
9425 effect(KILL cr);
9426
9427 ins_cost(125);
9428 format %{ "andl $dst, $src\t# int" %}
9429 opcode(0x23);
9430 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9431 ins_pipe(ialu_reg_mem);
9432 %}
9433
9434 // And Memory with Register
9435 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9436 %{
9437 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9438 effect(KILL cr);
9439
9440 ins_cost(150);
9441 format %{ "andb $dst, $src\t# byte" %}
9442 opcode(0x20);
9443 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9444 ins_pipe(ialu_mem_reg);
9445 %}
9446
9447 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9448 %{
9449 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9450 effect(KILL cr);
9451
9452 ins_cost(150);
9453 format %{ "andl $dst, $src\t# int" %}
9454 opcode(0x21); /* Opcode 21 /r */
9455 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9456 ins_pipe(ialu_mem_reg);
9457 %}
9458
9459 // And Memory with Immediate
9460 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9461 %{
9462 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9463 effect(KILL cr);
9464
9465 ins_cost(125);
9466 format %{ "andl $dst, $src\t# int" %}
9467 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9468 ins_encode(REX_mem(dst), OpcSE(src),
9469 RM_opc_mem(secondary, dst), Con8or32(src));
9470 ins_pipe(ialu_mem_imm);
9471 %}
9472
9473 // BMI1 instructions
9474 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9475 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9476 predicate(UseBMI1Instructions);
9477 effect(KILL cr);
9478
9479 ins_cost(125);
9480 format %{ "andnl $dst, $src1, $src2" %}
9481
9482 ins_encode %{
9483 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9484 %}
9485 ins_pipe(ialu_reg_mem);
9486 %}
9487
9488 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9489 match(Set dst (AndI (XorI src1 minus_1) src2));
9490 predicate(UseBMI1Instructions);
9491 effect(KILL cr);
9492
9493 format %{ "andnl $dst, $src1, $src2" %}
9494
9495 ins_encode %{
9496 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9497 %}
9498 ins_pipe(ialu_reg);
9499 %}
9500
9501 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9502 match(Set dst (AndI (SubI imm_zero src) src));
9503 predicate(UseBMI1Instructions);
9504 effect(KILL cr);
9505
9506 format %{ "blsil $dst, $src" %}
9507
9508 ins_encode %{
9509 __ blsil($dst$$Register, $src$$Register);
9510 %}
9511 ins_pipe(ialu_reg);
9512 %}
9513
9514 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9515 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9516 predicate(UseBMI1Instructions);
9517 effect(KILL cr);
9518
9519 ins_cost(125);
9520 format %{ "blsil $dst, $src" %}
9521
9522 ins_encode %{
9523 __ blsil($dst$$Register, $src$$Address);
9524 %}
9525 ins_pipe(ialu_reg_mem);
9526 %}
9527
9528 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9529 %{
9530 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9531 predicate(UseBMI1Instructions);
9532 effect(KILL cr);
9533
9534 ins_cost(125);
9535 format %{ "blsmskl $dst, $src" %}
9536
9537 ins_encode %{
9538 __ blsmskl($dst$$Register, $src$$Address);
9539 %}
9540 ins_pipe(ialu_reg_mem);
9541 %}
9542
9543 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9544 %{
9545 match(Set dst (XorI (AddI src minus_1) src));
9546 predicate(UseBMI1Instructions);
9547 effect(KILL cr);
9548
9549 format %{ "blsmskl $dst, $src" %}
9550
9551 ins_encode %{
9552 __ blsmskl($dst$$Register, $src$$Register);
9553 %}
9554
9555 ins_pipe(ialu_reg);
9556 %}
9557
9558 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9559 %{
9560 match(Set dst (AndI (AddI src minus_1) src) );
9561 predicate(UseBMI1Instructions);
9562 effect(KILL cr);
9563
9564 format %{ "blsrl $dst, $src" %}
9565
9566 ins_encode %{
9567 __ blsrl($dst$$Register, $src$$Register);
9568 %}
9569
9570 ins_pipe(ialu_reg_mem);
9571 %}
9572
9573 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9574 %{
9575 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9576 predicate(UseBMI1Instructions);
9577 effect(KILL cr);
9578
9579 ins_cost(125);
9580 format %{ "blsrl $dst, $src" %}
9581
9582 ins_encode %{
9583 __ blsrl($dst$$Register, $src$$Address);
9584 %}
9585
9586 ins_pipe(ialu_reg);
9587 %}
9588
9589 // Or Instructions
9590 // Or Register with Register
9591 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9592 %{
9593 match(Set dst (OrI dst src));
9594 effect(KILL cr);
9595
9596 format %{ "orl $dst, $src\t# int" %}
9597 opcode(0x0B);
9598 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9599 ins_pipe(ialu_reg_reg);
9600 %}
9601
9602 // Or Register with Immediate
9603 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9604 %{
9605 match(Set dst (OrI dst src));
9606 effect(KILL cr);
9607
9608 format %{ "orl $dst, $src\t# int" %}
9609 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9610 ins_encode(OpcSErm(dst, src), Con8or32(src));
9611 ins_pipe(ialu_reg);
9612 %}
9613
9614 // Or Register with Memory
9615 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9616 %{
9617 match(Set dst (OrI dst (LoadI src)));
9618 effect(KILL cr);
9619
9620 ins_cost(125);
9621 format %{ "orl $dst, $src\t# int" %}
9622 opcode(0x0B);
9623 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9624 ins_pipe(ialu_reg_mem);
9625 %}
9626
9627 // Or Memory with Register
9628 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9629 %{
9630 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9631 effect(KILL cr);
9632
9633 ins_cost(150);
9634 format %{ "orb $dst, $src\t# byte" %}
9635 opcode(0x08);
9636 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9637 ins_pipe(ialu_mem_reg);
9638 %}
9639
9640 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9641 %{
9642 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9643 effect(KILL cr);
9644
9645 ins_cost(150);
9646 format %{ "orl $dst, $src\t# int" %}
9647 opcode(0x09); /* Opcode 09 /r */
9648 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9649 ins_pipe(ialu_mem_reg);
9650 %}
9651
9652 // Or Memory with Immediate
9653 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9654 %{
9655 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9656 effect(KILL cr);
9657
9658 ins_cost(125);
9659 format %{ "orl $dst, $src\t# int" %}
9660 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9661 ins_encode(REX_mem(dst), OpcSE(src),
9662 RM_opc_mem(secondary, dst), Con8or32(src));
9663 ins_pipe(ialu_mem_imm);
9664 %}
9665
9666 // Xor Instructions
9667 // Xor Register with Register
9668 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9669 %{
9670 match(Set dst (XorI dst src));
9671 effect(KILL cr);
9672
9673 format %{ "xorl $dst, $src\t# int" %}
9674 opcode(0x33);
9675 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9676 ins_pipe(ialu_reg_reg);
9677 %}
9678
9679 // Xor Register with Immediate -1
9680 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9681 match(Set dst (XorI dst imm));
9682
9683 format %{ "not $dst" %}
9684 ins_encode %{
9685 __ notl($dst$$Register);
9686 %}
9687 ins_pipe(ialu_reg);
9688 %}
9689
9690 // Xor Register with Immediate
9691 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9692 %{
9693 match(Set dst (XorI dst src));
9694 effect(KILL cr);
9695
9696 format %{ "xorl $dst, $src\t# int" %}
9697 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9698 ins_encode(OpcSErm(dst, src), Con8or32(src));
9699 ins_pipe(ialu_reg);
9700 %}
9701
9702 // Xor Register with Memory
9703 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9704 %{
9705 match(Set dst (XorI dst (LoadI src)));
9706 effect(KILL cr);
9707
9708 ins_cost(125);
9709 format %{ "xorl $dst, $src\t# int" %}
9710 opcode(0x33);
9711 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9712 ins_pipe(ialu_reg_mem);
9713 %}
9714
9715 // Xor Memory with Register
9716 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9717 %{
9718 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9719 effect(KILL cr);
9720
9721 ins_cost(150);
9722 format %{ "xorb $dst, $src\t# byte" %}
9723 opcode(0x30);
9724 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9725 ins_pipe(ialu_mem_reg);
9726 %}
9727
9728 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9729 %{
9730 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9731 effect(KILL cr);
9732
9733 ins_cost(150);
9734 format %{ "xorl $dst, $src\t# int" %}
9735 opcode(0x31); /* Opcode 31 /r */
9736 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9737 ins_pipe(ialu_mem_reg);
9738 %}
9739
9740 // Xor Memory with Immediate
9741 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9742 %{
9743 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9744 effect(KILL cr);
9745
9746 ins_cost(125);
9747 format %{ "xorl $dst, $src\t# int" %}
9748 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9749 ins_encode(REX_mem(dst), OpcSE(src),
9750 RM_opc_mem(secondary, dst), Con8or32(src));
9751 ins_pipe(ialu_mem_imm);
9752 %}
9753
9754
9755 // Long Logical Instructions
9756
9757 // And Instructions
9758 // And Register with Register
9759 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9760 %{
9761 match(Set dst (AndL dst src));
9762 effect(KILL cr);
9763
9764 format %{ "andq $dst, $src\t# long" %}
9765 opcode(0x23);
9766 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9767 ins_pipe(ialu_reg_reg);
9768 %}
9769
9770 // And Register with Immediate 255
9771 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9772 %{
9773 match(Set dst (AndL dst src));
9774
9775 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9776 opcode(0x0F, 0xB6);
9777 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9778 ins_pipe(ialu_reg);
9779 %}
9780
9781 // And Register with Immediate 65535
9782 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9783 %{
9784 match(Set dst (AndL dst src));
9785
9786 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9787 opcode(0x0F, 0xB7);
9788 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9789 ins_pipe(ialu_reg);
9790 %}
9791
9792 // And Register with Immediate
9793 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9794 %{
9795 match(Set dst (AndL dst src));
9796 effect(KILL cr);
9797
9798 format %{ "andq $dst, $src\t# long" %}
9799 opcode(0x81, 0x04); /* Opcode 81 /4 */
9800 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9801 ins_pipe(ialu_reg);
9802 %}
9803
9804 // And Register with Memory
9805 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9806 %{
9807 match(Set dst (AndL dst (LoadL src)));
9808 effect(KILL cr);
9809
9810 ins_cost(125);
9811 format %{ "andq $dst, $src\t# long" %}
9812 opcode(0x23);
9813 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9814 ins_pipe(ialu_reg_mem);
9815 %}
9816
9817 // And Memory with Register
9818 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9819 %{
9820 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9821 effect(KILL cr);
9822
9823 ins_cost(150);
9824 format %{ "andq $dst, $src\t# long" %}
9825 opcode(0x21); /* Opcode 21 /r */
9826 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9827 ins_pipe(ialu_mem_reg);
9828 %}
9829
9830 // And Memory with Immediate
9831 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9832 %{
9833 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9834 effect(KILL cr);
9835
9836 ins_cost(125);
9837 format %{ "andq $dst, $src\t# long" %}
9838 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9839 ins_encode(REX_mem_wide(dst), OpcSE(src),
9840 RM_opc_mem(secondary, dst), Con8or32(src));
9841 ins_pipe(ialu_mem_imm);
9842 %}
9843
9844 // BMI1 instructions
9845 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9846 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9847 predicate(UseBMI1Instructions);
9848 effect(KILL cr);
9849
9850 ins_cost(125);
9851 format %{ "andnq $dst, $src1, $src2" %}
9852
9853 ins_encode %{
9854 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9855 %}
9856 ins_pipe(ialu_reg_mem);
9857 %}
9858
9859 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9860 match(Set dst (AndL (XorL src1 minus_1) src2));
9861 predicate(UseBMI1Instructions);
9862 effect(KILL cr);
9863
9864 format %{ "andnq $dst, $src1, $src2" %}
9865
9866 ins_encode %{
9867 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9868 %}
9869 ins_pipe(ialu_reg_mem);
9870 %}
9871
9872 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9873 match(Set dst (AndL (SubL imm_zero src) src));
9874 predicate(UseBMI1Instructions);
9875 effect(KILL cr);
9876
9877 format %{ "blsiq $dst, $src" %}
9878
9879 ins_encode %{
9880 __ blsiq($dst$$Register, $src$$Register);
9881 %}
9882 ins_pipe(ialu_reg);
9883 %}
9884
9885 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9886 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9887 predicate(UseBMI1Instructions);
9888 effect(KILL cr);
9889
9890 ins_cost(125);
9891 format %{ "blsiq $dst, $src" %}
9892
9893 ins_encode %{
9894 __ blsiq($dst$$Register, $src$$Address);
9895 %}
9896 ins_pipe(ialu_reg_mem);
9897 %}
9898
9899 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9900 %{
9901 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9902 predicate(UseBMI1Instructions);
9903 effect(KILL cr);
9904
9905 ins_cost(125);
9906 format %{ "blsmskq $dst, $src" %}
9907
9908 ins_encode %{
9909 __ blsmskq($dst$$Register, $src$$Address);
9910 %}
9911 ins_pipe(ialu_reg_mem);
9912 %}
9913
9914 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9915 %{
9916 match(Set dst (XorL (AddL src minus_1) src));
9917 predicate(UseBMI1Instructions);
9918 effect(KILL cr);
9919
9920 format %{ "blsmskq $dst, $src" %}
9921
9922 ins_encode %{
9923 __ blsmskq($dst$$Register, $src$$Register);
9924 %}
9925
9926 ins_pipe(ialu_reg);
9927 %}
9928
9929 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9930 %{
9931 match(Set dst (AndL (AddL src minus_1) src) );
9932 predicate(UseBMI1Instructions);
9933 effect(KILL cr);
9934
9935 format %{ "blsrq $dst, $src" %}
9936
9937 ins_encode %{
9938 __ blsrq($dst$$Register, $src$$Register);
9939 %}
9940
9941 ins_pipe(ialu_reg);
9942 %}
9943
9944 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9945 %{
9946 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9947 predicate(UseBMI1Instructions);
9948 effect(KILL cr);
9949
9950 ins_cost(125);
9951 format %{ "blsrq $dst, $src" %}
9952
9953 ins_encode %{
9954 __ blsrq($dst$$Register, $src$$Address);
9955 %}
9956
9957 ins_pipe(ialu_reg);
9958 %}
9959
9960 // Or Instructions
9961 // Or Register with Register
9962 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9963 %{
9964 match(Set dst (OrL dst src));
9965 effect(KILL cr);
9966
9967 format %{ "orq $dst, $src\t# long" %}
9968 opcode(0x0B);
9969 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9970 ins_pipe(ialu_reg_reg);
9971 %}
9972
9973 // Use any_RegP to match R15 (TLS register) without spilling.
9974 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9975 match(Set dst (OrL dst (CastP2X src)));
9976 effect(KILL cr);
9977
9978 format %{ "orq $dst, $src\t# long" %}
9979 opcode(0x0B);
9980 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9981 ins_pipe(ialu_reg_reg);
9982 %}
9983
9984
9985 // Or Register with Immediate
9986 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9987 %{
9988 match(Set dst (OrL dst src));
9989 effect(KILL cr);
9990
9991 format %{ "orq $dst, $src\t# long" %}
9992 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9993 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9994 ins_pipe(ialu_reg);
9995 %}
9996
9997 // Or Register with Memory
9998 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9999 %{
10000 match(Set dst (OrL dst (LoadL src)));
10001 effect(KILL cr);
10002
10003 ins_cost(125);
10004 format %{ "orq $dst, $src\t# long" %}
10005 opcode(0x0B);
10006 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10007 ins_pipe(ialu_reg_mem);
10008 %}
10009
10010 // Or Memory with Register
10011 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10012 %{
10013 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10014 effect(KILL cr);
10015
10016 ins_cost(150);
10017 format %{ "orq $dst, $src\t# long" %}
10018 opcode(0x09); /* Opcode 09 /r */
10019 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10020 ins_pipe(ialu_mem_reg);
10021 %}
10022
10023 // Or Memory with Immediate
10024 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10025 %{
10026 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10027 effect(KILL cr);
10028
10029 ins_cost(125);
10030 format %{ "orq $dst, $src\t# long" %}
10031 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10032 ins_encode(REX_mem_wide(dst), OpcSE(src),
10033 RM_opc_mem(secondary, dst), Con8or32(src));
10034 ins_pipe(ialu_mem_imm);
10035 %}
10036
10037 // Xor Instructions
10038 // Xor Register with Register
10039 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10040 %{
10041 match(Set dst (XorL dst src));
10042 effect(KILL cr);
10043
10044 format %{ "xorq $dst, $src\t# long" %}
10045 opcode(0x33);
10046 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10047 ins_pipe(ialu_reg_reg);
10048 %}
10049
10050 // Xor Register with Immediate -1
10051 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10052 match(Set dst (XorL dst imm));
10053
10054 format %{ "notq $dst" %}
10055 ins_encode %{
10056 __ notq($dst$$Register);
10057 %}
10058 ins_pipe(ialu_reg);
10059 %}
10060
10061 // Xor Register with Immediate
10062 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10063 %{
10064 match(Set dst (XorL dst src));
10065 effect(KILL cr);
10066
10067 format %{ "xorq $dst, $src\t# long" %}
10068 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10069 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10070 ins_pipe(ialu_reg);
10071 %}
10072
10073 // Xor Register with Memory
10074 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10075 %{
10076 match(Set dst (XorL dst (LoadL src)));
10077 effect(KILL cr);
10078
10079 ins_cost(125);
10080 format %{ "xorq $dst, $src\t# long" %}
10081 opcode(0x33);
10082 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10083 ins_pipe(ialu_reg_mem);
10084 %}
10085
10086 // Xor Memory with Register
10087 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10088 %{
10089 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10090 effect(KILL cr);
10091
10092 ins_cost(150);
10093 format %{ "xorq $dst, $src\t# long" %}
10094 opcode(0x31); /* Opcode 31 /r */
10095 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10096 ins_pipe(ialu_mem_reg);
10097 %}
10098
10099 // Xor Memory with Immediate
10100 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10101 %{
10102 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10103 effect(KILL cr);
10104
10105 ins_cost(125);
10106 format %{ "xorq $dst, $src\t# long" %}
10107 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10108 ins_encode(REX_mem_wide(dst), OpcSE(src),
10109 RM_opc_mem(secondary, dst), Con8or32(src));
10110 ins_pipe(ialu_mem_imm);
10111 %}
10112
10113 // Convert Int to Boolean
10114 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10115 %{
10116 match(Set dst (Conv2B src));
10117 effect(KILL cr);
10118
10119 format %{ "testl $src, $src\t# ci2b\n\t"
10120 "setnz $dst\n\t"
10121 "movzbl $dst, $dst" %}
10122 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10123 setNZ_reg(dst),
10124 REX_reg_breg(dst, dst), // movzbl
10125 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10126 ins_pipe(pipe_slow); // XXX
10127 %}
10128
10129 // Convert Pointer to Boolean
10130 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10131 %{
10132 match(Set dst (Conv2B src));
10133 effect(KILL cr);
10134
10135 format %{ "testq $src, $src\t# cp2b\n\t"
10136 "setnz $dst\n\t"
10137 "movzbl $dst, $dst" %}
10138 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10139 setNZ_reg(dst),
10140 REX_reg_breg(dst, dst), // movzbl
10141 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10142 ins_pipe(pipe_slow); // XXX
10143 %}
10144
10145 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10146 %{
10147 match(Set dst (CmpLTMask p q));
10148 effect(KILL cr);
10149
10150 ins_cost(400);
10151 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10152 "setlt $dst\n\t"
10153 "movzbl $dst, $dst\n\t"
10154 "negl $dst" %}
10155 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10156 setLT_reg(dst),
10157 REX_reg_breg(dst, dst), // movzbl
10158 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10159 neg_reg(dst));
10160 ins_pipe(pipe_slow);
10161 %}
10162
10163 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10164 %{
10165 match(Set dst (CmpLTMask dst zero));
10166 effect(KILL cr);
10167
10168 ins_cost(100);
10169 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10170 ins_encode %{
10171 __ sarl($dst$$Register, 31);
10172 %}
10173 ins_pipe(ialu_reg);
10174 %}
10175
10176 /* Better to save a register than avoid a branch */
10177 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10178 %{
10179 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10180 effect(KILL cr);
10181 ins_cost(300);
10182 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10183 "jge done\n\t"
10184 "addl $p,$y\n"
10185 "done: " %}
10186 ins_encode %{
10187 Register Rp = $p$$Register;
10188 Register Rq = $q$$Register;
10189 Register Ry = $y$$Register;
10190 Label done;
10191 __ subl(Rp, Rq);
10192 __ jccb(Assembler::greaterEqual, done);
10193 __ addl(Rp, Ry);
10194 __ bind(done);
10195 %}
10196 ins_pipe(pipe_cmplt);
10197 %}
10198
10199 /* Better to save a register than avoid a branch */
10200 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10201 %{
10202 match(Set y (AndI (CmpLTMask p q) y));
10203 effect(KILL cr);
10204
10205 ins_cost(300);
10206
10207 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10208 "jlt done\n\t"
10209 "xorl $y, $y\n"
10210 "done: " %}
10211 ins_encode %{
10212 Register Rp = $p$$Register;
10213 Register Rq = $q$$Register;
10214 Register Ry = $y$$Register;
10215 Label done;
10216 __ cmpl(Rp, Rq);
10217 __ jccb(Assembler::less, done);
10218 __ xorl(Ry, Ry);
10219 __ bind(done);
10220 %}
10221 ins_pipe(pipe_cmplt);
10222 %}
10223
10224
10225 //---------- FP Instructions------------------------------------------------
10226
10227 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10228 %{
10229 match(Set cr (CmpF src1 src2));
10230
10231 ins_cost(145);
10232 format %{ "ucomiss $src1, $src2\n\t"
10233 "jnp,s exit\n\t"
10234 "pushfq\t# saw NaN, set CF\n\t"
10235 "andq [rsp], #0xffffff2b\n\t"
10236 "popfq\n"
10237 "exit:" %}
10238 ins_encode %{
10239 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10240 emit_cmpfp_fixup(_masm);
10241 %}
10242 ins_pipe(pipe_slow);
10243 %}
10244
10245 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10246 match(Set cr (CmpF src1 src2));
10247
10248 ins_cost(100);
10249 format %{ "ucomiss $src1, $src2" %}
10250 ins_encode %{
10251 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10252 %}
10253 ins_pipe(pipe_slow);
10254 %}
10255
10256 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10257 %{
10258 match(Set cr (CmpF src1 (LoadF src2)));
10259
10260 ins_cost(145);
10261 format %{ "ucomiss $src1, $src2\n\t"
10262 "jnp,s exit\n\t"
10263 "pushfq\t# saw NaN, set CF\n\t"
10264 "andq [rsp], #0xffffff2b\n\t"
10265 "popfq\n"
10266 "exit:" %}
10267 ins_encode %{
10268 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10269 emit_cmpfp_fixup(_masm);
10270 %}
10271 ins_pipe(pipe_slow);
10272 %}
10273
10274 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10275 match(Set cr (CmpF src1 (LoadF src2)));
10276
10277 ins_cost(100);
10278 format %{ "ucomiss $src1, $src2" %}
10279 ins_encode %{
10280 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10281 %}
10282 ins_pipe(pipe_slow);
10283 %}
10284
10285 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10286 match(Set cr (CmpF src con));
10287
10288 ins_cost(145);
10289 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10290 "jnp,s exit\n\t"
10291 "pushfq\t# saw NaN, set CF\n\t"
10292 "andq [rsp], #0xffffff2b\n\t"
10293 "popfq\n"
10294 "exit:" %}
10295 ins_encode %{
10296 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10297 emit_cmpfp_fixup(_masm);
10298 %}
10299 ins_pipe(pipe_slow);
10300 %}
10301
10302 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10303 match(Set cr (CmpF src con));
10304 ins_cost(100);
10305 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10306 ins_encode %{
10307 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10308 %}
10309 ins_pipe(pipe_slow);
10310 %}
10311
10312 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10313 %{
10314 match(Set cr (CmpD src1 src2));
10315
10316 ins_cost(145);
10317 format %{ "ucomisd $src1, $src2\n\t"
10318 "jnp,s exit\n\t"
10319 "pushfq\t# saw NaN, set CF\n\t"
10320 "andq [rsp], #0xffffff2b\n\t"
10321 "popfq\n"
10322 "exit:" %}
10323 ins_encode %{
10324 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10325 emit_cmpfp_fixup(_masm);
10326 %}
10327 ins_pipe(pipe_slow);
10328 %}
10329
10330 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10331 match(Set cr (CmpD src1 src2));
10332
10333 ins_cost(100);
10334 format %{ "ucomisd $src1, $src2 test" %}
10335 ins_encode %{
10336 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10337 %}
10338 ins_pipe(pipe_slow);
10339 %}
10340
10341 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10342 %{
10343 match(Set cr (CmpD src1 (LoadD src2)));
10344
10345 ins_cost(145);
10346 format %{ "ucomisd $src1, $src2\n\t"
10347 "jnp,s exit\n\t"
10348 "pushfq\t# saw NaN, set CF\n\t"
10349 "andq [rsp], #0xffffff2b\n\t"
10350 "popfq\n"
10351 "exit:" %}
10352 ins_encode %{
10353 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10354 emit_cmpfp_fixup(_masm);
10355 %}
10356 ins_pipe(pipe_slow);
10357 %}
10358
10359 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10360 match(Set cr (CmpD src1 (LoadD src2)));
10361
10362 ins_cost(100);
10363 format %{ "ucomisd $src1, $src2" %}
10364 ins_encode %{
10365 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10366 %}
10367 ins_pipe(pipe_slow);
10368 %}
10369
10370 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10371 match(Set cr (CmpD src con));
10372
10373 ins_cost(145);
10374 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10375 "jnp,s exit\n\t"
10376 "pushfq\t# saw NaN, set CF\n\t"
10377 "andq [rsp], #0xffffff2b\n\t"
10378 "popfq\n"
10379 "exit:" %}
10380 ins_encode %{
10381 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10382 emit_cmpfp_fixup(_masm);
10383 %}
10384 ins_pipe(pipe_slow);
10385 %}
10386
10387 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10388 match(Set cr (CmpD src con));
10389 ins_cost(100);
10390 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10391 ins_encode %{
10392 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10393 %}
10394 ins_pipe(pipe_slow);
10395 %}
10396
10397 // Compare into -1,0,1
10398 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10399 %{
10400 match(Set dst (CmpF3 src1 src2));
10401 effect(KILL cr);
10402
10403 ins_cost(275);
10404 format %{ "ucomiss $src1, $src2\n\t"
10405 "movl $dst, #-1\n\t"
10406 "jp,s done\n\t"
10407 "jb,s done\n\t"
10408 "setne $dst\n\t"
10409 "movzbl $dst, $dst\n"
10410 "done:" %}
10411 ins_encode %{
10412 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10413 emit_cmpfp3(_masm, $dst$$Register);
10414 %}
10415 ins_pipe(pipe_slow);
10416 %}
10417
10418 // Compare into -1,0,1
10419 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10420 %{
10421 match(Set dst (CmpF3 src1 (LoadF src2)));
10422 effect(KILL cr);
10423
10424 ins_cost(275);
10425 format %{ "ucomiss $src1, $src2\n\t"
10426 "movl $dst, #-1\n\t"
10427 "jp,s done\n\t"
10428 "jb,s done\n\t"
10429 "setne $dst\n\t"
10430 "movzbl $dst, $dst\n"
10431 "done:" %}
10432 ins_encode %{
10433 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10434 emit_cmpfp3(_masm, $dst$$Register);
10435 %}
10436 ins_pipe(pipe_slow);
10437 %}
10438
10439 // Compare into -1,0,1
10440 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10441 match(Set dst (CmpF3 src con));
10442 effect(KILL cr);
10443
10444 ins_cost(275);
10445 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10446 "movl $dst, #-1\n\t"
10447 "jp,s done\n\t"
10448 "jb,s done\n\t"
10449 "setne $dst\n\t"
10450 "movzbl $dst, $dst\n"
10451 "done:" %}
10452 ins_encode %{
10453 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10454 emit_cmpfp3(_masm, $dst$$Register);
10455 %}
10456 ins_pipe(pipe_slow);
10457 %}
10458
10459 // Compare into -1,0,1
10460 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10461 %{
10462 match(Set dst (CmpD3 src1 src2));
10463 effect(KILL cr);
10464
10465 ins_cost(275);
10466 format %{ "ucomisd $src1, $src2\n\t"
10467 "movl $dst, #-1\n\t"
10468 "jp,s done\n\t"
10469 "jb,s done\n\t"
10470 "setne $dst\n\t"
10471 "movzbl $dst, $dst\n"
10472 "done:" %}
10473 ins_encode %{
10474 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10475 emit_cmpfp3(_masm, $dst$$Register);
10476 %}
10477 ins_pipe(pipe_slow);
10478 %}
10479
10480 // Compare into -1,0,1
10481 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10482 %{
10483 match(Set dst (CmpD3 src1 (LoadD src2)));
10484 effect(KILL cr);
10485
10486 ins_cost(275);
10487 format %{ "ucomisd $src1, $src2\n\t"
10488 "movl $dst, #-1\n\t"
10489 "jp,s done\n\t"
10490 "jb,s done\n\t"
10491 "setne $dst\n\t"
10492 "movzbl $dst, $dst\n"
10493 "done:" %}
10494 ins_encode %{
10495 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10496 emit_cmpfp3(_masm, $dst$$Register);
10497 %}
10498 ins_pipe(pipe_slow);
10499 %}
10500
10501 // Compare into -1,0,1
10502 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10503 match(Set dst (CmpD3 src con));
10504 effect(KILL cr);
10505
10506 ins_cost(275);
10507 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10508 "movl $dst, #-1\n\t"
10509 "jp,s done\n\t"
10510 "jb,s done\n\t"
10511 "setne $dst\n\t"
10512 "movzbl $dst, $dst\n"
10513 "done:" %}
10514 ins_encode %{
10515 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10516 emit_cmpfp3(_masm, $dst$$Register);
10517 %}
10518 ins_pipe(pipe_slow);
10519 %}
10520
10521 //----------Arithmetic Conversion Instructions---------------------------------
10522
10523 instruct roundFloat_nop(regF dst)
10524 %{
10525 match(Set dst (RoundFloat dst));
10526
10527 ins_cost(0);
10528 ins_encode();
10529 ins_pipe(empty);
10530 %}
10531
10532 instruct roundDouble_nop(regD dst)
10533 %{
10534 match(Set dst (RoundDouble dst));
10535
10536 ins_cost(0);
10537 ins_encode();
10538 ins_pipe(empty);
10539 %}
10540
10541 instruct convF2D_reg_reg(regD dst, regF src)
10542 %{
10543 match(Set dst (ConvF2D src));
10544
10545 format %{ "cvtss2sd $dst, $src" %}
10546 ins_encode %{
10547 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10548 %}
10549 ins_pipe(pipe_slow); // XXX
10550 %}
10551
10552 instruct convF2D_reg_mem(regD dst, memory src)
10553 %{
10554 match(Set dst (ConvF2D (LoadF src)));
10555
10556 format %{ "cvtss2sd $dst, $src" %}
10557 ins_encode %{
10558 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10559 %}
10560 ins_pipe(pipe_slow); // XXX
10561 %}
10562
10563 instruct convD2F_reg_reg(regF dst, regD src)
10564 %{
10565 match(Set dst (ConvD2F src));
10566
10567 format %{ "cvtsd2ss $dst, $src" %}
10568 ins_encode %{
10569 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10570 %}
10571 ins_pipe(pipe_slow); // XXX
10572 %}
10573
10574 instruct convD2F_reg_mem(regF dst, memory src)
10575 %{
10576 match(Set dst (ConvD2F (LoadD src)));
10577
10578 format %{ "cvtsd2ss $dst, $src" %}
10579 ins_encode %{
10580 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10581 %}
10582 ins_pipe(pipe_slow); // XXX
10583 %}
10584
10585 // XXX do mem variants
10586 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10587 %{
10588 match(Set dst (ConvF2I src));
10589 effect(KILL cr);
10590
10591 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10592 "cmpl $dst, #0x80000000\n\t"
10593 "jne,s done\n\t"
10594 "subq rsp, #8\n\t"
10595 "movss [rsp], $src\n\t"
10596 "call f2i_fixup\n\t"
10597 "popq $dst\n"
10598 "done: "%}
10599 ins_encode %{
10600 Label done;
10601 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10602 __ cmpl($dst$$Register, 0x80000000);
10603 __ jccb(Assembler::notEqual, done);
10604 __ subptr(rsp, 8);
10605 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10606 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10607 __ pop($dst$$Register);
10608 __ bind(done);
10609 %}
10610 ins_pipe(pipe_slow);
10611 %}
10612
10613 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10614 %{
10615 match(Set dst (ConvF2L src));
10616 effect(KILL cr);
10617
10618 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10619 "cmpq $dst, [0x8000000000000000]\n\t"
10620 "jne,s done\n\t"
10621 "subq rsp, #8\n\t"
10622 "movss [rsp], $src\n\t"
10623 "call f2l_fixup\n\t"
10624 "popq $dst\n"
10625 "done: "%}
10626 ins_encode %{
10627 Label done;
10628 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10629 __ cmp64($dst$$Register,
10630 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10631 __ jccb(Assembler::notEqual, done);
10632 __ subptr(rsp, 8);
10633 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10634 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10635 __ pop($dst$$Register);
10636 __ bind(done);
10637 %}
10638 ins_pipe(pipe_slow);
10639 %}
10640
10641 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10642 %{
10643 match(Set dst (ConvD2I src));
10644 effect(KILL cr);
10645
10646 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10647 "cmpl $dst, #0x80000000\n\t"
10648 "jne,s done\n\t"
10649 "subq rsp, #8\n\t"
10650 "movsd [rsp], $src\n\t"
10651 "call d2i_fixup\n\t"
10652 "popq $dst\n"
10653 "done: "%}
10654 ins_encode %{
10655 Label done;
10656 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10657 __ cmpl($dst$$Register, 0x80000000);
10658 __ jccb(Assembler::notEqual, done);
10659 __ subptr(rsp, 8);
10660 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10661 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10662 __ pop($dst$$Register);
10663 __ bind(done);
10664 %}
10665 ins_pipe(pipe_slow);
10666 %}
10667
10668 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10669 %{
10670 match(Set dst (ConvD2L src));
10671 effect(KILL cr);
10672
10673 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10674 "cmpq $dst, [0x8000000000000000]\n\t"
10675 "jne,s done\n\t"
10676 "subq rsp, #8\n\t"
10677 "movsd [rsp], $src\n\t"
10678 "call d2l_fixup\n\t"
10679 "popq $dst\n"
10680 "done: "%}
10681 ins_encode %{
10682 Label done;
10683 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10684 __ cmp64($dst$$Register,
10685 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10686 __ jccb(Assembler::notEqual, done);
10687 __ subptr(rsp, 8);
10688 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10689 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10690 __ pop($dst$$Register);
10691 __ bind(done);
10692 %}
10693 ins_pipe(pipe_slow);
10694 %}
10695
10696 instruct convI2F_reg_reg(regF dst, rRegI src)
10697 %{
10698 predicate(!UseXmmI2F);
10699 match(Set dst (ConvI2F src));
10700
10701 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10702 ins_encode %{
10703 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10704 %}
10705 ins_pipe(pipe_slow); // XXX
10706 %}
10707
10708 instruct convI2F_reg_mem(regF dst, memory src)
10709 %{
10710 match(Set dst (ConvI2F (LoadI src)));
10711
10712 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10713 ins_encode %{
10714 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10715 %}
10716 ins_pipe(pipe_slow); // XXX
10717 %}
10718
10719 instruct convI2D_reg_reg(regD dst, rRegI src)
10720 %{
10721 predicate(!UseXmmI2D);
10722 match(Set dst (ConvI2D src));
10723
10724 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10725 ins_encode %{
10726 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10727 %}
10728 ins_pipe(pipe_slow); // XXX
10729 %}
10730
10731 instruct convI2D_reg_mem(regD dst, memory src)
10732 %{
10733 match(Set dst (ConvI2D (LoadI src)));
10734
10735 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10736 ins_encode %{
10737 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10738 %}
10739 ins_pipe(pipe_slow); // XXX
10740 %}
10741
10742 instruct convXI2F_reg(regF dst, rRegI src)
10743 %{
10744 predicate(UseXmmI2F);
10745 match(Set dst (ConvI2F src));
10746
10747 format %{ "movdl $dst, $src\n\t"
10748 "cvtdq2psl $dst, $dst\t# i2f" %}
10749 ins_encode %{
10750 __ movdl($dst$$XMMRegister, $src$$Register);
10751 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10752 %}
10753 ins_pipe(pipe_slow); // XXX
10754 %}
10755
10756 instruct convXI2D_reg(regD dst, rRegI src)
10757 %{
10758 predicate(UseXmmI2D);
10759 match(Set dst (ConvI2D src));
10760
10761 format %{ "movdl $dst, $src\n\t"
10762 "cvtdq2pdl $dst, $dst\t# i2d" %}
10763 ins_encode %{
10764 __ movdl($dst$$XMMRegister, $src$$Register);
10765 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10766 %}
10767 ins_pipe(pipe_slow); // XXX
10768 %}
10769
10770 instruct convL2F_reg_reg(regF dst, rRegL src)
10771 %{
10772 match(Set dst (ConvL2F src));
10773
10774 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10775 ins_encode %{
10776 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10777 %}
10778 ins_pipe(pipe_slow); // XXX
10779 %}
10780
10781 instruct convL2F_reg_mem(regF dst, memory src)
10782 %{
10783 match(Set dst (ConvL2F (LoadL src)));
10784
10785 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10786 ins_encode %{
10787 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10788 %}
10789 ins_pipe(pipe_slow); // XXX
10790 %}
10791
10792 instruct convL2D_reg_reg(regD dst, rRegL src)
10793 %{
10794 match(Set dst (ConvL2D src));
10795
10796 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10797 ins_encode %{
10798 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10799 %}
10800 ins_pipe(pipe_slow); // XXX
10801 %}
10802
10803 instruct convL2D_reg_mem(regD dst, memory src)
10804 %{
10805 match(Set dst (ConvL2D (LoadL src)));
10806
10807 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10808 ins_encode %{
10809 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10810 %}
10811 ins_pipe(pipe_slow); // XXX
10812 %}
10813
10814 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10815 %{
10816 match(Set dst (ConvI2L src));
10817
10818 ins_cost(125);
10819 format %{ "movslq $dst, $src\t# i2l" %}
10820 ins_encode %{
10821 __ movslq($dst$$Register, $src$$Register);
10822 %}
10823 ins_pipe(ialu_reg_reg);
10824 %}
10825
10826 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10827 // %{
10828 // match(Set dst (ConvI2L src));
10829 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10830 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10831 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10832 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10833 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10834 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10835
10836 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10837 // ins_encode(enc_copy(dst, src));
10838 // // opcode(0x63); // needs REX.W
10839 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10840 // ins_pipe(ialu_reg_reg);
10841 // %}
10842
10843 // Zero-extend convert int to long
10844 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10845 %{
10846 match(Set dst (AndL (ConvI2L src) mask));
10847
10848 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10849 ins_encode %{
10850 if ($dst$$reg != $src$$reg) {
10851 __ movl($dst$$Register, $src$$Register);
10852 }
10853 %}
10854 ins_pipe(ialu_reg_reg);
10855 %}
10856
10857 // Zero-extend convert int to long
10858 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10859 %{
10860 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10861
10862 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10863 ins_encode %{
10864 __ movl($dst$$Register, $src$$Address);
10865 %}
10866 ins_pipe(ialu_reg_mem);
10867 %}
10868
10869 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10870 %{
10871 match(Set dst (AndL src mask));
10872
10873 format %{ "movl $dst, $src\t# zero-extend long" %}
10874 ins_encode %{
10875 __ movl($dst$$Register, $src$$Register);
10876 %}
10877 ins_pipe(ialu_reg_reg);
10878 %}
10879
10880 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10881 %{
10882 match(Set dst (ConvL2I src));
10883
10884 format %{ "movl $dst, $src\t# l2i" %}
10885 ins_encode %{
10886 __ movl($dst$$Register, $src$$Register);
10887 %}
10888 ins_pipe(ialu_reg_reg);
10889 %}
10890
10891
10892 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10893 match(Set dst (MoveF2I src));
10894 effect(DEF dst, USE src);
10895
10896 ins_cost(125);
10897 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10898 ins_encode %{
10899 __ movl($dst$$Register, Address(rsp, $src$$disp));
10900 %}
10901 ins_pipe(ialu_reg_mem);
10902 %}
10903
10904 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10905 match(Set dst (MoveI2F src));
10906 effect(DEF dst, USE src);
10907
10908 ins_cost(125);
10909 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10910 ins_encode %{
10911 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10912 %}
10913 ins_pipe(pipe_slow);
10914 %}
10915
10916 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10917 match(Set dst (MoveD2L src));
10918 effect(DEF dst, USE src);
10919
10920 ins_cost(125);
10921 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10922 ins_encode %{
10923 __ movq($dst$$Register, Address(rsp, $src$$disp));
10924 %}
10925 ins_pipe(ialu_reg_mem);
10926 %}
10927
10928 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10929 predicate(!UseXmmLoadAndClearUpper);
10930 match(Set dst (MoveL2D src));
10931 effect(DEF dst, USE src);
10932
10933 ins_cost(125);
10934 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10935 ins_encode %{
10936 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10937 %}
10938 ins_pipe(pipe_slow);
10939 %}
10940
10941 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10942 predicate(UseXmmLoadAndClearUpper);
10943 match(Set dst (MoveL2D src));
10944 effect(DEF dst, USE src);
10945
10946 ins_cost(125);
10947 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10948 ins_encode %{
10949 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10950 %}
10951 ins_pipe(pipe_slow);
10952 %}
10953
10954
10955 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10956 match(Set dst (MoveF2I src));
10957 effect(DEF dst, USE src);
10958
10959 ins_cost(95); // XXX
10960 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10961 ins_encode %{
10962 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10963 %}
10964 ins_pipe(pipe_slow);
10965 %}
10966
10967 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10968 match(Set dst (MoveI2F src));
10969 effect(DEF dst, USE src);
10970
10971 ins_cost(100);
10972 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10973 ins_encode %{
10974 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10975 %}
10976 ins_pipe( ialu_mem_reg );
10977 %}
10978
10979 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10980 match(Set dst (MoveD2L src));
10981 effect(DEF dst, USE src);
10982
10983 ins_cost(95); // XXX
10984 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10985 ins_encode %{
10986 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10987 %}
10988 ins_pipe(pipe_slow);
10989 %}
10990
10991 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10992 match(Set dst (MoveL2D src));
10993 effect(DEF dst, USE src);
10994
10995 ins_cost(100);
10996 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10997 ins_encode %{
10998 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10999 %}
11000 ins_pipe(ialu_mem_reg);
11001 %}
11002
11003 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11004 match(Set dst (MoveF2I src));
11005 effect(DEF dst, USE src);
11006 ins_cost(85);
11007 format %{ "movd $dst,$src\t# MoveF2I" %}
11008 ins_encode %{
11009 __ movdl($dst$$Register, $src$$XMMRegister);
11010 %}
11011 ins_pipe( pipe_slow );
11012 %}
11013
11014 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11015 match(Set dst (MoveD2L src));
11016 effect(DEF dst, USE src);
11017 ins_cost(85);
11018 format %{ "movd $dst,$src\t# MoveD2L" %}
11019 ins_encode %{
11020 __ movdq($dst$$Register, $src$$XMMRegister);
11021 %}
11022 ins_pipe( pipe_slow );
11023 %}
11024
11025 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11026 match(Set dst (MoveI2F src));
11027 effect(DEF dst, USE src);
11028 ins_cost(100);
11029 format %{ "movd $dst,$src\t# MoveI2F" %}
11030 ins_encode %{
11031 __ movdl($dst$$XMMRegister, $src$$Register);
11032 %}
11033 ins_pipe( pipe_slow );
11034 %}
11035
11036 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11037 match(Set dst (MoveL2D src));
11038 effect(DEF dst, USE src);
11039 ins_cost(100);
11040 format %{ "movd $dst,$src\t# MoveL2D" %}
11041 ins_encode %{
11042 __ movdq($dst$$XMMRegister, $src$$Register);
11043 %}
11044 ins_pipe( pipe_slow );
11045 %}
11046
11047
11048 // =======================================================================
11049 // fast clearing of an array
11050 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11051 Universe dummy, rFlagsReg cr)
11052 %{
11053 predicate(!((ClearArrayNode*)n)->is_large());
11054 match(Set dummy (ClearArray cnt base));
11055 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11056
11057 format %{ $$template
11058 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11059 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11060 $$emit$$"jg LARGE\n\t"
11061 $$emit$$"dec rcx\n\t"
11062 $$emit$$"js DONE\t# Zero length\n\t"
11063 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11064 $$emit$$"dec rcx\n\t"
11065 $$emit$$"jge LOOP\n\t"
11066 $$emit$$"jmp DONE\n\t"
11067 $$emit$$"# LARGE:\n\t"
11068 if (UseFastStosb) {
11069 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11070 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11071 } else if (UseXMMForObjInit) {
11072 $$emit$$"mov rdi,rax\n\t"
11073 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11074 $$emit$$"jmpq L_zero_64_bytes\n\t"
11075 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11076 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11077 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11078 $$emit$$"add 0x40,rax\n\t"
11079 $$emit$$"# L_zero_64_bytes:\n\t"
11080 $$emit$$"sub 0x8,rcx\n\t"
11081 $$emit$$"jge L_loop\n\t"
11082 $$emit$$"add 0x4,rcx\n\t"
11083 $$emit$$"jl L_tail\n\t"
11084 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11085 $$emit$$"add 0x20,rax\n\t"
11086 $$emit$$"sub 0x4,rcx\n\t"
11087 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11088 $$emit$$"add 0x4,rcx\n\t"
11089 $$emit$$"jle L_end\n\t"
11090 $$emit$$"dec rcx\n\t"
11091 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11092 $$emit$$"vmovq xmm0,(rax)\n\t"
11093 $$emit$$"add 0x8,rax\n\t"
11094 $$emit$$"dec rcx\n\t"
11095 $$emit$$"jge L_sloop\n\t"
11096 $$emit$$"# L_end:\n\t"
11097 } else {
11098 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11099 }
11100 $$emit$$"# DONE"
11101 %}
11102 ins_encode %{
11103 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11104 $tmp$$XMMRegister, false);
11105 %}
11106 ins_pipe(pipe_slow);
11107 %}
11108
11109 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11110 Universe dummy, rFlagsReg cr)
11111 %{
11112 predicate(((ClearArrayNode*)n)->is_large());
11113 match(Set dummy (ClearArray cnt base));
11114 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11115
11116 format %{ $$template
11117 if (UseFastStosb) {
11118 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11119 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11120 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11121 } else if (UseXMMForObjInit) {
11122 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11123 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11124 $$emit$$"jmpq L_zero_64_bytes\n\t"
11125 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11126 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11127 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11128 $$emit$$"add 0x40,rax\n\t"
11129 $$emit$$"# L_zero_64_bytes:\n\t"
11130 $$emit$$"sub 0x8,rcx\n\t"
11131 $$emit$$"jge L_loop\n\t"
11132 $$emit$$"add 0x4,rcx\n\t"
11133 $$emit$$"jl L_tail\n\t"
11134 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11135 $$emit$$"add 0x20,rax\n\t"
11136 $$emit$$"sub 0x4,rcx\n\t"
11137 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11138 $$emit$$"add 0x4,rcx\n\t"
11139 $$emit$$"jle L_end\n\t"
11140 $$emit$$"dec rcx\n\t"
11141 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11142 $$emit$$"vmovq xmm0,(rax)\n\t"
11143 $$emit$$"add 0x8,rax\n\t"
11144 $$emit$$"dec rcx\n\t"
11145 $$emit$$"jge L_sloop\n\t"
11146 $$emit$$"# L_end:\n\t"
11147 } else {
11148 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11149 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11150 }
11151 %}
11152 ins_encode %{
11153 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11154 $tmp$$XMMRegister, true);
11155 %}
11156 ins_pipe(pipe_slow);
11157 %}
11158
11159 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11160 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11161 %{
11162 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11163 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11164 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11165
11166 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11167 ins_encode %{
11168 __ string_compare($str1$$Register, $str2$$Register,
11169 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11170 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11171 %}
11172 ins_pipe( pipe_slow );
11173 %}
11174
11175 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11176 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11177 %{
11178 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11179 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11180 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11181
11182 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11183 ins_encode %{
11184 __ string_compare($str1$$Register, $str2$$Register,
11185 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11186 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11187 %}
11188 ins_pipe( pipe_slow );
11189 %}
11190
11191 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11192 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11193 %{
11194 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11195 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11196 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11197
11198 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11199 ins_encode %{
11200 __ string_compare($str1$$Register, $str2$$Register,
11201 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11202 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11203 %}
11204 ins_pipe( pipe_slow );
11205 %}
11206
11207 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11208 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11209 %{
11210 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11211 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11212 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11213
11214 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11215 ins_encode %{
11216 __ string_compare($str2$$Register, $str1$$Register,
11217 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11218 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11219 %}
11220 ins_pipe( pipe_slow );
11221 %}
11222
11223 // fast search of substring with known size.
11224 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11225 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11226 %{
11227 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11228 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11229 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11230
11231 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11232 ins_encode %{
11233 int icnt2 = (int)$int_cnt2$$constant;
11234 if (icnt2 >= 16) {
11235 // IndexOf for constant substrings with size >= 16 elements
11236 // which don't need to be loaded through stack.
11237 __ string_indexofC8($str1$$Register, $str2$$Register,
11238 $cnt1$$Register, $cnt2$$Register,
11239 icnt2, $result$$Register,
11240 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11241 } else {
11242 // Small strings are loaded through stack if they cross page boundary.
11243 __ string_indexof($str1$$Register, $str2$$Register,
11244 $cnt1$$Register, $cnt2$$Register,
11245 icnt2, $result$$Register,
11246 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11247 }
11248 %}
11249 ins_pipe( pipe_slow );
11250 %}
11251
11252 // fast search of substring with known size.
11253 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11254 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11255 %{
11256 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11257 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11258 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11259
11260 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11261 ins_encode %{
11262 int icnt2 = (int)$int_cnt2$$constant;
11263 if (icnt2 >= 8) {
11264 // IndexOf for constant substrings with size >= 8 elements
11265 // which don't need to be loaded through stack.
11266 __ string_indexofC8($str1$$Register, $str2$$Register,
11267 $cnt1$$Register, $cnt2$$Register,
11268 icnt2, $result$$Register,
11269 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11270 } else {
11271 // Small strings are loaded through stack if they cross page boundary.
11272 __ string_indexof($str1$$Register, $str2$$Register,
11273 $cnt1$$Register, $cnt2$$Register,
11274 icnt2, $result$$Register,
11275 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11276 }
11277 %}
11278 ins_pipe( pipe_slow );
11279 %}
11280
11281 // fast search of substring with known size.
11282 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11283 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11284 %{
11285 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11286 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11287 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11288
11289 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11290 ins_encode %{
11291 int icnt2 = (int)$int_cnt2$$constant;
11292 if (icnt2 >= 8) {
11293 // IndexOf for constant substrings with size >= 8 elements
11294 // which don't need to be loaded through stack.
11295 __ string_indexofC8($str1$$Register, $str2$$Register,
11296 $cnt1$$Register, $cnt2$$Register,
11297 icnt2, $result$$Register,
11298 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11299 } else {
11300 // Small strings are loaded through stack if they cross page boundary.
11301 __ string_indexof($str1$$Register, $str2$$Register,
11302 $cnt1$$Register, $cnt2$$Register,
11303 icnt2, $result$$Register,
11304 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11305 }
11306 %}
11307 ins_pipe( pipe_slow );
11308 %}
11309
11310 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11311 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11312 %{
11313 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11314 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11315 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11316
11317 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11318 ins_encode %{
11319 __ string_indexof($str1$$Register, $str2$$Register,
11320 $cnt1$$Register, $cnt2$$Register,
11321 (-1), $result$$Register,
11322 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11323 %}
11324 ins_pipe( pipe_slow );
11325 %}
11326
11327 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11328 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11329 %{
11330 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11331 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11332 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11333
11334 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11335 ins_encode %{
11336 __ string_indexof($str1$$Register, $str2$$Register,
11337 $cnt1$$Register, $cnt2$$Register,
11338 (-1), $result$$Register,
11339 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11340 %}
11341 ins_pipe( pipe_slow );
11342 %}
11343
11344 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11345 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11346 %{
11347 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11348 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11349 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11350
11351 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11352 ins_encode %{
11353 __ string_indexof($str1$$Register, $str2$$Register,
11354 $cnt1$$Register, $cnt2$$Register,
11355 (-1), $result$$Register,
11356 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11357 %}
11358 ins_pipe( pipe_slow );
11359 %}
11360
11361 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11362 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11363 %{
11364 predicate(UseSSE42Intrinsics);
11365 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11366 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11367 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11368 ins_encode %{
11369 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11370 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11371 %}
11372 ins_pipe( pipe_slow );
11373 %}
11374
11375 // fast string equals
11376 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11377 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11378 %{
11379 match(Set result (StrEquals (Binary str1 str2) cnt));
11380 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11381
11382 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11383 ins_encode %{
11384 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11385 $cnt$$Register, $result$$Register, $tmp3$$Register,
11386 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11387 %}
11388 ins_pipe( pipe_slow );
11389 %}
11390
11391 // fast array equals
11392 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11393 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11394 %{
11395 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11396 match(Set result (AryEq ary1 ary2));
11397 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11398
11399 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11400 ins_encode %{
11401 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11402 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11403 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11404 %}
11405 ins_pipe( pipe_slow );
11406 %}
11407
11408 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11409 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11410 %{
11411 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11412 match(Set result (AryEq ary1 ary2));
11413 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11414
11415 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11416 ins_encode %{
11417 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11418 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11419 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11420 %}
11421 ins_pipe( pipe_slow );
11422 %}
11423
11424 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11425 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11426 %{
11427 match(Set result (HasNegatives ary1 len));
11428 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11429
11430 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11431 ins_encode %{
11432 __ has_negatives($ary1$$Register, $len$$Register,
11433 $result$$Register, $tmp3$$Register,
11434 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11435 %}
11436 ins_pipe( pipe_slow );
11437 %}
11438
11439 // fast char[] to byte[] compression
11440 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11441 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11442 match(Set result (StrCompressedCopy src (Binary dst len)));
11443 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11444
11445 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11446 ins_encode %{
11447 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11448 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11449 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11450 %}
11451 ins_pipe( pipe_slow );
11452 %}
11453
11454 // fast byte[] to char[] inflation
11455 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11456 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11457 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11458 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11459
11460 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11461 ins_encode %{
11462 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11463 $tmp1$$XMMRegister, $tmp2$$Register);
11464 %}
11465 ins_pipe( pipe_slow );
11466 %}
11467
11468 // encode char[] to byte[] in ISO_8859_1
11469 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11470 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11471 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11472 match(Set result (EncodeISOArray src (Binary dst len)));
11473 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11474
11475 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11476 ins_encode %{
11477 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11478 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11479 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11480 %}
11481 ins_pipe( pipe_slow );
11482 %}
11483
11484 //----------Overflow Math Instructions-----------------------------------------
11485
11486 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11487 %{
11488 match(Set cr (OverflowAddI op1 op2));
11489 effect(DEF cr, USE_KILL op1, USE op2);
11490
11491 format %{ "addl $op1, $op2\t# overflow check int" %}
11492
11493 ins_encode %{
11494 __ addl($op1$$Register, $op2$$Register);
11495 %}
11496 ins_pipe(ialu_reg_reg);
11497 %}
11498
11499 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11500 %{
11501 match(Set cr (OverflowAddI op1 op2));
11502 effect(DEF cr, USE_KILL op1, USE op2);
11503
11504 format %{ "addl $op1, $op2\t# overflow check int" %}
11505
11506 ins_encode %{
11507 __ addl($op1$$Register, $op2$$constant);
11508 %}
11509 ins_pipe(ialu_reg_reg);
11510 %}
11511
11512 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11513 %{
11514 match(Set cr (OverflowAddL op1 op2));
11515 effect(DEF cr, USE_KILL op1, USE op2);
11516
11517 format %{ "addq $op1, $op2\t# overflow check long" %}
11518 ins_encode %{
11519 __ addq($op1$$Register, $op2$$Register);
11520 %}
11521 ins_pipe(ialu_reg_reg);
11522 %}
11523
11524 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11525 %{
11526 match(Set cr (OverflowAddL op1 op2));
11527 effect(DEF cr, USE_KILL op1, USE op2);
11528
11529 format %{ "addq $op1, $op2\t# overflow check long" %}
11530 ins_encode %{
11531 __ addq($op1$$Register, $op2$$constant);
11532 %}
11533 ins_pipe(ialu_reg_reg);
11534 %}
11535
11536 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11537 %{
11538 match(Set cr (OverflowSubI op1 op2));
11539
11540 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11541 ins_encode %{
11542 __ cmpl($op1$$Register, $op2$$Register);
11543 %}
11544 ins_pipe(ialu_reg_reg);
11545 %}
11546
11547 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11548 %{
11549 match(Set cr (OverflowSubI op1 op2));
11550
11551 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11552 ins_encode %{
11553 __ cmpl($op1$$Register, $op2$$constant);
11554 %}
11555 ins_pipe(ialu_reg_reg);
11556 %}
11557
11558 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11559 %{
11560 match(Set cr (OverflowSubL op1 op2));
11561
11562 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11563 ins_encode %{
11564 __ cmpq($op1$$Register, $op2$$Register);
11565 %}
11566 ins_pipe(ialu_reg_reg);
11567 %}
11568
11569 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11570 %{
11571 match(Set cr (OverflowSubL op1 op2));
11572
11573 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11574 ins_encode %{
11575 __ cmpq($op1$$Register, $op2$$constant);
11576 %}
11577 ins_pipe(ialu_reg_reg);
11578 %}
11579
11580 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11581 %{
11582 match(Set cr (OverflowSubI zero op2));
11583 effect(DEF cr, USE_KILL op2);
11584
11585 format %{ "negl $op2\t# overflow check int" %}
11586 ins_encode %{
11587 __ negl($op2$$Register);
11588 %}
11589 ins_pipe(ialu_reg_reg);
11590 %}
11591
11592 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11593 %{
11594 match(Set cr (OverflowSubL zero op2));
11595 effect(DEF cr, USE_KILL op2);
11596
11597 format %{ "negq $op2\t# overflow check long" %}
11598 ins_encode %{
11599 __ negq($op2$$Register);
11600 %}
11601 ins_pipe(ialu_reg_reg);
11602 %}
11603
11604 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11605 %{
11606 match(Set cr (OverflowMulI op1 op2));
11607 effect(DEF cr, USE_KILL op1, USE op2);
11608
11609 format %{ "imull $op1, $op2\t# overflow check int" %}
11610 ins_encode %{
11611 __ imull($op1$$Register, $op2$$Register);
11612 %}
11613 ins_pipe(ialu_reg_reg_alu0);
11614 %}
11615
11616 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11617 %{
11618 match(Set cr (OverflowMulI op1 op2));
11619 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11620
11621 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11622 ins_encode %{
11623 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11624 %}
11625 ins_pipe(ialu_reg_reg_alu0);
11626 %}
11627
11628 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11629 %{
11630 match(Set cr (OverflowMulL op1 op2));
11631 effect(DEF cr, USE_KILL op1, USE op2);
11632
11633 format %{ "imulq $op1, $op2\t# overflow check long" %}
11634 ins_encode %{
11635 __ imulq($op1$$Register, $op2$$Register);
11636 %}
11637 ins_pipe(ialu_reg_reg_alu0);
11638 %}
11639
11640 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11641 %{
11642 match(Set cr (OverflowMulL op1 op2));
11643 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11644
11645 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11646 ins_encode %{
11647 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11648 %}
11649 ins_pipe(ialu_reg_reg_alu0);
11650 %}
11651
11652
11653 //----------Control Flow Instructions------------------------------------------
11654 // Signed compare Instructions
11655
11656 // XXX more variants!!
11657 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11658 %{
11659 match(Set cr (CmpI op1 op2));
11660 effect(DEF cr, USE op1, USE op2);
11661
11662 format %{ "cmpl $op1, $op2" %}
11663 opcode(0x3B); /* Opcode 3B /r */
11664 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11665 ins_pipe(ialu_cr_reg_reg);
11666 %}
11667
11668 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11669 %{
11670 match(Set cr (CmpI op1 op2));
11671
11672 format %{ "cmpl $op1, $op2" %}
11673 opcode(0x81, 0x07); /* Opcode 81 /7 */
11674 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11675 ins_pipe(ialu_cr_reg_imm);
11676 %}
11677
11678 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11679 %{
11680 match(Set cr (CmpI op1 (LoadI op2)));
11681
11682 ins_cost(500); // XXX
11683 format %{ "cmpl $op1, $op2" %}
11684 opcode(0x3B); /* Opcode 3B /r */
11685 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11686 ins_pipe(ialu_cr_reg_mem);
11687 %}
11688
11689 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11690 %{
11691 match(Set cr (CmpI src zero));
11692
11693 format %{ "testl $src, $src" %}
11694 opcode(0x85);
11695 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11696 ins_pipe(ialu_cr_reg_imm);
11697 %}
11698
11699 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11700 %{
11701 match(Set cr (CmpI (AndI src con) zero));
11702
11703 format %{ "testl $src, $con" %}
11704 opcode(0xF7, 0x00);
11705 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11706 ins_pipe(ialu_cr_reg_imm);
11707 %}
11708
11709 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11710 %{
11711 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11712
11713 format %{ "testl $src, $mem" %}
11714 opcode(0x85);
11715 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11716 ins_pipe(ialu_cr_reg_mem);
11717 %}
11718
11719 // Unsigned compare Instructions; really, same as signed except they
11720 // produce an rFlagsRegU instead of rFlagsReg.
11721 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11722 %{
11723 match(Set cr (CmpU op1 op2));
11724
11725 format %{ "cmpl $op1, $op2\t# unsigned" %}
11726 opcode(0x3B); /* Opcode 3B /r */
11727 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11728 ins_pipe(ialu_cr_reg_reg);
11729 %}
11730
11731 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11732 %{
11733 match(Set cr (CmpU op1 op2));
11734
11735 format %{ "cmpl $op1, $op2\t# unsigned" %}
11736 opcode(0x81,0x07); /* Opcode 81 /7 */
11737 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11738 ins_pipe(ialu_cr_reg_imm);
11739 %}
11740
11741 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11742 %{
11743 match(Set cr (CmpU op1 (LoadI op2)));
11744
11745 ins_cost(500); // XXX
11746 format %{ "cmpl $op1, $op2\t# unsigned" %}
11747 opcode(0x3B); /* Opcode 3B /r */
11748 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11749 ins_pipe(ialu_cr_reg_mem);
11750 %}
11751
11752 // // // Cisc-spilled version of cmpU_rReg
11753 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11754 // //%{
11755 // // match(Set cr (CmpU (LoadI op1) op2));
11756 // //
11757 // // format %{ "CMPu $op1,$op2" %}
11758 // // ins_cost(500);
11759 // // opcode(0x39); /* Opcode 39 /r */
11760 // // ins_encode( OpcP, reg_mem( op1, op2) );
11761 // //%}
11762
11763 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11764 %{
11765 match(Set cr (CmpU src zero));
11766
11767 format %{ "testl $src, $src\t# unsigned" %}
11768 opcode(0x85);
11769 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11770 ins_pipe(ialu_cr_reg_imm);
11771 %}
11772
11773 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11774 %{
11775 match(Set cr (CmpP op1 op2));
11776
11777 format %{ "cmpq $op1, $op2\t# ptr" %}
11778 opcode(0x3B); /* Opcode 3B /r */
11779 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11780 ins_pipe(ialu_cr_reg_reg);
11781 %}
11782
11783 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11784 %{
11785 match(Set cr (CmpP op1 (LoadP op2)));
11786 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11787
11788 ins_cost(500); // XXX
11789 format %{ "cmpq $op1, $op2\t# ptr" %}
11790 opcode(0x3B); /* Opcode 3B /r */
11791 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11792 ins_pipe(ialu_cr_reg_mem);
11793 %}
11794
11795 // // // Cisc-spilled version of cmpP_rReg
11796 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11797 // //%{
11798 // // match(Set cr (CmpP (LoadP op1) op2));
11799 // //
11800 // // format %{ "CMPu $op1,$op2" %}
11801 // // ins_cost(500);
11802 // // opcode(0x39); /* Opcode 39 /r */
11803 // // ins_encode( OpcP, reg_mem( op1, op2) );
11804 // //%}
11805
11806 // XXX this is generalized by compP_rReg_mem???
11807 // Compare raw pointer (used in out-of-heap check).
11808 // Only works because non-oop pointers must be raw pointers
11809 // and raw pointers have no anti-dependencies.
11810 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11811 %{
11812 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
11813 n->in(2)->as_Load()->barrier_data() == 0);
11814 match(Set cr (CmpP op1 (LoadP op2)));
11815
11816 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11817 opcode(0x3B); /* Opcode 3B /r */
11818 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11819 ins_pipe(ialu_cr_reg_mem);
11820 %}
11821
11822 // This will generate a signed flags result. This should be OK since
11823 // any compare to a zero should be eq/neq.
11824 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11825 %{
11826 match(Set cr (CmpP src zero));
11827
11828 format %{ "testq $src, $src\t# ptr" %}
11829 opcode(0x85);
11830 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11831 ins_pipe(ialu_cr_reg_imm);
11832 %}
11833
11834 // This will generate a signed flags result. This should be OK since
11835 // any compare to a zero should be eq/neq.
11836 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11837 %{
11838 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
11839 n->in(1)->as_Load()->barrier_data() == 0);
11840 match(Set cr (CmpP (LoadP op) zero));
11841
11842 ins_cost(500); // XXX
11843 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11844 opcode(0xF7); /* Opcode F7 /0 */
11845 ins_encode(REX_mem_wide(op),
11846 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11847 ins_pipe(ialu_cr_reg_imm);
11848 %}
11849
11850 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11851 %{
11852 predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
11853 (CompressedKlassPointers::base() == NULL) &&
11854 n->in(1)->as_Load()->barrier_data() == 0);
11855 match(Set cr (CmpP (LoadP mem) zero));
11856
11857 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11858 ins_encode %{
11859 __ cmpq(r12, $mem$$Address);
11860 %}
11861 ins_pipe(ialu_cr_reg_mem);
11862 %}
11863
11864 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11865 %{
11866 match(Set cr (CmpN op1 op2));
11867
11868 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11869 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11870 ins_pipe(ialu_cr_reg_reg);
11871 %}
11872
11873 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11874 %{
11875 match(Set cr (CmpN src (LoadN mem)));
11876
11877 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11878 ins_encode %{
11879 __ cmpl($src$$Register, $mem$$Address);
11880 %}
11881 ins_pipe(ialu_cr_reg_mem);
11882 %}
11883
11884 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11885 match(Set cr (CmpN op1 op2));
11886
11887 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11888 ins_encode %{
11889 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11890 %}
11891 ins_pipe(ialu_cr_reg_imm);
11892 %}
11893
11894 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11895 %{
11896 match(Set cr (CmpN src (LoadN mem)));
11897
11898 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11899 ins_encode %{
11900 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11901 %}
11902 ins_pipe(ialu_cr_reg_mem);
11903 %}
11904
11905 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11906 match(Set cr (CmpN op1 op2));
11907
11908 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11909 ins_encode %{
11910 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11911 %}
11912 ins_pipe(ialu_cr_reg_imm);
11913 %}
11914
11915 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11916 %{
11917 match(Set cr (CmpN src (LoadNKlass mem)));
11918
11919 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11920 ins_encode %{
11921 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11922 %}
11923 ins_pipe(ialu_cr_reg_mem);
11924 %}
11925
11926 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11927 match(Set cr (CmpN src zero));
11928
11929 format %{ "testl $src, $src\t# compressed ptr" %}
11930 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11931 ins_pipe(ialu_cr_reg_imm);
11932 %}
11933
11934 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11935 %{
11936 predicate(CompressedOops::base() != NULL);
11937 match(Set cr (CmpN (LoadN mem) zero));
11938
11939 ins_cost(500); // XXX
11940 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11941 ins_encode %{
11942 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11943 %}
11944 ins_pipe(ialu_cr_reg_mem);
11945 %}
11946
11947 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11948 %{
11949 predicate(CompressedOops::base() == NULL && (CompressedKlassPointers::base() == NULL));
11950 match(Set cr (CmpN (LoadN mem) zero));
11951
11952 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11953 ins_encode %{
11954 __ cmpl(r12, $mem$$Address);
11955 %}
11956 ins_pipe(ialu_cr_reg_mem);
11957 %}
11958
11959 // Yanked all unsigned pointer compare operations.
11960 // Pointer compares are done with CmpP which is already unsigned.
11961
11962 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11963 %{
11964 match(Set cr (CmpL op1 op2));
11965
11966 format %{ "cmpq $op1, $op2" %}
11967 opcode(0x3B); /* Opcode 3B /r */
11968 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11969 ins_pipe(ialu_cr_reg_reg);
11970 %}
11971
11972 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11973 %{
11974 match(Set cr (CmpL op1 op2));
11975
11976 format %{ "cmpq $op1, $op2" %}
11977 opcode(0x81, 0x07); /* Opcode 81 /7 */
11978 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11979 ins_pipe(ialu_cr_reg_imm);
11980 %}
11981
11982 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11983 %{
11984 match(Set cr (CmpL op1 (LoadL op2)));
11985
11986 format %{ "cmpq $op1, $op2" %}
11987 opcode(0x3B); /* Opcode 3B /r */
11988 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11989 ins_pipe(ialu_cr_reg_mem);
11990 %}
11991
11992 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11993 %{
11994 match(Set cr (CmpL src zero));
11995
11996 format %{ "testq $src, $src" %}
11997 opcode(0x85);
11998 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11999 ins_pipe(ialu_cr_reg_imm);
12000 %}
12001
12002 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12003 %{
12004 match(Set cr (CmpL (AndL src con) zero));
12005
12006 format %{ "testq $src, $con\t# long" %}
12007 opcode(0xF7, 0x00);
12008 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12009 ins_pipe(ialu_cr_reg_imm);
12010 %}
12011
12012 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12013 %{
12014 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12015
12016 format %{ "testq $src, $mem" %}
12017 opcode(0x85);
12018 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12019 ins_pipe(ialu_cr_reg_mem);
12020 %}
12021
12022 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12023 %{
12024 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12025
12026 format %{ "testq $src, $mem" %}
12027 opcode(0x85);
12028 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12029 ins_pipe(ialu_cr_reg_mem);
12030 %}
12031
12032 // Manifest a CmpL result in an integer register. Very painful.
12033 // This is the test to avoid.
12034 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12035 %{
12036 match(Set dst (CmpL3 src1 src2));
12037 effect(KILL flags);
12038
12039 ins_cost(275); // XXX
12040 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12041 "movl $dst, -1\n\t"
12042 "jl,s done\n\t"
12043 "setne $dst\n\t"
12044 "movzbl $dst, $dst\n\t"
12045 "done:" %}
12046 ins_encode(cmpl3_flag(src1, src2, dst));
12047 ins_pipe(pipe_slow);
12048 %}
12049
12050 // Unsigned long compare Instructions; really, same as signed long except they
12051 // produce an rFlagsRegU instead of rFlagsReg.
12052 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12053 %{
12054 match(Set cr (CmpUL op1 op2));
12055
12056 format %{ "cmpq $op1, $op2\t# unsigned" %}
12057 opcode(0x3B); /* Opcode 3B /r */
12058 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12059 ins_pipe(ialu_cr_reg_reg);
12060 %}
12061
12062 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12063 %{
12064 match(Set cr (CmpUL op1 op2));
12065
12066 format %{ "cmpq $op1, $op2\t# unsigned" %}
12067 opcode(0x81, 0x07); /* Opcode 81 /7 */
12068 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12069 ins_pipe(ialu_cr_reg_imm);
12070 %}
12071
12072 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12073 %{
12074 match(Set cr (CmpUL op1 (LoadL op2)));
12075
12076 format %{ "cmpq $op1, $op2\t# unsigned" %}
12077 opcode(0x3B); /* Opcode 3B /r */
12078 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12079 ins_pipe(ialu_cr_reg_mem);
12080 %}
12081
12082 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12083 %{
12084 match(Set cr (CmpUL src zero));
12085
12086 format %{ "testq $src, $src\t# unsigned" %}
12087 opcode(0x85);
12088 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12089 ins_pipe(ialu_cr_reg_imm);
12090 %}
12091
12092 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12093 %{
12094 match(Set cr (CmpI (LoadB mem) imm));
12095
12096 ins_cost(125);
12097 format %{ "cmpb $mem, $imm" %}
12098 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12099 ins_pipe(ialu_cr_reg_mem);
12100 %}
12101
12102 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12103 %{
12104 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12105
12106 ins_cost(125);
12107 format %{ "testb $mem, $imm\t# ubyte" %}
12108 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12109 ins_pipe(ialu_cr_reg_mem);
12110 %}
12111
12112 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12113 %{
12114 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12115
12116 ins_cost(125);
12117 format %{ "testb $mem, $imm\t# byte" %}
12118 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12119 ins_pipe(ialu_cr_reg_mem);
12120 %}
12121
12122 //----------Max and Min--------------------------------------------------------
12123 // Min Instructions
12124
12125 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12126 %{
12127 effect(USE_DEF dst, USE src, USE cr);
12128
12129 format %{ "cmovlgt $dst, $src\t# min" %}
12130 opcode(0x0F, 0x4F);
12131 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12132 ins_pipe(pipe_cmov_reg);
12133 %}
12134
12135
12136 instruct minI_rReg(rRegI dst, rRegI src)
12137 %{
12138 match(Set dst (MinI dst src));
12139
12140 ins_cost(200);
12141 expand %{
12142 rFlagsReg cr;
12143 compI_rReg(cr, dst, src);
12144 cmovI_reg_g(dst, src, cr);
12145 %}
12146 %}
12147
12148 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12149 %{
12150 effect(USE_DEF dst, USE src, USE cr);
12151
12152 format %{ "cmovllt $dst, $src\t# max" %}
12153 opcode(0x0F, 0x4C);
12154 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12155 ins_pipe(pipe_cmov_reg);
12156 %}
12157
12158
12159 instruct maxI_rReg(rRegI dst, rRegI src)
12160 %{
12161 match(Set dst (MaxI dst src));
12162
12163 ins_cost(200);
12164 expand %{
12165 rFlagsReg cr;
12166 compI_rReg(cr, dst, src);
12167 cmovI_reg_l(dst, src, cr);
12168 %}
12169 %}
12170
12171 // ============================================================================
12172 // Branch Instructions
12173
12174 // Jump Direct - Label defines a relative address from JMP+1
12175 instruct jmpDir(label labl)
12176 %{
12177 match(Goto);
12178 effect(USE labl);
12179
12180 ins_cost(300);
12181 format %{ "jmp $labl" %}
12182 size(5);
12183 ins_encode %{
12184 Label* L = $labl$$label;
12185 __ jmp(*L, false); // Always long jump
12186 %}
12187 ins_pipe(pipe_jmp);
12188 %}
12189
12190 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12191 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12192 %{
12193 match(If cop cr);
12194 effect(USE labl);
12195
12196 ins_cost(300);
12197 format %{ "j$cop $labl" %}
12198 size(6);
12199 ins_encode %{
12200 Label* L = $labl$$label;
12201 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12202 %}
12203 ins_pipe(pipe_jcc);
12204 %}
12205
12206 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12207 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12208 %{
12209 predicate(!n->has_vector_mask_set());
12210 match(CountedLoopEnd cop cr);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "j$cop $labl\t# loop end" %}
12215 size(6);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12219 %}
12220 ins_pipe(pipe_jcc);
12221 %}
12222
12223 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12224 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12225 predicate(!n->has_vector_mask_set());
12226 match(CountedLoopEnd cop cmp);
12227 effect(USE labl);
12228
12229 ins_cost(300);
12230 format %{ "j$cop,u $labl\t# loop end" %}
12231 size(6);
12232 ins_encode %{
12233 Label* L = $labl$$label;
12234 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12235 %}
12236 ins_pipe(pipe_jcc);
12237 %}
12238
12239 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12240 predicate(!n->has_vector_mask_set());
12241 match(CountedLoopEnd cop cmp);
12242 effect(USE labl);
12243
12244 ins_cost(200);
12245 format %{ "j$cop,u $labl\t# loop end" %}
12246 size(6);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12250 %}
12251 ins_pipe(pipe_jcc);
12252 %}
12253
12254 // mask version
12255 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12256 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12257 %{
12258 predicate(n->has_vector_mask_set());
12259 match(CountedLoopEnd cop cr);
12260 effect(USE labl);
12261
12262 ins_cost(400);
12263 format %{ "j$cop $labl\t# loop end\n\t"
12264 "restorevectmask \t# vector mask restore for loops" %}
12265 size(10);
12266 ins_encode %{
12267 Label* L = $labl$$label;
12268 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12269 __ restorevectmask();
12270 %}
12271 ins_pipe(pipe_jcc);
12272 %}
12273
12274 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12275 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12276 predicate(n->has_vector_mask_set());
12277 match(CountedLoopEnd cop cmp);
12278 effect(USE labl);
12279
12280 ins_cost(400);
12281 format %{ "j$cop,u $labl\t# loop end\n\t"
12282 "restorevectmask \t# vector mask restore for loops" %}
12283 size(10);
12284 ins_encode %{
12285 Label* L = $labl$$label;
12286 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12287 __ restorevectmask();
12288 %}
12289 ins_pipe(pipe_jcc);
12290 %}
12291
12292 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12293 predicate(n->has_vector_mask_set());
12294 match(CountedLoopEnd cop cmp);
12295 effect(USE labl);
12296
12297 ins_cost(300);
12298 format %{ "j$cop,u $labl\t# loop end\n\t"
12299 "restorevectmask \t# vector mask restore for loops" %}
12300 size(10);
12301 ins_encode %{
12302 Label* L = $labl$$label;
12303 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12304 __ restorevectmask();
12305 %}
12306 ins_pipe(pipe_jcc);
12307 %}
12308
12309 // Jump Direct Conditional - using unsigned comparison
12310 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12311 match(If cop cmp);
12312 effect(USE labl);
12313
12314 ins_cost(300);
12315 format %{ "j$cop,u $labl" %}
12316 size(6);
12317 ins_encode %{
12318 Label* L = $labl$$label;
12319 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12320 %}
12321 ins_pipe(pipe_jcc);
12322 %}
12323
12324 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12325 match(If cop cmp);
12326 effect(USE labl);
12327
12328 ins_cost(200);
12329 format %{ "j$cop,u $labl" %}
12330 size(6);
12331 ins_encode %{
12332 Label* L = $labl$$label;
12333 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12334 %}
12335 ins_pipe(pipe_jcc);
12336 %}
12337
12338 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12339 match(If cop cmp);
12340 effect(USE labl);
12341
12342 ins_cost(200);
12343 format %{ $$template
12344 if ($cop$$cmpcode == Assembler::notEqual) {
12345 $$emit$$"jp,u $labl\n\t"
12346 $$emit$$"j$cop,u $labl"
12347 } else {
12348 $$emit$$"jp,u done\n\t"
12349 $$emit$$"j$cop,u $labl\n\t"
12350 $$emit$$"done:"
12351 }
12352 %}
12353 ins_encode %{
12354 Label* l = $labl$$label;
12355 if ($cop$$cmpcode == Assembler::notEqual) {
12356 __ jcc(Assembler::parity, *l, false);
12357 __ jcc(Assembler::notEqual, *l, false);
12358 } else if ($cop$$cmpcode == Assembler::equal) {
12359 Label done;
12360 __ jccb(Assembler::parity, done);
12361 __ jcc(Assembler::equal, *l, false);
12362 __ bind(done);
12363 } else {
12364 ShouldNotReachHere();
12365 }
12366 %}
12367 ins_pipe(pipe_jcc);
12368 %}
12369
12370 // ============================================================================
12371 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12372 // superklass array for an instance of the superklass. Set a hidden
12373 // internal cache on a hit (cache is checked with exposed code in
12374 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12375 // encoding ALSO sets flags.
12376
12377 instruct partialSubtypeCheck(rdi_RegP result,
12378 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12379 rFlagsReg cr)
12380 %{
12381 match(Set result (PartialSubtypeCheck sub super));
12382 effect(KILL rcx, KILL cr);
12383
12384 ins_cost(1100); // slightly larger than the next version
12385 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12386 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12387 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12388 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12389 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12390 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12391 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12392 "miss:\t" %}
12393
12394 opcode(0x1); // Force a XOR of RDI
12395 ins_encode(enc_PartialSubtypeCheck());
12396 ins_pipe(pipe_slow);
12397 %}
12398
12399 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12400 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12401 immP0 zero,
12402 rdi_RegP result)
12403 %{
12404 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12405 effect(KILL rcx, KILL result);
12406
12407 ins_cost(1000);
12408 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12409 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12410 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12411 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12412 "jne,s miss\t\t# Missed: flags nz\n\t"
12413 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12414 "miss:\t" %}
12415
12416 opcode(0x0); // No need to XOR RDI
12417 ins_encode(enc_PartialSubtypeCheck());
12418 ins_pipe(pipe_slow);
12419 %}
12420
12421 // ============================================================================
12422 // Branch Instructions -- short offset versions
12423 //
12424 // These instructions are used to replace jumps of a long offset (the default
12425 // match) with jumps of a shorter offset. These instructions are all tagged
12426 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12427 // match rules in general matching. Instead, the ADLC generates a conversion
12428 // method in the MachNode which can be used to do in-place replacement of the
12429 // long variant with the shorter variant. The compiler will determine if a
12430 // branch can be taken by the is_short_branch_offset() predicate in the machine
12431 // specific code section of the file.
12432
12433 // Jump Direct - Label defines a relative address from JMP+1
12434 instruct jmpDir_short(label labl) %{
12435 match(Goto);
12436 effect(USE labl);
12437
12438 ins_cost(300);
12439 format %{ "jmp,s $labl" %}
12440 size(2);
12441 ins_encode %{
12442 Label* L = $labl$$label;
12443 __ jmpb(*L);
12444 %}
12445 ins_pipe(pipe_jmp);
12446 ins_short_branch(1);
12447 %}
12448
12449 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12450 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12451 match(If cop cr);
12452 effect(USE labl);
12453
12454 ins_cost(300);
12455 format %{ "j$cop,s $labl" %}
12456 size(2);
12457 ins_encode %{
12458 Label* L = $labl$$label;
12459 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12460 %}
12461 ins_pipe(pipe_jcc);
12462 ins_short_branch(1);
12463 %}
12464
12465 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12466 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12467 match(CountedLoopEnd cop cr);
12468 effect(USE labl);
12469
12470 ins_cost(300);
12471 format %{ "j$cop,s $labl\t# loop end" %}
12472 size(2);
12473 ins_encode %{
12474 Label* L = $labl$$label;
12475 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12476 %}
12477 ins_pipe(pipe_jcc);
12478 ins_short_branch(1);
12479 %}
12480
12481 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12482 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12483 match(CountedLoopEnd cop cmp);
12484 effect(USE labl);
12485
12486 ins_cost(300);
12487 format %{ "j$cop,us $labl\t# loop end" %}
12488 size(2);
12489 ins_encode %{
12490 Label* L = $labl$$label;
12491 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12492 %}
12493 ins_pipe(pipe_jcc);
12494 ins_short_branch(1);
12495 %}
12496
12497 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12498 match(CountedLoopEnd cop cmp);
12499 effect(USE labl);
12500
12501 ins_cost(300);
12502 format %{ "j$cop,us $labl\t# loop end" %}
12503 size(2);
12504 ins_encode %{
12505 Label* L = $labl$$label;
12506 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12507 %}
12508 ins_pipe(pipe_jcc);
12509 ins_short_branch(1);
12510 %}
12511
12512 // Jump Direct Conditional - using unsigned comparison
12513 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12514 match(If cop cmp);
12515 effect(USE labl);
12516
12517 ins_cost(300);
12518 format %{ "j$cop,us $labl" %}
12519 size(2);
12520 ins_encode %{
12521 Label* L = $labl$$label;
12522 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12523 %}
12524 ins_pipe(pipe_jcc);
12525 ins_short_branch(1);
12526 %}
12527
12528 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12529 match(If cop cmp);
12530 effect(USE labl);
12531
12532 ins_cost(300);
12533 format %{ "j$cop,us $labl" %}
12534 size(2);
12535 ins_encode %{
12536 Label* L = $labl$$label;
12537 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12538 %}
12539 ins_pipe(pipe_jcc);
12540 ins_short_branch(1);
12541 %}
12542
12543 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12544 match(If cop cmp);
12545 effect(USE labl);
12546
12547 ins_cost(300);
12548 format %{ $$template
12549 if ($cop$$cmpcode == Assembler::notEqual) {
12550 $$emit$$"jp,u,s $labl\n\t"
12551 $$emit$$"j$cop,u,s $labl"
12552 } else {
12553 $$emit$$"jp,u,s done\n\t"
12554 $$emit$$"j$cop,u,s $labl\n\t"
12555 $$emit$$"done:"
12556 }
12557 %}
12558 size(4);
12559 ins_encode %{
12560 Label* l = $labl$$label;
12561 if ($cop$$cmpcode == Assembler::notEqual) {
12562 __ jccb(Assembler::parity, *l);
12563 __ jccb(Assembler::notEqual, *l);
12564 } else if ($cop$$cmpcode == Assembler::equal) {
12565 Label done;
12566 __ jccb(Assembler::parity, done);
12567 __ jccb(Assembler::equal, *l);
12568 __ bind(done);
12569 } else {
12570 ShouldNotReachHere();
12571 }
12572 %}
12573 ins_pipe(pipe_jcc);
12574 ins_short_branch(1);
12575 %}
12576
12577 // ============================================================================
12578 // inlined locking and unlocking
12579
12580 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12581 predicate(Compile::current()->use_rtm());
12582 match(Set cr (FastLock object box));
12583 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12584 ins_cost(300);
12585 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12586 ins_encode %{
12587 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12588 $scr$$Register, $cx1$$Register, $cx2$$Register,
12589 _counters, _rtm_counters, _stack_rtm_counters,
12590 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12591 true, ra_->C->profile_rtm());
12592 %}
12593 ins_pipe(pipe_slow);
12594 %}
12595
12596 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12597 predicate(!Compile::current()->use_rtm());
12598 match(Set cr (FastLock object box));
12599 effect(TEMP tmp, TEMP scr, USE_KILL box);
12600 ins_cost(300);
12601 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12602 ins_encode %{
12603 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12604 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12605 %}
12606 ins_pipe(pipe_slow);
12607 %}
12608
12609 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12610 match(Set cr (FastUnlock object box));
12611 effect(TEMP tmp, USE_KILL box);
12612 ins_cost(300);
12613 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12614 ins_encode %{
12615 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12616 %}
12617 ins_pipe(pipe_slow);
12618 %}
12619
12620
12621 // ============================================================================
12622 // Safepoint Instructions
12623 instruct safePoint_poll(rFlagsReg cr)
12624 %{
12625 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12626 match(SafePoint);
12627 effect(KILL cr);
12628
12629 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12630 "# Safepoint: poll for GC" %}
12631 ins_cost(125);
12632 ins_encode %{
12633 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12634 __ testl(rax, addr);
12635 %}
12636 ins_pipe(ialu_reg_mem);
12637 %}
12638
12639 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12640 %{
12641 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12642 match(SafePoint poll);
12643 effect(KILL cr, USE poll);
12644
12645 format %{ "testl rax, [$poll]\t"
12646 "# Safepoint: poll for GC" %}
12647 ins_cost(125);
12648 ins_encode %{
12649 __ relocate(relocInfo::poll_type);
12650 __ testl(rax, Address($poll$$Register, 0));
12651 %}
12652 ins_pipe(ialu_reg_mem);
12653 %}
12654
12655 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12656 %{
12657 predicate(SafepointMechanism::uses_thread_local_poll());
12658 match(SafePoint poll);
12659 effect(KILL cr, USE poll);
12660
12661 format %{ "testl rax, [$poll]\t"
12662 "# Safepoint: poll for GC" %}
12663 ins_cost(125);
12664 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12665 ins_encode %{
12666 __ relocate(relocInfo::poll_type);
12667 address pre_pc = __ pc();
12668 __ testl(rax, Address($poll$$Register, 0));
12669 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12670 %}
12671 ins_pipe(ialu_reg_mem);
12672 %}
12673
12674 // ============================================================================
12675 // Procedure Call/Return Instructions
12676 // Call Java Static Instruction
12677 // Note: If this code changes, the corresponding ret_addr_offset() and
12678 // compute_padding() functions will have to be adjusted.
12679 instruct CallStaticJavaDirect(method meth) %{
12680 match(CallStaticJava);
12681 effect(USE meth);
12682
12683 ins_cost(300);
12684 format %{ "call,static " %}
12685 opcode(0xE8); /* E8 cd */
12686 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12687 ins_pipe(pipe_slow);
12688 ins_alignment(4);
12689 %}
12690
12691 // Call Java Dynamic Instruction
12692 // Note: If this code changes, the corresponding ret_addr_offset() and
12693 // compute_padding() functions will have to be adjusted.
12694 instruct CallDynamicJavaDirect(method meth)
12695 %{
12696 match(CallDynamicJava);
12697 effect(USE meth);
12698
12699 ins_cost(300);
12700 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12701 "call,dynamic " %}
12702 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12703 ins_pipe(pipe_slow);
12704 ins_alignment(4);
12705 %}
12706
12707 // Call Runtime Instruction
12708 instruct CallRuntimeDirect(method meth)
12709 %{
12710 match(CallRuntime);
12711 effect(USE meth);
12712
12713 ins_cost(300);
12714 format %{ "call,runtime " %}
12715 ins_encode(clear_avx, Java_To_Runtime(meth));
12716 ins_pipe(pipe_slow);
12717 %}
12718
12719 // Call runtime without safepoint
12720 instruct CallLeafDirect(method meth)
12721 %{
12722 match(CallLeaf);
12723 effect(USE meth);
12724
12725 ins_cost(300);
12726 format %{ "call_leaf,runtime " %}
12727 ins_encode(clear_avx, Java_To_Runtime(meth));
12728 ins_pipe(pipe_slow);
12729 %}
12730
12731 // Call runtime without safepoint
12732 instruct CallLeafNoFPDirect(method meth)
12733 %{
12734 match(CallLeafNoFP);
12735 effect(USE meth);
12736
12737 ins_cost(300);
12738 format %{ "call_leaf_nofp,runtime " %}
12739 ins_encode(clear_avx, Java_To_Runtime(meth));
12740 ins_pipe(pipe_slow);
12741 %}
12742
12743 // Return Instruction
12744 // Remove the return address & jump to it.
12745 // Notice: We always emit a nop after a ret to make sure there is room
12746 // for safepoint patching
12747 instruct Ret()
12748 %{
12749 match(Return);
12750
12751 format %{ "ret" %}
12752 opcode(0xC3);
12753 ins_encode(OpcP);
12754 ins_pipe(pipe_jmp);
12755 %}
12756
12757 // Tail Call; Jump from runtime stub to Java code.
12758 // Also known as an 'interprocedural jump'.
12759 // Target of jump will eventually return to caller.
12760 // TailJump below removes the return address.
12761 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12762 %{
12763 match(TailCall jump_target method_oop);
12764
12765 ins_cost(300);
12766 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12767 opcode(0xFF, 0x4); /* Opcode FF /4 */
12768 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12769 ins_pipe(pipe_jmp);
12770 %}
12771
12772 // Tail Jump; remove the return address; jump to target.
12773 // TailCall above leaves the return address around.
12774 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12775 %{
12776 match(TailJump jump_target ex_oop);
12777
12778 ins_cost(300);
12779 format %{ "popq rdx\t# pop return address\n\t"
12780 "jmp $jump_target" %}
12781 opcode(0xFF, 0x4); /* Opcode FF /4 */
12782 ins_encode(Opcode(0x5a), // popq rdx
12783 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12784 ins_pipe(pipe_jmp);
12785 %}
12786
12787 // Create exception oop: created by stack-crawling runtime code.
12788 // Created exception is now available to this handler, and is setup
12789 // just prior to jumping to this handler. No code emitted.
12790 instruct CreateException(rax_RegP ex_oop)
12791 %{
12792 match(Set ex_oop (CreateEx));
12793
12794 size(0);
12795 // use the following format syntax
12796 format %{ "# exception oop is in rax; no code emitted" %}
12797 ins_encode();
12798 ins_pipe(empty);
12799 %}
12800
12801 // Rethrow exception:
12802 // The exception oop will come in the first argument position.
12803 // Then JUMP (not call) to the rethrow stub code.
12804 instruct RethrowException()
12805 %{
12806 match(Rethrow);
12807
12808 // use the following format syntax
12809 format %{ "jmp rethrow_stub" %}
12810 ins_encode(enc_rethrow);
12811 ins_pipe(pipe_jmp);
12812 %}
12813
12814 // ============================================================================
12815 // This name is KNOWN by the ADLC and cannot be changed.
12816 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12817 // for this guy.
12818 instruct tlsLoadP(r15_RegP dst) %{
12819 match(Set dst (ThreadLocal));
12820 effect(DEF dst);
12821
12822 size(0);
12823 format %{ "# TLS is in R15" %}
12824 ins_encode( /*empty encoding*/ );
12825 ins_pipe(ialu_reg_reg);
12826 %}
12827
12828
12829 //----------PEEPHOLE RULES-----------------------------------------------------
12830 // These must follow all instruction definitions as they use the names
12831 // defined in the instructions definitions.
12832 //
12833 // peepmatch ( root_instr_name [preceding_instruction]* );
12834 //
12835 // peepconstraint %{
12836 // (instruction_number.operand_name relational_op instruction_number.operand_name
12837 // [, ...] );
12838 // // instruction numbers are zero-based using left to right order in peepmatch
12839 //
12840 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12841 // // provide an instruction_number.operand_name for each operand that appears
12842 // // in the replacement instruction's match rule
12843 //
12844 // ---------VM FLAGS---------------------------------------------------------
12845 //
12846 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12847 //
12848 // Each peephole rule is given an identifying number starting with zero and
12849 // increasing by one in the order seen by the parser. An individual peephole
12850 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12851 // on the command-line.
12852 //
12853 // ---------CURRENT LIMITATIONS----------------------------------------------
12854 //
12855 // Only match adjacent instructions in same basic block
12856 // Only equality constraints
12857 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12858 // Only one replacement instruction
12859 //
12860 // ---------EXAMPLE----------------------------------------------------------
12861 //
12862 // // pertinent parts of existing instructions in architecture description
12863 // instruct movI(rRegI dst, rRegI src)
12864 // %{
12865 // match(Set dst (CopyI src));
12866 // %}
12867 //
12868 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12869 // %{
12870 // match(Set dst (AddI dst src));
12871 // effect(KILL cr);
12872 // %}
12873 //
12874 // // Change (inc mov) to lea
12875 // peephole %{
12876 // // increment preceeded by register-register move
12877 // peepmatch ( incI_rReg movI );
12878 // // require that the destination register of the increment
12879 // // match the destination register of the move
12880 // peepconstraint ( 0.dst == 1.dst );
12881 // // construct a replacement instruction that sets
12882 // // the destination to ( move's source register + one )
12883 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12884 // %}
12885 //
12886
12887 // Implementation no longer uses movX instructions since
12888 // machine-independent system no longer uses CopyX nodes.
12889 //
12890 // peephole
12891 // %{
12892 // peepmatch (incI_rReg movI);
12893 // peepconstraint (0.dst == 1.dst);
12894 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12895 // %}
12896
12897 // peephole
12898 // %{
12899 // peepmatch (decI_rReg movI);
12900 // peepconstraint (0.dst == 1.dst);
12901 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12902 // %}
12903
12904 // peephole
12905 // %{
12906 // peepmatch (addI_rReg_imm movI);
12907 // peepconstraint (0.dst == 1.dst);
12908 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12909 // %}
12910
12911 // peephole
12912 // %{
12913 // peepmatch (incL_rReg movL);
12914 // peepconstraint (0.dst == 1.dst);
12915 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12916 // %}
12917
12918 // peephole
12919 // %{
12920 // peepmatch (decL_rReg movL);
12921 // peepconstraint (0.dst == 1.dst);
12922 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12923 // %}
12924
12925 // peephole
12926 // %{
12927 // peepmatch (addL_rReg_imm movL);
12928 // peepconstraint (0.dst == 1.dst);
12929 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12930 // %}
12931
12932 // peephole
12933 // %{
12934 // peepmatch (addP_rReg_imm movP);
12935 // peepconstraint (0.dst == 1.dst);
12936 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12937 // %}
12938
12939 // // Change load of spilled value to only a spill
12940 // instruct storeI(memory mem, rRegI src)
12941 // %{
12942 // match(Set mem (StoreI mem src));
12943 // %}
12944 //
12945 // instruct loadI(rRegI dst, memory mem)
12946 // %{
12947 // match(Set dst (LoadI mem));
12948 // %}
12949 //
12950
12951 peephole
12952 %{
12953 peepmatch (loadI storeI);
12954 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12955 peepreplace (storeI(1.mem 1.mem 1.src));
12956 %}
12957
12958 peephole
12959 %{
12960 peepmatch (loadL storeL);
12961 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12962 peepreplace (storeL(1.mem 1.mem 1.src));
12963 %}
12964
12965 //----------SMARTSPILL RULES---------------------------------------------------
12966 // These must follow all instruction definitions as they use the names
12967 // defined in the instructions definitions.