1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "gc/shared/barrierSet.hpp" 27 #include "gc/shared/c2/barrierSetC2.hpp" 28 #include "memory/allocation.inline.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "oops/compressedOops.hpp" 31 #include "opto/ad.hpp" 32 #include "opto/addnode.hpp" 33 #include "opto/callnode.hpp" 34 #include "opto/idealGraphPrinter.hpp" 35 #include "opto/matcher.hpp" 36 #include "opto/memnode.hpp" 37 #include "opto/movenode.hpp" 38 #include "opto/opcodes.hpp" 39 #include "opto/regmask.hpp" 40 #include "opto/rootnode.hpp" 41 #include "opto/runtime.hpp" 42 #include "opto/type.hpp" 43 #include "opto/vectornode.hpp" 44 #include "runtime/os.hpp" 45 #include "runtime/sharedRuntime.hpp" 46 #include "utilities/align.hpp" 47 48 OptoReg::Name OptoReg::c_frame_pointer; 49 50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 51 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 52 RegMask Matcher::STACK_ONLY_mask; 53 RegMask Matcher::c_frame_ptr_mask; 54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 55 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 56 57 //---------------------------Matcher------------------------------------------- 58 Matcher::Matcher() 59 : PhaseTransform( Phase::Ins_Select ), 60 _states_arena(Chunk::medium_size, mtCompiler), 61 _visited(&_states_arena), 62 _shared(&_states_arena), 63 _dontcare(&_states_arena), 64 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 65 _swallowed(swallowed), 66 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 67 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 68 _must_clone(must_clone), 69 _shared_nodes(C->comp_arena()), 70 #ifdef ASSERT 71 _old2new_map(C->comp_arena()), 72 _new2old_map(C->comp_arena()), 73 #endif 74 _allocation_started(false), 75 _ruleName(ruleName), 76 _register_save_policy(register_save_policy), 77 _c_reg_save_policy(c_reg_save_policy), 78 _register_save_type(register_save_type) { 79 C->set_matcher(this); 80 81 idealreg2spillmask [Op_RegI] = NULL; 82 idealreg2spillmask [Op_RegN] = NULL; 83 idealreg2spillmask [Op_RegL] = NULL; 84 idealreg2spillmask [Op_RegF] = NULL; 85 idealreg2spillmask [Op_RegD] = NULL; 86 idealreg2spillmask [Op_RegP] = NULL; 87 idealreg2spillmask [Op_VecS] = NULL; 88 idealreg2spillmask [Op_VecD] = NULL; 89 idealreg2spillmask [Op_VecX] = NULL; 90 idealreg2spillmask [Op_VecY] = NULL; 91 idealreg2spillmask [Op_VecZ] = NULL; 92 idealreg2spillmask [Op_RegFlags] = NULL; 93 94 idealreg2debugmask [Op_RegI] = NULL; 95 idealreg2debugmask [Op_RegN] = NULL; 96 idealreg2debugmask [Op_RegL] = NULL; 97 idealreg2debugmask [Op_RegF] = NULL; 98 idealreg2debugmask [Op_RegD] = NULL; 99 idealreg2debugmask [Op_RegP] = NULL; 100 idealreg2debugmask [Op_VecS] = NULL; 101 idealreg2debugmask [Op_VecD] = NULL; 102 idealreg2debugmask [Op_VecX] = NULL; 103 idealreg2debugmask [Op_VecY] = NULL; 104 idealreg2debugmask [Op_VecZ] = NULL; 105 idealreg2debugmask [Op_RegFlags] = NULL; 106 107 idealreg2mhdebugmask[Op_RegI] = NULL; 108 idealreg2mhdebugmask[Op_RegN] = NULL; 109 idealreg2mhdebugmask[Op_RegL] = NULL; 110 idealreg2mhdebugmask[Op_RegF] = NULL; 111 idealreg2mhdebugmask[Op_RegD] = NULL; 112 idealreg2mhdebugmask[Op_RegP] = NULL; 113 idealreg2mhdebugmask[Op_VecS] = NULL; 114 idealreg2mhdebugmask[Op_VecD] = NULL; 115 idealreg2mhdebugmask[Op_VecX] = NULL; 116 idealreg2mhdebugmask[Op_VecY] = NULL; 117 idealreg2mhdebugmask[Op_VecZ] = NULL; 118 idealreg2mhdebugmask[Op_RegFlags] = NULL; 119 120 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 121 } 122 123 //------------------------------warp_incoming_stk_arg------------------------ 124 // This warps a VMReg into an OptoReg::Name 125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 126 OptoReg::Name warped; 127 if( reg->is_stack() ) { // Stack slot argument? 128 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 129 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 130 if( warped >= _in_arg_limit ) 131 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 132 if (!RegMask::can_represent_arg(warped)) { 133 // the compiler cannot represent this method's calling sequence 134 C->record_method_not_compilable("unsupported incoming calling sequence"); 135 return OptoReg::Bad; 136 } 137 return warped; 138 } 139 return OptoReg::as_OptoReg(reg); 140 } 141 142 //---------------------------compute_old_SP------------------------------------ 143 OptoReg::Name Compile::compute_old_SP() { 144 int fixed = fixed_slots(); 145 int preserve = in_preserve_stack_slots(); 146 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots())); 147 } 148 149 150 151 #ifdef ASSERT 152 void Matcher::verify_new_nodes_only(Node* xroot) { 153 // Make sure that the new graph only references new nodes 154 ResourceMark rm; 155 Unique_Node_List worklist; 156 VectorSet visited(Thread::current()->resource_area()); 157 worklist.push(xroot); 158 while (worklist.size() > 0) { 159 Node* n = worklist.pop(); 160 visited <<= n->_idx; 161 assert(C->node_arena()->contains(n), "dead node"); 162 for (uint j = 0; j < n->req(); j++) { 163 Node* in = n->in(j); 164 if (in != NULL) { 165 assert(C->node_arena()->contains(in), "dead node"); 166 if (!visited.test(in->_idx)) { 167 worklist.push(in); 168 } 169 } 170 } 171 } 172 } 173 #endif 174 175 176 //---------------------------match--------------------------------------------- 177 void Matcher::match( ) { 178 if( MaxLabelRootDepth < 100 ) { // Too small? 179 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 180 MaxLabelRootDepth = 100; 181 } 182 // One-time initialization of some register masks. 183 init_spill_mask( C->root()->in(1) ); 184 _return_addr_mask = return_addr(); 185 #ifdef _LP64 186 // Pointers take 2 slots in 64-bit land 187 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 188 #endif 189 190 // Map a Java-signature return type into return register-value 191 // machine registers for 0, 1 and 2 returned values. 192 const TypeTuple *range = C->tf()->range(); 193 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 194 // Get ideal-register return type 195 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 196 // Get machine return register 197 uint sop = C->start()->Opcode(); 198 OptoRegPair regs = return_value(ireg, false); 199 200 // And mask for same 201 _return_value_mask = RegMask(regs.first()); 202 if( OptoReg::is_valid(regs.second()) ) 203 _return_value_mask.Insert(regs.second()); 204 } 205 206 // --------------- 207 // Frame Layout 208 209 // Need the method signature to determine the incoming argument types, 210 // because the types determine which registers the incoming arguments are 211 // in, and this affects the matched code. 212 const TypeTuple *domain = C->tf()->domain(); 213 uint argcnt = domain->cnt() - TypeFunc::Parms; 214 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 215 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 216 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 217 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 218 uint i; 219 for( i = 0; i<argcnt; i++ ) { 220 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 221 } 222 223 // Pass array of ideal registers and length to USER code (from the AD file) 224 // that will convert this to an array of register numbers. 225 const StartNode *start = C->start(); 226 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 227 #ifdef ASSERT 228 // Sanity check users' calling convention. Real handy while trying to 229 // get the initial port correct. 230 { for (uint i = 0; i<argcnt; i++) { 231 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 232 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 233 _parm_regs[i].set_bad(); 234 continue; 235 } 236 VMReg parm_reg = vm_parm_regs[i].first(); 237 assert(parm_reg->is_valid(), "invalid arg?"); 238 if (parm_reg->is_reg()) { 239 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 240 assert(can_be_java_arg(opto_parm_reg) || 241 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 242 opto_parm_reg == inline_cache_reg(), 243 "parameters in register must be preserved by runtime stubs"); 244 } 245 for (uint j = 0; j < i; j++) { 246 assert(parm_reg != vm_parm_regs[j].first(), 247 "calling conv. must produce distinct regs"); 248 } 249 } 250 } 251 #endif 252 253 // Do some initial frame layout. 254 255 // Compute the old incoming SP (may be called FP) as 256 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 257 _old_SP = C->compute_old_SP(); 258 assert( is_even(_old_SP), "must be even" ); 259 260 // Compute highest incoming stack argument as 261 // _old_SP + out_preserve_stack_slots + incoming argument size. 262 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 263 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 264 for( i = 0; i < argcnt; i++ ) { 265 // Permit args to have no register 266 _calling_convention_mask[i].Clear(); 267 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 268 continue; 269 } 270 // calling_convention returns stack arguments as a count of 271 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 272 // the allocators point of view, taking into account all the 273 // preserve area, locks & pad2. 274 275 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 276 if( OptoReg::is_valid(reg1)) 277 _calling_convention_mask[i].Insert(reg1); 278 279 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 280 if( OptoReg::is_valid(reg2)) 281 _calling_convention_mask[i].Insert(reg2); 282 283 // Saved biased stack-slot register number 284 _parm_regs[i].set_pair(reg2, reg1); 285 } 286 287 // Finally, make sure the incoming arguments take up an even number of 288 // words, in case the arguments or locals need to contain doubleword stack 289 // slots. The rest of the system assumes that stack slot pairs (in 290 // particular, in the spill area) which look aligned will in fact be 291 // aligned relative to the stack pointer in the target machine. Double 292 // stack slots will always be allocated aligned. 293 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong)); 294 295 // Compute highest outgoing stack argument as 296 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 297 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 298 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 299 300 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 301 // the compiler cannot represent this method's calling sequence 302 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 303 } 304 305 if (C->failing()) return; // bailed out on incoming arg failure 306 307 // --------------- 308 // Collect roots of matcher trees. Every node for which 309 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 310 // can be a valid interior of some tree. 311 find_shared( C->root() ); 312 find_shared( C->top() ); 313 314 C->print_method(PHASE_BEFORE_MATCHING); 315 316 // Create new ideal node ConP #NULL even if it does exist in old space 317 // to avoid false sharing if the corresponding mach node is not used. 318 // The corresponding mach node is only used in rare cases for derived 319 // pointers. 320 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 321 322 // Swap out to old-space; emptying new-space 323 Arena *old = C->node_arena()->move_contents(C->old_arena()); 324 325 // Save debug and profile information for nodes in old space: 326 _old_node_note_array = C->node_note_array(); 327 if (_old_node_note_array != NULL) { 328 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 329 (C->comp_arena(), _old_node_note_array->length(), 330 0, NULL)); 331 } 332 333 // Pre-size the new_node table to avoid the need for range checks. 334 grow_new_node_array(C->unique()); 335 336 // Reset node counter so MachNodes start with _idx at 0 337 int live_nodes = C->live_nodes(); 338 C->set_unique(0); 339 C->reset_dead_node_list(); 340 341 // Recursively match trees from old space into new space. 342 // Correct leaves of new-space Nodes; they point to old-space. 343 _visited.Clear(); // Clear visit bits for xform call 344 C->set_cached_top_node(xform( C->top(), live_nodes )); 345 if (!C->failing()) { 346 Node* xroot = xform( C->root(), 1 ); 347 if (xroot == NULL) { 348 Matcher::soft_match_failure(); // recursive matching process failed 349 C->record_method_not_compilable("instruction match failed"); 350 } else { 351 // During matching shared constants were attached to C->root() 352 // because xroot wasn't available yet, so transfer the uses to 353 // the xroot. 354 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 355 Node* n = C->root()->fast_out(j); 356 if (C->node_arena()->contains(n)) { 357 assert(n->in(0) == C->root(), "should be control user"); 358 n->set_req(0, xroot); 359 --j; 360 --jmax; 361 } 362 } 363 364 // Generate new mach node for ConP #NULL 365 assert(new_ideal_null != NULL, "sanity"); 366 _mach_null = match_tree(new_ideal_null); 367 // Don't set control, it will confuse GCM since there are no uses. 368 // The control will be set when this node is used first time 369 // in find_base_for_derived(). 370 assert(_mach_null != NULL, ""); 371 372 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 373 374 #ifdef ASSERT 375 verify_new_nodes_only(xroot); 376 #endif 377 } 378 } 379 if (C->top() == NULL || C->root() == NULL) { 380 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 381 } 382 if (C->failing()) { 383 // delete old; 384 old->destruct_contents(); 385 return; 386 } 387 assert( C->top(), "" ); 388 assert( C->root(), "" ); 389 validate_null_checks(); 390 391 // Now smoke old-space 392 NOT_DEBUG( old->destruct_contents() ); 393 394 // ------------------------ 395 // Set up save-on-entry registers 396 Fixup_Save_On_Entry( ); 397 } 398 399 400 //------------------------------Fixup_Save_On_Entry---------------------------- 401 // The stated purpose of this routine is to take care of save-on-entry 402 // registers. However, the overall goal of the Match phase is to convert into 403 // machine-specific instructions which have RegMasks to guide allocation. 404 // So what this procedure really does is put a valid RegMask on each input 405 // to the machine-specific variations of all Return, TailCall and Halt 406 // instructions. It also adds edgs to define the save-on-entry values (and of 407 // course gives them a mask). 408 409 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 410 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 411 // Do all the pre-defined register masks 412 rms[TypeFunc::Control ] = RegMask::Empty; 413 rms[TypeFunc::I_O ] = RegMask::Empty; 414 rms[TypeFunc::Memory ] = RegMask::Empty; 415 rms[TypeFunc::ReturnAdr] = ret_adr; 416 rms[TypeFunc::FramePtr ] = fp; 417 return rms; 418 } 419 420 #define NOF_STACK_MASKS (3*6+5) 421 422 // Create the initial stack mask used by values spilling to the stack. 423 // Disallow any debug info in outgoing argument areas by setting the 424 // initial mask accordingly. 425 void Matcher::init_first_stack_mask() { 426 427 // Allocate storage for spill masks as masks for the appropriate load type. 428 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * NOF_STACK_MASKS); 429 430 // Initialize empty placeholder masks into the newly allocated arena 431 for (int i = 0; i < NOF_STACK_MASKS; i++) { 432 new (rms + i) RegMask(); 433 } 434 435 idealreg2spillmask [Op_RegN] = &rms[0]; 436 idealreg2spillmask [Op_RegI] = &rms[1]; 437 idealreg2spillmask [Op_RegL] = &rms[2]; 438 idealreg2spillmask [Op_RegF] = &rms[3]; 439 idealreg2spillmask [Op_RegD] = &rms[4]; 440 idealreg2spillmask [Op_RegP] = &rms[5]; 441 442 idealreg2debugmask [Op_RegN] = &rms[6]; 443 idealreg2debugmask [Op_RegI] = &rms[7]; 444 idealreg2debugmask [Op_RegL] = &rms[8]; 445 idealreg2debugmask [Op_RegF] = &rms[9]; 446 idealreg2debugmask [Op_RegD] = &rms[10]; 447 idealreg2debugmask [Op_RegP] = &rms[11]; 448 449 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 450 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 451 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 452 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 453 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 454 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 455 456 idealreg2spillmask [Op_VecS] = &rms[18]; 457 idealreg2spillmask [Op_VecD] = &rms[19]; 458 idealreg2spillmask [Op_VecX] = &rms[20]; 459 idealreg2spillmask [Op_VecY] = &rms[21]; 460 idealreg2spillmask [Op_VecZ] = &rms[22]; 461 462 OptoReg::Name i; 463 464 // At first, start with the empty mask 465 C->FIRST_STACK_mask().Clear(); 466 467 // Add in the incoming argument area 468 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 469 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 470 C->FIRST_STACK_mask().Insert(i); 471 } 472 // Add in all bits past the outgoing argument area 473 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 474 "must be able to represent all call arguments in reg mask"); 475 OptoReg::Name init = _out_arg_limit; 476 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 477 C->FIRST_STACK_mask().Insert(i); 478 } 479 // Finally, set the "infinite stack" bit. 480 C->FIRST_STACK_mask().set_AllStack(); 481 482 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 483 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 484 // Keep spill masks aligned. 485 aligned_stack_mask.clear_to_pairs(); 486 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 487 488 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 489 #ifdef _LP64 490 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 491 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 492 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 493 #else 494 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 495 #endif 496 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 497 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 498 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 499 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 500 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 501 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 502 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 503 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 504 505 if (Matcher::vector_size_supported(T_BYTE,4)) { 506 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 507 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 508 } 509 if (Matcher::vector_size_supported(T_FLOAT,2)) { 510 // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 511 // RA guarantees such alignment since it is needed for Double and Long values. 512 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 513 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 514 } 515 if (Matcher::vector_size_supported(T_FLOAT,4)) { 516 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 517 // 518 // RA can use input arguments stack slots for spills but until RA 519 // we don't know frame size and offset of input arg stack slots. 520 // 521 // Exclude last input arg stack slots to avoid spilling vectors there 522 // otherwise vector spills could stomp over stack slots in caller frame. 523 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 524 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 525 aligned_stack_mask.Remove(in); 526 in = OptoReg::add(in, -1); 527 } 528 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 529 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 530 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 531 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 532 } 533 if (Matcher::vector_size_supported(T_FLOAT,8)) { 534 // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 535 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 536 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 537 aligned_stack_mask.Remove(in); 538 in = OptoReg::add(in, -1); 539 } 540 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 541 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 542 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 543 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 544 } 545 if (Matcher::vector_size_supported(T_FLOAT,16)) { 546 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 547 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 548 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 549 aligned_stack_mask.Remove(in); 550 in = OptoReg::add(in, -1); 551 } 552 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 553 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 554 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 555 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 556 } 557 if (UseFPUForSpilling) { 558 // This mask logic assumes that the spill operations are 559 // symmetric and that the registers involved are the same size. 560 // On sparc for instance we may have to use 64 bit moves will 561 // kill 2 registers when used with F0-F31. 562 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 563 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 564 #ifdef _LP64 565 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 566 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 567 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 568 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 569 #else 570 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 571 #ifdef ARM 572 // ARM has support for moving 64bit values between a pair of 573 // integer registers and a double register 574 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 575 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 576 #endif 577 #endif 578 } 579 580 // Make up debug masks. Any spill slot plus callee-save registers. 581 // Caller-save registers are assumed to be trashable by the various 582 // inline-cache fixup routines. 583 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 584 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 585 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 586 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 587 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 588 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 589 590 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 591 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 592 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 593 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 594 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 595 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 596 597 // Prevent stub compilations from attempting to reference 598 // callee-saved registers from debug info 599 bool exclude_soe = !Compile::current()->is_method_compilation(); 600 601 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 602 // registers the caller has to save do not work 603 if( _register_save_policy[i] == 'C' || 604 _register_save_policy[i] == 'A' || 605 (_register_save_policy[i] == 'E' && exclude_soe) ) { 606 idealreg2debugmask [Op_RegN]->Remove(i); 607 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 608 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 609 idealreg2debugmask [Op_RegF]->Remove(i); // masks 610 idealreg2debugmask [Op_RegD]->Remove(i); 611 idealreg2debugmask [Op_RegP]->Remove(i); 612 613 idealreg2mhdebugmask[Op_RegN]->Remove(i); 614 idealreg2mhdebugmask[Op_RegI]->Remove(i); 615 idealreg2mhdebugmask[Op_RegL]->Remove(i); 616 idealreg2mhdebugmask[Op_RegF]->Remove(i); 617 idealreg2mhdebugmask[Op_RegD]->Remove(i); 618 idealreg2mhdebugmask[Op_RegP]->Remove(i); 619 } 620 } 621 622 // Subtract the register we use to save the SP for MethodHandle 623 // invokes to from the debug mask. 624 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 625 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 626 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 627 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 628 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 629 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 630 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 631 } 632 633 //---------------------------is_save_on_entry---------------------------------- 634 bool Matcher::is_save_on_entry( int reg ) { 635 return 636 _register_save_policy[reg] == 'E' || 637 _register_save_policy[reg] == 'A' || // Save-on-entry register? 638 // Also save argument registers in the trampolining stubs 639 (C->save_argument_registers() && is_spillable_arg(reg)); 640 } 641 642 //---------------------------Fixup_Save_On_Entry------------------------------- 643 void Matcher::Fixup_Save_On_Entry( ) { 644 init_first_stack_mask(); 645 646 Node *root = C->root(); // Short name for root 647 // Count number of save-on-entry registers. 648 uint soe_cnt = number_of_saved_registers(); 649 uint i; 650 651 // Find the procedure Start Node 652 StartNode *start = C->start(); 653 assert( start, "Expect a start node" ); 654 655 // Save argument registers in the trampolining stubs 656 if( C->save_argument_registers() ) 657 for( i = 0; i < _last_Mach_Reg; i++ ) 658 if( is_spillable_arg(i) ) 659 soe_cnt++; 660 661 // Input RegMask array shared by all Returns. 662 // The type for doubles and longs has a count of 2, but 663 // there is only 1 returned value 664 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 665 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 666 // Returns have 0 or 1 returned values depending on call signature. 667 // Return register is specified by return_value in the AD file. 668 if (ret_edge_cnt > TypeFunc::Parms) 669 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 670 671 // Input RegMask array shared by all Rethrows. 672 uint reth_edge_cnt = TypeFunc::Parms+1; 673 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 674 // Rethrow takes exception oop only, but in the argument 0 slot. 675 OptoReg::Name reg = find_receiver(false); 676 if (reg >= 0) { 677 reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 678 #ifdef _LP64 679 // Need two slots for ptrs in 64-bit land 680 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 681 #endif 682 } 683 684 // Input RegMask array shared by all TailCalls 685 uint tail_call_edge_cnt = TypeFunc::Parms+2; 686 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 687 688 // Input RegMask array shared by all TailJumps 689 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 690 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 691 692 // TailCalls have 2 returned values (target & moop), whose masks come 693 // from the usual MachNode/MachOper mechanism. Find a sample 694 // TailCall to extract these masks and put the correct masks into 695 // the tail_call_rms array. 696 for( i=1; i < root->req(); i++ ) { 697 MachReturnNode *m = root->in(i)->as_MachReturn(); 698 if( m->ideal_Opcode() == Op_TailCall ) { 699 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 700 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 701 break; 702 } 703 } 704 705 // TailJumps have 2 returned values (target & ex_oop), whose masks come 706 // from the usual MachNode/MachOper mechanism. Find a sample 707 // TailJump to extract these masks and put the correct masks into 708 // the tail_jump_rms array. 709 for( i=1; i < root->req(); i++ ) { 710 MachReturnNode *m = root->in(i)->as_MachReturn(); 711 if( m->ideal_Opcode() == Op_TailJump ) { 712 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 713 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 714 break; 715 } 716 } 717 718 // Input RegMask array shared by all Halts 719 uint halt_edge_cnt = TypeFunc::Parms; 720 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 721 722 // Capture the return input masks into each exit flavor 723 for( i=1; i < root->req(); i++ ) { 724 MachReturnNode *exit = root->in(i)->as_MachReturn(); 725 switch( exit->ideal_Opcode() ) { 726 case Op_Return : exit->_in_rms = ret_rms; break; 727 case Op_Rethrow : exit->_in_rms = reth_rms; break; 728 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 729 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 730 case Op_Halt : exit->_in_rms = halt_rms; break; 731 default : ShouldNotReachHere(); 732 } 733 } 734 735 // Next unused projection number from Start. 736 int proj_cnt = C->tf()->domain()->cnt(); 737 738 // Do all the save-on-entry registers. Make projections from Start for 739 // them, and give them a use at the exit points. To the allocator, they 740 // look like incoming register arguments. 741 for( i = 0; i < _last_Mach_Reg; i++ ) { 742 if( is_save_on_entry(i) ) { 743 744 // Add the save-on-entry to the mask array 745 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 746 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 747 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 748 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 749 // Halts need the SOE registers, but only in the stack as debug info. 750 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 751 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 752 753 Node *mproj; 754 755 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 756 // into a single RegD. 757 if( (i&1) == 0 && 758 _register_save_type[i ] == Op_RegF && 759 _register_save_type[i+1] == Op_RegF && 760 is_save_on_entry(i+1) ) { 761 // Add other bit for double 762 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 763 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 764 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 765 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 766 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 767 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 768 proj_cnt += 2; // Skip 2 for doubles 769 } 770 else if( (i&1) == 1 && // Else check for high half of double 771 _register_save_type[i-1] == Op_RegF && 772 _register_save_type[i ] == Op_RegF && 773 is_save_on_entry(i-1) ) { 774 ret_rms [ ret_edge_cnt] = RegMask::Empty; 775 reth_rms [ reth_edge_cnt] = RegMask::Empty; 776 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 777 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 778 halt_rms [ halt_edge_cnt] = RegMask::Empty; 779 mproj = C->top(); 780 } 781 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 782 // into a single RegL. 783 else if( (i&1) == 0 && 784 _register_save_type[i ] == Op_RegI && 785 _register_save_type[i+1] == Op_RegI && 786 is_save_on_entry(i+1) ) { 787 // Add other bit for long 788 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 789 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 790 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 791 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 792 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 793 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 794 proj_cnt += 2; // Skip 2 for longs 795 } 796 else if( (i&1) == 1 && // Else check for high half of long 797 _register_save_type[i-1] == Op_RegI && 798 _register_save_type[i ] == Op_RegI && 799 is_save_on_entry(i-1) ) { 800 ret_rms [ ret_edge_cnt] = RegMask::Empty; 801 reth_rms [ reth_edge_cnt] = RegMask::Empty; 802 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 803 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 804 halt_rms [ halt_edge_cnt] = RegMask::Empty; 805 mproj = C->top(); 806 } else { 807 // Make a projection for it off the Start 808 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 809 } 810 811 ret_edge_cnt ++; 812 reth_edge_cnt ++; 813 tail_call_edge_cnt ++; 814 tail_jump_edge_cnt ++; 815 halt_edge_cnt ++; 816 817 // Add a use of the SOE register to all exit paths 818 for( uint j=1; j < root->req(); j++ ) 819 root->in(j)->add_req(mproj); 820 } // End of if a save-on-entry register 821 } // End of for all machine registers 822 } 823 824 //------------------------------init_spill_mask-------------------------------- 825 void Matcher::init_spill_mask( Node *ret ) { 826 if( idealreg2regmask[Op_RegI] ) return; // One time only init 827 828 OptoReg::c_frame_pointer = c_frame_pointer(); 829 c_frame_ptr_mask = c_frame_pointer(); 830 #ifdef _LP64 831 // pointers are twice as big 832 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 833 #endif 834 835 // Start at OptoReg::stack0() 836 STACK_ONLY_mask.Clear(); 837 OptoReg::Name init = OptoReg::stack2reg(0); 838 // STACK_ONLY_mask is all stack bits 839 OptoReg::Name i; 840 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 841 STACK_ONLY_mask.Insert(i); 842 // Also set the "infinite stack" bit. 843 STACK_ONLY_mask.set_AllStack(); 844 845 // Copy the register names over into the shared world 846 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 847 // SharedInfo::regName[i] = regName[i]; 848 // Handy RegMasks per machine register 849 mreg2regmask[i].Insert(i); 850 } 851 852 // Grab the Frame Pointer 853 Node *fp = ret->in(TypeFunc::FramePtr); 854 Node *mem = ret->in(TypeFunc::Memory); 855 const TypePtr* atp = TypePtr::BOTTOM; 856 // Share frame pointer while making spill ops 857 set_shared(fp); 858 859 // Compute generic short-offset Loads 860 #ifdef _LP64 861 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 862 #endif 863 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered)); 864 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false)); 865 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered)); 866 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered)); 867 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 868 assert(spillI != NULL && spillL != NULL && spillF != NULL && 869 spillD != NULL && spillP != NULL, ""); 870 // Get the ADLC notion of the right regmask, for each basic type. 871 #ifdef _LP64 872 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 873 #endif 874 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 875 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 876 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 877 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 878 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 879 880 // Vector regmasks. 881 if (Matcher::vector_size_supported(T_BYTE,4)) { 882 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 883 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 884 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 885 } 886 if (Matcher::vector_size_supported(T_FLOAT,2)) { 887 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 888 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 889 } 890 if (Matcher::vector_size_supported(T_FLOAT,4)) { 891 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 892 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 893 } 894 if (Matcher::vector_size_supported(T_FLOAT,8)) { 895 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 896 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 897 } 898 if (Matcher::vector_size_supported(T_FLOAT,16)) { 899 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ)); 900 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask(); 901 } 902 } 903 904 #ifdef ASSERT 905 static void match_alias_type(Compile* C, Node* n, Node* m) { 906 if (!VerifyAliases) return; // do not go looking for trouble by default 907 const TypePtr* nat = n->adr_type(); 908 const TypePtr* mat = m->adr_type(); 909 int nidx = C->get_alias_index(nat); 910 int midx = C->get_alias_index(mat); 911 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 912 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 913 for (uint i = 1; i < n->req(); i++) { 914 Node* n1 = n->in(i); 915 const TypePtr* n1at = n1->adr_type(); 916 if (n1at != NULL) { 917 nat = n1at; 918 nidx = C->get_alias_index(n1at); 919 } 920 } 921 } 922 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 923 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 924 switch (n->Opcode()) { 925 case Op_PrefetchAllocation: 926 nidx = Compile::AliasIdxRaw; 927 nat = TypeRawPtr::BOTTOM; 928 break; 929 } 930 } 931 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 932 switch (n->Opcode()) { 933 case Op_ClearArray: 934 midx = Compile::AliasIdxRaw; 935 mat = TypeRawPtr::BOTTOM; 936 break; 937 } 938 } 939 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 940 switch (n->Opcode()) { 941 case Op_Return: 942 case Op_Rethrow: 943 case Op_Halt: 944 case Op_TailCall: 945 case Op_TailJump: 946 nidx = Compile::AliasIdxBot; 947 nat = TypePtr::BOTTOM; 948 break; 949 } 950 } 951 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 952 switch (n->Opcode()) { 953 case Op_StrComp: 954 case Op_StrEquals: 955 case Op_StrIndexOf: 956 case Op_StrIndexOfChar: 957 case Op_AryEq: 958 case Op_HasNegatives: 959 case Op_MemBarVolatile: 960 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 961 case Op_StrInflatedCopy: 962 case Op_StrCompressedCopy: 963 case Op_OnSpinWait: 964 case Op_EncodeISOArray: 965 nidx = Compile::AliasIdxTop; 966 nat = NULL; 967 break; 968 } 969 } 970 if (nidx != midx) { 971 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 972 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 973 n->dump(); 974 m->dump(); 975 } 976 assert(C->subsume_loads() && C->must_alias(nat, midx), 977 "must not lose alias info when matching"); 978 } 979 } 980 #endif 981 982 //------------------------------xform------------------------------------------ 983 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine 984 // Node in new-space. Given a new-space Node, recursively walk his children. 985 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 986 Node *Matcher::xform( Node *n, int max_stack ) { 987 // Use one stack to keep both: child's node/state and parent's node/index 988 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 989 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 990 while (mstack.is_nonempty()) { 991 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 992 if (C->failing()) return NULL; 993 n = mstack.node(); // Leave node on stack 994 Node_State nstate = mstack.state(); 995 if (nstate == Visit) { 996 mstack.set_state(Post_Visit); 997 Node *oldn = n; 998 // Old-space or new-space check 999 if (!C->node_arena()->contains(n)) { 1000 // Old space! 1001 Node* m; 1002 if (has_new_node(n)) { // Not yet Label/Reduced 1003 m = new_node(n); 1004 } else { 1005 if (!is_dontcare(n)) { // Matcher can match this guy 1006 // Calls match special. They match alone with no children. 1007 // Their children, the incoming arguments, match normally. 1008 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1009 if (C->failing()) return NULL; 1010 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1011 if (n->is_MemBar()) { 1012 m->as_MachMemBar()->set_adr_type(n->adr_type()); 1013 } 1014 } else { // Nothing the matcher cares about 1015 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections? 1016 // Convert to machine-dependent projection 1017 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1018 #ifdef ASSERT 1019 _new2old_map.map(m->_idx, n); 1020 #endif 1021 if (m->in(0) != NULL) // m might be top 1022 collect_null_checks(m, n); 1023 } else { // Else just a regular 'ol guy 1024 m = n->clone(); // So just clone into new-space 1025 #ifdef ASSERT 1026 _new2old_map.map(m->_idx, n); 1027 #endif 1028 // Def-Use edges will be added incrementally as Uses 1029 // of this node are matched. 1030 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1031 } 1032 } 1033 1034 set_new_node(n, m); // Map old to new 1035 if (_old_node_note_array != NULL) { 1036 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1037 n->_idx); 1038 C->set_node_notes_at(m->_idx, nn); 1039 } 1040 debug_only(match_alias_type(C, n, m)); 1041 } 1042 n = m; // n is now a new-space node 1043 mstack.set_node(n); 1044 } 1045 1046 // New space! 1047 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1048 1049 int i; 1050 // Put precedence edges on stack first (match them last). 1051 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1052 Node *m = oldn->in(i); 1053 if (m == NULL) break; 1054 // set -1 to call add_prec() instead of set_req() during Step1 1055 mstack.push(m, Visit, n, -1); 1056 } 1057 1058 // Handle precedence edges for interior nodes 1059 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1060 Node *m = n->in(i); 1061 if (m == NULL || C->node_arena()->contains(m)) continue; 1062 n->rm_prec(i); 1063 // set -1 to call add_prec() instead of set_req() during Step1 1064 mstack.push(m, Visit, n, -1); 1065 } 1066 1067 // For constant debug info, I'd rather have unmatched constants. 1068 int cnt = n->req(); 1069 JVMState* jvms = n->jvms(); 1070 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1071 1072 // Now do only debug info. Clone constants rather than matching. 1073 // Constants are represented directly in the debug info without 1074 // the need for executable machine instructions. 1075 // Monitor boxes are also represented directly. 1076 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1077 Node *m = n->in(i); // Get input 1078 int op = m->Opcode(); 1079 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1080 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1081 op == Op_ConF || op == Op_ConD || op == Op_ConL 1082 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1083 ) { 1084 m = m->clone(); 1085 #ifdef ASSERT 1086 _new2old_map.map(m->_idx, n); 1087 #endif 1088 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1089 mstack.push(m->in(0), Visit, m, 0); 1090 } else { 1091 mstack.push(m, Visit, n, i); 1092 } 1093 } 1094 1095 // And now walk his children, and convert his inputs to new-space. 1096 for( ; i >= 0; --i ) { // For all normal inputs do 1097 Node *m = n->in(i); // Get input 1098 if(m != NULL) 1099 mstack.push(m, Visit, n, i); 1100 } 1101 1102 } 1103 else if (nstate == Post_Visit) { 1104 // Set xformed input 1105 Node *p = mstack.parent(); 1106 if (p != NULL) { // root doesn't have parent 1107 int i = (int)mstack.index(); 1108 if (i >= 0) 1109 p->set_req(i, n); // required input 1110 else if (i == -1) 1111 p->add_prec(n); // precedence input 1112 else 1113 ShouldNotReachHere(); 1114 } 1115 mstack.pop(); // remove processed node from stack 1116 } 1117 else { 1118 ShouldNotReachHere(); 1119 } 1120 } // while (mstack.is_nonempty()) 1121 return n; // Return new-space Node 1122 } 1123 1124 //------------------------------warp_outgoing_stk_arg------------------------ 1125 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1126 // Convert outgoing argument location to a pre-biased stack offset 1127 if (reg->is_stack()) { 1128 OptoReg::Name warped = reg->reg2stack(); 1129 // Adjust the stack slot offset to be the register number used 1130 // by the allocator. 1131 warped = OptoReg::add(begin_out_arg_area, warped); 1132 // Keep track of the largest numbered stack slot used for an arg. 1133 // Largest used slot per call-site indicates the amount of stack 1134 // that is killed by the call. 1135 if( warped >= out_arg_limit_per_call ) 1136 out_arg_limit_per_call = OptoReg::add(warped,1); 1137 if (!RegMask::can_represent_arg(warped)) { 1138 C->record_method_not_compilable("unsupported calling sequence"); 1139 return OptoReg::Bad; 1140 } 1141 return warped; 1142 } 1143 return OptoReg::as_OptoReg(reg); 1144 } 1145 1146 1147 //------------------------------match_sfpt------------------------------------- 1148 // Helper function to match call instructions. Calls match special. 1149 // They match alone with no children. Their children, the incoming 1150 // arguments, match normally. 1151 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1152 MachSafePointNode *msfpt = NULL; 1153 MachCallNode *mcall = NULL; 1154 uint cnt; 1155 // Split out case for SafePoint vs Call 1156 CallNode *call; 1157 const TypeTuple *domain; 1158 ciMethod* method = NULL; 1159 bool is_method_handle_invoke = false; // for special kill effects 1160 if( sfpt->is_Call() ) { 1161 call = sfpt->as_Call(); 1162 domain = call->tf()->domain(); 1163 cnt = domain->cnt(); 1164 1165 // Match just the call, nothing else 1166 MachNode *m = match_tree(call); 1167 if (C->failing()) return NULL; 1168 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1169 1170 // Copy data from the Ideal SafePoint to the machine version 1171 mcall = m->as_MachCall(); 1172 1173 mcall->set_tf( call->tf()); 1174 mcall->set_entry_point(call->entry_point()); 1175 mcall->set_cnt( call->cnt()); 1176 1177 if( mcall->is_MachCallJava() ) { 1178 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1179 const CallJavaNode *call_java = call->as_CallJava(); 1180 assert(call_java->validate_symbolic_info(), "inconsistent info"); 1181 method = call_java->method(); 1182 mcall_java->_method = method; 1183 mcall_java->_bci = call_java->_bci; 1184 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1185 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1186 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1187 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1188 if (is_method_handle_invoke) { 1189 C->set_has_method_handle_invokes(true); 1190 } 1191 if( mcall_java->is_MachCallStaticJava() ) 1192 mcall_java->as_MachCallStaticJava()->_name = 1193 call_java->as_CallStaticJava()->_name; 1194 if( mcall_java->is_MachCallDynamicJava() ) 1195 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1196 call_java->as_CallDynamicJava()->_vtable_index; 1197 } 1198 else if( mcall->is_MachCallRuntime() ) { 1199 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1200 } 1201 msfpt = mcall; 1202 } 1203 // This is a non-call safepoint 1204 else { 1205 call = NULL; 1206 domain = NULL; 1207 MachNode *mn = match_tree(sfpt); 1208 if (C->failing()) return NULL; 1209 msfpt = mn->as_MachSafePoint(); 1210 cnt = TypeFunc::Parms; 1211 } 1212 1213 // Advertise the correct memory effects (for anti-dependence computation). 1214 msfpt->set_adr_type(sfpt->adr_type()); 1215 1216 // Allocate a private array of RegMasks. These RegMasks are not shared. 1217 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1218 // Empty them all. 1219 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask(); 1220 1221 // Do all the pre-defined non-Empty register masks 1222 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1223 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1224 1225 // Place first outgoing argument can possibly be put. 1226 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1227 assert( is_even(begin_out_arg_area), "" ); 1228 // Compute max outgoing register number per call site. 1229 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1230 // Calls to C may hammer extra stack slots above and beyond any arguments. 1231 // These are usually backing store for register arguments for varargs. 1232 if( call != NULL && call->is_CallRuntime() ) 1233 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1234 1235 1236 // Do the normal argument list (parameters) register masks 1237 int argcnt = cnt - TypeFunc::Parms; 1238 if( argcnt > 0 ) { // Skip it all if we have no args 1239 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1240 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1241 int i; 1242 for( i = 0; i < argcnt; i++ ) { 1243 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1244 } 1245 // V-call to pick proper calling convention 1246 call->calling_convention( sig_bt, parm_regs, argcnt ); 1247 1248 #ifdef ASSERT 1249 // Sanity check users' calling convention. Really handy during 1250 // the initial porting effort. Fairly expensive otherwise. 1251 { for (int i = 0; i<argcnt; i++) { 1252 if( !parm_regs[i].first()->is_valid() && 1253 !parm_regs[i].second()->is_valid() ) continue; 1254 VMReg reg1 = parm_regs[i].first(); 1255 VMReg reg2 = parm_regs[i].second(); 1256 for (int j = 0; j < i; j++) { 1257 if( !parm_regs[j].first()->is_valid() && 1258 !parm_regs[j].second()->is_valid() ) continue; 1259 VMReg reg3 = parm_regs[j].first(); 1260 VMReg reg4 = parm_regs[j].second(); 1261 if( !reg1->is_valid() ) { 1262 assert( !reg2->is_valid(), "valid halvsies" ); 1263 } else if( !reg3->is_valid() ) { 1264 assert( !reg4->is_valid(), "valid halvsies" ); 1265 } else { 1266 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1267 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1268 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1269 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1270 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1271 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1272 } 1273 } 1274 } 1275 } 1276 #endif 1277 1278 // Visit each argument. Compute its outgoing register mask. 1279 // Return results now can have 2 bits returned. 1280 // Compute max over all outgoing arguments both per call-site 1281 // and over the entire method. 1282 for( i = 0; i < argcnt; i++ ) { 1283 // Address of incoming argument mask to fill in 1284 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1285 if( !parm_regs[i].first()->is_valid() && 1286 !parm_regs[i].second()->is_valid() ) { 1287 continue; // Avoid Halves 1288 } 1289 // Grab first register, adjust stack slots and insert in mask. 1290 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1291 if (OptoReg::is_valid(reg1)) 1292 rm->Insert( reg1 ); 1293 // Grab second register (if any), adjust stack slots and insert in mask. 1294 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1295 if (OptoReg::is_valid(reg2)) 1296 rm->Insert( reg2 ); 1297 } // End of for all arguments 1298 1299 // Compute number of stack slots needed to restore stack in case of 1300 // Pascal-style argument popping. 1301 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1302 } 1303 1304 // Compute the max stack slot killed by any call. These will not be 1305 // available for debug info, and will be used to adjust FIRST_STACK_mask 1306 // after all call sites have been visited. 1307 if( _out_arg_limit < out_arg_limit_per_call) 1308 _out_arg_limit = out_arg_limit_per_call; 1309 1310 if (mcall) { 1311 // Kill the outgoing argument area, including any non-argument holes and 1312 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1313 // Since the max-per-method covers the max-per-call-site and debug info 1314 // is excluded on the max-per-method basis, debug info cannot land in 1315 // this killed area. 1316 uint r_cnt = mcall->tf()->range()->cnt(); 1317 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1318 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1319 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1320 } else { 1321 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1322 proj->_rout.Insert(OptoReg::Name(i)); 1323 } 1324 if (proj->_rout.is_NotEmpty()) { 1325 push_projection(proj); 1326 } 1327 } 1328 // Transfer the safepoint information from the call to the mcall 1329 // Move the JVMState list 1330 msfpt->set_jvms(sfpt->jvms()); 1331 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1332 jvms->set_map(sfpt); 1333 } 1334 1335 // Debug inputs begin just after the last incoming parameter 1336 assert((mcall == NULL) || (mcall->jvms() == NULL) || 1337 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), ""); 1338 1339 // Move the OopMap 1340 msfpt->_oop_map = sfpt->_oop_map; 1341 1342 // Add additional edges. 1343 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1344 // For these calls we can not add MachConstantBase in expand(), as the 1345 // ins are not complete then. 1346 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1347 if (msfpt->jvms() && 1348 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1349 // We added an edge before jvms, so we must adapt the position of the ins. 1350 msfpt->jvms()->adapt_position(+1); 1351 } 1352 } 1353 1354 // Registers killed by the call are set in the local scheduling pass 1355 // of Global Code Motion. 1356 return msfpt; 1357 } 1358 1359 //---------------------------match_tree---------------------------------------- 1360 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1361 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1362 // making GotoNodes while building the CFG and in init_spill_mask() to identify 1363 // a Load's result RegMask for memoization in idealreg2regmask[] 1364 MachNode *Matcher::match_tree( const Node *n ) { 1365 assert( n->Opcode() != Op_Phi, "cannot match" ); 1366 assert( !n->is_block_start(), "cannot match" ); 1367 // Set the mark for all locally allocated State objects. 1368 // When this call returns, the _states_arena arena will be reset 1369 // freeing all State objects. 1370 ResourceMark rm( &_states_arena ); 1371 1372 LabelRootDepth = 0; 1373 1374 // StoreNodes require their Memory input to match any LoadNodes 1375 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1376 #ifdef ASSERT 1377 Node* save_mem_node = _mem_node; 1378 _mem_node = n->is_Store() ? (Node*)n : NULL; 1379 #endif 1380 // State object for root node of match tree 1381 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1382 State *s = new (&_states_arena) State; 1383 s->_kids[0] = NULL; 1384 s->_kids[1] = NULL; 1385 s->_leaf = (Node*)n; 1386 // Label the input tree, allocating labels from top-level arena 1387 Label_Root( n, s, n->in(0), mem ); 1388 if (C->failing()) return NULL; 1389 1390 // The minimum cost match for the whole tree is found at the root State 1391 uint mincost = max_juint; 1392 uint cost = max_juint; 1393 uint i; 1394 for( i = 0; i < NUM_OPERANDS; i++ ) { 1395 if( s->valid(i) && // valid entry and 1396 s->_cost[i] < cost && // low cost and 1397 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1398 cost = s->_cost[mincost=i]; 1399 } 1400 if (mincost == max_juint) { 1401 #ifndef PRODUCT 1402 tty->print("No matching rule for:"); 1403 s->dump(); 1404 #endif 1405 Matcher::soft_match_failure(); 1406 return NULL; 1407 } 1408 // Reduce input tree based upon the state labels to machine Nodes 1409 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1410 #ifdef ASSERT 1411 _old2new_map.map(n->_idx, m); 1412 _new2old_map.map(m->_idx, (Node*)n); 1413 #endif 1414 1415 // Add any Matcher-ignored edges 1416 uint cnt = n->req(); 1417 uint start = 1; 1418 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1419 if( n->is_AddP() ) { 1420 assert( mem == (Node*)1, "" ); 1421 start = AddPNode::Base+1; 1422 } 1423 for( i = start; i < cnt; i++ ) { 1424 if( !n->match_edge(i) ) { 1425 if( i < m->req() ) 1426 m->ins_req( i, n->in(i) ); 1427 else 1428 m->add_req( n->in(i) ); 1429 } 1430 } 1431 1432 debug_only( _mem_node = save_mem_node; ) 1433 return m; 1434 } 1435 1436 1437 //------------------------------match_into_reg--------------------------------- 1438 // Choose to either match this Node in a register or part of the current 1439 // match tree. Return true for requiring a register and false for matching 1440 // as part of the current match tree. 1441 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1442 1443 const Type *t = m->bottom_type(); 1444 1445 if (t->singleton()) { 1446 // Never force constants into registers. Allow them to match as 1447 // constants or registers. Copies of the same value will share 1448 // the same register. See find_shared_node. 1449 return false; 1450 } else { // Not a constant 1451 // Stop recursion if they have different Controls. 1452 Node* m_control = m->in(0); 1453 // Control of load's memory can post-dominates load's control. 1454 // So use it since load can't float above its memory. 1455 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1456 if (control && m_control && control != m_control && control != mem_control) { 1457 1458 // Actually, we can live with the most conservative control we 1459 // find, if it post-dominates the others. This allows us to 1460 // pick up load/op/store trees where the load can float a little 1461 // above the store. 1462 Node *x = control; 1463 const uint max_scan = 6; // Arbitrary scan cutoff 1464 uint j; 1465 for (j=0; j<max_scan; j++) { 1466 if (x->is_Region()) // Bail out at merge points 1467 return true; 1468 x = x->in(0); 1469 if (x == m_control) // Does 'control' post-dominate 1470 break; // m->in(0)? If so, we can use it 1471 if (x == mem_control) // Does 'control' post-dominate 1472 break; // mem_control? If so, we can use it 1473 } 1474 if (j == max_scan) // No post-domination before scan end? 1475 return true; // Then break the match tree up 1476 } 1477 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1478 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1479 // These are commonly used in address expressions and can 1480 // efficiently fold into them on X64 in some cases. 1481 return false; 1482 } 1483 } 1484 1485 // Not forceable cloning. If shared, put it into a register. 1486 return shared; 1487 } 1488 1489 1490 //------------------------------Instruction Selection-------------------------- 1491 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1492 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1493 // things the Matcher does not match (e.g., Memory), and things with different 1494 // Controls (hence forced into different blocks). We pass in the Control 1495 // selected for this entire State tree. 1496 1497 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1498 // Store and the Load must have identical Memories (as well as identical 1499 // pointers). Since the Matcher does not have anything for Memory (and 1500 // does not handle DAGs), I have to match the Memory input myself. If the 1501 // Tree root is a Store, I require all Loads to have the identical memory. 1502 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1503 // Since Label_Root is a recursive function, its possible that we might run 1504 // out of stack space. See bugs 6272980 & 6227033 for more info. 1505 LabelRootDepth++; 1506 if (LabelRootDepth > MaxLabelRootDepth) { 1507 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1508 return NULL; 1509 } 1510 uint care = 0; // Edges matcher cares about 1511 uint cnt = n->req(); 1512 uint i = 0; 1513 1514 // Examine children for memory state 1515 // Can only subsume a child into your match-tree if that child's memory state 1516 // is not modified along the path to another input. 1517 // It is unsafe even if the other inputs are separate roots. 1518 Node *input_mem = NULL; 1519 for( i = 1; i < cnt; i++ ) { 1520 if( !n->match_edge(i) ) continue; 1521 Node *m = n->in(i); // Get ith input 1522 assert( m, "expect non-null children" ); 1523 if( m->is_Load() ) { 1524 if( input_mem == NULL ) { 1525 input_mem = m->in(MemNode::Memory); 1526 } else if( input_mem != m->in(MemNode::Memory) ) { 1527 input_mem = NodeSentinel; 1528 } 1529 } 1530 } 1531 1532 for( i = 1; i < cnt; i++ ){// For my children 1533 if( !n->match_edge(i) ) continue; 1534 Node *m = n->in(i); // Get ith input 1535 // Allocate states out of a private arena 1536 State *s = new (&_states_arena) State; 1537 svec->_kids[care++] = s; 1538 assert( care <= 2, "binary only for now" ); 1539 1540 // Recursively label the State tree. 1541 s->_kids[0] = NULL; 1542 s->_kids[1] = NULL; 1543 s->_leaf = m; 1544 1545 // Check for leaves of the State Tree; things that cannot be a part of 1546 // the current tree. If it finds any, that value is matched as a 1547 // register operand. If not, then the normal matching is used. 1548 if( match_into_reg(n, m, control, i, is_shared(m)) || 1549 // 1550 // Stop recursion if this is LoadNode and the root of this tree is a 1551 // StoreNode and the load & store have different memories. 1552 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1553 // Can NOT include the match of a subtree when its memory state 1554 // is used by any of the other subtrees 1555 (input_mem == NodeSentinel) ) { 1556 // Print when we exclude matching due to different memory states at input-loads 1557 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1558 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1559 tty->print_cr("invalid input_mem"); 1560 } 1561 // Switch to a register-only opcode; this value must be in a register 1562 // and cannot be subsumed as part of a larger instruction. 1563 s->DFA( m->ideal_reg(), m ); 1564 1565 } else { 1566 // If match tree has no control and we do, adopt it for entire tree 1567 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1568 control = m->in(0); // Pick up control 1569 // Else match as a normal part of the match tree. 1570 control = Label_Root(m,s,control,mem); 1571 if (C->failing()) return NULL; 1572 } 1573 } 1574 1575 1576 // Call DFA to match this node, and return 1577 svec->DFA( n->Opcode(), n ); 1578 1579 #ifdef ASSERT 1580 uint x; 1581 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1582 if( svec->valid(x) ) 1583 break; 1584 1585 if (x >= _LAST_MACH_OPER) { 1586 n->dump(); 1587 svec->dump(); 1588 assert( false, "bad AD file" ); 1589 } 1590 #endif 1591 return control; 1592 } 1593 1594 1595 // Con nodes reduced using the same rule can share their MachNode 1596 // which reduces the number of copies of a constant in the final 1597 // program. The register allocator is free to split uses later to 1598 // split live ranges. 1599 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1600 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1601 1602 // See if this Con has already been reduced using this rule. 1603 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1604 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1605 if (last != NULL && rule == last->rule()) { 1606 // Don't expect control change for DecodeN 1607 if (leaf->is_DecodeNarrowPtr()) 1608 return last; 1609 // Get the new space root. 1610 Node* xroot = new_node(C->root()); 1611 if (xroot == NULL) { 1612 // This shouldn't happen give the order of matching. 1613 return NULL; 1614 } 1615 1616 // Shared constants need to have their control be root so they 1617 // can be scheduled properly. 1618 Node* control = last->in(0); 1619 if (control != xroot) { 1620 if (control == NULL || control == C->root()) { 1621 last->set_req(0, xroot); 1622 } else { 1623 assert(false, "unexpected control"); 1624 return NULL; 1625 } 1626 } 1627 return last; 1628 } 1629 return NULL; 1630 } 1631 1632 1633 //------------------------------ReduceInst------------------------------------- 1634 // Reduce a State tree (with given Control) into a tree of MachNodes. 1635 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1636 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1637 // Each MachNode has a number of complicated MachOper operands; each 1638 // MachOper also covers a further tree of Ideal Nodes. 1639 1640 // The root of the Ideal match tree is always an instruction, so we enter 1641 // the recursion here. After building the MachNode, we need to recurse 1642 // the tree checking for these cases: 1643 // (1) Child is an instruction - 1644 // Build the instruction (recursively), add it as an edge. 1645 // Build a simple operand (register) to hold the result of the instruction. 1646 // (2) Child is an interior part of an instruction - 1647 // Skip over it (do nothing) 1648 // (3) Child is the start of a operand - 1649 // Build the operand, place it inside the instruction 1650 // Call ReduceOper. 1651 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1652 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1653 1654 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1655 if (shared_node != NULL) { 1656 return shared_node; 1657 } 1658 1659 // Build the object to represent this state & prepare for recursive calls 1660 MachNode *mach = s->MachNodeGenerator(rule); 1661 guarantee(mach != NULL, "Missing MachNode"); 1662 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1663 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1664 Node *leaf = s->_leaf; 1665 // Check for instruction or instruction chain rule 1666 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1667 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1668 "duplicating node that's already been matched"); 1669 // Instruction 1670 mach->add_req( leaf->in(0) ); // Set initial control 1671 // Reduce interior of complex instruction 1672 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1673 } else { 1674 // Instruction chain rules are data-dependent on their inputs 1675 mach->add_req(0); // Set initial control to none 1676 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1677 } 1678 1679 // If a Memory was used, insert a Memory edge 1680 if( mem != (Node*)1 ) { 1681 mach->ins_req(MemNode::Memory,mem); 1682 #ifdef ASSERT 1683 // Verify adr type after matching memory operation 1684 const MachOper* oper = mach->memory_operand(); 1685 if (oper != NULL && oper != (MachOper*)-1) { 1686 // It has a unique memory operand. Find corresponding ideal mem node. 1687 Node* m = NULL; 1688 if (leaf->is_Mem()) { 1689 m = leaf; 1690 } else { 1691 m = _mem_node; 1692 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1693 } 1694 const Type* mach_at = mach->adr_type(); 1695 // DecodeN node consumed by an address may have different type 1696 // than its input. Don't compare types for such case. 1697 if (m->adr_type() != mach_at && 1698 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1699 (m->in(MemNode::Address)->is_AddP() && 1700 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) || 1701 (m->in(MemNode::Address)->is_AddP() && 1702 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1703 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) { 1704 mach_at = m->adr_type(); 1705 } 1706 if (m->adr_type() != mach_at) { 1707 m->dump(); 1708 tty->print_cr("mach:"); 1709 mach->dump(1); 1710 } 1711 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1712 } 1713 #endif 1714 } 1715 1716 // If the _leaf is an AddP, insert the base edge 1717 if (leaf->is_AddP()) { 1718 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1719 } 1720 1721 uint number_of_projections_prior = number_of_projections(); 1722 1723 // Perform any 1-to-many expansions required 1724 MachNode *ex = mach->Expand(s, _projection_list, mem); 1725 if (ex != mach) { 1726 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1727 if( ex->in(1)->is_Con() ) 1728 ex->in(1)->set_req(0, C->root()); 1729 // Remove old node from the graph 1730 for( uint i=0; i<mach->req(); i++ ) { 1731 mach->set_req(i,NULL); 1732 } 1733 #ifdef ASSERT 1734 _new2old_map.map(ex->_idx, s->_leaf); 1735 #endif 1736 } 1737 1738 // PhaseChaitin::fixup_spills will sometimes generate spill code 1739 // via the matcher. By the time, nodes have been wired into the CFG, 1740 // and any further nodes generated by expand rules will be left hanging 1741 // in space, and will not get emitted as output code. Catch this. 1742 // Also, catch any new register allocation constraints ("projections") 1743 // generated belatedly during spill code generation. 1744 if (_allocation_started) { 1745 guarantee(ex == mach, "no expand rules during spill generation"); 1746 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1747 } 1748 1749 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1750 // Record the con for sharing 1751 _shared_nodes.map(leaf->_idx, ex); 1752 } 1753 1754 // Have mach nodes inherit GC barrier data 1755 if (leaf->is_LoadStore()) { 1756 mach->set_barrier_data(leaf->as_LoadStore()->barrier_data()); 1757 } else if (leaf->is_Mem()) { 1758 mach->set_barrier_data(leaf->as_Mem()->barrier_data()); 1759 } 1760 1761 return ex; 1762 } 1763 1764 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1765 for (uint i = n->req(); i < n->len(); i++) { 1766 if (n->in(i) != NULL) { 1767 mach->add_prec(n->in(i)); 1768 } 1769 } 1770 } 1771 1772 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1773 // 'op' is what I am expecting to receive 1774 int op = _leftOp[rule]; 1775 // Operand type to catch childs result 1776 // This is what my child will give me. 1777 int opnd_class_instance = s->_rule[op]; 1778 // Choose between operand class or not. 1779 // This is what I will receive. 1780 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1781 // New rule for child. Chase operand classes to get the actual rule. 1782 int newrule = s->_rule[catch_op]; 1783 1784 if( newrule < NUM_OPERANDS ) { 1785 // Chain from operand or operand class, may be output of shared node 1786 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1787 "Bad AD file: Instruction chain rule must chain from operand"); 1788 // Insert operand into array of operands for this instruction 1789 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1790 1791 ReduceOper( s, newrule, mem, mach ); 1792 } else { 1793 // Chain from the result of an instruction 1794 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1795 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1796 Node *mem1 = (Node*)1; 1797 debug_only(Node *save_mem_node = _mem_node;) 1798 mach->add_req( ReduceInst(s, newrule, mem1) ); 1799 debug_only(_mem_node = save_mem_node;) 1800 } 1801 return; 1802 } 1803 1804 1805 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1806 handle_precedence_edges(s->_leaf, mach); 1807 1808 if( s->_leaf->is_Load() ) { 1809 Node *mem2 = s->_leaf->in(MemNode::Memory); 1810 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1811 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1812 mem = mem2; 1813 } 1814 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1815 if( mach->in(0) == NULL ) 1816 mach->set_req(0, s->_leaf->in(0)); 1817 } 1818 1819 // Now recursively walk the state tree & add operand list. 1820 for( uint i=0; i<2; i++ ) { // binary tree 1821 State *newstate = s->_kids[i]; 1822 if( newstate == NULL ) break; // Might only have 1 child 1823 // 'op' is what I am expecting to receive 1824 int op; 1825 if( i == 0 ) { 1826 op = _leftOp[rule]; 1827 } else { 1828 op = _rightOp[rule]; 1829 } 1830 // Operand type to catch childs result 1831 // This is what my child will give me. 1832 int opnd_class_instance = newstate->_rule[op]; 1833 // Choose between operand class or not. 1834 // This is what I will receive. 1835 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1836 // New rule for child. Chase operand classes to get the actual rule. 1837 int newrule = newstate->_rule[catch_op]; 1838 1839 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1840 // Operand/operandClass 1841 // Insert operand into array of operands for this instruction 1842 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 1843 ReduceOper( newstate, newrule, mem, mach ); 1844 1845 } else { // Child is internal operand or new instruction 1846 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1847 // internal operand --> call ReduceInst_Interior 1848 // Interior of complex instruction. Do nothing but recurse. 1849 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1850 } else { 1851 // instruction --> call build operand( ) to catch result 1852 // --> ReduceInst( newrule ) 1853 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 1854 Node *mem1 = (Node*)1; 1855 debug_only(Node *save_mem_node = _mem_node;) 1856 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1857 debug_only(_mem_node = save_mem_node;) 1858 } 1859 } 1860 assert( mach->_opnds[num_opnds-1], "" ); 1861 } 1862 return num_opnds; 1863 } 1864 1865 // This routine walks the interior of possible complex operands. 1866 // At each point we check our children in the match tree: 1867 // (1) No children - 1868 // We are a leaf; add _leaf field as an input to the MachNode 1869 // (2) Child is an internal operand - 1870 // Skip over it ( do nothing ) 1871 // (3) Child is an instruction - 1872 // Call ReduceInst recursively and 1873 // and instruction as an input to the MachNode 1874 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1875 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1876 State *kid = s->_kids[0]; 1877 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1878 1879 // Leaf? And not subsumed? 1880 if( kid == NULL && !_swallowed[rule] ) { 1881 mach->add_req( s->_leaf ); // Add leaf pointer 1882 return; // Bail out 1883 } 1884 1885 if( s->_leaf->is_Load() ) { 1886 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1887 mem = s->_leaf->in(MemNode::Memory); 1888 debug_only(_mem_node = s->_leaf;) 1889 } 1890 1891 handle_precedence_edges(s->_leaf, mach); 1892 1893 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1894 if( !mach->in(0) ) 1895 mach->set_req(0,s->_leaf->in(0)); 1896 else { 1897 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1898 } 1899 } 1900 1901 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1902 int newrule; 1903 if( i == 0) 1904 newrule = kid->_rule[_leftOp[rule]]; 1905 else 1906 newrule = kid->_rule[_rightOp[rule]]; 1907 1908 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1909 // Internal operand; recurse but do nothing else 1910 ReduceOper( kid, newrule, mem, mach ); 1911 1912 } else { // Child is a new instruction 1913 // Reduce the instruction, and add a direct pointer from this 1914 // machine instruction to the newly reduced one. 1915 Node *mem1 = (Node*)1; 1916 debug_only(Node *save_mem_node = _mem_node;) 1917 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1918 debug_only(_mem_node = save_mem_node;) 1919 } 1920 } 1921 } 1922 1923 1924 // ------------------------------------------------------------------------- 1925 // Java-Java calling convention 1926 // (what you use when Java calls Java) 1927 1928 //------------------------------find_receiver---------------------------------- 1929 // For a given signature, return the OptoReg for parameter 0. 1930 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1931 VMRegPair regs; 1932 BasicType sig_bt = T_OBJECT; 1933 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1934 // Return argument 0 register. In the LP64 build pointers 1935 // take 2 registers, but the VM wants only the 'main' name. 1936 return OptoReg::as_OptoReg(regs.first()); 1937 } 1938 1939 // This function identifies sub-graphs in which a 'load' node is 1940 // input to two different nodes, and such that it can be matched 1941 // with BMI instructions like blsi, blsr, etc. 1942 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32. 1943 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL* 1944 // refers to the same node. 1945 #ifdef X86 1946 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop) 1947 // This is a temporary solution until we make DAGs expressible in ADL. 1948 template<typename ConType> 1949 class FusedPatternMatcher { 1950 Node* _op1_node; 1951 Node* _mop_node; 1952 int _con_op; 1953 1954 static int match_next(Node* n, int next_op, int next_op_idx) { 1955 if (n->in(1) == NULL || n->in(2) == NULL) { 1956 return -1; 1957 } 1958 1959 if (next_op_idx == -1) { // n is commutative, try rotations 1960 if (n->in(1)->Opcode() == next_op) { 1961 return 1; 1962 } else if (n->in(2)->Opcode() == next_op) { 1963 return 2; 1964 } 1965 } else { 1966 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index"); 1967 if (n->in(next_op_idx)->Opcode() == next_op) { 1968 return next_op_idx; 1969 } 1970 } 1971 return -1; 1972 } 1973 public: 1974 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) : 1975 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { } 1976 1977 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative 1978 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative 1979 typename ConType::NativeType con_value) { 1980 if (_op1_node->Opcode() != op1) { 1981 return false; 1982 } 1983 if (_mop_node->outcnt() > 2) { 1984 return false; 1985 } 1986 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx); 1987 if (op1_op2_idx == -1) { 1988 return false; 1989 } 1990 // Memory operation must be the other edge 1991 int op1_mop_idx = (op1_op2_idx & 1) + 1; 1992 1993 // Check that the mop node is really what we want 1994 if (_op1_node->in(op1_mop_idx) == _mop_node) { 1995 Node *op2_node = _op1_node->in(op1_op2_idx); 1996 if (op2_node->outcnt() > 1) { 1997 return false; 1998 } 1999 assert(op2_node->Opcode() == op2, "Should be"); 2000 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx); 2001 if (op2_con_idx == -1) { 2002 return false; 2003 } 2004 // Memory operation must be the other edge 2005 int op2_mop_idx = (op2_con_idx & 1) + 1; 2006 // Check that the memory operation is the same node 2007 if (op2_node->in(op2_mop_idx) == _mop_node) { 2008 // Now check the constant 2009 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type(); 2010 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) { 2011 return true; 2012 } 2013 } 2014 } 2015 return false; 2016 } 2017 }; 2018 2019 2020 bool Matcher::is_bmi_pattern(Node *n, Node *m) { 2021 if (n != NULL && m != NULL) { 2022 if (m->Opcode() == Op_LoadI) { 2023 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI); 2024 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) || 2025 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) || 2026 bmii.match(Op_XorI, -1, Op_AddI, -1, -1); 2027 } else if (m->Opcode() == Op_LoadL) { 2028 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL); 2029 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) || 2030 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) || 2031 bmil.match(Op_XorL, -1, Op_AddL, -1, -1); 2032 } 2033 } 2034 return false; 2035 } 2036 #endif // X86 2037 2038 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2039 Node *off = m->in(AddPNode::Offset); 2040 if (off->is_Con()) { 2041 address_visited.test_set(m->_idx); // Flag as address_visited 2042 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2043 // Clone X+offset as it also folds into most addressing expressions 2044 mstack.push(off, Visit); 2045 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2046 return true; 2047 } 2048 return false; 2049 } 2050 2051 // A method-klass-holder may be passed in the inline_cache_reg 2052 // and then expanded into the inline_cache_reg and a method_oop register 2053 // defined in ad_<arch>.cpp 2054 2055 //------------------------------find_shared------------------------------------ 2056 // Set bits if Node is shared or otherwise a root 2057 void Matcher::find_shared( Node *n ) { 2058 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2059 MStack mstack(C->live_nodes() * 2); 2060 // Mark nodes as address_visited if they are inputs to an address expression 2061 VectorSet address_visited(Thread::current()->resource_area()); 2062 mstack.push(n, Visit); // Don't need to pre-visit root node 2063 while (mstack.is_nonempty()) { 2064 n = mstack.node(); // Leave node on stack 2065 Node_State nstate = mstack.state(); 2066 uint nop = n->Opcode(); 2067 if (nstate == Pre_Visit) { 2068 if (address_visited.test(n->_idx)) { // Visited in address already? 2069 // Flag as visited and shared now. 2070 set_visited(n); 2071 } 2072 if (is_visited(n)) { // Visited already? 2073 // Node is shared and has no reason to clone. Flag it as shared. 2074 // This causes it to match into a register for the sharing. 2075 set_shared(n); // Flag as shared and 2076 if (n->is_DecodeNarrowPtr()) { 2077 // Oop field/array element loads must be shared but since 2078 // they are shared through a DecodeN they may appear to have 2079 // a single use so force sharing here. 2080 set_shared(n->in(1)); 2081 } 2082 mstack.pop(); // remove node from stack 2083 continue; 2084 } 2085 nstate = Visit; // Not already visited; so visit now 2086 } 2087 if (nstate == Visit) { 2088 mstack.set_state(Post_Visit); 2089 set_visited(n); // Flag as visited now 2090 bool mem_op = false; 2091 int mem_addr_idx = MemNode::Address; 2092 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_visit(this, mstack, n, nop, mem_op, mem_addr_idx); 2093 if (!gc_handled) { 2094 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) { 2095 continue; 2096 } 2097 } 2098 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2099 Node *m = n->in(i); // Get ith input 2100 if (m == NULL) continue; // Ignore NULLs 2101 uint mop = m->Opcode(); 2102 2103 // Must clone all producers of flags, or we will not match correctly. 2104 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2105 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2106 // are also there, so we may match a float-branch to int-flags and 2107 // expect the allocator to haul the flags from the int-side to the 2108 // fp-side. No can do. 2109 if( _must_clone[mop] ) { 2110 mstack.push(m, Visit); 2111 continue; // for(int i = ...) 2112 } 2113 2114 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node. 2115 #ifdef X86 2116 if (UseBMI1Instructions && is_bmi_pattern(n, m)) { 2117 mstack.push(m, Visit); 2118 continue; 2119 } 2120 #endif 2121 2122 // Clone addressing expressions as they are "free" in memory access instructions 2123 if (mem_op && i == mem_addr_idx && mop == Op_AddP && 2124 // When there are other uses besides address expressions 2125 // put it on stack and mark as shared. 2126 !is_visited(m)) { 2127 // Some inputs for address expression are not put on stack 2128 // to avoid marking them as shared and forcing them into register 2129 // if they are used only in address expressions. 2130 // But they should be marked as shared if there are other uses 2131 // besides address expressions. 2132 2133 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2134 continue; 2135 } 2136 } // if( mem_op && 2137 mstack.push(m, Pre_Visit); 2138 } // for(int i = ...) 2139 } 2140 else if (nstate == Alt_Post_Visit) { 2141 mstack.pop(); // Remove node from stack 2142 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2143 // shared and all users of the Bool need to move the Cmp in parallel. 2144 // This leaves both the Bool and the If pointing at the Cmp. To 2145 // prevent the Matcher from trying to Match the Cmp along both paths 2146 // BoolNode::match_edge always returns a zero. 2147 2148 // We reorder the Op_If in a pre-order manner, so we can visit without 2149 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2150 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2151 } 2152 else if (nstate == Post_Visit) { 2153 mstack.pop(); // Remove node from stack 2154 2155 // Now hack a few special opcodes 2156 uint opcode = n->Opcode(); 2157 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode); 2158 if (!gc_handled) { 2159 find_shared_post_visit(n, opcode); 2160 } 2161 } 2162 else { 2163 ShouldNotReachHere(); 2164 } 2165 } // end of while (mstack.is_nonempty()) 2166 } 2167 2168 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) { 2169 switch(opcode) { // Handle some opcodes special 2170 case Op_Phi: // Treat Phis as shared roots 2171 case Op_Parm: 2172 case Op_Proj: // All handled specially during matching 2173 case Op_SafePointScalarObject: 2174 set_shared(n); 2175 set_dontcare(n); 2176 break; 2177 case Op_If: 2178 case Op_CountedLoopEnd: 2179 mstack.set_state(Alt_Post_Visit); // Alternative way 2180 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2181 // with matching cmp/branch in 1 instruction. The Matcher needs the 2182 // Bool and CmpX side-by-side, because it can only get at constants 2183 // that are at the leaves of Match trees, and the Bool's condition acts 2184 // as a constant here. 2185 mstack.push(n->in(1), Visit); // Clone the Bool 2186 mstack.push(n->in(0), Pre_Visit); // Visit control input 2187 return true; // while (mstack.is_nonempty()) 2188 case Op_ConvI2D: // These forms efficiently match with a prior 2189 case Op_ConvI2F: // Load but not a following Store 2190 if( n->in(1)->is_Load() && // Prior load 2191 n->outcnt() == 1 && // Not already shared 2192 n->unique_out()->is_Store() ) // Following store 2193 set_shared(n); // Force it to be a root 2194 break; 2195 case Op_ReverseBytesI: 2196 case Op_ReverseBytesL: 2197 if( n->in(1)->is_Load() && // Prior load 2198 n->outcnt() == 1 ) // Not already shared 2199 set_shared(n); // Force it to be a root 2200 break; 2201 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 2202 case Op_IfFalse: 2203 case Op_IfTrue: 2204 case Op_MachProj: 2205 case Op_MergeMem: 2206 case Op_Catch: 2207 case Op_CatchProj: 2208 case Op_CProj: 2209 case Op_JumpProj: 2210 case Op_JProj: 2211 case Op_NeverBranch: 2212 set_dontcare(n); 2213 break; 2214 case Op_Jump: 2215 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2216 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2217 return true; // while (mstack.is_nonempty()) 2218 case Op_StrComp: 2219 case Op_StrEquals: 2220 case Op_StrIndexOf: 2221 case Op_StrIndexOfChar: 2222 case Op_AryEq: 2223 case Op_HasNegatives: 2224 case Op_StrInflatedCopy: 2225 case Op_StrCompressedCopy: 2226 case Op_EncodeISOArray: 2227 case Op_FmaD: 2228 case Op_FmaF: 2229 case Op_FmaVD: 2230 case Op_FmaVF: 2231 set_shared(n); // Force result into register (it will be anyways) 2232 break; 2233 case Op_ConP: { // Convert pointers above the centerline to NUL 2234 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2235 const TypePtr* tp = tn->type()->is_ptr(); 2236 if (tp->_ptr == TypePtr::AnyNull) { 2237 tn->set_type(TypePtr::NULL_PTR); 2238 } 2239 break; 2240 } 2241 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2242 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2243 const TypePtr* tp = tn->type()->make_ptr(); 2244 if (tp && tp->_ptr == TypePtr::AnyNull) { 2245 tn->set_type(TypeNarrowOop::NULL_PTR); 2246 } 2247 break; 2248 } 2249 case Op_Binary: // These are introduced in the Post_Visit state. 2250 ShouldNotReachHere(); 2251 break; 2252 case Op_ClearArray: 2253 case Op_SafePoint: 2254 mem_op = true; 2255 break; 2256 default: 2257 if( n->is_Store() ) { 2258 // Do match stores, despite no ideal reg 2259 mem_op = true; 2260 break; 2261 } 2262 if( n->is_Mem() ) { // Loads and LoadStores 2263 mem_op = true; 2264 // Loads must be root of match tree due to prior load conflict 2265 if( C->subsume_loads() == false ) 2266 set_shared(n); 2267 } 2268 // Fall into default case 2269 if( !n->ideal_reg() ) 2270 set_dontcare(n); // Unmatchable Nodes 2271 } // end_switch 2272 return false; 2273 } 2274 2275 void Matcher::find_shared_post_visit(Node* n, uint opcode) { 2276 switch(opcode) { // Handle some opcodes special 2277 case Op_StorePConditional: 2278 case Op_StoreIConditional: 2279 case Op_StoreLConditional: 2280 case Op_CompareAndExchangeB: 2281 case Op_CompareAndExchangeS: 2282 case Op_CompareAndExchangeI: 2283 case Op_CompareAndExchangeL: 2284 case Op_CompareAndExchangeP: 2285 case Op_CompareAndExchangeN: 2286 case Op_WeakCompareAndSwapB: 2287 case Op_WeakCompareAndSwapS: 2288 case Op_WeakCompareAndSwapI: 2289 case Op_WeakCompareAndSwapL: 2290 case Op_WeakCompareAndSwapP: 2291 case Op_WeakCompareAndSwapN: 2292 case Op_CompareAndSwapB: 2293 case Op_CompareAndSwapS: 2294 case Op_CompareAndSwapI: 2295 case Op_CompareAndSwapL: 2296 case Op_CompareAndSwapP: 2297 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2298 Node* newval = n->in(MemNode::ValueIn); 2299 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2300 Node* pair = new BinaryNode(oldval, newval); 2301 n->set_req(MemNode::ValueIn, pair); 2302 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2303 break; 2304 } 2305 case Op_CMoveD: // Convert trinary to binary-tree 2306 case Op_CMoveF: 2307 case Op_CMoveI: 2308 case Op_CMoveL: 2309 case Op_CMoveN: 2310 case Op_CMoveP: 2311 case Op_CMoveVF: 2312 case Op_CMoveVD: { 2313 // Restructure into a binary tree for Matching. It's possible that 2314 // we could move this code up next to the graph reshaping for IfNodes 2315 // or vice-versa, but I do not want to debug this for Ladybird. 2316 // 10/2/2000 CNC. 2317 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1)); 2318 n->set_req(1, pair1); 2319 Node* pair2 = new BinaryNode(n->in(2), n->in(3)); 2320 n->set_req(2, pair2); 2321 n->del_req(3); 2322 break; 2323 } 2324 case Op_LoopLimit: { 2325 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2326 n->set_req(1, pair1); 2327 n->set_req(2, n->in(3)); 2328 n->del_req(3); 2329 break; 2330 } 2331 case Op_StrEquals: 2332 case Op_StrIndexOfChar: { 2333 Node* pair1 = new BinaryNode(n->in(2), n->in(3)); 2334 n->set_req(2, pair1); 2335 n->set_req(3, n->in(4)); 2336 n->del_req(4); 2337 break; 2338 } 2339 case Op_StrComp: 2340 case Op_StrIndexOf: { 2341 Node* pair1 = new BinaryNode(n->in(2), n->in(3)); 2342 n->set_req(2, pair1); 2343 Node* pair2 = new BinaryNode(n->in(4),n->in(5)); 2344 n->set_req(3, pair2); 2345 n->del_req(5); 2346 n->del_req(4); 2347 break; 2348 } 2349 case Op_StrCompressedCopy: 2350 case Op_StrInflatedCopy: 2351 case Op_EncodeISOArray: { 2352 // Restructure into a binary tree for Matching. 2353 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2354 n->set_req(3, pair); 2355 n->del_req(4); 2356 break; 2357 } 2358 case Op_FmaD: 2359 case Op_FmaF: 2360 case Op_FmaVD: 2361 case Op_FmaVF: { 2362 // Restructure into a binary tree for Matching. 2363 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2364 n->set_req(2, pair); 2365 n->set_req(1, n->in(3)); 2366 n->del_req(3); 2367 break; 2368 } 2369 case Op_MulAddS2I: { 2370 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2371 Node* pair2 = new BinaryNode(n->in(3), n->in(4)); 2372 n->set_req(1, pair1); 2373 n->set_req(2, pair2); 2374 n->del_req(4); 2375 n->del_req(3); 2376 break; 2377 } 2378 default: 2379 break; 2380 } 2381 } 2382 2383 #ifdef ASSERT 2384 // machine-independent root to machine-dependent root 2385 void Matcher::dump_old2new_map() { 2386 _old2new_map.dump(); 2387 } 2388 #endif 2389 2390 //---------------------------collect_null_checks------------------------------- 2391 // Find null checks in the ideal graph; write a machine-specific node for 2392 // it. Used by later implicit-null-check handling. Actually collects 2393 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2394 // value being tested. 2395 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2396 Node *iff = proj->in(0); 2397 if( iff->Opcode() == Op_If ) { 2398 // During matching If's have Bool & Cmp side-by-side 2399 BoolNode *b = iff->in(1)->as_Bool(); 2400 Node *cmp = iff->in(2); 2401 int opc = cmp->Opcode(); 2402 if (opc != Op_CmpP && opc != Op_CmpN) return; 2403 2404 const Type* ct = cmp->in(2)->bottom_type(); 2405 if (ct == TypePtr::NULL_PTR || 2406 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2407 2408 bool push_it = false; 2409 if( proj->Opcode() == Op_IfTrue ) { 2410 #ifndef PRODUCT 2411 extern int all_null_checks_found; 2412 all_null_checks_found++; 2413 #endif 2414 if( b->_test._test == BoolTest::ne ) { 2415 push_it = true; 2416 } 2417 } else { 2418 assert( proj->Opcode() == Op_IfFalse, "" ); 2419 if( b->_test._test == BoolTest::eq ) { 2420 push_it = true; 2421 } 2422 } 2423 if( push_it ) { 2424 _null_check_tests.push(proj); 2425 Node* val = cmp->in(1); 2426 #ifdef _LP64 2427 if (val->bottom_type()->isa_narrowoop() && 2428 !Matcher::narrow_oop_use_complex_address()) { 2429 // 2430 // Look for DecodeN node which should be pinned to orig_proj. 2431 // On platforms (Sparc) which can not handle 2 adds 2432 // in addressing mode we have to keep a DecodeN node and 2433 // use it to do implicit NULL check in address. 2434 // 2435 // DecodeN node was pinned to non-null path (orig_proj) during 2436 // CastPP transformation in final_graph_reshaping_impl(). 2437 // 2438 uint cnt = orig_proj->outcnt(); 2439 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2440 Node* d = orig_proj->raw_out(i); 2441 if (d->is_DecodeN() && d->in(1) == val) { 2442 val = d; 2443 val->set_req(0, NULL); // Unpin now. 2444 // Mark this as special case to distinguish from 2445 // a regular case: CmpP(DecodeN, NULL). 2446 val = (Node*)(((intptr_t)val) | 1); 2447 break; 2448 } 2449 } 2450 } 2451 #endif 2452 _null_check_tests.push(val); 2453 } 2454 } 2455 } 2456 } 2457 2458 //---------------------------validate_null_checks------------------------------ 2459 // Its possible that the value being NULL checked is not the root of a match 2460 // tree. If so, I cannot use the value in an implicit null check. 2461 void Matcher::validate_null_checks( ) { 2462 uint cnt = _null_check_tests.size(); 2463 for( uint i=0; i < cnt; i+=2 ) { 2464 Node *test = _null_check_tests[i]; 2465 Node *val = _null_check_tests[i+1]; 2466 bool is_decoden = ((intptr_t)val) & 1; 2467 val = (Node*)(((intptr_t)val) & ~1); 2468 if (has_new_node(val)) { 2469 Node* new_val = new_node(val); 2470 if (is_decoden) { 2471 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2472 // Note: new_val may have a control edge if 2473 // the original ideal node DecodeN was matched before 2474 // it was unpinned in Matcher::collect_null_checks(). 2475 // Unpin the mach node and mark it. 2476 new_val->set_req(0, NULL); 2477 new_val = (Node*)(((intptr_t)new_val) | 1); 2478 } 2479 // Is a match-tree root, so replace with the matched value 2480 _null_check_tests.map(i+1, new_val); 2481 } else { 2482 // Yank from candidate list 2483 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2484 _null_check_tests.map(i,_null_check_tests[--cnt]); 2485 _null_check_tests.pop(); 2486 _null_check_tests.pop(); 2487 i-=2; 2488 } 2489 } 2490 } 2491 2492 bool Matcher::gen_narrow_oop_implicit_null_checks() { 2493 // Advice matcher to perform null checks on the narrow oop side. 2494 // Implicit checks are not possible on the uncompressed oop side anyway 2495 // (at least not for read accesses). 2496 // Performs significantly better (especially on Power 6). 2497 if (!os::zero_page_read_protected()) { 2498 return true; 2499 } 2500 return CompressedOops::use_implicit_null_checks() && 2501 (narrow_oop_use_complex_address() || 2502 CompressedOops::base() != NULL); 2503 } 2504 2505 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2506 // atomic instruction acting as a store_load barrier without any 2507 // intervening volatile load, and thus we don't need a barrier here. 2508 // We retain the Node to act as a compiler ordering barrier. 2509 bool Matcher::post_store_load_barrier(const Node* vmb) { 2510 Compile* C = Compile::current(); 2511 assert(vmb->is_MemBar(), ""); 2512 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2513 const MemBarNode* membar = vmb->as_MemBar(); 2514 2515 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2516 Node* ctrl = NULL; 2517 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2518 Node* p = membar->fast_out(i); 2519 assert(p->is_Proj(), "only projections here"); 2520 if ((p->as_Proj()->_con == TypeFunc::Control) && 2521 !C->node_arena()->contains(p)) { // Unmatched old-space only 2522 ctrl = p; 2523 break; 2524 } 2525 } 2526 assert((ctrl != NULL), "missing control projection"); 2527 2528 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2529 Node *x = ctrl->fast_out(j); 2530 int xop = x->Opcode(); 2531 2532 // We don't need current barrier if we see another or a lock 2533 // before seeing volatile load. 2534 // 2535 // Op_Fastunlock previously appeared in the Op_* list below. 2536 // With the advent of 1-0 lock operations we're no longer guaranteed 2537 // that a monitor exit operation contains a serializing instruction. 2538 2539 if (xop == Op_MemBarVolatile || 2540 xop == Op_CompareAndExchangeB || 2541 xop == Op_CompareAndExchangeS || 2542 xop == Op_CompareAndExchangeI || 2543 xop == Op_CompareAndExchangeL || 2544 xop == Op_CompareAndExchangeP || 2545 xop == Op_CompareAndExchangeN || 2546 xop == Op_WeakCompareAndSwapB || 2547 xop == Op_WeakCompareAndSwapS || 2548 xop == Op_WeakCompareAndSwapL || 2549 xop == Op_WeakCompareAndSwapP || 2550 xop == Op_WeakCompareAndSwapN || 2551 xop == Op_WeakCompareAndSwapI || 2552 xop == Op_CompareAndSwapB || 2553 xop == Op_CompareAndSwapS || 2554 xop == Op_CompareAndSwapL || 2555 xop == Op_CompareAndSwapP || 2556 xop == Op_CompareAndSwapN || 2557 xop == Op_CompareAndSwapI || 2558 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) { 2559 return true; 2560 } 2561 2562 // Op_FastLock previously appeared in the Op_* list above. 2563 // With biased locking we're no longer guaranteed that a monitor 2564 // enter operation contains a serializing instruction. 2565 if ((xop == Op_FastLock) && !UseBiasedLocking) { 2566 return true; 2567 } 2568 2569 if (x->is_MemBar()) { 2570 // We must retain this membar if there is an upcoming volatile 2571 // load, which will be followed by acquire membar. 2572 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2573 return false; 2574 } else { 2575 // For other kinds of barriers, check by pretending we 2576 // are them, and seeing if we can be removed. 2577 return post_store_load_barrier(x->as_MemBar()); 2578 } 2579 } 2580 2581 // probably not necessary to check for these 2582 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2583 return false; 2584 } 2585 } 2586 return false; 2587 } 2588 2589 // Check whether node n is a branch to an uncommon trap that we could 2590 // optimize as test with very high branch costs in case of going to 2591 // the uncommon trap. The code must be able to be recompiled to use 2592 // a cheaper test. 2593 bool Matcher::branches_to_uncommon_trap(const Node *n) { 2594 // Don't do it for natives, adapters, or runtime stubs 2595 Compile *C = Compile::current(); 2596 if (!C->is_method_compilation()) return false; 2597 2598 assert(n->is_If(), "You should only call this on if nodes."); 2599 IfNode *ifn = n->as_If(); 2600 2601 Node *ifFalse = NULL; 2602 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2603 if (ifn->fast_out(i)->is_IfFalse()) { 2604 ifFalse = ifn->fast_out(i); 2605 break; 2606 } 2607 } 2608 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2609 2610 Node *reg = ifFalse; 2611 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2612 // Alternatively use visited set? Seems too expensive. 2613 while (reg != NULL && cnt > 0) { 2614 CallNode *call = NULL; 2615 RegionNode *nxt_reg = NULL; 2616 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2617 Node *o = reg->fast_out(i); 2618 if (o->is_Call()) { 2619 call = o->as_Call(); 2620 } 2621 if (o->is_Region()) { 2622 nxt_reg = o->as_Region(); 2623 } 2624 } 2625 2626 if (call && 2627 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2628 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2629 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2630 jint tr_con = trtype->is_int()->get_con(); 2631 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2632 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2633 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2634 2635 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 2636 && action != Deoptimization::Action_none) { 2637 // This uncommon trap is sure to recompile, eventually. 2638 // When that happens, C->too_many_traps will prevent 2639 // this transformation from happening again. 2640 return true; 2641 } 2642 } 2643 } 2644 2645 reg = nxt_reg; 2646 cnt--; 2647 } 2648 2649 return false; 2650 } 2651 2652 //============================================================================= 2653 //---------------------------State--------------------------------------------- 2654 State::State(void) { 2655 #ifdef ASSERT 2656 _id = 0; 2657 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2658 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2659 //memset(_cost, -1, sizeof(_cost)); 2660 //memset(_rule, -1, sizeof(_rule)); 2661 #endif 2662 memset(_valid, 0, sizeof(_valid)); 2663 } 2664 2665 #ifdef ASSERT 2666 State::~State() { 2667 _id = 99; 2668 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2669 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2670 memset(_cost, -3, sizeof(_cost)); 2671 memset(_rule, -3, sizeof(_rule)); 2672 } 2673 #endif 2674 2675 #ifndef PRODUCT 2676 //---------------------------dump---------------------------------------------- 2677 void State::dump() { 2678 tty->print("\n"); 2679 dump(0); 2680 } 2681 2682 void State::dump(int depth) { 2683 for( int j = 0; j < depth; j++ ) 2684 tty->print(" "); 2685 tty->print("--N: "); 2686 _leaf->dump(); 2687 uint i; 2688 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2689 // Check for valid entry 2690 if( valid(i) ) { 2691 for( int j = 0; j < depth; j++ ) 2692 tty->print(" "); 2693 assert(_cost[i] != max_juint, "cost must be a valid value"); 2694 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2695 tty->print_cr("%s %d %s", 2696 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2697 } 2698 tty->cr(); 2699 2700 for( i=0; i<2; i++ ) 2701 if( _kids[i] ) 2702 _kids[i]->dump(depth+1); 2703 } 2704 #endif