32 class Arena;
33 class Bundle;
34 class Block;
35 class Block_Array;
36 class Node;
37 class Node_Array;
38 class Node_List;
39 class PhaseCFG;
40 class PhaseChaitin;
41 class Pipeline_Use_Element;
42 class Pipeline_Use;
43
44 #ifndef PRODUCT
45 #define DEBUG_ARG(x) , x
46 #else
47 #define DEBUG_ARG(x)
48 #endif
49
50 // Define the initial sizes for allocation of the resizable code buffer
51 enum {
52 initial_code_capacity = 16 * 1024,
53 initial_stub_capacity = 4 * 1024,
54 initial_const_capacity = 4 * 1024,
55 initial_locs_capacity = 3 * 1024
56 };
57
58 //------------------------------Scheduling----------------------------------
59 // This class contains all the information necessary to implement instruction
60 // scheduling and bundling.
61 class Scheduling {
62
63 private:
64 // Arena to use
65 Arena *_arena;
66
67 // Control-Flow Graph info
68 PhaseCFG *_cfg;
69
70 // Register Allocation info
71 PhaseRegAlloc *_regalloc;
72
73 // Number of nodes in the method
74 uint _node_bundling_limit;
75
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32 class Arena;
33 class Bundle;
34 class Block;
35 class Block_Array;
36 class Node;
37 class Node_Array;
38 class Node_List;
39 class PhaseCFG;
40 class PhaseChaitin;
41 class Pipeline_Use_Element;
42 class Pipeline_Use;
43
44 #ifndef PRODUCT
45 #define DEBUG_ARG(x) , x
46 #else
47 #define DEBUG_ARG(x)
48 #endif
49
50 // Define the initial sizes for allocation of the resizable code buffer
51 enum {
52 initial_const_capacity = 4 * 1024,
53 };
54
55 //------------------------------Scheduling----------------------------------
56 // This class contains all the information necessary to implement instruction
57 // scheduling and bundling.
58 class Scheduling {
59
60 private:
61 // Arena to use
62 Arena *_arena;
63
64 // Control-Flow Graph info
65 PhaseCFG *_cfg;
66
67 // Register Allocation info
68 PhaseRegAlloc *_regalloc;
69
70 // Number of nodes in the method
71 uint _node_bundling_limit;
72
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