1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
360
361
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
368
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
375
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() const {
378 // if rounding, must let FrameMap know!
379
380 // The frame_map records size in slots (32bit word)
381
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
385
386
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
394
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size());
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
402
403 int offset = code_offset();
404
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
408
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
411
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
435 NOT_LP64(__ get_thread(rsi));
436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
444 }
445
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rsi, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
454
455 if (compilation()->env()->dtrace_method_probes()) {
456 #ifdef _LP64
457 __ mov(rdi, r15_thread);
458 __ mov_metadata(rsi, method()->constant_encoding());
459 #else
460 __ get_thread(rax);
461 __ movptr(Address(rsp, 0), rax);
462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
463 #endif
464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
465 }
466
467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
468 __ mov(rax, rbx); // Restore the exception
469 }
470
471 // remove the activation and dispatch to the unwind handler
472 __ remove_frame(initial_frame_size_in_bytes());
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
474
475 // Emit the slow path assembly
476 if (stub != NULL) {
477 stub->emit_code(this);
478 }
479
480 return offset;
481 }
482
483
484 int LIR_Assembler::emit_deopt_handler() {
485 // if the last instruction is a call (typically to do a throw which
486 // is coming at the end after block reordering) the return address
487 // must still point into the code area in order to avoid assertion
488 // failures when searching for the corresponding bci => add a nop
489 // (was bug 5/14/1999 - gri)
490 __ nop();
491
492 // generate code for exception handler
493 address handler_base = __ start_a_stub(deopt_handler_size());
494 if (handler_base == NULL) {
495 // not enough space left for the handler
496 bailout("deopt handler overflow");
497 return -1;
498 }
499
500 int offset = code_offset();
501 InternalAddress here(__ pc());
502
503 __ pushptr(here.addr());
504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
506 __ end_a_stub();
507
508 return offset;
509 }
510
511
512 void LIR_Assembler::return_op(LIR_Opr result) {
513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
515 assert(result->fpu() == 0, "result must already be on TOS");
516 }
517
518 // Pop the stack before the safepoint code
519 __ remove_frame(initial_frame_size_in_bytes());
520
521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
522 __ reserved_stack_check();
523 }
524
525 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529
530 if (SafepointMechanism::uses_thread_local_poll()) {
531 #ifdef _LP64
532 const Register poll_addr = rscratch1;
533 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
534 #else
535 const Register poll_addr = rbx;
536 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
537 __ get_thread(poll_addr);
538 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
539 #endif
540 __ relocate(relocInfo::poll_return_type);
541 __ testl(rax, Address(poll_addr, 0));
542 } else {
543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
544
545 if (Assembler::is_polling_page_far()) {
546 __ lea(rscratch1, polling_page);
547 __ relocate(relocInfo::poll_return_type);
548 __ testl(rax, Address(rscratch1, 0));
549 } else {
550 __ testl(rax, polling_page);
551 }
552 }
553 __ ret(0);
554 }
555
556
557 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
558 guarantee(info != NULL, "Shouldn't be NULL");
559 int offset = __ offset();
560 if (SafepointMechanism::uses_thread_local_poll()) {
561 #ifdef _LP64
562 const Register poll_addr = rscratch1;
563 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
564 #else
565 assert(tmp->is_cpu_register(), "needed");
566 const Register poll_addr = tmp->as_register();
567 __ get_thread(poll_addr);
568 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
569 #endif
570 add_debug_info_for_branch(info);
571 __ relocate(relocInfo::poll_type);
572 address pre_pc = __ pc();
573 __ testl(rax, Address(poll_addr, 0));
574 address post_pc = __ pc();
575 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
576 } else {
577 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
578 if (Assembler::is_polling_page_far()) {
579 __ lea(rscratch1, polling_page);
580 offset = __ offset();
581 add_debug_info_for_branch(info);
582 __ relocate(relocInfo::poll_type);
583 __ testl(rax, Address(rscratch1, 0));
584 } else {
585 add_debug_info_for_branch(info);
586 __ testl(rax, polling_page);
587 }
588 }
589 return offset;
590 }
591
592
593 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
594 if (from_reg != to_reg) __ mov(to_reg, from_reg);
595 }
596
597 void LIR_Assembler::swap_reg(Register a, Register b) {
598 __ xchgptr(a, b);
599 }
600
601
602 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
603 assert(src->is_constant(), "should not call otherwise");
604 assert(dest->is_register(), "should not call otherwise");
605 LIR_Const* c = src->as_constant_ptr();
606
607 switch (c->type()) {
608 case T_INT: {
609 assert(patch_code == lir_patch_none, "no patching handled here");
610 __ movl(dest->as_register(), c->as_jint());
611 break;
612 }
613
614 case T_ADDRESS: {
615 assert(patch_code == lir_patch_none, "no patching handled here");
616 __ movptr(dest->as_register(), c->as_jint());
617 break;
618 }
619
620 case T_LONG: {
621 assert(patch_code == lir_patch_none, "no patching handled here");
622 #ifdef _LP64
623 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
624 #else
625 __ movptr(dest->as_register_lo(), c->as_jint_lo());
626 __ movptr(dest->as_register_hi(), c->as_jint_hi());
627 #endif // _LP64
628 break;
629 }
630
631 case T_OBJECT: {
632 if (patch_code != lir_patch_none) {
633 jobject2reg_with_patching(dest->as_register(), info);
634 } else {
635 __ movoop(dest->as_register(), c->as_jobject());
636 }
637 break;
638 }
639
640 case T_METADATA: {
641 if (patch_code != lir_patch_none) {
642 klass2reg_with_patching(dest->as_register(), info);
643 } else {
644 __ mov_metadata(dest->as_register(), c->as_metadata());
645 }
646 break;
647 }
648
649 case T_FLOAT: {
650 if (dest->is_single_xmm()) {
651 if (c->is_zero_float()) {
652 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
653 } else {
654 __ movflt(dest->as_xmm_float_reg(),
655 InternalAddress(float_constant(c->as_jfloat())));
656 }
657 } else {
658 assert(dest->is_single_fpu(), "must be");
659 assert(dest->fpu_regnr() == 0, "dest must be TOS");
660 if (c->is_zero_float()) {
661 __ fldz();
662 } else if (c->is_one_float()) {
663 __ fld1();
664 } else {
665 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
666 }
667 }
668 break;
669 }
670
671 case T_DOUBLE: {
672 if (dest->is_double_xmm()) {
673 if (c->is_zero_double()) {
674 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
675 } else {
676 __ movdbl(dest->as_xmm_double_reg(),
677 InternalAddress(double_constant(c->as_jdouble())));
678 }
679 } else {
680 assert(dest->is_double_fpu(), "must be");
681 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
682 if (c->is_zero_double()) {
683 __ fldz();
684 } else if (c->is_one_double()) {
685 __ fld1();
686 } else {
687 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
688 }
689 }
690 break;
691 }
692
693 default:
694 ShouldNotReachHere();
695 }
696 }
697
698 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
699 assert(src->is_constant(), "should not call otherwise");
700 assert(dest->is_stack(), "should not call otherwise");
701 LIR_Const* c = src->as_constant_ptr();
702
703 switch (c->type()) {
704 case T_INT: // fall through
705 case T_FLOAT:
706 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
707 break;
708
709 case T_ADDRESS:
710 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
711 break;
712
713 case T_OBJECT:
714 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
715 break;
716
717 case T_LONG: // fall through
718 case T_DOUBLE:
719 #ifdef _LP64
720 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
721 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
722 #else
723 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
724 lo_word_offset_in_bytes), c->as_jint_lo_bits());
725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
726 hi_word_offset_in_bytes), c->as_jint_hi_bits());
727 #endif // _LP64
728 break;
729
730 default:
731 ShouldNotReachHere();
732 }
733 }
734
735 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
736 assert(src->is_constant(), "should not call otherwise");
737 assert(dest->is_address(), "should not call otherwise");
738 LIR_Const* c = src->as_constant_ptr();
739 LIR_Address* addr = dest->as_address_ptr();
740
741 int null_check_here = code_offset();
742 switch (type) {
743 case T_INT: // fall through
744 case T_FLOAT:
745 __ movl(as_Address(addr), c->as_jint_bits());
746 break;
747
748 case T_ADDRESS:
749 __ movptr(as_Address(addr), c->as_jint_bits());
750 break;
751
752 case T_OBJECT: // fall through
753 case T_ARRAY:
754 if (c->as_jobject() == NULL) {
755 if (UseCompressedOops && !wide) {
756 __ movl(as_Address(addr), (int32_t)NULL_WORD);
757 } else {
758 #ifdef _LP64
759 __ xorptr(rscratch1, rscratch1);
760 null_check_here = code_offset();
761 __ movptr(as_Address(addr), rscratch1);
762 #else
763 __ movptr(as_Address(addr), NULL_WORD);
764 #endif
765 }
766 } else {
767 if (is_literal_address(addr)) {
768 ShouldNotReachHere();
769 __ movoop(as_Address(addr, noreg), c->as_jobject());
770 } else {
771 #ifdef _LP64
772 __ movoop(rscratch1, c->as_jobject());
773 if (UseCompressedOops && !wide) {
774 __ encode_heap_oop(rscratch1);
775 null_check_here = code_offset();
776 __ movl(as_Address_lo(addr), rscratch1);
777 } else {
778 null_check_here = code_offset();
779 __ movptr(as_Address_lo(addr), rscratch1);
780 }
781 #else
782 __ movoop(as_Address(addr), c->as_jobject());
783 #endif
784 }
785 }
786 break;
787
788 case T_LONG: // fall through
789 case T_DOUBLE:
790 #ifdef _LP64
791 if (is_literal_address(addr)) {
792 ShouldNotReachHere();
793 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
794 } else {
795 __ movptr(r10, (intptr_t)c->as_jlong_bits());
796 null_check_here = code_offset();
797 __ movptr(as_Address_lo(addr), r10);
798 }
799 #else
800 // Always reachable in 32bit so this doesn't produce useless move literal
801 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
802 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
803 #endif // _LP64
804 break;
805
806 case T_BOOLEAN: // fall through
807 case T_BYTE:
808 __ movb(as_Address(addr), c->as_jint() & 0xFF);
809 break;
810
811 case T_CHAR: // fall through
812 case T_SHORT:
813 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
814 break;
815
816 default:
817 ShouldNotReachHere();
818 };
819
820 if (info != NULL) {
821 add_debug_info_for_null_check(null_check_here, info);
822 }
823 }
824
825
826 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
827 assert(src->is_register(), "should not call otherwise");
828 assert(dest->is_register(), "should not call otherwise");
829
830 // move between cpu-registers
831 if (dest->is_single_cpu()) {
832 #ifdef _LP64
833 if (src->type() == T_LONG) {
834 // Can do LONG -> OBJECT
835 move_regs(src->as_register_lo(), dest->as_register());
836 return;
837 }
838 #endif
839 assert(src->is_single_cpu(), "must match");
840 if (src->type() == T_OBJECT) {
841 __ verify_oop(src->as_register());
842 }
843 move_regs(src->as_register(), dest->as_register());
844
845 } else if (dest->is_double_cpu()) {
846 #ifdef _LP64
847 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
848 // Surprising to me but we can see move of a long to t_object
849 __ verify_oop(src->as_register());
850 move_regs(src->as_register(), dest->as_register_lo());
851 return;
852 }
853 #endif
854 assert(src->is_double_cpu(), "must match");
855 Register f_lo = src->as_register_lo();
856 Register f_hi = src->as_register_hi();
857 Register t_lo = dest->as_register_lo();
858 Register t_hi = dest->as_register_hi();
859 #ifdef _LP64
860 assert(f_hi == f_lo, "must be same");
861 assert(t_hi == t_lo, "must be same");
862 move_regs(f_lo, t_lo);
863 #else
864 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
865
866
867 if (f_lo == t_hi && f_hi == t_lo) {
868 swap_reg(f_lo, f_hi);
869 } else if (f_hi == t_lo) {
870 assert(f_lo != t_hi, "overwriting register");
871 move_regs(f_hi, t_hi);
872 move_regs(f_lo, t_lo);
873 } else {
874 assert(f_hi != t_lo, "overwriting register");
875 move_regs(f_lo, t_lo);
876 move_regs(f_hi, t_hi);
877 }
878 #endif // LP64
879
880 // special moves from fpu-register to xmm-register
881 // necessary for method results
882 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
883 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
884 __ fld_s(Address(rsp, 0));
885 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
886 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
887 __ fld_d(Address(rsp, 0));
888 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
889 __ fstp_s(Address(rsp, 0));
890 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
891 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
892 __ fstp_d(Address(rsp, 0));
893 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
894
895 // move between xmm-registers
896 } else if (dest->is_single_xmm()) {
897 assert(src->is_single_xmm(), "must match");
898 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
899 } else if (dest->is_double_xmm()) {
900 assert(src->is_double_xmm(), "must match");
901 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
902
903 // move between fpu-registers (no instruction necessary because of fpu-stack)
904 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
905 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
906 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
907 } else {
908 ShouldNotReachHere();
909 }
910 }
911
912 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
913 assert(src->is_register(), "should not call otherwise");
914 assert(dest->is_stack(), "should not call otherwise");
915
916 if (src->is_single_cpu()) {
917 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
918 if (type == T_OBJECT || type == T_ARRAY) {
919 __ verify_oop(src->as_register());
920 __ movptr (dst, src->as_register());
921 } else if (type == T_METADATA) {
922 __ movptr (dst, src->as_register());
923 } else {
924 __ movl (dst, src->as_register());
925 }
926
927 } else if (src->is_double_cpu()) {
928 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
929 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
930 __ movptr (dstLO, src->as_register_lo());
931 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
932
933 } else if (src->is_single_xmm()) {
934 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
935 __ movflt(dst_addr, src->as_xmm_float_reg());
936
937 } else if (src->is_double_xmm()) {
938 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
939 __ movdbl(dst_addr, src->as_xmm_double_reg());
940
941 } else if (src->is_single_fpu()) {
942 assert(src->fpu_regnr() == 0, "argument must be on TOS");
943 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
944 if (pop_fpu_stack) __ fstp_s (dst_addr);
945 else __ fst_s (dst_addr);
946
947 } else if (src->is_double_fpu()) {
948 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
949 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
950 if (pop_fpu_stack) __ fstp_d (dst_addr);
951 else __ fst_d (dst_addr);
952
953 } else {
954 ShouldNotReachHere();
955 }
956 }
957
958
959 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
960 LIR_Address* to_addr = dest->as_address_ptr();
961 PatchingStub* patch = NULL;
962 Register compressed_src = rscratch1;
963
964 if (type == T_ARRAY || type == T_OBJECT) {
965 __ verify_oop(src->as_register());
966 #ifdef _LP64
967 if (UseCompressedOops && !wide) {
968 __ movptr(compressed_src, src->as_register());
969 __ encode_heap_oop(compressed_src);
970 if (patch_code != lir_patch_none) {
971 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
972 }
973 }
974 #endif
975 }
976
977 if (patch_code != lir_patch_none) {
978 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
979 Address toa = as_Address(to_addr);
980 assert(toa.disp() != 0, "must have");
981 }
982
983 int null_check_here = code_offset();
984 switch (type) {
985 case T_FLOAT: {
986 if (src->is_single_xmm()) {
987 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
988 } else {
989 assert(src->is_single_fpu(), "must be");
990 assert(src->fpu_regnr() == 0, "argument must be on TOS");
991 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
992 else __ fst_s (as_Address(to_addr));
993 }
994 break;
995 }
996
997 case T_DOUBLE: {
998 if (src->is_double_xmm()) {
999 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1000 } else {
1001 assert(src->is_double_fpu(), "must be");
1002 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1003 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1004 else __ fst_d (as_Address(to_addr));
1005 }
1006 break;
1007 }
1008
1009 case T_ARRAY: // fall through
1010 case T_OBJECT: // fall through
1011 if (UseCompressedOops && !wide) {
1012 __ movl(as_Address(to_addr), compressed_src);
1013 } else {
1014 __ movptr(as_Address(to_addr), src->as_register());
1015 }
1016 break;
1017 case T_METADATA:
1018 // We get here to store a method pointer to the stack to pass to
1019 // a dtrace runtime call. This can't work on 64 bit with
1020 // compressed klass ptrs: T_METADATA can be a compressed klass
1021 // ptr or a 64 bit method pointer.
1022 LP64_ONLY(ShouldNotReachHere());
1023 __ movptr(as_Address(to_addr), src->as_register());
1024 break;
1025 case T_ADDRESS:
1026 __ movptr(as_Address(to_addr), src->as_register());
1027 break;
1028 case T_INT:
1029 __ movl(as_Address(to_addr), src->as_register());
1030 break;
1031
1032 case T_LONG: {
1033 Register from_lo = src->as_register_lo();
1034 Register from_hi = src->as_register_hi();
1035 #ifdef _LP64
1036 __ movptr(as_Address_lo(to_addr), from_lo);
1037 #else
1038 Register base = to_addr->base()->as_register();
1039 Register index = noreg;
1040 if (to_addr->index()->is_register()) {
1041 index = to_addr->index()->as_register();
1042 }
1043 if (base == from_lo || index == from_lo) {
1044 assert(base != from_hi, "can't be");
1045 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1046 __ movl(as_Address_hi(to_addr), from_hi);
1047 if (patch != NULL) {
1048 patching_epilog(patch, lir_patch_high, base, info);
1049 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1050 patch_code = lir_patch_low;
1051 }
1052 __ movl(as_Address_lo(to_addr), from_lo);
1053 } else {
1054 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1055 __ movl(as_Address_lo(to_addr), from_lo);
1056 if (patch != NULL) {
1057 patching_epilog(patch, lir_patch_low, base, info);
1058 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1059 patch_code = lir_patch_high;
1060 }
1061 __ movl(as_Address_hi(to_addr), from_hi);
1062 }
1063 #endif // _LP64
1064 break;
1065 }
1066
1067 case T_BYTE: // fall through
1068 case T_BOOLEAN: {
1069 Register src_reg = src->as_register();
1070 Address dst_addr = as_Address(to_addr);
1071 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1072 __ movb(dst_addr, src_reg);
1073 break;
1074 }
1075
1076 case T_CHAR: // fall through
1077 case T_SHORT:
1078 __ movw(as_Address(to_addr), src->as_register());
1079 break;
1080
1081 default:
1082 ShouldNotReachHere();
1083 }
1084 if (info != NULL) {
1085 add_debug_info_for_null_check(null_check_here, info);
1086 }
1087
1088 if (patch_code != lir_patch_none) {
1089 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1090 }
1091 }
1092
1093
1094 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1095 assert(src->is_stack(), "should not call otherwise");
1096 assert(dest->is_register(), "should not call otherwise");
1097
1098 if (dest->is_single_cpu()) {
1099 if (type == T_ARRAY || type == T_OBJECT) {
1100 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1101 __ verify_oop(dest->as_register());
1102 } else if (type == T_METADATA) {
1103 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1104 } else {
1105 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1106 }
1107
1108 } else if (dest->is_double_cpu()) {
1109 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1110 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1111 __ movptr(dest->as_register_lo(), src_addr_LO);
1112 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1113
1114 } else if (dest->is_single_xmm()) {
1115 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1116 __ movflt(dest->as_xmm_float_reg(), src_addr);
1117
1118 } else if (dest->is_double_xmm()) {
1119 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1120 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1121
1122 } else if (dest->is_single_fpu()) {
1123 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1124 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1125 __ fld_s(src_addr);
1126
1127 } else if (dest->is_double_fpu()) {
1128 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1129 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1130 __ fld_d(src_addr);
1131
1132 } else {
1133 ShouldNotReachHere();
1134 }
1135 }
1136
1137
1138 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1139 if (src->is_single_stack()) {
1140 if (type == T_OBJECT || type == T_ARRAY) {
1141 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1142 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1143 } else {
1144 #ifndef _LP64
1145 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1146 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1147 #else
1148 //no pushl on 64bits
1149 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1150 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1151 #endif
1152 }
1153
1154 } else if (src->is_double_stack()) {
1155 #ifdef _LP64
1156 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1157 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1158 #else
1159 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1160 // push and pop the part at src + wordSize, adding wordSize for the previous push
1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1162 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1164 #endif // _LP64
1165
1166 } else {
1167 ShouldNotReachHere();
1168 }
1169 }
1170
1171
1172 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1173 assert(src->is_address(), "should not call otherwise");
1174 assert(dest->is_register(), "should not call otherwise");
1175
1176 LIR_Address* addr = src->as_address_ptr();
1177 Address from_addr = as_Address(addr);
1178
1179 if (addr->base()->type() == T_OBJECT) {
1180 __ verify_oop(addr->base()->as_pointer_register());
1181 }
1182
1183 switch (type) {
1184 case T_BOOLEAN: // fall through
1185 case T_BYTE: // fall through
1186 case T_CHAR: // fall through
1187 case T_SHORT:
1188 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1189 // on pre P6 processors we may get partial register stalls
1190 // so blow away the value of to_rinfo before loading a
1191 // partial word into it. Do it here so that it precedes
1192 // the potential patch point below.
1193 __ xorptr(dest->as_register(), dest->as_register());
1194 }
1195 break;
1196 default:
1197 break;
1198 }
1199
1200 PatchingStub* patch = NULL;
1201 if (patch_code != lir_patch_none) {
1202 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1203 assert(from_addr.disp() != 0, "must have");
1204 }
1205 if (info != NULL) {
1206 add_debug_info_for_null_check_here(info);
1207 }
1208
1209 switch (type) {
1210 case T_FLOAT: {
1211 if (dest->is_single_xmm()) {
1212 __ movflt(dest->as_xmm_float_reg(), from_addr);
1213 } else {
1214 assert(dest->is_single_fpu(), "must be");
1215 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1216 __ fld_s(from_addr);
1217 }
1218 break;
1219 }
1220
1221 case T_DOUBLE: {
1222 if (dest->is_double_xmm()) {
1223 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1224 } else {
1225 assert(dest->is_double_fpu(), "must be");
1226 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1227 __ fld_d(from_addr);
1228 }
1229 break;
1230 }
1231
1232 case T_OBJECT: // fall through
1233 case T_ARRAY: // fall through
1234 if (UseCompressedOops && !wide) {
1235 __ movl(dest->as_register(), from_addr);
1236 } else {
1237 __ movptr(dest->as_register(), from_addr);
1238 }
1239 break;
1240
1241 case T_ADDRESS:
1242 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1243 __ movl(dest->as_register(), from_addr);
1244 } else {
1245 __ movptr(dest->as_register(), from_addr);
1246 }
1247 break;
1248 case T_INT:
1249 __ movl(dest->as_register(), from_addr);
1250 break;
1251
1252 case T_LONG: {
1253 Register to_lo = dest->as_register_lo();
1254 Register to_hi = dest->as_register_hi();
1255 #ifdef _LP64
1256 __ movptr(to_lo, as_Address_lo(addr));
1257 #else
1258 Register base = addr->base()->as_register();
1259 Register index = noreg;
1260 if (addr->index()->is_register()) {
1261 index = addr->index()->as_register();
1262 }
1263 if ((base == to_lo && index == to_hi) ||
1264 (base == to_hi && index == to_lo)) {
1265 // addresses with 2 registers are only formed as a result of
1266 // array access so this code will never have to deal with
1267 // patches or null checks.
1268 assert(info == NULL && patch == NULL, "must be");
1269 __ lea(to_hi, as_Address(addr));
1270 __ movl(to_lo, Address(to_hi, 0));
1271 __ movl(to_hi, Address(to_hi, BytesPerWord));
1272 } else if (base == to_lo || index == to_lo) {
1273 assert(base != to_hi, "can't be");
1274 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1275 __ movl(to_hi, as_Address_hi(addr));
1276 if (patch != NULL) {
1277 patching_epilog(patch, lir_patch_high, base, info);
1278 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1279 patch_code = lir_patch_low;
1280 }
1281 __ movl(to_lo, as_Address_lo(addr));
1282 } else {
1283 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1284 __ movl(to_lo, as_Address_lo(addr));
1285 if (patch != NULL) {
1286 patching_epilog(patch, lir_patch_low, base, info);
1287 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1288 patch_code = lir_patch_high;
1289 }
1290 __ movl(to_hi, as_Address_hi(addr));
1291 }
1292 #endif // _LP64
1293 break;
1294 }
1295
1296 case T_BOOLEAN: // fall through
1297 case T_BYTE: {
1298 Register dest_reg = dest->as_register();
1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1301 __ movsbl(dest_reg, from_addr);
1302 } else {
1303 __ movb(dest_reg, from_addr);
1304 __ shll(dest_reg, 24);
1305 __ sarl(dest_reg, 24);
1306 }
1307 break;
1308 }
1309
1310 case T_CHAR: {
1311 Register dest_reg = dest->as_register();
1312 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1313 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1314 __ movzwl(dest_reg, from_addr);
1315 } else {
1316 __ movw(dest_reg, from_addr);
1317 }
1318 break;
1319 }
1320
1321 case T_SHORT: {
1322 Register dest_reg = dest->as_register();
1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1324 __ movswl(dest_reg, from_addr);
1325 } else {
1326 __ movw(dest_reg, from_addr);
1327 __ shll(dest_reg, 16);
1328 __ sarl(dest_reg, 16);
1329 }
1330 break;
1331 }
1332
1333 default:
1334 ShouldNotReachHere();
1335 }
1336
1337 if (patch != NULL) {
1338 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1339 }
1340
1341 if (type == T_ARRAY || type == T_OBJECT) {
1342 #ifdef _LP64
1343 if (UseCompressedOops && !wide) {
1344 __ decode_heap_oop(dest->as_register());
1345 }
1346 #endif
1347 if (!UseLoadBarrier) {
1348 // Load barrier not yet applied, so a verification here would fail
1349 __ verify_oop(dest->as_register());
1350 }
1351 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1352 #ifdef _LP64
1353 if (UseCompressedClassPointers) {
1354 __ decode_klass_not_null(dest->as_register());
1355 }
1356 #endif
1357 }
1358 }
1359
1360
1361 NEEDS_CLEANUP; // This could be static?
1362 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1363 int elem_size = type2aelembytes(type);
1364 switch (elem_size) {
1365 case 1: return Address::times_1;
1366 case 2: return Address::times_2;
1367 case 4: return Address::times_4;
1368 case 8: return Address::times_8;
1369 }
1370 ShouldNotReachHere();
1371 return Address::no_scale;
1372 }
1373
1374
1375 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1376 switch (op->code()) {
1377 case lir_idiv:
1378 case lir_irem:
1379 arithmetic_idiv(op->code(),
1380 op->in_opr1(),
1381 op->in_opr2(),
1382 op->in_opr3(),
1383 op->result_opr(),
1384 op->info());
1385 break;
1386 case lir_fmad:
1387 __ fmad(op->result_opr()->as_xmm_double_reg(),
1388 op->in_opr1()->as_xmm_double_reg(),
1389 op->in_opr2()->as_xmm_double_reg(),
1390 op->in_opr3()->as_xmm_double_reg());
1391 break;
1392 case lir_fmaf:
1393 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1394 op->in_opr1()->as_xmm_float_reg(),
1395 op->in_opr2()->as_xmm_float_reg(),
1396 op->in_opr3()->as_xmm_float_reg());
1397 break;
1398 default: ShouldNotReachHere(); break;
1399 }
1400 }
1401
1402 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1403 #ifdef ASSERT
1404 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1405 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1406 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1407 #endif
1408
1409 if (op->cond() == lir_cond_always) {
1410 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1411 __ jmp (*(op->label()));
1412 } else {
1413 Assembler::Condition acond = Assembler::zero;
1414 if (op->code() == lir_cond_float_branch) {
1415 assert(op->ublock() != NULL, "must have unordered successor");
1416 __ jcc(Assembler::parity, *(op->ublock()->label()));
1417 switch(op->cond()) {
1418 case lir_cond_equal: acond = Assembler::equal; break;
1419 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1420 case lir_cond_less: acond = Assembler::below; break;
1421 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1422 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1423 case lir_cond_greater: acond = Assembler::above; break;
1424 default: ShouldNotReachHere();
1425 }
1426 } else {
1427 switch (op->cond()) {
1428 case lir_cond_equal: acond = Assembler::equal; break;
1429 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1430 case lir_cond_less: acond = Assembler::less; break;
1431 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1432 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1433 case lir_cond_greater: acond = Assembler::greater; break;
1434 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1435 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1436 default: ShouldNotReachHere();
1437 }
1438 }
1439 __ jcc(acond,*(op->label()));
1440 }
1441 }
1442
1443 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1444 LIR_Opr src = op->in_opr();
1445 LIR_Opr dest = op->result_opr();
1446
1447 switch (op->bytecode()) {
1448 case Bytecodes::_i2l:
1449 #ifdef _LP64
1450 __ movl2ptr(dest->as_register_lo(), src->as_register());
1451 #else
1452 move_regs(src->as_register(), dest->as_register_lo());
1453 move_regs(src->as_register(), dest->as_register_hi());
1454 __ sarl(dest->as_register_hi(), 31);
1455 #endif // LP64
1456 break;
1457
1458 case Bytecodes::_l2i:
1459 #ifdef _LP64
1460 __ movl(dest->as_register(), src->as_register_lo());
1461 #else
1462 move_regs(src->as_register_lo(), dest->as_register());
1463 #endif
1464 break;
1465
1466 case Bytecodes::_i2b:
1467 move_regs(src->as_register(), dest->as_register());
1468 __ sign_extend_byte(dest->as_register());
1469 break;
1470
1471 case Bytecodes::_i2c:
1472 move_regs(src->as_register(), dest->as_register());
1473 __ andl(dest->as_register(), 0xFFFF);
1474 break;
1475
1476 case Bytecodes::_i2s:
1477 move_regs(src->as_register(), dest->as_register());
1478 __ sign_extend_short(dest->as_register());
1479 break;
1480
1481
1482 case Bytecodes::_f2d:
1483 case Bytecodes::_d2f:
1484 if (dest->is_single_xmm()) {
1485 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1486 } else if (dest->is_double_xmm()) {
1487 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1488 } else {
1489 assert(src->fpu() == dest->fpu(), "register must be equal");
1490 // do nothing (float result is rounded later through spilling)
1491 }
1492 break;
1493
1494 case Bytecodes::_i2f:
1495 case Bytecodes::_i2d:
1496 if (dest->is_single_xmm()) {
1497 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1498 } else if (dest->is_double_xmm()) {
1499 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1500 } else {
1501 assert(dest->fpu() == 0, "result must be on TOS");
1502 __ movl(Address(rsp, 0), src->as_register());
1503 __ fild_s(Address(rsp, 0));
1504 }
1505 break;
1506
1507 case Bytecodes::_f2i:
1508 case Bytecodes::_d2i:
1509 if (src->is_single_xmm()) {
1510 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1511 } else if (src->is_double_xmm()) {
1512 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1513 } else {
1514 assert(src->fpu() == 0, "input must be on TOS");
1515 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1516 __ fist_s(Address(rsp, 0));
1517 __ movl(dest->as_register(), Address(rsp, 0));
1518 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1519 }
1520
1521 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1522 assert(op->stub() != NULL, "stub required");
1523 __ cmpl(dest->as_register(), 0x80000000);
1524 __ jcc(Assembler::equal, *op->stub()->entry());
1525 __ bind(*op->stub()->continuation());
1526 break;
1527
1528 case Bytecodes::_l2f:
1529 case Bytecodes::_l2d:
1530 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1531 assert(dest->fpu() == 0, "result must be on TOS");
1532
1533 __ movptr(Address(rsp, 0), src->as_register_lo());
1534 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1535 __ fild_d(Address(rsp, 0));
1536 // float result is rounded later through spilling
1537 break;
1538
1539 case Bytecodes::_f2l:
1540 case Bytecodes::_d2l:
1541 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1542 assert(src->fpu() == 0, "input must be on TOS");
1543 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1544
1545 // instruction sequence too long to inline it here
1546 {
1547 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1548 }
1549 break;
1550
1551 default: ShouldNotReachHere();
1552 }
1553 }
1554
1555 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1556 if (op->init_check()) {
1557 add_debug_info_for_null_check_here(op->stub()->info());
1558 __ cmpb(Address(op->klass()->as_register(),
1559 InstanceKlass::init_state_offset()),
1560 InstanceKlass::fully_initialized);
1561 __ jcc(Assembler::notEqual, *op->stub()->entry());
1562 }
1563 __ allocate_object(op->obj()->as_register(),
1564 op->tmp1()->as_register(),
1565 op->tmp2()->as_register(),
1566 op->header_size(),
1567 op->object_size(),
1568 op->klass()->as_register(),
1569 *op->stub()->entry());
1570 __ bind(*op->stub()->continuation());
1571 }
1572
1573 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1574 Register len = op->len()->as_register();
1575 LP64_ONLY( __ movslq(len, len); )
1576
1577 if (UseSlowPath ||
1578 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1579 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1580 __ jmp(*op->stub()->entry());
1581 } else {
1582 Register tmp1 = op->tmp1()->as_register();
1583 Register tmp2 = op->tmp2()->as_register();
1584 Register tmp3 = op->tmp3()->as_register();
1585 if (len == tmp1) {
1586 tmp1 = tmp3;
1587 } else if (len == tmp2) {
1588 tmp2 = tmp3;
1589 } else if (len == tmp3) {
1590 // everything is ok
1591 } else {
1592 __ mov(tmp3, len);
1593 }
1594 __ allocate_array(op->obj()->as_register(),
1595 len,
1596 tmp1,
1597 tmp2,
1598 arrayOopDesc::header_size(op->type()),
1599 array_element_size(op->type()),
1600 op->klass()->as_register(),
1601 *op->stub()->entry());
1602 }
1603 __ bind(*op->stub()->continuation());
1604 }
1605
1606 void LIR_Assembler::type_profile_helper(Register mdo,
1607 ciMethodData *md, ciProfileData *data,
1608 Register recv, Label* update_done) {
1609 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1610 Label next_test;
1611 // See if the receiver is receiver[n].
1612 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1613 __ jccb(Assembler::notEqual, next_test);
1614 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1615 __ addptr(data_addr, DataLayout::counter_increment);
1616 __ jmp(*update_done);
1617 __ bind(next_test);
1618 }
1619
1620 // Didn't find receiver; find next empty slot and fill it in
1621 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1622 Label next_test;
1623 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1624 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1625 __ jccb(Assembler::notEqual, next_test);
1626 __ movptr(recv_addr, recv);
1627 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1628 __ jmp(*update_done);
1629 __ bind(next_test);
1630 }
1631 }
1632
1633 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1634 // we always need a stub for the failure case.
1635 CodeStub* stub = op->stub();
1636 Register obj = op->object()->as_register();
1637 Register k_RInfo = op->tmp1()->as_register();
1638 Register klass_RInfo = op->tmp2()->as_register();
1639 Register dst = op->result_opr()->as_register();
1640 ciKlass* k = op->klass();
1641 Register Rtmp1 = noreg;
1642
1643 // check if it needs to be profiled
1644 ciMethodData* md = NULL;
1645 ciProfileData* data = NULL;
1646
1647 if (op->should_profile()) {
1648 ciMethod* method = op->profiled_method();
1649 assert(method != NULL, "Should have method");
1650 int bci = op->profiled_bci();
1651 md = method->method_data_or_null();
1652 assert(md != NULL, "Sanity");
1653 data = md->bci_to_data(bci);
1654 assert(data != NULL, "need data for type check");
1655 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1656 }
1657 Label profile_cast_success, profile_cast_failure;
1658 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1659 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1660
1661 if (obj == k_RInfo) {
1662 k_RInfo = dst;
1663 } else if (obj == klass_RInfo) {
1664 klass_RInfo = dst;
1665 }
1666 if (k->is_loaded() && !UseCompressedClassPointers) {
1667 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1668 } else {
1669 Rtmp1 = op->tmp3()->as_register();
1670 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1671 }
1672
1673 assert_different_registers(obj, k_RInfo, klass_RInfo);
1674
1675 __ cmpptr(obj, (int32_t)NULL_WORD);
1676 if (op->should_profile()) {
1677 Label not_null;
1678 __ jccb(Assembler::notEqual, not_null);
1679 // Object is null; update MDO and exit
1680 Register mdo = klass_RInfo;
1681 __ mov_metadata(mdo, md->constant_encoding());
1682 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1683 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1684 __ orl(data_addr, header_bits);
1685 __ jmp(*obj_is_null);
1686 __ bind(not_null);
1687 } else {
1688 __ jcc(Assembler::equal, *obj_is_null);
1689 }
1690
1691 if (!k->is_loaded()) {
1692 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1693 } else {
1694 #ifdef _LP64
1695 __ mov_metadata(k_RInfo, k->constant_encoding());
1696 #endif // _LP64
1697 }
1698 __ verify_oop(obj);
1699
1700 if (op->fast_check()) {
1701 // get object class
1702 // not a safepoint as obj null check happens earlier
1703 #ifdef _LP64
1704 if (UseCompressedClassPointers) {
1705 __ load_klass(Rtmp1, obj);
1706 __ cmpptr(k_RInfo, Rtmp1);
1707 } else {
1708 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1709 }
1710 #else
1711 if (k->is_loaded()) {
1712 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1713 } else {
1714 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1715 }
1716 #endif
1717 __ jcc(Assembler::notEqual, *failure_target);
1718 // successful cast, fall through to profile or jump
1719 } else {
1720 // get object class
1721 // not a safepoint as obj null check happens earlier
1722 __ load_klass(klass_RInfo, obj);
1723 if (k->is_loaded()) {
1724 // See if we get an immediate positive hit
1725 #ifdef _LP64
1726 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1727 #else
1728 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1729 #endif // _LP64
1730 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1731 __ jcc(Assembler::notEqual, *failure_target);
1732 // successful cast, fall through to profile or jump
1733 } else {
1734 // See if we get an immediate positive hit
1735 __ jcc(Assembler::equal, *success_target);
1736 // check for self
1737 #ifdef _LP64
1738 __ cmpptr(klass_RInfo, k_RInfo);
1739 #else
1740 __ cmpklass(klass_RInfo, k->constant_encoding());
1741 #endif // _LP64
1742 __ jcc(Assembler::equal, *success_target);
1743
1744 __ push(klass_RInfo);
1745 #ifdef _LP64
1746 __ push(k_RInfo);
1747 #else
1748 __ pushklass(k->constant_encoding());
1749 #endif // _LP64
1750 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1751 __ pop(klass_RInfo);
1752 __ pop(klass_RInfo);
1753 // result is a boolean
1754 __ cmpl(klass_RInfo, 0);
1755 __ jcc(Assembler::equal, *failure_target);
1756 // successful cast, fall through to profile or jump
1757 }
1758 } else {
1759 // perform the fast part of the checking logic
1760 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1761 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1762 __ push(klass_RInfo);
1763 __ push(k_RInfo);
1764 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1765 __ pop(klass_RInfo);
1766 __ pop(k_RInfo);
1767 // result is a boolean
1768 __ cmpl(k_RInfo, 0);
1769 __ jcc(Assembler::equal, *failure_target);
1770 // successful cast, fall through to profile or jump
1771 }
1772 }
1773 if (op->should_profile()) {
1774 Register mdo = klass_RInfo, recv = k_RInfo;
1775 __ bind(profile_cast_success);
1776 __ mov_metadata(mdo, md->constant_encoding());
1777 __ load_klass(recv, obj);
1778 Label update_done;
1779 type_profile_helper(mdo, md, data, recv, success);
1780 __ jmp(*success);
1781
1782 __ bind(profile_cast_failure);
1783 __ mov_metadata(mdo, md->constant_encoding());
1784 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1785 __ subptr(counter_addr, DataLayout::counter_increment);
1786 __ jmp(*failure);
1787 }
1788 __ jmp(*success);
1789 }
1790
1791
1792 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1793 LIR_Code code = op->code();
1794 if (code == lir_store_check) {
1795 Register value = op->object()->as_register();
1796 Register array = op->array()->as_register();
1797 Register k_RInfo = op->tmp1()->as_register();
1798 Register klass_RInfo = op->tmp2()->as_register();
1799 Register Rtmp1 = op->tmp3()->as_register();
1800
1801 CodeStub* stub = op->stub();
1802
1803 // check if it needs to be profiled
1804 ciMethodData* md = NULL;
1805 ciProfileData* data = NULL;
1806
1807 if (op->should_profile()) {
1808 ciMethod* method = op->profiled_method();
1809 assert(method != NULL, "Should have method");
1810 int bci = op->profiled_bci();
1811 md = method->method_data_or_null();
1812 assert(md != NULL, "Sanity");
1813 data = md->bci_to_data(bci);
1814 assert(data != NULL, "need data for type check");
1815 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1816 }
1817 Label profile_cast_success, profile_cast_failure, done;
1818 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1819 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1820
1821 __ cmpptr(value, (int32_t)NULL_WORD);
1822 if (op->should_profile()) {
1823 Label not_null;
1824 __ jccb(Assembler::notEqual, not_null);
1825 // Object is null; update MDO and exit
1826 Register mdo = klass_RInfo;
1827 __ mov_metadata(mdo, md->constant_encoding());
1828 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1829 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1830 __ orl(data_addr, header_bits);
1831 __ jmp(done);
1832 __ bind(not_null);
1833 } else {
1834 __ jcc(Assembler::equal, done);
1835 }
1836
1837 add_debug_info_for_null_check_here(op->info_for_exception());
1838 __ load_klass(k_RInfo, array);
1839 __ load_klass(klass_RInfo, value);
1840
1841 // get instance klass (it's already uncompressed)
1842 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1843 // perform the fast part of the checking logic
1844 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1845 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1846 __ push(klass_RInfo);
1847 __ push(k_RInfo);
1848 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1849 __ pop(klass_RInfo);
1850 __ pop(k_RInfo);
1851 // result is a boolean
1852 __ cmpl(k_RInfo, 0);
1853 __ jcc(Assembler::equal, *failure_target);
1854 // fall through to the success case
1855
1856 if (op->should_profile()) {
1857 Register mdo = klass_RInfo, recv = k_RInfo;
1858 __ bind(profile_cast_success);
1859 __ mov_metadata(mdo, md->constant_encoding());
1860 __ load_klass(recv, value);
1861 Label update_done;
1862 type_profile_helper(mdo, md, data, recv, &done);
1863 __ jmpb(done);
1864
1865 __ bind(profile_cast_failure);
1866 __ mov_metadata(mdo, md->constant_encoding());
1867 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1868 __ subptr(counter_addr, DataLayout::counter_increment);
1869 __ jmp(*stub->entry());
1870 }
1871
1872 __ bind(done);
1873 } else
1874 if (code == lir_checkcast) {
1875 Register obj = op->object()->as_register();
1876 Register dst = op->result_opr()->as_register();
1877 Label success;
1878 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1879 __ bind(success);
1880 if (dst != obj) {
1881 __ mov(dst, obj);
1882 }
1883 } else
1884 if (code == lir_instanceof) {
1885 Register obj = op->object()->as_register();
1886 Register dst = op->result_opr()->as_register();
1887 Label success, failure, done;
1888 emit_typecheck_helper(op, &success, &failure, &failure);
1889 __ bind(failure);
1890 __ xorptr(dst, dst);
1891 __ jmpb(done);
1892 __ bind(success);
1893 __ movptr(dst, 1);
1894 __ bind(done);
1895 } else {
1896 ShouldNotReachHere();
1897 }
1898
1899 }
1900
1901
1902 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1903 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1904 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1905 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1906 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1907 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1908 Register addr = op->addr()->as_register();
1909 if (os::is_MP()) {
1910 __ lock();
1911 }
1912 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1913
1914 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1915 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1916 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1917 Register newval = op->new_value()->as_register();
1918 Register cmpval = op->cmp_value()->as_register();
1919 assert(cmpval == rax, "wrong register");
1920 assert(newval != NULL, "new val must be register");
1921 assert(cmpval != newval, "cmp and new values must be in different registers");
1922 assert(cmpval != addr, "cmp and addr must be in different registers");
1923 assert(newval != addr, "new value and addr must be in different registers");
1924
1925 if ( op->code() == lir_cas_obj) {
1926 #ifdef _LP64
1927 if (UseCompressedOops) {
1928 __ encode_heap_oop(cmpval);
1929 __ mov(rscratch1, newval);
1930 __ encode_heap_oop(rscratch1);
1931 if (os::is_MP()) {
1932 __ lock();
1933 }
1934 // cmpval (rax) is implicitly used by this instruction
1935 __ cmpxchgl(rscratch1, Address(addr, 0));
1936 } else
1937 #endif
1938 {
1939 if (os::is_MP()) {
1940 __ lock();
1941 }
1942 __ cmpxchgptr(newval, Address(addr, 0));
1943 }
1944 } else {
1945 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1946 if (os::is_MP()) {
1947 __ lock();
1948 }
1949 __ cmpxchgl(newval, Address(addr, 0));
1950 }
1951 #ifdef _LP64
1952 } else if (op->code() == lir_cas_long) {
1953 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1954 Register newval = op->new_value()->as_register_lo();
1955 Register cmpval = op->cmp_value()->as_register_lo();
1956 assert(cmpval == rax, "wrong register");
1957 assert(newval != NULL, "new val must be register");
1958 assert(cmpval != newval, "cmp and new values must be in different registers");
1959 assert(cmpval != addr, "cmp and addr must be in different registers");
1960 assert(newval != addr, "new value and addr must be in different registers");
1961 if (os::is_MP()) {
1962 __ lock();
1963 }
1964 __ cmpxchgq(newval, Address(addr, 0));
1965 #endif // _LP64
1966 } else {
1967 Unimplemented();
1968 }
1969 }
1970
1971 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1972 Assembler::Condition acond, ncond;
1973 switch (condition) {
1974 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1975 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1976 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1977 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1978 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1979 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1980 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1981 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1982 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1983 ShouldNotReachHere();
1984 }
1985
1986 if (opr1->is_cpu_register()) {
1987 reg2reg(opr1, result);
1988 } else if (opr1->is_stack()) {
1989 stack2reg(opr1, result, result->type());
1990 } else if (opr1->is_constant()) {
1991 const2reg(opr1, result, lir_patch_none, NULL);
1992 } else {
1993 ShouldNotReachHere();
1994 }
1995
1996 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1997 // optimized version that does not require a branch
1998 if (opr2->is_single_cpu()) {
1999 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2000 __ cmov(ncond, result->as_register(), opr2->as_register());
2001 } else if (opr2->is_double_cpu()) {
2002 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2003 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2004 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2005 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2006 } else if (opr2->is_single_stack()) {
2007 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2008 } else if (opr2->is_double_stack()) {
2009 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2011 } else {
2012 ShouldNotReachHere();
2013 }
2014
2015 } else {
2016 Label skip;
2017 __ jcc (acond, skip);
2018 if (opr2->is_cpu_register()) {
2019 reg2reg(opr2, result);
2020 } else if (opr2->is_stack()) {
2021 stack2reg(opr2, result, result->type());
2022 } else if (opr2->is_constant()) {
2023 const2reg(opr2, result, lir_patch_none, NULL);
2024 } else {
2025 ShouldNotReachHere();
2026 }
2027 __ bind(skip);
2028 }
2029 }
2030
2031
2032 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2033 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2034
2035 if (left->is_single_cpu()) {
2036 assert(left == dest, "left and dest must be equal");
2037 Register lreg = left->as_register();
2038
2039 if (right->is_single_cpu()) {
2040 // cpu register - cpu register
2041 Register rreg = right->as_register();
2042 switch (code) {
2043 case lir_add: __ addl (lreg, rreg); break;
2044 case lir_sub: __ subl (lreg, rreg); break;
2045 case lir_mul: __ imull(lreg, rreg); break;
2046 default: ShouldNotReachHere();
2047 }
2048
2049 } else if (right->is_stack()) {
2050 // cpu register - stack
2051 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2052 switch (code) {
2053 case lir_add: __ addl(lreg, raddr); break;
2054 case lir_sub: __ subl(lreg, raddr); break;
2055 default: ShouldNotReachHere();
2056 }
2057
2058 } else if (right->is_constant()) {
2059 // cpu register - constant
2060 jint c = right->as_constant_ptr()->as_jint();
2061 switch (code) {
2062 case lir_add: {
2063 __ incrementl(lreg, c);
2064 break;
2065 }
2066 case lir_sub: {
2067 __ decrementl(lreg, c);
2068 break;
2069 }
2070 default: ShouldNotReachHere();
2071 }
2072
2073 } else {
2074 ShouldNotReachHere();
2075 }
2076
2077 } else if (left->is_double_cpu()) {
2078 assert(left == dest, "left and dest must be equal");
2079 Register lreg_lo = left->as_register_lo();
2080 Register lreg_hi = left->as_register_hi();
2081
2082 if (right->is_double_cpu()) {
2083 // cpu register - cpu register
2084 Register rreg_lo = right->as_register_lo();
2085 Register rreg_hi = right->as_register_hi();
2086 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2087 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2088 switch (code) {
2089 case lir_add:
2090 __ addptr(lreg_lo, rreg_lo);
2091 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2092 break;
2093 case lir_sub:
2094 __ subptr(lreg_lo, rreg_lo);
2095 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2096 break;
2097 case lir_mul:
2098 #ifdef _LP64
2099 __ imulq(lreg_lo, rreg_lo);
2100 #else
2101 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2102 __ imull(lreg_hi, rreg_lo);
2103 __ imull(rreg_hi, lreg_lo);
2104 __ addl (rreg_hi, lreg_hi);
2105 __ mull (rreg_lo);
2106 __ addl (lreg_hi, rreg_hi);
2107 #endif // _LP64
2108 break;
2109 default:
2110 ShouldNotReachHere();
2111 }
2112
2113 } else if (right->is_constant()) {
2114 // cpu register - constant
2115 #ifdef _LP64
2116 jlong c = right->as_constant_ptr()->as_jlong_bits();
2117 __ movptr(r10, (intptr_t) c);
2118 switch (code) {
2119 case lir_add:
2120 __ addptr(lreg_lo, r10);
2121 break;
2122 case lir_sub:
2123 __ subptr(lreg_lo, r10);
2124 break;
2125 default:
2126 ShouldNotReachHere();
2127 }
2128 #else
2129 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2130 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2131 switch (code) {
2132 case lir_add:
2133 __ addptr(lreg_lo, c_lo);
2134 __ adcl(lreg_hi, c_hi);
2135 break;
2136 case lir_sub:
2137 __ subptr(lreg_lo, c_lo);
2138 __ sbbl(lreg_hi, c_hi);
2139 break;
2140 default:
2141 ShouldNotReachHere();
2142 }
2143 #endif // _LP64
2144
2145 } else {
2146 ShouldNotReachHere();
2147 }
2148
2149 } else if (left->is_single_xmm()) {
2150 assert(left == dest, "left and dest must be equal");
2151 XMMRegister lreg = left->as_xmm_float_reg();
2152
2153 if (right->is_single_xmm()) {
2154 XMMRegister rreg = right->as_xmm_float_reg();
2155 switch (code) {
2156 case lir_add: __ addss(lreg, rreg); break;
2157 case lir_sub: __ subss(lreg, rreg); break;
2158 case lir_mul_strictfp: // fall through
2159 case lir_mul: __ mulss(lreg, rreg); break;
2160 case lir_div_strictfp: // fall through
2161 case lir_div: __ divss(lreg, rreg); break;
2162 default: ShouldNotReachHere();
2163 }
2164 } else {
2165 Address raddr;
2166 if (right->is_single_stack()) {
2167 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2168 } else if (right->is_constant()) {
2169 // hack for now
2170 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2171 } else {
2172 ShouldNotReachHere();
2173 }
2174 switch (code) {
2175 case lir_add: __ addss(lreg, raddr); break;
2176 case lir_sub: __ subss(lreg, raddr); break;
2177 case lir_mul_strictfp: // fall through
2178 case lir_mul: __ mulss(lreg, raddr); break;
2179 case lir_div_strictfp: // fall through
2180 case lir_div: __ divss(lreg, raddr); break;
2181 default: ShouldNotReachHere();
2182 }
2183 }
2184
2185 } else if (left->is_double_xmm()) {
2186 assert(left == dest, "left and dest must be equal");
2187
2188 XMMRegister lreg = left->as_xmm_double_reg();
2189 if (right->is_double_xmm()) {
2190 XMMRegister rreg = right->as_xmm_double_reg();
2191 switch (code) {
2192 case lir_add: __ addsd(lreg, rreg); break;
2193 case lir_sub: __ subsd(lreg, rreg); break;
2194 case lir_mul_strictfp: // fall through
2195 case lir_mul: __ mulsd(lreg, rreg); break;
2196 case lir_div_strictfp: // fall through
2197 case lir_div: __ divsd(lreg, rreg); break;
2198 default: ShouldNotReachHere();
2199 }
2200 } else {
2201 Address raddr;
2202 if (right->is_double_stack()) {
2203 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2204 } else if (right->is_constant()) {
2205 // hack for now
2206 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2207 } else {
2208 ShouldNotReachHere();
2209 }
2210 switch (code) {
2211 case lir_add: __ addsd(lreg, raddr); break;
2212 case lir_sub: __ subsd(lreg, raddr); break;
2213 case lir_mul_strictfp: // fall through
2214 case lir_mul: __ mulsd(lreg, raddr); break;
2215 case lir_div_strictfp: // fall through
2216 case lir_div: __ divsd(lreg, raddr); break;
2217 default: ShouldNotReachHere();
2218 }
2219 }
2220
2221 } else if (left->is_single_fpu()) {
2222 assert(dest->is_single_fpu(), "fpu stack allocation required");
2223
2224 if (right->is_single_fpu()) {
2225 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2226
2227 } else {
2228 assert(left->fpu_regnr() == 0, "left must be on TOS");
2229 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2230
2231 Address raddr;
2232 if (right->is_single_stack()) {
2233 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2234 } else if (right->is_constant()) {
2235 address const_addr = float_constant(right->as_jfloat());
2236 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2237 // hack for now
2238 raddr = __ as_Address(InternalAddress(const_addr));
2239 } else {
2240 ShouldNotReachHere();
2241 }
2242
2243 switch (code) {
2244 case lir_add: __ fadd_s(raddr); break;
2245 case lir_sub: __ fsub_s(raddr); break;
2246 case lir_mul_strictfp: // fall through
2247 case lir_mul: __ fmul_s(raddr); break;
2248 case lir_div_strictfp: // fall through
2249 case lir_div: __ fdiv_s(raddr); break;
2250 default: ShouldNotReachHere();
2251 }
2252 }
2253
2254 } else if (left->is_double_fpu()) {
2255 assert(dest->is_double_fpu(), "fpu stack allocation required");
2256
2257 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2258 // Double values require special handling for strictfp mul/div on x86
2259 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2260 __ fmulp(left->fpu_regnrLo() + 1);
2261 }
2262
2263 if (right->is_double_fpu()) {
2264 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2265
2266 } else {
2267 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2268 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2269
2270 Address raddr;
2271 if (right->is_double_stack()) {
2272 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2273 } else if (right->is_constant()) {
2274 // hack for now
2275 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2276 } else {
2277 ShouldNotReachHere();
2278 }
2279
2280 switch (code) {
2281 case lir_add: __ fadd_d(raddr); break;
2282 case lir_sub: __ fsub_d(raddr); break;
2283 case lir_mul_strictfp: // fall through
2284 case lir_mul: __ fmul_d(raddr); break;
2285 case lir_div_strictfp: // fall through
2286 case lir_div: __ fdiv_d(raddr); break;
2287 default: ShouldNotReachHere();
2288 }
2289 }
2290
2291 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2292 // Double values require special handling for strictfp mul/div on x86
2293 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2294 __ fmulp(dest->fpu_regnrLo() + 1);
2295 }
2296
2297 } else if (left->is_single_stack() || left->is_address()) {
2298 assert(left == dest, "left and dest must be equal");
2299
2300 Address laddr;
2301 if (left->is_single_stack()) {
2302 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2303 } else if (left->is_address()) {
2304 laddr = as_Address(left->as_address_ptr());
2305 } else {
2306 ShouldNotReachHere();
2307 }
2308
2309 if (right->is_single_cpu()) {
2310 Register rreg = right->as_register();
2311 switch (code) {
2312 case lir_add: __ addl(laddr, rreg); break;
2313 case lir_sub: __ subl(laddr, rreg); break;
2314 default: ShouldNotReachHere();
2315 }
2316 } else if (right->is_constant()) {
2317 jint c = right->as_constant_ptr()->as_jint();
2318 switch (code) {
2319 case lir_add: {
2320 __ incrementl(laddr, c);
2321 break;
2322 }
2323 case lir_sub: {
2324 __ decrementl(laddr, c);
2325 break;
2326 }
2327 default: ShouldNotReachHere();
2328 }
2329 } else {
2330 ShouldNotReachHere();
2331 }
2332
2333 } else {
2334 ShouldNotReachHere();
2335 }
2336 }
2337
2338 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2339 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2340 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2341 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2342
2343 bool left_is_tos = (left_index == 0);
2344 bool dest_is_tos = (dest_index == 0);
2345 int non_tos_index = (left_is_tos ? right_index : left_index);
2346
2347 switch (code) {
2348 case lir_add:
2349 if (pop_fpu_stack) __ faddp(non_tos_index);
2350 else if (dest_is_tos) __ fadd (non_tos_index);
2351 else __ fadda(non_tos_index);
2352 break;
2353
2354 case lir_sub:
2355 if (left_is_tos) {
2356 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2357 else if (dest_is_tos) __ fsub (non_tos_index);
2358 else __ fsubra(non_tos_index);
2359 } else {
2360 if (pop_fpu_stack) __ fsubp (non_tos_index);
2361 else if (dest_is_tos) __ fsubr (non_tos_index);
2362 else __ fsuba (non_tos_index);
2363 }
2364 break;
2365
2366 case lir_mul_strictfp: // fall through
2367 case lir_mul:
2368 if (pop_fpu_stack) __ fmulp(non_tos_index);
2369 else if (dest_is_tos) __ fmul (non_tos_index);
2370 else __ fmula(non_tos_index);
2371 break;
2372
2373 case lir_div_strictfp: // fall through
2374 case lir_div:
2375 if (left_is_tos) {
2376 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2377 else if (dest_is_tos) __ fdiv (non_tos_index);
2378 else __ fdivra(non_tos_index);
2379 } else {
2380 if (pop_fpu_stack) __ fdivp (non_tos_index);
2381 else if (dest_is_tos) __ fdivr (non_tos_index);
2382 else __ fdiva (non_tos_index);
2383 }
2384 break;
2385
2386 case lir_rem:
2387 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2388 __ fremr(noreg);
2389 break;
2390
2391 default:
2392 ShouldNotReachHere();
2393 }
2394 }
2395
2396
2397 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2398 if (value->is_double_xmm()) {
2399 switch(code) {
2400 case lir_abs :
2401 {
2402 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2403 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2404 }
2405 __ andpd(dest->as_xmm_double_reg(),
2406 ExternalAddress((address)double_signmask_pool));
2407 }
2408 break;
2409
2410 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2411 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2412 default : ShouldNotReachHere();
2413 }
2414
2415 } else if (value->is_double_fpu()) {
2416 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2417 switch(code) {
2418 case lir_abs : __ fabs() ; break;
2419 case lir_sqrt : __ fsqrt(); break;
2420 default : ShouldNotReachHere();
2421 }
2422 } else {
2423 Unimplemented();
2424 }
2425 }
2426
2427 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2428 // assert(left->destroys_register(), "check");
2429 if (left->is_single_cpu()) {
2430 Register reg = left->as_register();
2431 if (right->is_constant()) {
2432 int val = right->as_constant_ptr()->as_jint();
2433 switch (code) {
2434 case lir_logic_and: __ andl (reg, val); break;
2435 case lir_logic_or: __ orl (reg, val); break;
2436 case lir_logic_xor: __ xorl (reg, val); break;
2437 default: ShouldNotReachHere();
2438 }
2439 } else if (right->is_stack()) {
2440 // added support for stack operands
2441 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2442 switch (code) {
2443 case lir_logic_and: __ andl (reg, raddr); break;
2444 case lir_logic_or: __ orl (reg, raddr); break;
2445 case lir_logic_xor: __ xorl (reg, raddr); break;
2446 default: ShouldNotReachHere();
2447 }
2448 } else {
2449 Register rright = right->as_register();
2450 switch (code) {
2451 case lir_logic_and: __ andptr (reg, rright); break;
2452 case lir_logic_or : __ orptr (reg, rright); break;
2453 case lir_logic_xor: __ xorptr (reg, rright); break;
2454 default: ShouldNotReachHere();
2455 }
2456 }
2457 move_regs(reg, dst->as_register());
2458 } else {
2459 Register l_lo = left->as_register_lo();
2460 Register l_hi = left->as_register_hi();
2461 if (right->is_constant()) {
2462 #ifdef _LP64
2463 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2464 switch (code) {
2465 case lir_logic_and:
2466 __ andq(l_lo, rscratch1);
2467 break;
2468 case lir_logic_or:
2469 __ orq(l_lo, rscratch1);
2470 break;
2471 case lir_logic_xor:
2472 __ xorq(l_lo, rscratch1);
2473 break;
2474 default: ShouldNotReachHere();
2475 }
2476 #else
2477 int r_lo = right->as_constant_ptr()->as_jint_lo();
2478 int r_hi = right->as_constant_ptr()->as_jint_hi();
2479 switch (code) {
2480 case lir_logic_and:
2481 __ andl(l_lo, r_lo);
2482 __ andl(l_hi, r_hi);
2483 break;
2484 case lir_logic_or:
2485 __ orl(l_lo, r_lo);
2486 __ orl(l_hi, r_hi);
2487 break;
2488 case lir_logic_xor:
2489 __ xorl(l_lo, r_lo);
2490 __ xorl(l_hi, r_hi);
2491 break;
2492 default: ShouldNotReachHere();
2493 }
2494 #endif // _LP64
2495 } else {
2496 #ifdef _LP64
2497 Register r_lo;
2498 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2499 r_lo = right->as_register();
2500 } else {
2501 r_lo = right->as_register_lo();
2502 }
2503 #else
2504 Register r_lo = right->as_register_lo();
2505 Register r_hi = right->as_register_hi();
2506 assert(l_lo != r_hi, "overwriting registers");
2507 #endif
2508 switch (code) {
2509 case lir_logic_and:
2510 __ andptr(l_lo, r_lo);
2511 NOT_LP64(__ andptr(l_hi, r_hi);)
2512 break;
2513 case lir_logic_or:
2514 __ orptr(l_lo, r_lo);
2515 NOT_LP64(__ orptr(l_hi, r_hi);)
2516 break;
2517 case lir_logic_xor:
2518 __ xorptr(l_lo, r_lo);
2519 NOT_LP64(__ xorptr(l_hi, r_hi);)
2520 break;
2521 default: ShouldNotReachHere();
2522 }
2523 }
2524
2525 Register dst_lo = dst->as_register_lo();
2526 Register dst_hi = dst->as_register_hi();
2527
2528 #ifdef _LP64
2529 move_regs(l_lo, dst_lo);
2530 #else
2531 if (dst_lo == l_hi) {
2532 assert(dst_hi != l_lo, "overwriting registers");
2533 move_regs(l_hi, dst_hi);
2534 move_regs(l_lo, dst_lo);
2535 } else {
2536 assert(dst_lo != l_hi, "overwriting registers");
2537 move_regs(l_lo, dst_lo);
2538 move_regs(l_hi, dst_hi);
2539 }
2540 #endif // _LP64
2541 }
2542 }
2543
2544
2545 // we assume that rax, and rdx can be overwritten
2546 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2547
2548 assert(left->is_single_cpu(), "left must be register");
2549 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2550 assert(result->is_single_cpu(), "result must be register");
2551
2552 // assert(left->destroys_register(), "check");
2553 // assert(right->destroys_register(), "check");
2554
2555 Register lreg = left->as_register();
2556 Register dreg = result->as_register();
2557
2558 if (right->is_constant()) {
2559 int divisor = right->as_constant_ptr()->as_jint();
2560 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2561 if (code == lir_idiv) {
2562 assert(lreg == rax, "must be rax,");
2563 assert(temp->as_register() == rdx, "tmp register must be rdx");
2564 __ cdql(); // sign extend into rdx:rax
2565 if (divisor == 2) {
2566 __ subl(lreg, rdx);
2567 } else {
2568 __ andl(rdx, divisor - 1);
2569 __ addl(lreg, rdx);
2570 }
2571 __ sarl(lreg, log2_intptr(divisor));
2572 move_regs(lreg, dreg);
2573 } else if (code == lir_irem) {
2574 Label done;
2575 __ mov(dreg, lreg);
2576 __ andl(dreg, 0x80000000 | (divisor - 1));
2577 __ jcc(Assembler::positive, done);
2578 __ decrement(dreg);
2579 __ orl(dreg, ~(divisor - 1));
2580 __ increment(dreg);
2581 __ bind(done);
2582 } else {
2583 ShouldNotReachHere();
2584 }
2585 } else {
2586 Register rreg = right->as_register();
2587 assert(lreg == rax, "left register must be rax,");
2588 assert(rreg != rdx, "right register must not be rdx");
2589 assert(temp->as_register() == rdx, "tmp register must be rdx");
2590
2591 move_regs(lreg, rax);
2592
2593 int idivl_offset = __ corrected_idivl(rreg);
2594 if (ImplicitDiv0Checks) {
2595 add_debug_info_for_div0(idivl_offset, info);
2596 }
2597 if (code == lir_irem) {
2598 move_regs(rdx, dreg); // result is in rdx
2599 } else {
2600 move_regs(rax, dreg);
2601 }
2602 }
2603 }
2604
2605
2606 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2607 if (opr1->is_single_cpu()) {
2608 Register reg1 = opr1->as_register();
2609 if (opr2->is_single_cpu()) {
2610 // cpu register - cpu register
2611 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2612 __ cmpoop(reg1, opr2->as_register());
2613 } else {
2614 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2615 __ cmpl(reg1, opr2->as_register());
2616 }
2617 } else if (opr2->is_stack()) {
2618 // cpu register - stack
2619 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2620 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2621 } else {
2622 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2623 }
2624 } else if (opr2->is_constant()) {
2625 // cpu register - constant
2626 LIR_Const* c = opr2->as_constant_ptr();
2627 if (c->type() == T_INT) {
2628 __ cmpl(reg1, c->as_jint());
2629 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2630 // In 64bit oops are single register
2631 jobject o = c->as_jobject();
2632 if (o == NULL) {
2633 __ cmpptr(reg1, (int32_t)NULL_WORD);
2634 } else {
2635 __ cmpoop(reg1, o);
2636 }
2637 } else {
2638 fatal("unexpected type: %s", basictype_to_str(c->type()));
2639 }
2640 // cpu register - address
2641 } else if (opr2->is_address()) {
2642 if (op->info() != NULL) {
2643 add_debug_info_for_null_check_here(op->info());
2644 }
2645 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2646 } else {
2647 ShouldNotReachHere();
2648 }
2649
2650 } else if(opr1->is_double_cpu()) {
2651 Register xlo = opr1->as_register_lo();
2652 Register xhi = opr1->as_register_hi();
2653 if (opr2->is_double_cpu()) {
2654 #ifdef _LP64
2655 __ cmpptr(xlo, opr2->as_register_lo());
2656 #else
2657 // cpu register - cpu register
2658 Register ylo = opr2->as_register_lo();
2659 Register yhi = opr2->as_register_hi();
2660 __ subl(xlo, ylo);
2661 __ sbbl(xhi, yhi);
2662 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2663 __ orl(xhi, xlo);
2664 }
2665 #endif // _LP64
2666 } else if (opr2->is_constant()) {
2667 // cpu register - constant 0
2668 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2669 #ifdef _LP64
2670 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2671 #else
2672 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2673 __ orl(xhi, xlo);
2674 #endif // _LP64
2675 } else {
2676 ShouldNotReachHere();
2677 }
2678
2679 } else if (opr1->is_single_xmm()) {
2680 XMMRegister reg1 = opr1->as_xmm_float_reg();
2681 if (opr2->is_single_xmm()) {
2682 // xmm register - xmm register
2683 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2684 } else if (opr2->is_stack()) {
2685 // xmm register - stack
2686 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2687 } else if (opr2->is_constant()) {
2688 // xmm register - constant
2689 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2690 } else if (opr2->is_address()) {
2691 // xmm register - address
2692 if (op->info() != NULL) {
2693 add_debug_info_for_null_check_here(op->info());
2694 }
2695 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2696 } else {
2697 ShouldNotReachHere();
2698 }
2699
2700 } else if (opr1->is_double_xmm()) {
2701 XMMRegister reg1 = opr1->as_xmm_double_reg();
2702 if (opr2->is_double_xmm()) {
2703 // xmm register - xmm register
2704 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2705 } else if (opr2->is_stack()) {
2706 // xmm register - stack
2707 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2708 } else if (opr2->is_constant()) {
2709 // xmm register - constant
2710 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2711 } else if (opr2->is_address()) {
2712 // xmm register - address
2713 if (op->info() != NULL) {
2714 add_debug_info_for_null_check_here(op->info());
2715 }
2716 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2717 } else {
2718 ShouldNotReachHere();
2719 }
2720
2721 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2722 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2723 assert(opr2->is_fpu_register(), "both must be registers");
2724 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2725
2726 } else if (opr1->is_address() && opr2->is_constant()) {
2727 LIR_Const* c = opr2->as_constant_ptr();
2728 #ifdef _LP64
2729 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2730 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2731 __ movoop(rscratch1, c->as_jobject());
2732 }
2733 #endif // LP64
2734 if (op->info() != NULL) {
2735 add_debug_info_for_null_check_here(op->info());
2736 }
2737 // special case: address - constant
2738 LIR_Address* addr = opr1->as_address_ptr();
2739 if (c->type() == T_INT) {
2740 __ cmpl(as_Address(addr), c->as_jint());
2741 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2742 #ifdef _LP64
2743 // %%% Make this explode if addr isn't reachable until we figure out a
2744 // better strategy by giving noreg as the temp for as_Address
2745 __ cmpoop(rscratch1, as_Address(addr, noreg));
2746 #else
2747 __ cmpoop(as_Address(addr), c->as_jobject());
2748 #endif // _LP64
2749 } else {
2750 ShouldNotReachHere();
2751 }
2752
2753 } else {
2754 ShouldNotReachHere();
2755 }
2756 }
2757
2758 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2759 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2760 if (left->is_single_xmm()) {
2761 assert(right->is_single_xmm(), "must match");
2762 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2763 } else if (left->is_double_xmm()) {
2764 assert(right->is_double_xmm(), "must match");
2765 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2766
2767 } else {
2768 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2769 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2770
2771 assert(left->fpu() == 0, "left must be on TOS");
2772 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2773 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2774 }
2775 } else {
2776 assert(code == lir_cmp_l2i, "check");
2777 #ifdef _LP64
2778 Label done;
2779 Register dest = dst->as_register();
2780 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2781 __ movl(dest, -1);
2782 __ jccb(Assembler::less, done);
2783 __ set_byte_if_not_zero(dest);
2784 __ movzbl(dest, dest);
2785 __ bind(done);
2786 #else
2787 __ lcmp2int(left->as_register_hi(),
2788 left->as_register_lo(),
2789 right->as_register_hi(),
2790 right->as_register_lo());
2791 move_regs(left->as_register_hi(), dst->as_register());
2792 #endif // _LP64
2793 }
2794 }
2795
2796
2797 void LIR_Assembler::align_call(LIR_Code code) {
2798 if (os::is_MP()) {
2799 // make sure that the displacement word of the call ends up word aligned
2800 int offset = __ offset();
2801 switch (code) {
2802 case lir_static_call:
2803 case lir_optvirtual_call:
2804 case lir_dynamic_call:
2805 offset += NativeCall::displacement_offset;
2806 break;
2807 case lir_icvirtual_call:
2808 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2809 break;
2810 case lir_virtual_call: // currently, sparc-specific for niagara
2811 default: ShouldNotReachHere();
2812 }
2813 __ align(BytesPerWord, offset);
2814 }
2815 }
2816
2817
2818 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2819 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2820 "must be aligned");
2821 __ call(AddressLiteral(op->addr(), rtype));
2822 add_call_info(code_offset(), op->info());
2823 }
2824
2825
2826 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2827 __ ic_call(op->addr());
2828 add_call_info(code_offset(), op->info());
2829 assert(!os::is_MP() ||
2830 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2831 "must be aligned");
2832 }
2833
2834
2835 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2836 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2837 ShouldNotReachHere();
2838 }
2839
2840
2841 void LIR_Assembler::emit_static_call_stub() {
2842 address call_pc = __ pc();
2843 address stub = __ start_a_stub(call_stub_size());
2844 if (stub == NULL) {
2845 bailout("static call stub overflow");
2846 return;
2847 }
2848
2849 int start = __ offset();
2850 if (os::is_MP()) {
2851 // make sure that the displacement word of the call ends up word aligned
2852 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2853 }
2854 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2855 __ mov_metadata(rbx, (Metadata*)NULL);
2856 // must be set to -1 at code generation time
2857 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2858 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2859 __ jump(RuntimeAddress(__ pc()));
2860
2861 if (UseAOT) {
2862 // Trampoline to aot code
2863 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2864 #ifdef _LP64
2865 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2866 #else
2867 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2868 #endif
2869 __ jmp(rax);
2870 }
2871 assert(__ offset() - start <= call_stub_size(), "stub too big");
2872 __ end_a_stub();
2873 }
2874
2875
2876 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2877 assert(exceptionOop->as_register() == rax, "must match");
2878 assert(exceptionPC->as_register() == rdx, "must match");
2879
2880 // exception object is not added to oop map by LinearScan
2881 // (LinearScan assumes that no oops are in fixed registers)
2882 info->add_register_oop(exceptionOop);
2883 Runtime1::StubID unwind_id;
2884
2885 // get current pc information
2886 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2887 int pc_for_athrow_offset = __ offset();
2888 InternalAddress pc_for_athrow(__ pc());
2889 __ lea(exceptionPC->as_register(), pc_for_athrow);
2890 add_call_info(pc_for_athrow_offset, info); // for exception handler
2891
2892 __ verify_not_null_oop(rax);
2893 // search an exception handler (rax: exception oop, rdx: throwing pc)
2894 if (compilation()->has_fpu_code()) {
2895 unwind_id = Runtime1::handle_exception_id;
2896 } else {
2897 unwind_id = Runtime1::handle_exception_nofpu_id;
2898 }
2899 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2900
2901 // enough room for two byte trap
2902 __ nop();
2903 }
2904
2905
2906 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2907 assert(exceptionOop->as_register() == rax, "must match");
2908
2909 __ jmp(_unwind_handler_entry);
2910 }
2911
2912
2913 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2914
2915 // optimized version for linear scan:
2916 // * count must be already in ECX (guaranteed by LinearScan)
2917 // * left and dest must be equal
2918 // * tmp must be unused
2919 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2920 assert(left == dest, "left and dest must be equal");
2921 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2922
2923 if (left->is_single_cpu()) {
2924 Register value = left->as_register();
2925 assert(value != SHIFT_count, "left cannot be ECX");
2926
2927 switch (code) {
2928 case lir_shl: __ shll(value); break;
2929 case lir_shr: __ sarl(value); break;
2930 case lir_ushr: __ shrl(value); break;
2931 default: ShouldNotReachHere();
2932 }
2933 } else if (left->is_double_cpu()) {
2934 Register lo = left->as_register_lo();
2935 Register hi = left->as_register_hi();
2936 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2937 #ifdef _LP64
2938 switch (code) {
2939 case lir_shl: __ shlptr(lo); break;
2940 case lir_shr: __ sarptr(lo); break;
2941 case lir_ushr: __ shrptr(lo); break;
2942 default: ShouldNotReachHere();
2943 }
2944 #else
2945
2946 switch (code) {
2947 case lir_shl: __ lshl(hi, lo); break;
2948 case lir_shr: __ lshr(hi, lo, true); break;
2949 case lir_ushr: __ lshr(hi, lo, false); break;
2950 default: ShouldNotReachHere();
2951 }
2952 #endif // LP64
2953 } else {
2954 ShouldNotReachHere();
2955 }
2956 }
2957
2958
2959 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2960 if (dest->is_single_cpu()) {
2961 // first move left into dest so that left is not destroyed by the shift
2962 Register value = dest->as_register();
2963 count = count & 0x1F; // Java spec
2964
2965 move_regs(left->as_register(), value);
2966 switch (code) {
2967 case lir_shl: __ shll(value, count); break;
2968 case lir_shr: __ sarl(value, count); break;
2969 case lir_ushr: __ shrl(value, count); break;
2970 default: ShouldNotReachHere();
2971 }
2972 } else if (dest->is_double_cpu()) {
2973 #ifndef _LP64
2974 Unimplemented();
2975 #else
2976 // first move left into dest so that left is not destroyed by the shift
2977 Register value = dest->as_register_lo();
2978 count = count & 0x1F; // Java spec
2979
2980 move_regs(left->as_register_lo(), value);
2981 switch (code) {
2982 case lir_shl: __ shlptr(value, count); break;
2983 case lir_shr: __ sarptr(value, count); break;
2984 case lir_ushr: __ shrptr(value, count); break;
2985 default: ShouldNotReachHere();
2986 }
2987 #endif // _LP64
2988 } else {
2989 ShouldNotReachHere();
2990 }
2991 }
2992
2993 void LIR_Assembler::load_barrier_test(LIR_Opr ref) {
2994 __ testptr(ref->as_register(), Address(r15_thread, JavaThread::zaddress_bad_mask_offset()));
2995 }
2996
2997 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2998 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2999 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3000 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3001 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3002 }
3003
3004
3005 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3006 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3007 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3008 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3009 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3010 }
3011
3012
3013 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3014 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3015 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3016 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3017 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3018 }
3019
3020
3021 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3022 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3023 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3024 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3025 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3026 }
3027
3028
3029 // This code replaces a call to arraycopy; no exception may
3030 // be thrown in this code, they must be thrown in the System.arraycopy
3031 // activation frame; we could save some checks if this would not be the case
3032 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3033 ciArrayKlass* default_type = op->expected_type();
3034 Register src = op->src()->as_register();
3035 Register dst = op->dst()->as_register();
3036 Register src_pos = op->src_pos()->as_register();
3037 Register dst_pos = op->dst_pos()->as_register();
3038 Register length = op->length()->as_register();
3039 Register tmp = op->tmp()->as_register();
3040
3041 CodeStub* stub = op->stub();
3042 int flags = op->flags();
3043 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3044 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3045
3046 // if we don't know anything, just go through the generic arraycopy
3047 if (default_type == NULL) {
3048 Label done;
3049 // save outgoing arguments on stack in case call to System.arraycopy is needed
3050 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3051 // for interpreter calling conventions. Now we have to do it in new style conventions.
3052 // For the moment until C1 gets the new register allocator I just force all the
3053 // args to the right place (except the register args) and then on the back side
3054 // reload the register args properly if we go slow path. Yuck
3055
3056 // These are proper for the calling convention
3057 store_parameter(length, 2);
3058 store_parameter(dst_pos, 1);
3059 store_parameter(dst, 0);
3060
3061 // these are just temporary placements until we need to reload
3062 store_parameter(src_pos, 3);
3063 store_parameter(src, 4);
3064 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3065
3066 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3067
3068 address copyfunc_addr = StubRoutines::generic_arraycopy();
3069
3070 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3071 #ifdef _LP64
3072 // The arguments are in java calling convention so we can trivially shift them to C
3073 // convention
3074 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3075 __ mov(c_rarg0, j_rarg0);
3076 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3077 __ mov(c_rarg1, j_rarg1);
3078 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3079 __ mov(c_rarg2, j_rarg2);
3080 assert_different_registers(c_rarg3, j_rarg4);
3081 __ mov(c_rarg3, j_rarg3);
3082 #ifdef _WIN64
3083 // Allocate abi space for args but be sure to keep stack aligned
3084 __ subptr(rsp, 6*wordSize);
3085 store_parameter(j_rarg4, 4);
3086 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3087 __ call(RuntimeAddress(C_entry));
3088 } else {
3089 #ifndef PRODUCT
3090 if (PrintC1Statistics) {
3091 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3092 }
3093 #endif
3094 __ call(RuntimeAddress(copyfunc_addr));
3095 }
3096 __ addptr(rsp, 6*wordSize);
3097 #else
3098 __ mov(c_rarg4, j_rarg4);
3099 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3100 __ call(RuntimeAddress(C_entry));
3101 } else {
3102 #ifndef PRODUCT
3103 if (PrintC1Statistics) {
3104 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3105 }
3106 #endif
3107 __ call(RuntimeAddress(copyfunc_addr));
3108 }
3109 #endif // _WIN64
3110 #else
3111 __ push(length);
3112 __ push(dst_pos);
3113 __ push(dst);
3114 __ push(src_pos);
3115 __ push(src);
3116
3117 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3118 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3119 } else {
3120 #ifndef PRODUCT
3121 if (PrintC1Statistics) {
3122 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3123 }
3124 #endif
3125 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3126 }
3127
3128 #endif // _LP64
3129
3130 __ cmpl(rax, 0);
3131 __ jcc(Assembler::equal, *stub->continuation());
3132
3133 if (copyfunc_addr != NULL) {
3134 __ mov(tmp, rax);
3135 __ xorl(tmp, -1);
3136 }
3137
3138 // Reload values from the stack so they are where the stub
3139 // expects them.
3140 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3141 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3142 __ movptr (length, Address(rsp, 2*BytesPerWord));
3143 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3144 __ movptr (src, Address(rsp, 4*BytesPerWord));
3145
3146 if (copyfunc_addr != NULL) {
3147 __ subl(length, tmp);
3148 __ addl(src_pos, tmp);
3149 __ addl(dst_pos, tmp);
3150 }
3151 __ jmp(*stub->entry());
3152
3153 __ bind(*stub->continuation());
3154 return;
3155 }
3156
3157 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3158
3159 int elem_size = type2aelembytes(basic_type);
3160 Address::ScaleFactor scale;
3161
3162 switch (elem_size) {
3163 case 1 :
3164 scale = Address::times_1;
3165 break;
3166 case 2 :
3167 scale = Address::times_2;
3168 break;
3169 case 4 :
3170 scale = Address::times_4;
3171 break;
3172 case 8 :
3173 scale = Address::times_8;
3174 break;
3175 default:
3176 scale = Address::no_scale;
3177 ShouldNotReachHere();
3178 }
3179
3180 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3181 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3182 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3183 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3184
3185 // length and pos's are all sign extended at this point on 64bit
3186
3187 // test for NULL
3188 if (flags & LIR_OpArrayCopy::src_null_check) {
3189 __ testptr(src, src);
3190 __ jcc(Assembler::zero, *stub->entry());
3191 }
3192 if (flags & LIR_OpArrayCopy::dst_null_check) {
3193 __ testptr(dst, dst);
3194 __ jcc(Assembler::zero, *stub->entry());
3195 }
3196
3197 // If the compiler was not able to prove that exact type of the source or the destination
3198 // of the arraycopy is an array type, check at runtime if the source or the destination is
3199 // an instance type.
3200 if (flags & LIR_OpArrayCopy::type_check) {
3201 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3202 __ load_klass(tmp, dst);
3203 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3204 __ jcc(Assembler::greaterEqual, *stub->entry());
3205 }
3206
3207 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3208 __ load_klass(tmp, src);
3209 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3210 __ jcc(Assembler::greaterEqual, *stub->entry());
3211 }
3212 }
3213
3214 // check if negative
3215 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3216 __ testl(src_pos, src_pos);
3217 __ jcc(Assembler::less, *stub->entry());
3218 }
3219 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3220 __ testl(dst_pos, dst_pos);
3221 __ jcc(Assembler::less, *stub->entry());
3222 }
3223
3224 if (flags & LIR_OpArrayCopy::src_range_check) {
3225 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3226 __ cmpl(tmp, src_length_addr);
3227 __ jcc(Assembler::above, *stub->entry());
3228 }
3229 if (flags & LIR_OpArrayCopy::dst_range_check) {
3230 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3231 __ cmpl(tmp, dst_length_addr);
3232 __ jcc(Assembler::above, *stub->entry());
3233 }
3234
3235 if (flags & LIR_OpArrayCopy::length_positive_check) {
3236 __ testl(length, length);
3237 __ jcc(Assembler::less, *stub->entry());
3238 }
3239
3240 #ifdef _LP64
3241 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3242 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3243 #endif
3244
3245 if (flags & LIR_OpArrayCopy::type_check) {
3246 // We don't know the array types are compatible
3247 if (basic_type != T_OBJECT) {
3248 // Simple test for basic type arrays
3249 if (UseCompressedClassPointers) {
3250 __ movl(tmp, src_klass_addr);
3251 __ cmpl(tmp, dst_klass_addr);
3252 } else {
3253 __ movptr(tmp, src_klass_addr);
3254 __ cmpptr(tmp, dst_klass_addr);
3255 }
3256 __ jcc(Assembler::notEqual, *stub->entry());
3257 } else {
3258 // For object arrays, if src is a sub class of dst then we can
3259 // safely do the copy.
3260 Label cont, slow;
3261
3262 __ push(src);
3263 __ push(dst);
3264
3265 __ load_klass(src, src);
3266 __ load_klass(dst, dst);
3267
3268 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3269
3270 __ push(src);
3271 __ push(dst);
3272 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3273 __ pop(dst);
3274 __ pop(src);
3275
3276 __ cmpl(src, 0);
3277 __ jcc(Assembler::notEqual, cont);
3278
3279 __ bind(slow);
3280 __ pop(dst);
3281 __ pop(src);
3282
3283 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3284 if (copyfunc_addr != NULL) { // use stub if available
3285 // src is not a sub class of dst so we have to do a
3286 // per-element check.
3287
3288 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3289 if ((flags & mask) != mask) {
3290 // Check that at least both of them object arrays.
3291 assert(flags & mask, "one of the two should be known to be an object array");
3292
3293 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3294 __ load_klass(tmp, src);
3295 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3296 __ load_klass(tmp, dst);
3297 }
3298 int lh_offset = in_bytes(Klass::layout_helper_offset());
3299 Address klass_lh_addr(tmp, lh_offset);
3300 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3301 __ cmpl(klass_lh_addr, objArray_lh);
3302 __ jcc(Assembler::notEqual, *stub->entry());
3303 }
3304
3305 // Spill because stubs can use any register they like and it's
3306 // easier to restore just those that we care about.
3307 store_parameter(dst, 0);
3308 store_parameter(dst_pos, 1);
3309 store_parameter(length, 2);
3310 store_parameter(src_pos, 3);
3311 store_parameter(src, 4);
3312
3313 #ifndef _LP64
3314 __ movptr(tmp, dst_klass_addr);
3315 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3316 __ push(tmp);
3317 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3318 __ push(tmp);
3319 __ push(length);
3320 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3321 __ push(tmp);
3322 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3323 __ push(tmp);
3324
3325 __ call_VM_leaf(copyfunc_addr, 5);
3326 #else
3327 __ movl2ptr(length, length); //higher 32bits must be null
3328
3329 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3330 assert_different_registers(c_rarg0, dst, dst_pos, length);
3331 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3332 assert_different_registers(c_rarg1, dst, length);
3333
3334 __ mov(c_rarg2, length);
3335 assert_different_registers(c_rarg2, dst);
3336
3337 #ifdef _WIN64
3338 // Allocate abi space for args but be sure to keep stack aligned
3339 __ subptr(rsp, 6*wordSize);
3340 __ load_klass(c_rarg3, dst);
3341 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3342 store_parameter(c_rarg3, 4);
3343 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3344 __ call(RuntimeAddress(copyfunc_addr));
3345 __ addptr(rsp, 6*wordSize);
3346 #else
3347 __ load_klass(c_rarg4, dst);
3348 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3349 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3350 __ call(RuntimeAddress(copyfunc_addr));
3351 #endif
3352
3353 #endif
3354
3355 #ifndef PRODUCT
3356 if (PrintC1Statistics) {
3357 Label failed;
3358 __ testl(rax, rax);
3359 __ jcc(Assembler::notZero, failed);
3360 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3361 __ bind(failed);
3362 }
3363 #endif
3364
3365 __ testl(rax, rax);
3366 __ jcc(Assembler::zero, *stub->continuation());
3367
3368 #ifndef PRODUCT
3369 if (PrintC1Statistics) {
3370 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3371 }
3372 #endif
3373
3374 __ mov(tmp, rax);
3375
3376 __ xorl(tmp, -1);
3377
3378 // Restore previously spilled arguments
3379 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3380 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3381 __ movptr (length, Address(rsp, 2*BytesPerWord));
3382 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3383 __ movptr (src, Address(rsp, 4*BytesPerWord));
3384
3385
3386 __ subl(length, tmp);
3387 __ addl(src_pos, tmp);
3388 __ addl(dst_pos, tmp);
3389 }
3390
3391 __ jmp(*stub->entry());
3392
3393 __ bind(cont);
3394 __ pop(dst);
3395 __ pop(src);
3396 }
3397 }
3398
3399 #ifdef ASSERT
3400 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3401 // Sanity check the known type with the incoming class. For the
3402 // primitive case the types must match exactly with src.klass and
3403 // dst.klass each exactly matching the default type. For the
3404 // object array case, if no type check is needed then either the
3405 // dst type is exactly the expected type and the src type is a
3406 // subtype which we can't check or src is the same array as dst
3407 // but not necessarily exactly of type default_type.
3408 Label known_ok, halt;
3409 __ mov_metadata(tmp, default_type->constant_encoding());
3410 #ifdef _LP64
3411 if (UseCompressedClassPointers) {
3412 __ encode_klass_not_null(tmp);
3413 }
3414 #endif
3415
3416 if (basic_type != T_OBJECT) {
3417
3418 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3419 else __ cmpptr(tmp, dst_klass_addr);
3420 __ jcc(Assembler::notEqual, halt);
3421 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3422 else __ cmpptr(tmp, src_klass_addr);
3423 __ jcc(Assembler::equal, known_ok);
3424 } else {
3425 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3426 else __ cmpptr(tmp, dst_klass_addr);
3427 __ jcc(Assembler::equal, known_ok);
3428 __ cmpptr(src, dst);
3429 __ jcc(Assembler::equal, known_ok);
3430 }
3431 __ bind(halt);
3432 __ stop("incorrect type information in arraycopy");
3433 __ bind(known_ok);
3434 }
3435 #endif
3436
3437 #ifndef PRODUCT
3438 if (PrintC1Statistics) {
3439 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3440 }
3441 #endif
3442
3443 #ifdef _LP64
3444 assert_different_registers(c_rarg0, dst, dst_pos, length);
3445 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3446 assert_different_registers(c_rarg1, length);
3447 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3448 __ mov(c_rarg2, length);
3449
3450 #else
3451 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3452 store_parameter(tmp, 0);
3453 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3454 store_parameter(tmp, 1);
3455 store_parameter(length, 2);
3456 #endif // _LP64
3457
3458 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3459 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3460 const char *name;
3461 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3462 __ call_VM_leaf(entry, 0);
3463
3464 __ bind(*stub->continuation());
3465 }
3466
3467 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3468 assert(op->crc()->is_single_cpu(), "crc must be register");
3469 assert(op->val()->is_single_cpu(), "byte value must be register");
3470 assert(op->result_opr()->is_single_cpu(), "result must be register");
3471 Register crc = op->crc()->as_register();
3472 Register val = op->val()->as_register();
3473 Register res = op->result_opr()->as_register();
3474
3475 assert_different_registers(val, crc, res);
3476
3477 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3478 __ notl(crc); // ~crc
3479 __ update_byte_crc32(crc, val, res);
3480 __ notl(crc); // ~crc
3481 __ mov(res, crc);
3482 }
3483
3484 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3485 Register obj = op->obj_opr()->as_register(); // may not be an oop
3486 Register hdr = op->hdr_opr()->as_register();
3487 Register lock = op->lock_opr()->as_register();
3488 if (!UseFastLocking) {
3489 __ jmp(*op->stub()->entry());
3490 } else if (op->code() == lir_lock) {
3491 Register scratch = noreg;
3492 if (UseBiasedLocking) {
3493 scratch = op->scratch_opr()->as_register();
3494 }
3495 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3496 // add debug info for NullPointerException only if one is possible
3497 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3498 if (op->info() != NULL) {
3499 add_debug_info_for_null_check(null_check_offset, op->info());
3500 }
3501 // done
3502 } else if (op->code() == lir_unlock) {
3503 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3504 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3505 } else {
3506 Unimplemented();
3507 }
3508 __ bind(*op->stub()->continuation());
3509 }
3510
3511
3512 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3513 ciMethod* method = op->profiled_method();
3514 int bci = op->profiled_bci();
3515 ciMethod* callee = op->profiled_callee();
3516
3517 // Update counter for all call types
3518 ciMethodData* md = method->method_data_or_null();
3519 assert(md != NULL, "Sanity");
3520 ciProfileData* data = md->bci_to_data(bci);
3521 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3522 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3523 Register mdo = op->mdo()->as_register();
3524 __ mov_metadata(mdo, md->constant_encoding());
3525 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3526 // Perform additional virtual call profiling for invokevirtual and
3527 // invokeinterface bytecodes
3528 if (op->should_profile_receiver_type()) {
3529 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3530 Register recv = op->recv()->as_register();
3531 assert_different_registers(mdo, recv);
3532 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3533 ciKlass* known_klass = op->known_holder();
3534 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3535 // We know the type that will be seen at this call site; we can
3536 // statically update the MethodData* rather than needing to do
3537 // dynamic tests on the receiver type
3538
3539 // NOTE: we should probably put a lock around this search to
3540 // avoid collisions by concurrent compilations
3541 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3542 uint i;
3543 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3544 ciKlass* receiver = vc_data->receiver(i);
3545 if (known_klass->equals(receiver)) {
3546 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3547 __ addptr(data_addr, DataLayout::counter_increment);
3548 return;
3549 }
3550 }
3551
3552 // Receiver type not found in profile data; select an empty slot
3553
3554 // Note that this is less efficient than it should be because it
3555 // always does a write to the receiver part of the
3556 // VirtualCallData rather than just the first time
3557 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3558 ciKlass* receiver = vc_data->receiver(i);
3559 if (receiver == NULL) {
3560 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3561 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3562 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3563 __ addptr(data_addr, DataLayout::counter_increment);
3564 return;
3565 }
3566 }
3567 } else {
3568 __ load_klass(recv, recv);
3569 Label update_done;
3570 type_profile_helper(mdo, md, data, recv, &update_done);
3571 // Receiver did not match any saved receiver and there is no empty row for it.
3572 // Increment total counter to indicate polymorphic case.
3573 __ addptr(counter_addr, DataLayout::counter_increment);
3574
3575 __ bind(update_done);
3576 }
3577 } else {
3578 // Static call
3579 __ addptr(counter_addr, DataLayout::counter_increment);
3580 }
3581 }
3582
3583 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3584 Register obj = op->obj()->as_register();
3585 Register tmp = op->tmp()->as_pointer_register();
3586 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3587 ciKlass* exact_klass = op->exact_klass();
3588 intptr_t current_klass = op->current_klass();
3589 bool not_null = op->not_null();
3590 bool no_conflict = op->no_conflict();
3591
3592 Label update, next, none;
3593
3594 bool do_null = !not_null;
3595 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3596 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3597
3598 assert(do_null || do_update, "why are we here?");
3599 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3600
3601 __ verify_oop(obj);
3602
3603 if (tmp != obj) {
3604 __ mov(tmp, obj);
3605 }
3606 if (do_null) {
3607 __ testptr(tmp, tmp);
3608 __ jccb(Assembler::notZero, update);
3609 if (!TypeEntries::was_null_seen(current_klass)) {
3610 __ orptr(mdo_addr, TypeEntries::null_seen);
3611 }
3612 if (do_update) {
3613 #ifndef ASSERT
3614 __ jmpb(next);
3615 }
3616 #else
3617 __ jmp(next);
3618 }
3619 } else {
3620 __ testptr(tmp, tmp);
3621 __ jccb(Assembler::notZero, update);
3622 __ stop("unexpect null obj");
3623 #endif
3624 }
3625
3626 __ bind(update);
3627
3628 if (do_update) {
3629 #ifdef ASSERT
3630 if (exact_klass != NULL) {
3631 Label ok;
3632 __ load_klass(tmp, tmp);
3633 __ push(tmp);
3634 __ mov_metadata(tmp, exact_klass->constant_encoding());
3635 __ cmpptr(tmp, Address(rsp, 0));
3636 __ jccb(Assembler::equal, ok);
3637 __ stop("exact klass and actual klass differ");
3638 __ bind(ok);
3639 __ pop(tmp);
3640 }
3641 #endif
3642 if (!no_conflict) {
3643 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3644 if (exact_klass != NULL) {
3645 __ mov_metadata(tmp, exact_klass->constant_encoding());
3646 } else {
3647 __ load_klass(tmp, tmp);
3648 }
3649
3650 __ xorptr(tmp, mdo_addr);
3651 __ testptr(tmp, TypeEntries::type_klass_mask);
3652 // klass seen before, nothing to do. The unknown bit may have been
3653 // set already but no need to check.
3654 __ jccb(Assembler::zero, next);
3655
3656 __ testptr(tmp, TypeEntries::type_unknown);
3657 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3658
3659 if (TypeEntries::is_type_none(current_klass)) {
3660 __ cmpptr(mdo_addr, 0);
3661 __ jccb(Assembler::equal, none);
3662 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3663 __ jccb(Assembler::equal, none);
3664 // There is a chance that the checks above (re-reading profiling
3665 // data from memory) fail if another thread has just set the
3666 // profiling to this obj's klass
3667 __ xorptr(tmp, mdo_addr);
3668 __ testptr(tmp, TypeEntries::type_klass_mask);
3669 __ jccb(Assembler::zero, next);
3670 }
3671 } else {
3672 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3673 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3674
3675 __ movptr(tmp, mdo_addr);
3676 __ testptr(tmp, TypeEntries::type_unknown);
3677 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3678 }
3679
3680 // different than before. Cannot keep accurate profile.
3681 __ orptr(mdo_addr, TypeEntries::type_unknown);
3682
3683 if (TypeEntries::is_type_none(current_klass)) {
3684 __ jmpb(next);
3685
3686 __ bind(none);
3687 // first time here. Set profile type.
3688 __ movptr(mdo_addr, tmp);
3689 }
3690 } else {
3691 // There's a single possible klass at this profile point
3692 assert(exact_klass != NULL, "should be");
3693 if (TypeEntries::is_type_none(current_klass)) {
3694 __ mov_metadata(tmp, exact_klass->constant_encoding());
3695 __ xorptr(tmp, mdo_addr);
3696 __ testptr(tmp, TypeEntries::type_klass_mask);
3697 #ifdef ASSERT
3698 __ jcc(Assembler::zero, next);
3699
3700 {
3701 Label ok;
3702 __ push(tmp);
3703 __ cmpptr(mdo_addr, 0);
3704 __ jcc(Assembler::equal, ok);
3705 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3706 __ jcc(Assembler::equal, ok);
3707 // may have been set by another thread
3708 __ mov_metadata(tmp, exact_klass->constant_encoding());
3709 __ xorptr(tmp, mdo_addr);
3710 __ testptr(tmp, TypeEntries::type_mask);
3711 __ jcc(Assembler::zero, ok);
3712
3713 __ stop("unexpected profiling mismatch");
3714 __ bind(ok);
3715 __ pop(tmp);
3716 }
3717 #else
3718 __ jccb(Assembler::zero, next);
3719 #endif
3720 // first time here. Set profile type.
3721 __ movptr(mdo_addr, tmp);
3722 } else {
3723 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3724 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3725
3726 __ movptr(tmp, mdo_addr);
3727 __ testptr(tmp, TypeEntries::type_unknown);
3728 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3729
3730 __ orptr(mdo_addr, TypeEntries::type_unknown);
3731 }
3732 }
3733
3734 __ bind(next);
3735 }
3736 }
3737
3738 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3739 Unimplemented();
3740 }
3741
3742
3743 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3744 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3745 }
3746
3747
3748 void LIR_Assembler::align_backward_branch_target() {
3749 __ align(BytesPerWord);
3750 }
3751
3752
3753 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3754 if (left->is_single_cpu()) {
3755 __ negl(left->as_register());
3756 move_regs(left->as_register(), dest->as_register());
3757
3758 } else if (left->is_double_cpu()) {
3759 Register lo = left->as_register_lo();
3760 #ifdef _LP64
3761 Register dst = dest->as_register_lo();
3762 __ movptr(dst, lo);
3763 __ negptr(dst);
3764 #else
3765 Register hi = left->as_register_hi();
3766 __ lneg(hi, lo);
3767 if (dest->as_register_lo() == hi) {
3768 assert(dest->as_register_hi() != lo, "destroying register");
3769 move_regs(hi, dest->as_register_hi());
3770 move_regs(lo, dest->as_register_lo());
3771 } else {
3772 move_regs(lo, dest->as_register_lo());
3773 move_regs(hi, dest->as_register_hi());
3774 }
3775 #endif // _LP64
3776
3777 } else if (dest->is_single_xmm()) {
3778 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3779 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3780 }
3781 if (UseAVX > 0) {
3782 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3783 ExternalAddress((address)float_signflip_pool));
3784 } else {
3785 __ xorps(dest->as_xmm_float_reg(),
3786 ExternalAddress((address)float_signflip_pool));
3787 }
3788 } else if (dest->is_double_xmm()) {
3789 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3790 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3791 }
3792 if (UseAVX > 0) {
3793 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3794 ExternalAddress((address)double_signflip_pool));
3795 } else {
3796 __ xorpd(dest->as_xmm_double_reg(),
3797 ExternalAddress((address)double_signflip_pool));
3798 }
3799 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3800 assert(left->fpu() == 0, "arg must be on TOS");
3801 assert(dest->fpu() == 0, "dest must be TOS");
3802 __ fchs();
3803
3804 } else {
3805 ShouldNotReachHere();
3806 }
3807 }
3808
3809
3810 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3811 assert(src->is_address() && dest->is_register(), "check");
3812
3813 LIR_Address* addr = src->as_address_ptr();
3814
3815 PatchingStub* patch = NULL;
3816 if (patch_code != lir_patch_none) {
3817 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3818 assert(addr->disp() != 0, "must have");
3819 }
3820
3821 Register reg;
3822 reg = dest->as_pointer_register();
3823 __ lea(reg, as_Address(addr));
3824
3825 if (patch != NULL) {
3826 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3827 }
3828 }
3829
3830
3831
3832 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3833 assert(!tmp->is_valid(), "don't need temporary");
3834 __ call(RuntimeAddress(dest));
3835 if (info != NULL) {
3836 add_call_info_here(info);
3837 }
3838 }
3839
3840
3841 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3842 assert(type == T_LONG, "only for volatile long fields");
3843
3844 if (info != NULL) {
3845 add_debug_info_for_null_check_here(info);
3846 }
3847
3848 if (src->is_double_xmm()) {
3849 if (dest->is_double_cpu()) {
3850 #ifdef _LP64
3851 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3852 #else
3853 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3854 __ psrlq(src->as_xmm_double_reg(), 32);
3855 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3856 #endif // _LP64
3857 } else if (dest->is_double_stack()) {
3858 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3859 } else if (dest->is_address()) {
3860 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3861 } else {
3862 ShouldNotReachHere();
3863 }
3864
3865 } else if (dest->is_double_xmm()) {
3866 if (src->is_double_stack()) {
3867 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3868 } else if (src->is_address()) {
3869 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3870 } else {
3871 ShouldNotReachHere();
3872 }
3873
3874 } else if (src->is_double_fpu()) {
3875 assert(src->fpu_regnrLo() == 0, "must be TOS");
3876 if (dest->is_double_stack()) {
3877 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3878 } else if (dest->is_address()) {
3879 __ fistp_d(as_Address(dest->as_address_ptr()));
3880 } else {
3881 ShouldNotReachHere();
3882 }
3883
3884 } else if (dest->is_double_fpu()) {
3885 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3886 if (src->is_double_stack()) {
3887 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3888 } else if (src->is_address()) {
3889 __ fild_d(as_Address(src->as_address_ptr()));
3890 } else {
3891 ShouldNotReachHere();
3892 }
3893 } else {
3894 ShouldNotReachHere();
3895 }
3896 }
3897
3898 #ifdef ASSERT
3899 // emit run-time assertion
3900 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3901 assert(op->code() == lir_assert, "must be");
3902
3903 if (op->in_opr1()->is_valid()) {
3904 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3905 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3906 } else {
3907 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3908 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3909 }
3910
3911 Label ok;
3912 if (op->condition() != lir_cond_always) {
3913 Assembler::Condition acond = Assembler::zero;
3914 switch (op->condition()) {
3915 case lir_cond_equal: acond = Assembler::equal; break;
3916 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3917 case lir_cond_less: acond = Assembler::less; break;
3918 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3919 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3920 case lir_cond_greater: acond = Assembler::greater; break;
3921 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3922 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3923 default: ShouldNotReachHere();
3924 }
3925 __ jcc(acond, ok);
3926 }
3927 if (op->halt()) {
3928 const char* str = __ code_string(op->msg());
3929 __ stop(str);
3930 } else {
3931 breakpoint();
3932 }
3933 __ bind(ok);
3934 }
3935 #endif
3936
3937 void LIR_Assembler::membar() {
3938 // QQQ sparc TSO uses this,
3939 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3940 }
3941
3942 void LIR_Assembler::membar_acquire() {
3943 // No x86 machines currently require load fences
3944 }
3945
3946 void LIR_Assembler::membar_release() {
3947 // No x86 machines currently require store fences
3948 }
3949
3950 void LIR_Assembler::membar_loadload() {
3951 // no-op
3952 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3953 }
3954
3955 void LIR_Assembler::membar_storestore() {
3956 // no-op
3957 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3958 }
3959
3960 void LIR_Assembler::membar_loadstore() {
3961 // no-op
3962 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3963 }
3964
3965 void LIR_Assembler::membar_storeload() {
3966 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3967 }
3968
3969 void LIR_Assembler::on_spin_wait() {
3970 __ pause ();
3971 }
3972
3973 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3974 assert(result_reg->is_register(), "check");
3975 #ifdef _LP64
3976 // __ get_thread(result_reg->as_register_lo());
3977 __ mov(result_reg->as_register(), r15_thread);
3978 #else
3979 __ get_thread(result_reg->as_register());
3980 #endif // _LP64
3981 }
3982
3983
3984 void LIR_Assembler::peephole(LIR_List*) {
3985 // do nothing for now
3986 }
3987
3988 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3989 assert(data == dest, "xchg/xadd uses only 2 operands");
3990
3991 if (data->type() == T_INT) {
3992 if (code == lir_xadd) {
3993 if (os::is_MP()) {
3994 __ lock();
3995 }
3996 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3997 } else {
3998 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3999 }
4000 } else if (data->is_oop()) {
4001 assert (code == lir_xchg, "xadd for oops");
4002 Register obj = data->as_register();
4003 #ifdef _LP64
4004 if (UseCompressedOops) {
4005 __ encode_heap_oop(obj);
4006 __ xchgl(obj, as_Address(src->as_address_ptr()));
4007 __ decode_heap_oop(obj);
4008 } else {
4009 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4010 }
4011 #else
4012 __ xchgl(obj, as_Address(src->as_address_ptr()));
4013 #endif
4014 } else if (data->type() == T_LONG) {
4015 #ifdef _LP64
4016 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4017 if (code == lir_xadd) {
4018 if (os::is_MP()) {
4019 __ lock();
4020 }
4021 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4022 } else {
4023 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4024 }
4025 #else
4026 ShouldNotReachHere();
4027 #endif
4028 } else {
4029 ShouldNotReachHere();
4030 }
4031 }
4032
4033 #undef __