src/cpu/sparc/vm/sparc.ad

*** 9693,9702 ****
--- 9693,9738 ----
    opcode(Assembler::ldxa_op3);
    ins_encode( form3_mem_reg_little(src, dst) );
    ins_pipe( iload_mem );
  %}
  
+ instruct bytes_reverse_char(iRegI dst, stackSlotI src) %{
+   match(Set dst (ReverseBytesC src));
+   effect(DEF dst, USE src);
+ 
+   // Op cost is artificially doubled to make sure that load or store
+   // instructions are preferred over this one which requires a spill
+   // onto a stack slot.
+   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::lduh_op3, -1,
+                            $src$$base, $src$$disp, $src$$index,
+                            $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe( iload_mem );
+ %}
+ 
+ instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
+   match(Set dst (ReverseBytesS src));
+   effect(DEF dst, USE src);
+ 
+   // Op cost is artificially doubled to make sure that load or store
+   // instructions are preferred over this one which requires a spill
+   // onto a stack slot.
+   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::ldsh_op3, -1,
+                            $src$$base, $src$$disp, $src$$index,
+                            $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe( iload_mem );
+ %}
+ 
  // Load Integer reversed byte order
  instruct loadI_reversed(iRegI dst, memory src) %{
    match(Set dst (ReverseBytesI (LoadI src)));
  
    ins_cost(DEFAULT_COST + MEMORY_REF_COST);
*** 9719,9728 ****
--- 9755,9796 ----
    opcode(Assembler::ldxa_op3);
    ins_encode( form3_mem_reg_little( src, dst ) );
    ins_pipe(iload_mem);
  %}
  
+ // Load char reversed byte order
+ instruct loadC_reversed(iRegI dst, memory src) %{
+   match(Set dst (ReverseBytesC (LoadUS src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::lduh_op3, -1,
+                            $src$$base, $src$$disp, $src$$index,
+                            $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe(iload_mem);
+ %}
+ 
+ // Load short reversed byte order
+ instruct loadS_reversed(iRegI dst, memory src) %{
+   match(Set dst (ReverseBytesS (LoadS src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::ldsh_op3, -1,
+                            $src$$base, $src$$disp, $src$$index,
+                            $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe(iload_mem);
+ %}
+ 
  // Store Integer reversed byte order
  instruct storeI_reversed(memory dst, iRegI src) %{
    match(Set dst (StoreI dst (ReverseBytesI src)));
  
    ins_cost(MEMORY_REF_COST);
*** 9745,9754 ****
--- 9813,9854 ----
    opcode(Assembler::stxa_op3);
    ins_encode( form3_mem_reg_little( dst, src) );
    ins_pipe(istore_mem_reg);
  %}
  
+ // Store char reversed byte order
+ instruct storeC_reversed(memory dst, iRegI src) %{
+   match(Set dst (StoreUS dst (ReverseBytesC src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::sth_op3, -1,
+                            $dst$$base, $dst$$disp, $dst$$index,
+                            $src$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe(istore_mem_reg);
+ %}
+ 
+ // Store short reversed byte order
+ instruct storeS_reversed(memory dst, iRegI src) %{
+   match(Set dst (StoreS dst (ReverseBytesS src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     emit_form3_mem_reg_asi(cbuf, this, Assembler::sth_op3, -1,
+                            $dst$$base, $dst$$disp, $dst$$index,
+                            $src$$reg, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+   ins_pipe(istore_mem_reg);
+ %}
+ 
  //----------PEEPHOLE RULES-----------------------------------------------------
  // These must follow all instruction definitions as they use the names
  // defined in the instructions definitions.
  //
  // peepmatch ( root_instr_name [preceding_instruction]* );