9678 ins_encode( form3_mem_reg_little(src, dst) );
9679 ins_pipe( iload_mem );
9680 %}
9681
9682 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9683 match(Set dst (ReverseBytesL src));
9684 effect(DEF dst, USE src);
9685
9686 // Op cost is artificially doubled to make sure that load or store
9687 // instructions are preferred over this one which requires a spill
9688 // onto a stack slot.
9689 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9690 size(8);
9691 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9692
9693 opcode(Assembler::ldxa_op3);
9694 ins_encode( form3_mem_reg_little(src, dst) );
9695 ins_pipe( iload_mem );
9696 %}
9697
9698 // Load Integer reversed byte order
9699 instruct loadI_reversed(iRegI dst, memory src) %{
9700 match(Set dst (ReverseBytesI (LoadI src)));
9701
9702 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9703 size(8);
9704 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9705
9706 opcode(Assembler::lduwa_op3);
9707 ins_encode( form3_mem_reg_little( src, dst) );
9708 ins_pipe(iload_mem);
9709 %}
9710
9711 // Load Long - aligned and reversed
9712 instruct loadL_reversed(iRegL dst, memory src) %{
9713 match(Set dst (ReverseBytesL (LoadL src)));
9714
9715 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9716 size(8);
9717 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9718
9719 opcode(Assembler::ldxa_op3);
9720 ins_encode( form3_mem_reg_little( src, dst ) );
9721 ins_pipe(iload_mem);
9722 %}
9723
9724 // Store Integer reversed byte order
9725 instruct storeI_reversed(memory dst, iRegI src) %{
9726 match(Set dst (StoreI dst (ReverseBytesI src)));
9727
9728 ins_cost(MEMORY_REF_COST);
9729 size(8);
9730 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9731
9732 opcode(Assembler::stwa_op3);
9733 ins_encode( form3_mem_reg_little( dst, src) );
9734 ins_pipe(istore_mem_reg);
9735 %}
9736
9737 // Store Long reversed byte order
9738 instruct storeL_reversed(memory dst, iRegL src) %{
9739 match(Set dst (StoreL dst (ReverseBytesL src)));
9740
9741 ins_cost(MEMORY_REF_COST);
9742 size(8);
9743 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9744
9745 opcode(Assembler::stxa_op3);
9746 ins_encode( form3_mem_reg_little( dst, src) );
9747 ins_pipe(istore_mem_reg);
9748 %}
9749
9750 //----------PEEPHOLE RULES-----------------------------------------------------
9751 // These must follow all instruction definitions as they use the names
9752 // defined in the instructions definitions.
9753 //
9754 // peepmatch ( root_instr_name [preceding_instruction]* );
9755 //
9756 // peepconstraint %{
9757 // (instruction_number.operand_name relational_op instruction_number.operand_name
9758 // [, ...] );
9759 // // instruction numbers are zero-based using left to right order in peepmatch
9760 //
9761 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9762 // // provide an instruction_number.operand_name for each operand that appears
9763 // // in the replacement instruction's match rule
9764 //
9765 // ---------VM FLAGS---------------------------------------------------------
9766 //
9767 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9768 //
9769 // Each peephole rule is given an identifying number starting with zero and
|
9678 ins_encode( form3_mem_reg_little(src, dst) );
9679 ins_pipe( iload_mem );
9680 %}
9681
9682 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9683 match(Set dst (ReverseBytesL src));
9684 effect(DEF dst, USE src);
9685
9686 // Op cost is artificially doubled to make sure that load or store
9687 // instructions are preferred over this one which requires a spill
9688 // onto a stack slot.
9689 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9690 size(8);
9691 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9692
9693 opcode(Assembler::ldxa_op3);
9694 ins_encode( form3_mem_reg_little(src, dst) );
9695 ins_pipe( iload_mem );
9696 %}
9697
9698 instruct bytes_reverse_char(iRegI dst, stackSlotI src) %{
9699 match(Set dst (ReverseBytesC src));
9700 effect(DEF dst, USE src);
9701
9702 // Op cost is artificially doubled to make sure that load or store
9703 // instructions are preferred over this one which requires a spill
9704 // onto a stack slot.
9705 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9706 size(8);
9707 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9708 ins_encode %{
9709 emit_form3_mem_reg_asi(cbuf, this, Assembler::lduh_op3, -1,
9710 $src$$base, $src$$disp, $src$$index,
9711 $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
9712 %}
9713 ins_pipe( iload_mem );
9714 %}
9715
9716 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9717 match(Set dst (ReverseBytesS src));
9718 effect(DEF dst, USE src);
9719
9720 // Op cost is artificially doubled to make sure that load or store
9721 // instructions are preferred over this one which requires a spill
9722 // onto a stack slot.
9723 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9724 size(8);
9725 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9726 ins_encode %{
9727 emit_form3_mem_reg_asi(cbuf, this, Assembler::ldsh_op3, -1,
9728 $src$$base, $src$$disp, $src$$index,
9729 $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
9730 %}
9731 ins_pipe( iload_mem );
9732 %}
9733
9734 // Load Integer reversed byte order
9735 instruct loadI_reversed(iRegI dst, memory src) %{
9736 match(Set dst (ReverseBytesI (LoadI src)));
9737
9738 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9739 size(8);
9740 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9741
9742 opcode(Assembler::lduwa_op3);
9743 ins_encode( form3_mem_reg_little( src, dst) );
9744 ins_pipe(iload_mem);
9745 %}
9746
9747 // Load Long - aligned and reversed
9748 instruct loadL_reversed(iRegL dst, memory src) %{
9749 match(Set dst (ReverseBytesL (LoadL src)));
9750
9751 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9752 size(8);
9753 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9754
9755 opcode(Assembler::ldxa_op3);
9756 ins_encode( form3_mem_reg_little( src, dst ) );
9757 ins_pipe(iload_mem);
9758 %}
9759
9760 // Load char reversed byte order
9761 instruct loadC_reversed(iRegI dst, memory src) %{
9762 match(Set dst (ReverseBytesC (LoadUS src)));
9763
9764 ins_cost(MEMORY_REF_COST);
9765 size(8);
9766 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9767
9768 ins_encode %{
9769 emit_form3_mem_reg_asi(cbuf, this, Assembler::lduh_op3, -1,
9770 $src$$base, $src$$disp, $src$$index,
9771 $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
9772 %}
9773 ins_pipe(iload_mem);
9774 %}
9775
9776 // Load short reversed byte order
9777 instruct loadS_reversed(iRegI dst, memory src) %{
9778 match(Set dst (ReverseBytesS (LoadS src)));
9779
9780 ins_cost(MEMORY_REF_COST);
9781 size(8);
9782 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9783
9784 ins_encode %{
9785 emit_form3_mem_reg_asi(cbuf, this, Assembler::ldsh_op3, -1,
9786 $src$$base, $src$$disp, $src$$index,
9787 $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
9788 %}
9789 ins_pipe(iload_mem);
9790 %}
9791
9792 // Store Integer reversed byte order
9793 instruct storeI_reversed(memory dst, iRegI src) %{
9794 match(Set dst (StoreI dst (ReverseBytesI src)));
9795
9796 ins_cost(MEMORY_REF_COST);
9797 size(8);
9798 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9799
9800 opcode(Assembler::stwa_op3);
9801 ins_encode( form3_mem_reg_little( dst, src) );
9802 ins_pipe(istore_mem_reg);
9803 %}
9804
9805 // Store Long reversed byte order
9806 instruct storeL_reversed(memory dst, iRegL src) %{
9807 match(Set dst (StoreL dst (ReverseBytesL src)));
9808
9809 ins_cost(MEMORY_REF_COST);
9810 size(8);
9811 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9812
9813 opcode(Assembler::stxa_op3);
9814 ins_encode( form3_mem_reg_little( dst, src) );
9815 ins_pipe(istore_mem_reg);
9816 %}
9817
9818 // Store char reversed byte order
9819 instruct storeC_reversed(memory dst, iRegI src) %{
9820 match(Set dst (StoreUS dst (ReverseBytesC src)));
9821
9822 ins_cost(MEMORY_REF_COST);
9823 size(8);
9824 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9825
9826 ins_encode %{
9827 emit_form3_mem_reg_asi(cbuf, this, Assembler::sth_op3, -1,
9828 $dst$$base, $dst$$disp, $dst$$index,
9829 $src$$reg, Assembler::ASI_PRIMARY_LITTLE);
9830 %}
9831 ins_pipe(istore_mem_reg);
9832 %}
9833
9834 // Store short reversed byte order
9835 instruct storeS_reversed(memory dst, iRegI src) %{
9836 match(Set dst (StoreS dst (ReverseBytesS src)));
9837
9838 ins_cost(MEMORY_REF_COST);
9839 size(8);
9840 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9841
9842 ins_encode %{
9843 emit_form3_mem_reg_asi(cbuf, this, Assembler::sth_op3, -1,
9844 $dst$$base, $dst$$disp, $dst$$index,
9845 $src$$reg, Assembler::ASI_PRIMARY_LITTLE);
9846 %}
9847 ins_pipe(istore_mem_reg);
9848 %}
9849
9850 //----------PEEPHOLE RULES-----------------------------------------------------
9851 // These must follow all instruction definitions as they use the names
9852 // defined in the instructions definitions.
9853 //
9854 // peepmatch ( root_instr_name [preceding_instruction]* );
9855 //
9856 // peepconstraint %{
9857 // (instruction_number.operand_name relational_op instruction_number.operand_name
9858 // [, ...] );
9859 // // instruction numbers are zero-based using left to right order in peepmatch
9860 //
9861 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9862 // // provide an instruction_number.operand_name for each operand that appears
9863 // // in the replacement instruction's match rule
9864 //
9865 // ---------VM FLAGS---------------------------------------------------------
9866 //
9867 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9868 //
9869 // Each peephole rule is given an identifying number starting with zero and
|