src/cpu/sparc/vm/sparc.ad

*** 9693,9702 ****
--- 9693,9758 ----
    opcode(Assembler::ldxa_op3);
    ins_encode( form3_mem_reg_little(src, dst) );
    ins_pipe( iload_mem );
  %}
  
+ instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
+   match(Set dst (ReverseBytesUS src));
+   effect(DEF dst, USE src);
+ 
+   // Op cost is artificially doubled to make sure that load or store
+   // instructions are preferred over this one which requires a spill
+   // onto a stack slot.
+   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
+ 
+   ins_encode %{
+     int disp = $src$$disp;
+     Register index = $src$$index;
+     Register base = $src$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ lduha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
+   %}
+ 
+   ins_pipe( iload_mem );
+ %}
+ 
+ instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
+   match(Set dst (ReverseBytesS src));
+   effect(DEF dst, USE src);
+ 
+   // Op cost is artificially doubled to make sure that load or store
+   // instructions are preferred over this one which requires a spill
+   // onto a stack slot.
+   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
+ 
+   ins_encode %{
+     int disp = $src$$disp;
+     Register index = $src$$index;
+     Register base = $src$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ ldsha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
+   %}
+ 
+   ins_pipe( iload_mem );
+ %}
+ 
  // Load Integer reversed byte order
  instruct loadI_reversed(iRegI dst, memory src) %{
    match(Set dst (ReverseBytesI (LoadI src)));
  
    ins_cost(DEFAULT_COST + MEMORY_REF_COST);
*** 9719,9728 ****
--- 9775,9834 ----
    opcode(Assembler::ldxa_op3);
    ins_encode( form3_mem_reg_little( src, dst ) );
    ins_pipe(iload_mem);
  %}
  
+ // Load unsigned short / char reversed byte order
+ instruct loadUS_reversed(iRegI dst, memory src) %{
+   match(Set dst (ReverseBytesUS (LoadUS src)));
+ 
+   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     int disp = $src$$disp;
+     Register index = $src$$index;
+     Register base = $src$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ lduha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
+   %}
+ 
+   ins_pipe(iload_mem);
+ %}
+ 
+ // Load short reversed byte order
+ instruct loadS_reversed(iRegI dst, memory src) %{
+   match(Set dst (ReverseBytesS (LoadS src)));
+ 
+   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
+   size(8);
+   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     int disp = $src$$disp;
+     Register index = $src$$index;
+     Register base = $src$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ ldsha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
+   %}
+ 
+   ins_pipe(iload_mem);
+ %}
+ 
  // Store Integer reversed byte order
  instruct storeI_reversed(memory dst, iRegI src) %{
    match(Set dst (StoreI dst (ReverseBytesI src)));
  
    ins_cost(MEMORY_REF_COST);
*** 9745,9754 ****
--- 9851,9910 ----
    opcode(Assembler::stxa_op3);
    ins_encode( form3_mem_reg_little( dst, src) );
    ins_pipe(istore_mem_reg);
  %}
  
+ // Store unsighed short/char reversed byte order
+ instruct storeUS_reversed(memory dst, iRegI src) %{
+   match(Set dst (StoreUS dst (ReverseBytesUS src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     int disp = $dst$$disp;
+     Register index = $dst$index;
+     Register base = $dst$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ stha($src$$reg, base, index, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+ 
+   ins_pipe(istore_mem_reg);
+ %}
+ 
+ // Store short reversed byte order
+ instruct storeS_reversed(memory dst, iRegI src) %{
+   match(Set dst (StoreS dst (ReverseBytesS src)));
+ 
+   ins_cost(MEMORY_REF_COST);
+   size(8);
+   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
+ 
+   ins_encode %{
+     int disp = $dst$$disp;
+     Register index = $dst$index;
+     Register base = $dst$$base;
+     if (base == SP || base == FP) {
+       disp += STACK_BIAS;
+     }
+     if (disp != 0) {
+       index = O7;
+       __ set(disp, index);
+     }
+     __ stha($src$$reg, base, index, Assembler::ASI_PRIMARY_LITTLE);
+   %}
+ 
+   ins_pipe(istore_mem_reg);
+ %}
+ 
  //----------PEEPHOLE RULES-----------------------------------------------------
  // These must follow all instruction definitions as they use the names
  // defined in the instructions definitions.
  //
  // peepmatch ( root_instr_name [preceding_instruction]* );