1 //
2 // Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 // ****************************************************************************
528
529 // REQUIRED FUNCTIONALITY
530
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
535
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 return NativeCall::instruction_size; // call; delay slot
538 }
539
540 int MachCallDynamicJavaNode::ret_addr_offset() {
541 int vtable_index = this->_vtable_index;
542 if (vtable_index < 0) {
543 // must be invalid_vtable_index, not nonvirtual_vtable_index
544 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
545 return (NativeMovConstReg::instruction_size +
546 NativeCall::instruction_size); // sethi; setlo; call; delay slot
547 } else {
548 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
549 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
550 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
551 int klass_load_size;
552 if (UseCompressedOops) {
553 assert(Universe::heap() != NULL, "java heap should be initialized");
554 if (Universe::narrow_oop_base() == NULL)
555 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
556 else
557 klass_load_size = 3*BytesPerInstWord;
558 } else {
559 klass_load_size = 1*BytesPerInstWord;
560 }
561 if( Assembler::is_simm13(v_off) ) {
562 return klass_load_size +
563 (2*BytesPerInstWord + // ld_ptr, ld_ptr
564 NativeCall::instruction_size); // call; delay slot
565 } else {
566 return klass_load_size +
567 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
568 NativeCall::instruction_size); // call; delay slot
569 }
570 }
571 }
572
573 int MachCallRuntimeNode::ret_addr_offset() {
574 #ifdef _LP64
575 return NativeFarCall::instruction_size; // farcall; delay slot
576 #else
577 return NativeCall::instruction_size; // call; delay slot
578 #endif
579 }
580
581 // Indicate if the safepoint node needs the polling page as an input.
582 // Since Sparc does not have absolute addressing, it does.
583 bool SafePointNode::needs_polling_address_input() {
584 return true;
585 }
586
587 // emit an interrupt that is caught by the debugger (for debugging compiler)
588 void emit_break(CodeBuffer &cbuf) {
589 MacroAssembler _masm(&cbuf);
590 __ breakpoint_trap();
591 }
592
593 #ifndef PRODUCT
594 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
595 st->print("TA");
596 }
597 #endif
598
599 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
600 emit_break(cbuf);
601 }
602
603 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
604 return MachNode::size(ra_);
605 }
606
607 // Traceable jump
608 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
609 MacroAssembler _masm(&cbuf);
610 Register rdest = reg_to_register_object(jump_target);
611 __ JMP(rdest, 0);
612 __ delayed()->nop();
613 }
614
615 // Traceable jump and set exception pc
616 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
617 MacroAssembler _masm(&cbuf);
618 Register rdest = reg_to_register_object(jump_target);
619 __ JMP(rdest, 0);
620 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
621 }
622
623 void emit_nop(CodeBuffer &cbuf) {
624 MacroAssembler _masm(&cbuf);
625 __ nop();
626 }
627
628 void emit_illtrap(CodeBuffer &cbuf) {
629 MacroAssembler _masm(&cbuf);
630 __ illtrap(0);
631 }
632
633
634 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
635 assert(n->rule() != loadUB_rule, "");
636
637 intptr_t offset = 0;
638 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
639 const Node* addr = n->get_base_and_disp(offset, adr_type);
640 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
641 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
642 assert(addr->bottom_type()->isa_oopptr() == atype, "");
643 atype = atype->add_offset(offset);
644 assert(disp32 == offset, "wrong disp32");
645 return atype->_offset;
646 }
647
648
649 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
650 assert(n->rule() != loadUB_rule, "");
651
652 intptr_t offset = 0;
653 Node* addr = n->in(2);
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
656 Node* a = addr->in(2/*AddPNode::Address*/);
657 Node* o = addr->in(3/*AddPNode::Offset*/);
658 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
659 atype = a->bottom_type()->is_ptr()->add_offset(offset);
660 assert(atype->isa_oop_ptr(), "still an oop");
661 }
662 offset = atype->is_ptr()->_offset;
663 if (offset != Type::OffsetBot) offset += disp32;
664 return offset;
665 }
666
667 // Standard Sparc opcode form2 field breakdown
668 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
669 f0 &= (1<<19)-1; // Mask displacement to 19 bits
670 int op = (f30 << 30) |
671 (f29 << 29) |
672 (f25 << 25) |
673 (f22 << 22) |
674 (f20 << 20) |
675 (f19 << 19) |
676 (f0 << 0);
677 *((int*)(cbuf.code_end())) = op;
678 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
679 }
680
681 // Standard Sparc opcode form2 field breakdown
682 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
683 f0 >>= 10; // Drop 10 bits
684 f0 &= (1<<22)-1; // Mask displacement to 22 bits
685 int op = (f30 << 30) |
686 (f25 << 25) |
687 (f22 << 22) |
688 (f0 << 0);
689 *((int*)(cbuf.code_end())) = op;
690 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
691 }
692
693 // Standard Sparc opcode form3 field breakdown
694 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
695 int op = (f30 << 30) |
696 (f25 << 25) |
697 (f19 << 19) |
698 (f14 << 14) |
699 (f5 << 5) |
700 (f0 << 0);
701 *((int*)(cbuf.code_end())) = op;
702 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
703 }
704
705 // Standard Sparc opcode form3 field breakdown
706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
707 simm13 &= (1<<13)-1; // Mask to 13 bits
708 int op = (f30 << 30) |
709 (f25 << 25) |
710 (f19 << 19) |
711 (f14 << 14) |
712 (1 << 13) | // bit to indicate immediate-mode
713 (simm13<<0);
714 *((int*)(cbuf.code_end())) = op;
715 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
716 }
717
718 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
719 simm10 &= (1<<10)-1; // Mask to 10 bits
720 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
721 }
722
723 #ifdef ASSERT
724 // Helper function for VerifyOops in emit_form3_mem_reg
725 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
726 warning("VerifyOops encountered unexpected instruction:");
727 n->dump(2);
728 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
729 }
730 #endif
731
732
733 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
734 int src1_enc, int disp32, int src2_enc, int dst_enc) {
735
736 #ifdef ASSERT
737 // The following code implements the +VerifyOops feature.
738 // It verifies oop values which are loaded into or stored out of
739 // the current method activation. +VerifyOops complements techniques
740 // like ScavengeALot, because it eagerly inspects oops in transit,
741 // as they enter or leave the stack, as opposed to ScavengeALot,
742 // which inspects oops "at rest", in the stack or heap, at safepoints.
743 // For this reason, +VerifyOops can sometimes detect bugs very close
744 // to their point of creation. It can also serve as a cross-check
745 // on the validity of oop maps, when used toegether with ScavengeALot.
746
747 // It would be good to verify oops at other points, especially
748 // when an oop is used as a base pointer for a load or store.
749 // This is presently difficult, because it is hard to know when
750 // a base address is biased or not. (If we had such information,
751 // it would be easy and useful to make a two-argument version of
752 // verify_oop which unbiases the base, and performs verification.)
753
754 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
755 bool is_verified_oop_base = false;
756 bool is_verified_oop_load = false;
757 bool is_verified_oop_store = false;
758 int tmp_enc = -1;
759 if (VerifyOops && src1_enc != R_SP_enc) {
760 // classify the op, mainly for an assert check
761 int st_op = 0, ld_op = 0;
762 switch (primary) {
763 case Assembler::stb_op3: st_op = Op_StoreB; break;
764 case Assembler::sth_op3: st_op = Op_StoreC; break;
765 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
766 case Assembler::stw_op3: st_op = Op_StoreI; break;
767 case Assembler::std_op3: st_op = Op_StoreL; break;
768 case Assembler::stf_op3: st_op = Op_StoreF; break;
769 case Assembler::stdf_op3: st_op = Op_StoreD; break;
770
771 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
772 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
773 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
774 case Assembler::ldx_op3: // may become LoadP or stay LoadI
775 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
776 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
777 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
778 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
779 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
780 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
781 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
782
783 default: ShouldNotReachHere();
784 }
785 if (tertiary == REGP_OP) {
786 if (st_op == Op_StoreI) st_op = Op_StoreP;
787 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
788 else ShouldNotReachHere();
789 if (st_op) {
790 // a store
791 // inputs are (0:control, 1:memory, 2:address, 3:value)
792 Node* n2 = n->in(3);
793 if (n2 != NULL) {
794 const Type* t = n2->bottom_type();
795 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
796 }
797 } else {
798 // a load
799 const Type* t = n->bottom_type();
800 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
801 }
802 }
803
804 if (ld_op) {
805 // a Load
806 // inputs are (0:control, 1:memory, 2:address)
807 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
808 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
810 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
811 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
814 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
815 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
816 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
817 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
818 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
819 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
820 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
821 !(n->rule() == loadUB_rule)) {
822 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
823 }
824 } else if (st_op) {
825 // a Store
826 // inputs are (0:control, 1:memory, 2:address, 3:value)
827 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
828 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
829 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
830 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
831 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
832 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
833 verify_oops_warning(n, n->ideal_Opcode(), st_op);
834 }
835 }
836
837 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
838 Node* addr = n->in(2);
839 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
840 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
841 if (atype != NULL) {
842 intptr_t offset = get_offset_from_base(n, atype, disp32);
843 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
844 if (offset != offset_2) {
845 get_offset_from_base(n, atype, disp32);
846 get_offset_from_base_2(n, atype, disp32);
847 }
848 assert(offset == offset_2, "different offsets");
849 if (offset == disp32) {
850 // we now know that src1 is a true oop pointer
851 is_verified_oop_base = true;
852 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
853 if( primary == Assembler::ldd_op3 ) {
854 is_verified_oop_base = false; // Cannot 'ldd' into O7
855 } else {
856 tmp_enc = dst_enc;
857 dst_enc = R_O7_enc; // Load into O7; preserve source oop
858 assert(src1_enc != dst_enc, "");
859 }
860 }
861 }
862 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
863 || offset == oopDesc::mark_offset_in_bytes())) {
864 // loading the mark should not be allowed either, but
865 // we don't check this since it conflicts with InlineObjectHash
866 // usage of LoadINode to get the mark. We could keep the
867 // check if we create a new LoadMarkNode
868 // but do not verify the object before its header is initialized
869 ShouldNotReachHere();
870 }
871 }
872 }
873 }
874 }
875 #endif
876
877 uint instr;
878 instr = (Assembler::ldst_op << 30)
879 | (dst_enc << 25)
880 | (primary << 19)
881 | (src1_enc << 14);
882
883 uint index = src2_enc;
884 int disp = disp32;
885
886 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
887 disp += STACK_BIAS;
888
889 // We should have a compiler bailout here rather than a guarantee.
890 // Better yet would be some mechanism to handle variable-size matches correctly.
891 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
892
893 if( disp == 0 ) {
894 // use reg-reg form
895 // bit 13 is already zero
896 instr |= index;
897 } else {
898 // use reg-imm form
899 instr |= 0x00002000; // set bit 13 to one
900 instr |= disp & 0x1FFF;
901 }
902
903 uint *code = (uint*)cbuf.code_end();
904 *code = instr;
905 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
906
907 #ifdef ASSERT
908 {
909 MacroAssembler _masm(&cbuf);
910 if (is_verified_oop_base) {
911 __ verify_oop(reg_to_register_object(src1_enc));
912 }
913 if (is_verified_oop_store) {
914 __ verify_oop(reg_to_register_object(dst_enc));
915 }
916 if (tmp_enc != -1) {
917 __ mov(O7, reg_to_register_object(tmp_enc));
918 }
919 if (is_verified_oop_load) {
920 __ verify_oop(reg_to_register_object(dst_enc));
921 }
922 }
923 #endif
924 }
925
926 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
927 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
928
929 uint instr;
930 instr = (Assembler::ldst_op << 30)
931 | (dst_enc << 25)
932 | (primary << 19)
933 | (src1_enc << 14);
934
935 int disp = disp32;
936 int index = src2_enc;
937
938 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
939 disp += STACK_BIAS;
940
941 // We should have a compiler bailout here rather than a guarantee.
942 // Better yet would be some mechanism to handle variable-size matches correctly.
943 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
944
945 if( disp != 0 ) {
946 // use reg-reg form
947 // set src2=R_O7 contains offset
948 index = R_O7_enc;
949 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
950 }
951 instr |= (asi << 5);
952 instr |= index;
953 uint *code = (uint*)cbuf.code_end();
954 *code = instr;
955 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
956 }
957
958 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
959 // The method which records debug information at every safepoint
960 // expects the call to be the first instruction in the snippet as
961 // it creates a PcDesc structure which tracks the offset of a call
962 // from the start of the codeBlob. This offset is computed as
963 // code_end() - code_begin() of the code which has been emitted
964 // so far.
965 // In this particular case we have skirted around the problem by
966 // putting the "mov" instruction in the delay slot but the problem
967 // may bite us again at some other point and a cleaner/generic
968 // solution using relocations would be needed.
969 MacroAssembler _masm(&cbuf);
970 __ set_inst_mark();
971
972 // We flush the current window just so that there is a valid stack copy
973 // the fact that the current window becomes active again instantly is
974 // not a problem there is nothing live in it.
975
976 #ifdef ASSERT
977 int startpos = __ offset();
978 #endif /* ASSERT */
979
980 #ifdef _LP64
981 // Calls to the runtime or native may not be reachable from compiled code,
982 // so we generate the far call sequence on 64 bit sparc.
983 // This code sequence is relocatable to any address, even on LP64.
984 if ( force_far_call ) {
985 __ relocate(rtype);
986 AddressLiteral dest(entry_point);
987 __ jumpl_to(dest, O7, O7);
988 }
989 else
990 #endif
991 {
992 __ call((address)entry_point, rtype);
993 }
994
995 if (preserve_g2) __ delayed()->mov(G2, L7);
996 else __ delayed()->nop();
997
998 if (preserve_g2) __ mov(L7, G2);
999
1000 #ifdef ASSERT
1001 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1002 #ifdef _LP64
1003 // Trash argument dump slots.
1004 __ set(0xb0b8ac0db0b8ac0d, G1);
1005 __ mov(G1, G5);
1006 __ stx(G1, SP, STACK_BIAS + 0x80);
1007 __ stx(G1, SP, STACK_BIAS + 0x88);
1008 __ stx(G1, SP, STACK_BIAS + 0x90);
1009 __ stx(G1, SP, STACK_BIAS + 0x98);
1010 __ stx(G1, SP, STACK_BIAS + 0xA0);
1011 __ stx(G1, SP, STACK_BIAS + 0xA8);
1012 #else // _LP64
1013 // this is also a native call, so smash the first 7 stack locations,
1014 // and the various registers
1015
1016 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1017 // while [SP+0x44..0x58] are the argument dump slots.
1018 __ set((intptr_t)0xbaadf00d, G1);
1019 __ mov(G1, G5);
1020 __ sllx(G1, 32, G1);
1021 __ or3(G1, G5, G1);
1022 __ mov(G1, G5);
1023 __ stx(G1, SP, 0x40);
1024 __ stx(G1, SP, 0x48);
1025 __ stx(G1, SP, 0x50);
1026 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1027 #endif // _LP64
1028 }
1029 #endif /*ASSERT*/
1030 }
1031
1032 //=============================================================================
1033 // REQUIRED FUNCTIONALITY for encoding
1034 void emit_lo(CodeBuffer &cbuf, int val) { }
1035 void emit_hi(CodeBuffer &cbuf, int val) { }
1036
1037
1038 //=============================================================================
1039
1040 #ifndef PRODUCT
1041 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1042 Compile* C = ra_->C;
1043
1044 for (int i = 0; i < OptoPrologueNops; i++) {
1045 st->print_cr("NOP"); st->print("\t");
1046 }
1047
1048 if( VerifyThread ) {
1049 st->print_cr("Verify_Thread"); st->print("\t");
1050 }
1051
1052 size_t framesize = C->frame_slots() << LogBytesPerInt;
1053
1054 // Calls to C2R adapters often do not accept exceptional returns.
1055 // We require that their callers must bang for them. But be careful, because
1056 // some VM calls (such as call site linkage) can use several kilobytes of
1057 // stack. But the stack safety zone should account for that.
1058 // See bugs 4446381, 4468289, 4497237.
1059 if (C->need_stack_bang(framesize)) {
1060 st->print_cr("! stack bang"); st->print("\t");
1061 }
1062
1063 if (Assembler::is_simm13(-framesize)) {
1064 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1065 } else {
1066 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1067 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1068 st->print ("SAVE R_SP,R_G3,R_SP");
1069 }
1070
1071 }
1072 #endif
1073
1074 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1075 Compile* C = ra_->C;
1076 MacroAssembler _masm(&cbuf);
1077
1078 for (int i = 0; i < OptoPrologueNops; i++) {
1079 __ nop();
1080 }
1081
1082 __ verify_thread();
1083
1084 size_t framesize = C->frame_slots() << LogBytesPerInt;
1085 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1086 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1087
1088 // Calls to C2R adapters often do not accept exceptional returns.
1089 // We require that their callers must bang for them. But be careful, because
1090 // some VM calls (such as call site linkage) can use several kilobytes of
1091 // stack. But the stack safety zone should account for that.
1092 // See bugs 4446381, 4468289, 4497237.
1093 if (C->need_stack_bang(framesize)) {
1094 __ generate_stack_overflow_check(framesize);
1095 }
1096
1097 if (Assembler::is_simm13(-framesize)) {
1098 __ save(SP, -framesize, SP);
1099 } else {
1100 __ sethi(-framesize & ~0x3ff, G3);
1101 __ add(G3, -framesize & 0x3ff, G3);
1102 __ save(SP, G3, SP);
1103 }
1104 C->set_frame_complete( __ offset() );
1105 }
1106
1107 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1108 return MachNode::size(ra_);
1109 }
1110
1111 int MachPrologNode::reloc() const {
1112 return 10; // a large enough number
1113 }
1114
1115 //=============================================================================
1116 #ifndef PRODUCT
1117 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1118 Compile* C = ra_->C;
1119
1120 if( do_polling() && ra_->C->is_method_compilation() ) {
1121 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1122 #ifdef _LP64
1123 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1124 #else
1125 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1126 #endif
1127 }
1128
1129 if( do_polling() )
1130 st->print("RET\n\t");
1131
1132 st->print("RESTORE");
1133 }
1134 #endif
1135
1136 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1137 MacroAssembler _masm(&cbuf);
1138 Compile* C = ra_->C;
1139
1140 __ verify_thread();
1141
1142 // If this does safepoint polling, then do it here
1143 if( do_polling() && ra_->C->is_method_compilation() ) {
1144 AddressLiteral polling_page(os::get_polling_page());
1145 __ sethi(polling_page, L0);
1146 __ relocate(relocInfo::poll_return_type);
1147 __ ld_ptr( L0, 0, G0 );
1148 }
1149
1150 // If this is a return, then stuff the restore in the delay slot
1151 if( do_polling() ) {
1152 __ ret();
1153 __ delayed()->restore();
1154 } else {
1155 __ restore();
1156 }
1157 }
1158
1159 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1160 return MachNode::size(ra_);
1161 }
1162
1163 int MachEpilogNode::reloc() const {
1164 return 16; // a large enough number
1165 }
1166
1167 const Pipeline * MachEpilogNode::pipeline() const {
1168 return MachNode::pipeline_class();
1169 }
1170
1171 int MachEpilogNode::safepoint_offset() const {
1172 assert( do_polling(), "no return for this epilog node");
1173 return MacroAssembler::size_of_sethi(os::get_polling_page());
1174 }
1175
1176 //=============================================================================
1177
1178 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1179 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1180 static enum RC rc_class( OptoReg::Name reg ) {
1181 if( !OptoReg::is_valid(reg) ) return rc_bad;
1182 if (OptoReg::is_stack(reg)) return rc_stack;
1183 VMReg r = OptoReg::as_VMReg(reg);
1184 if (r->is_Register()) return rc_int;
1185 assert(r->is_FloatRegister(), "must be");
1186 return rc_float;
1187 }
1188
1189 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1190 if( cbuf ) {
1191 // Better yet would be some mechanism to handle variable-size matches correctly
1192 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1193 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1194 } else {
1195 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1196 }
1197 }
1198 #ifndef PRODUCT
1199 else if( !do_size ) {
1200 if( size != 0 ) st->print("\n\t");
1201 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1202 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1203 }
1204 #endif
1205 return size+4;
1206 }
1207
1208 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1209 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1210 #ifndef PRODUCT
1211 else if( !do_size ) {
1212 if( size != 0 ) st->print("\n\t");
1213 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1214 }
1215 #endif
1216 return size+4;
1217 }
1218
1219 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1220 PhaseRegAlloc *ra_,
1221 bool do_size,
1222 outputStream* st ) const {
1223 // Get registers to move
1224 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1225 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1226 OptoReg::Name dst_second = ra_->get_reg_second(this );
1227 OptoReg::Name dst_first = ra_->get_reg_first(this );
1228
1229 enum RC src_second_rc = rc_class(src_second);
1230 enum RC src_first_rc = rc_class(src_first);
1231 enum RC dst_second_rc = rc_class(dst_second);
1232 enum RC dst_first_rc = rc_class(dst_first);
1233
1234 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1235
1236 // Generate spill code!
1237 int size = 0;
1238
1239 if( src_first == dst_first && src_second == dst_second )
1240 return size; // Self copy, no move
1241
1242 // --------------------------------------
1243 // Check for mem-mem move. Load into unused float registers and fall into
1244 // the float-store case.
1245 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1246 int offset = ra_->reg2offset(src_first);
1247 // Further check for aligned-adjacent pair, so we can use a double load
1248 if( (src_first&1)==0 && src_first+1 == src_second ) {
1249 src_second = OptoReg::Name(R_F31_num);
1250 src_second_rc = rc_float;
1251 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1252 } else {
1253 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1254 }
1255 src_first = OptoReg::Name(R_F30_num);
1256 src_first_rc = rc_float;
1257 }
1258
1259 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1260 int offset = ra_->reg2offset(src_second);
1261 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1262 src_second = OptoReg::Name(R_F31_num);
1263 src_second_rc = rc_float;
1264 }
1265
1266 // --------------------------------------
1267 // Check for float->int copy; requires a trip through memory
1268 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1269 int offset = frame::register_save_words*wordSize;
1270 if( cbuf ) {
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1272 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1273 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1274 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1275 }
1276 #ifndef PRODUCT
1277 else if( !do_size ) {
1278 if( size != 0 ) st->print("\n\t");
1279 st->print( "SUB R_SP,16,R_SP\n");
1280 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1281 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1282 st->print("\tADD R_SP,16,R_SP\n");
1283 }
1284 #endif
1285 size += 16;
1286 }
1287
1288 // --------------------------------------
1289 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1290 // In such cases, I have to do the big-endian swap. For aligned targets, the
1291 // hardware does the flop for me. Doubles are always aligned, so no problem
1292 // there. Misaligned sources only come from native-long-returns (handled
1293 // special below).
1294 #ifndef _LP64
1295 if( src_first_rc == rc_int && // source is already big-endian
1296 src_second_rc != rc_bad && // 64-bit move
1297 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1298 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1299 // Do the big-endian flop.
1300 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1301 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1302 }
1303 #endif
1304
1305 // --------------------------------------
1306 // Check for integer reg-reg copy
1307 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1308 #ifndef _LP64
1309 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1310 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1311 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1312 // operand contains the least significant word of the 64-bit value and vice versa.
1313 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1314 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1315 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1316 if( cbuf ) {
1317 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1318 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1319 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1320 #ifndef PRODUCT
1321 } else if( !do_size ) {
1322 if( size != 0 ) st->print("\n\t");
1323 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1324 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1325 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1326 #endif
1327 }
1328 return size+12;
1329 }
1330 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1331 // returning a long value in I0/I1
1332 // a SpillCopy must be able to target a return instruction's reg_class
1333 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1334 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1335 // operand contains the least significant word of the 64-bit value and vice versa.
1336 OptoReg::Name tdest = dst_first;
1337
1338 if (src_first == dst_first) {
1339 tdest = OptoReg::Name(R_O7_num);
1340 size += 4;
1341 }
1342
1343 if( cbuf ) {
1344 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1345 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1346 // ShrL_reg_imm6
1347 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1348 // ShrR_reg_imm6 src, 0, dst
1349 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1350 if (tdest != dst_first) {
1351 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1352 }
1353 }
1354 #ifndef PRODUCT
1355 else if( !do_size ) {
1356 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1357 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1358 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1359 if (tdest != dst_first) {
1360 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1361 }
1362 }
1363 #endif // PRODUCT
1364 return size+8;
1365 }
1366 #endif // !_LP64
1367 // Else normal reg-reg copy
1368 assert( src_second != dst_first, "smashed second before evacuating it" );
1369 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1370 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1371 // This moves an aligned adjacent pair.
1372 // See if we are done.
1373 if( src_first+1 == src_second && dst_first+1 == dst_second )
1374 return size;
1375 }
1376
1377 // Check for integer store
1378 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1379 int offset = ra_->reg2offset(dst_first);
1380 // Further check for aligned-adjacent pair, so we can use a double store
1381 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1382 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1383 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1384 }
1385
1386 // Check for integer load
1387 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1388 int offset = ra_->reg2offset(src_first);
1389 // Further check for aligned-adjacent pair, so we can use a double load
1390 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1391 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1392 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1393 }
1394
1395 // Check for float reg-reg copy
1396 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1397 // Further check for aligned-adjacent pair, so we can use a double move
1398 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1399 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1400 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1401 }
1402
1403 // Check for float store
1404 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1405 int offset = ra_->reg2offset(dst_first);
1406 // Further check for aligned-adjacent pair, so we can use a double store
1407 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1408 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1409 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1410 }
1411
1412 // Check for float load
1413 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1414 int offset = ra_->reg2offset(src_first);
1415 // Further check for aligned-adjacent pair, so we can use a double load
1416 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1417 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1418 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1419 }
1420
1421 // --------------------------------------------------------------------
1422 // Check for hi bits still needing moving. Only happens for misaligned
1423 // arguments to native calls.
1424 if( src_second == dst_second )
1425 return size; // Self copy; no move
1426 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1427
1428 #ifndef _LP64
1429 // In the LP64 build, all registers can be moved as aligned/adjacent
1430 // pairs, so there's never any need to move the high bits separately.
1431 // The 32-bit builds have to deal with the 32-bit ABI which can force
1432 // all sorts of silly alignment problems.
1433
1434 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1435 // 32-bits of a 64-bit register, but are needed in low bits of another
1436 // register (else it's a hi-bits-to-hi-bits copy which should have
1437 // happened already as part of a 64-bit move)
1438 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1439 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1440 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1441 // Shift src_second down to dst_second's low bits.
1442 if( cbuf ) {
1443 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1444 #ifndef PRODUCT
1445 } else if( !do_size ) {
1446 if( size != 0 ) st->print("\n\t");
1447 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1448 #endif
1449 }
1450 return size+4;
1451 }
1452
1453 // Check for high word integer store. Must down-shift the hi bits
1454 // into a temp register, then fall into the case of storing int bits.
1455 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1456 // Shift src_second down to dst_second's low bits.
1457 if( cbuf ) {
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1459 #ifndef PRODUCT
1460 } else if( !do_size ) {
1461 if( size != 0 ) st->print("\n\t");
1462 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1463 #endif
1464 }
1465 size+=4;
1466 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1467 }
1468
1469 // Check for high word integer load
1470 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1471 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1472
1473 // Check for high word integer store
1474 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1475 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1476
1477 // Check for high word float store
1478 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1479 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1480
1481 #endif // !_LP64
1482
1483 Unimplemented();
1484 }
1485
1486 #ifndef PRODUCT
1487 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1488 implementation( NULL, ra_, false, st );
1489 }
1490 #endif
1491
1492 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1493 implementation( &cbuf, ra_, false, NULL );
1494 }
1495
1496 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1497 return implementation( NULL, ra_, true, NULL );
1498 }
1499
1500 //=============================================================================
1501 #ifndef PRODUCT
1502 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1503 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1504 }
1505 #endif
1506
1507 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1508 MacroAssembler _masm(&cbuf);
1509 for(int i = 0; i < _count; i += 1) {
1510 __ nop();
1511 }
1512 }
1513
1514 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1515 return 4 * _count;
1516 }
1517
1518
1519 //=============================================================================
1520 #ifndef PRODUCT
1521 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1522 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1523 int reg = ra_->get_reg_first(this);
1524 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1525 }
1526 #endif
1527
1528 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1529 MacroAssembler _masm(&cbuf);
1530 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1531 int reg = ra_->get_encode(this);
1532
1533 if (Assembler::is_simm13(offset)) {
1534 __ add(SP, offset, reg_to_register_object(reg));
1535 } else {
1536 __ set(offset, O7);
1537 __ add(SP, O7, reg_to_register_object(reg));
1538 }
1539 }
1540
1541 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1542 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1543 assert(ra_ == ra_->C->regalloc(), "sanity");
1544 return ra_->C->scratch_emit_size(this);
1545 }
1546
1547 //=============================================================================
1548
1549 // emit call stub, compiled java to interpretor
1550 void emit_java_to_interp(CodeBuffer &cbuf ) {
1551
1552 // Stub is fixed up when the corresponding call is converted from calling
1553 // compiled code to calling interpreted code.
1554 // set (empty), G5
1555 // jmp -1
1556
1557 address mark = cbuf.inst_mark(); // get mark within main instrs section
1558
1559 MacroAssembler _masm(&cbuf);
1560
1561 address base =
1562 __ start_a_stub(Compile::MAX_stubs_size);
1563 if (base == NULL) return; // CodeBuffer::expand failed
1564
1565 // static stub relocation stores the instruction address of the call
1566 __ relocate(static_stub_Relocation::spec(mark));
1567
1568 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1569
1570 __ set_inst_mark();
1571 AddressLiteral addrlit(-1);
1572 __ JUMP(addrlit, G3, 0);
1573
1574 __ delayed()->nop();
1575
1576 // Update current stubs pointer and restore code_end.
1577 __ end_a_stub();
1578 }
1579
1580 // size of call stub, compiled java to interpretor
1581 uint size_java_to_interp() {
1582 // This doesn't need to be accurate but it must be larger or equal to
1583 // the real size of the stub.
1584 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1585 NativeJump::instruction_size + // sethi; jmp; nop
1586 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1587 }
1588 // relocation entries for call stub, compiled java to interpretor
1589 uint reloc_java_to_interp() {
1590 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1591 }
1592
1593
1594 //=============================================================================
1595 #ifndef PRODUCT
1596 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1597 st->print_cr("\nUEP:");
1598 #ifdef _LP64
1599 if (UseCompressedOops) {
1600 assert(Universe::heap() != NULL, "java heap should be initialized");
1601 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1602 st->print_cr("\tSLL R_G5,3,R_G5");
1603 if (Universe::narrow_oop_base() != NULL)
1604 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1605 } else {
1606 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1607 }
1608 st->print_cr("\tCMP R_G5,R_G3" );
1609 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1610 #else // _LP64
1611 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1612 st->print_cr("\tCMP R_G5,R_G3" );
1613 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1614 #endif // _LP64
1615 }
1616 #endif
1617
1618 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1619 MacroAssembler _masm(&cbuf);
1620 Label L;
1621 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1622 Register temp_reg = G3;
1623 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1624
1625 // Load klass from receiver
1626 __ load_klass(O0, temp_reg);
1627 // Compare against expected klass
1628 __ cmp(temp_reg, G5_ic_reg);
1629 // Branch to miss code, checks xcc or icc depending
1630 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1631 }
1632
1633 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1634 return MachNode::size(ra_);
1635 }
1636
1637
1638 //=============================================================================
1639
1640 uint size_exception_handler() {
1641 if (TraceJumps) {
1642 return (400); // just a guess
1643 }
1644 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1645 }
1646
1647 uint size_deopt_handler() {
1648 if (TraceJumps) {
1649 return (400); // just a guess
1650 }
1651 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1652 }
1653
1654 // Emit exception handler code.
1655 int emit_exception_handler(CodeBuffer& cbuf) {
1656 Register temp_reg = G3;
1657 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1658 MacroAssembler _masm(&cbuf);
1659
1660 address base =
1661 __ start_a_stub(size_exception_handler());
1662 if (base == NULL) return 0; // CodeBuffer::expand failed
1663
1664 int offset = __ offset();
1665
1666 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1667 __ delayed()->nop();
1668
1669 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1670
1671 __ end_a_stub();
1672
1673 return offset;
1674 }
1675
1676 int emit_deopt_handler(CodeBuffer& cbuf) {
1677 // Can't use any of the current frame's registers as we may have deopted
1678 // at a poll and everything (including G3) can be live.
1679 Register temp_reg = L0;
1680 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1681 MacroAssembler _masm(&cbuf);
1682
1683 address base =
1684 __ start_a_stub(size_deopt_handler());
1685 if (base == NULL) return 0; // CodeBuffer::expand failed
1686
1687 int offset = __ offset();
1688 __ save_frame(0);
1689 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1690 __ delayed()->restore();
1691
1692 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1693
1694 __ end_a_stub();
1695 return offset;
1696
1697 }
1698
1699 // Given a register encoding, produce a Integer Register object
1700 static Register reg_to_register_object(int register_encoding) {
1701 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1702 return as_Register(register_encoding);
1703 }
1704
1705 // Given a register encoding, produce a single-precision Float Register object
1706 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1707 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1708 return as_SingleFloatRegister(register_encoding);
1709 }
1710
1711 // Given a register encoding, produce a double-precision Float Register object
1712 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1713 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1714 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1715 return as_DoubleFloatRegister(register_encoding);
1716 }
1717
1718 const bool Matcher::match_rule_supported(int opcode) {
1719 if (!has_match_rule(opcode))
1720 return false;
1721
1722 switch (opcode) {
1723 case Op_CountLeadingZerosI:
1724 case Op_CountLeadingZerosL:
1725 case Op_CountTrailingZerosI:
1726 case Op_CountTrailingZerosL:
1727 if (!UsePopCountInstruction)
1728 return false;
1729 break;
1730 }
1731
1732 return true; // Per default match rules are supported.
1733 }
1734
1735 int Matcher::regnum_to_fpu_offset(int regnum) {
1736 return regnum - 32; // The FP registers are in the second chunk
1737 }
1738
1739 #ifdef ASSERT
1740 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1741 #endif
1742
1743 // Vector width in bytes
1744 const uint Matcher::vector_width_in_bytes(void) {
1745 return 8;
1746 }
1747
1748 // Vector ideal reg
1749 const uint Matcher::vector_ideal_reg(void) {
1750 return Op_RegD;
1751 }
1752
1753 // USII supports fxtof through the whole range of number, USIII doesn't
1754 const bool Matcher::convL2FSupported(void) {
1755 return VM_Version::has_fast_fxtof();
1756 }
1757
1758 // Is this branch offset short enough that a short branch can be used?
1759 //
1760 // NOTE: If the platform does not provide any short branch variants, then
1761 // this method should return false for offset 0.
1762 bool Matcher::is_short_branch_offset(int rule, int offset) {
1763 return false;
1764 }
1765
1766 const bool Matcher::isSimpleConstant64(jlong value) {
1767 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1768 // Depends on optimizations in MacroAssembler::setx.
1769 int hi = (int)(value >> 32);
1770 int lo = (int)(value & ~0);
1771 return (hi == 0) || (hi == -1) || (lo == 0);
1772 }
1773
1774 // No scaling for the parameter the ClearArray node.
1775 const bool Matcher::init_array_count_is_in_bytes = true;
1776
1777 // Threshold size for cleararray.
1778 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1779
1780 // Should the Matcher clone shifts on addressing modes, expecting them to
1781 // be subsumed into complex addressing expressions or compute them into
1782 // registers? True for Intel but false for most RISCs
1783 const bool Matcher::clone_shift_expressions = false;
1784
1785 // Is it better to copy float constants, or load them directly from memory?
1786 // Intel can load a float constant from a direct address, requiring no
1787 // extra registers. Most RISCs will have to materialize an address into a
1788 // register first, so they would do better to copy the constant from stack.
1789 const bool Matcher::rematerialize_float_constants = false;
1790
1791 // If CPU can load and store mis-aligned doubles directly then no fixup is
1792 // needed. Else we split the double into 2 integer pieces and move it
1793 // piece-by-piece. Only happens when passing doubles into C code as the
1794 // Java calling convention forces doubles to be aligned.
1795 #ifdef _LP64
1796 const bool Matcher::misaligned_doubles_ok = true;
1797 #else
1798 const bool Matcher::misaligned_doubles_ok = false;
1799 #endif
1800
1801 // No-op on SPARC.
1802 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1803 }
1804
1805 // Advertise here if the CPU requires explicit rounding operations
1806 // to implement the UseStrictFP mode.
1807 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1808
1809 // Are floats conerted to double when stored to stack during deoptimization?
1810 // Sparc does not handle callee-save floats.
1811 bool Matcher::float_in_double() { return false; }
1812
1813 // Do ints take an entire long register or just half?
1814 // Note that we if-def off of _LP64.
1815 // The relevant question is how the int is callee-saved. In _LP64
1816 // the whole long is written but de-opt'ing will have to extract
1817 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1818 #ifdef _LP64
1819 const bool Matcher::int_in_long = true;
1820 #else
1821 const bool Matcher::int_in_long = false;
1822 #endif
1823
1824 // Return whether or not this register is ever used as an argument. This
1825 // function is used on startup to build the trampoline stubs in generateOptoStub.
1826 // Registers not mentioned will be killed by the VM call in the trampoline, and
1827 // arguments in those registers not be available to the callee.
1828 bool Matcher::can_be_java_arg( int reg ) {
1829 // Standard sparc 6 args in registers
1830 if( reg == R_I0_num ||
1831 reg == R_I1_num ||
1832 reg == R_I2_num ||
1833 reg == R_I3_num ||
1834 reg == R_I4_num ||
1835 reg == R_I5_num ) return true;
1836 #ifdef _LP64
1837 // 64-bit builds can pass 64-bit pointers and longs in
1838 // the high I registers
1839 if( reg == R_I0H_num ||
1840 reg == R_I1H_num ||
1841 reg == R_I2H_num ||
1842 reg == R_I3H_num ||
1843 reg == R_I4H_num ||
1844 reg == R_I5H_num ) return true;
1845
1846 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1847 return true;
1848 }
1849
1850 #else
1851 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1852 // Longs cannot be passed in O regs, because O regs become I regs
1853 // after a 'save' and I regs get their high bits chopped off on
1854 // interrupt.
1855 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1856 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1857 #endif
1858 // A few float args in registers
1859 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1860
1861 return false;
1862 }
1863
1864 bool Matcher::is_spillable_arg( int reg ) {
1865 return can_be_java_arg(reg);
1866 }
1867
1868 // Register for DIVI projection of divmodI
1869 RegMask Matcher::divI_proj_mask() {
1870 ShouldNotReachHere();
1871 return RegMask();
1872 }
1873
1874 // Register for MODI projection of divmodI
1875 RegMask Matcher::modI_proj_mask() {
1876 ShouldNotReachHere();
1877 return RegMask();
1878 }
1879
1880 // Register for DIVL projection of divmodL
1881 RegMask Matcher::divL_proj_mask() {
1882 ShouldNotReachHere();
1883 return RegMask();
1884 }
1885
1886 // Register for MODL projection of divmodL
1887 RegMask Matcher::modL_proj_mask() {
1888 ShouldNotReachHere();
1889 return RegMask();
1890 }
1891
1892 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1893 return RegMask();
1894 }
1895
1896 %}
1897
1898
1899 // The intptr_t operand types, defined by textual substitution.
1900 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1901 #ifdef _LP64
1902 #define immX immL
1903 #define immX13 immL13
1904 #define immX13m7 immL13m7
1905 #define iRegX iRegL
1906 #define g1RegX g1RegL
1907 #else
1908 #define immX immI
1909 #define immX13 immI13
1910 #define immX13m7 immI13m7
1911 #define iRegX iRegI
1912 #define g1RegX g1RegI
1913 #endif
1914
1915 //----------ENCODING BLOCK-----------------------------------------------------
1916 // This block specifies the encoding classes used by the compiler to output
1917 // byte streams. Encoding classes are parameterized macros used by
1918 // Machine Instruction Nodes in order to generate the bit encoding of the
1919 // instruction. Operands specify their base encoding interface with the
1920 // interface keyword. There are currently supported four interfaces,
1921 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1922 // operand to generate a function which returns its register number when
1923 // queried. CONST_INTER causes an operand to generate a function which
1924 // returns the value of the constant when queried. MEMORY_INTER causes an
1925 // operand to generate four functions which return the Base Register, the
1926 // Index Register, the Scale Value, and the Offset Value of the operand when
1927 // queried. COND_INTER causes an operand to generate six functions which
1928 // return the encoding code (ie - encoding bits for the instruction)
1929 // associated with each basic boolean condition for a conditional instruction.
1930 //
1931 // Instructions specify two basic values for encoding. Again, a function
1932 // is available to check if the constant displacement is an oop. They use the
1933 // ins_encode keyword to specify their encoding classes (which must be
1934 // a sequence of enc_class names, and their parameters, specified in
1935 // the encoding block), and they use the
1936 // opcode keyword to specify, in order, their primary, secondary, and
1937 // tertiary opcode. Only the opcode sections which a particular instruction
1938 // needs for encoding need to be specified.
1939 encode %{
1940 enc_class enc_untested %{
1941 #ifdef ASSERT
1942 MacroAssembler _masm(&cbuf);
1943 __ untested("encoding");
1944 #endif
1945 %}
1946
1947 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1948 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1949 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1950 %}
1951
1952 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1953 emit_form3_mem_reg(cbuf, this, $primary, -1,
1954 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1955 %}
1956
1957 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1958 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1959 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1960 %}
1961
1962 enc_class form3_mem_prefetch_read( memory mem ) %{
1963 emit_form3_mem_reg(cbuf, this, $primary, -1,
1964 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1965 %}
1966
1967 enc_class form3_mem_prefetch_write( memory mem ) %{
1968 emit_form3_mem_reg(cbuf, this, $primary, -1,
1969 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1970 %}
1971
1972 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1973 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1974 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1975 guarantee($mem$$index == R_G0_enc, "double index?");
1976 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1977 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1978 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1979 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1980 %}
1981
1982 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1983 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1984 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1985 guarantee($mem$$index == R_G0_enc, "double index?");
1986 // Load long with 2 instructions
1987 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1988 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1989 %}
1990
1991 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1992 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1993 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1994 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1995 %}
1996
1997 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1998 // Encode a reg-reg copy. If it is useless, then empty encoding.
1999 if( $rs2$$reg != $rd$$reg )
2000 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2001 %}
2002
2003 // Target lo half of long
2004 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2005 // Encode a reg-reg copy. If it is useless, then empty encoding.
2006 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2007 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2008 %}
2009
2010 // Source lo half of long
2011 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2012 // Encode a reg-reg copy. If it is useless, then empty encoding.
2013 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2014 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2015 %}
2016
2017 // Target hi half of long
2018 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2019 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2020 %}
2021
2022 // Source lo half of long, and leave it sign extended.
2023 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2024 // Sign extend low half
2025 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2026 %}
2027
2028 // Source hi half of long, and leave it sign extended.
2029 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2030 // Shift high half to low half
2031 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2032 %}
2033
2034 // Source hi half of long
2035 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2036 // Encode a reg-reg copy. If it is useless, then empty encoding.
2037 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2038 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2039 %}
2040
2041 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2043 %}
2044
2045 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2046 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2047 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2048 %}
2049
2050 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2051 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2052 // clear if nothing else is happening
2053 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2054 // blt,a,pn done
2055 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2056 // mov dst,-1 in delay slot
2057 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2058 %}
2059
2060 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2061 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2062 %}
2063
2064 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2065 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2066 %}
2067
2068 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2069 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2070 %}
2071
2072 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2073 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2074 %}
2075
2076 enc_class move_return_pc_to_o1() %{
2077 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2078 %}
2079
2080 #ifdef _LP64
2081 /* %%% merge with enc_to_bool */
2082 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2083 MacroAssembler _masm(&cbuf);
2084
2085 Register src_reg = reg_to_register_object($src$$reg);
2086 Register dst_reg = reg_to_register_object($dst$$reg);
2087 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2088 %}
2089 #endif
2090
2091 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2092 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2093 MacroAssembler _masm(&cbuf);
2094
2095 Register p_reg = reg_to_register_object($p$$reg);
2096 Register q_reg = reg_to_register_object($q$$reg);
2097 Register y_reg = reg_to_register_object($y$$reg);
2098 Register tmp_reg = reg_to_register_object($tmp$$reg);
2099
2100 __ subcc( p_reg, q_reg, p_reg );
2101 __ add ( p_reg, y_reg, tmp_reg );
2102 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2103 %}
2104
2105 enc_class form_d2i_helper(regD src, regF dst) %{
2106 // fcmp %fcc0,$src,$src
2107 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2108 // branch %fcc0 not-nan, predict taken
2109 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2110 // fdtoi $src,$dst
2111 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2112 // fitos $dst,$dst (if nan)
2113 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2114 // clear $dst (if nan)
2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2116 // carry on here...
2117 %}
2118
2119 enc_class form_d2l_helper(regD src, regD dst) %{
2120 // fcmp %fcc0,$src,$src check for NAN
2121 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2122 // branch %fcc0 not-nan, predict taken
2123 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2124 // fdtox $src,$dst convert in delay slot
2125 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2126 // fxtod $dst,$dst (if nan)
2127 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2128 // clear $dst (if nan)
2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2130 // carry on here...
2131 %}
2132
2133 enc_class form_f2i_helper(regF src, regF dst) %{
2134 // fcmps %fcc0,$src,$src
2135 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2136 // branch %fcc0 not-nan, predict taken
2137 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2138 // fstoi $src,$dst
2139 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2140 // fitos $dst,$dst (if nan)
2141 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2142 // clear $dst (if nan)
2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2144 // carry on here...
2145 %}
2146
2147 enc_class form_f2l_helper(regF src, regD dst) %{
2148 // fcmps %fcc0,$src,$src
2149 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2150 // branch %fcc0 not-nan, predict taken
2151 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2152 // fstox $src,$dst
2153 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2154 // fxtod $dst,$dst (if nan)
2155 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2156 // clear $dst (if nan)
2157 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2158 // carry on here...
2159 %}
2160
2161 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2162 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2163 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2164 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2165
2166 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2167
2168 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2169 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2170
2171 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2172 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2173 %}
2174
2175 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2176 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2177 %}
2178
2179 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2180 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2181 %}
2182
2183 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2184 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2185 %}
2186
2187 enc_class form3_convI2F(regF rs2, regF rd) %{
2188 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2189 %}
2190
2191 // Encloding class for traceable jumps
2192 enc_class form_jmpl(g3RegP dest) %{
2193 emit_jmpl(cbuf, $dest$$reg);
2194 %}
2195
2196 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2197 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2198 %}
2199
2200 enc_class form2_nop() %{
2201 emit_nop(cbuf);
2202 %}
2203
2204 enc_class form2_illtrap() %{
2205 emit_illtrap(cbuf);
2206 %}
2207
2208
2209 // Compare longs and convert into -1, 0, 1.
2210 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2211 // CMP $src1,$src2
2212 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2213 // blt,a,pn done
2214 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2215 // mov dst,-1 in delay slot
2216 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2217 // bgt,a,pn done
2218 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2219 // mov dst,1 in delay slot
2220 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2221 // CLR $dst
2222 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2223 %}
2224
2225 enc_class enc_PartialSubtypeCheck() %{
2226 MacroAssembler _masm(&cbuf);
2227 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2228 __ delayed()->nop();
2229 %}
2230
2231 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2232 MacroAssembler _masm(&cbuf);
2233 Label &L = *($labl$$label);
2234 Assembler::Predict predict_taken =
2235 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2236
2237 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2238 __ delayed()->nop();
2239 %}
2240
2241 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2242 MacroAssembler _masm(&cbuf);
2243 Label &L = *($labl$$label);
2244 Assembler::Predict predict_taken =
2245 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2246
2247 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2248 __ delayed()->nop();
2249 %}
2250
2251 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2252 MacroAssembler _masm(&cbuf);
2253 Label &L = *($labl$$label);
2254 Assembler::Predict predict_taken =
2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2256
2257 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2258 __ delayed()->nop();
2259 %}
2260
2261 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2262 MacroAssembler _masm(&cbuf);
2263 Label &L = *($labl$$label);
2264 Assembler::Predict predict_taken =
2265 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2266
2267 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2268 __ delayed()->nop();
2269 %}
2270
2271 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2272 MacroAssembler _masm(&cbuf);
2273
2274 Register switch_reg = as_Register($switch_val$$reg);
2275 Register table_reg = O7;
2276
2277 address table_base = __ address_table_constant(_index2label);
2278 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2279
2280 // Move table address into a register.
2281 __ set(table_base, table_reg, rspec);
2282
2283 // Jump to base address + switch value
2284 __ ld_ptr(table_reg, switch_reg, table_reg);
2285 __ jmp(table_reg, G0);
2286 __ delayed()->nop();
2287
2288 %}
2289
2290 enc_class enc_ba( Label labl ) %{
2291 MacroAssembler _masm(&cbuf);
2292 Label &L = *($labl$$label);
2293 __ ba(false, L);
2294 __ delayed()->nop();
2295 %}
2296
2297 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2298 MacroAssembler _masm(&cbuf);
2299 Label &L = *$labl$$label;
2300 Assembler::Predict predict_taken =
2301 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2302
2303 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2304 __ delayed()->nop();
2305 %}
2306
2307 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2308 int op = (Assembler::arith_op << 30) |
2309 ($dst$$reg << 25) |
2310 (Assembler::movcc_op3 << 19) |
2311 (1 << 18) | // cc2 bit for 'icc'
2312 ($cmp$$cmpcode << 14) |
2313 (0 << 13) | // select register move
2314 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2315 ($src$$reg << 0);
2316 *((int*)(cbuf.code_end())) = op;
2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2318 %}
2319
2320 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2322 int op = (Assembler::arith_op << 30) |
2323 ($dst$$reg << 25) |
2324 (Assembler::movcc_op3 << 19) |
2325 (1 << 18) | // cc2 bit for 'icc'
2326 ($cmp$$cmpcode << 14) |
2327 (1 << 13) | // select immediate move
2328 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2329 (simm11 << 0);
2330 *((int*)(cbuf.code_end())) = op;
2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2332 %}
2333
2334 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2335 int op = (Assembler::arith_op << 30) |
2336 ($dst$$reg << 25) |
2337 (Assembler::movcc_op3 << 19) |
2338 (0 << 18) | // cc2 bit for 'fccX'
2339 ($cmp$$cmpcode << 14) |
2340 (0 << 13) | // select register move
2341 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2342 ($src$$reg << 0);
2343 *((int*)(cbuf.code_end())) = op;
2344 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2345 %}
2346
2347 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2348 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2349 int op = (Assembler::arith_op << 30) |
2350 ($dst$$reg << 25) |
2351 (Assembler::movcc_op3 << 19) |
2352 (0 << 18) | // cc2 bit for 'fccX'
2353 ($cmp$$cmpcode << 14) |
2354 (1 << 13) | // select immediate move
2355 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2356 (simm11 << 0);
2357 *((int*)(cbuf.code_end())) = op;
2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2359 %}
2360
2361 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2362 int op = (Assembler::arith_op << 30) |
2363 ($dst$$reg << 25) |
2364 (Assembler::fpop2_op3 << 19) |
2365 (0 << 18) |
2366 ($cmp$$cmpcode << 14) |
2367 (1 << 13) | // select register move
2368 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2369 ($primary << 5) | // select single, double or quad
2370 ($src$$reg << 0);
2371 *((int*)(cbuf.code_end())) = op;
2372 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2373 %}
2374
2375 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2376 int op = (Assembler::arith_op << 30) |
2377 ($dst$$reg << 25) |
2378 (Assembler::fpop2_op3 << 19) |
2379 (0 << 18) |
2380 ($cmp$$cmpcode << 14) |
2381 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2382 ($primary << 5) | // select single, double or quad
2383 ($src$$reg << 0);
2384 *((int*)(cbuf.code_end())) = op;
2385 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2386 %}
2387
2388 // Used by the MIN/MAX encodings. Same as a CMOV, but
2389 // the condition comes from opcode-field instead of an argument.
2390 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2391 int op = (Assembler::arith_op << 30) |
2392 ($dst$$reg << 25) |
2393 (Assembler::movcc_op3 << 19) |
2394 (1 << 18) | // cc2 bit for 'icc'
2395 ($primary << 14) |
2396 (0 << 13) | // select register move
2397 (0 << 11) | // cc1, cc0 bits for 'icc'
2398 ($src$$reg << 0);
2399 *((int*)(cbuf.code_end())) = op;
2400 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2401 %}
2402
2403 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2404 int op = (Assembler::arith_op << 30) |
2405 ($dst$$reg << 25) |
2406 (Assembler::movcc_op3 << 19) |
2407 (6 << 16) | // cc2 bit for 'xcc'
2408 ($primary << 14) |
2409 (0 << 13) | // select register move
2410 (0 << 11) | // cc1, cc0 bits for 'icc'
2411 ($src$$reg << 0);
2412 *((int*)(cbuf.code_end())) = op;
2413 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2414 %}
2415
2416 // Utility encoding for loading a 64 bit Pointer into a register
2417 // The 64 bit pointer is stored in the generated code stream
2418 enc_class SetPtr( immP src, iRegP rd ) %{
2419 Register dest = reg_to_register_object($rd$$reg);
2420 MacroAssembler _masm(&cbuf);
2421 // [RGV] This next line should be generated from ADLC
2422 if ( _opnds[1]->constant_is_oop() ) {
2423 intptr_t val = $src$$constant;
2424 __ set_oop_constant((jobject)val, dest);
2425 } else { // non-oop pointers, e.g. card mark base, heap top
2426 __ set($src$$constant, dest);
2427 }
2428 %}
2429
2430 enc_class Set13( immI13 src, iRegI rd ) %{
2431 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2432 %}
2433
2434 enc_class SetHi22( immI src, iRegI rd ) %{
2435 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2436 %}
2437
2438 enc_class Set32( immI src, iRegI rd ) %{
2439 MacroAssembler _masm(&cbuf);
2440 __ set($src$$constant, reg_to_register_object($rd$$reg));
2441 %}
2442
2443 enc_class SetNull( iRegI rd ) %{
2444 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2445 %}
2446
2447 enc_class call_epilog %{
2448 if( VerifyStackAtCalls ) {
2449 MacroAssembler _masm(&cbuf);
2450 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2451 Register temp_reg = G3;
2452 __ add(SP, framesize, temp_reg);
2453 __ cmp(temp_reg, FP);
2454 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2455 }
2456 %}
2457
2458 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2459 // to G1 so the register allocator will not have to deal with the misaligned register
2460 // pair.
2461 enc_class adjust_long_from_native_call %{
2462 #ifndef _LP64
2463 if (returns_long()) {
2464 // sllx O0,32,O0
2465 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2466 // srl O1,0,O1
2467 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2468 // or O0,O1,G1
2469 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2470 }
2471 #endif
2472 %}
2473
2474 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2475 // CALL directly to the runtime
2476 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2478 /*preserve_g2=*/true, /*force far call*/true);
2479 %}
2480
2481 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2482 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2483 // who we intended to call.
2484 if ( !_method ) {
2485 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2486 } else if (_optimized_virtual) {
2487 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2488 } else {
2489 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2490 }
2491 if( _method ) { // Emit stub for static call
2492 emit_java_to_interp(cbuf);
2493 }
2494 %}
2495
2496 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2497 MacroAssembler _masm(&cbuf);
2498 __ set_inst_mark();
2499 int vtable_index = this->_vtable_index;
2500 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2501 if (vtable_index < 0) {
2502 // must be invalid_vtable_index, not nonvirtual_vtable_index
2503 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2504 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2505 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2506 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2507 // !!!!!
2508 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2509 // emit_call_dynamic_prologue( cbuf );
2510 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2511
2512 address virtual_call_oop_addr = __ inst_mark();
2513 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2514 // who we intended to call.
2515 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2516 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2517 } else {
2518 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2519 // Just go thru the vtable
2520 // get receiver klass (receiver already checked for non-null)
2521 // If we end up going thru a c2i adapter interpreter expects method in G5
2522 int off = __ offset();
2523 __ load_klass(O0, G3_scratch);
2524 int klass_load_size;
2525 if (UseCompressedOops) {
2526 assert(Universe::heap() != NULL, "java heap should be initialized");
2527 if (Universe::narrow_oop_base() == NULL)
2528 klass_load_size = 2*BytesPerInstWord;
2529 else
2530 klass_load_size = 3*BytesPerInstWord;
2531 } else {
2532 klass_load_size = 1*BytesPerInstWord;
2533 }
2534 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2535 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2536 if( __ is_simm13(v_off) ) {
2537 __ ld_ptr(G3, v_off, G5_method);
2538 } else {
2539 // Generate 2 instructions
2540 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2541 __ or3(G5_method, v_off & 0x3ff, G5_method);
2542 // ld_ptr, set_hi, set
2543 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2544 "Unexpected instruction size(s)");
2545 __ ld_ptr(G3, G5_method, G5_method);
2546 }
2547 // NOTE: for vtable dispatches, the vtable entry will never be null.
2548 // However it may very well end up in handle_wrong_method if the
2549 // method is abstract for the particular class.
2550 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2551 // jump to target (either compiled code or c2iadapter)
2552 __ jmpl(G3_scratch, G0, O7);
2553 __ delayed()->nop();
2554 }
2555 %}
2556
2557 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2558 MacroAssembler _masm(&cbuf);
2559
2560 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2561 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2562 // we might be calling a C2I adapter which needs it.
2563
2564 assert(temp_reg != G5_ic_reg, "conflicting registers");
2565 // Load nmethod
2566 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2567
2568 // CALL to compiled java, indirect the contents of G3
2569 __ set_inst_mark();
2570 __ callr(temp_reg, G0);
2571 __ delayed()->nop();
2572 %}
2573
2574 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2575 MacroAssembler _masm(&cbuf);
2576 Register Rdividend = reg_to_register_object($src1$$reg);
2577 Register Rdivisor = reg_to_register_object($src2$$reg);
2578 Register Rresult = reg_to_register_object($dst$$reg);
2579
2580 __ sra(Rdivisor, 0, Rdivisor);
2581 __ sra(Rdividend, 0, Rdividend);
2582 __ sdivx(Rdividend, Rdivisor, Rresult);
2583 %}
2584
2585 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2586 MacroAssembler _masm(&cbuf);
2587
2588 Register Rdividend = reg_to_register_object($src1$$reg);
2589 int divisor = $imm$$constant;
2590 Register Rresult = reg_to_register_object($dst$$reg);
2591
2592 __ sra(Rdividend, 0, Rdividend);
2593 __ sdivx(Rdividend, divisor, Rresult);
2594 %}
2595
2596 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2597 MacroAssembler _masm(&cbuf);
2598 Register Rsrc1 = reg_to_register_object($src1$$reg);
2599 Register Rsrc2 = reg_to_register_object($src2$$reg);
2600 Register Rdst = reg_to_register_object($dst$$reg);
2601
2602 __ sra( Rsrc1, 0, Rsrc1 );
2603 __ sra( Rsrc2, 0, Rsrc2 );
2604 __ mulx( Rsrc1, Rsrc2, Rdst );
2605 __ srlx( Rdst, 32, Rdst );
2606 %}
2607
2608 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2609 MacroAssembler _masm(&cbuf);
2610 Register Rdividend = reg_to_register_object($src1$$reg);
2611 Register Rdivisor = reg_to_register_object($src2$$reg);
2612 Register Rresult = reg_to_register_object($dst$$reg);
2613 Register Rscratch = reg_to_register_object($scratch$$reg);
2614
2615 assert(Rdividend != Rscratch, "");
2616 assert(Rdivisor != Rscratch, "");
2617
2618 __ sra(Rdividend, 0, Rdividend);
2619 __ sra(Rdivisor, 0, Rdivisor);
2620 __ sdivx(Rdividend, Rdivisor, Rscratch);
2621 __ mulx(Rscratch, Rdivisor, Rscratch);
2622 __ sub(Rdividend, Rscratch, Rresult);
2623 %}
2624
2625 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2626 MacroAssembler _masm(&cbuf);
2627
2628 Register Rdividend = reg_to_register_object($src1$$reg);
2629 int divisor = $imm$$constant;
2630 Register Rresult = reg_to_register_object($dst$$reg);
2631 Register Rscratch = reg_to_register_object($scratch$$reg);
2632
2633 assert(Rdividend != Rscratch, "");
2634
2635 __ sra(Rdividend, 0, Rdividend);
2636 __ sdivx(Rdividend, divisor, Rscratch);
2637 __ mulx(Rscratch, divisor, Rscratch);
2638 __ sub(Rdividend, Rscratch, Rresult);
2639 %}
2640
2641 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2642 MacroAssembler _masm(&cbuf);
2643
2644 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2645 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2646
2647 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2648 %}
2649
2650 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2651 MacroAssembler _masm(&cbuf);
2652
2653 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2654 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2655
2656 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2657 %}
2658
2659 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2660 MacroAssembler _masm(&cbuf);
2661
2662 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2663 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2664
2665 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2666 %}
2667
2668 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2669 MacroAssembler _masm(&cbuf);
2670
2671 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2672 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2673
2674 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2675 %}
2676
2677 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2678 MacroAssembler _masm(&cbuf);
2679
2680 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2681 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2682
2683 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2684 %}
2685
2686 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2687 MacroAssembler _masm(&cbuf);
2688
2689 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2690 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2691
2692 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2693 %}
2694
2695 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2696 MacroAssembler _masm(&cbuf);
2697
2698 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2699 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2700
2701 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2702 %}
2703
2704 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2705 MacroAssembler _masm(&cbuf);
2706
2707 Register Roop = reg_to_register_object($oop$$reg);
2708 Register Rbox = reg_to_register_object($box$$reg);
2709 Register Rscratch = reg_to_register_object($scratch$$reg);
2710 Register Rmark = reg_to_register_object($scratch2$$reg);
2711
2712 assert(Roop != Rscratch, "");
2713 assert(Roop != Rmark, "");
2714 assert(Rbox != Rscratch, "");
2715 assert(Rbox != Rmark, "");
2716
2717 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2718 %}
2719
2720 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2721 MacroAssembler _masm(&cbuf);
2722
2723 Register Roop = reg_to_register_object($oop$$reg);
2724 Register Rbox = reg_to_register_object($box$$reg);
2725 Register Rscratch = reg_to_register_object($scratch$$reg);
2726 Register Rmark = reg_to_register_object($scratch2$$reg);
2727
2728 assert(Roop != Rscratch, "");
2729 assert(Roop != Rmark, "");
2730 assert(Rbox != Rscratch, "");
2731 assert(Rbox != Rmark, "");
2732
2733 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2734 %}
2735
2736 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2737 MacroAssembler _masm(&cbuf);
2738 Register Rmem = reg_to_register_object($mem$$reg);
2739 Register Rold = reg_to_register_object($old$$reg);
2740 Register Rnew = reg_to_register_object($new$$reg);
2741
2742 // casx_under_lock picks 1 of 3 encodings:
2743 // For 32-bit pointers you get a 32-bit CAS
2744 // For 64-bit pointers you get a 64-bit CASX
2745 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2746 __ cmp( Rold, Rnew );
2747 %}
2748
2749 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2750 Register Rmem = reg_to_register_object($mem$$reg);
2751 Register Rold = reg_to_register_object($old$$reg);
2752 Register Rnew = reg_to_register_object($new$$reg);
2753
2754 MacroAssembler _masm(&cbuf);
2755 __ mov(Rnew, O7);
2756 __ casx(Rmem, Rold, O7);
2757 __ cmp( Rold, O7 );
2758 %}
2759
2760 // raw int cas, used for compareAndSwap
2761 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2762 Register Rmem = reg_to_register_object($mem$$reg);
2763 Register Rold = reg_to_register_object($old$$reg);
2764 Register Rnew = reg_to_register_object($new$$reg);
2765
2766 MacroAssembler _masm(&cbuf);
2767 __ mov(Rnew, O7);
2768 __ cas(Rmem, Rold, O7);
2769 __ cmp( Rold, O7 );
2770 %}
2771
2772 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2773 Register Rres = reg_to_register_object($res$$reg);
2774
2775 MacroAssembler _masm(&cbuf);
2776 __ mov(1, Rres);
2777 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2778 %}
2779
2780 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2781 Register Rres = reg_to_register_object($res$$reg);
2782
2783 MacroAssembler _masm(&cbuf);
2784 __ mov(1, Rres);
2785 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2786 %}
2787
2788 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2789 MacroAssembler _masm(&cbuf);
2790 Register Rdst = reg_to_register_object($dst$$reg);
2791 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2792 : reg_to_DoubleFloatRegister_object($src1$$reg);
2793 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2794 : reg_to_DoubleFloatRegister_object($src2$$reg);
2795
2796 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2797 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2798 %}
2799
2800 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2801 MacroAssembler _masm(&cbuf);
2802 Register dest = reg_to_register_object($dst$$reg);
2803 Register temp = reg_to_register_object($tmp$$reg);
2804 __ set64( $src$$constant, dest, temp );
2805 %}
2806
2807 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2808 // Load a constant replicated "count" times with width "width"
2809 int bit_width = $width$$constant * 8;
2810 jlong elt_val = $src$$constant;
2811 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2812 jlong val = elt_val;
2813 for (int i = 0; i < $count$$constant - 1; i++) {
2814 val <<= bit_width;
2815 val |= elt_val;
2816 }
2817 jdouble dval = *(jdouble*)&val; // coerce to double type
2818 MacroAssembler _masm(&cbuf);
2819 address double_address = __ double_constant(dval);
2820 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2821 AddressLiteral addrlit(double_address, rspec);
2822
2823 __ sethi(addrlit, $tmp$$Register);
2824 // XXX This is a quick fix for 6833573.
2825 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2826 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
2827 %}
2828
2829 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2830 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2831 MacroAssembler _masm(&cbuf);
2832 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2833 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2834 Register base_pointer_arg = reg_to_register_object($base$$reg);
2835
2836 Label loop;
2837 __ mov(nof_bytes_arg, nof_bytes_tmp);
2838
2839 // Loop and clear, walking backwards through the array.
2840 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2841 __ bind(loop);
2842 __ deccc(nof_bytes_tmp, 8);
2843 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2844 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2845 // %%%% this mini-loop must not cross a cache boundary!
2846 %}
2847
2848
2849 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2850 Label Ldone, Lloop;
2851 MacroAssembler _masm(&cbuf);
2852
2853 Register str1_reg = reg_to_register_object($str1$$reg);
2854 Register str2_reg = reg_to_register_object($str2$$reg);
2855 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2856 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2857 Register result_reg = reg_to_register_object($result$$reg);
2858
2859 assert(result_reg != str1_reg &&
2860 result_reg != str2_reg &&
2861 result_reg != cnt1_reg &&
2862 result_reg != cnt2_reg ,
2863 "need different registers");
2864
2865 // Compute the minimum of the string lengths(str1_reg) and the
2866 // difference of the string lengths (stack)
2867
2868 // See if the lengths are different, and calculate min in str1_reg.
2869 // Stash diff in O7 in case we need it for a tie-breaker.
2870 Label Lskip;
2871 __ subcc(cnt1_reg, cnt2_reg, O7);
2872 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2873 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2874 // cnt2 is shorter, so use its count:
2875 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2876 __ bind(Lskip);
2877
2878 // reallocate cnt1_reg, cnt2_reg, result_reg
2879 // Note: limit_reg holds the string length pre-scaled by 2
2880 Register limit_reg = cnt1_reg;
2881 Register chr2_reg = cnt2_reg;
2882 Register chr1_reg = result_reg;
2883 // str{12} are the base pointers
2884
2885 // Is the minimum length zero?
2886 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2887 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2888 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2889
2890 // Load first characters
2891 __ lduh(str1_reg, 0, chr1_reg);
2892 __ lduh(str2_reg, 0, chr2_reg);
2893
2894 // Compare first characters
2895 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2896 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2897 assert(chr1_reg == result_reg, "result must be pre-placed");
2898 __ delayed()->nop();
2899
2900 {
2901 // Check after comparing first character to see if strings are equivalent
2902 Label LSkip2;
2903 // Check if the strings start at same location
2904 __ cmp(str1_reg, str2_reg);
2905 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2906 __ delayed()->nop();
2907
2908 // Check if the length difference is zero (in O7)
2909 __ cmp(G0, O7);
2910 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2911 __ delayed()->mov(G0, result_reg); // result is zero
2912
2913 // Strings might not be equal
2914 __ bind(LSkip2);
2915 }
2916
2917 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2918 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2919 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2920
2921 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2922 __ add(str1_reg, limit_reg, str1_reg);
2923 __ add(str2_reg, limit_reg, str2_reg);
2924 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2925
2926 // Compare the rest of the characters
2927 __ lduh(str1_reg, limit_reg, chr1_reg);
2928 __ bind(Lloop);
2929 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2930 __ lduh(str2_reg, limit_reg, chr2_reg);
2931 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2932 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2933 assert(chr1_reg == result_reg, "result must be pre-placed");
2934 __ delayed()->inccc(limit_reg, sizeof(jchar));
2935 // annul LDUH if branch is not taken to prevent access past end of string
2936 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2937 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2938
2939 // If strings are equal up to min length, return the length difference.
2940 __ mov(O7, result_reg);
2941
2942 // Otherwise, return the difference between the first mismatched chars.
2943 __ bind(Ldone);
2944 %}
2945
2946 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2947 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2948 MacroAssembler _masm(&cbuf);
2949
2950 Register str1_reg = reg_to_register_object($str1$$reg);
2951 Register str2_reg = reg_to_register_object($str2$$reg);
2952 Register cnt_reg = reg_to_register_object($cnt$$reg);
2953 Register tmp1_reg = O7;
2954 Register result_reg = reg_to_register_object($result$$reg);
2955
2956 assert(result_reg != str1_reg &&
2957 result_reg != str2_reg &&
2958 result_reg != cnt_reg &&
2959 result_reg != tmp1_reg ,
2960 "need different registers");
2961
2962 __ cmp(str1_reg, str2_reg); //same char[] ?
2963 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2964 __ delayed()->add(G0, 1, result_reg);
2965
2966 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2967 __ delayed()->add(G0, 1, result_reg); // count == 0
2968
2969 //rename registers
2970 Register limit_reg = cnt_reg;
2971 Register chr1_reg = result_reg;
2972 Register chr2_reg = tmp1_reg;
2973
2974 //check for alignment and position the pointers to the ends
2975 __ or3(str1_reg, str2_reg, chr1_reg);
2976 __ andcc(chr1_reg, 0x3, chr1_reg);
2977 // notZero means at least one not 4-byte aligned.
2978 // We could optimize the case when both arrays are not aligned
2979 // but it is not frequent case and it requires additional checks.
2980 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2981 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2982
2983 // Compare char[] arrays aligned to 4 bytes.
2984 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2985 chr1_reg, chr2_reg, Ldone);
2986 __ ba(false,Ldone);
2987 __ delayed()->add(G0, 1, result_reg);
2988
2989 // char by char compare
2990 __ bind(Lchar);
2991 __ add(str1_reg, limit_reg, str1_reg);
2992 __ add(str2_reg, limit_reg, str2_reg);
2993 __ neg(limit_reg); //negate count
2994
2995 __ lduh(str1_reg, limit_reg, chr1_reg);
2996 // Lchar_loop
2997 __ bind(Lchar_loop);
2998 __ lduh(str2_reg, limit_reg, chr2_reg);
2999 __ cmp(chr1_reg, chr2_reg);
3000 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3001 __ delayed()->mov(G0, result_reg); //not equal
3002 __ inccc(limit_reg, sizeof(jchar));
3003 // annul LDUH if branch is not taken to prevent access past end of string
3004 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3005 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3006
3007 __ add(G0, 1, result_reg); //equal
3008
3009 __ bind(Ldone);
3010 %}
3011
3012 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3013 Label Lvector, Ldone, Lloop;
3014 MacroAssembler _masm(&cbuf);
3015
3016 Register ary1_reg = reg_to_register_object($ary1$$reg);
3017 Register ary2_reg = reg_to_register_object($ary2$$reg);
3018 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3019 Register tmp2_reg = O7;
3020 Register result_reg = reg_to_register_object($result$$reg);
3021
3022 int length_offset = arrayOopDesc::length_offset_in_bytes();
3023 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3024
3025 // return true if the same array
3026 __ cmp(ary1_reg, ary2_reg);
3027 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3028 __ delayed()->add(G0, 1, result_reg); // equal
3029
3030 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3031 __ delayed()->mov(G0, result_reg); // not equal
3032
3033 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3034 __ delayed()->mov(G0, result_reg); // not equal
3035
3036 //load the lengths of arrays
3037 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3038 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3039
3040 // return false if the two arrays are not equal length
3041 __ cmp(tmp1_reg, tmp2_reg);
3042 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3043 __ delayed()->mov(G0, result_reg); // not equal
3044
3045 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3046 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3047
3048 // load array addresses
3049 __ add(ary1_reg, base_offset, ary1_reg);
3050 __ add(ary2_reg, base_offset, ary2_reg);
3051
3052 // renaming registers
3053 Register chr1_reg = result_reg; // for characters in ary1
3054 Register chr2_reg = tmp2_reg; // for characters in ary2
3055 Register limit_reg = tmp1_reg; // length
3056
3057 // set byte count
3058 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3059
3060 // Compare char[] arrays aligned to 4 bytes.
3061 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3062 chr1_reg, chr2_reg, Ldone);
3063 __ add(G0, 1, result_reg); // equals
3064
3065 __ bind(Ldone);
3066 %}
3067
3068 enc_class enc_rethrow() %{
3069 cbuf.set_inst_mark();
3070 Register temp_reg = G3;
3071 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3072 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3073 MacroAssembler _masm(&cbuf);
3074 #ifdef ASSERT
3075 __ save_frame(0);
3076 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3077 __ sethi(last_rethrow_addrlit, L1);
3078 Address addr(L1, last_rethrow_addrlit.low10());
3079 __ get_pc(L2);
3080 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3081 __ st_ptr(L2, addr);
3082 __ restore();
3083 #endif
3084 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3085 __ delayed()->nop();
3086 %}
3087
3088 enc_class emit_mem_nop() %{
3089 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3090 unsigned int *code = (unsigned int*)cbuf.code_end();
3091 *code = (unsigned int)0xc0839040;
3092 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3093 %}
3094
3095 enc_class emit_fadd_nop() %{
3096 // Generates the instruction FMOVS f31,f31
3097 unsigned int *code = (unsigned int*)cbuf.code_end();
3098 *code = (unsigned int)0xbfa0003f;
3099 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3100 %}
3101
3102 enc_class emit_br_nop() %{
3103 // Generates the instruction BPN,PN .
3104 unsigned int *code = (unsigned int*)cbuf.code_end();
3105 *code = (unsigned int)0x00400000;
3106 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3107 %}
3108
3109 enc_class enc_membar_acquire %{
3110 MacroAssembler _masm(&cbuf);
3111 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3112 %}
3113
3114 enc_class enc_membar_release %{
3115 MacroAssembler _masm(&cbuf);
3116 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3117 %}
3118
3119 enc_class enc_membar_volatile %{
3120 MacroAssembler _masm(&cbuf);
3121 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3122 %}
3123
3124 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3125 MacroAssembler _masm(&cbuf);
3126 Register src_reg = reg_to_register_object($src$$reg);
3127 Register dst_reg = reg_to_register_object($dst$$reg);
3128 __ sllx(src_reg, 56, dst_reg);
3129 __ srlx(dst_reg, 8, O7);
3130 __ or3 (dst_reg, O7, dst_reg);
3131 __ srlx(dst_reg, 16, O7);
3132 __ or3 (dst_reg, O7, dst_reg);
3133 __ srlx(dst_reg, 32, O7);
3134 __ or3 (dst_reg, O7, dst_reg);
3135 %}
3136
3137 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3138 MacroAssembler _masm(&cbuf);
3139 Register src_reg = reg_to_register_object($src$$reg);
3140 Register dst_reg = reg_to_register_object($dst$$reg);
3141 __ sll(src_reg, 24, dst_reg);
3142 __ srl(dst_reg, 8, O7);
3143 __ or3(dst_reg, O7, dst_reg);
3144 __ srl(dst_reg, 16, O7);
3145 __ or3(dst_reg, O7, dst_reg);
3146 %}
3147
3148 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3149 MacroAssembler _masm(&cbuf);
3150 Register src_reg = reg_to_register_object($src$$reg);
3151 Register dst_reg = reg_to_register_object($dst$$reg);
3152 __ sllx(src_reg, 48, dst_reg);
3153 __ srlx(dst_reg, 16, O7);
3154 __ or3 (dst_reg, O7, dst_reg);
3155 __ srlx(dst_reg, 32, O7);
3156 __ or3 (dst_reg, O7, dst_reg);
3157 %}
3158
3159 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3160 MacroAssembler _masm(&cbuf);
3161 Register src_reg = reg_to_register_object($src$$reg);
3162 Register dst_reg = reg_to_register_object($dst$$reg);
3163 __ sllx(src_reg, 32, dst_reg);
3164 __ srlx(dst_reg, 32, O7);
3165 __ or3 (dst_reg, O7, dst_reg);
3166 %}
3167
3168 %}
3169
3170 //----------FRAME--------------------------------------------------------------
3171 // Definition of frame structure and management information.
3172 //
3173 // S T A C K L A Y O U T Allocators stack-slot number
3174 // | (to get allocators register number
3175 // G Owned by | | v add VMRegImpl::stack0)
3176 // r CALLER | |
3177 // o | +--------+ pad to even-align allocators stack-slot
3178 // w V | pad0 | numbers; owned by CALLER
3179 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3180 // h ^ | in | 5
3181 // | | args | 4 Holes in incoming args owned by SELF
3182 // | | | | 3
3183 // | | +--------+
3184 // V | | old out| Empty on Intel, window on Sparc
3185 // | old |preserve| Must be even aligned.
3186 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3187 // | | in | 3 area for Intel ret address
3188 // Owned by |preserve| Empty on Sparc.
3189 // SELF +--------+
3190 // | | pad2 | 2 pad to align old SP
3191 // | +--------+ 1
3192 // | | locks | 0
3193 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3194 // | | pad1 | 11 pad to align new SP
3195 // | +--------+
3196 // | | | 10
3197 // | | spills | 9 spills
3198 // V | | 8 (pad0 slot for callee)
3199 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3200 // ^ | out | 7
3201 // | | args | 6 Holes in outgoing args owned by CALLEE
3202 // Owned by +--------+
3203 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3204 // | new |preserve| Must be even-aligned.
3205 // | SP-+--------+----> Matcher::_new_SP, even aligned
3206 // | | |
3207 //
3208 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3209 // known from SELF's arguments and the Java calling convention.
3210 // Region 6-7 is determined per call site.
3211 // Note 2: If the calling convention leaves holes in the incoming argument
3212 // area, those holes are owned by SELF. Holes in the outgoing area
3213 // are owned by the CALLEE. Holes should not be nessecary in the
3214 // incoming area, as the Java calling convention is completely under
3215 // the control of the AD file. Doubles can be sorted and packed to
3216 // avoid holes. Holes in the outgoing arguments may be nessecary for
3217 // varargs C calling conventions.
3218 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3219 // even aligned with pad0 as needed.
3220 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3221 // region 6-11 is even aligned; it may be padded out more so that
3222 // the region from SP to FP meets the minimum stack alignment.
3223
3224 frame %{
3225 // What direction does stack grow in (assumed to be same for native & Java)
3226 stack_direction(TOWARDS_LOW);
3227
3228 // These two registers define part of the calling convention
3229 // between compiled code and the interpreter.
3230 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3231 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3232
3233 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3234 cisc_spilling_operand_name(indOffset);
3235
3236 // Number of stack slots consumed by a Monitor enter
3237 #ifdef _LP64
3238 sync_stack_slots(2);
3239 #else
3240 sync_stack_slots(1);
3241 #endif
3242
3243 // Compiled code's Frame Pointer
3244 frame_pointer(R_SP);
3245
3246 // Stack alignment requirement
3247 stack_alignment(StackAlignmentInBytes);
3248 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3249 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3250
3251 // Number of stack slots between incoming argument block and the start of
3252 // a new frame. The PROLOG must add this many slots to the stack. The
3253 // EPILOG must remove this many slots.
3254 in_preserve_stack_slots(0);
3255
3256 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3257 // for calls to C. Supports the var-args backing area for register parms.
3258 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3259 #ifdef _LP64
3260 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3261 varargs_C_out_slots_killed(12);
3262 #else
3263 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3264 varargs_C_out_slots_killed( 7);
3265 #endif
3266
3267 // The after-PROLOG location of the return address. Location of
3268 // return address specifies a type (REG or STACK) and a number
3269 // representing the register number (i.e. - use a register name) or
3270 // stack slot.
3271 return_addr(REG R_I7); // Ret Addr is in register I7
3272
3273 // Body of function which returns an OptoRegs array locating
3274 // arguments either in registers or in stack slots for calling
3275 // java
3276 calling_convention %{
3277 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3278
3279 %}
3280
3281 // Body of function which returns an OptoRegs array locating
3282 // arguments either in registers or in stack slots for callin
3283 // C.
3284 c_calling_convention %{
3285 // This is obviously always outgoing
3286 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3287 %}
3288
3289 // Location of native (C/C++) and interpreter return values. This is specified to
3290 // be the same as Java. In the 32-bit VM, long values are actually returned from
3291 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3292 // to and from the register pairs is done by the appropriate call and epilog
3293 // opcodes. This simplifies the register allocator.
3294 c_return_value %{
3295 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3296 #ifdef _LP64
3297 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3298 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3299 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3300 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3301 #else // !_LP64
3302 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3303 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3304 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3305 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3306 #endif
3307 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3308 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3309 %}
3310
3311 // Location of compiled Java return values. Same as C
3312 return_value %{
3313 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3314 #ifdef _LP64
3315 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3316 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3317 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3318 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3319 #else // !_LP64
3320 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3321 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3322 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3323 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3324 #endif
3325 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3326 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3327 %}
3328
3329 %}
3330
3331
3332 //----------ATTRIBUTES---------------------------------------------------------
3333 //----------Operand Attributes-------------------------------------------------
3334 op_attrib op_cost(1); // Required cost attribute
3335
3336 //----------Instruction Attributes---------------------------------------------
3337 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3338 ins_attrib ins_size(32); // Required size attribute (in bits)
3339 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3340 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3341 // non-matching short branch variant of some
3342 // long branch?
3343
3344 //----------OPERANDS-----------------------------------------------------------
3345 // Operand definitions must precede instruction definitions for correct parsing
3346 // in the ADLC because operands constitute user defined types which are used in
3347 // instruction definitions.
3348
3349 //----------Simple Operands----------------------------------------------------
3350 // Immediate Operands
3351 // Integer Immediate: 32-bit
3352 operand immI() %{
3353 match(ConI);
3354
3355 op_cost(0);
3356 // formats are generated automatically for constants and base registers
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360
3361 // Integer Immediate: 8-bit
3362 operand immI8() %{
3363 predicate(Assembler::is_simm(n->get_int(), 8));
3364 match(ConI);
3365 op_cost(0);
3366 format %{ %}
3367 interface(CONST_INTER);
3368 %}
3369
3370 // Integer Immediate: 13-bit
3371 operand immI13() %{
3372 predicate(Assembler::is_simm13(n->get_int()));
3373 match(ConI);
3374 op_cost(0);
3375
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 // Integer Immediate: 13-bit minus 7
3381 operand immI13m7() %{
3382 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3383 match(ConI);
3384 op_cost(0);
3385
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 // Integer Immediate: 16-bit
3391 operand immI16() %{
3392 predicate(Assembler::is_simm(n->get_int(), 16));
3393 match(ConI);
3394 op_cost(0);
3395 format %{ %}
3396 interface(CONST_INTER);
3397 %}
3398
3399 // Unsigned (positive) Integer Immediate: 13-bit
3400 operand immU13() %{
3401 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3402 match(ConI);
3403 op_cost(0);
3404
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Integer Immediate: 6-bit
3410 operand immU6() %{
3411 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3412 match(ConI);
3413 op_cost(0);
3414 format %{ %}
3415 interface(CONST_INTER);
3416 %}
3417
3418 // Integer Immediate: 11-bit
3419 operand immI11() %{
3420 predicate(Assembler::is_simm(n->get_int(),11));
3421 match(ConI);
3422 op_cost(0);
3423 format %{ %}
3424 interface(CONST_INTER);
3425 %}
3426
3427 // Integer Immediate: 0-bit
3428 operand immI0() %{
3429 predicate(n->get_int() == 0);
3430 match(ConI);
3431 op_cost(0);
3432
3433 format %{ %}
3434 interface(CONST_INTER);
3435 %}
3436
3437 // Integer Immediate: the value 10
3438 operand immI10() %{
3439 predicate(n->get_int() == 10);
3440 match(ConI);
3441 op_cost(0);
3442
3443 format %{ %}
3444 interface(CONST_INTER);
3445 %}
3446
3447 // Integer Immediate: the values 0-31
3448 operand immU5() %{
3449 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3450 match(ConI);
3451 op_cost(0);
3452
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 // Integer Immediate: the values 1-31
3458 operand immI_1_31() %{
3459 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3460 match(ConI);
3461 op_cost(0);
3462
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Integer Immediate: the values 32-63
3468 operand immI_32_63() %{
3469 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3470 match(ConI);
3471 op_cost(0);
3472
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3476
3477 // Immediates for special shifts (sign extend)
3478
3479 // Integer Immediate: the value 16
3480 operand immI_16() %{
3481 predicate(n->get_int() == 16);
3482 match(ConI);
3483 op_cost(0);
3484
3485 format %{ %}
3486 interface(CONST_INTER);
3487 %}
3488
3489 // Integer Immediate: the value 24
3490 operand immI_24() %{
3491 predicate(n->get_int() == 24);
3492 match(ConI);
3493 op_cost(0);
3494
3495 format %{ %}
3496 interface(CONST_INTER);
3497 %}
3498
3499 // Integer Immediate: the value 255
3500 operand immI_255() %{
3501 predicate( n->get_int() == 255 );
3502 match(ConI);
3503 op_cost(0);
3504
3505 format %{ %}
3506 interface(CONST_INTER);
3507 %}
3508
3509 // Integer Immediate: the value 65535
3510 operand immI_65535() %{
3511 predicate(n->get_int() == 65535);
3512 match(ConI);
3513 op_cost(0);
3514
3515 format %{ %}
3516 interface(CONST_INTER);
3517 %}
3518
3519 // Long Immediate: the value FF
3520 operand immL_FF() %{
3521 predicate( n->get_long() == 0xFFL );
3522 match(ConL);
3523 op_cost(0);
3524
3525 format %{ %}
3526 interface(CONST_INTER);
3527 %}
3528
3529 // Long Immediate: the value FFFF
3530 operand immL_FFFF() %{
3531 predicate( n->get_long() == 0xFFFFL );
3532 match(ConL);
3533 op_cost(0);
3534
3535 format %{ %}
3536 interface(CONST_INTER);
3537 %}
3538
3539 // Pointer Immediate: 32 or 64-bit
3540 operand immP() %{
3541 match(ConP);
3542
3543 op_cost(5);
3544 // formats are generated automatically for constants and base registers
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3548
3549 operand immP13() %{
3550 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3551 match(ConP);
3552 op_cost(0);
3553
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3557
3558 operand immP0() %{
3559 predicate(n->get_ptr() == 0);
3560 match(ConP);
3561 op_cost(0);
3562
3563 format %{ %}
3564 interface(CONST_INTER);
3565 %}
3566
3567 operand immP_poll() %{
3568 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3569 match(ConP);
3570
3571 // formats are generated automatically for constants and base registers
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 // Pointer Immediate
3577 operand immN()
3578 %{
3579 match(ConN);
3580
3581 op_cost(10);
3582 format %{ %}
3583 interface(CONST_INTER);
3584 %}
3585
3586 // NULL Pointer Immediate
3587 operand immN0()
3588 %{
3589 predicate(n->get_narrowcon() == 0);
3590 match(ConN);
3591
3592 op_cost(0);
3593 format %{ %}
3594 interface(CONST_INTER);
3595 %}
3596
3597 operand immL() %{
3598 match(ConL);
3599 op_cost(40);
3600 // formats are generated automatically for constants and base registers
3601 format %{ %}
3602 interface(CONST_INTER);
3603 %}
3604
3605 operand immL0() %{
3606 predicate(n->get_long() == 0L);
3607 match(ConL);
3608 op_cost(0);
3609 // formats are generated automatically for constants and base registers
3610 format %{ %}
3611 interface(CONST_INTER);
3612 %}
3613
3614 // Long Immediate: 13-bit
3615 operand immL13() %{
3616 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3617 match(ConL);
3618 op_cost(0);
3619
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3623
3624 // Long Immediate: 13-bit minus 7
3625 operand immL13m7() %{
3626 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3627 match(ConL);
3628 op_cost(0);
3629
3630 format %{ %}
3631 interface(CONST_INTER);
3632 %}
3633
3634 // Long Immediate: low 32-bit mask
3635 operand immL_32bits() %{
3636 predicate(n->get_long() == 0xFFFFFFFFL);
3637 match(ConL);
3638 op_cost(0);
3639
3640 format %{ %}
3641 interface(CONST_INTER);
3642 %}
3643
3644 // Double Immediate
3645 operand immD() %{
3646 match(ConD);
3647
3648 op_cost(40);
3649 format %{ %}
3650 interface(CONST_INTER);
3651 %}
3652
3653 operand immD0() %{
3654 #ifdef _LP64
3655 // on 64-bit architectures this comparision is faster
3656 predicate(jlong_cast(n->getd()) == 0);
3657 #else
3658 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3659 #endif
3660 match(ConD);
3661
3662 op_cost(0);
3663 format %{ %}
3664 interface(CONST_INTER);
3665 %}
3666
3667 // Float Immediate
3668 operand immF() %{
3669 match(ConF);
3670
3671 op_cost(20);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3675
3676 // Float Immediate: 0
3677 operand immF0() %{
3678 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3679 match(ConF);
3680
3681 op_cost(0);
3682 format %{ %}
3683 interface(CONST_INTER);
3684 %}
3685
3686 // Integer Register Operands
3687 // Integer Register
3688 operand iRegI() %{
3689 constraint(ALLOC_IN_RC(int_reg));
3690 match(RegI);
3691
3692 match(notemp_iRegI);
3693 match(g1RegI);
3694 match(o0RegI);
3695 match(iRegIsafe);
3696
3697 format %{ %}
3698 interface(REG_INTER);
3699 %}
3700
3701 operand notemp_iRegI() %{
3702 constraint(ALLOC_IN_RC(notemp_int_reg));
3703 match(RegI);
3704
3705 match(o0RegI);
3706
3707 format %{ %}
3708 interface(REG_INTER);
3709 %}
3710
3711 operand o0RegI() %{
3712 constraint(ALLOC_IN_RC(o0_regI));
3713 match(iRegI);
3714
3715 format %{ %}
3716 interface(REG_INTER);
3717 %}
3718
3719 // Pointer Register
3720 operand iRegP() %{
3721 constraint(ALLOC_IN_RC(ptr_reg));
3722 match(RegP);
3723
3724 match(lock_ptr_RegP);
3725 match(g1RegP);
3726 match(g2RegP);
3727 match(g3RegP);
3728 match(g4RegP);
3729 match(i0RegP);
3730 match(o0RegP);
3731 match(o1RegP);
3732 match(l7RegP);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand sp_ptr_RegP() %{
3739 constraint(ALLOC_IN_RC(sp_ptr_reg));
3740 match(RegP);
3741 match(iRegP);
3742
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3746
3747 operand lock_ptr_RegP() %{
3748 constraint(ALLOC_IN_RC(lock_ptr_reg));
3749 match(RegP);
3750 match(i0RegP);
3751 match(o0RegP);
3752 match(o1RegP);
3753 match(l7RegP);
3754
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 operand g1RegP() %{
3760 constraint(ALLOC_IN_RC(g1_regP));
3761 match(iRegP);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 operand g2RegP() %{
3768 constraint(ALLOC_IN_RC(g2_regP));
3769 match(iRegP);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 operand g3RegP() %{
3776 constraint(ALLOC_IN_RC(g3_regP));
3777 match(iRegP);
3778
3779 format %{ %}
3780 interface(REG_INTER);
3781 %}
3782
3783 operand g1RegI() %{
3784 constraint(ALLOC_IN_RC(g1_regI));
3785 match(iRegI);
3786
3787 format %{ %}
3788 interface(REG_INTER);
3789 %}
3790
3791 operand g3RegI() %{
3792 constraint(ALLOC_IN_RC(g3_regI));
3793 match(iRegI);
3794
3795 format %{ %}
3796 interface(REG_INTER);
3797 %}
3798
3799 operand g4RegI() %{
3800 constraint(ALLOC_IN_RC(g4_regI));
3801 match(iRegI);
3802
3803 format %{ %}
3804 interface(REG_INTER);
3805 %}
3806
3807 operand g4RegP() %{
3808 constraint(ALLOC_IN_RC(g4_regP));
3809 match(iRegP);
3810
3811 format %{ %}
3812 interface(REG_INTER);
3813 %}
3814
3815 operand i0RegP() %{
3816 constraint(ALLOC_IN_RC(i0_regP));
3817 match(iRegP);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand o0RegP() %{
3824 constraint(ALLOC_IN_RC(o0_regP));
3825 match(iRegP);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand o1RegP() %{
3832 constraint(ALLOC_IN_RC(o1_regP));
3833 match(iRegP);
3834
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand o2RegP() %{
3840 constraint(ALLOC_IN_RC(o2_regP));
3841 match(iRegP);
3842
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand o7RegP() %{
3848 constraint(ALLOC_IN_RC(o7_regP));
3849 match(iRegP);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand l7RegP() %{
3856 constraint(ALLOC_IN_RC(l7_regP));
3857 match(iRegP);
3858
3859 format %{ %}
3860 interface(REG_INTER);
3861 %}
3862
3863 operand o7RegI() %{
3864 constraint(ALLOC_IN_RC(o7_regI));
3865 match(iRegI);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand iRegN() %{
3872 constraint(ALLOC_IN_RC(int_reg));
3873 match(RegN);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 // Long Register
3880 operand iRegL() %{
3881 constraint(ALLOC_IN_RC(long_reg));
3882 match(RegL);
3883
3884 format %{ %}
3885 interface(REG_INTER);
3886 %}
3887
3888 operand o2RegL() %{
3889 constraint(ALLOC_IN_RC(o2_regL));
3890 match(iRegL);
3891
3892 format %{ %}
3893 interface(REG_INTER);
3894 %}
3895
3896 operand o7RegL() %{
3897 constraint(ALLOC_IN_RC(o7_regL));
3898 match(iRegL);
3899
3900 format %{ %}
3901 interface(REG_INTER);
3902 %}
3903
3904 operand g1RegL() %{
3905 constraint(ALLOC_IN_RC(g1_regL));
3906 match(iRegL);
3907
3908 format %{ %}
3909 interface(REG_INTER);
3910 %}
3911
3912 operand g3RegL() %{
3913 constraint(ALLOC_IN_RC(g3_regL));
3914 match(iRegL);
3915
3916 format %{ %}
3917 interface(REG_INTER);
3918 %}
3919
3920 // Int Register safe
3921 // This is 64bit safe
3922 operand iRegIsafe() %{
3923 constraint(ALLOC_IN_RC(long_reg));
3924
3925 match(iRegI);
3926
3927 format %{ %}
3928 interface(REG_INTER);
3929 %}
3930
3931 // Condition Code Flag Register
3932 operand flagsReg() %{
3933 constraint(ALLOC_IN_RC(int_flags));
3934 match(RegFlags);
3935
3936 format %{ "ccr" %} // both ICC and XCC
3937 interface(REG_INTER);
3938 %}
3939
3940 // Condition Code Register, unsigned comparisons.
3941 operand flagsRegU() %{
3942 constraint(ALLOC_IN_RC(int_flags));
3943 match(RegFlags);
3944
3945 format %{ "icc_U" %}
3946 interface(REG_INTER);
3947 %}
3948
3949 // Condition Code Register, pointer comparisons.
3950 operand flagsRegP() %{
3951 constraint(ALLOC_IN_RC(int_flags));
3952 match(RegFlags);
3953
3954 #ifdef _LP64
3955 format %{ "xcc_P" %}
3956 #else
3957 format %{ "icc_P" %}
3958 #endif
3959 interface(REG_INTER);
3960 %}
3961
3962 // Condition Code Register, long comparisons.
3963 operand flagsRegL() %{
3964 constraint(ALLOC_IN_RC(int_flags));
3965 match(RegFlags);
3966
3967 format %{ "xcc_L" %}
3968 interface(REG_INTER);
3969 %}
3970
3971 // Condition Code Register, floating comparisons, unordered same as "less".
3972 operand flagsRegF() %{
3973 constraint(ALLOC_IN_RC(float_flags));
3974 match(RegFlags);
3975 match(flagsRegF0);
3976
3977 format %{ %}
3978 interface(REG_INTER);
3979 %}
3980
3981 operand flagsRegF0() %{
3982 constraint(ALLOC_IN_RC(float_flag0));
3983 match(RegFlags);
3984
3985 format %{ %}
3986 interface(REG_INTER);
3987 %}
3988
3989
3990 // Condition Code Flag Register used by long compare
3991 operand flagsReg_long_LTGE() %{
3992 constraint(ALLOC_IN_RC(int_flags));
3993 match(RegFlags);
3994 format %{ "icc_LTGE" %}
3995 interface(REG_INTER);
3996 %}
3997 operand flagsReg_long_EQNE() %{
3998 constraint(ALLOC_IN_RC(int_flags));
3999 match(RegFlags);
4000 format %{ "icc_EQNE" %}
4001 interface(REG_INTER);
4002 %}
4003 operand flagsReg_long_LEGT() %{
4004 constraint(ALLOC_IN_RC(int_flags));
4005 match(RegFlags);
4006 format %{ "icc_LEGT" %}
4007 interface(REG_INTER);
4008 %}
4009
4010
4011 operand regD() %{
4012 constraint(ALLOC_IN_RC(dflt_reg));
4013 match(RegD);
4014
4015 match(regD_low);
4016
4017 format %{ %}
4018 interface(REG_INTER);
4019 %}
4020
4021 operand regF() %{
4022 constraint(ALLOC_IN_RC(sflt_reg));
4023 match(RegF);
4024
4025 format %{ %}
4026 interface(REG_INTER);
4027 %}
4028
4029 operand regD_low() %{
4030 constraint(ALLOC_IN_RC(dflt_low_reg));
4031 match(regD);
4032
4033 format %{ %}
4034 interface(REG_INTER);
4035 %}
4036
4037 // Special Registers
4038
4039 // Method Register
4040 operand inline_cache_regP(iRegP reg) %{
4041 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4042 match(reg);
4043 format %{ %}
4044 interface(REG_INTER);
4045 %}
4046
4047 operand interpreter_method_oop_regP(iRegP reg) %{
4048 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4049 match(reg);
4050 format %{ %}
4051 interface(REG_INTER);
4052 %}
4053
4054
4055 //----------Complex Operands---------------------------------------------------
4056 // Indirect Memory Reference
4057 operand indirect(sp_ptr_RegP reg) %{
4058 constraint(ALLOC_IN_RC(sp_ptr_reg));
4059 match(reg);
4060
4061 op_cost(100);
4062 format %{ "[$reg]" %}
4063 interface(MEMORY_INTER) %{
4064 base($reg);
4065 index(0x0);
4066 scale(0x0);
4067 disp(0x0);
4068 %}
4069 %}
4070
4071 // Indirect with simm13 Offset
4072 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4073 constraint(ALLOC_IN_RC(sp_ptr_reg));
4074 match(AddP reg offset);
4075
4076 op_cost(100);
4077 format %{ "[$reg + $offset]" %}
4078 interface(MEMORY_INTER) %{
4079 base($reg);
4080 index(0x0);
4081 scale(0x0);
4082 disp($offset);
4083 %}
4084 %}
4085
4086 // Indirect with simm13 Offset minus 7
4087 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4088 constraint(ALLOC_IN_RC(sp_ptr_reg));
4089 match(AddP reg offset);
4090
4091 op_cost(100);
4092 format %{ "[$reg + $offset]" %}
4093 interface(MEMORY_INTER) %{
4094 base($reg);
4095 index(0x0);
4096 scale(0x0);
4097 disp($offset);
4098 %}
4099 %}
4100
4101 // Note: Intel has a swapped version also, like this:
4102 //operand indOffsetX(iRegI reg, immP offset) %{
4103 // constraint(ALLOC_IN_RC(int_reg));
4104 // match(AddP offset reg);
4105 //
4106 // op_cost(100);
4107 // format %{ "[$reg + $offset]" %}
4108 // interface(MEMORY_INTER) %{
4109 // base($reg);
4110 // index(0x0);
4111 // scale(0x0);
4112 // disp($offset);
4113 // %}
4114 //%}
4115 //// However, it doesn't make sense for SPARC, since
4116 // we have no particularly good way to embed oops in
4117 // single instructions.
4118
4119 // Indirect with Register Index
4120 operand indIndex(iRegP addr, iRegX index) %{
4121 constraint(ALLOC_IN_RC(ptr_reg));
4122 match(AddP addr index);
4123
4124 op_cost(100);
4125 format %{ "[$addr + $index]" %}
4126 interface(MEMORY_INTER) %{
4127 base($addr);
4128 index($index);
4129 scale(0x0);
4130 disp(0x0);
4131 %}
4132 %}
4133
4134 //----------Special Memory Operands--------------------------------------------
4135 // Stack Slot Operand - This operand is used for loading and storing temporary
4136 // values on the stack where a match requires a value to
4137 // flow through memory.
4138 operand stackSlotI(sRegI reg) %{
4139 constraint(ALLOC_IN_RC(stack_slots));
4140 op_cost(100);
4141 //match(RegI);
4142 format %{ "[$reg]" %}
4143 interface(MEMORY_INTER) %{
4144 base(0xE); // R_SP
4145 index(0x0);
4146 scale(0x0);
4147 disp($reg); // Stack Offset
4148 %}
4149 %}
4150
4151 operand stackSlotP(sRegP reg) %{
4152 constraint(ALLOC_IN_RC(stack_slots));
4153 op_cost(100);
4154 //match(RegP);
4155 format %{ "[$reg]" %}
4156 interface(MEMORY_INTER) %{
4157 base(0xE); // R_SP
4158 index(0x0);
4159 scale(0x0);
4160 disp($reg); // Stack Offset
4161 %}
4162 %}
4163
4164 operand stackSlotF(sRegF reg) %{
4165 constraint(ALLOC_IN_RC(stack_slots));
4166 op_cost(100);
4167 //match(RegF);
4168 format %{ "[$reg]" %}
4169 interface(MEMORY_INTER) %{
4170 base(0xE); // R_SP
4171 index(0x0);
4172 scale(0x0);
4173 disp($reg); // Stack Offset
4174 %}
4175 %}
4176 operand stackSlotD(sRegD reg) %{
4177 constraint(ALLOC_IN_RC(stack_slots));
4178 op_cost(100);
4179 //match(RegD);
4180 format %{ "[$reg]" %}
4181 interface(MEMORY_INTER) %{
4182 base(0xE); // R_SP
4183 index(0x0);
4184 scale(0x0);
4185 disp($reg); // Stack Offset
4186 %}
4187 %}
4188 operand stackSlotL(sRegL reg) %{
4189 constraint(ALLOC_IN_RC(stack_slots));
4190 op_cost(100);
4191 //match(RegL);
4192 format %{ "[$reg]" %}
4193 interface(MEMORY_INTER) %{
4194 base(0xE); // R_SP
4195 index(0x0);
4196 scale(0x0);
4197 disp($reg); // Stack Offset
4198 %}
4199 %}
4200
4201 // Operands for expressing Control Flow
4202 // NOTE: Label is a predefined operand which should not be redefined in
4203 // the AD file. It is generically handled within the ADLC.
4204
4205 //----------Conditional Branch Operands----------------------------------------
4206 // Comparison Op - This is the operation of the comparison, and is limited to
4207 // the following set of codes:
4208 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4209 //
4210 // Other attributes of the comparison, such as unsignedness, are specified
4211 // by the comparison instruction that sets a condition code flags register.
4212 // That result is represented by a flags operand whose subtype is appropriate
4213 // to the unsignedness (etc.) of the comparison.
4214 //
4215 // Later, the instruction which matches both the Comparison Op (a Bool) and
4216 // the flags (produced by the Cmp) specifies the coding of the comparison op
4217 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4218
4219 operand cmpOp() %{
4220 match(Bool);
4221
4222 format %{ "" %}
4223 interface(COND_INTER) %{
4224 equal(0x1);
4225 not_equal(0x9);
4226 less(0x3);
4227 greater_equal(0xB);
4228 less_equal(0x2);
4229 greater(0xA);
4230 %}
4231 %}
4232
4233 // Comparison Op, unsigned
4234 operand cmpOpU() %{
4235 match(Bool);
4236
4237 format %{ "u" %}
4238 interface(COND_INTER) %{
4239 equal(0x1);
4240 not_equal(0x9);
4241 less(0x5);
4242 greater_equal(0xD);
4243 less_equal(0x4);
4244 greater(0xC);
4245 %}
4246 %}
4247
4248 // Comparison Op, pointer (same as unsigned)
4249 operand cmpOpP() %{
4250 match(Bool);
4251
4252 format %{ "p" %}
4253 interface(COND_INTER) %{
4254 equal(0x1);
4255 not_equal(0x9);
4256 less(0x5);
4257 greater_equal(0xD);
4258 less_equal(0x4);
4259 greater(0xC);
4260 %}
4261 %}
4262
4263 // Comparison Op, branch-register encoding
4264 operand cmpOp_reg() %{
4265 match(Bool);
4266
4267 format %{ "" %}
4268 interface(COND_INTER) %{
4269 equal (0x1);
4270 not_equal (0x5);
4271 less (0x3);
4272 greater_equal(0x7);
4273 less_equal (0x2);
4274 greater (0x6);
4275 %}
4276 %}
4277
4278 // Comparison Code, floating, unordered same as less
4279 operand cmpOpF() %{
4280 match(Bool);
4281
4282 format %{ "fl" %}
4283 interface(COND_INTER) %{
4284 equal(0x9);
4285 not_equal(0x1);
4286 less(0x3);
4287 greater_equal(0xB);
4288 less_equal(0xE);
4289 greater(0x6);
4290 %}
4291 %}
4292
4293 // Used by long compare
4294 operand cmpOp_commute() %{
4295 match(Bool);
4296
4297 format %{ "" %}
4298 interface(COND_INTER) %{
4299 equal(0x1);
4300 not_equal(0x9);
4301 less(0xA);
4302 greater_equal(0x2);
4303 less_equal(0xB);
4304 greater(0x3);
4305 %}
4306 %}
4307
4308 //----------OPERAND CLASSES----------------------------------------------------
4309 // Operand Classes are groups of operands that are used to simplify
4310 // instruction definitions by not requiring the AD writer to specify separate
4311 // instructions for every form of operand when the instruction accepts
4312 // multiple operand types with the same basic encoding and format. The classic
4313 // case of this is memory operands.
4314 // Indirect is not included since its use is limited to Compare & Swap
4315 opclass memory( indirect, indOffset13, indIndex );
4316
4317 //----------PIPELINE-----------------------------------------------------------
4318 pipeline %{
4319
4320 //----------ATTRIBUTES---------------------------------------------------------
4321 attributes %{
4322 fixed_size_instructions; // Fixed size instructions
4323 branch_has_delay_slot; // Branch has delay slot following
4324 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4325 instruction_unit_size = 4; // An instruction is 4 bytes long
4326 instruction_fetch_unit_size = 16; // The processor fetches one line
4327 instruction_fetch_units = 1; // of 16 bytes
4328
4329 // List of nop instructions
4330 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4331 %}
4332
4333 //----------RESOURCES----------------------------------------------------------
4334 // Resources are the functional units available to the machine
4335 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4336
4337 //----------PIPELINE DESCRIPTION-----------------------------------------------
4338 // Pipeline Description specifies the stages in the machine's pipeline
4339
4340 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4341
4342 //----------PIPELINE CLASSES---------------------------------------------------
4343 // Pipeline Classes describe the stages in which input and output are
4344 // referenced by the hardware pipeline.
4345
4346 // Integer ALU reg-reg operation
4347 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4348 single_instruction;
4349 dst : E(write);
4350 src1 : R(read);
4351 src2 : R(read);
4352 IALU : R;
4353 %}
4354
4355 // Integer ALU reg-reg long operation
4356 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4357 instruction_count(2);
4358 dst : E(write);
4359 src1 : R(read);
4360 src2 : R(read);
4361 IALU : R;
4362 IALU : R;
4363 %}
4364
4365 // Integer ALU reg-reg long dependent operation
4366 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4367 instruction_count(1); multiple_bundles;
4368 dst : E(write);
4369 src1 : R(read);
4370 src2 : R(read);
4371 cr : E(write);
4372 IALU : R(2);
4373 %}
4374
4375 // Integer ALU reg-imm operaion
4376 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4377 single_instruction;
4378 dst : E(write);
4379 src1 : R(read);
4380 IALU : R;
4381 %}
4382
4383 // Integer ALU reg-reg operation with condition code
4384 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4385 single_instruction;
4386 dst : E(write);
4387 cr : E(write);
4388 src1 : R(read);
4389 src2 : R(read);
4390 IALU : R;
4391 %}
4392
4393 // Integer ALU reg-imm operation with condition code
4394 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4395 single_instruction;
4396 dst : E(write);
4397 cr : E(write);
4398 src1 : R(read);
4399 IALU : R;
4400 %}
4401
4402 // Integer ALU zero-reg operation
4403 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4404 single_instruction;
4405 dst : E(write);
4406 src2 : R(read);
4407 IALU : R;
4408 %}
4409
4410 // Integer ALU zero-reg operation with condition code only
4411 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4412 single_instruction;
4413 cr : E(write);
4414 src : R(read);
4415 IALU : R;
4416 %}
4417
4418 // Integer ALU reg-reg operation with condition code only
4419 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4420 single_instruction;
4421 cr : E(write);
4422 src1 : R(read);
4423 src2 : R(read);
4424 IALU : R;
4425 %}
4426
4427 // Integer ALU reg-imm operation with condition code only
4428 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4429 single_instruction;
4430 cr : E(write);
4431 src1 : R(read);
4432 IALU : R;
4433 %}
4434
4435 // Integer ALU reg-reg-zero operation with condition code only
4436 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4437 single_instruction;
4438 cr : E(write);
4439 src1 : R(read);
4440 src2 : R(read);
4441 IALU : R;
4442 %}
4443
4444 // Integer ALU reg-imm-zero operation with condition code only
4445 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4446 single_instruction;
4447 cr : E(write);
4448 src1 : R(read);
4449 IALU : R;
4450 %}
4451
4452 // Integer ALU reg-reg operation with condition code, src1 modified
4453 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4454 single_instruction;
4455 cr : E(write);
4456 src1 : E(write);
4457 src1 : R(read);
4458 src2 : R(read);
4459 IALU : R;
4460 %}
4461
4462 // Integer ALU reg-imm operation with condition code, src1 modified
4463 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4464 single_instruction;
4465 cr : E(write);
4466 src1 : E(write);
4467 src1 : R(read);
4468 IALU : R;
4469 %}
4470
4471 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4472 multiple_bundles;
4473 dst : E(write)+4;
4474 cr : E(write);
4475 src1 : R(read);
4476 src2 : R(read);
4477 IALU : R(3);
4478 BR : R(2);
4479 %}
4480
4481 // Integer ALU operation
4482 pipe_class ialu_none(iRegI dst) %{
4483 single_instruction;
4484 dst : E(write);
4485 IALU : R;
4486 %}
4487
4488 // Integer ALU reg operation
4489 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4490 single_instruction; may_have_no_code;
4491 dst : E(write);
4492 src : R(read);
4493 IALU : R;
4494 %}
4495
4496 // Integer ALU reg conditional operation
4497 // This instruction has a 1 cycle stall, and cannot execute
4498 // in the same cycle as the instruction setting the condition
4499 // code. We kludge this by pretending to read the condition code
4500 // 1 cycle earlier, and by marking the functional units as busy
4501 // for 2 cycles with the result available 1 cycle later than
4502 // is really the case.
4503 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4504 single_instruction;
4505 op2_out : C(write);
4506 op1 : R(read);
4507 cr : R(read); // This is really E, with a 1 cycle stall
4508 BR : R(2);
4509 MS : R(2);
4510 %}
4511
4512 #ifdef _LP64
4513 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4514 instruction_count(1); multiple_bundles;
4515 dst : C(write)+1;
4516 src : R(read)+1;
4517 IALU : R(1);
4518 BR : E(2);
4519 MS : E(2);
4520 %}
4521 #endif
4522
4523 // Integer ALU reg operation
4524 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4525 single_instruction; may_have_no_code;
4526 dst : E(write);
4527 src : R(read);
4528 IALU : R;
4529 %}
4530 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4531 single_instruction; may_have_no_code;
4532 dst : E(write);
4533 src : R(read);
4534 IALU : R;
4535 %}
4536
4537 // Two integer ALU reg operations
4538 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4539 instruction_count(2);
4540 dst : E(write);
4541 src : R(read);
4542 A0 : R;
4543 A1 : R;
4544 %}
4545
4546 // Two integer ALU reg operations
4547 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4548 instruction_count(2); may_have_no_code;
4549 dst : E(write);
4550 src : R(read);
4551 A0 : R;
4552 A1 : R;
4553 %}
4554
4555 // Integer ALU imm operation
4556 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4557 single_instruction;
4558 dst : E(write);
4559 IALU : R;
4560 %}
4561
4562 // Integer ALU reg-reg with carry operation
4563 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4564 single_instruction;
4565 dst : E(write);
4566 src1 : R(read);
4567 src2 : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU cc operation
4572 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4573 single_instruction;
4574 dst : E(write);
4575 cc : R(read);
4576 IALU : R;
4577 %}
4578
4579 // Integer ALU cc / second IALU operation
4580 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4581 instruction_count(1); multiple_bundles;
4582 dst : E(write)+1;
4583 src : R(read);
4584 IALU : R;
4585 %}
4586
4587 // Integer ALU cc / second IALU operation
4588 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4589 instruction_count(1); multiple_bundles;
4590 dst : E(write)+1;
4591 p : R(read);
4592 q : R(read);
4593 IALU : R;
4594 %}
4595
4596 // Integer ALU hi-lo-reg operation
4597 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4598 instruction_count(1); multiple_bundles;
4599 dst : E(write)+1;
4600 IALU : R(2);
4601 %}
4602
4603 // Float ALU hi-lo-reg operation (with temp)
4604 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4605 instruction_count(1); multiple_bundles;
4606 dst : E(write)+1;
4607 IALU : R(2);
4608 %}
4609
4610 // Long Constant
4611 pipe_class loadConL( iRegL dst, immL src ) %{
4612 instruction_count(2); multiple_bundles;
4613 dst : E(write)+1;
4614 IALU : R(2);
4615 IALU : R(2);
4616 %}
4617
4618 // Pointer Constant
4619 pipe_class loadConP( iRegP dst, immP src ) %{
4620 instruction_count(0); multiple_bundles;
4621 fixed_latency(6);
4622 %}
4623
4624 // Polling Address
4625 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4626 #ifdef _LP64
4627 instruction_count(0); multiple_bundles;
4628 fixed_latency(6);
4629 #else
4630 dst : E(write);
4631 IALU : R;
4632 #endif
4633 %}
4634
4635 // Long Constant small
4636 pipe_class loadConLlo( iRegL dst, immL src ) %{
4637 instruction_count(2);
4638 dst : E(write);
4639 IALU : R;
4640 IALU : R;
4641 %}
4642
4643 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4644 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4645 instruction_count(1); multiple_bundles;
4646 src : R(read);
4647 dst : M(write)+1;
4648 IALU : R;
4649 MS : E;
4650 %}
4651
4652 // Integer ALU nop operation
4653 pipe_class ialu_nop() %{
4654 single_instruction;
4655 IALU : R;
4656 %}
4657
4658 // Integer ALU nop operation
4659 pipe_class ialu_nop_A0() %{
4660 single_instruction;
4661 A0 : R;
4662 %}
4663
4664 // Integer ALU nop operation
4665 pipe_class ialu_nop_A1() %{
4666 single_instruction;
4667 A1 : R;
4668 %}
4669
4670 // Integer Multiply reg-reg operation
4671 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4672 single_instruction;
4673 dst : E(write);
4674 src1 : R(read);
4675 src2 : R(read);
4676 MS : R(5);
4677 %}
4678
4679 // Integer Multiply reg-imm operation
4680 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4681 single_instruction;
4682 dst : E(write);
4683 src1 : R(read);
4684 MS : R(5);
4685 %}
4686
4687 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4688 single_instruction;
4689 dst : E(write)+4;
4690 src1 : R(read);
4691 src2 : R(read);
4692 MS : R(6);
4693 %}
4694
4695 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4696 single_instruction;
4697 dst : E(write)+4;
4698 src1 : R(read);
4699 MS : R(6);
4700 %}
4701
4702 // Integer Divide reg-reg
4703 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4704 instruction_count(1); multiple_bundles;
4705 dst : E(write);
4706 temp : E(write);
4707 src1 : R(read);
4708 src2 : R(read);
4709 temp : R(read);
4710 MS : R(38);
4711 %}
4712
4713 // Integer Divide reg-imm
4714 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4715 instruction_count(1); multiple_bundles;
4716 dst : E(write);
4717 temp : E(write);
4718 src1 : R(read);
4719 temp : R(read);
4720 MS : R(38);
4721 %}
4722
4723 // Long Divide
4724 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4725 dst : E(write)+71;
4726 src1 : R(read);
4727 src2 : R(read)+1;
4728 MS : R(70);
4729 %}
4730
4731 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4732 dst : E(write)+71;
4733 src1 : R(read);
4734 MS : R(70);
4735 %}
4736
4737 // Floating Point Add Float
4738 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4739 single_instruction;
4740 dst : X(write);
4741 src1 : E(read);
4742 src2 : E(read);
4743 FA : R;
4744 %}
4745
4746 // Floating Point Add Double
4747 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4748 single_instruction;
4749 dst : X(write);
4750 src1 : E(read);
4751 src2 : E(read);
4752 FA : R;
4753 %}
4754
4755 // Floating Point Conditional Move based on integer flags
4756 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4757 single_instruction;
4758 dst : X(write);
4759 src : E(read);
4760 cr : R(read);
4761 FA : R(2);
4762 BR : R(2);
4763 %}
4764
4765 // Floating Point Conditional Move based on integer flags
4766 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4767 single_instruction;
4768 dst : X(write);
4769 src : E(read);
4770 cr : R(read);
4771 FA : R(2);
4772 BR : R(2);
4773 %}
4774
4775 // Floating Point Multiply Float
4776 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4777 single_instruction;
4778 dst : X(write);
4779 src1 : E(read);
4780 src2 : E(read);
4781 FM : R;
4782 %}
4783
4784 // Floating Point Multiply Double
4785 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4786 single_instruction;
4787 dst : X(write);
4788 src1 : E(read);
4789 src2 : E(read);
4790 FM : R;
4791 %}
4792
4793 // Floating Point Divide Float
4794 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4795 single_instruction;
4796 dst : X(write);
4797 src1 : E(read);
4798 src2 : E(read);
4799 FM : R;
4800 FDIV : C(14);
4801 %}
4802
4803 // Floating Point Divide Double
4804 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4805 single_instruction;
4806 dst : X(write);
4807 src1 : E(read);
4808 src2 : E(read);
4809 FM : R;
4810 FDIV : C(17);
4811 %}
4812
4813 // Floating Point Move/Negate/Abs Float
4814 pipe_class faddF_reg(regF dst, regF src) %{
4815 single_instruction;
4816 dst : W(write);
4817 src : E(read);
4818 FA : R(1);
4819 %}
4820
4821 // Floating Point Move/Negate/Abs Double
4822 pipe_class faddD_reg(regD dst, regD src) %{
4823 single_instruction;
4824 dst : W(write);
4825 src : E(read);
4826 FA : R;
4827 %}
4828
4829 // Floating Point Convert F->D
4830 pipe_class fcvtF2D(regD dst, regF src) %{
4831 single_instruction;
4832 dst : X(write);
4833 src : E(read);
4834 FA : R;
4835 %}
4836
4837 // Floating Point Convert I->D
4838 pipe_class fcvtI2D(regD dst, regF src) %{
4839 single_instruction;
4840 dst : X(write);
4841 src : E(read);
4842 FA : R;
4843 %}
4844
4845 // Floating Point Convert LHi->D
4846 pipe_class fcvtLHi2D(regD dst, regD src) %{
4847 single_instruction;
4848 dst : X(write);
4849 src : E(read);
4850 FA : R;
4851 %}
4852
4853 // Floating Point Convert L->D
4854 pipe_class fcvtL2D(regD dst, regF src) %{
4855 single_instruction;
4856 dst : X(write);
4857 src : E(read);
4858 FA : R;
4859 %}
4860
4861 // Floating Point Convert L->F
4862 pipe_class fcvtL2F(regD dst, regF src) %{
4863 single_instruction;
4864 dst : X(write);
4865 src : E(read);
4866 FA : R;
4867 %}
4868
4869 // Floating Point Convert D->F
4870 pipe_class fcvtD2F(regD dst, regF src) %{
4871 single_instruction;
4872 dst : X(write);
4873 src : E(read);
4874 FA : R;
4875 %}
4876
4877 // Floating Point Convert I->L
4878 pipe_class fcvtI2L(regD dst, regF src) %{
4879 single_instruction;
4880 dst : X(write);
4881 src : E(read);
4882 FA : R;
4883 %}
4884
4885 // Floating Point Convert D->F
4886 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4887 instruction_count(1); multiple_bundles;
4888 dst : X(write)+6;
4889 src : E(read);
4890 FA : R;
4891 %}
4892
4893 // Floating Point Convert D->L
4894 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4895 instruction_count(1); multiple_bundles;
4896 dst : X(write)+6;
4897 src : E(read);
4898 FA : R;
4899 %}
4900
4901 // Floating Point Convert F->I
4902 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4903 instruction_count(1); multiple_bundles;
4904 dst : X(write)+6;
4905 src : E(read);
4906 FA : R;
4907 %}
4908
4909 // Floating Point Convert F->L
4910 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4911 instruction_count(1); multiple_bundles;
4912 dst : X(write)+6;
4913 src : E(read);
4914 FA : R;
4915 %}
4916
4917 // Floating Point Convert I->F
4918 pipe_class fcvtI2F(regF dst, regF src) %{
4919 single_instruction;
4920 dst : X(write);
4921 src : E(read);
4922 FA : R;
4923 %}
4924
4925 // Floating Point Compare
4926 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4927 single_instruction;
4928 cr : X(write);
4929 src1 : E(read);
4930 src2 : E(read);
4931 FA : R;
4932 %}
4933
4934 // Floating Point Compare
4935 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4936 single_instruction;
4937 cr : X(write);
4938 src1 : E(read);
4939 src2 : E(read);
4940 FA : R;
4941 %}
4942
4943 // Floating Add Nop
4944 pipe_class fadd_nop() %{
4945 single_instruction;
4946 FA : R;
4947 %}
4948
4949 // Integer Store to Memory
4950 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4951 single_instruction;
4952 mem : R(read);
4953 src : C(read);
4954 MS : R;
4955 %}
4956
4957 // Integer Store to Memory
4958 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4959 single_instruction;
4960 mem : R(read);
4961 src : C(read);
4962 MS : R;
4963 %}
4964
4965 // Integer Store Zero to Memory
4966 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4967 single_instruction;
4968 mem : R(read);
4969 MS : R;
4970 %}
4971
4972 // Special Stack Slot Store
4973 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4974 single_instruction;
4975 stkSlot : R(read);
4976 src : C(read);
4977 MS : R;
4978 %}
4979
4980 // Special Stack Slot Store
4981 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4982 instruction_count(2); multiple_bundles;
4983 stkSlot : R(read);
4984 src : C(read);
4985 MS : R(2);
4986 %}
4987
4988 // Float Store
4989 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4990 single_instruction;
4991 mem : R(read);
4992 src : C(read);
4993 MS : R;
4994 %}
4995
4996 // Float Store
4997 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4998 single_instruction;
4999 mem : R(read);
5000 MS : R;
5001 %}
5002
5003 // Double Store
5004 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5005 instruction_count(1);
5006 mem : R(read);
5007 src : C(read);
5008 MS : R;
5009 %}
5010
5011 // Double Store
5012 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5013 single_instruction;
5014 mem : R(read);
5015 MS : R;
5016 %}
5017
5018 // Special Stack Slot Float Store
5019 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5020 single_instruction;
5021 stkSlot : R(read);
5022 src : C(read);
5023 MS : R;
5024 %}
5025
5026 // Special Stack Slot Double Store
5027 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5028 single_instruction;
5029 stkSlot : R(read);
5030 src : C(read);
5031 MS : R;
5032 %}
5033
5034 // Integer Load (when sign bit propagation not needed)
5035 pipe_class iload_mem(iRegI dst, memory mem) %{
5036 single_instruction;
5037 mem : R(read);
5038 dst : C(write);
5039 MS : R;
5040 %}
5041
5042 // Integer Load from stack operand
5043 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5044 single_instruction;
5045 mem : R(read);
5046 dst : C(write);
5047 MS : R;
5048 %}
5049
5050 // Integer Load (when sign bit propagation or masking is needed)
5051 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5052 single_instruction;
5053 mem : R(read);
5054 dst : M(write);
5055 MS : R;
5056 %}
5057
5058 // Float Load
5059 pipe_class floadF_mem(regF dst, memory mem) %{
5060 single_instruction;
5061 mem : R(read);
5062 dst : M(write);
5063 MS : R;
5064 %}
5065
5066 // Float Load
5067 pipe_class floadD_mem(regD dst, memory mem) %{
5068 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5069 mem : R(read);
5070 dst : M(write);
5071 MS : R;
5072 %}
5073
5074 // Float Load
5075 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5076 single_instruction;
5077 stkSlot : R(read);
5078 dst : M(write);
5079 MS : R;
5080 %}
5081
5082 // Float Load
5083 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5084 single_instruction;
5085 stkSlot : R(read);
5086 dst : M(write);
5087 MS : R;
5088 %}
5089
5090 // Memory Nop
5091 pipe_class mem_nop() %{
5092 single_instruction;
5093 MS : R;
5094 %}
5095
5096 pipe_class sethi(iRegP dst, immI src) %{
5097 single_instruction;
5098 dst : E(write);
5099 IALU : R;
5100 %}
5101
5102 pipe_class loadPollP(iRegP poll) %{
5103 single_instruction;
5104 poll : R(read);
5105 MS : R;
5106 %}
5107
5108 pipe_class br(Universe br, label labl) %{
5109 single_instruction_with_delay_slot;
5110 BR : R;
5111 %}
5112
5113 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5114 single_instruction_with_delay_slot;
5115 cr : E(read);
5116 BR : R;
5117 %}
5118
5119 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5120 single_instruction_with_delay_slot;
5121 op1 : E(read);
5122 BR : R;
5123 MS : R;
5124 %}
5125
5126 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5127 single_instruction_with_delay_slot;
5128 cr : E(read);
5129 BR : R;
5130 %}
5131
5132 pipe_class br_nop() %{
5133 single_instruction;
5134 BR : R;
5135 %}
5136
5137 pipe_class simple_call(method meth) %{
5138 instruction_count(2); multiple_bundles; force_serialization;
5139 fixed_latency(100);
5140 BR : R(1);
5141 MS : R(1);
5142 A0 : R(1);
5143 %}
5144
5145 pipe_class compiled_call(method meth) %{
5146 instruction_count(1); multiple_bundles; force_serialization;
5147 fixed_latency(100);
5148 MS : R(1);
5149 %}
5150
5151 pipe_class call(method meth) %{
5152 instruction_count(0); multiple_bundles; force_serialization;
5153 fixed_latency(100);
5154 %}
5155
5156 pipe_class tail_call(Universe ignore, label labl) %{
5157 single_instruction; has_delay_slot;
5158 fixed_latency(100);
5159 BR : R(1);
5160 MS : R(1);
5161 %}
5162
5163 pipe_class ret(Universe ignore) %{
5164 single_instruction; has_delay_slot;
5165 BR : R(1);
5166 MS : R(1);
5167 %}
5168
5169 pipe_class ret_poll(g3RegP poll) %{
5170 instruction_count(3); has_delay_slot;
5171 poll : E(read);
5172 MS : R;
5173 %}
5174
5175 // The real do-nothing guy
5176 pipe_class empty( ) %{
5177 instruction_count(0);
5178 %}
5179
5180 pipe_class long_memory_op() %{
5181 instruction_count(0); multiple_bundles; force_serialization;
5182 fixed_latency(25);
5183 MS : R(1);
5184 %}
5185
5186 // Check-cast
5187 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5188 array : R(read);
5189 match : R(read);
5190 IALU : R(2);
5191 BR : R(2);
5192 MS : R;
5193 %}
5194
5195 // Convert FPU flags into +1,0,-1
5196 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5197 src1 : E(read);
5198 src2 : E(read);
5199 dst : E(write);
5200 FA : R;
5201 MS : R(2);
5202 BR : R(2);
5203 %}
5204
5205 // Compare for p < q, and conditionally add y
5206 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5207 p : E(read);
5208 q : E(read);
5209 y : E(read);
5210 IALU : R(3)
5211 %}
5212
5213 // Perform a compare, then move conditionally in a branch delay slot.
5214 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5215 src2 : E(read);
5216 srcdst : E(read);
5217 IALU : R;
5218 BR : R;
5219 %}
5220
5221 // Define the class for the Nop node
5222 define %{
5223 MachNop = ialu_nop;
5224 %}
5225
5226 %}
5227
5228 //----------INSTRUCTIONS-------------------------------------------------------
5229
5230 //------------Special Stack Slot instructions - no match rules-----------------
5231 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5232 // No match rule to avoid chain rule match.
5233 effect(DEF dst, USE src);
5234 ins_cost(MEMORY_REF_COST);
5235 size(4);
5236 format %{ "LDF $src,$dst\t! stkI to regF" %}
5237 opcode(Assembler::ldf_op3);
5238 ins_encode(simple_form3_mem_reg(src, dst));
5239 ins_pipe(floadF_stk);
5240 %}
5241
5242 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5243 // No match rule to avoid chain rule match.
5244 effect(DEF dst, USE src);
5245 ins_cost(MEMORY_REF_COST);
5246 size(4);
5247 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5248 opcode(Assembler::lddf_op3);
5249 ins_encode(simple_form3_mem_reg(src, dst));
5250 ins_pipe(floadD_stk);
5251 %}
5252
5253 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5254 // No match rule to avoid chain rule match.
5255 effect(DEF dst, USE src);
5256 ins_cost(MEMORY_REF_COST);
5257 size(4);
5258 format %{ "STF $src,$dst\t! regF to stkI" %}
5259 opcode(Assembler::stf_op3);
5260 ins_encode(simple_form3_mem_reg(dst, src));
5261 ins_pipe(fstoreF_stk_reg);
5262 %}
5263
5264 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5265 // No match rule to avoid chain rule match.
5266 effect(DEF dst, USE src);
5267 ins_cost(MEMORY_REF_COST);
5268 size(4);
5269 format %{ "STDF $src,$dst\t! regD to stkL" %}
5270 opcode(Assembler::stdf_op3);
5271 ins_encode(simple_form3_mem_reg(dst, src));
5272 ins_pipe(fstoreD_stk_reg);
5273 %}
5274
5275 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5276 effect(DEF dst, USE src);
5277 ins_cost(MEMORY_REF_COST*2);
5278 size(8);
5279 format %{ "STW $src,$dst.hi\t! long\n\t"
5280 "STW R_G0,$dst.lo" %}
5281 opcode(Assembler::stw_op3);
5282 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5283 ins_pipe(lstoreI_stk_reg);
5284 %}
5285
5286 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5287 // No match rule to avoid chain rule match.
5288 effect(DEF dst, USE src);
5289 ins_cost(MEMORY_REF_COST);
5290 size(4);
5291 format %{ "STX $src,$dst\t! regL to stkD" %}
5292 opcode(Assembler::stx_op3);
5293 ins_encode(simple_form3_mem_reg( dst, src ) );
5294 ins_pipe(istore_stk_reg);
5295 %}
5296
5297 //---------- Chain stack slots between similar types --------
5298
5299 // Load integer from stack slot
5300 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5301 match(Set dst src);
5302 ins_cost(MEMORY_REF_COST);
5303
5304 size(4);
5305 format %{ "LDUW $src,$dst\t!stk" %}
5306 opcode(Assembler::lduw_op3);
5307 ins_encode(simple_form3_mem_reg( src, dst ) );
5308 ins_pipe(iload_mem);
5309 %}
5310
5311 // Store integer to stack slot
5312 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5313 match(Set dst src);
5314 ins_cost(MEMORY_REF_COST);
5315
5316 size(4);
5317 format %{ "STW $src,$dst\t!stk" %}
5318 opcode(Assembler::stw_op3);
5319 ins_encode(simple_form3_mem_reg( dst, src ) );
5320 ins_pipe(istore_mem_reg);
5321 %}
5322
5323 // Load long from stack slot
5324 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5325 match(Set dst src);
5326
5327 ins_cost(MEMORY_REF_COST);
5328 size(4);
5329 format %{ "LDX $src,$dst\t! long" %}
5330 opcode(Assembler::ldx_op3);
5331 ins_encode(simple_form3_mem_reg( src, dst ) );
5332 ins_pipe(iload_mem);
5333 %}
5334
5335 // Store long to stack slot
5336 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5337 match(Set dst src);
5338
5339 ins_cost(MEMORY_REF_COST);
5340 size(4);
5341 format %{ "STX $src,$dst\t! long" %}
5342 opcode(Assembler::stx_op3);
5343 ins_encode(simple_form3_mem_reg( dst, src ) );
5344 ins_pipe(istore_mem_reg);
5345 %}
5346
5347 #ifdef _LP64
5348 // Load pointer from stack slot, 64-bit encoding
5349 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5350 match(Set dst src);
5351 ins_cost(MEMORY_REF_COST);
5352 size(4);
5353 format %{ "LDX $src,$dst\t!ptr" %}
5354 opcode(Assembler::ldx_op3);
5355 ins_encode(simple_form3_mem_reg( src, dst ) );
5356 ins_pipe(iload_mem);
5357 %}
5358
5359 // Store pointer to stack slot
5360 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5361 match(Set dst src);
5362 ins_cost(MEMORY_REF_COST);
5363 size(4);
5364 format %{ "STX $src,$dst\t!ptr" %}
5365 opcode(Assembler::stx_op3);
5366 ins_encode(simple_form3_mem_reg( dst, src ) );
5367 ins_pipe(istore_mem_reg);
5368 %}
5369 #else // _LP64
5370 // Load pointer from stack slot, 32-bit encoding
5371 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5372 match(Set dst src);
5373 ins_cost(MEMORY_REF_COST);
5374 format %{ "LDUW $src,$dst\t!ptr" %}
5375 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5376 ins_encode(simple_form3_mem_reg( src, dst ) );
5377 ins_pipe(iload_mem);
5378 %}
5379
5380 // Store pointer to stack slot
5381 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5382 match(Set dst src);
5383 ins_cost(MEMORY_REF_COST);
5384 format %{ "STW $src,$dst\t!ptr" %}
5385 opcode(Assembler::stw_op3, Assembler::ldst_op);
5386 ins_encode(simple_form3_mem_reg( dst, src ) );
5387 ins_pipe(istore_mem_reg);
5388 %}
5389 #endif // _LP64
5390
5391 //------------Special Nop instructions for bundling - no match rules-----------
5392 // Nop using the A0 functional unit
5393 instruct Nop_A0() %{
5394 ins_cost(0);
5395
5396 format %{ "NOP ! Alu Pipeline" %}
5397 opcode(Assembler::or_op3, Assembler::arith_op);
5398 ins_encode( form2_nop() );
5399 ins_pipe(ialu_nop_A0);
5400 %}
5401
5402 // Nop using the A1 functional unit
5403 instruct Nop_A1( ) %{
5404 ins_cost(0);
5405
5406 format %{ "NOP ! Alu Pipeline" %}
5407 opcode(Assembler::or_op3, Assembler::arith_op);
5408 ins_encode( form2_nop() );
5409 ins_pipe(ialu_nop_A1);
5410 %}
5411
5412 // Nop using the memory functional unit
5413 instruct Nop_MS( ) %{
5414 ins_cost(0);
5415
5416 format %{ "NOP ! Memory Pipeline" %}
5417 ins_encode( emit_mem_nop );
5418 ins_pipe(mem_nop);
5419 %}
5420
5421 // Nop using the floating add functional unit
5422 instruct Nop_FA( ) %{
5423 ins_cost(0);
5424
5425 format %{ "NOP ! Floating Add Pipeline" %}
5426 ins_encode( emit_fadd_nop );
5427 ins_pipe(fadd_nop);
5428 %}
5429
5430 // Nop using the branch functional unit
5431 instruct Nop_BR( ) %{
5432 ins_cost(0);
5433
5434 format %{ "NOP ! Branch Pipeline" %}
5435 ins_encode( emit_br_nop );
5436 ins_pipe(br_nop);
5437 %}
5438
5439 //----------Load/Store/Move Instructions---------------------------------------
5440 //----------Load Instructions--------------------------------------------------
5441 // Load Byte (8bit signed)
5442 instruct loadB(iRegI dst, memory mem) %{
5443 match(Set dst (LoadB mem));
5444 ins_cost(MEMORY_REF_COST);
5445
5446 size(4);
5447 format %{ "LDSB $mem,$dst\t! byte" %}
5448 ins_encode %{
5449 __ ldsb($mem$$Address, $dst$$Register);
5450 %}
5451 ins_pipe(iload_mask_mem);
5452 %}
5453
5454 // Load Byte (8bit signed) into a Long Register
5455 instruct loadB2L(iRegL dst, memory mem) %{
5456 match(Set dst (ConvI2L (LoadB mem)));
5457 ins_cost(MEMORY_REF_COST);
5458
5459 size(4);
5460 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5461 ins_encode %{
5462 __ ldsb($mem$$Address, $dst$$Register);
5463 %}
5464 ins_pipe(iload_mask_mem);
5465 %}
5466
5467 // Load Unsigned Byte (8bit UNsigned) into an int reg
5468 instruct loadUB(iRegI dst, memory mem) %{
5469 match(Set dst (LoadUB mem));
5470 ins_cost(MEMORY_REF_COST);
5471
5472 size(4);
5473 format %{ "LDUB $mem,$dst\t! ubyte" %}
5474 ins_encode %{
5475 __ ldub($mem$$Address, $dst$$Register);
5476 %}
5477 ins_pipe(iload_mem);
5478 %}
5479
5480 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5481 instruct loadUB2L(iRegL dst, memory mem) %{
5482 match(Set dst (ConvI2L (LoadUB mem)));
5483 ins_cost(MEMORY_REF_COST);
5484
5485 size(4);
5486 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5487 ins_encode %{
5488 __ ldub($mem$$Address, $dst$$Register);
5489 %}
5490 ins_pipe(iload_mem);
5491 %}
5492
5493 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5494 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5495 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5496 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5497
5498 size(2*4);
5499 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5500 "AND $dst,$mask,$dst" %}
5501 ins_encode %{
5502 __ ldub($mem$$Address, $dst$$Register);
5503 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5504 %}
5505 ins_pipe(iload_mem);
5506 %}
5507
5508 // Load Short (16bit signed)
5509 instruct loadS(iRegI dst, memory mem) %{
5510 match(Set dst (LoadS mem));
5511 ins_cost(MEMORY_REF_COST);
5512
5513 size(4);
5514 format %{ "LDSH $mem,$dst\t! short" %}
5515 ins_encode %{
5516 __ ldsh($mem$$Address, $dst$$Register);
5517 %}
5518 ins_pipe(iload_mask_mem);
5519 %}
5520
5521 // Load Short (16 bit signed) to Byte (8 bit signed)
5522 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5523 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5524 ins_cost(MEMORY_REF_COST);
5525
5526 size(4);
5527
5528 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5529 ins_encode %{
5530 __ ldsb($mem$$Address, $dst$$Register, 1);
5531 %}
5532 ins_pipe(iload_mask_mem);
5533 %}
5534
5535 // Load Short (16bit signed) into a Long Register
5536 instruct loadS2L(iRegL dst, memory mem) %{
5537 match(Set dst (ConvI2L (LoadS mem)));
5538 ins_cost(MEMORY_REF_COST);
5539
5540 size(4);
5541 format %{ "LDSH $mem,$dst\t! short -> long" %}
5542 ins_encode %{
5543 __ ldsh($mem$$Address, $dst$$Register);
5544 %}
5545 ins_pipe(iload_mask_mem);
5546 %}
5547
5548 // Load Unsigned Short/Char (16bit UNsigned)
5549 instruct loadUS(iRegI dst, memory mem) %{
5550 match(Set dst (LoadUS mem));
5551 ins_cost(MEMORY_REF_COST);
5552
5553 size(4);
5554 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5555 ins_encode %{
5556 __ lduh($mem$$Address, $dst$$Register);
5557 %}
5558 ins_pipe(iload_mem);
5559 %}
5560
5561 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5562 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5563 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5564 ins_cost(MEMORY_REF_COST);
5565
5566 size(4);
5567 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5568 ins_encode %{
5569 __ ldsb($mem$$Address, $dst$$Register, 1);
5570 %}
5571 ins_pipe(iload_mask_mem);
5572 %}
5573
5574 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5575 instruct loadUS2L(iRegL dst, memory mem) %{
5576 match(Set dst (ConvI2L (LoadUS mem)));
5577 ins_cost(MEMORY_REF_COST);
5578
5579 size(4);
5580 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5581 ins_encode %{
5582 __ lduh($mem$$Address, $dst$$Register);
5583 %}
5584 ins_pipe(iload_mem);
5585 %}
5586
5587 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5588 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5589 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5590 ins_cost(MEMORY_REF_COST);
5591
5592 size(4);
5593 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5594 ins_encode %{
5595 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5596 %}
5597 ins_pipe(iload_mem);
5598 %}
5599
5600 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5601 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5602 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5603 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5604
5605 size(2*4);
5606 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5607 "AND $dst,$mask,$dst" %}
5608 ins_encode %{
5609 Register Rdst = $dst$$Register;
5610 __ lduh($mem$$Address, Rdst);
5611 __ and3(Rdst, $mask$$constant, Rdst);
5612 %}
5613 ins_pipe(iload_mem);
5614 %}
5615
5616 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5617 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5618 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5619 effect(TEMP dst, TEMP tmp);
5620 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5621
5622 size((3+1)*4); // set may use two instructions.
5623 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5624 "SET $mask,$tmp\n\t"
5625 "AND $dst,$tmp,$dst" %}
5626 ins_encode %{
5627 Register Rdst = $dst$$Register;
5628 Register Rtmp = $tmp$$Register;
5629 __ lduh($mem$$Address, Rdst);
5630 __ set($mask$$constant, Rtmp);
5631 __ and3(Rdst, Rtmp, Rdst);
5632 %}
5633 ins_pipe(iload_mem);
5634 %}
5635
5636 // Load Integer
5637 instruct loadI(iRegI dst, memory mem) %{
5638 match(Set dst (LoadI mem));
5639 ins_cost(MEMORY_REF_COST);
5640
5641 size(4);
5642 format %{ "LDUW $mem,$dst\t! int" %}
5643 ins_encode %{
5644 __ lduw($mem$$Address, $dst$$Register);
5645 %}
5646 ins_pipe(iload_mem);
5647 %}
5648
5649 // Load Integer to Byte (8 bit signed)
5650 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5651 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5652 ins_cost(MEMORY_REF_COST);
5653
5654 size(4);
5655
5656 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5657 ins_encode %{
5658 __ ldsb($mem$$Address, $dst$$Register, 3);
5659 %}
5660 ins_pipe(iload_mask_mem);
5661 %}
5662
5663 // Load Integer to Unsigned Byte (8 bit UNsigned)
5664 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5665 match(Set dst (AndI (LoadI mem) mask));
5666 ins_cost(MEMORY_REF_COST);
5667
5668 size(4);
5669
5670 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5671 ins_encode %{
5672 __ ldub($mem$$Address, $dst$$Register, 3);
5673 %}
5674 ins_pipe(iload_mask_mem);
5675 %}
5676
5677 // Load Integer to Short (16 bit signed)
5678 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5679 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5680 ins_cost(MEMORY_REF_COST);
5681
5682 size(4);
5683
5684 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5685 ins_encode %{
5686 __ ldsh($mem$$Address, $dst$$Register, 2);
5687 %}
5688 ins_pipe(iload_mask_mem);
5689 %}
5690
5691 // Load Integer to Unsigned Short (16 bit UNsigned)
5692 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5693 match(Set dst (AndI (LoadI mem) mask));
5694 ins_cost(MEMORY_REF_COST);
5695
5696 size(4);
5697
5698 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5699 ins_encode %{
5700 __ lduh($mem$$Address, $dst$$Register, 2);
5701 %}
5702 ins_pipe(iload_mask_mem);
5703 %}
5704
5705 // Load Integer into a Long Register
5706 instruct loadI2L(iRegL dst, memory mem) %{
5707 match(Set dst (ConvI2L (LoadI mem)));
5708 ins_cost(MEMORY_REF_COST);
5709
5710 size(4);
5711 format %{ "LDSW $mem,$dst\t! int -> long" %}
5712 ins_encode %{
5713 __ ldsw($mem$$Address, $dst$$Register);
5714 %}
5715 ins_pipe(iload_mask_mem);
5716 %}
5717
5718 // Load Integer with mask 0xFF into a Long Register
5719 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5720 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5721 ins_cost(MEMORY_REF_COST);
5722
5723 size(4);
5724 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5725 ins_encode %{
5726 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5727 %}
5728 ins_pipe(iload_mem);
5729 %}
5730
5731 // Load Integer with mask 0xFFFF into a Long Register
5732 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5733 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5734 ins_cost(MEMORY_REF_COST);
5735
5736 size(4);
5737 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5738 ins_encode %{
5739 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5740 %}
5741 ins_pipe(iload_mem);
5742 %}
5743
5744 // Load Integer with a 13-bit mask into a Long Register
5745 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5746 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5747 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5748
5749 size(2*4);
5750 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5751 "AND $dst,$mask,$dst" %}
5752 ins_encode %{
5753 Register Rdst = $dst$$Register;
5754 __ lduw($mem$$Address, Rdst);
5755 __ and3(Rdst, $mask$$constant, Rdst);
5756 %}
5757 ins_pipe(iload_mem);
5758 %}
5759
5760 // Load Integer with a 32-bit mask into a Long Register
5761 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5762 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5763 effect(TEMP dst, TEMP tmp);
5764 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5765
5766 size((3+1)*4); // set may use two instructions.
5767 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5768 "SET $mask,$tmp\n\t"
5769 "AND $dst,$tmp,$dst" %}
5770 ins_encode %{
5771 Register Rdst = $dst$$Register;
5772 Register Rtmp = $tmp$$Register;
5773 __ lduw($mem$$Address, Rdst);
5774 __ set($mask$$constant, Rtmp);
5775 __ and3(Rdst, Rtmp, Rdst);
5776 %}
5777 ins_pipe(iload_mem);
5778 %}
5779
5780 // Load Unsigned Integer into a Long Register
5781 instruct loadUI2L(iRegL dst, memory mem) %{
5782 match(Set dst (LoadUI2L mem));
5783 ins_cost(MEMORY_REF_COST);
5784
5785 size(4);
5786 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5787 ins_encode %{
5788 __ lduw($mem$$Address, $dst$$Register);
5789 %}
5790 ins_pipe(iload_mem);
5791 %}
5792
5793 // Load Long - aligned
5794 instruct loadL(iRegL dst, memory mem ) %{
5795 match(Set dst (LoadL mem));
5796 ins_cost(MEMORY_REF_COST);
5797
5798 size(4);
5799 format %{ "LDX $mem,$dst\t! long" %}
5800 ins_encode %{
5801 __ ldx($mem$$Address, $dst$$Register);
5802 %}
5803 ins_pipe(iload_mem);
5804 %}
5805
5806 // Load Long - UNaligned
5807 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5808 match(Set dst (LoadL_unaligned mem));
5809 effect(KILL tmp);
5810 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5811 size(16);
5812 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5813 "\tLDUW $mem ,$dst\n"
5814 "\tSLLX #32, $dst, $dst\n"
5815 "\tOR $dst, R_O7, $dst" %}
5816 opcode(Assembler::lduw_op3);
5817 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5818 ins_pipe(iload_mem);
5819 %}
5820
5821 // Load Aligned Packed Byte into a Double Register
5822 instruct loadA8B(regD dst, memory mem) %{
5823 match(Set dst (Load8B mem));
5824 ins_cost(MEMORY_REF_COST);
5825 size(4);
5826 format %{ "LDDF $mem,$dst\t! packed8B" %}
5827 opcode(Assembler::lddf_op3);
5828 ins_encode(simple_form3_mem_reg( mem, dst ) );
5829 ins_pipe(floadD_mem);
5830 %}
5831
5832 // Load Aligned Packed Char into a Double Register
5833 instruct loadA4C(regD dst, memory mem) %{
5834 match(Set dst (Load4C mem));
5835 ins_cost(MEMORY_REF_COST);
5836 size(4);
5837 format %{ "LDDF $mem,$dst\t! packed4C" %}
5838 opcode(Assembler::lddf_op3);
5839 ins_encode(simple_form3_mem_reg( mem, dst ) );
5840 ins_pipe(floadD_mem);
5841 %}
5842
5843 // Load Aligned Packed Short into a Double Register
5844 instruct loadA4S(regD dst, memory mem) %{
5845 match(Set dst (Load4S mem));
5846 ins_cost(MEMORY_REF_COST);
5847 size(4);
5848 format %{ "LDDF $mem,$dst\t! packed4S" %}
5849 opcode(Assembler::lddf_op3);
5850 ins_encode(simple_form3_mem_reg( mem, dst ) );
5851 ins_pipe(floadD_mem);
5852 %}
5853
5854 // Load Aligned Packed Int into a Double Register
5855 instruct loadA2I(regD dst, memory mem) %{
5856 match(Set dst (Load2I mem));
5857 ins_cost(MEMORY_REF_COST);
5858 size(4);
5859 format %{ "LDDF $mem,$dst\t! packed2I" %}
5860 opcode(Assembler::lddf_op3);
5861 ins_encode(simple_form3_mem_reg( mem, dst ) );
5862 ins_pipe(floadD_mem);
5863 %}
5864
5865 // Load Range
5866 instruct loadRange(iRegI dst, memory mem) %{
5867 match(Set dst (LoadRange mem));
5868 ins_cost(MEMORY_REF_COST);
5869
5870 size(4);
5871 format %{ "LDUW $mem,$dst\t! range" %}
5872 opcode(Assembler::lduw_op3);
5873 ins_encode(simple_form3_mem_reg( mem, dst ) );
5874 ins_pipe(iload_mem);
5875 %}
5876
5877 // Load Integer into %f register (for fitos/fitod)
5878 instruct loadI_freg(regF dst, memory mem) %{
5879 match(Set dst (LoadI mem));
5880 ins_cost(MEMORY_REF_COST);
5881 size(4);
5882
5883 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5884 opcode(Assembler::ldf_op3);
5885 ins_encode(simple_form3_mem_reg( mem, dst ) );
5886 ins_pipe(floadF_mem);
5887 %}
5888
5889 // Load Pointer
5890 instruct loadP(iRegP dst, memory mem) %{
5891 match(Set dst (LoadP mem));
5892 ins_cost(MEMORY_REF_COST);
5893 size(4);
5894
5895 #ifndef _LP64
5896 format %{ "LDUW $mem,$dst\t! ptr" %}
5897 ins_encode %{
5898 __ lduw($mem$$Address, $dst$$Register);
5899 %}
5900 #else
5901 format %{ "LDX $mem,$dst\t! ptr" %}
5902 ins_encode %{
5903 __ ldx($mem$$Address, $dst$$Register);
5904 %}
5905 #endif
5906 ins_pipe(iload_mem);
5907 %}
5908
5909 // Load Compressed Pointer
5910 instruct loadN(iRegN dst, memory mem) %{
5911 match(Set dst (LoadN mem));
5912 ins_cost(MEMORY_REF_COST);
5913 size(4);
5914
5915 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5916 ins_encode %{
5917 __ lduw($mem$$Address, $dst$$Register);
5918 %}
5919 ins_pipe(iload_mem);
5920 %}
5921
5922 // Load Klass Pointer
5923 instruct loadKlass(iRegP dst, memory mem) %{
5924 match(Set dst (LoadKlass mem));
5925 ins_cost(MEMORY_REF_COST);
5926 size(4);
5927
5928 #ifndef _LP64
5929 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5930 ins_encode %{
5931 __ lduw($mem$$Address, $dst$$Register);
5932 %}
5933 #else
5934 format %{ "LDX $mem,$dst\t! klass ptr" %}
5935 ins_encode %{
5936 __ ldx($mem$$Address, $dst$$Register);
5937 %}
5938 #endif
5939 ins_pipe(iload_mem);
5940 %}
5941
5942 // Load narrow Klass Pointer
5943 instruct loadNKlass(iRegN dst, memory mem) %{
5944 match(Set dst (LoadNKlass mem));
5945 ins_cost(MEMORY_REF_COST);
5946 size(4);
5947
5948 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5949 ins_encode %{
5950 __ lduw($mem$$Address, $dst$$Register);
5951 %}
5952 ins_pipe(iload_mem);
5953 %}
5954
5955 // Load Double
5956 instruct loadD(regD dst, memory mem) %{
5957 match(Set dst (LoadD mem));
5958 ins_cost(MEMORY_REF_COST);
5959
5960 size(4);
5961 format %{ "LDDF $mem,$dst" %}
5962 opcode(Assembler::lddf_op3);
5963 ins_encode(simple_form3_mem_reg( mem, dst ) );
5964 ins_pipe(floadD_mem);
5965 %}
5966
5967 // Load Double - UNaligned
5968 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5969 match(Set dst (LoadD_unaligned mem));
5970 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5971 size(8);
5972 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5973 "\tLDF $mem+4,$dst.lo\t!" %}
5974 opcode(Assembler::ldf_op3);
5975 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5976 ins_pipe(iload_mem);
5977 %}
5978
5979 // Load Float
5980 instruct loadF(regF dst, memory mem) %{
5981 match(Set dst (LoadF mem));
5982 ins_cost(MEMORY_REF_COST);
5983
5984 size(4);
5985 format %{ "LDF $mem,$dst" %}
5986 opcode(Assembler::ldf_op3);
5987 ins_encode(simple_form3_mem_reg( mem, dst ) );
5988 ins_pipe(floadF_mem);
5989 %}
5990
5991 // Load Constant
5992 instruct loadConI( iRegI dst, immI src ) %{
5993 match(Set dst src);
5994 ins_cost(DEFAULT_COST * 3/2);
5995 format %{ "SET $src,$dst" %}
5996 ins_encode( Set32(src, dst) );
5997 ins_pipe(ialu_hi_lo_reg);
5998 %}
5999
6000 instruct loadConI13( iRegI dst, immI13 src ) %{
6001 match(Set dst src);
6002
6003 size(4);
6004 format %{ "MOV $src,$dst" %}
6005 ins_encode( Set13( src, dst ) );
6006 ins_pipe(ialu_imm);
6007 %}
6008
6009 instruct loadConP(iRegP dst, immP src) %{
6010 match(Set dst src);
6011 ins_cost(DEFAULT_COST * 3/2);
6012 format %{ "SET $src,$dst\t!ptr" %}
6013 // This rule does not use "expand" unlike loadConI because then
6014 // the result type is not known to be an Oop. An ADLC
6015 // enhancement will be needed to make that work - not worth it!
6016
6017 ins_encode( SetPtr( src, dst ) );
6018 ins_pipe(loadConP);
6019
6020 %}
6021
6022 instruct loadConP0(iRegP dst, immP0 src) %{
6023 match(Set dst src);
6024
6025 size(4);
6026 format %{ "CLR $dst\t!ptr" %}
6027 ins_encode( SetNull( dst ) );
6028 ins_pipe(ialu_imm);
6029 %}
6030
6031 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6032 match(Set dst src);
6033 ins_cost(DEFAULT_COST);
6034 format %{ "SET $src,$dst\t!ptr" %}
6035 ins_encode %{
6036 AddressLiteral polling_page(os::get_polling_page());
6037 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6038 %}
6039 ins_pipe(loadConP_poll);
6040 %}
6041
6042 instruct loadConN0(iRegN dst, immN0 src) %{
6043 match(Set dst src);
6044
6045 size(4);
6046 format %{ "CLR $dst\t! compressed NULL ptr" %}
6047 ins_encode( SetNull( dst ) );
6048 ins_pipe(ialu_imm);
6049 %}
6050
6051 instruct loadConN(iRegN dst, immN src) %{
6052 match(Set dst src);
6053 ins_cost(DEFAULT_COST * 3/2);
6054 format %{ "SET $src,$dst\t! compressed ptr" %}
6055 ins_encode %{
6056 Register dst = $dst$$Register;
6057 __ set_narrow_oop((jobject)$src$$constant, dst);
6058 %}
6059 ins_pipe(ialu_hi_lo_reg);
6060 %}
6061
6062 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
6063 // %%% maybe this should work like loadConD
6064 match(Set dst src);
6065 effect(KILL tmp);
6066 ins_cost(DEFAULT_COST * 4);
6067 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
6068 ins_encode( LdImmL(src, dst, tmp) );
6069 ins_pipe(loadConL);
6070 %}
6071
6072 instruct loadConL0( iRegL dst, immL0 src ) %{
6073 match(Set dst src);
6074 ins_cost(DEFAULT_COST);
6075 size(4);
6076 format %{ "CLR $dst\t! long" %}
6077 ins_encode( Set13( src, dst ) );
6078 ins_pipe(ialu_imm);
6079 %}
6080
6081 instruct loadConL13( iRegL dst, immL13 src ) %{
6082 match(Set dst src);
6083 ins_cost(DEFAULT_COST * 2);
6084
6085 size(4);
6086 format %{ "MOV $src,$dst\t! long" %}
6087 ins_encode( Set13( src, dst ) );
6088 ins_pipe(ialu_imm);
6089 %}
6090
6091 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
6092 match(Set dst src);
6093 effect(KILL tmp);
6094
6095 #ifdef _LP64
6096 size(8*4);
6097 #else
6098 size(2*4);
6099 #endif
6100
6101 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
6102 "LDF [$tmp+lo(&$src)],$dst" %}
6103 ins_encode %{
6104 address float_address = __ float_constant($src$$constant);
6105 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6106 AddressLiteral addrlit(float_address, rspec);
6107
6108 __ sethi(addrlit, $tmp$$Register);
6109 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6110 %}
6111 ins_pipe(loadConFD);
6112 %}
6113
6114 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
6115 match(Set dst src);
6116 effect(KILL tmp);
6117
6118 #ifdef _LP64
6119 size(8*4);
6120 #else
6121 size(2*4);
6122 #endif
6123
6124 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
6125 "LDDF [$tmp+lo(&$src)],$dst" %}
6126 ins_encode %{
6127 address double_address = __ double_constant($src$$constant);
6128 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6129 AddressLiteral addrlit(double_address, rspec);
6130
6131 __ sethi(addrlit, $tmp$$Register);
6132 // XXX This is a quick fix for 6833573.
6133 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6134 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
6135 %}
6136 ins_pipe(loadConFD);
6137 %}
6138
6139 // Prefetch instructions.
6140 // Must be safe to execute with invalid address (cannot fault).
6141
6142 instruct prefetchr( memory mem ) %{
6143 match( PrefetchRead mem );
6144 ins_cost(MEMORY_REF_COST);
6145
6146 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6147 opcode(Assembler::prefetch_op3);
6148 ins_encode( form3_mem_prefetch_read( mem ) );
6149 ins_pipe(iload_mem);
6150 %}
6151
6152 instruct prefetchw( memory mem ) %{
6153 predicate(AllocatePrefetchStyle != 3 );
6154 match( PrefetchWrite mem );
6155 ins_cost(MEMORY_REF_COST);
6156
6157 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6158 opcode(Assembler::prefetch_op3);
6159 ins_encode( form3_mem_prefetch_write( mem ) );
6160 ins_pipe(iload_mem);
6161 %}
6162
6163 // Use BIS instruction to prefetch.
6164 instruct prefetchw_bis( memory mem ) %{
6165 predicate(AllocatePrefetchStyle == 3);
6166 match( PrefetchWrite mem );
6167 ins_cost(MEMORY_REF_COST);
6168
6169 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6170 ins_encode %{
6171 Register base = as_Register($mem$$base);
6172 int disp = $mem$$disp;
6173 if (disp != 0) {
6174 __ add(base, AllocatePrefetchStepSize, base);
6175 }
6176 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6177 %}
6178 ins_pipe(istore_mem_reg);
6179 %}
6180
6181 //----------Store Instructions-------------------------------------------------
6182 // Store Byte
6183 instruct storeB(memory mem, iRegI src) %{
6184 match(Set mem (StoreB mem src));
6185 ins_cost(MEMORY_REF_COST);
6186
6187 size(4);
6188 format %{ "STB $src,$mem\t! byte" %}
6189 opcode(Assembler::stb_op3);
6190 ins_encode(simple_form3_mem_reg( mem, src ) );
6191 ins_pipe(istore_mem_reg);
6192 %}
6193
6194 instruct storeB0(memory mem, immI0 src) %{
6195 match(Set mem (StoreB mem src));
6196 ins_cost(MEMORY_REF_COST);
6197
6198 size(4);
6199 format %{ "STB $src,$mem\t! byte" %}
6200 opcode(Assembler::stb_op3);
6201 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6202 ins_pipe(istore_mem_zero);
6203 %}
6204
6205 instruct storeCM0(memory mem, immI0 src) %{
6206 match(Set mem (StoreCM mem src));
6207 ins_cost(MEMORY_REF_COST);
6208
6209 size(4);
6210 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6211 opcode(Assembler::stb_op3);
6212 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6213 ins_pipe(istore_mem_zero);
6214 %}
6215
6216 // Store Char/Short
6217 instruct storeC(memory mem, iRegI src) %{
6218 match(Set mem (StoreC mem src));
6219 ins_cost(MEMORY_REF_COST);
6220
6221 size(4);
6222 format %{ "STH $src,$mem\t! short" %}
6223 opcode(Assembler::sth_op3);
6224 ins_encode(simple_form3_mem_reg( mem, src ) );
6225 ins_pipe(istore_mem_reg);
6226 %}
6227
6228 instruct storeC0(memory mem, immI0 src) %{
6229 match(Set mem (StoreC mem src));
6230 ins_cost(MEMORY_REF_COST);
6231
6232 size(4);
6233 format %{ "STH $src,$mem\t! short" %}
6234 opcode(Assembler::sth_op3);
6235 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6236 ins_pipe(istore_mem_zero);
6237 %}
6238
6239 // Store Integer
6240 instruct storeI(memory mem, iRegI src) %{
6241 match(Set mem (StoreI mem src));
6242 ins_cost(MEMORY_REF_COST);
6243
6244 size(4);
6245 format %{ "STW $src,$mem" %}
6246 opcode(Assembler::stw_op3);
6247 ins_encode(simple_form3_mem_reg( mem, src ) );
6248 ins_pipe(istore_mem_reg);
6249 %}
6250
6251 // Store Long
6252 instruct storeL(memory mem, iRegL src) %{
6253 match(Set mem (StoreL mem src));
6254 ins_cost(MEMORY_REF_COST);
6255 size(4);
6256 format %{ "STX $src,$mem\t! long" %}
6257 opcode(Assembler::stx_op3);
6258 ins_encode(simple_form3_mem_reg( mem, src ) );
6259 ins_pipe(istore_mem_reg);
6260 %}
6261
6262 instruct storeI0(memory mem, immI0 src) %{
6263 match(Set mem (StoreI mem src));
6264 ins_cost(MEMORY_REF_COST);
6265
6266 size(4);
6267 format %{ "STW $src,$mem" %}
6268 opcode(Assembler::stw_op3);
6269 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6270 ins_pipe(istore_mem_zero);
6271 %}
6272
6273 instruct storeL0(memory mem, immL0 src) %{
6274 match(Set mem (StoreL mem src));
6275 ins_cost(MEMORY_REF_COST);
6276
6277 size(4);
6278 format %{ "STX $src,$mem" %}
6279 opcode(Assembler::stx_op3);
6280 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6281 ins_pipe(istore_mem_zero);
6282 %}
6283
6284 // Store Integer from float register (used after fstoi)
6285 instruct storeI_Freg(memory mem, regF src) %{
6286 match(Set mem (StoreI mem src));
6287 ins_cost(MEMORY_REF_COST);
6288
6289 size(4);
6290 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6291 opcode(Assembler::stf_op3);
6292 ins_encode(simple_form3_mem_reg( mem, src ) );
6293 ins_pipe(fstoreF_mem_reg);
6294 %}
6295
6296 // Store Pointer
6297 instruct storeP(memory dst, sp_ptr_RegP src) %{
6298 match(Set dst (StoreP dst src));
6299 ins_cost(MEMORY_REF_COST);
6300 size(4);
6301
6302 #ifndef _LP64
6303 format %{ "STW $src,$dst\t! ptr" %}
6304 opcode(Assembler::stw_op3, 0, REGP_OP);
6305 #else
6306 format %{ "STX $src,$dst\t! ptr" %}
6307 opcode(Assembler::stx_op3, 0, REGP_OP);
6308 #endif
6309 ins_encode( form3_mem_reg( dst, src ) );
6310 ins_pipe(istore_mem_spORreg);
6311 %}
6312
6313 instruct storeP0(memory dst, immP0 src) %{
6314 match(Set dst (StoreP dst src));
6315 ins_cost(MEMORY_REF_COST);
6316 size(4);
6317
6318 #ifndef _LP64
6319 format %{ "STW $src,$dst\t! ptr" %}
6320 opcode(Assembler::stw_op3, 0, REGP_OP);
6321 #else
6322 format %{ "STX $src,$dst\t! ptr" %}
6323 opcode(Assembler::stx_op3, 0, REGP_OP);
6324 #endif
6325 ins_encode( form3_mem_reg( dst, R_G0 ) );
6326 ins_pipe(istore_mem_zero);
6327 %}
6328
6329 // Store Compressed Pointer
6330 instruct storeN(memory dst, iRegN src) %{
6331 match(Set dst (StoreN dst src));
6332 ins_cost(MEMORY_REF_COST);
6333 size(4);
6334
6335 format %{ "STW $src,$dst\t! compressed ptr" %}
6336 ins_encode %{
6337 Register base = as_Register($dst$$base);
6338 Register index = as_Register($dst$$index);
6339 Register src = $src$$Register;
6340 if (index != G0) {
6341 __ stw(src, base, index);
6342 } else {
6343 __ stw(src, base, $dst$$disp);
6344 }
6345 %}
6346 ins_pipe(istore_mem_spORreg);
6347 %}
6348
6349 instruct storeN0(memory dst, immN0 src) %{
6350 match(Set dst (StoreN dst src));
6351 ins_cost(MEMORY_REF_COST);
6352 size(4);
6353
6354 format %{ "STW $src,$dst\t! compressed ptr" %}
6355 ins_encode %{
6356 Register base = as_Register($dst$$base);
6357 Register index = as_Register($dst$$index);
6358 if (index != G0) {
6359 __ stw(0, base, index);
6360 } else {
6361 __ stw(0, base, $dst$$disp);
6362 }
6363 %}
6364 ins_pipe(istore_mem_zero);
6365 %}
6366
6367 // Store Double
6368 instruct storeD( memory mem, regD src) %{
6369 match(Set mem (StoreD mem src));
6370 ins_cost(MEMORY_REF_COST);
6371
6372 size(4);
6373 format %{ "STDF $src,$mem" %}
6374 opcode(Assembler::stdf_op3);
6375 ins_encode(simple_form3_mem_reg( mem, src ) );
6376 ins_pipe(fstoreD_mem_reg);
6377 %}
6378
6379 instruct storeD0( memory mem, immD0 src) %{
6380 match(Set mem (StoreD mem src));
6381 ins_cost(MEMORY_REF_COST);
6382
6383 size(4);
6384 format %{ "STX $src,$mem" %}
6385 opcode(Assembler::stx_op3);
6386 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6387 ins_pipe(fstoreD_mem_zero);
6388 %}
6389
6390 // Store Float
6391 instruct storeF( memory mem, regF src) %{
6392 match(Set mem (StoreF mem src));
6393 ins_cost(MEMORY_REF_COST);
6394
6395 size(4);
6396 format %{ "STF $src,$mem" %}
6397 opcode(Assembler::stf_op3);
6398 ins_encode(simple_form3_mem_reg( mem, src ) );
6399 ins_pipe(fstoreF_mem_reg);
6400 %}
6401
6402 instruct storeF0( memory mem, immF0 src) %{
6403 match(Set mem (StoreF mem src));
6404 ins_cost(MEMORY_REF_COST);
6405
6406 size(4);
6407 format %{ "STW $src,$mem\t! storeF0" %}
6408 opcode(Assembler::stw_op3);
6409 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6410 ins_pipe(fstoreF_mem_zero);
6411 %}
6412
6413 // Store Aligned Packed Bytes in Double register to memory
6414 instruct storeA8B(memory mem, regD src) %{
6415 match(Set mem (Store8B mem src));
6416 ins_cost(MEMORY_REF_COST);
6417 size(4);
6418 format %{ "STDF $src,$mem\t! packed8B" %}
6419 opcode(Assembler::stdf_op3);
6420 ins_encode(simple_form3_mem_reg( mem, src ) );
6421 ins_pipe(fstoreD_mem_reg);
6422 %}
6423
6424 // Convert oop pointer into compressed form
6425 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6426 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6427 match(Set dst (EncodeP src));
6428 format %{ "encode_heap_oop $src, $dst" %}
6429 ins_encode %{
6430 __ encode_heap_oop($src$$Register, $dst$$Register);
6431 %}
6432 ins_pipe(ialu_reg);
6433 %}
6434
6435 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6436 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6437 match(Set dst (EncodeP src));
6438 format %{ "encode_heap_oop_not_null $src, $dst" %}
6439 ins_encode %{
6440 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6441 %}
6442 ins_pipe(ialu_reg);
6443 %}
6444
6445 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6446 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6447 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6448 match(Set dst (DecodeN src));
6449 format %{ "decode_heap_oop $src, $dst" %}
6450 ins_encode %{
6451 __ decode_heap_oop($src$$Register, $dst$$Register);
6452 %}
6453 ins_pipe(ialu_reg);
6454 %}
6455
6456 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6457 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6458 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6459 match(Set dst (DecodeN src));
6460 format %{ "decode_heap_oop_not_null $src, $dst" %}
6461 ins_encode %{
6462 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6463 %}
6464 ins_pipe(ialu_reg);
6465 %}
6466
6467
6468 // Store Zero into Aligned Packed Bytes
6469 instruct storeA8B0(memory mem, immI0 zero) %{
6470 match(Set mem (Store8B mem zero));
6471 ins_cost(MEMORY_REF_COST);
6472 size(4);
6473 format %{ "STX $zero,$mem\t! packed8B" %}
6474 opcode(Assembler::stx_op3);
6475 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6476 ins_pipe(fstoreD_mem_zero);
6477 %}
6478
6479 // Store Aligned Packed Chars/Shorts in Double register to memory
6480 instruct storeA4C(memory mem, regD src) %{
6481 match(Set mem (Store4C mem src));
6482 ins_cost(MEMORY_REF_COST);
6483 size(4);
6484 format %{ "STDF $src,$mem\t! packed4C" %}
6485 opcode(Assembler::stdf_op3);
6486 ins_encode(simple_form3_mem_reg( mem, src ) );
6487 ins_pipe(fstoreD_mem_reg);
6488 %}
6489
6490 // Store Zero into Aligned Packed Chars/Shorts
6491 instruct storeA4C0(memory mem, immI0 zero) %{
6492 match(Set mem (Store4C mem (Replicate4C zero)));
6493 ins_cost(MEMORY_REF_COST);
6494 size(4);
6495 format %{ "STX $zero,$mem\t! packed4C" %}
6496 opcode(Assembler::stx_op3);
6497 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6498 ins_pipe(fstoreD_mem_zero);
6499 %}
6500
6501 // Store Aligned Packed Ints in Double register to memory
6502 instruct storeA2I(memory mem, regD src) %{
6503 match(Set mem (Store2I mem src));
6504 ins_cost(MEMORY_REF_COST);
6505 size(4);
6506 format %{ "STDF $src,$mem\t! packed2I" %}
6507 opcode(Assembler::stdf_op3);
6508 ins_encode(simple_form3_mem_reg( mem, src ) );
6509 ins_pipe(fstoreD_mem_reg);
6510 %}
6511
6512 // Store Zero into Aligned Packed Ints
6513 instruct storeA2I0(memory mem, immI0 zero) %{
6514 match(Set mem (Store2I mem zero));
6515 ins_cost(MEMORY_REF_COST);
6516 size(4);
6517 format %{ "STX $zero,$mem\t! packed2I" %}
6518 opcode(Assembler::stx_op3);
6519 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6520 ins_pipe(fstoreD_mem_zero);
6521 %}
6522
6523
6524 //----------MemBar Instructions-----------------------------------------------
6525 // Memory barrier flavors
6526
6527 instruct membar_acquire() %{
6528 match(MemBarAcquire);
6529 ins_cost(4*MEMORY_REF_COST);
6530
6531 size(0);
6532 format %{ "MEMBAR-acquire" %}
6533 ins_encode( enc_membar_acquire );
6534 ins_pipe(long_memory_op);
6535 %}
6536
6537 instruct membar_acquire_lock() %{
6538 match(MemBarAcquire);
6539 predicate(Matcher::prior_fast_lock(n));
6540 ins_cost(0);
6541
6542 size(0);
6543 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6544 ins_encode( );
6545 ins_pipe(empty);
6546 %}
6547
6548 instruct membar_release() %{
6549 match(MemBarRelease);
6550 ins_cost(4*MEMORY_REF_COST);
6551
6552 size(0);
6553 format %{ "MEMBAR-release" %}
6554 ins_encode( enc_membar_release );
6555 ins_pipe(long_memory_op);
6556 %}
6557
6558 instruct membar_release_lock() %{
6559 match(MemBarRelease);
6560 predicate(Matcher::post_fast_unlock(n));
6561 ins_cost(0);
6562
6563 size(0);
6564 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6565 ins_encode( );
6566 ins_pipe(empty);
6567 %}
6568
6569 instruct membar_volatile() %{
6570 match(MemBarVolatile);
6571 ins_cost(4*MEMORY_REF_COST);
6572
6573 size(4);
6574 format %{ "MEMBAR-volatile" %}
6575 ins_encode( enc_membar_volatile );
6576 ins_pipe(long_memory_op);
6577 %}
6578
6579 instruct unnecessary_membar_volatile() %{
6580 match(MemBarVolatile);
6581 predicate(Matcher::post_store_load_barrier(n));
6582 ins_cost(0);
6583
6584 size(0);
6585 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6586 ins_encode( );
6587 ins_pipe(empty);
6588 %}
6589
6590 //----------Register Move Instructions-----------------------------------------
6591 instruct roundDouble_nop(regD dst) %{
6592 match(Set dst (RoundDouble dst));
6593 ins_cost(0);
6594 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6595 ins_encode( );
6596 ins_pipe(empty);
6597 %}
6598
6599
6600 instruct roundFloat_nop(regF dst) %{
6601 match(Set dst (RoundFloat dst));
6602 ins_cost(0);
6603 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6604 ins_encode( );
6605 ins_pipe(empty);
6606 %}
6607
6608
6609 // Cast Index to Pointer for unsafe natives
6610 instruct castX2P(iRegX src, iRegP dst) %{
6611 match(Set dst (CastX2P src));
6612
6613 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6614 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6615 ins_pipe(ialu_reg);
6616 %}
6617
6618 // Cast Pointer to Index for unsafe natives
6619 instruct castP2X(iRegP src, iRegX dst) %{
6620 match(Set dst (CastP2X src));
6621
6622 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6623 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6624 ins_pipe(ialu_reg);
6625 %}
6626
6627 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6628 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6629 match(Set stkSlot src); // chain rule
6630 ins_cost(MEMORY_REF_COST);
6631 format %{ "STDF $src,$stkSlot\t!stk" %}
6632 opcode(Assembler::stdf_op3);
6633 ins_encode(simple_form3_mem_reg(stkSlot, src));
6634 ins_pipe(fstoreD_stk_reg);
6635 %}
6636
6637 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6638 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6639 match(Set dst stkSlot); // chain rule
6640 ins_cost(MEMORY_REF_COST);
6641 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6642 opcode(Assembler::lddf_op3);
6643 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6644 ins_pipe(floadD_stk);
6645 %}
6646
6647 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6648 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6649 match(Set stkSlot src); // chain rule
6650 ins_cost(MEMORY_REF_COST);
6651 format %{ "STF $src,$stkSlot\t!stk" %}
6652 opcode(Assembler::stf_op3);
6653 ins_encode(simple_form3_mem_reg(stkSlot, src));
6654 ins_pipe(fstoreF_stk_reg);
6655 %}
6656
6657 //----------Conditional Move---------------------------------------------------
6658 // Conditional move
6659 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6660 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6661 ins_cost(150);
6662 format %{ "MOV$cmp $pcc,$src,$dst" %}
6663 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6664 ins_pipe(ialu_reg);
6665 %}
6666
6667 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6668 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6669 ins_cost(140);
6670 format %{ "MOV$cmp $pcc,$src,$dst" %}
6671 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6672 ins_pipe(ialu_imm);
6673 %}
6674
6675 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6676 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6677 ins_cost(150);
6678 size(4);
6679 format %{ "MOV$cmp $icc,$src,$dst" %}
6680 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6681 ins_pipe(ialu_reg);
6682 %}
6683
6684 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6685 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6686 ins_cost(140);
6687 size(4);
6688 format %{ "MOV$cmp $icc,$src,$dst" %}
6689 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6690 ins_pipe(ialu_imm);
6691 %}
6692
6693 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6694 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6695 ins_cost(150);
6696 size(4);
6697 format %{ "MOV$cmp $icc,$src,$dst" %}
6698 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6699 ins_pipe(ialu_reg);
6700 %}
6701
6702 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6703 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6704 ins_cost(140);
6705 size(4);
6706 format %{ "MOV$cmp $icc,$src,$dst" %}
6707 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6708 ins_pipe(ialu_imm);
6709 %}
6710
6711 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6712 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6713 ins_cost(150);
6714 size(4);
6715 format %{ "MOV$cmp $fcc,$src,$dst" %}
6716 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6717 ins_pipe(ialu_reg);
6718 %}
6719
6720 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6721 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6722 ins_cost(140);
6723 size(4);
6724 format %{ "MOV$cmp $fcc,$src,$dst" %}
6725 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6726 ins_pipe(ialu_imm);
6727 %}
6728
6729 // Conditional move for RegN. Only cmov(reg,reg).
6730 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6731 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6732 ins_cost(150);
6733 format %{ "MOV$cmp $pcc,$src,$dst" %}
6734 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6735 ins_pipe(ialu_reg);
6736 %}
6737
6738 // This instruction also works with CmpN so we don't need cmovNN_reg.
6739 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6740 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6741 ins_cost(150);
6742 size(4);
6743 format %{ "MOV$cmp $icc,$src,$dst" %}
6744 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6745 ins_pipe(ialu_reg);
6746 %}
6747
6748 // This instruction also works with CmpN so we don't need cmovNN_reg.
6749 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6750 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6751 ins_cost(150);
6752 size(4);
6753 format %{ "MOV$cmp $icc,$src,$dst" %}
6754 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6755 ins_pipe(ialu_reg);
6756 %}
6757
6758 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6759 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6760 ins_cost(150);
6761 size(4);
6762 format %{ "MOV$cmp $fcc,$src,$dst" %}
6763 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6764 ins_pipe(ialu_reg);
6765 %}
6766
6767 // Conditional move
6768 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6769 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6770 ins_cost(150);
6771 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6772 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6773 ins_pipe(ialu_reg);
6774 %}
6775
6776 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6777 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6778 ins_cost(140);
6779 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6781 ins_pipe(ialu_imm);
6782 %}
6783
6784 // This instruction also works with CmpN so we don't need cmovPN_reg.
6785 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6786 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6787 ins_cost(150);
6788
6789 size(4);
6790 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6791 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6792 ins_pipe(ialu_reg);
6793 %}
6794
6795 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6796 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6797 ins_cost(150);
6798
6799 size(4);
6800 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6801 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6802 ins_pipe(ialu_reg);
6803 %}
6804
6805 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6806 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6807 ins_cost(140);
6808
6809 size(4);
6810 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6811 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6812 ins_pipe(ialu_imm);
6813 %}
6814
6815 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6816 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6817 ins_cost(140);
6818
6819 size(4);
6820 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6821 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6822 ins_pipe(ialu_imm);
6823 %}
6824
6825 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6826 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6827 ins_cost(150);
6828 size(4);
6829 format %{ "MOV$cmp $fcc,$src,$dst" %}
6830 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6831 ins_pipe(ialu_imm);
6832 %}
6833
6834 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6835 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6836 ins_cost(140);
6837 size(4);
6838 format %{ "MOV$cmp $fcc,$src,$dst" %}
6839 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6840 ins_pipe(ialu_imm);
6841 %}
6842
6843 // Conditional move
6844 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6845 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6846 ins_cost(150);
6847 opcode(0x101);
6848 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6849 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6850 ins_pipe(int_conditional_float_move);
6851 %}
6852
6853 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6854 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6855 ins_cost(150);
6856
6857 size(4);
6858 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6859 opcode(0x101);
6860 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6861 ins_pipe(int_conditional_float_move);
6862 %}
6863
6864 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6865 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6866 ins_cost(150);
6867
6868 size(4);
6869 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6870 opcode(0x101);
6871 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6872 ins_pipe(int_conditional_float_move);
6873 %}
6874
6875 // Conditional move,
6876 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6877 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6878 ins_cost(150);
6879 size(4);
6880 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6881 opcode(0x1);
6882 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6883 ins_pipe(int_conditional_double_move);
6884 %}
6885
6886 // Conditional move
6887 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6888 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6889 ins_cost(150);
6890 size(4);
6891 opcode(0x102);
6892 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6893 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6894 ins_pipe(int_conditional_double_move);
6895 %}
6896
6897 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6898 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6899 ins_cost(150);
6900
6901 size(4);
6902 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6903 opcode(0x102);
6904 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6905 ins_pipe(int_conditional_double_move);
6906 %}
6907
6908 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6909 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6910 ins_cost(150);
6911
6912 size(4);
6913 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6914 opcode(0x102);
6915 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6916 ins_pipe(int_conditional_double_move);
6917 %}
6918
6919 // Conditional move,
6920 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6921 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6922 ins_cost(150);
6923 size(4);
6924 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6925 opcode(0x2);
6926 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6927 ins_pipe(int_conditional_double_move);
6928 %}
6929
6930 // Conditional move
6931 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6932 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6933 ins_cost(150);
6934 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6935 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6936 ins_pipe(ialu_reg);
6937 %}
6938
6939 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6940 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6941 ins_cost(140);
6942 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6943 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6944 ins_pipe(ialu_imm);
6945 %}
6946
6947 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6948 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6949 ins_cost(150);
6950
6951 size(4);
6952 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6953 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6954 ins_pipe(ialu_reg);
6955 %}
6956
6957
6958 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6959 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6960 ins_cost(150);
6961
6962 size(4);
6963 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6964 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6965 ins_pipe(ialu_reg);
6966 %}
6967
6968
6969 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6970 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6971 ins_cost(150);
6972
6973 size(4);
6974 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6975 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6976 ins_pipe(ialu_reg);
6977 %}
6978
6979
6980
6981 //----------OS and Locking Instructions----------------------------------------
6982
6983 // This name is KNOWN by the ADLC and cannot be changed.
6984 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6985 // for this guy.
6986 instruct tlsLoadP(g2RegP dst) %{
6987 match(Set dst (ThreadLocal));
6988
6989 size(0);
6990 ins_cost(0);
6991 format %{ "# TLS is in G2" %}
6992 ins_encode( /*empty encoding*/ );
6993 ins_pipe(ialu_none);
6994 %}
6995
6996 instruct checkCastPP( iRegP dst ) %{
6997 match(Set dst (CheckCastPP dst));
6998
6999 size(0);
7000 format %{ "# checkcastPP of $dst" %}
7001 ins_encode( /*empty encoding*/ );
7002 ins_pipe(empty);
7003 %}
7004
7005
7006 instruct castPP( iRegP dst ) %{
7007 match(Set dst (CastPP dst));
7008 format %{ "# castPP of $dst" %}
7009 ins_encode( /*empty encoding*/ );
7010 ins_pipe(empty);
7011 %}
7012
7013 instruct castII( iRegI dst ) %{
7014 match(Set dst (CastII dst));
7015 format %{ "# castII of $dst" %}
7016 ins_encode( /*empty encoding*/ );
7017 ins_cost(0);
7018 ins_pipe(empty);
7019 %}
7020
7021 //----------Arithmetic Instructions--------------------------------------------
7022 // Addition Instructions
7023 // Register Addition
7024 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7025 match(Set dst (AddI src1 src2));
7026
7027 size(4);
7028 format %{ "ADD $src1,$src2,$dst" %}
7029 ins_encode %{
7030 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7031 %}
7032 ins_pipe(ialu_reg_reg);
7033 %}
7034
7035 // Immediate Addition
7036 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7037 match(Set dst (AddI src1 src2));
7038
7039 size(4);
7040 format %{ "ADD $src1,$src2,$dst" %}
7041 opcode(Assembler::add_op3, Assembler::arith_op);
7042 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7043 ins_pipe(ialu_reg_imm);
7044 %}
7045
7046 // Pointer Register Addition
7047 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7048 match(Set dst (AddP src1 src2));
7049
7050 size(4);
7051 format %{ "ADD $src1,$src2,$dst" %}
7052 opcode(Assembler::add_op3, Assembler::arith_op);
7053 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7054 ins_pipe(ialu_reg_reg);
7055 %}
7056
7057 // Pointer Immediate Addition
7058 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7059 match(Set dst (AddP src1 src2));
7060
7061 size(4);
7062 format %{ "ADD $src1,$src2,$dst" %}
7063 opcode(Assembler::add_op3, Assembler::arith_op);
7064 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7065 ins_pipe(ialu_reg_imm);
7066 %}
7067
7068 // Long Addition
7069 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7070 match(Set dst (AddL src1 src2));
7071
7072 size(4);
7073 format %{ "ADD $src1,$src2,$dst\t! long" %}
7074 opcode(Assembler::add_op3, Assembler::arith_op);
7075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7076 ins_pipe(ialu_reg_reg);
7077 %}
7078
7079 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7080 match(Set dst (AddL src1 con));
7081
7082 size(4);
7083 format %{ "ADD $src1,$con,$dst" %}
7084 opcode(Assembler::add_op3, Assembler::arith_op);
7085 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7086 ins_pipe(ialu_reg_imm);
7087 %}
7088
7089 //----------Conditional_store--------------------------------------------------
7090 // Conditional-store of the updated heap-top.
7091 // Used during allocation of the shared heap.
7092 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7093
7094 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7095 instruct loadPLocked(iRegP dst, memory mem) %{
7096 match(Set dst (LoadPLocked mem));
7097 ins_cost(MEMORY_REF_COST);
7098
7099 #ifndef _LP64
7100 size(4);
7101 format %{ "LDUW $mem,$dst\t! ptr" %}
7102 opcode(Assembler::lduw_op3, 0, REGP_OP);
7103 #else
7104 format %{ "LDX $mem,$dst\t! ptr" %}
7105 opcode(Assembler::ldx_op3, 0, REGP_OP);
7106 #endif
7107 ins_encode( form3_mem_reg( mem, dst ) );
7108 ins_pipe(iload_mem);
7109 %}
7110
7111 // LoadL-locked. Same as a regular long load when used with a compare-swap
7112 instruct loadLLocked(iRegL dst, memory mem) %{
7113 match(Set dst (LoadLLocked mem));
7114 ins_cost(MEMORY_REF_COST);
7115 size(4);
7116 format %{ "LDX $mem,$dst\t! long" %}
7117 opcode(Assembler::ldx_op3);
7118 ins_encode(simple_form3_mem_reg( mem, dst ) );
7119 ins_pipe(iload_mem);
7120 %}
7121
7122 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7123 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7124 effect( KILL newval );
7125 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7126 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7127 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7128 ins_pipe( long_memory_op );
7129 %}
7130
7131 // Conditional-store of an int value.
7132 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7133 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7134 effect( KILL newval );
7135 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7136 "CMP $oldval,$newval\t\t! See if we made progress" %}
7137 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7138 ins_pipe( long_memory_op );
7139 %}
7140
7141 // Conditional-store of a long value.
7142 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7143 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7144 effect( KILL newval );
7145 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7146 "CMP $oldval,$newval\t\t! See if we made progress" %}
7147 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7148 ins_pipe( long_memory_op );
7149 %}
7150
7151 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7152
7153 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7154 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7155 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7156 format %{
7157 "MOV $newval,O7\n\t"
7158 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7159 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7160 "MOV 1,$res\n\t"
7161 "MOVne xcc,R_G0,$res"
7162 %}
7163 ins_encode( enc_casx(mem_ptr, oldval, newval),
7164 enc_lflags_ne_to_boolean(res) );
7165 ins_pipe( long_memory_op );
7166 %}
7167
7168
7169 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7170 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7171 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7172 format %{
7173 "MOV $newval,O7\n\t"
7174 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7175 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7176 "MOV 1,$res\n\t"
7177 "MOVne icc,R_G0,$res"
7178 %}
7179 ins_encode( enc_casi(mem_ptr, oldval, newval),
7180 enc_iflags_ne_to_boolean(res) );
7181 ins_pipe( long_memory_op );
7182 %}
7183
7184 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7185 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7186 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7187 format %{
7188 "MOV $newval,O7\n\t"
7189 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7190 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7191 "MOV 1,$res\n\t"
7192 "MOVne xcc,R_G0,$res"
7193 %}
7194 #ifdef _LP64
7195 ins_encode( enc_casx(mem_ptr, oldval, newval),
7196 enc_lflags_ne_to_boolean(res) );
7197 #else
7198 ins_encode( enc_casi(mem_ptr, oldval, newval),
7199 enc_iflags_ne_to_boolean(res) );
7200 #endif
7201 ins_pipe( long_memory_op );
7202 %}
7203
7204 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7205 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7206 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7207 format %{
7208 "MOV $newval,O7\n\t"
7209 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7210 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7211 "MOV 1,$res\n\t"
7212 "MOVne icc,R_G0,$res"
7213 %}
7214 ins_encode( enc_casi(mem_ptr, oldval, newval),
7215 enc_iflags_ne_to_boolean(res) );
7216 ins_pipe( long_memory_op );
7217 %}
7218
7219 //---------------------
7220 // Subtraction Instructions
7221 // Register Subtraction
7222 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7223 match(Set dst (SubI src1 src2));
7224
7225 size(4);
7226 format %{ "SUB $src1,$src2,$dst" %}
7227 opcode(Assembler::sub_op3, Assembler::arith_op);
7228 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7229 ins_pipe(ialu_reg_reg);
7230 %}
7231
7232 // Immediate Subtraction
7233 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7234 match(Set dst (SubI src1 src2));
7235
7236 size(4);
7237 format %{ "SUB $src1,$src2,$dst" %}
7238 opcode(Assembler::sub_op3, Assembler::arith_op);
7239 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7240 ins_pipe(ialu_reg_imm);
7241 %}
7242
7243 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7244 match(Set dst (SubI zero src2));
7245
7246 size(4);
7247 format %{ "NEG $src2,$dst" %}
7248 opcode(Assembler::sub_op3, Assembler::arith_op);
7249 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7250 ins_pipe(ialu_zero_reg);
7251 %}
7252
7253 // Long subtraction
7254 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7255 match(Set dst (SubL src1 src2));
7256
7257 size(4);
7258 format %{ "SUB $src1,$src2,$dst\t! long" %}
7259 opcode(Assembler::sub_op3, Assembler::arith_op);
7260 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7261 ins_pipe(ialu_reg_reg);
7262 %}
7263
7264 // Immediate Subtraction
7265 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7266 match(Set dst (SubL src1 con));
7267
7268 size(4);
7269 format %{ "SUB $src1,$con,$dst\t! long" %}
7270 opcode(Assembler::sub_op3, Assembler::arith_op);
7271 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7272 ins_pipe(ialu_reg_imm);
7273 %}
7274
7275 // Long negation
7276 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7277 match(Set dst (SubL zero src2));
7278
7279 size(4);
7280 format %{ "NEG $src2,$dst\t! long" %}
7281 opcode(Assembler::sub_op3, Assembler::arith_op);
7282 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7283 ins_pipe(ialu_zero_reg);
7284 %}
7285
7286 // Multiplication Instructions
7287 // Integer Multiplication
7288 // Register Multiplication
7289 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7290 match(Set dst (MulI src1 src2));
7291
7292 size(4);
7293 format %{ "MULX $src1,$src2,$dst" %}
7294 opcode(Assembler::mulx_op3, Assembler::arith_op);
7295 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7296 ins_pipe(imul_reg_reg);
7297 %}
7298
7299 // Immediate Multiplication
7300 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7301 match(Set dst (MulI src1 src2));
7302
7303 size(4);
7304 format %{ "MULX $src1,$src2,$dst" %}
7305 opcode(Assembler::mulx_op3, Assembler::arith_op);
7306 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7307 ins_pipe(imul_reg_imm);
7308 %}
7309
7310 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7311 match(Set dst (MulL src1 src2));
7312 ins_cost(DEFAULT_COST * 5);
7313 size(4);
7314 format %{ "MULX $src1,$src2,$dst\t! long" %}
7315 opcode(Assembler::mulx_op3, Assembler::arith_op);
7316 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7317 ins_pipe(mulL_reg_reg);
7318 %}
7319
7320 // Immediate Multiplication
7321 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7322 match(Set dst (MulL src1 src2));
7323 ins_cost(DEFAULT_COST * 5);
7324 size(4);
7325 format %{ "MULX $src1,$src2,$dst" %}
7326 opcode(Assembler::mulx_op3, Assembler::arith_op);
7327 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7328 ins_pipe(mulL_reg_imm);
7329 %}
7330
7331 // Integer Division
7332 // Register Division
7333 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7334 match(Set dst (DivI src1 src2));
7335 ins_cost((2+71)*DEFAULT_COST);
7336
7337 format %{ "SRA $src2,0,$src2\n\t"
7338 "SRA $src1,0,$src1\n\t"
7339 "SDIVX $src1,$src2,$dst" %}
7340 ins_encode( idiv_reg( src1, src2, dst ) );
7341 ins_pipe(sdiv_reg_reg);
7342 %}
7343
7344 // Immediate Division
7345 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7346 match(Set dst (DivI src1 src2));
7347 ins_cost((2+71)*DEFAULT_COST);
7348
7349 format %{ "SRA $src1,0,$src1\n\t"
7350 "SDIVX $src1,$src2,$dst" %}
7351 ins_encode( idiv_imm( src1, src2, dst ) );
7352 ins_pipe(sdiv_reg_imm);
7353 %}
7354
7355 //----------Div-By-10-Expansion------------------------------------------------
7356 // Extract hi bits of a 32x32->64 bit multiply.
7357 // Expand rule only, not matched
7358 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7359 effect( DEF dst, USE src1, USE src2 );
7360 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7361 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7362 ins_encode( enc_mul_hi(dst,src1,src2));
7363 ins_pipe(sdiv_reg_reg);
7364 %}
7365
7366 // Magic constant, reciprocal of 10
7367 instruct loadConI_x66666667(iRegIsafe dst) %{
7368 effect( DEF dst );
7369
7370 size(8);
7371 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7372 ins_encode( Set32(0x66666667, dst) );
7373 ins_pipe(ialu_hi_lo_reg);
7374 %}
7375
7376 // Register Shift Right Arithmetic Long by 32-63
7377 instruct sra_31( iRegI dst, iRegI src ) %{
7378 effect( DEF dst, USE src );
7379 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7380 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7381 ins_pipe(ialu_reg_reg);
7382 %}
7383
7384 // Arithmetic Shift Right by 8-bit immediate
7385 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7386 effect( DEF dst, USE src );
7387 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7388 opcode(Assembler::sra_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7390 ins_pipe(ialu_reg_imm);
7391 %}
7392
7393 // Integer DIV with 10
7394 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7395 match(Set dst (DivI src div));
7396 ins_cost((6+6)*DEFAULT_COST);
7397 expand %{
7398 iRegIsafe tmp1; // Killed temps;
7399 iRegIsafe tmp2; // Killed temps;
7400 iRegI tmp3; // Killed temps;
7401 iRegI tmp4; // Killed temps;
7402 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7403 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7404 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7405 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7406 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7407 %}
7408 %}
7409
7410 // Register Long Division
7411 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7412 match(Set dst (DivL src1 src2));
7413 ins_cost(DEFAULT_COST*71);
7414 size(4);
7415 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7416 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7417 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7418 ins_pipe(divL_reg_reg);
7419 %}
7420
7421 // Register Long Division
7422 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7423 match(Set dst (DivL src1 src2));
7424 ins_cost(DEFAULT_COST*71);
7425 size(4);
7426 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7427 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7428 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7429 ins_pipe(divL_reg_imm);
7430 %}
7431
7432 // Integer Remainder
7433 // Register Remainder
7434 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7435 match(Set dst (ModI src1 src2));
7436 effect( KILL ccr, KILL temp);
7437
7438 format %{ "SREM $src1,$src2,$dst" %}
7439 ins_encode( irem_reg(src1, src2, dst, temp) );
7440 ins_pipe(sdiv_reg_reg);
7441 %}
7442
7443 // Immediate Remainder
7444 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7445 match(Set dst (ModI src1 src2));
7446 effect( KILL ccr, KILL temp);
7447
7448 format %{ "SREM $src1,$src2,$dst" %}
7449 ins_encode( irem_imm(src1, src2, dst, temp) );
7450 ins_pipe(sdiv_reg_imm);
7451 %}
7452
7453 // Register Long Remainder
7454 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7455 effect(DEF dst, USE src1, USE src2);
7456 size(4);
7457 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7458 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7459 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7460 ins_pipe(divL_reg_reg);
7461 %}
7462
7463 // Register Long Division
7464 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7465 effect(DEF dst, USE src1, USE src2);
7466 size(4);
7467 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7468 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7470 ins_pipe(divL_reg_imm);
7471 %}
7472
7473 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7474 effect(DEF dst, USE src1, USE src2);
7475 size(4);
7476 format %{ "MULX $src1,$src2,$dst\t! long" %}
7477 opcode(Assembler::mulx_op3, Assembler::arith_op);
7478 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7479 ins_pipe(mulL_reg_reg);
7480 %}
7481
7482 // Immediate Multiplication
7483 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7484 effect(DEF dst, USE src1, USE src2);
7485 size(4);
7486 format %{ "MULX $src1,$src2,$dst" %}
7487 opcode(Assembler::mulx_op3, Assembler::arith_op);
7488 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7489 ins_pipe(mulL_reg_imm);
7490 %}
7491
7492 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7493 effect(DEF dst, USE src1, USE src2);
7494 size(4);
7495 format %{ "SUB $src1,$src2,$dst\t! long" %}
7496 opcode(Assembler::sub_op3, Assembler::arith_op);
7497 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7498 ins_pipe(ialu_reg_reg);
7499 %}
7500
7501 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7502 effect(DEF dst, USE src1, USE src2);
7503 size(4);
7504 format %{ "SUB $src1,$src2,$dst\t! long" %}
7505 opcode(Assembler::sub_op3, Assembler::arith_op);
7506 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7507 ins_pipe(ialu_reg_reg);
7508 %}
7509
7510 // Register Long Remainder
7511 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7512 match(Set dst (ModL src1 src2));
7513 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7514 expand %{
7515 iRegL tmp1;
7516 iRegL tmp2;
7517 divL_reg_reg_1(tmp1, src1, src2);
7518 mulL_reg_reg_1(tmp2, tmp1, src2);
7519 subL_reg_reg_1(dst, src1, tmp2);
7520 %}
7521 %}
7522
7523 // Register Long Remainder
7524 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7525 match(Set dst (ModL src1 src2));
7526 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7527 expand %{
7528 iRegL tmp1;
7529 iRegL tmp2;
7530 divL_reg_imm13_1(tmp1, src1, src2);
7531 mulL_reg_imm13_1(tmp2, tmp1, src2);
7532 subL_reg_reg_2 (dst, src1, tmp2);
7533 %}
7534 %}
7535
7536 // Integer Shift Instructions
7537 // Register Shift Left
7538 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7539 match(Set dst (LShiftI src1 src2));
7540
7541 size(4);
7542 format %{ "SLL $src1,$src2,$dst" %}
7543 opcode(Assembler::sll_op3, Assembler::arith_op);
7544 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7545 ins_pipe(ialu_reg_reg);
7546 %}
7547
7548 // Register Shift Left Immediate
7549 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7550 match(Set dst (LShiftI src1 src2));
7551
7552 size(4);
7553 format %{ "SLL $src1,$src2,$dst" %}
7554 opcode(Assembler::sll_op3, Assembler::arith_op);
7555 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7556 ins_pipe(ialu_reg_imm);
7557 %}
7558
7559 // Register Shift Left
7560 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7561 match(Set dst (LShiftL src1 src2));
7562
7563 size(4);
7564 format %{ "SLLX $src1,$src2,$dst" %}
7565 opcode(Assembler::sllx_op3, Assembler::arith_op);
7566 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7567 ins_pipe(ialu_reg_reg);
7568 %}
7569
7570 // Register Shift Left Immediate
7571 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7572 match(Set dst (LShiftL src1 src2));
7573
7574 size(4);
7575 format %{ "SLLX $src1,$src2,$dst" %}
7576 opcode(Assembler::sllx_op3, Assembler::arith_op);
7577 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7578 ins_pipe(ialu_reg_imm);
7579 %}
7580
7581 // Register Arithmetic Shift Right
7582 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7583 match(Set dst (RShiftI src1 src2));
7584 size(4);
7585 format %{ "SRA $src1,$src2,$dst" %}
7586 opcode(Assembler::sra_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7588 ins_pipe(ialu_reg_reg);
7589 %}
7590
7591 // Register Arithmetic Shift Right Immediate
7592 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7593 match(Set dst (RShiftI src1 src2));
7594
7595 size(4);
7596 format %{ "SRA $src1,$src2,$dst" %}
7597 opcode(Assembler::sra_op3, Assembler::arith_op);
7598 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7599 ins_pipe(ialu_reg_imm);
7600 %}
7601
7602 // Register Shift Right Arithmatic Long
7603 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7604 match(Set dst (RShiftL src1 src2));
7605
7606 size(4);
7607 format %{ "SRAX $src1,$src2,$dst" %}
7608 opcode(Assembler::srax_op3, Assembler::arith_op);
7609 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7610 ins_pipe(ialu_reg_reg);
7611 %}
7612
7613 // Register Shift Left Immediate
7614 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7615 match(Set dst (RShiftL src1 src2));
7616
7617 size(4);
7618 format %{ "SRAX $src1,$src2,$dst" %}
7619 opcode(Assembler::srax_op3, Assembler::arith_op);
7620 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7621 ins_pipe(ialu_reg_imm);
7622 %}
7623
7624 // Register Shift Right
7625 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7626 match(Set dst (URShiftI src1 src2));
7627
7628 size(4);
7629 format %{ "SRL $src1,$src2,$dst" %}
7630 opcode(Assembler::srl_op3, Assembler::arith_op);
7631 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7632 ins_pipe(ialu_reg_reg);
7633 %}
7634
7635 // Register Shift Right Immediate
7636 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7637 match(Set dst (URShiftI src1 src2));
7638
7639 size(4);
7640 format %{ "SRL $src1,$src2,$dst" %}
7641 opcode(Assembler::srl_op3, Assembler::arith_op);
7642 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7643 ins_pipe(ialu_reg_imm);
7644 %}
7645
7646 // Register Shift Right
7647 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7648 match(Set dst (URShiftL src1 src2));
7649
7650 size(4);
7651 format %{ "SRLX $src1,$src2,$dst" %}
7652 opcode(Assembler::srlx_op3, Assembler::arith_op);
7653 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7654 ins_pipe(ialu_reg_reg);
7655 %}
7656
7657 // Register Shift Right Immediate
7658 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7659 match(Set dst (URShiftL src1 src2));
7660
7661 size(4);
7662 format %{ "SRLX $src1,$src2,$dst" %}
7663 opcode(Assembler::srlx_op3, Assembler::arith_op);
7664 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7665 ins_pipe(ialu_reg_imm);
7666 %}
7667
7668 // Register Shift Right Immediate with a CastP2X
7669 #ifdef _LP64
7670 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7671 match(Set dst (URShiftL (CastP2X src1) src2));
7672 size(4);
7673 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7674 opcode(Assembler::srlx_op3, Assembler::arith_op);
7675 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7676 ins_pipe(ialu_reg_imm);
7677 %}
7678 #else
7679 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7680 match(Set dst (URShiftI (CastP2X src1) src2));
7681 size(4);
7682 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7683 opcode(Assembler::srl_op3, Assembler::arith_op);
7684 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7685 ins_pipe(ialu_reg_imm);
7686 %}
7687 #endif
7688
7689
7690 //----------Floating Point Arithmetic Instructions-----------------------------
7691
7692 // Add float single precision
7693 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7694 match(Set dst (AddF src1 src2));
7695
7696 size(4);
7697 format %{ "FADDS $src1,$src2,$dst" %}
7698 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7699 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7700 ins_pipe(faddF_reg_reg);
7701 %}
7702
7703 // Add float double precision
7704 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7705 match(Set dst (AddD src1 src2));
7706
7707 size(4);
7708 format %{ "FADDD $src1,$src2,$dst" %}
7709 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7710 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7711 ins_pipe(faddD_reg_reg);
7712 %}
7713
7714 // Sub float single precision
7715 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7716 match(Set dst (SubF src1 src2));
7717
7718 size(4);
7719 format %{ "FSUBS $src1,$src2,$dst" %}
7720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7721 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7722 ins_pipe(faddF_reg_reg);
7723 %}
7724
7725 // Sub float double precision
7726 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7727 match(Set dst (SubD src1 src2));
7728
7729 size(4);
7730 format %{ "FSUBD $src1,$src2,$dst" %}
7731 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7732 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7733 ins_pipe(faddD_reg_reg);
7734 %}
7735
7736 // Mul float single precision
7737 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7738 match(Set dst (MulF src1 src2));
7739
7740 size(4);
7741 format %{ "FMULS $src1,$src2,$dst" %}
7742 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7743 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7744 ins_pipe(fmulF_reg_reg);
7745 %}
7746
7747 // Mul float double precision
7748 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7749 match(Set dst (MulD src1 src2));
7750
7751 size(4);
7752 format %{ "FMULD $src1,$src2,$dst" %}
7753 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7754 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7755 ins_pipe(fmulD_reg_reg);
7756 %}
7757
7758 // Div float single precision
7759 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7760 match(Set dst (DivF src1 src2));
7761
7762 size(4);
7763 format %{ "FDIVS $src1,$src2,$dst" %}
7764 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7765 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7766 ins_pipe(fdivF_reg_reg);
7767 %}
7768
7769 // Div float double precision
7770 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7771 match(Set dst (DivD src1 src2));
7772
7773 size(4);
7774 format %{ "FDIVD $src1,$src2,$dst" %}
7775 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7776 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7777 ins_pipe(fdivD_reg_reg);
7778 %}
7779
7780 // Absolute float double precision
7781 instruct absD_reg(regD dst, regD src) %{
7782 match(Set dst (AbsD src));
7783
7784 format %{ "FABSd $src,$dst" %}
7785 ins_encode(fabsd(dst, src));
7786 ins_pipe(faddD_reg);
7787 %}
7788
7789 // Absolute float single precision
7790 instruct absF_reg(regF dst, regF src) %{
7791 match(Set dst (AbsF src));
7792
7793 format %{ "FABSs $src,$dst" %}
7794 ins_encode(fabss(dst, src));
7795 ins_pipe(faddF_reg);
7796 %}
7797
7798 instruct negF_reg(regF dst, regF src) %{
7799 match(Set dst (NegF src));
7800
7801 size(4);
7802 format %{ "FNEGs $src,$dst" %}
7803 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7804 ins_encode(form3_opf_rs2F_rdF(src, dst));
7805 ins_pipe(faddF_reg);
7806 %}
7807
7808 instruct negD_reg(regD dst, regD src) %{
7809 match(Set dst (NegD src));
7810
7811 format %{ "FNEGd $src,$dst" %}
7812 ins_encode(fnegd(dst, src));
7813 ins_pipe(faddD_reg);
7814 %}
7815
7816 // Sqrt float double precision
7817 instruct sqrtF_reg_reg(regF dst, regF src) %{
7818 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7819
7820 size(4);
7821 format %{ "FSQRTS $src,$dst" %}
7822 ins_encode(fsqrts(dst, src));
7823 ins_pipe(fdivF_reg_reg);
7824 %}
7825
7826 // Sqrt float double precision
7827 instruct sqrtD_reg_reg(regD dst, regD src) %{
7828 match(Set dst (SqrtD src));
7829
7830 size(4);
7831 format %{ "FSQRTD $src,$dst" %}
7832 ins_encode(fsqrtd(dst, src));
7833 ins_pipe(fdivD_reg_reg);
7834 %}
7835
7836 //----------Logical Instructions-----------------------------------------------
7837 // And Instructions
7838 // Register And
7839 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7840 match(Set dst (AndI src1 src2));
7841
7842 size(4);
7843 format %{ "AND $src1,$src2,$dst" %}
7844 opcode(Assembler::and_op3, Assembler::arith_op);
7845 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7846 ins_pipe(ialu_reg_reg);
7847 %}
7848
7849 // Immediate And
7850 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7851 match(Set dst (AndI src1 src2));
7852
7853 size(4);
7854 format %{ "AND $src1,$src2,$dst" %}
7855 opcode(Assembler::and_op3, Assembler::arith_op);
7856 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7857 ins_pipe(ialu_reg_imm);
7858 %}
7859
7860 // Register And Long
7861 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7862 match(Set dst (AndL src1 src2));
7863
7864 ins_cost(DEFAULT_COST);
7865 size(4);
7866 format %{ "AND $src1,$src2,$dst\t! long" %}
7867 opcode(Assembler::and_op3, Assembler::arith_op);
7868 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7869 ins_pipe(ialu_reg_reg);
7870 %}
7871
7872 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7873 match(Set dst (AndL src1 con));
7874
7875 ins_cost(DEFAULT_COST);
7876 size(4);
7877 format %{ "AND $src1,$con,$dst\t! long" %}
7878 opcode(Assembler::and_op3, Assembler::arith_op);
7879 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7880 ins_pipe(ialu_reg_imm);
7881 %}
7882
7883 // Or Instructions
7884 // Register Or
7885 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7886 match(Set dst (OrI src1 src2));
7887
7888 size(4);
7889 format %{ "OR $src1,$src2,$dst" %}
7890 opcode(Assembler::or_op3, Assembler::arith_op);
7891 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7892 ins_pipe(ialu_reg_reg);
7893 %}
7894
7895 // Immediate Or
7896 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7897 match(Set dst (OrI src1 src2));
7898
7899 size(4);
7900 format %{ "OR $src1,$src2,$dst" %}
7901 opcode(Assembler::or_op3, Assembler::arith_op);
7902 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7903 ins_pipe(ialu_reg_imm);
7904 %}
7905
7906 // Register Or Long
7907 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7908 match(Set dst (OrL src1 src2));
7909
7910 ins_cost(DEFAULT_COST);
7911 size(4);
7912 format %{ "OR $src1,$src2,$dst\t! long" %}
7913 opcode(Assembler::or_op3, Assembler::arith_op);
7914 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7915 ins_pipe(ialu_reg_reg);
7916 %}
7917
7918 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7919 match(Set dst (OrL src1 con));
7920 ins_cost(DEFAULT_COST*2);
7921
7922 ins_cost(DEFAULT_COST);
7923 size(4);
7924 format %{ "OR $src1,$con,$dst\t! long" %}
7925 opcode(Assembler::or_op3, Assembler::arith_op);
7926 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7927 ins_pipe(ialu_reg_imm);
7928 %}
7929
7930 #ifndef _LP64
7931
7932 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7933 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7934 match(Set dst (OrI src1 (CastP2X src2)));
7935
7936 size(4);
7937 format %{ "OR $src1,$src2,$dst" %}
7938 opcode(Assembler::or_op3, Assembler::arith_op);
7939 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7940 ins_pipe(ialu_reg_reg);
7941 %}
7942
7943 #else
7944
7945 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7946 match(Set dst (OrL src1 (CastP2X src2)));
7947
7948 ins_cost(DEFAULT_COST);
7949 size(4);
7950 format %{ "OR $src1,$src2,$dst\t! long" %}
7951 opcode(Assembler::or_op3, Assembler::arith_op);
7952 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7953 ins_pipe(ialu_reg_reg);
7954 %}
7955
7956 #endif
7957
7958 // Xor Instructions
7959 // Register Xor
7960 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7961 match(Set dst (XorI src1 src2));
7962
7963 size(4);
7964 format %{ "XOR $src1,$src2,$dst" %}
7965 opcode(Assembler::xor_op3, Assembler::arith_op);
7966 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7967 ins_pipe(ialu_reg_reg);
7968 %}
7969
7970 // Immediate Xor
7971 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7972 match(Set dst (XorI src1 src2));
7973
7974 size(4);
7975 format %{ "XOR $src1,$src2,$dst" %}
7976 opcode(Assembler::xor_op3, Assembler::arith_op);
7977 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7978 ins_pipe(ialu_reg_imm);
7979 %}
7980
7981 // Register Xor Long
7982 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7983 match(Set dst (XorL src1 src2));
7984
7985 ins_cost(DEFAULT_COST);
7986 size(4);
7987 format %{ "XOR $src1,$src2,$dst\t! long" %}
7988 opcode(Assembler::xor_op3, Assembler::arith_op);
7989 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7990 ins_pipe(ialu_reg_reg);
7991 %}
7992
7993 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7994 match(Set dst (XorL src1 con));
7995
7996 ins_cost(DEFAULT_COST);
7997 size(4);
7998 format %{ "XOR $src1,$con,$dst\t! long" %}
7999 opcode(Assembler::xor_op3, Assembler::arith_op);
8000 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8001 ins_pipe(ialu_reg_imm);
8002 %}
8003
8004 //----------Convert to Boolean-------------------------------------------------
8005 // Nice hack for 32-bit tests but doesn't work for
8006 // 64-bit pointers.
8007 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8008 match(Set dst (Conv2B src));
8009 effect( KILL ccr );
8010 ins_cost(DEFAULT_COST*2);
8011 format %{ "CMP R_G0,$src\n\t"
8012 "ADDX R_G0,0,$dst" %}
8013 ins_encode( enc_to_bool( src, dst ) );
8014 ins_pipe(ialu_reg_ialu);
8015 %}
8016
8017 #ifndef _LP64
8018 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8019 match(Set dst (Conv2B src));
8020 effect( KILL ccr );
8021 ins_cost(DEFAULT_COST*2);
8022 format %{ "CMP R_G0,$src\n\t"
8023 "ADDX R_G0,0,$dst" %}
8024 ins_encode( enc_to_bool( src, dst ) );
8025 ins_pipe(ialu_reg_ialu);
8026 %}
8027 #else
8028 instruct convP2B( iRegI dst, iRegP src ) %{
8029 match(Set dst (Conv2B src));
8030 ins_cost(DEFAULT_COST*2);
8031 format %{ "MOV $src,$dst\n\t"
8032 "MOVRNZ $src,1,$dst" %}
8033 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8034 ins_pipe(ialu_clr_and_mover);
8035 %}
8036 #endif
8037
8038 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8039 match(Set dst (CmpLTMask p q));
8040 effect( KILL ccr );
8041 ins_cost(DEFAULT_COST*4);
8042 format %{ "CMP $p,$q\n\t"
8043 "MOV #0,$dst\n\t"
8044 "BLT,a .+8\n\t"
8045 "MOV #-1,$dst" %}
8046 ins_encode( enc_ltmask(p,q,dst) );
8047 ins_pipe(ialu_reg_reg_ialu);
8048 %}
8049
8050 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8051 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8052 effect(KILL ccr, TEMP tmp);
8053 ins_cost(DEFAULT_COST*3);
8054
8055 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8056 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8057 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8058 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8059 ins_pipe( cadd_cmpltmask );
8060 %}
8061
8062 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8063 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
8064 effect( KILL ccr, TEMP tmp);
8065 ins_cost(DEFAULT_COST*3);
8066
8067 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8068 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8069 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8070 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8071 ins_pipe( cadd_cmpltmask );
8072 %}
8073
8074 //----------Arithmetic Conversion Instructions---------------------------------
8075 // The conversions operations are all Alpha sorted. Please keep it that way!
8076
8077 instruct convD2F_reg(regF dst, regD src) %{
8078 match(Set dst (ConvD2F src));
8079 size(4);
8080 format %{ "FDTOS $src,$dst" %}
8081 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8082 ins_encode(form3_opf_rs2D_rdF(src, dst));
8083 ins_pipe(fcvtD2F);
8084 %}
8085
8086
8087 // Convert a double to an int in a float register.
8088 // If the double is a NAN, stuff a zero in instead.
8089 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8090 effect(DEF dst, USE src, KILL fcc0);
8091 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8092 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8093 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8094 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8095 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8096 "skip:" %}
8097 ins_encode(form_d2i_helper(src,dst));
8098 ins_pipe(fcvtD2I);
8099 %}
8100
8101 instruct convD2I_reg(stackSlotI dst, regD src) %{
8102 match(Set dst (ConvD2I src));
8103 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8104 expand %{
8105 regF tmp;
8106 convD2I_helper(tmp, src);
8107 regF_to_stkI(dst, tmp);
8108 %}
8109 %}
8110
8111 // Convert a double to a long in a double register.
8112 // If the double is a NAN, stuff a zero in instead.
8113 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8114 effect(DEF dst, USE src, KILL fcc0);
8115 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8116 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8117 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8118 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8119 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8120 "skip:" %}
8121 ins_encode(form_d2l_helper(src,dst));
8122 ins_pipe(fcvtD2L);
8123 %}
8124
8125
8126 // Double to Long conversion
8127 instruct convD2L_reg(stackSlotL dst, regD src) %{
8128 match(Set dst (ConvD2L src));
8129 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8130 expand %{
8131 regD tmp;
8132 convD2L_helper(tmp, src);
8133 regD_to_stkL(dst, tmp);
8134 %}
8135 %}
8136
8137
8138 instruct convF2D_reg(regD dst, regF src) %{
8139 match(Set dst (ConvF2D src));
8140 format %{ "FSTOD $src,$dst" %}
8141 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8142 ins_encode(form3_opf_rs2F_rdD(src, dst));
8143 ins_pipe(fcvtF2D);
8144 %}
8145
8146
8147 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8148 effect(DEF dst, USE src, KILL fcc0);
8149 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8150 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8151 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8152 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8153 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8154 "skip:" %}
8155 ins_encode(form_f2i_helper(src,dst));
8156 ins_pipe(fcvtF2I);
8157 %}
8158
8159 instruct convF2I_reg(stackSlotI dst, regF src) %{
8160 match(Set dst (ConvF2I src));
8161 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8162 expand %{
8163 regF tmp;
8164 convF2I_helper(tmp, src);
8165 regF_to_stkI(dst, tmp);
8166 %}
8167 %}
8168
8169
8170 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8171 effect(DEF dst, USE src, KILL fcc0);
8172 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8173 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8174 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8175 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8176 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8177 "skip:" %}
8178 ins_encode(form_f2l_helper(src,dst));
8179 ins_pipe(fcvtF2L);
8180 %}
8181
8182 // Float to Long conversion
8183 instruct convF2L_reg(stackSlotL dst, regF src) %{
8184 match(Set dst (ConvF2L src));
8185 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8186 expand %{
8187 regD tmp;
8188 convF2L_helper(tmp, src);
8189 regD_to_stkL(dst, tmp);
8190 %}
8191 %}
8192
8193
8194 instruct convI2D_helper(regD dst, regF tmp) %{
8195 effect(USE tmp, DEF dst);
8196 format %{ "FITOD $tmp,$dst" %}
8197 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8198 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8199 ins_pipe(fcvtI2D);
8200 %}
8201
8202 instruct convI2D_reg(stackSlotI src, regD dst) %{
8203 match(Set dst (ConvI2D src));
8204 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8205 expand %{
8206 regF tmp;
8207 stkI_to_regF( tmp, src);
8208 convI2D_helper( dst, tmp);
8209 %}
8210 %}
8211
8212 instruct convI2D_mem( regD_low dst, memory mem ) %{
8213 match(Set dst (ConvI2D (LoadI mem)));
8214 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8215 size(8);
8216 format %{ "LDF $mem,$dst\n\t"
8217 "FITOD $dst,$dst" %}
8218 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8219 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8220 ins_pipe(floadF_mem);
8221 %}
8222
8223
8224 instruct convI2F_helper(regF dst, regF tmp) %{
8225 effect(DEF dst, USE tmp);
8226 format %{ "FITOS $tmp,$dst" %}
8227 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8228 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8229 ins_pipe(fcvtI2F);
8230 %}
8231
8232 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8233 match(Set dst (ConvI2F src));
8234 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8235 expand %{
8236 regF tmp;
8237 stkI_to_regF(tmp,src);
8238 convI2F_helper(dst, tmp);
8239 %}
8240 %}
8241
8242 instruct convI2F_mem( regF dst, memory mem ) %{
8243 match(Set dst (ConvI2F (LoadI mem)));
8244 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8245 size(8);
8246 format %{ "LDF $mem,$dst\n\t"
8247 "FITOS $dst,$dst" %}
8248 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8249 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8250 ins_pipe(floadF_mem);
8251 %}
8252
8253
8254 instruct convI2L_reg(iRegL dst, iRegI src) %{
8255 match(Set dst (ConvI2L src));
8256 size(4);
8257 format %{ "SRA $src,0,$dst\t! int->long" %}
8258 opcode(Assembler::sra_op3, Assembler::arith_op);
8259 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8260 ins_pipe(ialu_reg_reg);
8261 %}
8262
8263 // Zero-extend convert int to long
8264 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8265 match(Set dst (AndL (ConvI2L src) mask) );
8266 size(4);
8267 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8268 opcode(Assembler::srl_op3, Assembler::arith_op);
8269 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8270 ins_pipe(ialu_reg_reg);
8271 %}
8272
8273 // Zero-extend long
8274 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8275 match(Set dst (AndL src mask) );
8276 size(4);
8277 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8278 opcode(Assembler::srl_op3, Assembler::arith_op);
8279 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8280 ins_pipe(ialu_reg_reg);
8281 %}
8282
8283 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8284 match(Set dst (MoveF2I src));
8285 effect(DEF dst, USE src);
8286 ins_cost(MEMORY_REF_COST);
8287
8288 size(4);
8289 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8290 opcode(Assembler::lduw_op3);
8291 ins_encode(simple_form3_mem_reg( src, dst ) );
8292 ins_pipe(iload_mem);
8293 %}
8294
8295 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8296 match(Set dst (MoveI2F src));
8297 effect(DEF dst, USE src);
8298 ins_cost(MEMORY_REF_COST);
8299
8300 size(4);
8301 format %{ "LDF $src,$dst\t! MoveI2F" %}
8302 opcode(Assembler::ldf_op3);
8303 ins_encode(simple_form3_mem_reg(src, dst));
8304 ins_pipe(floadF_stk);
8305 %}
8306
8307 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8308 match(Set dst (MoveD2L src));
8309 effect(DEF dst, USE src);
8310 ins_cost(MEMORY_REF_COST);
8311
8312 size(4);
8313 format %{ "LDX $src,$dst\t! MoveD2L" %}
8314 opcode(Assembler::ldx_op3);
8315 ins_encode(simple_form3_mem_reg( src, dst ) );
8316 ins_pipe(iload_mem);
8317 %}
8318
8319 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8320 match(Set dst (MoveL2D src));
8321 effect(DEF dst, USE src);
8322 ins_cost(MEMORY_REF_COST);
8323
8324 size(4);
8325 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8326 opcode(Assembler::lddf_op3);
8327 ins_encode(simple_form3_mem_reg(src, dst));
8328 ins_pipe(floadD_stk);
8329 %}
8330
8331 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8332 match(Set dst (MoveF2I src));
8333 effect(DEF dst, USE src);
8334 ins_cost(MEMORY_REF_COST);
8335
8336 size(4);
8337 format %{ "STF $src,$dst\t!MoveF2I" %}
8338 opcode(Assembler::stf_op3);
8339 ins_encode(simple_form3_mem_reg(dst, src));
8340 ins_pipe(fstoreF_stk_reg);
8341 %}
8342
8343 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8344 match(Set dst (MoveI2F src));
8345 effect(DEF dst, USE src);
8346 ins_cost(MEMORY_REF_COST);
8347
8348 size(4);
8349 format %{ "STW $src,$dst\t!MoveI2F" %}
8350 opcode(Assembler::stw_op3);
8351 ins_encode(simple_form3_mem_reg( dst, src ) );
8352 ins_pipe(istore_mem_reg);
8353 %}
8354
8355 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8356 match(Set dst (MoveD2L src));
8357 effect(DEF dst, USE src);
8358 ins_cost(MEMORY_REF_COST);
8359
8360 size(4);
8361 format %{ "STDF $src,$dst\t!MoveD2L" %}
8362 opcode(Assembler::stdf_op3);
8363 ins_encode(simple_form3_mem_reg(dst, src));
8364 ins_pipe(fstoreD_stk_reg);
8365 %}
8366
8367 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8368 match(Set dst (MoveL2D src));
8369 effect(DEF dst, USE src);
8370 ins_cost(MEMORY_REF_COST);
8371
8372 size(4);
8373 format %{ "STX $src,$dst\t!MoveL2D" %}
8374 opcode(Assembler::stx_op3);
8375 ins_encode(simple_form3_mem_reg( dst, src ) );
8376 ins_pipe(istore_mem_reg);
8377 %}
8378
8379
8380 //-----------
8381 // Long to Double conversion using V8 opcodes.
8382 // Still useful because cheetah traps and becomes
8383 // amazingly slow for some common numbers.
8384
8385 // Magic constant, 0x43300000
8386 instruct loadConI_x43300000(iRegI dst) %{
8387 effect(DEF dst);
8388 size(4);
8389 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8390 ins_encode(SetHi22(0x43300000, dst));
8391 ins_pipe(ialu_none);
8392 %}
8393
8394 // Magic constant, 0x41f00000
8395 instruct loadConI_x41f00000(iRegI dst) %{
8396 effect(DEF dst);
8397 size(4);
8398 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8399 ins_encode(SetHi22(0x41f00000, dst));
8400 ins_pipe(ialu_none);
8401 %}
8402
8403 // Construct a double from two float halves
8404 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8405 effect(DEF dst, USE src1, USE src2);
8406 size(8);
8407 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8408 "FMOVS $src2.lo,$dst.lo" %}
8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8410 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8411 ins_pipe(faddD_reg_reg);
8412 %}
8413
8414 // Convert integer in high half of a double register (in the lower half of
8415 // the double register file) to double
8416 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8417 effect(DEF dst, USE src);
8418 size(4);
8419 format %{ "FITOD $src,$dst" %}
8420 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8421 ins_encode(form3_opf_rs2D_rdD(src, dst));
8422 ins_pipe(fcvtLHi2D);
8423 %}
8424
8425 // Add float double precision
8426 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8427 effect(DEF dst, USE src1, USE src2);
8428 size(4);
8429 format %{ "FADDD $src1,$src2,$dst" %}
8430 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8431 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8432 ins_pipe(faddD_reg_reg);
8433 %}
8434
8435 // Sub float double precision
8436 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8437 effect(DEF dst, USE src1, USE src2);
8438 size(4);
8439 format %{ "FSUBD $src1,$src2,$dst" %}
8440 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8441 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8442 ins_pipe(faddD_reg_reg);
8443 %}
8444
8445 // Mul float double precision
8446 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8447 effect(DEF dst, USE src1, USE src2);
8448 size(4);
8449 format %{ "FMULD $src1,$src2,$dst" %}
8450 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8451 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8452 ins_pipe(fmulD_reg_reg);
8453 %}
8454
8455 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8456 match(Set dst (ConvL2D src));
8457 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8458
8459 expand %{
8460 regD_low tmpsrc;
8461 iRegI ix43300000;
8462 iRegI ix41f00000;
8463 stackSlotL lx43300000;
8464 stackSlotL lx41f00000;
8465 regD_low dx43300000;
8466 regD dx41f00000;
8467 regD tmp1;
8468 regD_low tmp2;
8469 regD tmp3;
8470 regD tmp4;
8471
8472 stkL_to_regD(tmpsrc, src);
8473
8474 loadConI_x43300000(ix43300000);
8475 loadConI_x41f00000(ix41f00000);
8476 regI_to_stkLHi(lx43300000, ix43300000);
8477 regI_to_stkLHi(lx41f00000, ix41f00000);
8478 stkL_to_regD(dx43300000, lx43300000);
8479 stkL_to_regD(dx41f00000, lx41f00000);
8480
8481 convI2D_regDHi_regD(tmp1, tmpsrc);
8482 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8483 subD_regD_regD(tmp3, tmp2, dx43300000);
8484 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8485 addD_regD_regD(dst, tmp3, tmp4);
8486 %}
8487 %}
8488
8489 // Long to Double conversion using fast fxtof
8490 instruct convL2D_helper(regD dst, regD tmp) %{
8491 effect(DEF dst, USE tmp);
8492 size(4);
8493 format %{ "FXTOD $tmp,$dst" %}
8494 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8495 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8496 ins_pipe(fcvtL2D);
8497 %}
8498
8499 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8500 predicate(VM_Version::has_fast_fxtof());
8501 match(Set dst (ConvL2D src));
8502 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8503 expand %{
8504 regD tmp;
8505 stkL_to_regD(tmp, src);
8506 convL2D_helper(dst, tmp);
8507 %}
8508 %}
8509
8510 //-----------
8511 // Long to Float conversion using V8 opcodes.
8512 // Still useful because cheetah traps and becomes
8513 // amazingly slow for some common numbers.
8514
8515 // Long to Float conversion using fast fxtof
8516 instruct convL2F_helper(regF dst, regD tmp) %{
8517 effect(DEF dst, USE tmp);
8518 size(4);
8519 format %{ "FXTOS $tmp,$dst" %}
8520 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8521 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8522 ins_pipe(fcvtL2F);
8523 %}
8524
8525 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8526 match(Set dst (ConvL2F src));
8527 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8528 expand %{
8529 regD tmp;
8530 stkL_to_regD(tmp, src);
8531 convL2F_helper(dst, tmp);
8532 %}
8533 %}
8534 //-----------
8535
8536 instruct convL2I_reg(iRegI dst, iRegL src) %{
8537 match(Set dst (ConvL2I src));
8538 #ifndef _LP64
8539 format %{ "MOV $src.lo,$dst\t! long->int" %}
8540 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8541 ins_pipe(ialu_move_reg_I_to_L);
8542 #else
8543 size(4);
8544 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8545 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8546 ins_pipe(ialu_reg);
8547 #endif
8548 %}
8549
8550 // Register Shift Right Immediate
8551 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8552 match(Set dst (ConvL2I (RShiftL src cnt)));
8553
8554 size(4);
8555 format %{ "SRAX $src,$cnt,$dst" %}
8556 opcode(Assembler::srax_op3, Assembler::arith_op);
8557 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8558 ins_pipe(ialu_reg_imm);
8559 %}
8560
8561 // Replicate scalar to packed byte values in Double register
8562 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8563 effect(DEF dst, USE src);
8564 format %{ "SLLX $src,56,$dst\n\t"
8565 "SRLX $dst, 8,O7\n\t"
8566 "OR $dst,O7,$dst\n\t"
8567 "SRLX $dst,16,O7\n\t"
8568 "OR $dst,O7,$dst\n\t"
8569 "SRLX $dst,32,O7\n\t"
8570 "OR $dst,O7,$dst\t! replicate8B" %}
8571 ins_encode( enc_repl8b(src, dst));
8572 ins_pipe(ialu_reg);
8573 %}
8574
8575 // Replicate scalar to packed byte values in Double register
8576 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8577 match(Set dst (Replicate8B src));
8578 expand %{
8579 iRegL tmp;
8580 Repl8B_reg_helper(tmp, src);
8581 regL_to_stkD(dst, tmp);
8582 %}
8583 %}
8584
8585 // Replicate scalar constant to packed byte values in Double register
8586 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8587 match(Set dst (Replicate8B src));
8588 #ifdef _LP64
8589 size(36);
8590 #else
8591 size(8);
8592 #endif
8593 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8594 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8595 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8596 ins_pipe(loadConFD);
8597 %}
8598
8599 // Replicate scalar to packed char values into stack slot
8600 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8601 effect(DEF dst, USE src);
8602 format %{ "SLLX $src,48,$dst\n\t"
8603 "SRLX $dst,16,O7\n\t"
8604 "OR $dst,O7,$dst\n\t"
8605 "SRLX $dst,32,O7\n\t"
8606 "OR $dst,O7,$dst\t! replicate4C" %}
8607 ins_encode( enc_repl4s(src, dst) );
8608 ins_pipe(ialu_reg);
8609 %}
8610
8611 // Replicate scalar to packed char values into stack slot
8612 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8613 match(Set dst (Replicate4C src));
8614 expand %{
8615 iRegL tmp;
8616 Repl4C_reg_helper(tmp, src);
8617 regL_to_stkD(dst, tmp);
8618 %}
8619 %}
8620
8621 // Replicate scalar constant to packed char values in Double register
8622 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8623 match(Set dst (Replicate4C src));
8624 #ifdef _LP64
8625 size(36);
8626 #else
8627 size(8);
8628 #endif
8629 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8630 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8631 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8632 ins_pipe(loadConFD);
8633 %}
8634
8635 // Replicate scalar to packed short values into stack slot
8636 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8637 effect(DEF dst, USE src);
8638 format %{ "SLLX $src,48,$dst\n\t"
8639 "SRLX $dst,16,O7\n\t"
8640 "OR $dst,O7,$dst\n\t"
8641 "SRLX $dst,32,O7\n\t"
8642 "OR $dst,O7,$dst\t! replicate4S" %}
8643 ins_encode( enc_repl4s(src, dst) );
8644 ins_pipe(ialu_reg);
8645 %}
8646
8647 // Replicate scalar to packed short values into stack slot
8648 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8649 match(Set dst (Replicate4S src));
8650 expand %{
8651 iRegL tmp;
8652 Repl4S_reg_helper(tmp, src);
8653 regL_to_stkD(dst, tmp);
8654 %}
8655 %}
8656
8657 // Replicate scalar constant to packed short values in Double register
8658 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8659 match(Set dst (Replicate4S src));
8660 #ifdef _LP64
8661 size(36);
8662 #else
8663 size(8);
8664 #endif
8665 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8666 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8667 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8668 ins_pipe(loadConFD);
8669 %}
8670
8671 // Replicate scalar to packed int values in Double register
8672 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8673 effect(DEF dst, USE src);
8674 format %{ "SLLX $src,32,$dst\n\t"
8675 "SRLX $dst,32,O7\n\t"
8676 "OR $dst,O7,$dst\t! replicate2I" %}
8677 ins_encode( enc_repl2i(src, dst));
8678 ins_pipe(ialu_reg);
8679 %}
8680
8681 // Replicate scalar to packed int values in Double register
8682 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8683 match(Set dst (Replicate2I src));
8684 expand %{
8685 iRegL tmp;
8686 Repl2I_reg_helper(tmp, src);
8687 regL_to_stkD(dst, tmp);
8688 %}
8689 %}
8690
8691 // Replicate scalar zero constant to packed int values in Double register
8692 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8693 match(Set dst (Replicate2I src));
8694 #ifdef _LP64
8695 size(36);
8696 #else
8697 size(8);
8698 #endif
8699 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8700 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8701 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8702 ins_pipe(loadConFD);
8703 %}
8704
8705 //----------Control Flow Instructions------------------------------------------
8706 // Compare Instructions
8707 // Compare Integers
8708 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8709 match(Set icc (CmpI op1 op2));
8710 effect( DEF icc, USE op1, USE op2 );
8711
8712 size(4);
8713 format %{ "CMP $op1,$op2" %}
8714 opcode(Assembler::subcc_op3, Assembler::arith_op);
8715 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8716 ins_pipe(ialu_cconly_reg_reg);
8717 %}
8718
8719 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8720 match(Set icc (CmpU op1 op2));
8721
8722 size(4);
8723 format %{ "CMP $op1,$op2\t! unsigned" %}
8724 opcode(Assembler::subcc_op3, Assembler::arith_op);
8725 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8726 ins_pipe(ialu_cconly_reg_reg);
8727 %}
8728
8729 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8730 match(Set icc (CmpI op1 op2));
8731 effect( DEF icc, USE op1 );
8732
8733 size(4);
8734 format %{ "CMP $op1,$op2" %}
8735 opcode(Assembler::subcc_op3, Assembler::arith_op);
8736 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8737 ins_pipe(ialu_cconly_reg_imm);
8738 %}
8739
8740 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8741 match(Set icc (CmpI (AndI op1 op2) zero));
8742
8743 size(4);
8744 format %{ "BTST $op2,$op1" %}
8745 opcode(Assembler::andcc_op3, Assembler::arith_op);
8746 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8747 ins_pipe(ialu_cconly_reg_reg_zero);
8748 %}
8749
8750 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8751 match(Set icc (CmpI (AndI op1 op2) zero));
8752
8753 size(4);
8754 format %{ "BTST $op2,$op1" %}
8755 opcode(Assembler::andcc_op3, Assembler::arith_op);
8756 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8757 ins_pipe(ialu_cconly_reg_imm_zero);
8758 %}
8759
8760 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8761 match(Set xcc (CmpL op1 op2));
8762 effect( DEF xcc, USE op1, USE op2 );
8763
8764 size(4);
8765 format %{ "CMP $op1,$op2\t\t! long" %}
8766 opcode(Assembler::subcc_op3, Assembler::arith_op);
8767 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8768 ins_pipe(ialu_cconly_reg_reg);
8769 %}
8770
8771 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8772 match(Set xcc (CmpL op1 con));
8773 effect( DEF xcc, USE op1, USE con );
8774
8775 size(4);
8776 format %{ "CMP $op1,$con\t\t! long" %}
8777 opcode(Assembler::subcc_op3, Assembler::arith_op);
8778 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8779 ins_pipe(ialu_cconly_reg_reg);
8780 %}
8781
8782 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8783 match(Set xcc (CmpL (AndL op1 op2) zero));
8784 effect( DEF xcc, USE op1, USE op2 );
8785
8786 size(4);
8787 format %{ "BTST $op1,$op2\t\t! long" %}
8788 opcode(Assembler::andcc_op3, Assembler::arith_op);
8789 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8790 ins_pipe(ialu_cconly_reg_reg);
8791 %}
8792
8793 // useful for checking the alignment of a pointer:
8794 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8795 match(Set xcc (CmpL (AndL op1 con) zero));
8796 effect( DEF xcc, USE op1, USE con );
8797
8798 size(4);
8799 format %{ "BTST $op1,$con\t\t! long" %}
8800 opcode(Assembler::andcc_op3, Assembler::arith_op);
8801 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8802 ins_pipe(ialu_cconly_reg_reg);
8803 %}
8804
8805 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8806 match(Set icc (CmpU op1 op2));
8807
8808 size(4);
8809 format %{ "CMP $op1,$op2\t! unsigned" %}
8810 opcode(Assembler::subcc_op3, Assembler::arith_op);
8811 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8812 ins_pipe(ialu_cconly_reg_imm);
8813 %}
8814
8815 // Compare Pointers
8816 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8817 match(Set pcc (CmpP op1 op2));
8818
8819 size(4);
8820 format %{ "CMP $op1,$op2\t! ptr" %}
8821 opcode(Assembler::subcc_op3, Assembler::arith_op);
8822 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8823 ins_pipe(ialu_cconly_reg_reg);
8824 %}
8825
8826 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8827 match(Set pcc (CmpP op1 op2));
8828
8829 size(4);
8830 format %{ "CMP $op1,$op2\t! ptr" %}
8831 opcode(Assembler::subcc_op3, Assembler::arith_op);
8832 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8833 ins_pipe(ialu_cconly_reg_imm);
8834 %}
8835
8836 // Compare Narrow oops
8837 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8838 match(Set icc (CmpN op1 op2));
8839
8840 size(4);
8841 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8842 opcode(Assembler::subcc_op3, Assembler::arith_op);
8843 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8844 ins_pipe(ialu_cconly_reg_reg);
8845 %}
8846
8847 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8848 match(Set icc (CmpN op1 op2));
8849
8850 size(4);
8851 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8852 opcode(Assembler::subcc_op3, Assembler::arith_op);
8853 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8854 ins_pipe(ialu_cconly_reg_imm);
8855 %}
8856
8857 //----------Max and Min--------------------------------------------------------
8858 // Min Instructions
8859 // Conditional move for min
8860 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8861 effect( USE_DEF op2, USE op1, USE icc );
8862
8863 size(4);
8864 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8865 opcode(Assembler::less);
8866 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8867 ins_pipe(ialu_reg_flags);
8868 %}
8869
8870 // Min Register with Register.
8871 instruct minI_eReg(iRegI op1, iRegI op2) %{
8872 match(Set op2 (MinI op1 op2));
8873 ins_cost(DEFAULT_COST*2);
8874 expand %{
8875 flagsReg icc;
8876 compI_iReg(icc,op1,op2);
8877 cmovI_reg_lt(op2,op1,icc);
8878 %}
8879 %}
8880
8881 // Max Instructions
8882 // Conditional move for max
8883 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8884 effect( USE_DEF op2, USE op1, USE icc );
8885 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8886 opcode(Assembler::greater);
8887 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8888 ins_pipe(ialu_reg_flags);
8889 %}
8890
8891 // Max Register with Register
8892 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8893 match(Set op2 (MaxI op1 op2));
8894 ins_cost(DEFAULT_COST*2);
8895 expand %{
8896 flagsReg icc;
8897 compI_iReg(icc,op1,op2);
8898 cmovI_reg_gt(op2,op1,icc);
8899 %}
8900 %}
8901
8902
8903 //----------Float Compares----------------------------------------------------
8904 // Compare floating, generate condition code
8905 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8906 match(Set fcc (CmpF src1 src2));
8907
8908 size(4);
8909 format %{ "FCMPs $fcc,$src1,$src2" %}
8910 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8911 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8912 ins_pipe(faddF_fcc_reg_reg_zero);
8913 %}
8914
8915 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8916 match(Set fcc (CmpD src1 src2));
8917
8918 size(4);
8919 format %{ "FCMPd $fcc,$src1,$src2" %}
8920 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8921 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8922 ins_pipe(faddD_fcc_reg_reg_zero);
8923 %}
8924
8925
8926 // Compare floating, generate -1,0,1
8927 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8928 match(Set dst (CmpF3 src1 src2));
8929 effect(KILL fcc0);
8930 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8931 format %{ "fcmpl $dst,$src1,$src2" %}
8932 // Primary = float
8933 opcode( true );
8934 ins_encode( floating_cmp( dst, src1, src2 ) );
8935 ins_pipe( floating_cmp );
8936 %}
8937
8938 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8939 match(Set dst (CmpD3 src1 src2));
8940 effect(KILL fcc0);
8941 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8942 format %{ "dcmpl $dst,$src1,$src2" %}
8943 // Primary = double (not float)
8944 opcode( false );
8945 ins_encode( floating_cmp( dst, src1, src2 ) );
8946 ins_pipe( floating_cmp );
8947 %}
8948
8949 //----------Branches---------------------------------------------------------
8950 // Jump
8951 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8952 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8953 match(Jump switch_val);
8954
8955 ins_cost(350);
8956
8957 format %{ "SETHI [hi(table_base)],O7\n\t"
8958 "ADD O7, lo(table_base), O7\n\t"
8959 "LD [O7+$switch_val], O7\n\t"
8960 "JUMP O7"
8961 %}
8962 ins_encode( jump_enc( switch_val, table) );
8963 ins_pc_relative(1);
8964 ins_pipe(ialu_reg_reg);
8965 %}
8966
8967 // Direct Branch. Use V8 version with longer range.
8968 instruct branch(label labl) %{
8969 match(Goto);
8970 effect(USE labl);
8971
8972 size(8);
8973 ins_cost(BRANCH_COST);
8974 format %{ "BA $labl" %}
8975 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8976 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8977 ins_encode( enc_ba( labl ) );
8978 ins_pc_relative(1);
8979 ins_pipe(br);
8980 %}
8981
8982 // Conditional Direct Branch
8983 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8984 match(If cmp icc);
8985 effect(USE labl);
8986
8987 size(8);
8988 ins_cost(BRANCH_COST);
8989 format %{ "BP$cmp $icc,$labl" %}
8990 // Prim = bits 24-22, Secnd = bits 31-30
8991 ins_encode( enc_bp( labl, cmp, icc ) );
8992 ins_pc_relative(1);
8993 ins_pipe(br_cc);
8994 %}
8995
8996 // Branch-on-register tests all 64 bits. We assume that values
8997 // in 64-bit registers always remains zero or sign extended
8998 // unless our code munges the high bits. Interrupts can chop
8999 // the high order bits to zero or sign at any time.
9000 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9001 match(If cmp (CmpI op1 zero));
9002 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9003 effect(USE labl);
9004
9005 size(8);
9006 ins_cost(BRANCH_COST);
9007 format %{ "BR$cmp $op1,$labl" %}
9008 ins_encode( enc_bpr( labl, cmp, op1 ) );
9009 ins_pc_relative(1);
9010 ins_pipe(br_reg);
9011 %}
9012
9013 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9014 match(If cmp (CmpP op1 null));
9015 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9016 effect(USE labl);
9017
9018 size(8);
9019 ins_cost(BRANCH_COST);
9020 format %{ "BR$cmp $op1,$labl" %}
9021 ins_encode( enc_bpr( labl, cmp, op1 ) );
9022 ins_pc_relative(1);
9023 ins_pipe(br_reg);
9024 %}
9025
9026 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9027 match(If cmp (CmpL op1 zero));
9028 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9029 effect(USE labl);
9030
9031 size(8);
9032 ins_cost(BRANCH_COST);
9033 format %{ "BR$cmp $op1,$labl" %}
9034 ins_encode( enc_bpr( labl, cmp, op1 ) );
9035 ins_pc_relative(1);
9036 ins_pipe(br_reg);
9037 %}
9038
9039 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9040 match(If cmp icc);
9041 effect(USE labl);
9042
9043 format %{ "BP$cmp $icc,$labl" %}
9044 // Prim = bits 24-22, Secnd = bits 31-30
9045 ins_encode( enc_bp( labl, cmp, icc ) );
9046 ins_pc_relative(1);
9047 ins_pipe(br_cc);
9048 %}
9049
9050 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9051 match(If cmp pcc);
9052 effect(USE labl);
9053
9054 size(8);
9055 ins_cost(BRANCH_COST);
9056 format %{ "BP$cmp $pcc,$labl" %}
9057 // Prim = bits 24-22, Secnd = bits 31-30
9058 ins_encode( enc_bpx( labl, cmp, pcc ) );
9059 ins_pc_relative(1);
9060 ins_pipe(br_cc);
9061 %}
9062
9063 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9064 match(If cmp fcc);
9065 effect(USE labl);
9066
9067 size(8);
9068 ins_cost(BRANCH_COST);
9069 format %{ "FBP$cmp $fcc,$labl" %}
9070 // Prim = bits 24-22, Secnd = bits 31-30
9071 ins_encode( enc_fbp( labl, cmp, fcc ) );
9072 ins_pc_relative(1);
9073 ins_pipe(br_fcc);
9074 %}
9075
9076 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9077 match(CountedLoopEnd cmp icc);
9078 effect(USE labl);
9079
9080 size(8);
9081 ins_cost(BRANCH_COST);
9082 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9083 // Prim = bits 24-22, Secnd = bits 31-30
9084 ins_encode( enc_bp( labl, cmp, icc ) );
9085 ins_pc_relative(1);
9086 ins_pipe(br_cc);
9087 %}
9088
9089 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9090 match(CountedLoopEnd cmp icc);
9091 effect(USE labl);
9092
9093 size(8);
9094 ins_cost(BRANCH_COST);
9095 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9096 // Prim = bits 24-22, Secnd = bits 31-30
9097 ins_encode( enc_bp( labl, cmp, icc ) );
9098 ins_pc_relative(1);
9099 ins_pipe(br_cc);
9100 %}
9101
9102 // ============================================================================
9103 // Long Compare
9104 //
9105 // Currently we hold longs in 2 registers. Comparing such values efficiently
9106 // is tricky. The flavor of compare used depends on whether we are testing
9107 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9108 // The GE test is the negated LT test. The LE test can be had by commuting
9109 // the operands (yielding a GE test) and then negating; negate again for the
9110 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9111 // NE test is negated from that.
9112
9113 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9114 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9115 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9116 // are collapsed internally in the ADLC's dfa-gen code. The match for
9117 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9118 // foo match ends up with the wrong leaf. One fix is to not match both
9119 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9120 // both forms beat the trinary form of long-compare and both are very useful
9121 // on Intel which has so few registers.
9122
9123 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9124 match(If cmp xcc);
9125 effect(USE labl);
9126
9127 size(8);
9128 ins_cost(BRANCH_COST);
9129 format %{ "BP$cmp $xcc,$labl" %}
9130 // Prim = bits 24-22, Secnd = bits 31-30
9131 ins_encode( enc_bpl( labl, cmp, xcc ) );
9132 ins_pc_relative(1);
9133 ins_pipe(br_cc);
9134 %}
9135
9136 // Manifest a CmpL3 result in an integer register. Very painful.
9137 // This is the test to avoid.
9138 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9139 match(Set dst (CmpL3 src1 src2) );
9140 effect( KILL ccr );
9141 ins_cost(6*DEFAULT_COST);
9142 size(24);
9143 format %{ "CMP $src1,$src2\t\t! long\n"
9144 "\tBLT,a,pn done\n"
9145 "\tMOV -1,$dst\t! delay slot\n"
9146 "\tBGT,a,pn done\n"
9147 "\tMOV 1,$dst\t! delay slot\n"
9148 "\tCLR $dst\n"
9149 "done:" %}
9150 ins_encode( cmpl_flag(src1,src2,dst) );
9151 ins_pipe(cmpL_reg);
9152 %}
9153
9154 // Conditional move
9155 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9156 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9157 ins_cost(150);
9158 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9159 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9160 ins_pipe(ialu_reg);
9161 %}
9162
9163 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9164 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9165 ins_cost(140);
9166 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9167 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9168 ins_pipe(ialu_imm);
9169 %}
9170
9171 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9172 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9173 ins_cost(150);
9174 format %{ "MOV$cmp $xcc,$src,$dst" %}
9175 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9176 ins_pipe(ialu_reg);
9177 %}
9178
9179 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9180 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9181 ins_cost(140);
9182 format %{ "MOV$cmp $xcc,$src,$dst" %}
9183 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9184 ins_pipe(ialu_imm);
9185 %}
9186
9187 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9188 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9189 ins_cost(150);
9190 format %{ "MOV$cmp $xcc,$src,$dst" %}
9191 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9192 ins_pipe(ialu_reg);
9193 %}
9194
9195 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9196 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9197 ins_cost(150);
9198 format %{ "MOV$cmp $xcc,$src,$dst" %}
9199 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9200 ins_pipe(ialu_reg);
9201 %}
9202
9203 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9204 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9205 ins_cost(140);
9206 format %{ "MOV$cmp $xcc,$src,$dst" %}
9207 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9208 ins_pipe(ialu_imm);
9209 %}
9210
9211 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9212 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9213 ins_cost(150);
9214 opcode(0x101);
9215 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9216 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9217 ins_pipe(int_conditional_float_move);
9218 %}
9219
9220 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9221 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9222 ins_cost(150);
9223 opcode(0x102);
9224 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9225 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9226 ins_pipe(int_conditional_float_move);
9227 %}
9228
9229 // ============================================================================
9230 // Safepoint Instruction
9231 instruct safePoint_poll(iRegP poll) %{
9232 match(SafePoint poll);
9233 effect(USE poll);
9234
9235 size(4);
9236 #ifdef _LP64
9237 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9238 #else
9239 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9240 #endif
9241 ins_encode %{
9242 __ relocate(relocInfo::poll_type);
9243 __ ld_ptr($poll$$Register, 0, G0);
9244 %}
9245 ins_pipe(loadPollP);
9246 %}
9247
9248 // ============================================================================
9249 // Call Instructions
9250 // Call Java Static Instruction
9251 instruct CallStaticJavaDirect( method meth ) %{
9252 match(CallStaticJava);
9253 effect(USE meth);
9254
9255 size(8);
9256 ins_cost(CALL_COST);
9257 format %{ "CALL,static ; NOP ==> " %}
9258 ins_encode( Java_Static_Call( meth ), call_epilog );
9259 ins_pc_relative(1);
9260 ins_pipe(simple_call);
9261 %}
9262
9263 // Call Java Dynamic Instruction
9264 instruct CallDynamicJavaDirect( method meth ) %{
9265 match(CallDynamicJava);
9266 effect(USE meth);
9267
9268 ins_cost(CALL_COST);
9269 format %{ "SET (empty),R_G5\n\t"
9270 "CALL,dynamic ; NOP ==> " %}
9271 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9272 ins_pc_relative(1);
9273 ins_pipe(call);
9274 %}
9275
9276 // Call Runtime Instruction
9277 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9278 match(CallRuntime);
9279 effect(USE meth, KILL l7);
9280 ins_cost(CALL_COST);
9281 format %{ "CALL,runtime" %}
9282 ins_encode( Java_To_Runtime( meth ),
9283 call_epilog, adjust_long_from_native_call );
9284 ins_pc_relative(1);
9285 ins_pipe(simple_call);
9286 %}
9287
9288 // Call runtime without safepoint - same as CallRuntime
9289 instruct CallLeafDirect(method meth, l7RegP l7) %{
9290 match(CallLeaf);
9291 effect(USE meth, KILL l7);
9292 ins_cost(CALL_COST);
9293 format %{ "CALL,runtime leaf" %}
9294 ins_encode( Java_To_Runtime( meth ),
9295 call_epilog,
9296 adjust_long_from_native_call );
9297 ins_pc_relative(1);
9298 ins_pipe(simple_call);
9299 %}
9300
9301 // Call runtime without safepoint - same as CallLeaf
9302 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9303 match(CallLeafNoFP);
9304 effect(USE meth, KILL l7);
9305 ins_cost(CALL_COST);
9306 format %{ "CALL,runtime leaf nofp" %}
9307 ins_encode( Java_To_Runtime( meth ),
9308 call_epilog,
9309 adjust_long_from_native_call );
9310 ins_pc_relative(1);
9311 ins_pipe(simple_call);
9312 %}
9313
9314 // Tail Call; Jump from runtime stub to Java code.
9315 // Also known as an 'interprocedural jump'.
9316 // Target of jump will eventually return to caller.
9317 // TailJump below removes the return address.
9318 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9319 match(TailCall jump_target method_oop );
9320
9321 ins_cost(CALL_COST);
9322 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9323 ins_encode(form_jmpl(jump_target));
9324 ins_pipe(tail_call);
9325 %}
9326
9327
9328 // Return Instruction
9329 instruct Ret() %{
9330 match(Return);
9331
9332 // The epilogue node did the ret already.
9333 size(0);
9334 format %{ "! return" %}
9335 ins_encode();
9336 ins_pipe(empty);
9337 %}
9338
9339
9340 // Tail Jump; remove the return address; jump to target.
9341 // TailCall above leaves the return address around.
9342 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9343 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9344 // "restore" before this instruction (in Epilogue), we need to materialize it
9345 // in %i0.
9346 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9347 match( TailJump jump_target ex_oop );
9348 ins_cost(CALL_COST);
9349 format %{ "! discard R_O7\n\t"
9350 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9351 ins_encode(form_jmpl_set_exception_pc(jump_target));
9352 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9353 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9354 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9355 ins_pipe(tail_call);
9356 %}
9357
9358 // Create exception oop: created by stack-crawling runtime code.
9359 // Created exception is now available to this handler, and is setup
9360 // just prior to jumping to this handler. No code emitted.
9361 instruct CreateException( o0RegP ex_oop )
9362 %{
9363 match(Set ex_oop (CreateEx));
9364 ins_cost(0);
9365
9366 size(0);
9367 // use the following format syntax
9368 format %{ "! exception oop is in R_O0; no code emitted" %}
9369 ins_encode();
9370 ins_pipe(empty);
9371 %}
9372
9373
9374 // Rethrow exception:
9375 // The exception oop will come in the first argument position.
9376 // Then JUMP (not call) to the rethrow stub code.
9377 instruct RethrowException()
9378 %{
9379 match(Rethrow);
9380 ins_cost(CALL_COST);
9381
9382 // use the following format syntax
9383 format %{ "Jmp rethrow_stub" %}
9384 ins_encode(enc_rethrow);
9385 ins_pipe(tail_call);
9386 %}
9387
9388
9389 // Die now
9390 instruct ShouldNotReachHere( )
9391 %{
9392 match(Halt);
9393 ins_cost(CALL_COST);
9394
9395 size(4);
9396 // Use the following format syntax
9397 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9398 ins_encode( form2_illtrap() );
9399 ins_pipe(tail_call);
9400 %}
9401
9402 // ============================================================================
9403 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9404 // array for an instance of the superklass. Set a hidden internal cache on a
9405 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9406 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9407 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9408 match(Set index (PartialSubtypeCheck sub super));
9409 effect( KILL pcc, KILL o7 );
9410 ins_cost(DEFAULT_COST*10);
9411 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9412 ins_encode( enc_PartialSubtypeCheck() );
9413 ins_pipe(partial_subtype_check_pipe);
9414 %}
9415
9416 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9417 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9418 effect( KILL idx, KILL o7 );
9419 ins_cost(DEFAULT_COST*10);
9420 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9421 ins_encode( enc_PartialSubtypeCheck() );
9422 ins_pipe(partial_subtype_check_pipe);
9423 %}
9424
9425
9426 // ============================================================================
9427 // inlined locking and unlocking
9428
9429 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9430 match(Set pcc (FastLock object box));
9431
9432 effect(KILL scratch, TEMP scratch2);
9433 ins_cost(100);
9434
9435 size(4*112); // conservative overestimation ...
9436 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9437 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9438 ins_pipe(long_memory_op);
9439 %}
9440
9441
9442 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9443 match(Set pcc (FastUnlock object box));
9444 effect(KILL scratch, TEMP scratch2);
9445 ins_cost(100);
9446
9447 size(4*120); // conservative overestimation ...
9448 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9449 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9450 ins_pipe(long_memory_op);
9451 %}
9452
9453 // Count and Base registers are fixed because the allocator cannot
9454 // kill unknown registers. The encodings are generic.
9455 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9456 match(Set dummy (ClearArray cnt base));
9457 effect(TEMP temp, KILL ccr);
9458 ins_cost(300);
9459 format %{ "MOV $cnt,$temp\n"
9460 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9461 " BRge loop\t\t! Clearing loop\n"
9462 " STX G0,[$base+$temp]\t! delay slot" %}
9463 ins_encode( enc_Clear_Array(cnt, base, temp) );
9464 ins_pipe(long_memory_op);
9465 %}
9466
9467 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9468 o7RegI tmp, flagsReg ccr) %{
9469 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9470 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9471 ins_cost(300);
9472 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9473 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9474 ins_pipe(long_memory_op);
9475 %}
9476
9477 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9478 o7RegI tmp, flagsReg ccr) %{
9479 match(Set result (StrEquals (Binary str1 str2) cnt));
9480 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9481 ins_cost(300);
9482 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9483 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9484 ins_pipe(long_memory_op);
9485 %}
9486
9487 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9488 o7RegI tmp2, flagsReg ccr) %{
9489 match(Set result (AryEq ary1 ary2));
9490 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9491 ins_cost(300);
9492 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9493 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9494 ins_pipe(long_memory_op);
9495 %}
9496
9497
9498 //---------- Zeros Count Instructions ------------------------------------------
9499
9500 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9501 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9502 match(Set dst (CountLeadingZerosI src));
9503 effect(TEMP dst, TEMP tmp, KILL cr);
9504
9505 // x |= (x >> 1);
9506 // x |= (x >> 2);
9507 // x |= (x >> 4);
9508 // x |= (x >> 8);
9509 // x |= (x >> 16);
9510 // return (WORDBITS - popc(x));
9511 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9512 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9513 "OR $dst,$tmp,$dst\n\t"
9514 "SRL $dst,2,$tmp\n\t"
9515 "OR $dst,$tmp,$dst\n\t"
9516 "SRL $dst,4,$tmp\n\t"
9517 "OR $dst,$tmp,$dst\n\t"
9518 "SRL $dst,8,$tmp\n\t"
9519 "OR $dst,$tmp,$dst\n\t"
9520 "SRL $dst,16,$tmp\n\t"
9521 "OR $dst,$tmp,$dst\n\t"
9522 "POPC $dst,$dst\n\t"
9523 "MOV 32,$tmp\n\t"
9524 "SUB $tmp,$dst,$dst" %}
9525 ins_encode %{
9526 Register Rdst = $dst$$Register;
9527 Register Rsrc = $src$$Register;
9528 Register Rtmp = $tmp$$Register;
9529 __ srl(Rsrc, 1, Rtmp);
9530 __ srl(Rsrc, 0, Rdst);
9531 __ or3(Rdst, Rtmp, Rdst);
9532 __ srl(Rdst, 2, Rtmp);
9533 __ or3(Rdst, Rtmp, Rdst);
9534 __ srl(Rdst, 4, Rtmp);
9535 __ or3(Rdst, Rtmp, Rdst);
9536 __ srl(Rdst, 8, Rtmp);
9537 __ or3(Rdst, Rtmp, Rdst);
9538 __ srl(Rdst, 16, Rtmp);
9539 __ or3(Rdst, Rtmp, Rdst);
9540 __ popc(Rdst, Rdst);
9541 __ mov(BitsPerInt, Rtmp);
9542 __ sub(Rtmp, Rdst, Rdst);
9543 %}
9544 ins_pipe(ialu_reg);
9545 %}
9546
9547 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
9548 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9549 match(Set dst (CountLeadingZerosL src));
9550 effect(TEMP dst, TEMP tmp, KILL cr);
9551
9552 // x |= (x >> 1);
9553 // x |= (x >> 2);
9554 // x |= (x >> 4);
9555 // x |= (x >> 8);
9556 // x |= (x >> 16);
9557 // x |= (x >> 32);
9558 // return (WORDBITS - popc(x));
9559 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9560 "OR $src,$tmp,$dst\n\t"
9561 "SRLX $dst,2,$tmp\n\t"
9562 "OR $dst,$tmp,$dst\n\t"
9563 "SRLX $dst,4,$tmp\n\t"
9564 "OR $dst,$tmp,$dst\n\t"
9565 "SRLX $dst,8,$tmp\n\t"
9566 "OR $dst,$tmp,$dst\n\t"
9567 "SRLX $dst,16,$tmp\n\t"
9568 "OR $dst,$tmp,$dst\n\t"
9569 "SRLX $dst,32,$tmp\n\t"
9570 "OR $dst,$tmp,$dst\n\t"
9571 "POPC $dst,$dst\n\t"
9572 "MOV 64,$tmp\n\t"
9573 "SUB $tmp,$dst,$dst" %}
9574 ins_encode %{
9575 Register Rdst = $dst$$Register;
9576 Register Rsrc = $src$$Register;
9577 Register Rtmp = $tmp$$Register;
9578 __ srlx(Rsrc, 1, Rtmp);
9579 __ or3(Rsrc, Rtmp, Rdst);
9580 __ srlx(Rdst, 2, Rtmp);
9581 __ or3(Rdst, Rtmp, Rdst);
9582 __ srlx(Rdst, 4, Rtmp);
9583 __ or3(Rdst, Rtmp, Rdst);
9584 __ srlx(Rdst, 8, Rtmp);
9585 __ or3(Rdst, Rtmp, Rdst);
9586 __ srlx(Rdst, 16, Rtmp);
9587 __ or3(Rdst, Rtmp, Rdst);
9588 __ srlx(Rdst, 32, Rtmp);
9589 __ or3(Rdst, Rtmp, Rdst);
9590 __ popc(Rdst, Rdst);
9591 __ mov(BitsPerLong, Rtmp);
9592 __ sub(Rtmp, Rdst, Rdst);
9593 %}
9594 ins_pipe(ialu_reg);
9595 %}
9596
9597 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9598 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9599 match(Set dst (CountTrailingZerosI src));
9600 effect(TEMP dst, KILL cr);
9601
9602 // return popc(~x & (x - 1));
9603 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9604 "ANDN $dst,$src,$dst\n\t"
9605 "SRL $dst,R_G0,$dst\n\t"
9606 "POPC $dst,$dst" %}
9607 ins_encode %{
9608 Register Rdst = $dst$$Register;
9609 Register Rsrc = $src$$Register;
9610 __ sub(Rsrc, 1, Rdst);
9611 __ andn(Rdst, Rsrc, Rdst);
9612 __ srl(Rdst, G0, Rdst);
9613 __ popc(Rdst, Rdst);
9614 %}
9615 ins_pipe(ialu_reg);
9616 %}
9617
9618 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9619 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9620 match(Set dst (CountTrailingZerosL src));
9621 effect(TEMP dst, KILL cr);
9622
9623 // return popc(~x & (x - 1));
9624 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9625 "ANDN $dst,$src,$dst\n\t"
9626 "POPC $dst,$dst" %}
9627 ins_encode %{
9628 Register Rdst = $dst$$Register;
9629 Register Rsrc = $src$$Register;
9630 __ sub(Rsrc, 1, Rdst);
9631 __ andn(Rdst, Rsrc, Rdst);
9632 __ popc(Rdst, Rdst);
9633 %}
9634 ins_pipe(ialu_reg);
9635 %}
9636
9637
9638 //---------- Population Count Instructions -------------------------------------
9639
9640 instruct popCountI(iRegI dst, iRegI src) %{
9641 predicate(UsePopCountInstruction);
9642 match(Set dst (PopCountI src));
9643
9644 format %{ "POPC $src, $dst" %}
9645 ins_encode %{
9646 __ popc($src$$Register, $dst$$Register);
9647 %}
9648 ins_pipe(ialu_reg);
9649 %}
9650
9651 // Note: Long.bitCount(long) returns an int.
9652 instruct popCountL(iRegI dst, iRegL src) %{
9653 predicate(UsePopCountInstruction);
9654 match(Set dst (PopCountL src));
9655
9656 format %{ "POPC $src, $dst" %}
9657 ins_encode %{
9658 __ popc($src$$Register, $dst$$Register);
9659 %}
9660 ins_pipe(ialu_reg);
9661 %}
9662
9663
9664 // ============================================================================
9665 //------------Bytes reverse--------------------------------------------------
9666
9667 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9668 match(Set dst (ReverseBytesI src));
9669 effect(DEF dst, USE src);
9670
9671 // Op cost is artificially doubled to make sure that load or store
9672 // instructions are preferred over this one which requires a spill
9673 // onto a stack slot.
9674 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9675 size(8);
9676 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9677 opcode(Assembler::lduwa_op3);
9678 ins_encode( form3_mem_reg_little(src, dst) );
9679 ins_pipe( iload_mem );
9680 %}
9681
9682 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9683 match(Set dst (ReverseBytesL src));
9684 effect(DEF dst, USE src);
9685
9686 // Op cost is artificially doubled to make sure that load or store
9687 // instructions are preferred over this one which requires a spill
9688 // onto a stack slot.
9689 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9690 size(8);
9691 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9692
9693 opcode(Assembler::ldxa_op3);
9694 ins_encode( form3_mem_reg_little(src, dst) );
9695 ins_pipe( iload_mem );
9696 %}
9697
9698 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9699 match(Set dst (ReverseBytesUS src));
9700 effect(DEF dst, USE src);
9701
9702 // Op cost is artificially doubled to make sure that load or store
9703 // instructions are preferred over this one which requires a spill
9704 // onto a stack slot.
9705 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9706 size(8);
9707 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9708
9709 ins_encode %{
9710 int disp = $src$$disp;
9711 Register index = $src$$index;
9712 Register base = $src$$base;
9713 if (base == SP || base == FP) {
9714 disp += STACK_BIAS;
9715 }
9716 if (disp != 0) {
9717 index = O7;
9718 __ set(disp, index);
9719 }
9720 __ lduha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
9721 %}
9722
9723 ins_pipe( iload_mem );
9724 %}
9725
9726 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9727 match(Set dst (ReverseBytesS src));
9728 effect(DEF dst, USE src);
9729
9730 // Op cost is artificially doubled to make sure that load or store
9731 // instructions are preferred over this one which requires a spill
9732 // onto a stack slot.
9733 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9734 size(8);
9735 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9736
9737 ins_encode %{
9738 int disp = $src$$disp;
9739 Register index = $src$$index;
9740 Register base = $src$$base;
9741 if (base == SP || base == FP) {
9742 disp += STACK_BIAS;
9743 }
9744 if (disp != 0) {
9745 index = O7;
9746 __ set(disp, index);
9747 }
9748 __ ldsha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
9749 %}
9750
9751 ins_pipe( iload_mem );
9752 %}
9753
9754 // Load Integer reversed byte order
9755 instruct loadI_reversed(iRegI dst, memory src) %{
9756 match(Set dst (ReverseBytesI (LoadI src)));
9757
9758 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9759 size(8);
9760 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9761
9762 opcode(Assembler::lduwa_op3);
9763 ins_encode( form3_mem_reg_little( src, dst) );
9764 ins_pipe(iload_mem);
9765 %}
9766
9767 // Load Long - aligned and reversed
9768 instruct loadL_reversed(iRegL dst, memory src) %{
9769 match(Set dst (ReverseBytesL (LoadL src)));
9770
9771 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9772 size(8);
9773 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9774
9775 opcode(Assembler::ldxa_op3);
9776 ins_encode( form3_mem_reg_little( src, dst ) );
9777 ins_pipe(iload_mem);
9778 %}
9779
9780 // Load unsigned short / char reversed byte order
9781 instruct loadUS_reversed(iRegI dst, memory src) %{
9782 match(Set dst (ReverseBytesUS (LoadUS src)));
9783
9784 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9785 size(8);
9786 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9787
9788 ins_encode %{
9789 int disp = $src$$disp;
9790 Register index = $src$$index;
9791 Register base = $src$$base;
9792 if (base == SP || base == FP) {
9793 disp += STACK_BIAS;
9794 }
9795 if (disp != 0) {
9796 index = O7;
9797 __ set(disp, index);
9798 }
9799 __ lduha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
9800 %}
9801
9802 ins_pipe(iload_mem);
9803 %}
9804
9805 // Load short reversed byte order
9806 instruct loadS_reversed(iRegI dst, memory src) %{
9807 match(Set dst (ReverseBytesS (LoadS src)));
9808
9809 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9810 size(8);
9811 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9812
9813 ins_encode %{
9814 int disp = $src$$disp;
9815 Register index = $src$$index;
9816 Register base = $src$$base;
9817 if (base == SP || base == FP) {
9818 disp += STACK_BIAS;
9819 }
9820 if (disp != 0) {
9821 index = O7;
9822 __ set(disp, index);
9823 }
9824 __ ldsha(base, index, Assembler::ASI_PRIMARY_LITTLE, $dst$$reg);
9825 %}
9826
9827 ins_pipe(iload_mem);
9828 %}
9829
9830 // Store Integer reversed byte order
9831 instruct storeI_reversed(memory dst, iRegI src) %{
9832 match(Set dst (StoreI dst (ReverseBytesI src)));
9833
9834 ins_cost(MEMORY_REF_COST);
9835 size(8);
9836 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9837
9838 opcode(Assembler::stwa_op3);
9839 ins_encode( form3_mem_reg_little( dst, src) );
9840 ins_pipe(istore_mem_reg);
9841 %}
9842
9843 // Store Long reversed byte order
9844 instruct storeL_reversed(memory dst, iRegL src) %{
9845 match(Set dst (StoreL dst (ReverseBytesL src)));
9846
9847 ins_cost(MEMORY_REF_COST);
9848 size(8);
9849 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9850
9851 opcode(Assembler::stxa_op3);
9852 ins_encode( form3_mem_reg_little( dst, src) );
9853 ins_pipe(istore_mem_reg);
9854 %}
9855
9856 // Store unsighed short/char reversed byte order
9857 instruct storeUS_reversed(memory dst, iRegI src) %{
9858 match(Set dst (StoreUS dst (ReverseBytesUS src)));
9859
9860 ins_cost(MEMORY_REF_COST);
9861 size(8);
9862 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9863
9864 ins_encode %{
9865 int disp = $dst$$disp;
9866 Register index = $dst$index;
9867 Register base = $dst$$base;
9868 if (base == SP || base == FP) {
9869 disp += STACK_BIAS;
9870 }
9871 if (disp != 0) {
9872 index = O7;
9873 __ set(disp, index);
9874 }
9875 __ stha($src$$reg, base, index, Assembler::ASI_PRIMARY_LITTLE);
9876 %}
9877
9878 ins_pipe(istore_mem_reg);
9879 %}
9880
9881 // Store short reversed byte order
9882 instruct storeS_reversed(memory dst, iRegI src) %{
9883 match(Set dst (StoreS dst (ReverseBytesS src)));
9884
9885 ins_cost(MEMORY_REF_COST);
9886 size(8);
9887 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9888
9889 ins_encode %{
9890 int disp = $dst$$disp;
9891 Register index = $dst$index;
9892 Register base = $dst$$base;
9893 if (base == SP || base == FP) {
9894 disp += STACK_BIAS;
9895 }
9896 if (disp != 0) {
9897 index = O7;
9898 __ set(disp, index);
9899 }
9900 __ stha($src$$reg, base, index, Assembler::ASI_PRIMARY_LITTLE);
9901 %}
9902
9903 ins_pipe(istore_mem_reg);
9904 %}
9905
9906 //----------PEEPHOLE RULES-----------------------------------------------------
9907 // These must follow all instruction definitions as they use the names
9908 // defined in the instructions definitions.
9909 //
9910 // peepmatch ( root_instr_name [preceding_instruction]* );
9911 //
9912 // peepconstraint %{
9913 // (instruction_number.operand_name relational_op instruction_number.operand_name
9914 // [, ...] );
9915 // // instruction numbers are zero-based using left to right order in peepmatch
9916 //
9917 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9918 // // provide an instruction_number.operand_name for each operand that appears
9919 // // in the replacement instruction's match rule
9920 //
9921 // ---------VM FLAGS---------------------------------------------------------
9922 //
9923 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9924 //
9925 // Each peephole rule is given an identifying number starting with zero and
9926 // increasing by one in the order seen by the parser. An individual peephole
9927 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9928 // on the command-line.
9929 //
9930 // ---------CURRENT LIMITATIONS----------------------------------------------
9931 //
9932 // Only match adjacent instructions in same basic block
9933 // Only equality constraints
9934 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9935 // Only one replacement instruction
9936 //
9937 // ---------EXAMPLE----------------------------------------------------------
9938 //
9939 // // pertinent parts of existing instructions in architecture description
9940 // instruct movI(eRegI dst, eRegI src) %{
9941 // match(Set dst (CopyI src));
9942 // %}
9943 //
9944 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9945 // match(Set dst (AddI dst src));
9946 // effect(KILL cr);
9947 // %}
9948 //
9949 // // Change (inc mov) to lea
9950 // peephole %{
9951 // // increment preceeded by register-register move
9952 // peepmatch ( incI_eReg movI );
9953 // // require that the destination register of the increment
9954 // // match the destination register of the move
9955 // peepconstraint ( 0.dst == 1.dst );
9956 // // construct a replacement instruction that sets
9957 // // the destination to ( move's source register + one )
9958 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9959 // %}
9960 //
9961
9962 // // Change load of spilled value to only a spill
9963 // instruct storeI(memory mem, eRegI src) %{
9964 // match(Set mem (StoreI mem src));
9965 // %}
9966 //
9967 // instruct loadI(eRegI dst, memory mem) %{
9968 // match(Set dst (LoadI mem));
9969 // %}
9970 //
9971 // peephole %{
9972 // peepmatch ( loadI storeI );
9973 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9974 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9975 // %}
9976
9977 //----------SMARTSPILL RULES---------------------------------------------------
9978 // These must follow all instruction definitions as they use the names
9979 // defined in the instructions definitions.
9980 //
9981 // SPARC will probably not have any of these rules due to RISC instruction set.
9982
9983 //----------PIPELINE-----------------------------------------------------------
9984 // Rules which define the behavior of the target architectures pipeline.