1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
242
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
246
247 #define __ _masm.
248
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
251
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
255
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
266
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
269
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
275
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
282
283 static int preserve_SP_size() {
284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
296
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
300
301 static int sizeof_FFree_Float_Stack_All = -1;
302
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
307
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
313
314 //
315 // Compute padding required for nodes which need alignment
316 //
317
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
325
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
334
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
343
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
349
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 *(cbuf.code_end()) = c;
354 cbuf.set_code_end(cbuf.code_end() + 1);
355 }
356
357 // EMIT_CC()
358 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
359 unsigned char c = (unsigned char)( f1 | f2 );
360 *(cbuf.code_end()) = c;
361 cbuf.set_code_end(cbuf.code_end() + 1);
362 }
363
364 // EMIT_OPCODE()
365 void emit_opcode(CodeBuffer &cbuf, int code) {
366 *(cbuf.code_end()) = (unsigned char)code;
367 cbuf.set_code_end(cbuf.code_end() + 1);
368 }
369
370 // EMIT_OPCODE() w/ relocation information
371 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
372 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
373 emit_opcode(cbuf, code);
374 }
375
376 // EMIT_D8()
377 void emit_d8(CodeBuffer &cbuf, int d8) {
378 *(cbuf.code_end()) = (unsigned char)d8;
379 cbuf.set_code_end(cbuf.code_end() + 1);
380 }
381
382 // EMIT_D16()
383 void emit_d16(CodeBuffer &cbuf, int d16) {
384 *((short *)(cbuf.code_end())) = d16;
385 cbuf.set_code_end(cbuf.code_end() + 2);
386 }
387
388 // EMIT_D32()
389 void emit_d32(CodeBuffer &cbuf, int d32) {
390 *((int *)(cbuf.code_end())) = d32;
391 cbuf.set_code_end(cbuf.code_end() + 4);
392 }
393
394 // emit 32 bit value and construct relocation entry from relocInfo::relocType
395 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
396 int format) {
397 cbuf.relocate(cbuf.inst_mark(), reloc, format);
398
399 *((int *)(cbuf.code_end())) = d32;
400 cbuf.set_code_end(cbuf.code_end() + 4);
401 }
402
403 // emit 32 bit value and construct relocation entry from RelocationHolder
404 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
405 int format) {
406 #ifdef ASSERT
407 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
408 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
409 }
410 #endif
411 cbuf.relocate(cbuf.inst_mark(), rspec, format);
412
413 *((int *)(cbuf.code_end())) = d32;
414 cbuf.set_code_end(cbuf.code_end() + 4);
415 }
416
417 // Access stack slot for load or store
418 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
419 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
420 if( -128 <= disp && disp <= 127 ) {
421 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
422 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
423 emit_d8 (cbuf, disp); // Displacement // R/M byte
424 } else {
425 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
426 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
427 emit_d32(cbuf, disp); // Displacement // R/M byte
428 }
429 }
430
431 // eRegI ereg, memory mem) %{ // emit_reg_mem
432 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
433 // There is no index & no scale, use form without SIB byte
434 if ((index == 0x4) &&
435 (scale == 0) && (base != ESP_enc)) {
436 // If no displacement, mode is 0x0; unless base is [EBP]
437 if ( (displace == 0) && (base != EBP_enc) ) {
438 emit_rm(cbuf, 0x0, reg_encoding, base);
439 }
440 else { // If 8-bit displacement, mode 0x1
441 if ((displace >= -128) && (displace <= 127)
442 && !(displace_is_oop) ) {
443 emit_rm(cbuf, 0x1, reg_encoding, base);
444 emit_d8(cbuf, displace);
445 }
446 else { // If 32-bit displacement
447 if (base == -1) { // Special flag for absolute address
448 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
449 // (manual lies; no SIB needed here)
450 if ( displace_is_oop ) {
451 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
452 } else {
453 emit_d32 (cbuf, displace);
454 }
455 }
456 else { // Normal base + offset
457 emit_rm(cbuf, 0x2, reg_encoding, base);
458 if ( displace_is_oop ) {
459 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
460 } else {
461 emit_d32 (cbuf, displace);
462 }
463 }
464 }
465 }
466 }
467 else { // Else, encode with the SIB byte
468 // If no displacement, mode is 0x0; unless base is [EBP]
469 if (displace == 0 && (base != EBP_enc)) { // If no displacement
470 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
471 emit_rm(cbuf, scale, index, base);
472 }
473 else { // If 8-bit displacement, mode 0x1
474 if ((displace >= -128) && (displace <= 127)
475 && !(displace_is_oop) ) {
476 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
477 emit_rm(cbuf, scale, index, base);
478 emit_d8(cbuf, displace);
479 }
480 else { // If 32-bit displacement
481 if (base == 0x04 ) {
482 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
483 emit_rm(cbuf, scale, index, 0x04);
484 } else {
485 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
486 emit_rm(cbuf, scale, index, base);
487 }
488 if ( displace_is_oop ) {
489 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
490 } else {
491 emit_d32 (cbuf, displace);
492 }
493 }
494 }
495 }
496 }
497
498
499 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
500 if( dst_encoding == src_encoding ) {
501 // reg-reg copy, use an empty encoding
502 } else {
503 emit_opcode( cbuf, 0x8B );
504 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
505 }
506 }
507
508 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
509 if( dst_encoding == src_encoding ) {
510 // reg-reg copy, use an empty encoding
511 } else {
512 MacroAssembler _masm(&cbuf);
513
514 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
515 }
516 }
517
518
519 //=============================================================================
520 #ifndef PRODUCT
521 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
522 Compile* C = ra_->C;
523 if( C->in_24_bit_fp_mode() ) {
524 st->print("FLDCW 24 bit fpu control word");
525 st->print_cr(""); st->print("\t");
526 }
527
528 int framesize = C->frame_slots() << LogBytesPerInt;
529 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
530 // Remove two words for return addr and rbp,
531 framesize -= 2*wordSize;
532
533 // Calls to C2R adapters often do not accept exceptional returns.
534 // We require that their callers must bang for them. But be careful, because
535 // some VM calls (such as call site linkage) can use several kilobytes of
536 // stack. But the stack safety zone should account for that.
537 // See bugs 4446381, 4468289, 4497237.
538 if (C->need_stack_bang(framesize)) {
539 st->print_cr("# stack bang"); st->print("\t");
540 }
541 st->print_cr("PUSHL EBP"); st->print("\t");
542
543 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
544 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
545 st->print_cr(""); st->print("\t");
546 framesize -= wordSize;
547 }
548
549 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
550 if (framesize) {
551 st->print("SUB ESP,%d\t# Create frame",framesize);
552 }
553 } else {
554 st->print("SUB ESP,%d\t# Create frame",framesize);
555 }
556 }
557 #endif
558
559
560 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
561 Compile* C = ra_->C;
562
563 if (UseSSE >= 2 && VerifyFPU) {
564 MacroAssembler masm(&cbuf);
565 masm.verify_FPU(0, "FPU stack must be clean on entry");
566 }
567
568 // WARNING: Initial instruction MUST be 5 bytes or longer so that
569 // NativeJump::patch_verified_entry will be able to patch out the entry
570 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
571 // depth is ok at 5 bytes, the frame allocation can be either 3 or
572 // 6 bytes. So if we don't do the fldcw or the push then we must
573 // use the 6 byte frame allocation even if we have no frame. :-(
574 // If method sets FPU control word do it now
575 if( C->in_24_bit_fp_mode() ) {
576 MacroAssembler masm(&cbuf);
577 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
578 }
579
580 int framesize = C->frame_slots() << LogBytesPerInt;
581 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
582 // Remove two words for return addr and rbp,
583 framesize -= 2*wordSize;
584
585 // Calls to C2R adapters often do not accept exceptional returns.
586 // We require that their callers must bang for them. But be careful, because
587 // some VM calls (such as call site linkage) can use several kilobytes of
588 // stack. But the stack safety zone should account for that.
589 // See bugs 4446381, 4468289, 4497237.
590 if (C->need_stack_bang(framesize)) {
591 MacroAssembler masm(&cbuf);
592 masm.generate_stack_overflow_check(framesize);
593 }
594
595 // We always push rbp, so that on return to interpreter rbp, will be
596 // restored correctly and we can correct the stack.
597 emit_opcode(cbuf, 0x50 | EBP_enc);
598
599 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
600 emit_opcode(cbuf, 0x68); // push 0xbadb100d
601 emit_d32(cbuf, 0xbadb100d);
602 framesize -= wordSize;
603 }
604
605 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
606 if (framesize) {
607 emit_opcode(cbuf, 0x83); // sub SP,#framesize
608 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
609 emit_d8(cbuf, framesize);
610 }
611 } else {
612 emit_opcode(cbuf, 0x81); // sub SP,#framesize
613 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
614 emit_d32(cbuf, framesize);
615 }
616 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
617
618 #ifdef ASSERT
619 if (VerifyStackAtCalls) {
620 Label L;
621 MacroAssembler masm(&cbuf);
622 masm.push(rax);
623 masm.mov(rax, rsp);
624 masm.andptr(rax, StackAlignmentInBytes-1);
625 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
626 masm.pop(rax);
627 masm.jcc(Assembler::equal, L);
628 masm.stop("Stack is not properly aligned!");
629 masm.bind(L);
630 }
631 #endif
632
633 }
634
635 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
636 return MachNode::size(ra_); // too many variables; just compute it the hard way
637 }
638
639 int MachPrologNode::reloc() const {
640 return 0; // a large enough number
641 }
642
643 //=============================================================================
644 #ifndef PRODUCT
645 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
646 Compile *C = ra_->C;
647 int framesize = C->frame_slots() << LogBytesPerInt;
648 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
649 // Remove two words for return addr and rbp,
650 framesize -= 2*wordSize;
651
652 if( C->in_24_bit_fp_mode() ) {
653 st->print("FLDCW standard control word");
654 st->cr(); st->print("\t");
655 }
656 if( framesize ) {
657 st->print("ADD ESP,%d\t# Destroy frame",framesize);
658 st->cr(); st->print("\t");
659 }
660 st->print_cr("POPL EBP"); st->print("\t");
661 if( do_polling() && C->is_method_compilation() ) {
662 st->print("TEST PollPage,EAX\t! Poll Safepoint");
663 st->cr(); st->print("\t");
664 }
665 }
666 #endif
667
668 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
669 Compile *C = ra_->C;
670
671 // If method set FPU control word, restore to standard control word
672 if( C->in_24_bit_fp_mode() ) {
673 MacroAssembler masm(&cbuf);
674 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
675 }
676
677 int framesize = C->frame_slots() << LogBytesPerInt;
678 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
679 // Remove two words for return addr and rbp,
680 framesize -= 2*wordSize;
681
682 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
683
684 if( framesize >= 128 ) {
685 emit_opcode(cbuf, 0x81); // add SP, #framesize
686 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
687 emit_d32(cbuf, framesize);
688 }
689 else if( framesize ) {
690 emit_opcode(cbuf, 0x83); // add SP, #framesize
691 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
692 emit_d8(cbuf, framesize);
693 }
694
695 emit_opcode(cbuf, 0x58 | EBP_enc);
696
697 if( do_polling() && C->is_method_compilation() ) {
698 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
699 emit_opcode(cbuf,0x85);
700 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
701 emit_d32(cbuf, (intptr_t)os::get_polling_page());
702 }
703 }
704
705 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
706 Compile *C = ra_->C;
707 // If method set FPU control word, restore to standard control word
708 int size = C->in_24_bit_fp_mode() ? 6 : 0;
709 if( do_polling() && C->is_method_compilation() ) size += 6;
710
711 int framesize = C->frame_slots() << LogBytesPerInt;
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
713 // Remove two words for return addr and rbp,
714 framesize -= 2*wordSize;
715
716 size++; // popl rbp,
717
718 if( framesize >= 128 ) {
719 size += 6;
720 } else {
721 size += framesize ? 3 : 0;
722 }
723 return size;
724 }
725
726 int MachEpilogNode::reloc() const {
727 return 0; // a large enough number
728 }
729
730 const Pipeline * MachEpilogNode::pipeline() const {
731 return MachNode::pipeline_class();
732 }
733
734 int MachEpilogNode::safepoint_offset() const { return 0; }
735
736 //=============================================================================
737
738 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
739 static enum RC rc_class( OptoReg::Name reg ) {
740
741 if( !OptoReg::is_valid(reg) ) return rc_bad;
742 if (OptoReg::is_stack(reg)) return rc_stack;
743
744 VMReg r = OptoReg::as_VMReg(reg);
745 if (r->is_Register()) return rc_int;
746 if (r->is_FloatRegister()) {
747 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
748 return rc_float;
749 }
750 assert(r->is_XMMRegister(), "must be");
751 return rc_xmm;
752 }
753
754 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
755 int opcode, const char *op_str, int size, outputStream* st ) {
756 if( cbuf ) {
757 emit_opcode (*cbuf, opcode );
758 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
759 #ifndef PRODUCT
760 } else if( !do_size ) {
761 if( size != 0 ) st->print("\n\t");
762 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
763 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
764 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
765 } else { // FLD, FST, PUSH, POP
766 st->print("%s [ESP + #%d]",op_str,offset);
767 }
768 #endif
769 }
770 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
771 return size+3+offset_size;
772 }
773
774 // Helper for XMM registers. Extra opcode bits, limited syntax.
775 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
776 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
777 if( cbuf ) {
778 if( reg_lo+1 == reg_hi ) { // double move?
779 if( is_load && !UseXmmLoadAndClearUpper )
780 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
781 else
782 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
783 } else {
784 emit_opcode(*cbuf, 0xF3 );
785 }
786 emit_opcode(*cbuf, 0x0F );
787 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
788 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
789 else
790 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
791 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
792 #ifndef PRODUCT
793 } else if( !do_size ) {
794 if( size != 0 ) st->print("\n\t");
795 if( reg_lo+1 == reg_hi ) { // double move?
796 if( is_load ) st->print("%s %s,[ESP + #%d]",
797 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
798 Matcher::regName[reg_lo], offset);
799 else st->print("MOVSD [ESP + #%d],%s",
800 offset, Matcher::regName[reg_lo]);
801 } else {
802 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
803 Matcher::regName[reg_lo], offset);
804 else st->print("MOVSS [ESP + #%d],%s",
805 offset, Matcher::regName[reg_lo]);
806 }
807 #endif
808 }
809 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
810 return size+5+offset_size;
811 }
812
813
814 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
815 int src_hi, int dst_hi, int size, outputStream* st ) {
816 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
817 if( cbuf ) {
818 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
819 emit_opcode(*cbuf, 0x66 );
820 }
821 emit_opcode(*cbuf, 0x0F );
822 emit_opcode(*cbuf, 0x28 );
823 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
824 #ifndef PRODUCT
825 } else if( !do_size ) {
826 if( size != 0 ) st->print("\n\t");
827 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
829 } else {
830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
831 }
832 #endif
833 }
834 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
835 } else {
836 if( cbuf ) {
837 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
838 emit_opcode(*cbuf, 0x0F );
839 emit_opcode(*cbuf, 0x10 );
840 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
841 #ifndef PRODUCT
842 } else if( !do_size ) {
843 if( size != 0 ) st->print("\n\t");
844 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
845 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
846 } else {
847 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
848 }
849 #endif
850 }
851 return size+4;
852 }
853 }
854
855 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
856 if( cbuf ) {
857 emit_opcode(*cbuf, 0x8B );
858 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
859 #ifndef PRODUCT
860 } else if( !do_size ) {
861 if( size != 0 ) st->print("\n\t");
862 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
863 #endif
864 }
865 return size+2;
866 }
867
868 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
869 int offset, int size, outputStream* st ) {
870 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
871 if( cbuf ) {
872 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
873 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
874 #ifndef PRODUCT
875 } else if( !do_size ) {
876 if( size != 0 ) st->print("\n\t");
877 st->print("FLD %s",Matcher::regName[src_lo]);
878 #endif
879 }
880 size += 2;
881 }
882
883 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
884 const char *op_str;
885 int op;
886 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
887 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
888 op = 0xDD;
889 } else { // 32-bit store
890 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
891 op = 0xD9;
892 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
893 }
894
895 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
896 }
897
898 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
899 // Get registers to move
900 OptoReg::Name src_second = ra_->get_reg_second(in(1));
901 OptoReg::Name src_first = ra_->get_reg_first(in(1));
902 OptoReg::Name dst_second = ra_->get_reg_second(this );
903 OptoReg::Name dst_first = ra_->get_reg_first(this );
904
905 enum RC src_second_rc = rc_class(src_second);
906 enum RC src_first_rc = rc_class(src_first);
907 enum RC dst_second_rc = rc_class(dst_second);
908 enum RC dst_first_rc = rc_class(dst_first);
909
910 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
911
912 // Generate spill code!
913 int size = 0;
914
915 if( src_first == dst_first && src_second == dst_second )
916 return size; // Self copy, no move
917
918 // --------------------------------------
919 // Check for mem-mem move. push/pop to move.
920 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
921 if( src_second == dst_first ) { // overlapping stack copy ranges
922 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
923 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
924 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
925 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
926 }
927 // move low bits
928 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
929 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
930 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
933 }
934 return size;
935 }
936
937 // --------------------------------------
938 // Check for integer reg-reg copy
939 if( src_first_rc == rc_int && dst_first_rc == rc_int )
940 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
941
942 // Check for integer store
943 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
944 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
945
946 // Check for integer load
947 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
948 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
949
950 // --------------------------------------
951 // Check for float reg-reg copy
952 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
953 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
954 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
955 if( cbuf ) {
956
957 // Note the mucking with the register encode to compensate for the 0/1
958 // indexing issue mentioned in a comment in the reg_def sections
959 // for FPR registers many lines above here.
960
961 if( src_first != FPR1L_num ) {
962 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
963 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
964 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
965 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
966 } else {
967 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
968 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
969 }
970 #ifndef PRODUCT
971 } else if( !do_size ) {
972 if( size != 0 ) st->print("\n\t");
973 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
974 else st->print( "FST %s", Matcher::regName[dst_first]);
975 #endif
976 }
977 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
978 }
979
980 // Check for float store
981 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
982 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
983 }
984
985 // Check for float load
986 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
987 int offset = ra_->reg2offset(src_first);
988 const char *op_str;
989 int op;
990 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
991 op_str = "FLD_D";
992 op = 0xDD;
993 } else { // 32-bit load
994 op_str = "FLD_S";
995 op = 0xD9;
996 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
997 }
998 if( cbuf ) {
999 emit_opcode (*cbuf, op );
1000 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1001 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1002 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1003 #ifndef PRODUCT
1004 } else if( !do_size ) {
1005 if( size != 0 ) st->print("\n\t");
1006 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1007 #endif
1008 }
1009 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1010 return size + 3+offset_size+2;
1011 }
1012
1013 // Check for xmm reg-reg copy
1014 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1015 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1016 (src_first+1 == src_second && dst_first+1 == dst_second),
1017 "no non-adjacent float-moves" );
1018 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1019 }
1020
1021 // Check for xmm store
1022 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1023 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1024 }
1025
1026 // Check for float xmm load
1027 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1028 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1029 }
1030
1031 // Copy from float reg to xmm reg
1032 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1033 // copy to the top of stack from floating point reg
1034 // and use LEA to preserve flags
1035 if( cbuf ) {
1036 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1037 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1038 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1039 emit_d8(*cbuf,0xF8);
1040 #ifndef PRODUCT
1041 } else if( !do_size ) {
1042 if( size != 0 ) st->print("\n\t");
1043 st->print("LEA ESP,[ESP-8]");
1044 #endif
1045 }
1046 size += 4;
1047
1048 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1049
1050 // Copy from the temp memory to the xmm reg.
1051 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1052
1053 if( cbuf ) {
1054 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1055 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1056 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1057 emit_d8(*cbuf,0x08);
1058 #ifndef PRODUCT
1059 } else if( !do_size ) {
1060 if( size != 0 ) st->print("\n\t");
1061 st->print("LEA ESP,[ESP+8]");
1062 #endif
1063 }
1064 size += 4;
1065 return size;
1066 }
1067
1068 assert( size > 0, "missed a case" );
1069
1070 // --------------------------------------------------------------------
1071 // Check for second bits still needing moving.
1072 if( src_second == dst_second )
1073 return size; // Self copy; no move
1074 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1075
1076 // Check for second word int-int move
1077 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1078 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1079
1080 // Check for second word integer store
1081 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1082 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1083
1084 // Check for second word integer load
1085 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1086 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1087
1088
1089 Unimplemented();
1090 }
1091
1092 #ifndef PRODUCT
1093 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1094 implementation( NULL, ra_, false, st );
1095 }
1096 #endif
1097
1098 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1099 implementation( &cbuf, ra_, false, NULL );
1100 }
1101
1102 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1103 return implementation( NULL, ra_, true, NULL );
1104 }
1105
1106 //=============================================================================
1107 #ifndef PRODUCT
1108 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1109 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1110 }
1111 #endif
1112
1113 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1114 MacroAssembler _masm(&cbuf);
1115 __ nop(_count);
1116 }
1117
1118 uint MachNopNode::size(PhaseRegAlloc *) const {
1119 return _count;
1120 }
1121
1122
1123 //=============================================================================
1124 #ifndef PRODUCT
1125 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1126 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1127 int reg = ra_->get_reg_first(this);
1128 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1129 }
1130 #endif
1131
1132 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1133 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1134 int reg = ra_->get_encode(this);
1135 if( offset >= 128 ) {
1136 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1137 emit_rm(cbuf, 0x2, reg, 0x04);
1138 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d32(cbuf, offset);
1140 }
1141 else {
1142 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1143 emit_rm(cbuf, 0x1, reg, 0x04);
1144 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1145 emit_d8(cbuf, offset);
1146 }
1147 }
1148
1149 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1150 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1151 if( offset >= 128 ) {
1152 return 7;
1153 }
1154 else {
1155 return 4;
1156 }
1157 }
1158
1159 //=============================================================================
1160
1161 // emit call stub, compiled java to interpreter
1162 void emit_java_to_interp(CodeBuffer &cbuf ) {
1163 // Stub is fixed up when the corresponding call is converted from calling
1164 // compiled code to calling interpreted code.
1165 // mov rbx,0
1166 // jmp -1
1167
1168 address mark = cbuf.inst_mark(); // get mark within main instrs section
1169
1170 // Note that the code buffer's inst_mark is always relative to insts.
1171 // That's why we must use the macroassembler to generate a stub.
1172 MacroAssembler _masm(&cbuf);
1173
1174 address base =
1175 __ start_a_stub(Compile::MAX_stubs_size);
1176 if (base == NULL) return; // CodeBuffer::expand failed
1177 // static stub relocation stores the instruction address of the call
1178 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1179 // static stub relocation also tags the methodOop in the code-stream.
1180 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1181 // This is recognized as unresolved by relocs/nativeInst/ic code
1182 __ jump(RuntimeAddress(__ pc()));
1183
1184 __ end_a_stub();
1185 // Update current stubs pointer and restore code_end.
1186 }
1187 // size of call stub, compiled java to interpretor
1188 uint size_java_to_interp() {
1189 return 10; // movl; jmp
1190 }
1191 // relocation entries for call stub, compiled java to interpretor
1192 uint reloc_java_to_interp() {
1193 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1194 }
1195
1196 //=============================================================================
1197 #ifndef PRODUCT
1198 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1199 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1200 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1201 st->print_cr("\tNOP");
1202 st->print_cr("\tNOP");
1203 if( !OptoBreakpoint )
1204 st->print_cr("\tNOP");
1205 }
1206 #endif
1207
1208 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1209 MacroAssembler masm(&cbuf);
1210 #ifdef ASSERT
1211 uint code_size = cbuf.code_size();
1212 #endif
1213 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1214 masm.jump_cc(Assembler::notEqual,
1215 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1216 /* WARNING these NOPs are critical so that verified entry point is properly
1217 aligned for patching by NativeJump::patch_verified_entry() */
1218 int nops_cnt = 2;
1219 if( !OptoBreakpoint ) // Leave space for int3
1220 nops_cnt += 1;
1221 masm.nop(nops_cnt);
1222
1223 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1224 }
1225
1226 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1227 return OptoBreakpoint ? 11 : 12;
1228 }
1229
1230
1231 //=============================================================================
1232 uint size_exception_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return NativeJump::instruction_size;
1239 }
1240
1241 // Emit exception handler code. Stuff framesize into a register
1242 // and call a VM stub routine.
1243 int emit_exception_handler(CodeBuffer& cbuf) {
1244
1245 // Note that the code buffer's inst_mark is always relative to insts.
1246 // That's why we must use the macroassembler to generate a handler.
1247 MacroAssembler _masm(&cbuf);
1248 address base =
1249 __ start_a_stub(size_exception_handler());
1250 if (base == NULL) return 0; // CodeBuffer::expand failed
1251 int offset = __ offset();
1252 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1253 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1254 __ end_a_stub();
1255 return offset;
1256 }
1257
1258 uint size_deopt_handler() {
1259 // NativeCall instruction size is the same as NativeJump.
1260 // exception handler starts out as jump and can be patched to
1261 // a call be deoptimization. (4932387)
1262 // Note that this value is also credited (in output.cpp) to
1263 // the size of the code section.
1264 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1265 }
1266
1267 // Emit deopt handler code.
1268 int emit_deopt_handler(CodeBuffer& cbuf) {
1269
1270 // Note that the code buffer's inst_mark is always relative to insts.
1271 // That's why we must use the macroassembler to generate a handler.
1272 MacroAssembler _masm(&cbuf);
1273 address base =
1274 __ start_a_stub(size_exception_handler());
1275 if (base == NULL) return 0; // CodeBuffer::expand failed
1276 int offset = __ offset();
1277 InternalAddress here(__ pc());
1278 __ pushptr(here.addr());
1279
1280 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1281 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1282 __ end_a_stub();
1283 return offset;
1284 }
1285
1286
1287 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1288 int mark = cbuf.insts()->mark_off();
1289 MacroAssembler _masm(&cbuf);
1290 address double_address = __ double_constant(x);
1291 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1292 emit_d32_reloc(cbuf,
1293 (int)double_address,
1294 internal_word_Relocation::spec(double_address),
1295 RELOC_DISP32);
1296 }
1297
1298 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1299 int mark = cbuf.insts()->mark_off();
1300 MacroAssembler _masm(&cbuf);
1301 address float_address = __ float_constant(x);
1302 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1303 emit_d32_reloc(cbuf,
1304 (int)float_address,
1305 internal_word_Relocation::spec(float_address),
1306 RELOC_DISP32);
1307 }
1308
1309
1310 const bool Matcher::match_rule_supported(int opcode) {
1311 if (!has_match_rule(opcode))
1312 return false;
1313
1314 return true; // Per default match rules are supported.
1315 }
1316
1317 int Matcher::regnum_to_fpu_offset(int regnum) {
1318 return regnum - 32; // The FP registers are in the second chunk
1319 }
1320
1321 bool is_positive_zero_float(jfloat f) {
1322 return jint_cast(f) == jint_cast(0.0F);
1323 }
1324
1325 bool is_positive_one_float(jfloat f) {
1326 return jint_cast(f) == jint_cast(1.0F);
1327 }
1328
1329 bool is_positive_zero_double(jdouble d) {
1330 return jlong_cast(d) == jlong_cast(0.0);
1331 }
1332
1333 bool is_positive_one_double(jdouble d) {
1334 return jlong_cast(d) == jlong_cast(1.0);
1335 }
1336
1337 // This is UltraSparc specific, true just means we have fast l2f conversion
1338 const bool Matcher::convL2FSupported(void) {
1339 return true;
1340 }
1341
1342 // Vector width in bytes
1343 const uint Matcher::vector_width_in_bytes(void) {
1344 return UseSSE >= 2 ? 8 : 0;
1345 }
1346
1347 // Vector ideal reg
1348 const uint Matcher::vector_ideal_reg(void) {
1349 return Op_RegD;
1350 }
1351
1352 // Is this branch offset short enough that a short branch can be used?
1353 //
1354 // NOTE: If the platform does not provide any short branch variants, then
1355 // this method should return false for offset 0.
1356 bool Matcher::is_short_branch_offset(int rule, int offset) {
1357 // the short version of jmpConUCF2 contains multiple branches,
1358 // making the reach slightly less
1359 if (rule == jmpConUCF2_rule)
1360 return (-126 <= offset && offset <= 125);
1361 return (-128 <= offset && offset <= 127);
1362 }
1363
1364 const bool Matcher::isSimpleConstant64(jlong value) {
1365 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1366 return false;
1367 }
1368
1369 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1370 const bool Matcher::init_array_count_is_in_bytes = false;
1371
1372 // Threshold size for cleararray.
1373 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1374
1375 // Should the Matcher clone shifts on addressing modes, expecting them to
1376 // be subsumed into complex addressing expressions or compute them into
1377 // registers? True for Intel but false for most RISCs
1378 const bool Matcher::clone_shift_expressions = true;
1379
1380 // Is it better to copy float constants, or load them directly from memory?
1381 // Intel can load a float constant from a direct address, requiring no
1382 // extra registers. Most RISCs will have to materialize an address into a
1383 // register first, so they would do better to copy the constant from stack.
1384 const bool Matcher::rematerialize_float_constants = true;
1385
1386 // If CPU can load and store mis-aligned doubles directly then no fixup is
1387 // needed. Else we split the double into 2 integer pieces and move it
1388 // piece-by-piece. Only happens when passing doubles into C code as the
1389 // Java calling convention forces doubles to be aligned.
1390 const bool Matcher::misaligned_doubles_ok = true;
1391
1392
1393 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1394 // Get the memory operand from the node
1395 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1396 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1397 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1398 uint opcnt = 1; // First operand
1399 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1400 while( idx >= skipped+num_edges ) {
1401 skipped += num_edges;
1402 opcnt++; // Bump operand count
1403 assert( opcnt < numopnds, "Accessing non-existent operand" );
1404 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1405 }
1406
1407 MachOper *memory = node->_opnds[opcnt];
1408 MachOper *new_memory = NULL;
1409 switch (memory->opcode()) {
1410 case DIRECT:
1411 case INDOFFSET32X:
1412 // No transformation necessary.
1413 return;
1414 case INDIRECT:
1415 new_memory = new (C) indirect_win95_safeOper( );
1416 break;
1417 case INDOFFSET8:
1418 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1419 break;
1420 case INDOFFSET32:
1421 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1422 break;
1423 case INDINDEXOFFSET:
1424 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1425 break;
1426 case INDINDEXSCALE:
1427 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1428 break;
1429 case INDINDEXSCALEOFFSET:
1430 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1431 break;
1432 case LOAD_LONG_INDIRECT:
1433 case LOAD_LONG_INDOFFSET32:
1434 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1435 return;
1436 default:
1437 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1438 return;
1439 }
1440 node->_opnds[opcnt] = new_memory;
1441 }
1442
1443 // Advertise here if the CPU requires explicit rounding operations
1444 // to implement the UseStrictFP mode.
1445 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1446
1447 // Are floats conerted to double when stored to stack during deoptimization?
1448 // On x32 it is stored with convertion only when FPU is used for floats.
1449 bool Matcher::float_in_double() { return (UseSSE == 0); }
1450
1451 // Do ints take an entire long register or just half?
1452 const bool Matcher::int_in_long = false;
1453
1454 // Return whether or not this register is ever used as an argument. This
1455 // function is used on startup to build the trampoline stubs in generateOptoStub.
1456 // Registers not mentioned will be killed by the VM call in the trampoline, and
1457 // arguments in those registers not be available to the callee.
1458 bool Matcher::can_be_java_arg( int reg ) {
1459 if( reg == ECX_num || reg == EDX_num ) return true;
1460 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1461 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1462 return false;
1463 }
1464
1465 bool Matcher::is_spillable_arg( int reg ) {
1466 return can_be_java_arg(reg);
1467 }
1468
1469 // Register for DIVI projection of divmodI
1470 RegMask Matcher::divI_proj_mask() {
1471 return EAX_REG_mask;
1472 }
1473
1474 // Register for MODI projection of divmodI
1475 RegMask Matcher::modI_proj_mask() {
1476 return EDX_REG_mask;
1477 }
1478
1479 // Register for DIVL projection of divmodL
1480 RegMask Matcher::divL_proj_mask() {
1481 ShouldNotReachHere();
1482 return RegMask();
1483 }
1484
1485 // Register for MODL projection of divmodL
1486 RegMask Matcher::modL_proj_mask() {
1487 ShouldNotReachHere();
1488 return RegMask();
1489 }
1490
1491 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1492 return EBP_REG_mask;
1493 }
1494
1495 // Returns true if the high 32 bits of the value is known to be zero.
1496 bool is_operand_hi32_zero(Node* n) {
1497 int opc = n->Opcode();
1498 if (opc == Op_LoadUI2L) {
1499 return true;
1500 }
1501 if (opc == Op_AndL) {
1502 Node* o2 = n->in(2);
1503 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1504 return true;
1505 }
1506 }
1507 return false;
1508 }
1509
1510 %}
1511
1512 //----------ENCODING BLOCK-----------------------------------------------------
1513 // This block specifies the encoding classes used by the compiler to output
1514 // byte streams. Encoding classes generate functions which are called by
1515 // Machine Instruction Nodes in order to generate the bit encoding of the
1516 // instruction. Operands specify their base encoding interface with the
1517 // interface keyword. There are currently supported four interfaces,
1518 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1519 // operand to generate a function which returns its register number when
1520 // queried. CONST_INTER causes an operand to generate a function which
1521 // returns the value of the constant when queried. MEMORY_INTER causes an
1522 // operand to generate four functions which return the Base Register, the
1523 // Index Register, the Scale Value, and the Offset Value of the operand when
1524 // queried. COND_INTER causes an operand to generate six functions which
1525 // return the encoding code (ie - encoding bits for the instruction)
1526 // associated with each basic boolean condition for a conditional instruction.
1527 // Instructions specify two basic values for encoding. They use the
1528 // ins_encode keyword to specify their encoding class (which must be one of
1529 // the class names specified in the encoding block), and they use the
1530 // opcode keyword to specify, in order, their primary, secondary, and
1531 // tertiary opcode. Only the opcode sections which a particular instruction
1532 // needs for encoding need to be specified.
1533 encode %{
1534 // Build emit functions for each basic byte or larger field in the intel
1535 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1536 // code in the enc_class source block. Emit functions will live in the
1537 // main source block for now. In future, we can generalize this by
1538 // adding a syntax that specifies the sizes of fields in an order,
1539 // so that the adlc can build the emit functions automagically
1540
1541 // Emit primary opcode
1542 enc_class OpcP %{
1543 emit_opcode(cbuf, $primary);
1544 %}
1545
1546 // Emit secondary opcode
1547 enc_class OpcS %{
1548 emit_opcode(cbuf, $secondary);
1549 %}
1550
1551 // Emit opcode directly
1552 enc_class Opcode(immI d8) %{
1553 emit_opcode(cbuf, $d8$$constant);
1554 %}
1555
1556 enc_class SizePrefix %{
1557 emit_opcode(cbuf,0x66);
1558 %}
1559
1560 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1561 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1562 %}
1563
1564 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1565 emit_opcode(cbuf,$opcode$$constant);
1566 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1567 %}
1568
1569 enc_class mov_r32_imm0( eRegI dst ) %{
1570 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1571 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1572 %}
1573
1574 enc_class cdq_enc %{
1575 // Full implementation of Java idiv and irem; checks for
1576 // special case as described in JVM spec., p.243 & p.271.
1577 //
1578 // normal case special case
1579 //
1580 // input : rax,: dividend min_int
1581 // reg: divisor -1
1582 //
1583 // output: rax,: quotient (= rax, idiv reg) min_int
1584 // rdx: remainder (= rax, irem reg) 0
1585 //
1586 // Code sequnce:
1587 //
1588 // 81 F8 00 00 00 80 cmp rax,80000000h
1589 // 0F 85 0B 00 00 00 jne normal_case
1590 // 33 D2 xor rdx,edx
1591 // 83 F9 FF cmp rcx,0FFh
1592 // 0F 84 03 00 00 00 je done
1593 // normal_case:
1594 // 99 cdq
1595 // F7 F9 idiv rax,ecx
1596 // done:
1597 //
1598 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1599 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1600 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1601 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1602 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1603 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1604 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1605 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1606 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1607 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1609 // normal_case:
1610 emit_opcode(cbuf,0x99); // cdq
1611 // idiv (note: must be emitted by the user of this rule)
1612 // normal:
1613 %}
1614
1615 // Dense encoding for older common ops
1616 enc_class Opc_plus(immI opcode, eRegI reg) %{
1617 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1618 %}
1619
1620
1621 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1622 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1623 // Check for 8-bit immediate, and set sign extend bit in opcode
1624 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1625 emit_opcode(cbuf, $primary | 0x02);
1626 }
1627 else { // If 32-bit immediate
1628 emit_opcode(cbuf, $primary);
1629 }
1630 %}
1631
1632 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1633 // Emit primary opcode and set sign-extend bit
1634 // Check for 8-bit immediate, and set sign extend bit in opcode
1635 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1636 emit_opcode(cbuf, $primary | 0x02); }
1637 else { // If 32-bit immediate
1638 emit_opcode(cbuf, $primary);
1639 }
1640 // Emit r/m byte with secondary opcode, after primary opcode.
1641 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1642 %}
1643
1644 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1645 // Check for 8-bit immediate, and set sign extend bit in opcode
1646 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1647 $$$emit8$imm$$constant;
1648 }
1649 else { // If 32-bit immediate
1650 // Output immediate
1651 $$$emit32$imm$$constant;
1652 }
1653 %}
1654
1655 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1656 // Emit primary opcode and set sign-extend bit
1657 // Check for 8-bit immediate, and set sign extend bit in opcode
1658 int con = (int)$imm$$constant; // Throw away top bits
1659 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1660 // Emit r/m byte with secondary opcode, after primary opcode.
1661 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1662 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1663 else emit_d32(cbuf,con);
1664 %}
1665
1666 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1667 // Emit primary opcode and set sign-extend bit
1668 // Check for 8-bit immediate, and set sign extend bit in opcode
1669 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1670 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1671 // Emit r/m byte with tertiary opcode, after primary opcode.
1672 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1673 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1674 else emit_d32(cbuf,con);
1675 %}
1676
1677 enc_class Lbl (label labl) %{ // JMP, CALL
1678 Label *l = $labl$$label;
1679 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1680 %}
1681
1682 enc_class LblShort (label labl) %{ // JMP, CALL
1683 Label *l = $labl$$label;
1684 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1685 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1686 emit_d8(cbuf, disp);
1687 %}
1688
1689 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1690 emit_cc(cbuf, $secondary, $dst$$reg );
1691 %}
1692
1693 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1694 int destlo = $dst$$reg;
1695 int desthi = HIGH_FROM_LOW(destlo);
1696 // bswap lo
1697 emit_opcode(cbuf, 0x0F);
1698 emit_cc(cbuf, 0xC8, destlo);
1699 // bswap hi
1700 emit_opcode(cbuf, 0x0F);
1701 emit_cc(cbuf, 0xC8, desthi);
1702 // xchg lo and hi
1703 emit_opcode(cbuf, 0x87);
1704 emit_rm(cbuf, 0x3, destlo, desthi);
1705 %}
1706
1707 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1708 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1709 %}
1710
1711 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1712 Label *l = $labl$$label;
1713 $$$emit8$primary;
1714 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1715 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1716 %}
1717
1718 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1719 Label *l = $labl$$label;
1720 emit_cc(cbuf, $primary, $cop$$cmpcode);
1721 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1722 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1723 emit_d8(cbuf, disp);
1724 %}
1725
1726 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1727 $$$emit8$primary;
1728 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1729 %}
1730
1731 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1732 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1733 emit_d8(cbuf, op >> 8 );
1734 emit_d8(cbuf, op & 255);
1735 %}
1736
1737 // emulate a CMOV with a conditional branch around a MOV
1738 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1739 // Invert sense of branch from sense of CMOV
1740 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1741 emit_d8( cbuf, $brOffs$$constant );
1742 %}
1743
1744 enc_class enc_PartialSubtypeCheck( ) %{
1745 Register Redi = as_Register(EDI_enc); // result register
1746 Register Reax = as_Register(EAX_enc); // super class
1747 Register Recx = as_Register(ECX_enc); // killed
1748 Register Resi = as_Register(ESI_enc); // sub class
1749 Label miss;
1750
1751 MacroAssembler _masm(&cbuf);
1752 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1753 NULL, &miss,
1754 /*set_cond_codes:*/ true);
1755 if ($primary) {
1756 __ xorptr(Redi, Redi);
1757 }
1758 __ bind(miss);
1759 %}
1760
1761 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1762 MacroAssembler masm(&cbuf);
1763 int start = masm.offset();
1764 if (UseSSE >= 2) {
1765 if (VerifyFPU) {
1766 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1767 }
1768 } else {
1769 // External c_calling_convention expects the FPU stack to be 'clean'.
1770 // Compiled code leaves it dirty. Do cleanup now.
1771 masm.empty_FPU_stack();
1772 }
1773 if (sizeof_FFree_Float_Stack_All == -1) {
1774 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1775 } else {
1776 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1777 }
1778 %}
1779
1780 enc_class Verify_FPU_For_Leaf %{
1781 if( VerifyFPU ) {
1782 MacroAssembler masm(&cbuf);
1783 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1784 }
1785 %}
1786
1787 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1788 // This is the instruction starting address for relocation info.
1789 cbuf.set_inst_mark();
1790 $$$emit8$primary;
1791 // CALL directly to the runtime
1792 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1793 runtime_call_Relocation::spec(), RELOC_IMM32 );
1794
1795 if (UseSSE >= 2) {
1796 MacroAssembler _masm(&cbuf);
1797 BasicType rt = tf()->return_type();
1798
1799 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1800 // A C runtime call where the return value is unused. In SSE2+
1801 // mode the result needs to be removed from the FPU stack. It's
1802 // likely that this function call could be removed by the
1803 // optimizer if the C function is a pure function.
1804 __ ffree(0);
1805 } else if (rt == T_FLOAT) {
1806 __ lea(rsp, Address(rsp, -4));
1807 __ fstp_s(Address(rsp, 0));
1808 __ movflt(xmm0, Address(rsp, 0));
1809 __ lea(rsp, Address(rsp, 4));
1810 } else if (rt == T_DOUBLE) {
1811 __ lea(rsp, Address(rsp, -8));
1812 __ fstp_d(Address(rsp, 0));
1813 __ movdbl(xmm0, Address(rsp, 0));
1814 __ lea(rsp, Address(rsp, 8));
1815 }
1816 }
1817 %}
1818
1819
1820 enc_class pre_call_FPU %{
1821 // If method sets FPU control word restore it here
1822 debug_only(int off0 = cbuf.code_size());
1823 if( Compile::current()->in_24_bit_fp_mode() ) {
1824 MacroAssembler masm(&cbuf);
1825 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1826 }
1827 debug_only(int off1 = cbuf.code_size());
1828 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1829 %}
1830
1831 enc_class post_call_FPU %{
1832 // If method sets FPU control word do it here also
1833 if( Compile::current()->in_24_bit_fp_mode() ) {
1834 MacroAssembler masm(&cbuf);
1835 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1836 }
1837 %}
1838
1839 enc_class preserve_SP %{
1840 debug_only(int off0 = cbuf.code_size());
1841 MacroAssembler _masm(&cbuf);
1842 // RBP is preserved across all calls, even compiled calls.
1843 // Use it to preserve RSP in places where the callee might change the SP.
1844 __ movptr(rbp, rsp);
1845 debug_only(int off1 = cbuf.code_size());
1846 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1847 %}
1848
1849 enc_class restore_SP %{
1850 MacroAssembler _masm(&cbuf);
1851 __ movptr(rsp, rbp);
1852 %}
1853
1854 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1855 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1856 // who we intended to call.
1857 cbuf.set_inst_mark();
1858 $$$emit8$primary;
1859 if ( !_method ) {
1860 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1861 runtime_call_Relocation::spec(), RELOC_IMM32 );
1862 } else if(_optimized_virtual) {
1863 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1864 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1865 } else {
1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1867 static_call_Relocation::spec(), RELOC_IMM32 );
1868 }
1869 if( _method ) { // Emit stub for static call
1870 emit_java_to_interp(cbuf);
1871 }
1872 %}
1873
1874 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1875 // !!!!!
1876 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1877 // emit_call_dynamic_prologue( cbuf );
1878 cbuf.set_inst_mark();
1879 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1880 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1881 address virtual_call_oop_addr = cbuf.inst_mark();
1882 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1883 // who we intended to call.
1884 cbuf.set_inst_mark();
1885 $$$emit8$primary;
1886 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1887 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1888 %}
1889
1890 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1891 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1892 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1893
1894 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1895 cbuf.set_inst_mark();
1896 $$$emit8$primary;
1897 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1898 emit_d8(cbuf, disp); // Displacement
1899
1900 %}
1901
1902 enc_class Xor_Reg (eRegI dst) %{
1903 emit_opcode(cbuf, 0x33);
1904 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1905 %}
1906
1907 // Following encoding is no longer used, but may be restored if calling
1908 // convention changes significantly.
1909 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1910 //
1911 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1912 // // int ic_reg = Matcher::inline_cache_reg();
1913 // // int ic_encode = Matcher::_regEncode[ic_reg];
1914 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1915 // // int imo_encode = Matcher::_regEncode[imo_reg];
1916 //
1917 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1918 // // // so we load it immediately before the call
1919 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1920 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1921 //
1922 // // xor rbp,ebp
1923 // emit_opcode(cbuf, 0x33);
1924 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1925 //
1926 // // CALL to interpreter.
1927 // cbuf.set_inst_mark();
1928 // $$$emit8$primary;
1929 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1930 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1931 // %}
1932
1933 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1934 $$$emit8$primary;
1935 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1936 $$$emit8$shift$$constant;
1937 %}
1938
1939 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1940 // Load immediate does not have a zero or sign extended version
1941 // for 8-bit immediates
1942 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1943 $$$emit32$src$$constant;
1944 %}
1945
1946 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1947 // Load immediate does not have a zero or sign extended version
1948 // for 8-bit immediates
1949 emit_opcode(cbuf, $primary + $dst$$reg);
1950 $$$emit32$src$$constant;
1951 %}
1952
1953 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1954 // Load immediate does not have a zero or sign extended version
1955 // for 8-bit immediates
1956 int dst_enc = $dst$$reg;
1957 int src_con = $src$$constant & 0x0FFFFFFFFL;
1958 if (src_con == 0) {
1959 // xor dst, dst
1960 emit_opcode(cbuf, 0x33);
1961 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1962 } else {
1963 emit_opcode(cbuf, $primary + dst_enc);
1964 emit_d32(cbuf, src_con);
1965 }
1966 %}
1967
1968 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1969 // Load immediate does not have a zero or sign extended version
1970 // for 8-bit immediates
1971 int dst_enc = $dst$$reg + 2;
1972 int src_con = ((julong)($src$$constant)) >> 32;
1973 if (src_con == 0) {
1974 // xor dst, dst
1975 emit_opcode(cbuf, 0x33);
1976 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1977 } else {
1978 emit_opcode(cbuf, $primary + dst_enc);
1979 emit_d32(cbuf, src_con);
1980 }
1981 %}
1982
1983
1984 enc_class LdImmD (immD src) %{ // Load Immediate
1985 if( is_positive_zero_double($src$$constant)) {
1986 // FLDZ
1987 emit_opcode(cbuf,0xD9);
1988 emit_opcode(cbuf,0xEE);
1989 } else if( is_positive_one_double($src$$constant)) {
1990 // FLD1
1991 emit_opcode(cbuf,0xD9);
1992 emit_opcode(cbuf,0xE8);
1993 } else {
1994 emit_opcode(cbuf,0xDD);
1995 emit_rm(cbuf, 0x0, 0x0, 0x5);
1996 emit_double_constant(cbuf, $src$$constant);
1997 }
1998 %}
1999
2000
2001 enc_class LdImmF (immF src) %{ // Load Immediate
2002 if( is_positive_zero_float($src$$constant)) {
2003 emit_opcode(cbuf,0xD9);
2004 emit_opcode(cbuf,0xEE);
2005 } else if( is_positive_one_float($src$$constant)) {
2006 emit_opcode(cbuf,0xD9);
2007 emit_opcode(cbuf,0xE8);
2008 } else {
2009 $$$emit8$primary;
2010 // Load immediate does not have a zero or sign extended version
2011 // for 8-bit immediates
2012 // First load to TOS, then move to dst
2013 emit_rm(cbuf, 0x0, 0x0, 0x5);
2014 emit_float_constant(cbuf, $src$$constant);
2015 }
2016 %}
2017
2018 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
2019 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2020 emit_float_constant(cbuf, $con$$constant);
2021 %}
2022
2023 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
2024 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2025 emit_double_constant(cbuf, $con$$constant);
2026 %}
2027
2028 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
2029 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2030 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2031 emit_opcode(cbuf, 0x0F);
2032 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2033 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2034 emit_double_constant(cbuf, $con$$constant);
2035 %}
2036
2037 enc_class Opc_MemImm_F(immF src) %{
2038 cbuf.set_inst_mark();
2039 $$$emit8$primary;
2040 emit_rm(cbuf, 0x0, $secondary, 0x5);
2041 emit_float_constant(cbuf, $src$$constant);
2042 %}
2043
2044
2045 enc_class MovI2X_reg(regX dst, eRegI src) %{
2046 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2047 emit_opcode(cbuf, 0x0F );
2048 emit_opcode(cbuf, 0x6E );
2049 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2050 %}
2051
2052 enc_class MovX2I_reg(eRegI dst, regX src) %{
2053 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2054 emit_opcode(cbuf, 0x0F );
2055 emit_opcode(cbuf, 0x7E );
2056 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2057 %}
2058
2059 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2060 { // MOVD $dst,$src.lo
2061 emit_opcode(cbuf,0x66);
2062 emit_opcode(cbuf,0x0F);
2063 emit_opcode(cbuf,0x6E);
2064 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2065 }
2066 { // MOVD $tmp,$src.hi
2067 emit_opcode(cbuf,0x66);
2068 emit_opcode(cbuf,0x0F);
2069 emit_opcode(cbuf,0x6E);
2070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2071 }
2072 { // PUNPCKLDQ $dst,$tmp
2073 emit_opcode(cbuf,0x66);
2074 emit_opcode(cbuf,0x0F);
2075 emit_opcode(cbuf,0x62);
2076 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2077 }
2078 %}
2079
2080 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2081 { // MOVD $dst.lo,$src
2082 emit_opcode(cbuf,0x66);
2083 emit_opcode(cbuf,0x0F);
2084 emit_opcode(cbuf,0x7E);
2085 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2086 }
2087 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2088 emit_opcode(cbuf,0xF2);
2089 emit_opcode(cbuf,0x0F);
2090 emit_opcode(cbuf,0x70);
2091 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2092 emit_d8(cbuf, 0x4E);
2093 }
2094 { // MOVD $dst.hi,$tmp
2095 emit_opcode(cbuf,0x66);
2096 emit_opcode(cbuf,0x0F);
2097 emit_opcode(cbuf,0x7E);
2098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2099 }
2100 %}
2101
2102
2103 // Encode a reg-reg copy. If it is useless, then empty encoding.
2104 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2105 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2106 %}
2107
2108 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2109 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2110 %}
2111
2112 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2113 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2114 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2115 %}
2116
2117 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2118 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2119 %}
2120
2121 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2122 $$$emit8$primary;
2123 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2124 %}
2125
2126 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2127 $$$emit8$secondary;
2128 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2129 %}
2130
2131 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2132 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2133 %}
2134
2135 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2136 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2137 %}
2138
2139 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2140 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2141 %}
2142
2143 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2144 // Output immediate
2145 $$$emit32$src$$constant;
2146 %}
2147
2148 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2149 // Output Float immediate bits
2150 jfloat jf = $src$$constant;
2151 int jf_as_bits = jint_cast( jf );
2152 emit_d32(cbuf, jf_as_bits);
2153 %}
2154
2155 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2156 // Output Float immediate bits
2157 jfloat jf = $src$$constant;
2158 int jf_as_bits = jint_cast( jf );
2159 emit_d32(cbuf, jf_as_bits);
2160 %}
2161
2162 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2163 // Output immediate
2164 $$$emit16$src$$constant;
2165 %}
2166
2167 enc_class Con_d32(immI src) %{
2168 emit_d32(cbuf,$src$$constant);
2169 %}
2170
2171 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2172 // Output immediate memory reference
2173 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2174 emit_d32(cbuf, 0x00);
2175 %}
2176
2177 enc_class lock_prefix( ) %{
2178 if( os::is_MP() )
2179 emit_opcode(cbuf,0xF0); // [Lock]
2180 %}
2181
2182 // Cmp-xchg long value.
2183 // Note: we need to swap rbx, and rcx before and after the
2184 // cmpxchg8 instruction because the instruction uses
2185 // rcx as the high order word of the new value to store but
2186 // our register encoding uses rbx,.
2187 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2188
2189 // XCHG rbx,ecx
2190 emit_opcode(cbuf,0x87);
2191 emit_opcode(cbuf,0xD9);
2192 // [Lock]
2193 if( os::is_MP() )
2194 emit_opcode(cbuf,0xF0);
2195 // CMPXCHG8 [Eptr]
2196 emit_opcode(cbuf,0x0F);
2197 emit_opcode(cbuf,0xC7);
2198 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2199 // XCHG rbx,ecx
2200 emit_opcode(cbuf,0x87);
2201 emit_opcode(cbuf,0xD9);
2202 %}
2203
2204 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2205 // [Lock]
2206 if( os::is_MP() )
2207 emit_opcode(cbuf,0xF0);
2208
2209 // CMPXCHG [Eptr]
2210 emit_opcode(cbuf,0x0F);
2211 emit_opcode(cbuf,0xB1);
2212 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2213 %}
2214
2215 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2216 int res_encoding = $res$$reg;
2217
2218 // MOV res,0
2219 emit_opcode( cbuf, 0xB8 + res_encoding);
2220 emit_d32( cbuf, 0 );
2221 // JNE,s fail
2222 emit_opcode(cbuf,0x75);
2223 emit_d8(cbuf, 5 );
2224 // MOV res,1
2225 emit_opcode( cbuf, 0xB8 + res_encoding);
2226 emit_d32( cbuf, 1 );
2227 // fail:
2228 %}
2229
2230 enc_class set_instruction_start( ) %{
2231 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2232 %}
2233
2234 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2235 int reg_encoding = $ereg$$reg;
2236 int base = $mem$$base;
2237 int index = $mem$$index;
2238 int scale = $mem$$scale;
2239 int displace = $mem$$disp;
2240 bool disp_is_oop = $mem->disp_is_oop();
2241 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2242 %}
2243
2244 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2245 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2246 int base = $mem$$base;
2247 int index = $mem$$index;
2248 int scale = $mem$$scale;
2249 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2250 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2251 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2252 %}
2253
2254 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2255 int r1, r2;
2256 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2257 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2258 emit_opcode(cbuf,0x0F);
2259 emit_opcode(cbuf,$tertiary);
2260 emit_rm(cbuf, 0x3, r1, r2);
2261 emit_d8(cbuf,$cnt$$constant);
2262 emit_d8(cbuf,$primary);
2263 emit_rm(cbuf, 0x3, $secondary, r1);
2264 emit_d8(cbuf,$cnt$$constant);
2265 %}
2266
2267 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2268 emit_opcode( cbuf, 0x8B ); // Move
2269 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2270 emit_d8(cbuf,$primary);
2271 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2272 emit_d8(cbuf,$cnt$$constant-32);
2273 emit_d8(cbuf,$primary);
2274 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2275 emit_d8(cbuf,31);
2276 %}
2277
2278 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2279 int r1, r2;
2280 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2281 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2282
2283 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2284 emit_rm(cbuf, 0x3, r1, r2);
2285 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2286 emit_opcode(cbuf,$primary);
2287 emit_rm(cbuf, 0x3, $secondary, r1);
2288 emit_d8(cbuf,$cnt$$constant-32);
2289 }
2290 emit_opcode(cbuf,0x33); // XOR r2,r2
2291 emit_rm(cbuf, 0x3, r2, r2);
2292 %}
2293
2294 // Clone of RegMem but accepts an extra parameter to access each
2295 // half of a double in memory; it never needs relocation info.
2296 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2297 emit_opcode(cbuf,$opcode$$constant);
2298 int reg_encoding = $rm_reg$$reg;
2299 int base = $mem$$base;
2300 int index = $mem$$index;
2301 int scale = $mem$$scale;
2302 int displace = $mem$$disp + $disp_for_half$$constant;
2303 bool disp_is_oop = false;
2304 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2305 %}
2306
2307 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2308 //
2309 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2310 // and it never needs relocation information.
2311 // Frequently used to move data between FPU's Stack Top and memory.
2312 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2313 int rm_byte_opcode = $rm_opcode$$constant;
2314 int base = $mem$$base;
2315 int index = $mem$$index;
2316 int scale = $mem$$scale;
2317 int displace = $mem$$disp;
2318 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2319 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2320 %}
2321
2322 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2323 int rm_byte_opcode = $rm_opcode$$constant;
2324 int base = $mem$$base;
2325 int index = $mem$$index;
2326 int scale = $mem$$scale;
2327 int displace = $mem$$disp;
2328 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2329 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2330 %}
2331
2332 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2333 int reg_encoding = $dst$$reg;
2334 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2335 int index = 0x04; // 0x04 indicates no index
2336 int scale = 0x00; // 0x00 indicates no scale
2337 int displace = $src1$$constant; // 0x00 indicates no displacement
2338 bool disp_is_oop = false;
2339 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2340 %}
2341
2342 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2343 // Compare dst,src
2344 emit_opcode(cbuf,0x3B);
2345 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2346 // jmp dst < src around move
2347 emit_opcode(cbuf,0x7C);
2348 emit_d8(cbuf,2);
2349 // move dst,src
2350 emit_opcode(cbuf,0x8B);
2351 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2352 %}
2353
2354 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2355 // Compare dst,src
2356 emit_opcode(cbuf,0x3B);
2357 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2358 // jmp dst > src around move
2359 emit_opcode(cbuf,0x7F);
2360 emit_d8(cbuf,2);
2361 // move dst,src
2362 emit_opcode(cbuf,0x8B);
2363 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2364 %}
2365
2366 enc_class enc_FP_store(memory mem, regD src) %{
2367 // If src is FPR1, we can just FST to store it.
2368 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2369 int reg_encoding = 0x2; // Just store
2370 int base = $mem$$base;
2371 int index = $mem$$index;
2372 int scale = $mem$$scale;
2373 int displace = $mem$$disp;
2374 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2375 if( $src$$reg != FPR1L_enc ) {
2376 reg_encoding = 0x3; // Store & pop
2377 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2378 emit_d8( cbuf, 0xC0-1+$src$$reg );
2379 }
2380 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2381 emit_opcode(cbuf,$primary);
2382 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2383 %}
2384
2385 enc_class neg_reg(eRegI dst) %{
2386 // NEG $dst
2387 emit_opcode(cbuf,0xF7);
2388 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2389 %}
2390
2391 enc_class setLT_reg(eCXRegI dst) %{
2392 // SETLT $dst
2393 emit_opcode(cbuf,0x0F);
2394 emit_opcode(cbuf,0x9C);
2395 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2397
2398 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2399 int tmpReg = $tmp$$reg;
2400
2401 // SUB $p,$q
2402 emit_opcode(cbuf,0x2B);
2403 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2404 // SBB $tmp,$tmp
2405 emit_opcode(cbuf,0x1B);
2406 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2407 // AND $tmp,$y
2408 emit_opcode(cbuf,0x23);
2409 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2410 // ADD $p,$tmp
2411 emit_opcode(cbuf,0x03);
2412 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2413 %}
2414
2415 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2416 int tmpReg = $tmp$$reg;
2417
2418 // SUB $p,$q
2419 emit_opcode(cbuf,0x2B);
2420 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2421 // SBB $tmp,$tmp
2422 emit_opcode(cbuf,0x1B);
2423 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2424 // AND $tmp,$y
2425 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2426 emit_opcode(cbuf,0x23);
2427 int reg_encoding = tmpReg;
2428 int base = $mem$$base;
2429 int index = $mem$$index;
2430 int scale = $mem$$scale;
2431 int displace = $mem$$disp;
2432 bool disp_is_oop = $mem->disp_is_oop();
2433 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2434 // ADD $p,$tmp
2435 emit_opcode(cbuf,0x03);
2436 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2437 %}
2438
2439 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2440 // TEST shift,32
2441 emit_opcode(cbuf,0xF7);
2442 emit_rm(cbuf, 0x3, 0, ECX_enc);
2443 emit_d32(cbuf,0x20);
2444 // JEQ,s small
2445 emit_opcode(cbuf, 0x74);
2446 emit_d8(cbuf, 0x04);
2447 // MOV $dst.hi,$dst.lo
2448 emit_opcode( cbuf, 0x8B );
2449 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2450 // CLR $dst.lo
2451 emit_opcode(cbuf, 0x33);
2452 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2453 // small:
2454 // SHLD $dst.hi,$dst.lo,$shift
2455 emit_opcode(cbuf,0x0F);
2456 emit_opcode(cbuf,0xA5);
2457 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2458 // SHL $dst.lo,$shift"
2459 emit_opcode(cbuf,0xD3);
2460 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2461 %}
2462
2463 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2464 // TEST shift,32
2465 emit_opcode(cbuf,0xF7);
2466 emit_rm(cbuf, 0x3, 0, ECX_enc);
2467 emit_d32(cbuf,0x20);
2468 // JEQ,s small
2469 emit_opcode(cbuf, 0x74);
2470 emit_d8(cbuf, 0x04);
2471 // MOV $dst.lo,$dst.hi
2472 emit_opcode( cbuf, 0x8B );
2473 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2474 // CLR $dst.hi
2475 emit_opcode(cbuf, 0x33);
2476 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2477 // small:
2478 // SHRD $dst.lo,$dst.hi,$shift
2479 emit_opcode(cbuf,0x0F);
2480 emit_opcode(cbuf,0xAD);
2481 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2482 // SHR $dst.hi,$shift"
2483 emit_opcode(cbuf,0xD3);
2484 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2485 %}
2486
2487 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2488 // TEST shift,32
2489 emit_opcode(cbuf,0xF7);
2490 emit_rm(cbuf, 0x3, 0, ECX_enc);
2491 emit_d32(cbuf,0x20);
2492 // JEQ,s small
2493 emit_opcode(cbuf, 0x74);
2494 emit_d8(cbuf, 0x05);
2495 // MOV $dst.lo,$dst.hi
2496 emit_opcode( cbuf, 0x8B );
2497 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2498 // SAR $dst.hi,31
2499 emit_opcode(cbuf, 0xC1);
2500 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2501 emit_d8(cbuf, 0x1F );
2502 // small:
2503 // SHRD $dst.lo,$dst.hi,$shift
2504 emit_opcode(cbuf,0x0F);
2505 emit_opcode(cbuf,0xAD);
2506 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2507 // SAR $dst.hi,$shift"
2508 emit_opcode(cbuf,0xD3);
2509 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2510 %}
2511
2512
2513 // ----------------- Encodings for floating point unit -----------------
2514 // May leave result in FPU-TOS or FPU reg depending on opcodes
2515 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2516 $$$emit8$primary;
2517 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2518 %}
2519
2520 // Pop argument in FPR0 with FSTP ST(0)
2521 enc_class PopFPU() %{
2522 emit_opcode( cbuf, 0xDD );
2523 emit_d8( cbuf, 0xD8 );
2524 %}
2525
2526 // !!!!! equivalent to Pop_Reg_F
2527 enc_class Pop_Reg_D( regD dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2531
2532 enc_class Push_Reg_D( regD dst ) %{
2533 emit_opcode( cbuf, 0xD9 );
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2535 %}
2536
2537 enc_class strictfp_bias1( regD dst ) %{
2538 emit_opcode( cbuf, 0xDB ); // FLD m80real
2539 emit_opcode( cbuf, 0x2D );
2540 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2541 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2542 emit_opcode( cbuf, 0xC8+$dst$$reg );
2543 %}
2544
2545 enc_class strictfp_bias2( regD dst ) %{
2546 emit_opcode( cbuf, 0xDB ); // FLD m80real
2547 emit_opcode( cbuf, 0x2D );
2548 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2549 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2550 emit_opcode( cbuf, 0xC8+$dst$$reg );
2551 %}
2552
2553 // Special case for moving an integer register to a stack slot.
2554 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2555 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2556 %}
2557
2558 // Special case for moving a register to a stack slot.
2559 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2560 // Opcode already emitted
2561 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2562 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2563 emit_d32(cbuf, $dst$$disp); // Displacement
2564 %}
2565
2566 // Push the integer in stackSlot 'src' onto FP-stack
2567 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2568 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2569 %}
2570
2571 // Push the float in stackSlot 'src' onto FP-stack
2572 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2573 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2574 %}
2575
2576 // Push the double in stackSlot 'src' onto FP-stack
2577 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2578 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2579 %}
2580
2581 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2582 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2583 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2584 %}
2585
2586 // Same as Pop_Mem_F except for opcode
2587 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2588 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2589 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2590 %}
2591
2592 enc_class Pop_Reg_F( regF dst ) %{
2593 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2594 emit_d8( cbuf, 0xD8+$dst$$reg );
2595 %}
2596
2597 enc_class Push_Reg_F( regF dst ) %{
2598 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2599 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2600 %}
2601
2602 // Push FPU's float to a stack-slot, and pop FPU-stack
2603 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2604 int pop = 0x02;
2605 if ($src$$reg != FPR1L_enc) {
2606 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2607 emit_d8( cbuf, 0xC0-1+$src$$reg );
2608 pop = 0x03;
2609 }
2610 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2611 %}
2612
2613 // Push FPU's double to a stack-slot, and pop FPU-stack
2614 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2615 int pop = 0x02;
2616 if ($src$$reg != FPR1L_enc) {
2617 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2618 emit_d8( cbuf, 0xC0-1+$src$$reg );
2619 pop = 0x03;
2620 }
2621 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2622 %}
2623
2624 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2625 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2626 int pop = 0xD0 - 1; // -1 since we skip FLD
2627 if ($src$$reg != FPR1L_enc) {
2628 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2629 emit_d8( cbuf, 0xC0-1+$src$$reg );
2630 pop = 0xD8;
2631 }
2632 emit_opcode( cbuf, 0xDD );
2633 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2634 %}
2635
2636
2637 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2638 MacroAssembler masm(&cbuf);
2639 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2640 masm.fmul( $src2$$reg+0); // value at TOS
2641 masm.fadd( $src$$reg+0); // value at TOS
2642 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2643 %}
2644
2645
2646 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2647 // load dst in FPR0
2648 emit_opcode( cbuf, 0xD9 );
2649 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2650 if ($src$$reg != FPR1L_enc) {
2651 // fincstp
2652 emit_opcode (cbuf, 0xD9);
2653 emit_opcode (cbuf, 0xF7);
2654 // swap src with FPR1:
2655 // FXCH FPR1 with src
2656 emit_opcode(cbuf, 0xD9);
2657 emit_d8(cbuf, 0xC8-1+$src$$reg );
2658 // fdecstp
2659 emit_opcode (cbuf, 0xD9);
2660 emit_opcode (cbuf, 0xF6);
2661 }
2662 %}
2663
2664 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2665 // Allocate a word
2666 emit_opcode(cbuf,0x83); // SUB ESP,8
2667 emit_opcode(cbuf,0xEC);
2668 emit_d8(cbuf,0x08);
2669
2670 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2671 emit_opcode (cbuf, 0x0F );
2672 emit_opcode (cbuf, 0x11 );
2673 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2674
2675 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2676 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2677
2678 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2679 emit_opcode (cbuf, 0x0F );
2680 emit_opcode (cbuf, 0x11 );
2681 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2682
2683 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2684 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2685
2686 %}
2687
2688 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2689 // Allocate a word
2690 emit_opcode(cbuf,0x83); // SUB ESP,4
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8(cbuf,0x04);
2693
2694 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2695 emit_opcode (cbuf, 0x0F );
2696 emit_opcode (cbuf, 0x11 );
2697 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2698
2699 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2700 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2701
2702 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2706
2707 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709
2710 %}
2711
2712 enc_class Push_ResultXD(regXD dst) %{
2713 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2714
2715 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2716 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2717 emit_opcode (cbuf, 0x0F );
2718 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2719 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2720
2721 emit_opcode(cbuf,0x83); // ADD ESP,8
2722 emit_opcode(cbuf,0xC4);
2723 emit_d8(cbuf,0x08);
2724 %}
2725
2726 enc_class Push_ResultX(regX dst, immI d8) %{
2727 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2728
2729 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2730 emit_opcode (cbuf, 0x0F );
2731 emit_opcode (cbuf, 0x10 );
2732 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2733
2734 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2735 emit_opcode(cbuf,0xC4);
2736 emit_d8(cbuf,$d8$$constant);
2737 %}
2738
2739 enc_class Push_SrcXD(regXD src) %{
2740 // Allocate a word
2741 emit_opcode(cbuf,0x83); // SUB ESP,8
2742 emit_opcode(cbuf,0xEC);
2743 emit_d8(cbuf,0x08);
2744
2745 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2746 emit_opcode (cbuf, 0x0F );
2747 emit_opcode (cbuf, 0x11 );
2748 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2749
2750 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2751 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2752 %}
2753
2754 enc_class push_stack_temp_qword() %{
2755 emit_opcode(cbuf,0x83); // SUB ESP,8
2756 emit_opcode(cbuf,0xEC);
2757 emit_d8 (cbuf,0x08);
2758 %}
2759
2760 enc_class pop_stack_temp_qword() %{
2761 emit_opcode(cbuf,0x83); // ADD ESP,8
2762 emit_opcode(cbuf,0xC4);
2763 emit_d8 (cbuf,0x08);
2764 %}
2765
2766 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2767 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2768 emit_opcode (cbuf, 0x0F );
2769 emit_opcode (cbuf, 0x11 );
2770 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2771
2772 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2773 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2774 %}
2775
2776 // Compute X^Y using Intel's fast hardware instructions, if possible.
2777 // Otherwise return a NaN.
2778 enc_class pow_exp_core_encoding %{
2779 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2780 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2781 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2782 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2783 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2784 emit_opcode(cbuf,0x1C);
2785 emit_d8(cbuf,0x24);
2786 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2787 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2788 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2789 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2790 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2791 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2792 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2793 emit_d32(cbuf,0xFFFFF800);
2794 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2795 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2796 emit_d32(cbuf,1023);
2797 emit_opcode(cbuf,0x8B); // mov rbx,eax
2798 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2799 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2800 emit_rm(cbuf,0x3,0x4,EAX_enc);
2801 emit_d8(cbuf,20);
2802 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2803 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2804 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2805 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2806 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2807 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2808 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2809 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2810 emit_d32(cbuf,0);
2811 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2812 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2813 %}
2814
2815 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2816 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2817
2818 enc_class Push_Result_Mod_D( regD src) %{
2819 if ($src$$reg != FPR1L_enc) {
2820 // fincstp
2821 emit_opcode (cbuf, 0xD9);
2822 emit_opcode (cbuf, 0xF7);
2823 // FXCH FPR1 with src
2824 emit_opcode(cbuf, 0xD9);
2825 emit_d8(cbuf, 0xC8-1+$src$$reg );
2826 // fdecstp
2827 emit_opcode (cbuf, 0xD9);
2828 emit_opcode (cbuf, 0xF6);
2829 }
2830 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2831 // // FSTP FPR$dst$$reg
2832 // emit_opcode( cbuf, 0xDD );
2833 // emit_d8( cbuf, 0xD8+$dst$$reg );
2834 %}
2835
2836 enc_class fnstsw_sahf_skip_parity() %{
2837 // fnstsw ax
2838 emit_opcode( cbuf, 0xDF );
2839 emit_opcode( cbuf, 0xE0 );
2840 // sahf
2841 emit_opcode( cbuf, 0x9E );
2842 // jnp ::skip
2843 emit_opcode( cbuf, 0x7B );
2844 emit_opcode( cbuf, 0x05 );
2845 %}
2846
2847 enc_class emitModD() %{
2848 // fprem must be iterative
2849 // :: loop
2850 // fprem
2851 emit_opcode( cbuf, 0xD9 );
2852 emit_opcode( cbuf, 0xF8 );
2853 // wait
2854 emit_opcode( cbuf, 0x9b );
2855 // fnstsw ax
2856 emit_opcode( cbuf, 0xDF );
2857 emit_opcode( cbuf, 0xE0 );
2858 // sahf
2859 emit_opcode( cbuf, 0x9E );
2860 // jp ::loop
2861 emit_opcode( cbuf, 0x0F );
2862 emit_opcode( cbuf, 0x8A );
2863 emit_opcode( cbuf, 0xF4 );
2864 emit_opcode( cbuf, 0xFF );
2865 emit_opcode( cbuf, 0xFF );
2866 emit_opcode( cbuf, 0xFF );
2867 %}
2868
2869 enc_class fpu_flags() %{
2870 // fnstsw_ax
2871 emit_opcode( cbuf, 0xDF);
2872 emit_opcode( cbuf, 0xE0);
2873 // test ax,0x0400
2874 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2875 emit_opcode( cbuf, 0xA9 );
2876 emit_d16 ( cbuf, 0x0400 );
2877 // // // This sequence works, but stalls for 12-16 cycles on PPro
2878 // // test rax,0x0400
2879 // emit_opcode( cbuf, 0xA9 );
2880 // emit_d32 ( cbuf, 0x00000400 );
2881 //
2882 // jz exit (no unordered comparison)
2883 emit_opcode( cbuf, 0x74 );
2884 emit_d8 ( cbuf, 0x02 );
2885 // mov ah,1 - treat as LT case (set carry flag)
2886 emit_opcode( cbuf, 0xB4 );
2887 emit_d8 ( cbuf, 0x01 );
2888 // sahf
2889 emit_opcode( cbuf, 0x9E);
2890 %}
2891
2892 enc_class cmpF_P6_fixup() %{
2893 // Fixup the integer flags in case comparison involved a NaN
2894 //
2895 // JNP exit (no unordered comparison, P-flag is set by NaN)
2896 emit_opcode( cbuf, 0x7B );
2897 emit_d8 ( cbuf, 0x03 );
2898 // MOV AH,1 - treat as LT case (set carry flag)
2899 emit_opcode( cbuf, 0xB4 );
2900 emit_d8 ( cbuf, 0x01 );
2901 // SAHF
2902 emit_opcode( cbuf, 0x9E);
2903 // NOP // target for branch to avoid branch to branch
2904 emit_opcode( cbuf, 0x90);
2905 %}
2906
2907 // fnstsw_ax();
2908 // sahf();
2909 // movl(dst, nan_result);
2910 // jcc(Assembler::parity, exit);
2911 // movl(dst, less_result);
2912 // jcc(Assembler::below, exit);
2913 // movl(dst, equal_result);
2914 // jcc(Assembler::equal, exit);
2915 // movl(dst, greater_result);
2916
2917 // less_result = 1;
2918 // greater_result = -1;
2919 // equal_result = 0;
2920 // nan_result = -1;
2921
2922 enc_class CmpF_Result(eRegI dst) %{
2923 // fnstsw_ax();
2924 emit_opcode( cbuf, 0xDF);
2925 emit_opcode( cbuf, 0xE0);
2926 // sahf
2927 emit_opcode( cbuf, 0x9E);
2928 // movl(dst, nan_result);
2929 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2930 emit_d32( cbuf, -1 );
2931 // jcc(Assembler::parity, exit);
2932 emit_opcode( cbuf, 0x7A );
2933 emit_d8 ( cbuf, 0x13 );
2934 // movl(dst, less_result);
2935 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2936 emit_d32( cbuf, -1 );
2937 // jcc(Assembler::below, exit);
2938 emit_opcode( cbuf, 0x72 );
2939 emit_d8 ( cbuf, 0x0C );
2940 // movl(dst, equal_result);
2941 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2942 emit_d32( cbuf, 0 );
2943 // jcc(Assembler::equal, exit);
2944 emit_opcode( cbuf, 0x74 );
2945 emit_d8 ( cbuf, 0x05 );
2946 // movl(dst, greater_result);
2947 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2948 emit_d32( cbuf, 1 );
2949 %}
2950
2951
2952 // XMM version of CmpF_Result. Because the XMM compare
2953 // instructions set the EFLAGS directly. It becomes simpler than
2954 // the float version above.
2955 enc_class CmpX_Result(eRegI dst) %{
2956 MacroAssembler _masm(&cbuf);
2957 Label nan, inc, done;
2958
2959 __ jccb(Assembler::parity, nan);
2960 __ jccb(Assembler::equal, done);
2961 __ jccb(Assembler::above, inc);
2962 __ bind(nan);
2963 __ decrement(as_Register($dst$$reg)); // NO L qqq
2964 __ jmpb(done);
2965 __ bind(inc);
2966 __ increment(as_Register($dst$$reg)); // NO L qqq
2967 __ bind(done);
2968 %}
2969
2970 // Compare the longs and set flags
2971 // BROKEN! Do Not use as-is
2972 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2973 // CMP $src1.hi,$src2.hi
2974 emit_opcode( cbuf, 0x3B );
2975 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2976 // JNE,s done
2977 emit_opcode(cbuf,0x75);
2978 emit_d8(cbuf, 2 );
2979 // CMP $src1.lo,$src2.lo
2980 emit_opcode( cbuf, 0x3B );
2981 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2982 // done:
2983 %}
2984
2985 enc_class convert_int_long( regL dst, eRegI src ) %{
2986 // mov $dst.lo,$src
2987 int dst_encoding = $dst$$reg;
2988 int src_encoding = $src$$reg;
2989 encode_Copy( cbuf, dst_encoding , src_encoding );
2990 // mov $dst.hi,$src
2991 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2992 // sar $dst.hi,31
2993 emit_opcode( cbuf, 0xC1 );
2994 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2995 emit_d8(cbuf, 0x1F );
2996 %}
2997
2998 enc_class convert_long_double( eRegL src ) %{
2999 // push $src.hi
3000 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3001 // push $src.lo
3002 emit_opcode(cbuf, 0x50+$src$$reg );
3003 // fild 64-bits at [SP]
3004 emit_opcode(cbuf,0xdf);
3005 emit_d8(cbuf, 0x6C);
3006 emit_d8(cbuf, 0x24);
3007 emit_d8(cbuf, 0x00);
3008 // pop stack
3009 emit_opcode(cbuf, 0x83); // add SP, #8
3010 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3011 emit_d8(cbuf, 0x8);
3012 %}
3013
3014 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
3015 // IMUL EDX:EAX,$src1
3016 emit_opcode( cbuf, 0xF7 );
3017 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
3018 // SAR EDX,$cnt-32
3019 int shift_count = ((int)$cnt$$constant) - 32;
3020 if (shift_count > 0) {
3021 emit_opcode(cbuf, 0xC1);
3022 emit_rm(cbuf, 0x3, 7, $dst$$reg );
3023 emit_d8(cbuf, shift_count);
3024 }
3025 %}
3026
3027 // this version doesn't have add sp, 8
3028 enc_class convert_long_double2( eRegL src ) %{
3029 // push $src.hi
3030 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3031 // push $src.lo
3032 emit_opcode(cbuf, 0x50+$src$$reg );
3033 // fild 64-bits at [SP]
3034 emit_opcode(cbuf,0xdf);
3035 emit_d8(cbuf, 0x6C);
3036 emit_d8(cbuf, 0x24);
3037 emit_d8(cbuf, 0x00);
3038 %}
3039
3040 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
3041 // Basic idea: long = (long)int * (long)int
3042 // IMUL EDX:EAX, src
3043 emit_opcode( cbuf, 0xF7 );
3044 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3045 %}
3046
3047 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3048 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3049 // MUL EDX:EAX, src
3050 emit_opcode( cbuf, 0xF7 );
3051 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3052 %}
3053
3054 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3055 // Basic idea: lo(result) = lo(x_lo * y_lo)
3056 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3057 // MOV $tmp,$src.lo
3058 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3059 // IMUL $tmp,EDX
3060 emit_opcode( cbuf, 0x0F );
3061 emit_opcode( cbuf, 0xAF );
3062 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3063 // MOV EDX,$src.hi
3064 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3065 // IMUL EDX,EAX
3066 emit_opcode( cbuf, 0x0F );
3067 emit_opcode( cbuf, 0xAF );
3068 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3069 // ADD $tmp,EDX
3070 emit_opcode( cbuf, 0x03 );
3071 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3072 // MUL EDX:EAX,$src.lo
3073 emit_opcode( cbuf, 0xF7 );
3074 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3075 // ADD EDX,ESI
3076 emit_opcode( cbuf, 0x03 );
3077 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3078 %}
3079
3080 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3081 // Basic idea: lo(result) = lo(src * y_lo)
3082 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3083 // IMUL $tmp,EDX,$src
3084 emit_opcode( cbuf, 0x6B );
3085 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3086 emit_d8( cbuf, (int)$src$$constant );
3087 // MOV EDX,$src
3088 emit_opcode(cbuf, 0xB8 + EDX_enc);
3089 emit_d32( cbuf, (int)$src$$constant );
3090 // MUL EDX:EAX,EDX
3091 emit_opcode( cbuf, 0xF7 );
3092 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3093 // ADD EDX,ESI
3094 emit_opcode( cbuf, 0x03 );
3095 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3096 %}
3097
3098 enc_class long_div( eRegL src1, eRegL src2 ) %{
3099 // PUSH src1.hi
3100 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3101 // PUSH src1.lo
3102 emit_opcode(cbuf, 0x50+$src1$$reg );
3103 // PUSH src2.hi
3104 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3105 // PUSH src2.lo
3106 emit_opcode(cbuf, 0x50+$src2$$reg );
3107 // CALL directly to the runtime
3108 cbuf.set_inst_mark();
3109 emit_opcode(cbuf,0xE8); // Call into runtime
3110 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3111 // Restore stack
3112 emit_opcode(cbuf, 0x83); // add SP, #framesize
3113 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3114 emit_d8(cbuf, 4*4);
3115 %}
3116
3117 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3118 // PUSH src1.hi
3119 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3120 // PUSH src1.lo
3121 emit_opcode(cbuf, 0x50+$src1$$reg );
3122 // PUSH src2.hi
3123 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3124 // PUSH src2.lo
3125 emit_opcode(cbuf, 0x50+$src2$$reg );
3126 // CALL directly to the runtime
3127 cbuf.set_inst_mark();
3128 emit_opcode(cbuf,0xE8); // Call into runtime
3129 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3130 // Restore stack
3131 emit_opcode(cbuf, 0x83); // add SP, #framesize
3132 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3133 emit_d8(cbuf, 4*4);
3134 %}
3135
3136 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3137 // MOV $tmp,$src.lo
3138 emit_opcode(cbuf, 0x8B);
3139 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3140 // OR $tmp,$src.hi
3141 emit_opcode(cbuf, 0x0B);
3142 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3143 %}
3144
3145 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3146 // CMP $src1.lo,$src2.lo
3147 emit_opcode( cbuf, 0x3B );
3148 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3149 // JNE,s skip
3150 emit_cc(cbuf, 0x70, 0x5);
3151 emit_d8(cbuf,2);
3152 // CMP $src1.hi,$src2.hi
3153 emit_opcode( cbuf, 0x3B );
3154 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3155 %}
3156
3157 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3158 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3159 emit_opcode( cbuf, 0x3B );
3160 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3161 // MOV $tmp,$src1.hi
3162 emit_opcode( cbuf, 0x8B );
3163 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3164 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3165 emit_opcode( cbuf, 0x1B );
3166 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3167 %}
3168
3169 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3170 // XOR $tmp,$tmp
3171 emit_opcode(cbuf,0x33); // XOR
3172 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3173 // CMP $tmp,$src.lo
3174 emit_opcode( cbuf, 0x3B );
3175 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3176 // SBB $tmp,$src.hi
3177 emit_opcode( cbuf, 0x1B );
3178 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3179 %}
3180
3181 // Sniff, sniff... smells like Gnu Superoptimizer
3182 enc_class neg_long( eRegL dst ) %{
3183 emit_opcode(cbuf,0xF7); // NEG hi
3184 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3185 emit_opcode(cbuf,0xF7); // NEG lo
3186 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3187 emit_opcode(cbuf,0x83); // SBB hi,0
3188 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3189 emit_d8 (cbuf,0 );
3190 %}
3191
3192 enc_class movq_ld(regXD dst, memory mem) %{
3193 MacroAssembler _masm(&cbuf);
3194 __ movq($dst$$XMMRegister, $mem$$Address);
3195 %}
3196
3197 enc_class movq_st(memory mem, regXD src) %{
3198 MacroAssembler _masm(&cbuf);
3199 __ movq($mem$$Address, $src$$XMMRegister);
3200 %}
3201
3202 enc_class pshufd_8x8(regX dst, regX src) %{
3203 MacroAssembler _masm(&cbuf);
3204
3205 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3206 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3207 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3208 %}
3209
3210 enc_class pshufd_4x16(regX dst, regX src) %{
3211 MacroAssembler _masm(&cbuf);
3212
3213 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3214 %}
3215
3216 enc_class pshufd(regXD dst, regXD src, int mode) %{
3217 MacroAssembler _masm(&cbuf);
3218
3219 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3220 %}
3221
3222 enc_class pxor(regXD dst, regXD src) %{
3223 MacroAssembler _masm(&cbuf);
3224
3225 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3226 %}
3227
3228 enc_class mov_i2x(regXD dst, eRegI src) %{
3229 MacroAssembler _masm(&cbuf);
3230
3231 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3232 %}
3233
3234
3235 // Because the transitions from emitted code to the runtime
3236 // monitorenter/exit helper stubs are so slow it's critical that
3237 // we inline both the stack-locking fast-path and the inflated fast path.
3238 //
3239 // See also: cmpFastLock and cmpFastUnlock.
3240 //
3241 // What follows is a specialized inline transliteration of the code
3242 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3243 // another option would be to emit TrySlowEnter and TrySlowExit methods
3244 // at startup-time. These methods would accept arguments as
3245 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3246 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3247 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3248 // In practice, however, the # of lock sites is bounded and is usually small.
3249 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3250 // if the processor uses simple bimodal branch predictors keyed by EIP
3251 // Since the helper routines would be called from multiple synchronization
3252 // sites.
3253 //
3254 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3255 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3256 // to those specialized methods. That'd give us a mostly platform-independent
3257 // implementation that the JITs could optimize and inline at their pleasure.
3258 // Done correctly, the only time we'd need to cross to native could would be
3259 // to park() or unpark() threads. We'd also need a few more unsafe operators
3260 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3261 // (b) explicit barriers or fence operations.
3262 //
3263 // TODO:
3264 //
3265 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3266 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3267 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3268 // the lock operators would typically be faster than reifying Self.
3269 //
3270 // * Ideally I'd define the primitives as:
3271 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3272 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3273 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3274 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3275 // Furthermore the register assignments are overconstrained, possibly resulting in
3276 // sub-optimal code near the synchronization site.
3277 //
3278 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3279 // Alternately, use a better sp-proximity test.
3280 //
3281 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3282 // Either one is sufficient to uniquely identify a thread.
3283 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3284 //
3285 // * Intrinsify notify() and notifyAll() for the common cases where the
3286 // object is locked by the calling thread but the waitlist is empty.
3287 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3288 //
3289 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3290 // But beware of excessive branch density on AMD Opterons.
3291 //
3292 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3293 // or failure of the fast-path. If the fast-path fails then we pass
3294 // control to the slow-path, typically in C. In Fast_Lock and
3295 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3296 // will emit a conditional branch immediately after the node.
3297 // So we have branches to branches and lots of ICC.ZF games.
3298 // Instead, it might be better to have C2 pass a "FailureLabel"
3299 // into Fast_Lock and Fast_Unlock. In the case of success, control
3300 // will drop through the node. ICC.ZF is undefined at exit.
3301 // In the case of failure, the node will branch directly to the
3302 // FailureLabel
3303
3304
3305 // obj: object to lock
3306 // box: on-stack box address (displaced header location) - KILLED
3307 // rax,: tmp -- KILLED
3308 // scr: tmp -- KILLED
3309 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3310
3311 Register objReg = as_Register($obj$$reg);
3312 Register boxReg = as_Register($box$$reg);
3313 Register tmpReg = as_Register($tmp$$reg);
3314 Register scrReg = as_Register($scr$$reg);
3315
3316 // Ensure the register assignents are disjoint
3317 guarantee (objReg != boxReg, "") ;
3318 guarantee (objReg != tmpReg, "") ;
3319 guarantee (objReg != scrReg, "") ;
3320 guarantee (boxReg != tmpReg, "") ;
3321 guarantee (boxReg != scrReg, "") ;
3322 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3323
3324 MacroAssembler masm(&cbuf);
3325
3326 if (_counters != NULL) {
3327 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3328 }
3329 if (EmitSync & 1) {
3330 // set box->dhw = unused_mark (3)
3331 // Force all sync thru slow-path: slow_enter() and slow_exit()
3332 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3333 masm.cmpptr (rsp, (int32_t)0) ;
3334 } else
3335 if (EmitSync & 2) {
3336 Label DONE_LABEL ;
3337 if (UseBiasedLocking) {
3338 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3339 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3340 }
3341
3342 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3343 masm.orptr (tmpReg, 0x1);
3344 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3345 if (os::is_MP()) { masm.lock(); }
3346 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3347 masm.jcc(Assembler::equal, DONE_LABEL);
3348 // Recursive locking
3349 masm.subptr(tmpReg, rsp);
3350 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3351 masm.movptr(Address(boxReg, 0), tmpReg);
3352 masm.bind(DONE_LABEL) ;
3353 } else {
3354 // Possible cases that we'll encounter in fast_lock
3355 // ------------------------------------------------
3356 // * Inflated
3357 // -- unlocked
3358 // -- Locked
3359 // = by self
3360 // = by other
3361 // * biased
3362 // -- by Self
3363 // -- by other
3364 // * neutral
3365 // * stack-locked
3366 // -- by self
3367 // = sp-proximity test hits
3368 // = sp-proximity test generates false-negative
3369 // -- by other
3370 //
3371
3372 Label IsInflated, DONE_LABEL, PopDone ;
3373
3374 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3375 // order to reduce the number of conditional branches in the most common cases.
3376 // Beware -- there's a subtle invariant that fetch of the markword
3377 // at [FETCH], below, will never observe a biased encoding (*101b).
3378 // If this invariant is not held we risk exclusion (safety) failure.
3379 if (UseBiasedLocking && !UseOptoBiasInlining) {
3380 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3381 }
3382
3383 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3384 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3385 masm.jccb (Assembler::notZero, IsInflated) ;
3386
3387 // Attempt stack-locking ...
3388 masm.orptr (tmpReg, 0x1);
3389 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3390 if (os::is_MP()) { masm.lock(); }
3391 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3392 if (_counters != NULL) {
3393 masm.cond_inc32(Assembler::equal,
3394 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3395 }
3396 masm.jccb (Assembler::equal, DONE_LABEL);
3397
3398 // Recursive locking
3399 masm.subptr(tmpReg, rsp);
3400 masm.andptr(tmpReg, 0xFFFFF003 );
3401 masm.movptr(Address(boxReg, 0), tmpReg);
3402 if (_counters != NULL) {
3403 masm.cond_inc32(Assembler::equal,
3404 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3405 }
3406 masm.jmp (DONE_LABEL) ;
3407
3408 masm.bind (IsInflated) ;
3409
3410 // The object is inflated.
3411 //
3412 // TODO-FIXME: eliminate the ugly use of manifest constants:
3413 // Use markOopDesc::monitor_value instead of "2".
3414 // use markOop::unused_mark() instead of "3".
3415 // The tmpReg value is an objectMonitor reference ORed with
3416 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3417 // objectmonitor pointer by masking off the "2" bit or we can just
3418 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3419 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3420 //
3421 // I use the latter as it avoids AGI stalls.
3422 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3423 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3424 //
3425 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3426
3427 // boxReg refers to the on-stack BasicLock in the current frame.
3428 // We'd like to write:
3429 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3430 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3431 // additional latency as we have another ST in the store buffer that must drain.
3432
3433 if (EmitSync & 8192) {
3434 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3435 masm.get_thread (scrReg) ;
3436 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3437 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3438 if (os::is_MP()) { masm.lock(); }
3439 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3440 } else
3441 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3442 masm.movptr(scrReg, boxReg) ;
3443 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3444
3445 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3446 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3447 // prefetchw [eax + Offset(_owner)-2]
3448 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3449 }
3450
3451 if ((EmitSync & 64) == 0) {
3452 // Optimistic form: consider XORL tmpReg,tmpReg
3453 masm.movptr(tmpReg, NULL_WORD) ;
3454 } else {
3455 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3456 // Test-And-CAS instead of CAS
3457 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3458 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3459 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3460 }
3461
3462 // Appears unlocked - try to swing _owner from null to non-null.
3463 // Ideally, I'd manifest "Self" with get_thread and then attempt
3464 // to CAS the register containing Self into m->Owner.
3465 // But we don't have enough registers, so instead we can either try to CAS
3466 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3467 // we later store "Self" into m->Owner. Transiently storing a stack address
3468 // (rsp or the address of the box) into m->owner is harmless.
3469 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3470 if (os::is_MP()) { masm.lock(); }
3471 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3472 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3473 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3474 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3475 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3476 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3477
3478 // If the CAS fails we can either retry or pass control to the slow-path.
3479 // We use the latter tactic.
3480 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3481 // If the CAS was successful ...
3482 // Self has acquired the lock
3483 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3484 // Intentional fall-through into DONE_LABEL ...
3485 } else {
3486 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3487 masm.movptr(boxReg, tmpReg) ;
3488
3489 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3490 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3491 // prefetchw [eax + Offset(_owner)-2]
3492 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3493 }
3494
3495 if ((EmitSync & 64) == 0) {
3496 // Optimistic form
3497 masm.xorptr (tmpReg, tmpReg) ;
3498 } else {
3499 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3500 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3501 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3502 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3503 }
3504
3505 // Appears unlocked - try to swing _owner from null to non-null.
3506 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3507 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3508 masm.get_thread (scrReg) ;
3509 if (os::is_MP()) { masm.lock(); }
3510 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3511
3512 // If the CAS fails we can either retry or pass control to the slow-path.
3513 // We use the latter tactic.
3514 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3515 // If the CAS was successful ...
3516 // Self has acquired the lock
3517 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3518 // Intentional fall-through into DONE_LABEL ...
3519 }
3520
3521 // DONE_LABEL is a hot target - we'd really like to place it at the
3522 // start of cache line by padding with NOPs.
3523 // See the AMD and Intel software optimization manuals for the
3524 // most efficient "long" NOP encodings.
3525 // Unfortunately none of our alignment mechanisms suffice.
3526 masm.bind(DONE_LABEL);
3527
3528 // Avoid branch-to-branch on AMD processors
3529 // This appears to be superstition.
3530 if (EmitSync & 32) masm.nop() ;
3531
3532
3533 // At DONE_LABEL the icc ZFlag is set as follows ...
3534 // Fast_Unlock uses the same protocol.
3535 // ZFlag == 1 -> Success
3536 // ZFlag == 0 -> Failure - force control through the slow-path
3537 }
3538 %}
3539
3540 // obj: object to unlock
3541 // box: box address (displaced header location), killed. Must be EAX.
3542 // rbx,: killed tmp; cannot be obj nor box.
3543 //
3544 // Some commentary on balanced locking:
3545 //
3546 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3547 // Methods that don't have provably balanced locking are forced to run in the
3548 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3549 // The interpreter provides two properties:
3550 // I1: At return-time the interpreter automatically and quietly unlocks any
3551 // objects acquired the current activation (frame). Recall that the
3552 // interpreter maintains an on-stack list of locks currently held by
3553 // a frame.
3554 // I2: If a method attempts to unlock an object that is not held by the
3555 // the frame the interpreter throws IMSX.
3556 //
3557 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3558 // B() doesn't have provably balanced locking so it runs in the interpreter.
3559 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3560 // is still locked by A().
3561 //
3562 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3563 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3564 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3565 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3566
3567 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3568
3569 Register objReg = as_Register($obj$$reg);
3570 Register boxReg = as_Register($box$$reg);
3571 Register tmpReg = as_Register($tmp$$reg);
3572
3573 guarantee (objReg != boxReg, "") ;
3574 guarantee (objReg != tmpReg, "") ;
3575 guarantee (boxReg != tmpReg, "") ;
3576 guarantee (boxReg == as_Register(EAX_enc), "") ;
3577 MacroAssembler masm(&cbuf);
3578
3579 if (EmitSync & 4) {
3580 // Disable - inhibit all inlining. Force control through the slow-path
3581 masm.cmpptr (rsp, 0) ;
3582 } else
3583 if (EmitSync & 8) {
3584 Label DONE_LABEL ;
3585 if (UseBiasedLocking) {
3586 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3587 }
3588 // classic stack-locking code ...
3589 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3590 masm.testptr(tmpReg, tmpReg) ;
3591 masm.jcc (Assembler::zero, DONE_LABEL) ;
3592 if (os::is_MP()) { masm.lock(); }
3593 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3594 masm.bind(DONE_LABEL);
3595 } else {
3596 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3597
3598 // Critically, the biased locking test must have precedence over
3599 // and appear before the (box->dhw == 0) recursive stack-lock test.
3600 if (UseBiasedLocking && !UseOptoBiasInlining) {
3601 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3602 }
3603
3604 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3605 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3606 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3607
3608 masm.testptr(tmpReg, 0x02) ; // Inflated?
3609 masm.jccb (Assembler::zero, Stacked) ;
3610
3611 masm.bind (Inflated) ;
3612 // It's inflated.
3613 // Despite our balanced locking property we still check that m->_owner == Self
3614 // as java routines or native JNI code called by this thread might
3615 // have released the lock.
3616 // Refer to the comments in synchronizer.cpp for how we might encode extra
3617 // state in _succ so we can avoid fetching EntryList|cxq.
3618 //
3619 // I'd like to add more cases in fast_lock() and fast_unlock() --
3620 // such as recursive enter and exit -- but we have to be wary of
3621 // I$ bloat, T$ effects and BP$ effects.
3622 //
3623 // If there's no contention try a 1-0 exit. That is, exit without
3624 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3625 // we detect and recover from the race that the 1-0 exit admits.
3626 //
3627 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3628 // before it STs null into _owner, releasing the lock. Updates
3629 // to data protected by the critical section must be visible before
3630 // we drop the lock (and thus before any other thread could acquire
3631 // the lock and observe the fields protected by the lock).
3632 // IA32's memory-model is SPO, so STs are ordered with respect to
3633 // each other and there's no need for an explicit barrier (fence).
3634 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3635
3636 masm.get_thread (boxReg) ;
3637 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3638 // prefetchw [ebx + Offset(_owner)-2]
3639 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3640 }
3641
3642 // Note that we could employ various encoding schemes to reduce
3643 // the number of loads below (currently 4) to just 2 or 3.
3644 // Refer to the comments in synchronizer.cpp.
3645 // In practice the chain of fetches doesn't seem to impact performance, however.
3646 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3647 // Attempt to reduce branch density - AMD's branch predictor.
3648 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3649 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3650 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3651 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3652 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3653 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3654 masm.jmpb (DONE_LABEL) ;
3655 } else {
3656 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3657 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3658 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3659 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3660 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3661 masm.jccb (Assembler::notZero, CheckSucc) ;
3662 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3663 masm.jmpb (DONE_LABEL) ;
3664 }
3665
3666 // The Following code fragment (EmitSync & 65536) improves the performance of
3667 // contended applications and contended synchronization microbenchmarks.
3668 // Unfortunately the emission of the code - even though not executed - causes regressions
3669 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3670 // with an equal number of never-executed NOPs results in the same regression.
3671 // We leave it off by default.
3672
3673 if ((EmitSync & 65536) != 0) {
3674 Label LSuccess, LGoSlowPath ;
3675
3676 masm.bind (CheckSucc) ;
3677
3678 // Optional pre-test ... it's safe to elide this
3679 if ((EmitSync & 16) == 0) {
3680 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3681 masm.jccb (Assembler::zero, LGoSlowPath) ;
3682 }
3683
3684 // We have a classic Dekker-style idiom:
3685 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3686 // There are a number of ways to implement the barrier:
3687 // (1) lock:andl &m->_owner, 0
3688 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3689 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3690 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3691 // (2) If supported, an explicit MFENCE is appealing.
3692 // In older IA32 processors MFENCE is slower than lock:add or xchg
3693 // particularly if the write-buffer is full as might be the case if
3694 // if stores closely precede the fence or fence-equivalent instruction.
3695 // In more modern implementations MFENCE appears faster, however.
3696 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3697 // The $lines underlying the top-of-stack should be in M-state.
3698 // The locked add instruction is serializing, of course.
3699 // (4) Use xchg, which is serializing
3700 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3701 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3702 // The integer condition codes will tell us if succ was 0.
3703 // Since _succ and _owner should reside in the same $line and
3704 // we just stored into _owner, it's likely that the $line
3705 // remains in M-state for the lock:orl.
3706 //
3707 // We currently use (3), although it's likely that switching to (2)
3708 // is correct for the future.
3709
3710 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3711 if (os::is_MP()) {
3712 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3713 masm.mfence();
3714 } else {
3715 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3716 }
3717 }
3718 // Ratify _succ remains non-null
3719 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3720 masm.jccb (Assembler::notZero, LSuccess) ;
3721
3722 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3723 if (os::is_MP()) { masm.lock(); }
3724 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3725 masm.jccb (Assembler::notEqual, LSuccess) ;
3726 // Since we're low on registers we installed rsp as a placeholding in _owner.
3727 // Now install Self over rsp. This is safe as we're transitioning from
3728 // non-null to non=null
3729 masm.get_thread (boxReg) ;
3730 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3731 // Intentional fall-through into LGoSlowPath ...
3732
3733 masm.bind (LGoSlowPath) ;
3734 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3735 masm.jmpb (DONE_LABEL) ;
3736
3737 masm.bind (LSuccess) ;
3738 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3739 masm.jmpb (DONE_LABEL) ;
3740 }
3741
3742 masm.bind (Stacked) ;
3743 // It's not inflated and it's not recursively stack-locked and it's not biased.
3744 // It must be stack-locked.
3745 // Try to reset the header to displaced header.
3746 // The "box" value on the stack is stable, so we can reload
3747 // and be assured we observe the same value as above.
3748 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3749 if (os::is_MP()) { masm.lock(); }
3750 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3751 // Intention fall-thru into DONE_LABEL
3752
3753
3754 // DONE_LABEL is a hot target - we'd really like to place it at the
3755 // start of cache line by padding with NOPs.
3756 // See the AMD and Intel software optimization manuals for the
3757 // most efficient "long" NOP encodings.
3758 // Unfortunately none of our alignment mechanisms suffice.
3759 if ((EmitSync & 65536) == 0) {
3760 masm.bind (CheckSucc) ;
3761 }
3762 masm.bind(DONE_LABEL);
3763
3764 // Avoid branch to branch on AMD processors
3765 if (EmitSync & 32768) { masm.nop() ; }
3766 }
3767 %}
3768
3769
3770 enc_class enc_pop_rdx() %{
3771 emit_opcode(cbuf,0x5A);
3772 %}
3773
3774 enc_class enc_rethrow() %{
3775 cbuf.set_inst_mark();
3776 emit_opcode(cbuf, 0xE9); // jmp entry
3777 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3778 runtime_call_Relocation::spec(), RELOC_IMM32 );
3779 %}
3780
3781
3782 // Convert a double to an int. Java semantics require we do complex
3783 // manglelations in the corner cases. So we set the rounding mode to
3784 // 'zero', store the darned double down as an int, and reset the
3785 // rounding mode to 'nearest'. The hardware throws an exception which
3786 // patches up the correct value directly to the stack.
3787 enc_class D2I_encoding( regD src ) %{
3788 // Flip to round-to-zero mode. We attempted to allow invalid-op
3789 // exceptions here, so that a NAN or other corner-case value will
3790 // thrown an exception (but normal values get converted at full speed).
3791 // However, I2C adapters and other float-stack manglers leave pending
3792 // invalid-op exceptions hanging. We would have to clear them before
3793 // enabling them and that is more expensive than just testing for the
3794 // invalid value Intel stores down in the corner cases.
3795 emit_opcode(cbuf,0xD9); // FLDCW trunc
3796 emit_opcode(cbuf,0x2D);
3797 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3798 // Allocate a word
3799 emit_opcode(cbuf,0x83); // SUB ESP,4
3800 emit_opcode(cbuf,0xEC);
3801 emit_d8(cbuf,0x04);
3802 // Encoding assumes a double has been pushed into FPR0.
3803 // Store down the double as an int, popping the FPU stack
3804 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3805 emit_opcode(cbuf,0x1C);
3806 emit_d8(cbuf,0x24);
3807 // Restore the rounding mode; mask the exception
3808 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3809 emit_opcode(cbuf,0x2D);
3810 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3811 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3812 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3813
3814 // Load the converted int; adjust CPU stack
3815 emit_opcode(cbuf,0x58); // POP EAX
3816 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3817 emit_d32 (cbuf,0x80000000); // 0x80000000
3818 emit_opcode(cbuf,0x75); // JNE around_slow_call
3819 emit_d8 (cbuf,0x07); // Size of slow_call
3820 // Push src onto stack slow-path
3821 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3822 emit_d8 (cbuf,0xC0-1+$src$$reg );
3823 // CALL directly to the runtime
3824 cbuf.set_inst_mark();
3825 emit_opcode(cbuf,0xE8); // Call into runtime
3826 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3827 // Carry on here...
3828 %}
3829
3830 enc_class D2L_encoding( regD src ) %{
3831 emit_opcode(cbuf,0xD9); // FLDCW trunc
3832 emit_opcode(cbuf,0x2D);
3833 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3834 // Allocate a word
3835 emit_opcode(cbuf,0x83); // SUB ESP,8
3836 emit_opcode(cbuf,0xEC);
3837 emit_d8(cbuf,0x08);
3838 // Encoding assumes a double has been pushed into FPR0.
3839 // Store down the double as a long, popping the FPU stack
3840 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3841 emit_opcode(cbuf,0x3C);
3842 emit_d8(cbuf,0x24);
3843 // Restore the rounding mode; mask the exception
3844 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3845 emit_opcode(cbuf,0x2D);
3846 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3847 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3848 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3849
3850 // Load the converted int; adjust CPU stack
3851 emit_opcode(cbuf,0x58); // POP EAX
3852 emit_opcode(cbuf,0x5A); // POP EDX
3853 emit_opcode(cbuf,0x81); // CMP EDX,imm
3854 emit_d8 (cbuf,0xFA); // rdx
3855 emit_d32 (cbuf,0x80000000); // 0x80000000
3856 emit_opcode(cbuf,0x75); // JNE around_slow_call
3857 emit_d8 (cbuf,0x07+4); // Size of slow_call
3858 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3859 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3860 emit_opcode(cbuf,0x75); // JNE around_slow_call
3861 emit_d8 (cbuf,0x07); // Size of slow_call
3862 // Push src onto stack slow-path
3863 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3864 emit_d8 (cbuf,0xC0-1+$src$$reg );
3865 // CALL directly to the runtime
3866 cbuf.set_inst_mark();
3867 emit_opcode(cbuf,0xE8); // Call into runtime
3868 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3869 // Carry on here...
3870 %}
3871
3872 enc_class X2L_encoding( regX src ) %{
3873 // Allocate a word
3874 emit_opcode(cbuf,0x83); // SUB ESP,8
3875 emit_opcode(cbuf,0xEC);
3876 emit_d8(cbuf,0x08);
3877
3878 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3879 emit_opcode (cbuf, 0x0F );
3880 emit_opcode (cbuf, 0x11 );
3881 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3882
3883 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3884 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3885
3886 emit_opcode(cbuf,0xD9); // FLDCW trunc
3887 emit_opcode(cbuf,0x2D);
3888 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3889
3890 // Encoding assumes a double has been pushed into FPR0.
3891 // Store down the double as a long, popping the FPU stack
3892 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3893 emit_opcode(cbuf,0x3C);
3894 emit_d8(cbuf,0x24);
3895
3896 // Restore the rounding mode; mask the exception
3897 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3898 emit_opcode(cbuf,0x2D);
3899 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3900 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3901 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3902
3903 // Load the converted int; adjust CPU stack
3904 emit_opcode(cbuf,0x58); // POP EAX
3905
3906 emit_opcode(cbuf,0x5A); // POP EDX
3907
3908 emit_opcode(cbuf,0x81); // CMP EDX,imm
3909 emit_d8 (cbuf,0xFA); // rdx
3910 emit_d32 (cbuf,0x80000000);// 0x80000000
3911
3912 emit_opcode(cbuf,0x75); // JNE around_slow_call
3913 emit_d8 (cbuf,0x13+4); // Size of slow_call
3914
3915 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3916 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3917
3918 emit_opcode(cbuf,0x75); // JNE around_slow_call
3919 emit_d8 (cbuf,0x13); // Size of slow_call
3920
3921 // Allocate a word
3922 emit_opcode(cbuf,0x83); // SUB ESP,4
3923 emit_opcode(cbuf,0xEC);
3924 emit_d8(cbuf,0x04);
3925
3926 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3927 emit_opcode (cbuf, 0x0F );
3928 emit_opcode (cbuf, 0x11 );
3929 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3930
3931 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3932 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3933
3934 emit_opcode(cbuf,0x83); // ADD ESP,4
3935 emit_opcode(cbuf,0xC4);
3936 emit_d8(cbuf,0x04);
3937
3938 // CALL directly to the runtime
3939 cbuf.set_inst_mark();
3940 emit_opcode(cbuf,0xE8); // Call into runtime
3941 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3942 // Carry on here...
3943 %}
3944
3945 enc_class XD2L_encoding( regXD src ) %{
3946 // Allocate a word
3947 emit_opcode(cbuf,0x83); // SUB ESP,8
3948 emit_opcode(cbuf,0xEC);
3949 emit_d8(cbuf,0x08);
3950
3951 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3952 emit_opcode (cbuf, 0x0F );
3953 emit_opcode (cbuf, 0x11 );
3954 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3955
3956 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3957 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3958
3959 emit_opcode(cbuf,0xD9); // FLDCW trunc
3960 emit_opcode(cbuf,0x2D);
3961 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3962
3963 // Encoding assumes a double has been pushed into FPR0.
3964 // Store down the double as a long, popping the FPU stack
3965 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3966 emit_opcode(cbuf,0x3C);
3967 emit_d8(cbuf,0x24);
3968
3969 // Restore the rounding mode; mask the exception
3970 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3971 emit_opcode(cbuf,0x2D);
3972 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3973 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3974 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3975
3976 // Load the converted int; adjust CPU stack
3977 emit_opcode(cbuf,0x58); // POP EAX
3978
3979 emit_opcode(cbuf,0x5A); // POP EDX
3980
3981 emit_opcode(cbuf,0x81); // CMP EDX,imm
3982 emit_d8 (cbuf,0xFA); // rdx
3983 emit_d32 (cbuf,0x80000000); // 0x80000000
3984
3985 emit_opcode(cbuf,0x75); // JNE around_slow_call
3986 emit_d8 (cbuf,0x13+4); // Size of slow_call
3987
3988 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3989 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3990
3991 emit_opcode(cbuf,0x75); // JNE around_slow_call
3992 emit_d8 (cbuf,0x13); // Size of slow_call
3993
3994 // Push src onto stack slow-path
3995 // Allocate a word
3996 emit_opcode(cbuf,0x83); // SUB ESP,8
3997 emit_opcode(cbuf,0xEC);
3998 emit_d8(cbuf,0x08);
3999
4000 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4001 emit_opcode (cbuf, 0x0F );
4002 emit_opcode (cbuf, 0x11 );
4003 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4004
4005 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4006 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4007
4008 emit_opcode(cbuf,0x83); // ADD ESP,8
4009 emit_opcode(cbuf,0xC4);
4010 emit_d8(cbuf,0x08);
4011
4012 // CALL directly to the runtime
4013 cbuf.set_inst_mark();
4014 emit_opcode(cbuf,0xE8); // Call into runtime
4015 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4016 // Carry on here...
4017 %}
4018
4019 enc_class D2X_encoding( regX dst, regD src ) %{
4020 // Allocate a word
4021 emit_opcode(cbuf,0x83); // SUB ESP,4
4022 emit_opcode(cbuf,0xEC);
4023 emit_d8(cbuf,0x04);
4024 int pop = 0x02;
4025 if ($src$$reg != FPR1L_enc) {
4026 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4027 emit_d8( cbuf, 0xC0-1+$src$$reg );
4028 pop = 0x03;
4029 }
4030 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4031
4032 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4033 emit_opcode (cbuf, 0x0F );
4034 emit_opcode (cbuf, 0x10 );
4035 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4036
4037 emit_opcode(cbuf,0x83); // ADD ESP,4
4038 emit_opcode(cbuf,0xC4);
4039 emit_d8(cbuf,0x04);
4040 // Carry on here...
4041 %}
4042
4043 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4044 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4045
4046 // Compare the result to see if we need to go to the slow path
4047 emit_opcode(cbuf,0x81); // CMP dst,imm
4048 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4049 emit_d32 (cbuf,0x80000000); // 0x80000000
4050
4051 emit_opcode(cbuf,0x75); // JNE around_slow_call
4052 emit_d8 (cbuf,0x13); // Size of slow_call
4053 // Store xmm to a temp memory
4054 // location and push it onto stack.
4055
4056 emit_opcode(cbuf,0x83); // SUB ESP,4
4057 emit_opcode(cbuf,0xEC);
4058 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4059
4060 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4061 emit_opcode (cbuf, 0x0F );
4062 emit_opcode (cbuf, 0x11 );
4063 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4064
4065 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4066 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4067
4068 emit_opcode(cbuf,0x83); // ADD ESP,4
4069 emit_opcode(cbuf,0xC4);
4070 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4071
4072 // CALL directly to the runtime
4073 cbuf.set_inst_mark();
4074 emit_opcode(cbuf,0xE8); // Call into runtime
4075 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4076
4077 // Carry on here...
4078 %}
4079
4080 enc_class X2D_encoding( regD dst, regX src ) %{
4081 // Allocate a word
4082 emit_opcode(cbuf,0x83); // SUB ESP,4
4083 emit_opcode(cbuf,0xEC);
4084 emit_d8(cbuf,0x04);
4085
4086 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4087 emit_opcode (cbuf, 0x0F );
4088 emit_opcode (cbuf, 0x11 );
4089 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4090
4091 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4092 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4093
4094 emit_opcode(cbuf,0x83); // ADD ESP,4
4095 emit_opcode(cbuf,0xC4);
4096 emit_d8(cbuf,0x04);
4097
4098 // Carry on here...
4099 %}
4100
4101 enc_class AbsXF_encoding(regX dst) %{
4102 address signmask_address=(address)float_signmask_pool;
4103 // andpd:\tANDPS $dst,[signconst]
4104 emit_opcode(cbuf, 0x0F);
4105 emit_opcode(cbuf, 0x54);
4106 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4107 emit_d32(cbuf, (int)signmask_address);
4108 %}
4109
4110 enc_class AbsXD_encoding(regXD dst) %{
4111 address signmask_address=(address)double_signmask_pool;
4112 // andpd:\tANDPD $dst,[signconst]
4113 emit_opcode(cbuf, 0x66);
4114 emit_opcode(cbuf, 0x0F);
4115 emit_opcode(cbuf, 0x54);
4116 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4117 emit_d32(cbuf, (int)signmask_address);
4118 %}
4119
4120 enc_class NegXF_encoding(regX dst) %{
4121 address signmask_address=(address)float_signflip_pool;
4122 // andpd:\tXORPS $dst,[signconst]
4123 emit_opcode(cbuf, 0x0F);
4124 emit_opcode(cbuf, 0x57);
4125 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4126 emit_d32(cbuf, (int)signmask_address);
4127 %}
4128
4129 enc_class NegXD_encoding(regXD dst) %{
4130 address signmask_address=(address)double_signflip_pool;
4131 // andpd:\tXORPD $dst,[signconst]
4132 emit_opcode(cbuf, 0x66);
4133 emit_opcode(cbuf, 0x0F);
4134 emit_opcode(cbuf, 0x57);
4135 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4136 emit_d32(cbuf, (int)signmask_address);
4137 %}
4138
4139 enc_class FMul_ST_reg( eRegF src1 ) %{
4140 // Operand was loaded from memory into fp ST (stack top)
4141 // FMUL ST,$src /* D8 C8+i */
4142 emit_opcode(cbuf, 0xD8);
4143 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4144 %}
4145
4146 enc_class FAdd_ST_reg( eRegF src2 ) %{
4147 // FADDP ST,src2 /* D8 C0+i */
4148 emit_opcode(cbuf, 0xD8);
4149 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4150 //could use FADDP src2,fpST /* DE C0+i */
4151 %}
4152
4153 enc_class FAddP_reg_ST( eRegF src2 ) %{
4154 // FADDP src2,ST /* DE C0+i */
4155 emit_opcode(cbuf, 0xDE);
4156 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4157 %}
4158
4159 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4160 // Operand has been loaded into fp ST (stack top)
4161 // FSUB ST,$src1
4162 emit_opcode(cbuf, 0xD8);
4163 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4164
4165 // FDIV
4166 emit_opcode(cbuf, 0xD8);
4167 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4168 %}
4169
4170 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4171 // Operand was loaded from memory into fp ST (stack top)
4172 // FADD ST,$src /* D8 C0+i */
4173 emit_opcode(cbuf, 0xD8);
4174 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4175
4176 // FMUL ST,src2 /* D8 C*+i */
4177 emit_opcode(cbuf, 0xD8);
4178 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4179 %}
4180
4181
4182 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4183 // Operand was loaded from memory into fp ST (stack top)
4184 // FADD ST,$src /* D8 C0+i */
4185 emit_opcode(cbuf, 0xD8);
4186 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4187
4188 // FMULP src2,ST /* DE C8+i */
4189 emit_opcode(cbuf, 0xDE);
4190 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4191 %}
4192
4193 // Atomically load the volatile long
4194 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4195 emit_opcode(cbuf,0xDF);
4196 int rm_byte_opcode = 0x05;
4197 int base = $mem$$base;
4198 int index = $mem$$index;
4199 int scale = $mem$$scale;
4200 int displace = $mem$$disp;
4201 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4202 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4203 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4204 %}
4205
4206 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4207 { // Atomic long load
4208 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4209 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4210 emit_opcode(cbuf,0x0F);
4211 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4212 int base = $mem$$base;
4213 int index = $mem$$index;
4214 int scale = $mem$$scale;
4215 int displace = $mem$$disp;
4216 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4217 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4218 }
4219 { // MOVSD $dst,$tmp ! atomic long store
4220 emit_opcode(cbuf,0xF2);
4221 emit_opcode(cbuf,0x0F);
4222 emit_opcode(cbuf,0x11);
4223 int base = $dst$$base;
4224 int index = $dst$$index;
4225 int scale = $dst$$scale;
4226 int displace = $dst$$disp;
4227 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4228 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4229 }
4230 %}
4231
4232 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4233 { // Atomic long load
4234 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4235 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4236 emit_opcode(cbuf,0x0F);
4237 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4238 int base = $mem$$base;
4239 int index = $mem$$index;
4240 int scale = $mem$$scale;
4241 int displace = $mem$$disp;
4242 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4243 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4244 }
4245 { // MOVD $dst.lo,$tmp
4246 emit_opcode(cbuf,0x66);
4247 emit_opcode(cbuf,0x0F);
4248 emit_opcode(cbuf,0x7E);
4249 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4250 }
4251 { // PSRLQ $tmp,32
4252 emit_opcode(cbuf,0x66);
4253 emit_opcode(cbuf,0x0F);
4254 emit_opcode(cbuf,0x73);
4255 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4256 emit_d8(cbuf, 0x20);
4257 }
4258 { // MOVD $dst.hi,$tmp
4259 emit_opcode(cbuf,0x66);
4260 emit_opcode(cbuf,0x0F);
4261 emit_opcode(cbuf,0x7E);
4262 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4263 }
4264 %}
4265
4266 // Volatile Store Long. Must be atomic, so move it into
4267 // the FP TOS and then do a 64-bit FIST. Has to probe the
4268 // target address before the store (for null-ptr checks)
4269 // so the memory operand is used twice in the encoding.
4270 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4271 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4272 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4273 emit_opcode(cbuf,0xDF);
4274 int rm_byte_opcode = 0x07;
4275 int base = $mem$$base;
4276 int index = $mem$$index;
4277 int scale = $mem$$scale;
4278 int displace = $mem$$disp;
4279 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4280 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4281 %}
4282
4283 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4284 { // Atomic long load
4285 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4286 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4287 emit_opcode(cbuf,0x0F);
4288 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4289 int base = $src$$base;
4290 int index = $src$$index;
4291 int scale = $src$$scale;
4292 int displace = $src$$disp;
4293 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4294 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4295 }
4296 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4297 { // MOVSD $mem,$tmp ! atomic long store
4298 emit_opcode(cbuf,0xF2);
4299 emit_opcode(cbuf,0x0F);
4300 emit_opcode(cbuf,0x11);
4301 int base = $mem$$base;
4302 int index = $mem$$index;
4303 int scale = $mem$$scale;
4304 int displace = $mem$$disp;
4305 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4306 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4307 }
4308 %}
4309
4310 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4311 { // MOVD $tmp,$src.lo
4312 emit_opcode(cbuf,0x66);
4313 emit_opcode(cbuf,0x0F);
4314 emit_opcode(cbuf,0x6E);
4315 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4316 }
4317 { // MOVD $tmp2,$src.hi
4318 emit_opcode(cbuf,0x66);
4319 emit_opcode(cbuf,0x0F);
4320 emit_opcode(cbuf,0x6E);
4321 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4322 }
4323 { // PUNPCKLDQ $tmp,$tmp2
4324 emit_opcode(cbuf,0x66);
4325 emit_opcode(cbuf,0x0F);
4326 emit_opcode(cbuf,0x62);
4327 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4328 }
4329 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4330 { // MOVSD $mem,$tmp ! atomic long store
4331 emit_opcode(cbuf,0xF2);
4332 emit_opcode(cbuf,0x0F);
4333 emit_opcode(cbuf,0x11);
4334 int base = $mem$$base;
4335 int index = $mem$$index;
4336 int scale = $mem$$scale;
4337 int displace = $mem$$disp;
4338 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4339 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4340 }
4341 %}
4342
4343 // Safepoint Poll. This polls the safepoint page, and causes an
4344 // exception if it is not readable. Unfortunately, it kills the condition code
4345 // in the process
4346 // We current use TESTL [spp],EDI
4347 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4348
4349 enc_class Safepoint_Poll() %{
4350 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4351 emit_opcode(cbuf,0x85);
4352 emit_rm (cbuf, 0x0, 0x7, 0x5);
4353 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4354 %}
4355 %}
4356
4357
4358 //----------FRAME--------------------------------------------------------------
4359 // Definition of frame structure and management information.
4360 //
4361 // S T A C K L A Y O U T Allocators stack-slot number
4362 // | (to get allocators register number
4363 // G Owned by | | v add OptoReg::stack0())
4364 // r CALLER | |
4365 // o | +--------+ pad to even-align allocators stack-slot
4366 // w V | pad0 | numbers; owned by CALLER
4367 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4368 // h ^ | in | 5
4369 // | | args | 4 Holes in incoming args owned by SELF
4370 // | | | | 3
4371 // | | +--------+
4372 // V | | old out| Empty on Intel, window on Sparc
4373 // | old |preserve| Must be even aligned.
4374 // | SP-+--------+----> Matcher::_old_SP, even aligned
4375 // | | in | 3 area for Intel ret address
4376 // Owned by |preserve| Empty on Sparc.
4377 // SELF +--------+
4378 // | | pad2 | 2 pad to align old SP
4379 // | +--------+ 1
4380 // | | locks | 0
4381 // | +--------+----> OptoReg::stack0(), even aligned
4382 // | | pad1 | 11 pad to align new SP
4383 // | +--------+
4384 // | | | 10
4385 // | | spills | 9 spills
4386 // V | | 8 (pad0 slot for callee)
4387 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4388 // ^ | out | 7
4389 // | | args | 6 Holes in outgoing args owned by CALLEE
4390 // Owned by +--------+
4391 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4392 // | new |preserve| Must be even-aligned.
4393 // | SP-+--------+----> Matcher::_new_SP, even aligned
4394 // | | |
4395 //
4396 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4397 // known from SELF's arguments and the Java calling convention.
4398 // Region 6-7 is determined per call site.
4399 // Note 2: If the calling convention leaves holes in the incoming argument
4400 // area, those holes are owned by SELF. Holes in the outgoing area
4401 // are owned by the CALLEE. Holes should not be nessecary in the
4402 // incoming area, as the Java calling convention is completely under
4403 // the control of the AD file. Doubles can be sorted and packed to
4404 // avoid holes. Holes in the outgoing arguments may be nessecary for
4405 // varargs C calling conventions.
4406 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4407 // even aligned with pad0 as needed.
4408 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4409 // region 6-11 is even aligned; it may be padded out more so that
4410 // the region from SP to FP meets the minimum stack alignment.
4411
4412 frame %{
4413 // What direction does stack grow in (assumed to be same for C & Java)
4414 stack_direction(TOWARDS_LOW);
4415
4416 // These three registers define part of the calling convention
4417 // between compiled code and the interpreter.
4418 inline_cache_reg(EAX); // Inline Cache Register
4419 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4420
4421 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4422 cisc_spilling_operand_name(indOffset32);
4423
4424 // Number of stack slots consumed by locking an object
4425 sync_stack_slots(1);
4426
4427 // Compiled code's Frame Pointer
4428 frame_pointer(ESP);
4429 // Interpreter stores its frame pointer in a register which is
4430 // stored to the stack by I2CAdaptors.
4431 // I2CAdaptors convert from interpreted java to compiled java.
4432 interpreter_frame_pointer(EBP);
4433
4434 // Stack alignment requirement
4435 // Alignment size in bytes (128-bit -> 16 bytes)
4436 stack_alignment(StackAlignmentInBytes);
4437
4438 // Number of stack slots between incoming argument block and the start of
4439 // a new frame. The PROLOG must add this many slots to the stack. The
4440 // EPILOG must remove this many slots. Intel needs one slot for
4441 // return address and one for rbp, (must save rbp)
4442 in_preserve_stack_slots(2+VerifyStackAtCalls);
4443
4444 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4445 // for calls to C. Supports the var-args backing area for register parms.
4446 varargs_C_out_slots_killed(0);
4447
4448 // The after-PROLOG location of the return address. Location of
4449 // return address specifies a type (REG or STACK) and a number
4450 // representing the register number (i.e. - use a register name) or
4451 // stack slot.
4452 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4453 // Otherwise, it is above the locks and verification slot and alignment word
4454 return_addr(STACK - 1 +
4455 round_to(1+VerifyStackAtCalls+
4456 Compile::current()->fixed_slots(),
4457 (StackAlignmentInBytes/wordSize)));
4458
4459 // Body of function which returns an integer array locating
4460 // arguments either in registers or in stack slots. Passed an array
4461 // of ideal registers called "sig" and a "length" count. Stack-slot
4462 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4463 // arguments for a CALLEE. Incoming stack arguments are
4464 // automatically biased by the preserve_stack_slots field above.
4465 calling_convention %{
4466 // No difference between ingoing/outgoing just pass false
4467 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4468 %}
4469
4470
4471 // Body of function which returns an integer array locating
4472 // arguments either in registers or in stack slots. Passed an array
4473 // of ideal registers called "sig" and a "length" count. Stack-slot
4474 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4475 // arguments for a CALLEE. Incoming stack arguments are
4476 // automatically biased by the preserve_stack_slots field above.
4477 c_calling_convention %{
4478 // This is obviously always outgoing
4479 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4480 %}
4481
4482 // Location of C & interpreter return values
4483 c_return_value %{
4484 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4485 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4486 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4487
4488 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4489 // that C functions return float and double results in XMM0.
4490 if( ideal_reg == Op_RegD && UseSSE>=2 )
4491 return OptoRegPair(XMM0b_num,XMM0a_num);
4492 if( ideal_reg == Op_RegF && UseSSE>=2 )
4493 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4494
4495 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4496 %}
4497
4498 // Location of return values
4499 return_value %{
4500 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4501 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4502 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4503 if( ideal_reg == Op_RegD && UseSSE>=2 )
4504 return OptoRegPair(XMM0b_num,XMM0a_num);
4505 if( ideal_reg == Op_RegF && UseSSE>=1 )
4506 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4507 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4508 %}
4509
4510 %}
4511
4512 //----------ATTRIBUTES---------------------------------------------------------
4513 //----------Operand Attributes-------------------------------------------------
4514 op_attrib op_cost(0); // Required cost attribute
4515
4516 //----------Instruction Attributes---------------------------------------------
4517 ins_attrib ins_cost(100); // Required cost attribute
4518 ins_attrib ins_size(8); // Required size attribute (in bits)
4519 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4520 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4521 // non-matching short branch variant of some
4522 // long branch?
4523 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4524 // specifies the alignment that some part of the instruction (not
4525 // necessarily the start) requires. If > 1, a compute_padding()
4526 // function must be provided for the instruction
4527
4528 //----------OPERANDS-----------------------------------------------------------
4529 // Operand definitions must precede instruction definitions for correct parsing
4530 // in the ADLC because operands constitute user defined types which are used in
4531 // instruction definitions.
4532
4533 //----------Simple Operands----------------------------------------------------
4534 // Immediate Operands
4535 // Integer Immediate
4536 operand immI() %{
4537 match(ConI);
4538
4539 op_cost(10);
4540 format %{ %}
4541 interface(CONST_INTER);
4542 %}
4543
4544 // Constant for test vs zero
4545 operand immI0() %{
4546 predicate(n->get_int() == 0);
4547 match(ConI);
4548
4549 op_cost(0);
4550 format %{ %}
4551 interface(CONST_INTER);
4552 %}
4553
4554 // Constant for increment
4555 operand immI1() %{
4556 predicate(n->get_int() == 1);
4557 match(ConI);
4558
4559 op_cost(0);
4560 format %{ %}
4561 interface(CONST_INTER);
4562 %}
4563
4564 // Constant for decrement
4565 operand immI_M1() %{
4566 predicate(n->get_int() == -1);
4567 match(ConI);
4568
4569 op_cost(0);
4570 format %{ %}
4571 interface(CONST_INTER);
4572 %}
4573
4574 // Valid scale values for addressing modes
4575 operand immI2() %{
4576 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4577 match(ConI);
4578
4579 format %{ %}
4580 interface(CONST_INTER);
4581 %}
4582
4583 operand immI8() %{
4584 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4585 match(ConI);
4586
4587 op_cost(5);
4588 format %{ %}
4589 interface(CONST_INTER);
4590 %}
4591
4592 operand immI16() %{
4593 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4594 match(ConI);
4595
4596 op_cost(10);
4597 format %{ %}
4598 interface(CONST_INTER);
4599 %}
4600
4601 // Constant for long shifts
4602 operand immI_32() %{
4603 predicate( n->get_int() == 32 );
4604 match(ConI);
4605
4606 op_cost(0);
4607 format %{ %}
4608 interface(CONST_INTER);
4609 %}
4610
4611 operand immI_1_31() %{
4612 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4613 match(ConI);
4614
4615 op_cost(0);
4616 format %{ %}
4617 interface(CONST_INTER);
4618 %}
4619
4620 operand immI_32_63() %{
4621 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4622 match(ConI);
4623 op_cost(0);
4624
4625 format %{ %}
4626 interface(CONST_INTER);
4627 %}
4628
4629 operand immI_1() %{
4630 predicate( n->get_int() == 1 );
4631 match(ConI);
4632
4633 op_cost(0);
4634 format %{ %}
4635 interface(CONST_INTER);
4636 %}
4637
4638 operand immI_2() %{
4639 predicate( n->get_int() == 2 );
4640 match(ConI);
4641
4642 op_cost(0);
4643 format %{ %}
4644 interface(CONST_INTER);
4645 %}
4646
4647 operand immI_3() %{
4648 predicate( n->get_int() == 3 );
4649 match(ConI);
4650
4651 op_cost(0);
4652 format %{ %}
4653 interface(CONST_INTER);
4654 %}
4655
4656 // Pointer Immediate
4657 operand immP() %{
4658 match(ConP);
4659
4660 op_cost(10);
4661 format %{ %}
4662 interface(CONST_INTER);
4663 %}
4664
4665 // NULL Pointer Immediate
4666 operand immP0() %{
4667 predicate( n->get_ptr() == 0 );
4668 match(ConP);
4669 op_cost(0);
4670
4671 format %{ %}
4672 interface(CONST_INTER);
4673 %}
4674
4675 // Long Immediate
4676 operand immL() %{
4677 match(ConL);
4678
4679 op_cost(20);
4680 format %{ %}
4681 interface(CONST_INTER);
4682 %}
4683
4684 // Long Immediate zero
4685 operand immL0() %{
4686 predicate( n->get_long() == 0L );
4687 match(ConL);
4688 op_cost(0);
4689
4690 format %{ %}
4691 interface(CONST_INTER);
4692 %}
4693
4694 // Long Immediate zero
4695 operand immL_M1() %{
4696 predicate( n->get_long() == -1L );
4697 match(ConL);
4698 op_cost(0);
4699
4700 format %{ %}
4701 interface(CONST_INTER);
4702 %}
4703
4704 // Long immediate from 0 to 127.
4705 // Used for a shorter form of long mul by 10.
4706 operand immL_127() %{
4707 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4708 match(ConL);
4709 op_cost(0);
4710
4711 format %{ %}
4712 interface(CONST_INTER);
4713 %}
4714
4715 // Long Immediate: low 32-bit mask
4716 operand immL_32bits() %{
4717 predicate(n->get_long() == 0xFFFFFFFFL);
4718 match(ConL);
4719 op_cost(0);
4720
4721 format %{ %}
4722 interface(CONST_INTER);
4723 %}
4724
4725 // Long Immediate: low 32-bit mask
4726 operand immL32() %{
4727 predicate(n->get_long() == (int)(n->get_long()));
4728 match(ConL);
4729 op_cost(20);
4730
4731 format %{ %}
4732 interface(CONST_INTER);
4733 %}
4734
4735 //Double Immediate zero
4736 operand immD0() %{
4737 // Do additional (and counter-intuitive) test against NaN to work around VC++
4738 // bug that generates code such that NaNs compare equal to 0.0
4739 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4740 match(ConD);
4741
4742 op_cost(5);
4743 format %{ %}
4744 interface(CONST_INTER);
4745 %}
4746
4747 // Double Immediate
4748 operand immD1() %{
4749 predicate( UseSSE<=1 && n->getd() == 1.0 );
4750 match(ConD);
4751
4752 op_cost(5);
4753 format %{ %}
4754 interface(CONST_INTER);
4755 %}
4756
4757 // Double Immediate
4758 operand immD() %{
4759 predicate(UseSSE<=1);
4760 match(ConD);
4761
4762 op_cost(5);
4763 format %{ %}
4764 interface(CONST_INTER);
4765 %}
4766
4767 operand immXD() %{
4768 predicate(UseSSE>=2);
4769 match(ConD);
4770
4771 op_cost(5);
4772 format %{ %}
4773 interface(CONST_INTER);
4774 %}
4775
4776 // Double Immediate zero
4777 operand immXD0() %{
4778 // Do additional (and counter-intuitive) test against NaN to work around VC++
4779 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4780 // compare equal to -0.0.
4781 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4782 match(ConD);
4783
4784 format %{ %}
4785 interface(CONST_INTER);
4786 %}
4787
4788 // Float Immediate zero
4789 operand immF0() %{
4790 predicate( UseSSE == 0 && n->getf() == 0.0 );
4791 match(ConF);
4792
4793 op_cost(5);
4794 format %{ %}
4795 interface(CONST_INTER);
4796 %}
4797
4798 // Float Immediate
4799 operand immF() %{
4800 predicate( UseSSE == 0 );
4801 match(ConF);
4802
4803 op_cost(5);
4804 format %{ %}
4805 interface(CONST_INTER);
4806 %}
4807
4808 // Float Immediate
4809 operand immXF() %{
4810 predicate(UseSSE >= 1);
4811 match(ConF);
4812
4813 op_cost(5);
4814 format %{ %}
4815 interface(CONST_INTER);
4816 %}
4817
4818 // Float Immediate zero. Zero and not -0.0
4819 operand immXF0() %{
4820 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4821 match(ConF);
4822
4823 op_cost(5);
4824 format %{ %}
4825 interface(CONST_INTER);
4826 %}
4827
4828 // Immediates for special shifts (sign extend)
4829
4830 // Constants for increment
4831 operand immI_16() %{
4832 predicate( n->get_int() == 16 );
4833 match(ConI);
4834
4835 format %{ %}
4836 interface(CONST_INTER);
4837 %}
4838
4839 operand immI_24() %{
4840 predicate( n->get_int() == 24 );
4841 match(ConI);
4842
4843 format %{ %}
4844 interface(CONST_INTER);
4845 %}
4846
4847 // Constant for byte-wide masking
4848 operand immI_255() %{
4849 predicate( n->get_int() == 255 );
4850 match(ConI);
4851
4852 format %{ %}
4853 interface(CONST_INTER);
4854 %}
4855
4856 // Constant for short-wide masking
4857 operand immI_65535() %{
4858 predicate(n->get_int() == 65535);
4859 match(ConI);
4860
4861 format %{ %}
4862 interface(CONST_INTER);
4863 %}
4864
4865 // Register Operands
4866 // Integer Register
4867 operand eRegI() %{
4868 constraint(ALLOC_IN_RC(e_reg));
4869 match(RegI);
4870 match(xRegI);
4871 match(eAXRegI);
4872 match(eBXRegI);
4873 match(eCXRegI);
4874 match(eDXRegI);
4875 match(eDIRegI);
4876 match(eSIRegI);
4877
4878 format %{ %}
4879 interface(REG_INTER);
4880 %}
4881
4882 // Subset of Integer Register
4883 operand xRegI(eRegI reg) %{
4884 constraint(ALLOC_IN_RC(x_reg));
4885 match(reg);
4886 match(eAXRegI);
4887 match(eBXRegI);
4888 match(eCXRegI);
4889 match(eDXRegI);
4890
4891 format %{ %}
4892 interface(REG_INTER);
4893 %}
4894
4895 // Special Registers
4896 operand eAXRegI(xRegI reg) %{
4897 constraint(ALLOC_IN_RC(eax_reg));
4898 match(reg);
4899 match(eRegI);
4900
4901 format %{ "EAX" %}
4902 interface(REG_INTER);
4903 %}
4904
4905 // Special Registers
4906 operand eBXRegI(xRegI reg) %{
4907 constraint(ALLOC_IN_RC(ebx_reg));
4908 match(reg);
4909 match(eRegI);
4910
4911 format %{ "EBX" %}
4912 interface(REG_INTER);
4913 %}
4914
4915 operand eCXRegI(xRegI reg) %{
4916 constraint(ALLOC_IN_RC(ecx_reg));
4917 match(reg);
4918 match(eRegI);
4919
4920 format %{ "ECX" %}
4921 interface(REG_INTER);
4922 %}
4923
4924 operand eDXRegI(xRegI reg) %{
4925 constraint(ALLOC_IN_RC(edx_reg));
4926 match(reg);
4927 match(eRegI);
4928
4929 format %{ "EDX" %}
4930 interface(REG_INTER);
4931 %}
4932
4933 operand eDIRegI(xRegI reg) %{
4934 constraint(ALLOC_IN_RC(edi_reg));
4935 match(reg);
4936 match(eRegI);
4937
4938 format %{ "EDI" %}
4939 interface(REG_INTER);
4940 %}
4941
4942 operand naxRegI() %{
4943 constraint(ALLOC_IN_RC(nax_reg));
4944 match(RegI);
4945 match(eCXRegI);
4946 match(eDXRegI);
4947 match(eSIRegI);
4948 match(eDIRegI);
4949
4950 format %{ %}
4951 interface(REG_INTER);
4952 %}
4953
4954 operand nadxRegI() %{
4955 constraint(ALLOC_IN_RC(nadx_reg));
4956 match(RegI);
4957 match(eBXRegI);
4958 match(eCXRegI);
4959 match(eSIRegI);
4960 match(eDIRegI);
4961
4962 format %{ %}
4963 interface(REG_INTER);
4964 %}
4965
4966 operand ncxRegI() %{
4967 constraint(ALLOC_IN_RC(ncx_reg));
4968 match(RegI);
4969 match(eAXRegI);
4970 match(eDXRegI);
4971 match(eSIRegI);
4972 match(eDIRegI);
4973
4974 format %{ %}
4975 interface(REG_INTER);
4976 %}
4977
4978 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4979 // //
4980 operand eSIRegI(xRegI reg) %{
4981 constraint(ALLOC_IN_RC(esi_reg));
4982 match(reg);
4983 match(eRegI);
4984
4985 format %{ "ESI" %}
4986 interface(REG_INTER);
4987 %}
4988
4989 // Pointer Register
4990 operand anyRegP() %{
4991 constraint(ALLOC_IN_RC(any_reg));
4992 match(RegP);
4993 match(eAXRegP);
4994 match(eBXRegP);
4995 match(eCXRegP);
4996 match(eDIRegP);
4997 match(eRegP);
4998
4999 format %{ %}
5000 interface(REG_INTER);
5001 %}
5002
5003 operand eRegP() %{
5004 constraint(ALLOC_IN_RC(e_reg));
5005 match(RegP);
5006 match(eAXRegP);
5007 match(eBXRegP);
5008 match(eCXRegP);
5009 match(eDIRegP);
5010
5011 format %{ %}
5012 interface(REG_INTER);
5013 %}
5014
5015 // On windows95, EBP is not safe to use for implicit null tests.
5016 operand eRegP_no_EBP() %{
5017 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5018 match(RegP);
5019 match(eAXRegP);
5020 match(eBXRegP);
5021 match(eCXRegP);
5022 match(eDIRegP);
5023
5024 op_cost(100);
5025 format %{ %}
5026 interface(REG_INTER);
5027 %}
5028
5029 operand naxRegP() %{
5030 constraint(ALLOC_IN_RC(nax_reg));
5031 match(RegP);
5032 match(eBXRegP);
5033 match(eDXRegP);
5034 match(eCXRegP);
5035 match(eSIRegP);
5036 match(eDIRegP);
5037
5038 format %{ %}
5039 interface(REG_INTER);
5040 %}
5041
5042 operand nabxRegP() %{
5043 constraint(ALLOC_IN_RC(nabx_reg));
5044 match(RegP);
5045 match(eCXRegP);
5046 match(eDXRegP);
5047 match(eSIRegP);
5048 match(eDIRegP);
5049
5050 format %{ %}
5051 interface(REG_INTER);
5052 %}
5053
5054 operand pRegP() %{
5055 constraint(ALLOC_IN_RC(p_reg));
5056 match(RegP);
5057 match(eBXRegP);
5058 match(eDXRegP);
5059 match(eSIRegP);
5060 match(eDIRegP);
5061
5062 format %{ %}
5063 interface(REG_INTER);
5064 %}
5065
5066 // Special Registers
5067 // Return a pointer value
5068 operand eAXRegP(eRegP reg) %{
5069 constraint(ALLOC_IN_RC(eax_reg));
5070 match(reg);
5071 format %{ "EAX" %}
5072 interface(REG_INTER);
5073 %}
5074
5075 // Used in AtomicAdd
5076 operand eBXRegP(eRegP reg) %{
5077 constraint(ALLOC_IN_RC(ebx_reg));
5078 match(reg);
5079 format %{ "EBX" %}
5080 interface(REG_INTER);
5081 %}
5082
5083 // Tail-call (interprocedural jump) to interpreter
5084 operand eCXRegP(eRegP reg) %{
5085 constraint(ALLOC_IN_RC(ecx_reg));
5086 match(reg);
5087 format %{ "ECX" %}
5088 interface(REG_INTER);
5089 %}
5090
5091 operand eSIRegP(eRegP reg) %{
5092 constraint(ALLOC_IN_RC(esi_reg));
5093 match(reg);
5094 format %{ "ESI" %}
5095 interface(REG_INTER);
5096 %}
5097
5098 // Used in rep stosw
5099 operand eDIRegP(eRegP reg) %{
5100 constraint(ALLOC_IN_RC(edi_reg));
5101 match(reg);
5102 format %{ "EDI" %}
5103 interface(REG_INTER);
5104 %}
5105
5106 operand eBPRegP() %{
5107 constraint(ALLOC_IN_RC(ebp_reg));
5108 match(RegP);
5109 format %{ "EBP" %}
5110 interface(REG_INTER);
5111 %}
5112
5113 operand eRegL() %{
5114 constraint(ALLOC_IN_RC(long_reg));
5115 match(RegL);
5116 match(eADXRegL);
5117
5118 format %{ %}
5119 interface(REG_INTER);
5120 %}
5121
5122 operand eADXRegL( eRegL reg ) %{
5123 constraint(ALLOC_IN_RC(eadx_reg));
5124 match(reg);
5125
5126 format %{ "EDX:EAX" %}
5127 interface(REG_INTER);
5128 %}
5129
5130 operand eBCXRegL( eRegL reg ) %{
5131 constraint(ALLOC_IN_RC(ebcx_reg));
5132 match(reg);
5133
5134 format %{ "EBX:ECX" %}
5135 interface(REG_INTER);
5136 %}
5137
5138 // Special case for integer high multiply
5139 operand eADXRegL_low_only() %{
5140 constraint(ALLOC_IN_RC(eadx_reg));
5141 match(RegL);
5142
5143 format %{ "EAX" %}
5144 interface(REG_INTER);
5145 %}
5146
5147 // Flags register, used as output of compare instructions
5148 operand eFlagsReg() %{
5149 constraint(ALLOC_IN_RC(int_flags));
5150 match(RegFlags);
5151
5152 format %{ "EFLAGS" %}
5153 interface(REG_INTER);
5154 %}
5155
5156 // Flags register, used as output of FLOATING POINT compare instructions
5157 operand eFlagsRegU() %{
5158 constraint(ALLOC_IN_RC(int_flags));
5159 match(RegFlags);
5160
5161 format %{ "EFLAGS_U" %}
5162 interface(REG_INTER);
5163 %}
5164
5165 operand eFlagsRegUCF() %{
5166 constraint(ALLOC_IN_RC(int_flags));
5167 match(RegFlags);
5168 predicate(false);
5169
5170 format %{ "EFLAGS_U_CF" %}
5171 interface(REG_INTER);
5172 %}
5173
5174 // Condition Code Register used by long compare
5175 operand flagsReg_long_LTGE() %{
5176 constraint(ALLOC_IN_RC(int_flags));
5177 match(RegFlags);
5178 format %{ "FLAGS_LTGE" %}
5179 interface(REG_INTER);
5180 %}
5181 operand flagsReg_long_EQNE() %{
5182 constraint(ALLOC_IN_RC(int_flags));
5183 match(RegFlags);
5184 format %{ "FLAGS_EQNE" %}
5185 interface(REG_INTER);
5186 %}
5187 operand flagsReg_long_LEGT() %{
5188 constraint(ALLOC_IN_RC(int_flags));
5189 match(RegFlags);
5190 format %{ "FLAGS_LEGT" %}
5191 interface(REG_INTER);
5192 %}
5193
5194 // Float register operands
5195 operand regD() %{
5196 predicate( UseSSE < 2 );
5197 constraint(ALLOC_IN_RC(dbl_reg));
5198 match(RegD);
5199 match(regDPR1);
5200 match(regDPR2);
5201 format %{ %}
5202 interface(REG_INTER);
5203 %}
5204
5205 operand regDPR1(regD reg) %{
5206 predicate( UseSSE < 2 );
5207 constraint(ALLOC_IN_RC(dbl_reg0));
5208 match(reg);
5209 format %{ "FPR1" %}
5210 interface(REG_INTER);
5211 %}
5212
5213 operand regDPR2(regD reg) %{
5214 predicate( UseSSE < 2 );
5215 constraint(ALLOC_IN_RC(dbl_reg1));
5216 match(reg);
5217 format %{ "FPR2" %}
5218 interface(REG_INTER);
5219 %}
5220
5221 operand regnotDPR1(regD reg) %{
5222 predicate( UseSSE < 2 );
5223 constraint(ALLOC_IN_RC(dbl_notreg0));
5224 match(reg);
5225 format %{ %}
5226 interface(REG_INTER);
5227 %}
5228
5229 // XMM Double register operands
5230 operand regXD() %{
5231 predicate( UseSSE>=2 );
5232 constraint(ALLOC_IN_RC(xdb_reg));
5233 match(RegD);
5234 match(regXD6);
5235 match(regXD7);
5236 format %{ %}
5237 interface(REG_INTER);
5238 %}
5239
5240 // XMM6 double register operands
5241 operand regXD6(regXD reg) %{
5242 predicate( UseSSE>=2 );
5243 constraint(ALLOC_IN_RC(xdb_reg6));
5244 match(reg);
5245 format %{ "XMM6" %}
5246 interface(REG_INTER);
5247 %}
5248
5249 // XMM7 double register operands
5250 operand regXD7(regXD reg) %{
5251 predicate( UseSSE>=2 );
5252 constraint(ALLOC_IN_RC(xdb_reg7));
5253 match(reg);
5254 format %{ "XMM7" %}
5255 interface(REG_INTER);
5256 %}
5257
5258 // Float register operands
5259 operand regF() %{
5260 predicate( UseSSE < 2 );
5261 constraint(ALLOC_IN_RC(flt_reg));
5262 match(RegF);
5263 match(regFPR1);
5264 format %{ %}
5265 interface(REG_INTER);
5266 %}
5267
5268 // Float register operands
5269 operand regFPR1(regF reg) %{
5270 predicate( UseSSE < 2 );
5271 constraint(ALLOC_IN_RC(flt_reg0));
5272 match(reg);
5273 format %{ "FPR1" %}
5274 interface(REG_INTER);
5275 %}
5276
5277 // XMM register operands
5278 operand regX() %{
5279 predicate( UseSSE>=1 );
5280 constraint(ALLOC_IN_RC(xmm_reg));
5281 match(RegF);
5282 format %{ %}
5283 interface(REG_INTER);
5284 %}
5285
5286
5287 //----------Memory Operands----------------------------------------------------
5288 // Direct Memory Operand
5289 operand direct(immP addr) %{
5290 match(addr);
5291
5292 format %{ "[$addr]" %}
5293 interface(MEMORY_INTER) %{
5294 base(0xFFFFFFFF);
5295 index(0x4);
5296 scale(0x0);
5297 disp($addr);
5298 %}
5299 %}
5300
5301 // Indirect Memory Operand
5302 operand indirect(eRegP reg) %{
5303 constraint(ALLOC_IN_RC(e_reg));
5304 match(reg);
5305
5306 format %{ "[$reg]" %}
5307 interface(MEMORY_INTER) %{
5308 base($reg);
5309 index(0x4);
5310 scale(0x0);
5311 disp(0x0);
5312 %}
5313 %}
5314
5315 // Indirect Memory Plus Short Offset Operand
5316 operand indOffset8(eRegP reg, immI8 off) %{
5317 match(AddP reg off);
5318
5319 format %{ "[$reg + $off]" %}
5320 interface(MEMORY_INTER) %{
5321 base($reg);
5322 index(0x4);
5323 scale(0x0);
5324 disp($off);
5325 %}
5326 %}
5327
5328 // Indirect Memory Plus Long Offset Operand
5329 operand indOffset32(eRegP reg, immI off) %{
5330 match(AddP reg off);
5331
5332 format %{ "[$reg + $off]" %}
5333 interface(MEMORY_INTER) %{
5334 base($reg);
5335 index(0x4);
5336 scale(0x0);
5337 disp($off);
5338 %}
5339 %}
5340
5341 // Indirect Memory Plus Long Offset Operand
5342 operand indOffset32X(eRegI reg, immP off) %{
5343 match(AddP off reg);
5344
5345 format %{ "[$reg + $off]" %}
5346 interface(MEMORY_INTER) %{
5347 base($reg);
5348 index(0x4);
5349 scale(0x0);
5350 disp($off);
5351 %}
5352 %}
5353
5354 // Indirect Memory Plus Index Register Plus Offset Operand
5355 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5356 match(AddP (AddP reg ireg) off);
5357
5358 op_cost(10);
5359 format %{"[$reg + $off + $ireg]" %}
5360 interface(MEMORY_INTER) %{
5361 base($reg);
5362 index($ireg);
5363 scale(0x0);
5364 disp($off);
5365 %}
5366 %}
5367
5368 // Indirect Memory Plus Index Register Plus Offset Operand
5369 operand indIndex(eRegP reg, eRegI ireg) %{
5370 match(AddP reg ireg);
5371
5372 op_cost(10);
5373 format %{"[$reg + $ireg]" %}
5374 interface(MEMORY_INTER) %{
5375 base($reg);
5376 index($ireg);
5377 scale(0x0);
5378 disp(0x0);
5379 %}
5380 %}
5381
5382 // // -------------------------------------------------------------------------
5383 // // 486 architecture doesn't support "scale * index + offset" with out a base
5384 // // -------------------------------------------------------------------------
5385 // // Scaled Memory Operands
5386 // // Indirect Memory Times Scale Plus Offset Operand
5387 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5388 // match(AddP off (LShiftI ireg scale));
5389 //
5390 // op_cost(10);
5391 // format %{"[$off + $ireg << $scale]" %}
5392 // interface(MEMORY_INTER) %{
5393 // base(0x4);
5394 // index($ireg);
5395 // scale($scale);
5396 // disp($off);
5397 // %}
5398 // %}
5399
5400 // Indirect Memory Times Scale Plus Index Register
5401 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5402 match(AddP reg (LShiftI ireg scale));
5403
5404 op_cost(10);
5405 format %{"[$reg + $ireg << $scale]" %}
5406 interface(MEMORY_INTER) %{
5407 base($reg);
5408 index($ireg);
5409 scale($scale);
5410 disp(0x0);
5411 %}
5412 %}
5413
5414 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5415 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5416 match(AddP (AddP reg (LShiftI ireg scale)) off);
5417
5418 op_cost(10);
5419 format %{"[$reg + $off + $ireg << $scale]" %}
5420 interface(MEMORY_INTER) %{
5421 base($reg);
5422 index($ireg);
5423 scale($scale);
5424 disp($off);
5425 %}
5426 %}
5427
5428 //----------Load Long Memory Operands------------------------------------------
5429 // The load-long idiom will use it's address expression again after loading
5430 // the first word of the long. If the load-long destination overlaps with
5431 // registers used in the addressing expression, the 2nd half will be loaded
5432 // from a clobbered address. Fix this by requiring that load-long use
5433 // address registers that do not overlap with the load-long target.
5434
5435 // load-long support
5436 operand load_long_RegP() %{
5437 constraint(ALLOC_IN_RC(esi_reg));
5438 match(RegP);
5439 match(eSIRegP);
5440 op_cost(100);
5441 format %{ %}
5442 interface(REG_INTER);
5443 %}
5444
5445 // Indirect Memory Operand Long
5446 operand load_long_indirect(load_long_RegP reg) %{
5447 constraint(ALLOC_IN_RC(esi_reg));
5448 match(reg);
5449
5450 format %{ "[$reg]" %}
5451 interface(MEMORY_INTER) %{
5452 base($reg);
5453 index(0x4);
5454 scale(0x0);
5455 disp(0x0);
5456 %}
5457 %}
5458
5459 // Indirect Memory Plus Long Offset Operand
5460 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5461 match(AddP reg off);
5462
5463 format %{ "[$reg + $off]" %}
5464 interface(MEMORY_INTER) %{
5465 base($reg);
5466 index(0x4);
5467 scale(0x0);
5468 disp($off);
5469 %}
5470 %}
5471
5472 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5473
5474
5475 //----------Special Memory Operands--------------------------------------------
5476 // Stack Slot Operand - This operand is used for loading and storing temporary
5477 // values on the stack where a match requires a value to
5478 // flow through memory.
5479 operand stackSlotP(sRegP reg) %{
5480 constraint(ALLOC_IN_RC(stack_slots));
5481 // No match rule because this operand is only generated in matching
5482 format %{ "[$reg]" %}
5483 interface(MEMORY_INTER) %{
5484 base(0x4); // ESP
5485 index(0x4); // No Index
5486 scale(0x0); // No Scale
5487 disp($reg); // Stack Offset
5488 %}
5489 %}
5490
5491 operand stackSlotI(sRegI reg) %{
5492 constraint(ALLOC_IN_RC(stack_slots));
5493 // No match rule because this operand is only generated in matching
5494 format %{ "[$reg]" %}
5495 interface(MEMORY_INTER) %{
5496 base(0x4); // ESP
5497 index(0x4); // No Index
5498 scale(0x0); // No Scale
5499 disp($reg); // Stack Offset
5500 %}
5501 %}
5502
5503 operand stackSlotF(sRegF reg) %{
5504 constraint(ALLOC_IN_RC(stack_slots));
5505 // No match rule because this operand is only generated in matching
5506 format %{ "[$reg]" %}
5507 interface(MEMORY_INTER) %{
5508 base(0x4); // ESP
5509 index(0x4); // No Index
5510 scale(0x0); // No Scale
5511 disp($reg); // Stack Offset
5512 %}
5513 %}
5514
5515 operand stackSlotD(sRegD reg) %{
5516 constraint(ALLOC_IN_RC(stack_slots));
5517 // No match rule because this operand is only generated in matching
5518 format %{ "[$reg]" %}
5519 interface(MEMORY_INTER) %{
5520 base(0x4); // ESP
5521 index(0x4); // No Index
5522 scale(0x0); // No Scale
5523 disp($reg); // Stack Offset
5524 %}
5525 %}
5526
5527 operand stackSlotL(sRegL reg) %{
5528 constraint(ALLOC_IN_RC(stack_slots));
5529 // No match rule because this operand is only generated in matching
5530 format %{ "[$reg]" %}
5531 interface(MEMORY_INTER) %{
5532 base(0x4); // ESP
5533 index(0x4); // No Index
5534 scale(0x0); // No Scale
5535 disp($reg); // Stack Offset
5536 %}
5537 %}
5538
5539 //----------Memory Operands - Win95 Implicit Null Variants----------------
5540 // Indirect Memory Operand
5541 operand indirect_win95_safe(eRegP_no_EBP reg)
5542 %{
5543 constraint(ALLOC_IN_RC(e_reg));
5544 match(reg);
5545
5546 op_cost(100);
5547 format %{ "[$reg]" %}
5548 interface(MEMORY_INTER) %{
5549 base($reg);
5550 index(0x4);
5551 scale(0x0);
5552 disp(0x0);
5553 %}
5554 %}
5555
5556 // Indirect Memory Plus Short Offset Operand
5557 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5558 %{
5559 match(AddP reg off);
5560
5561 op_cost(100);
5562 format %{ "[$reg + $off]" %}
5563 interface(MEMORY_INTER) %{
5564 base($reg);
5565 index(0x4);
5566 scale(0x0);
5567 disp($off);
5568 %}
5569 %}
5570
5571 // Indirect Memory Plus Long Offset Operand
5572 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5573 %{
5574 match(AddP reg off);
5575
5576 op_cost(100);
5577 format %{ "[$reg + $off]" %}
5578 interface(MEMORY_INTER) %{
5579 base($reg);
5580 index(0x4);
5581 scale(0x0);
5582 disp($off);
5583 %}
5584 %}
5585
5586 // Indirect Memory Plus Index Register Plus Offset Operand
5587 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5588 %{
5589 match(AddP (AddP reg ireg) off);
5590
5591 op_cost(100);
5592 format %{"[$reg + $off + $ireg]" %}
5593 interface(MEMORY_INTER) %{
5594 base($reg);
5595 index($ireg);
5596 scale(0x0);
5597 disp($off);
5598 %}
5599 %}
5600
5601 // Indirect Memory Times Scale Plus Index Register
5602 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5603 %{
5604 match(AddP reg (LShiftI ireg scale));
5605
5606 op_cost(100);
5607 format %{"[$reg + $ireg << $scale]" %}
5608 interface(MEMORY_INTER) %{
5609 base($reg);
5610 index($ireg);
5611 scale($scale);
5612 disp(0x0);
5613 %}
5614 %}
5615
5616 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5617 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5618 %{
5619 match(AddP (AddP reg (LShiftI ireg scale)) off);
5620
5621 op_cost(100);
5622 format %{"[$reg + $off + $ireg << $scale]" %}
5623 interface(MEMORY_INTER) %{
5624 base($reg);
5625 index($ireg);
5626 scale($scale);
5627 disp($off);
5628 %}
5629 %}
5630
5631 //----------Conditional Branch Operands----------------------------------------
5632 // Comparison Op - This is the operation of the comparison, and is limited to
5633 // the following set of codes:
5634 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5635 //
5636 // Other attributes of the comparison, such as unsignedness, are specified
5637 // by the comparison instruction that sets a condition code flags register.
5638 // That result is represented by a flags operand whose subtype is appropriate
5639 // to the unsignedness (etc.) of the comparison.
5640 //
5641 // Later, the instruction which matches both the Comparison Op (a Bool) and
5642 // the flags (produced by the Cmp) specifies the coding of the comparison op
5643 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5644
5645 // Comparision Code
5646 operand cmpOp() %{
5647 match(Bool);
5648
5649 format %{ "" %}
5650 interface(COND_INTER) %{
5651 equal(0x4, "e");
5652 not_equal(0x5, "ne");
5653 less(0xC, "l");
5654 greater_equal(0xD, "ge");
5655 less_equal(0xE, "le");
5656 greater(0xF, "g");
5657 %}
5658 %}
5659
5660 // Comparison Code, unsigned compare. Used by FP also, with
5661 // C2 (unordered) turned into GT or LT already. The other bits
5662 // C0 and C3 are turned into Carry & Zero flags.
5663 operand cmpOpU() %{
5664 match(Bool);
5665
5666 format %{ "" %}
5667 interface(COND_INTER) %{
5668 equal(0x4, "e");
5669 not_equal(0x5, "ne");
5670 less(0x2, "b");
5671 greater_equal(0x3, "nb");
5672 less_equal(0x6, "be");
5673 greater(0x7, "nbe");
5674 %}
5675 %}
5676
5677 // Floating comparisons that don't require any fixup for the unordered case
5678 operand cmpOpUCF() %{
5679 match(Bool);
5680 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5681 n->as_Bool()->_test._test == BoolTest::ge ||
5682 n->as_Bool()->_test._test == BoolTest::le ||
5683 n->as_Bool()->_test._test == BoolTest::gt);
5684 format %{ "" %}
5685 interface(COND_INTER) %{
5686 equal(0x4, "e");
5687 not_equal(0x5, "ne");
5688 less(0x2, "b");
5689 greater_equal(0x3, "nb");
5690 less_equal(0x6, "be");
5691 greater(0x7, "nbe");
5692 %}
5693 %}
5694
5695
5696 // Floating comparisons that can be fixed up with extra conditional jumps
5697 operand cmpOpUCF2() %{
5698 match(Bool);
5699 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5700 n->as_Bool()->_test._test == BoolTest::eq);
5701 format %{ "" %}
5702 interface(COND_INTER) %{
5703 equal(0x4, "e");
5704 not_equal(0x5, "ne");
5705 less(0x2, "b");
5706 greater_equal(0x3, "nb");
5707 less_equal(0x6, "be");
5708 greater(0x7, "nbe");
5709 %}
5710 %}
5711
5712 // Comparison Code for FP conditional move
5713 operand cmpOp_fcmov() %{
5714 match(Bool);
5715
5716 format %{ "" %}
5717 interface(COND_INTER) %{
5718 equal (0x0C8);
5719 not_equal (0x1C8);
5720 less (0x0C0);
5721 greater_equal(0x1C0);
5722 less_equal (0x0D0);
5723 greater (0x1D0);
5724 %}
5725 %}
5726
5727 // Comparision Code used in long compares
5728 operand cmpOp_commute() %{
5729 match(Bool);
5730
5731 format %{ "" %}
5732 interface(COND_INTER) %{
5733 equal(0x4, "e");
5734 not_equal(0x5, "ne");
5735 less(0xF, "g");
5736 greater_equal(0xE, "le");
5737 less_equal(0xD, "ge");
5738 greater(0xC, "l");
5739 %}
5740 %}
5741
5742 //----------OPERAND CLASSES----------------------------------------------------
5743 // Operand Classes are groups of operands that are used as to simplify
5744 // instruction definitions by not requiring the AD writer to specify separate
5745 // instructions for every form of operand when the instruction accepts
5746 // multiple operand types with the same basic encoding and format. The classic
5747 // case of this is memory operands.
5748
5749 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5750 indIndex, indIndexScale, indIndexScaleOffset);
5751
5752 // Long memory operations are encoded in 2 instructions and a +4 offset.
5753 // This means some kind of offset is always required and you cannot use
5754 // an oop as the offset (done when working on static globals).
5755 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5756 indIndex, indIndexScale, indIndexScaleOffset);
5757
5758
5759 //----------PIPELINE-----------------------------------------------------------
5760 // Rules which define the behavior of the target architectures pipeline.
5761 pipeline %{
5762
5763 //----------ATTRIBUTES---------------------------------------------------------
5764 attributes %{
5765 variable_size_instructions; // Fixed size instructions
5766 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5767 instruction_unit_size = 1; // An instruction is 1 bytes long
5768 instruction_fetch_unit_size = 16; // The processor fetches one line
5769 instruction_fetch_units = 1; // of 16 bytes
5770
5771 // List of nop instructions
5772 nops( MachNop );
5773 %}
5774
5775 //----------RESOURCES----------------------------------------------------------
5776 // Resources are the functional units available to the machine
5777
5778 // Generic P2/P3 pipeline
5779 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5780 // 3 instructions decoded per cycle.
5781 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5782 // 2 ALU op, only ALU0 handles mul/div instructions.
5783 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5784 MS0, MS1, MEM = MS0 | MS1,
5785 BR, FPU,
5786 ALU0, ALU1, ALU = ALU0 | ALU1 );
5787
5788 //----------PIPELINE DESCRIPTION-----------------------------------------------
5789 // Pipeline Description specifies the stages in the machine's pipeline
5790
5791 // Generic P2/P3 pipeline
5792 pipe_desc(S0, S1, S2, S3, S4, S5);
5793
5794 //----------PIPELINE CLASSES---------------------------------------------------
5795 // Pipeline Classes describe the stages in which input and output are
5796 // referenced by the hardware pipeline.
5797
5798 // Naming convention: ialu or fpu
5799 // Then: _reg
5800 // Then: _reg if there is a 2nd register
5801 // Then: _long if it's a pair of instructions implementing a long
5802 // Then: _fat if it requires the big decoder
5803 // Or: _mem if it requires the big decoder and a memory unit.
5804
5805 // Integer ALU reg operation
5806 pipe_class ialu_reg(eRegI dst) %{
5807 single_instruction;
5808 dst : S4(write);
5809 dst : S3(read);
5810 DECODE : S0; // any decoder
5811 ALU : S3; // any alu
5812 %}
5813
5814 // Long ALU reg operation
5815 pipe_class ialu_reg_long(eRegL dst) %{
5816 instruction_count(2);
5817 dst : S4(write);
5818 dst : S3(read);
5819 DECODE : S0(2); // any 2 decoders
5820 ALU : S3(2); // both alus
5821 %}
5822
5823 // Integer ALU reg operation using big decoder
5824 pipe_class ialu_reg_fat(eRegI dst) %{
5825 single_instruction;
5826 dst : S4(write);
5827 dst : S3(read);
5828 D0 : S0; // big decoder only
5829 ALU : S3; // any alu
5830 %}
5831
5832 // Long ALU reg operation using big decoder
5833 pipe_class ialu_reg_long_fat(eRegL dst) %{
5834 instruction_count(2);
5835 dst : S4(write);
5836 dst : S3(read);
5837 D0 : S0(2); // big decoder only; twice
5838 ALU : S3(2); // any 2 alus
5839 %}
5840
5841 // Integer ALU reg-reg operation
5842 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5843 single_instruction;
5844 dst : S4(write);
5845 src : S3(read);
5846 DECODE : S0; // any decoder
5847 ALU : S3; // any alu
5848 %}
5849
5850 // Long ALU reg-reg operation
5851 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5852 instruction_count(2);
5853 dst : S4(write);
5854 src : S3(read);
5855 DECODE : S0(2); // any 2 decoders
5856 ALU : S3(2); // both alus
5857 %}
5858
5859 // Integer ALU reg-reg operation
5860 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5861 single_instruction;
5862 dst : S4(write);
5863 src : S3(read);
5864 D0 : S0; // big decoder only
5865 ALU : S3; // any alu
5866 %}
5867
5868 // Long ALU reg-reg operation
5869 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5870 instruction_count(2);
5871 dst : S4(write);
5872 src : S3(read);
5873 D0 : S0(2); // big decoder only; twice
5874 ALU : S3(2); // both alus
5875 %}
5876
5877 // Integer ALU reg-mem operation
5878 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5879 single_instruction;
5880 dst : S5(write);
5881 mem : S3(read);
5882 D0 : S0; // big decoder only
5883 ALU : S4; // any alu
5884 MEM : S3; // any mem
5885 %}
5886
5887 // Long ALU reg-mem operation
5888 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5889 instruction_count(2);
5890 dst : S5(write);
5891 mem : S3(read);
5892 D0 : S0(2); // big decoder only; twice
5893 ALU : S4(2); // any 2 alus
5894 MEM : S3(2); // both mems
5895 %}
5896
5897 // Integer mem operation (prefetch)
5898 pipe_class ialu_mem(memory mem)
5899 %{
5900 single_instruction;
5901 mem : S3(read);
5902 D0 : S0; // big decoder only
5903 MEM : S3; // any mem
5904 %}
5905
5906 // Integer Store to Memory
5907 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5908 single_instruction;
5909 mem : S3(read);
5910 src : S5(read);
5911 D0 : S0; // big decoder only
5912 ALU : S4; // any alu
5913 MEM : S3;
5914 %}
5915
5916 // Long Store to Memory
5917 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5918 instruction_count(2);
5919 mem : S3(read);
5920 src : S5(read);
5921 D0 : S0(2); // big decoder only; twice
5922 ALU : S4(2); // any 2 alus
5923 MEM : S3(2); // Both mems
5924 %}
5925
5926 // Integer Store to Memory
5927 pipe_class ialu_mem_imm(memory mem) %{
5928 single_instruction;
5929 mem : S3(read);
5930 D0 : S0; // big decoder only
5931 ALU : S4; // any alu
5932 MEM : S3;
5933 %}
5934
5935 // Integer ALU0 reg-reg operation
5936 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5937 single_instruction;
5938 dst : S4(write);
5939 src : S3(read);
5940 D0 : S0; // Big decoder only
5941 ALU0 : S3; // only alu0
5942 %}
5943
5944 // Integer ALU0 reg-mem operation
5945 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5946 single_instruction;
5947 dst : S5(write);
5948 mem : S3(read);
5949 D0 : S0; // big decoder only
5950 ALU0 : S4; // ALU0 only
5951 MEM : S3; // any mem
5952 %}
5953
5954 // Integer ALU reg-reg operation
5955 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5956 single_instruction;
5957 cr : S4(write);
5958 src1 : S3(read);
5959 src2 : S3(read);
5960 DECODE : S0; // any decoder
5961 ALU : S3; // any alu
5962 %}
5963
5964 // Integer ALU reg-imm operation
5965 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5966 single_instruction;
5967 cr : S4(write);
5968 src1 : S3(read);
5969 DECODE : S0; // any decoder
5970 ALU : S3; // any alu
5971 %}
5972
5973 // Integer ALU reg-mem operation
5974 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5975 single_instruction;
5976 cr : S4(write);
5977 src1 : S3(read);
5978 src2 : S3(read);
5979 D0 : S0; // big decoder only
5980 ALU : S4; // any alu
5981 MEM : S3;
5982 %}
5983
5984 // Conditional move reg-reg
5985 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5986 instruction_count(4);
5987 y : S4(read);
5988 q : S3(read);
5989 p : S3(read);
5990 DECODE : S0(4); // any decoder
5991 %}
5992
5993 // Conditional move reg-reg
5994 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5995 single_instruction;
5996 dst : S4(write);
5997 src : S3(read);
5998 cr : S3(read);
5999 DECODE : S0; // any decoder
6000 %}
6001
6002 // Conditional move reg-mem
6003 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6004 single_instruction;
6005 dst : S4(write);
6006 src : S3(read);
6007 cr : S3(read);
6008 DECODE : S0; // any decoder
6009 MEM : S3;
6010 %}
6011
6012 // Conditional move reg-reg long
6013 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6014 single_instruction;
6015 dst : S4(write);
6016 src : S3(read);
6017 cr : S3(read);
6018 DECODE : S0(2); // any 2 decoders
6019 %}
6020
6021 // Conditional move double reg-reg
6022 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6023 single_instruction;
6024 dst : S4(write);
6025 src : S3(read);
6026 cr : S3(read);
6027 DECODE : S0; // any decoder
6028 %}
6029
6030 // Float reg-reg operation
6031 pipe_class fpu_reg(regD dst) %{
6032 instruction_count(2);
6033 dst : S3(read);
6034 DECODE : S0(2); // any 2 decoders
6035 FPU : S3;
6036 %}
6037
6038 // Float reg-reg operation
6039 pipe_class fpu_reg_reg(regD dst, regD src) %{
6040 instruction_count(2);
6041 dst : S4(write);
6042 src : S3(read);
6043 DECODE : S0(2); // any 2 decoders
6044 FPU : S3;
6045 %}
6046
6047 // Float reg-reg operation
6048 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6049 instruction_count(3);
6050 dst : S4(write);
6051 src1 : S3(read);
6052 src2 : S3(read);
6053 DECODE : S0(3); // any 3 decoders
6054 FPU : S3(2);
6055 %}
6056
6057 // Float reg-reg operation
6058 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6059 instruction_count(4);
6060 dst : S4(write);
6061 src1 : S3(read);
6062 src2 : S3(read);
6063 src3 : S3(read);
6064 DECODE : S0(4); // any 3 decoders
6065 FPU : S3(2);
6066 %}
6067
6068 // Float reg-reg operation
6069 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6070 instruction_count(4);
6071 dst : S4(write);
6072 src1 : S3(read);
6073 src2 : S3(read);
6074 src3 : S3(read);
6075 DECODE : S1(3); // any 3 decoders
6076 D0 : S0; // Big decoder only
6077 FPU : S3(2);
6078 MEM : S3;
6079 %}
6080
6081 // Float reg-mem operation
6082 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6083 instruction_count(2);
6084 dst : S5(write);
6085 mem : S3(read);
6086 D0 : S0; // big decoder only
6087 DECODE : S1; // any decoder for FPU POP
6088 FPU : S4;
6089 MEM : S3; // any mem
6090 %}
6091
6092 // Float reg-mem operation
6093 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6094 instruction_count(3);
6095 dst : S5(write);
6096 src1 : S3(read);
6097 mem : S3(read);
6098 D0 : S0; // big decoder only
6099 DECODE : S1(2); // any decoder for FPU POP
6100 FPU : S4;
6101 MEM : S3; // any mem
6102 %}
6103
6104 // Float mem-reg operation
6105 pipe_class fpu_mem_reg(memory mem, regD src) %{
6106 instruction_count(2);
6107 src : S5(read);
6108 mem : S3(read);
6109 DECODE : S0; // any decoder for FPU PUSH
6110 D0 : S1; // big decoder only
6111 FPU : S4;
6112 MEM : S3; // any mem
6113 %}
6114
6115 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6116 instruction_count(3);
6117 src1 : S3(read);
6118 src2 : S3(read);
6119 mem : S3(read);
6120 DECODE : S0(2); // any decoder for FPU PUSH
6121 D0 : S1; // big decoder only
6122 FPU : S4;
6123 MEM : S3; // any mem
6124 %}
6125
6126 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6127 instruction_count(3);
6128 src1 : S3(read);
6129 src2 : S3(read);
6130 mem : S4(read);
6131 DECODE : S0; // any decoder for FPU PUSH
6132 D0 : S0(2); // big decoder only
6133 FPU : S4;
6134 MEM : S3(2); // any mem
6135 %}
6136
6137 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6138 instruction_count(2);
6139 src1 : S3(read);
6140 dst : S4(read);
6141 D0 : S0(2); // big decoder only
6142 MEM : S3(2); // any mem
6143 %}
6144
6145 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6146 instruction_count(3);
6147 src1 : S3(read);
6148 src2 : S3(read);
6149 dst : S4(read);
6150 D0 : S0(3); // big decoder only
6151 FPU : S4;
6152 MEM : S3(3); // any mem
6153 %}
6154
6155 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6156 instruction_count(3);
6157 src1 : S4(read);
6158 mem : S4(read);
6159 DECODE : S0; // any decoder for FPU PUSH
6160 D0 : S0(2); // big decoder only
6161 FPU : S4;
6162 MEM : S3(2); // any mem
6163 %}
6164
6165 // Float load constant
6166 pipe_class fpu_reg_con(regD dst) %{
6167 instruction_count(2);
6168 dst : S5(write);
6169 D0 : S0; // big decoder only for the load
6170 DECODE : S1; // any decoder for FPU POP
6171 FPU : S4;
6172 MEM : S3; // any mem
6173 %}
6174
6175 // Float load constant
6176 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6177 instruction_count(3);
6178 dst : S5(write);
6179 src : S3(read);
6180 D0 : S0; // big decoder only for the load
6181 DECODE : S1(2); // any decoder for FPU POP
6182 FPU : S4;
6183 MEM : S3; // any mem
6184 %}
6185
6186 // UnConditional branch
6187 pipe_class pipe_jmp( label labl ) %{
6188 single_instruction;
6189 BR : S3;
6190 %}
6191
6192 // Conditional branch
6193 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6194 single_instruction;
6195 cr : S1(read);
6196 BR : S3;
6197 %}
6198
6199 // Allocation idiom
6200 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6201 instruction_count(1); force_serialization;
6202 fixed_latency(6);
6203 heap_ptr : S3(read);
6204 DECODE : S0(3);
6205 D0 : S2;
6206 MEM : S3;
6207 ALU : S3(2);
6208 dst : S5(write);
6209 BR : S5;
6210 %}
6211
6212 // Generic big/slow expanded idiom
6213 pipe_class pipe_slow( ) %{
6214 instruction_count(10); multiple_bundles; force_serialization;
6215 fixed_latency(100);
6216 D0 : S0(2);
6217 MEM : S3(2);
6218 %}
6219
6220 // The real do-nothing guy
6221 pipe_class empty( ) %{
6222 instruction_count(0);
6223 %}
6224
6225 // Define the class for the Nop node
6226 define %{
6227 MachNop = empty;
6228 %}
6229
6230 %}
6231
6232 //----------INSTRUCTIONS-------------------------------------------------------
6233 //
6234 // match -- States which machine-independent subtree may be replaced
6235 // by this instruction.
6236 // ins_cost -- The estimated cost of this instruction is used by instruction
6237 // selection to identify a minimum cost tree of machine
6238 // instructions that matches a tree of machine-independent
6239 // instructions.
6240 // format -- A string providing the disassembly for this instruction.
6241 // The value of an instruction's operand may be inserted
6242 // by referring to it with a '$' prefix.
6243 // opcode -- Three instruction opcodes may be provided. These are referred
6244 // to within an encode class as $primary, $secondary, and $tertiary
6245 // respectively. The primary opcode is commonly used to
6246 // indicate the type of machine instruction, while secondary
6247 // and tertiary are often used for prefix options or addressing
6248 // modes.
6249 // ins_encode -- A list of encode classes with parameters. The encode class
6250 // name must have been defined in an 'enc_class' specification
6251 // in the encode section of the architecture description.
6252
6253 //----------BSWAP-Instruction--------------------------------------------------
6254 instruct bytes_reverse_int(eRegI dst) %{
6255 match(Set dst (ReverseBytesI dst));
6256
6257 format %{ "BSWAP $dst" %}
6258 opcode(0x0F, 0xC8);
6259 ins_encode( OpcP, OpcSReg(dst) );
6260 ins_pipe( ialu_reg );
6261 %}
6262
6263 instruct bytes_reverse_long(eRegL dst) %{
6264 match(Set dst (ReverseBytesL dst));
6265
6266 format %{ "BSWAP $dst.lo\n\t"
6267 "BSWAP $dst.hi\n\t"
6268 "XCHG $dst.lo $dst.hi" %}
6269
6270 ins_cost(125);
6271 ins_encode( bswap_long_bytes(dst) );
6272 ins_pipe( ialu_reg_reg);
6273 %}
6274
6275
6276 //---------- Zeros Count Instructions ------------------------------------------
6277
6278 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6279 predicate(UseCountLeadingZerosInstruction);
6280 match(Set dst (CountLeadingZerosI src));
6281 effect(KILL cr);
6282
6283 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6284 ins_encode %{
6285 __ lzcntl($dst$$Register, $src$$Register);
6286 %}
6287 ins_pipe(ialu_reg);
6288 %}
6289
6290 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6291 predicate(!UseCountLeadingZerosInstruction);
6292 match(Set dst (CountLeadingZerosI src));
6293 effect(KILL cr);
6294
6295 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6296 "JNZ skip\n\t"
6297 "MOV $dst, -1\n"
6298 "skip:\n\t"
6299 "NEG $dst\n\t"
6300 "ADD $dst, 31" %}
6301 ins_encode %{
6302 Register Rdst = $dst$$Register;
6303 Register Rsrc = $src$$Register;
6304 Label skip;
6305 __ bsrl(Rdst, Rsrc);
6306 __ jccb(Assembler::notZero, skip);
6307 __ movl(Rdst, -1);
6308 __ bind(skip);
6309 __ negl(Rdst);
6310 __ addl(Rdst, BitsPerInt - 1);
6311 %}
6312 ins_pipe(ialu_reg);
6313 %}
6314
6315 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6316 predicate(UseCountLeadingZerosInstruction);
6317 match(Set dst (CountLeadingZerosL src));
6318 effect(TEMP dst, KILL cr);
6319
6320 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6321 "JNC done\n\t"
6322 "LZCNT $dst, $src.lo\n\t"
6323 "ADD $dst, 32\n"
6324 "done:" %}
6325 ins_encode %{
6326 Register Rdst = $dst$$Register;
6327 Register Rsrc = $src$$Register;
6328 Label done;
6329 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6330 __ jccb(Assembler::carryClear, done);
6331 __ lzcntl(Rdst, Rsrc);
6332 __ addl(Rdst, BitsPerInt);
6333 __ bind(done);
6334 %}
6335 ins_pipe(ialu_reg);
6336 %}
6337
6338 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6339 predicate(!UseCountLeadingZerosInstruction);
6340 match(Set dst (CountLeadingZerosL src));
6341 effect(TEMP dst, KILL cr);
6342
6343 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6344 "JZ msw_is_zero\n\t"
6345 "ADD $dst, 32\n\t"
6346 "JMP not_zero\n"
6347 "msw_is_zero:\n\t"
6348 "BSR $dst, $src.lo\n\t"
6349 "JNZ not_zero\n\t"
6350 "MOV $dst, -1\n"
6351 "not_zero:\n\t"
6352 "NEG $dst\n\t"
6353 "ADD $dst, 63\n" %}
6354 ins_encode %{
6355 Register Rdst = $dst$$Register;
6356 Register Rsrc = $src$$Register;
6357 Label msw_is_zero;
6358 Label not_zero;
6359 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6360 __ jccb(Assembler::zero, msw_is_zero);
6361 __ addl(Rdst, BitsPerInt);
6362 __ jmpb(not_zero);
6363 __ bind(msw_is_zero);
6364 __ bsrl(Rdst, Rsrc);
6365 __ jccb(Assembler::notZero, not_zero);
6366 __ movl(Rdst, -1);
6367 __ bind(not_zero);
6368 __ negl(Rdst);
6369 __ addl(Rdst, BitsPerLong - 1);
6370 %}
6371 ins_pipe(ialu_reg);
6372 %}
6373
6374 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6375 match(Set dst (CountTrailingZerosI src));
6376 effect(KILL cr);
6377
6378 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6379 "JNZ done\n\t"
6380 "MOV $dst, 32\n"
6381 "done:" %}
6382 ins_encode %{
6383 Register Rdst = $dst$$Register;
6384 Label done;
6385 __ bsfl(Rdst, $src$$Register);
6386 __ jccb(Assembler::notZero, done);
6387 __ movl(Rdst, BitsPerInt);
6388 __ bind(done);
6389 %}
6390 ins_pipe(ialu_reg);
6391 %}
6392
6393 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6394 match(Set dst (CountTrailingZerosL src));
6395 effect(TEMP dst, KILL cr);
6396
6397 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6398 "JNZ done\n\t"
6399 "BSF $dst, $src.hi\n\t"
6400 "JNZ msw_not_zero\n\t"
6401 "MOV $dst, 32\n"
6402 "msw_not_zero:\n\t"
6403 "ADD $dst, 32\n"
6404 "done:" %}
6405 ins_encode %{
6406 Register Rdst = $dst$$Register;
6407 Register Rsrc = $src$$Register;
6408 Label msw_not_zero;
6409 Label done;
6410 __ bsfl(Rdst, Rsrc);
6411 __ jccb(Assembler::notZero, done);
6412 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6413 __ jccb(Assembler::notZero, msw_not_zero);
6414 __ movl(Rdst, BitsPerInt);
6415 __ bind(msw_not_zero);
6416 __ addl(Rdst, BitsPerInt);
6417 __ bind(done);
6418 %}
6419 ins_pipe(ialu_reg);
6420 %}
6421
6422
6423 //---------- Population Count Instructions -------------------------------------
6424
6425 instruct popCountI(eRegI dst, eRegI src) %{
6426 predicate(UsePopCountInstruction);
6427 match(Set dst (PopCountI src));
6428
6429 format %{ "POPCNT $dst, $src" %}
6430 ins_encode %{
6431 __ popcntl($dst$$Register, $src$$Register);
6432 %}
6433 ins_pipe(ialu_reg);
6434 %}
6435
6436 instruct popCountI_mem(eRegI dst, memory mem) %{
6437 predicate(UsePopCountInstruction);
6438 match(Set dst (PopCountI (LoadI mem)));
6439
6440 format %{ "POPCNT $dst, $mem" %}
6441 ins_encode %{
6442 __ popcntl($dst$$Register, $mem$$Address);
6443 %}
6444 ins_pipe(ialu_reg);
6445 %}
6446
6447 // Note: Long.bitCount(long) returns an int.
6448 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6449 predicate(UsePopCountInstruction);
6450 match(Set dst (PopCountL src));
6451 effect(KILL cr, TEMP tmp, TEMP dst);
6452
6453 format %{ "POPCNT $dst, $src.lo\n\t"
6454 "POPCNT $tmp, $src.hi\n\t"
6455 "ADD $dst, $tmp" %}
6456 ins_encode %{
6457 __ popcntl($dst$$Register, $src$$Register);
6458 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6459 __ addl($dst$$Register, $tmp$$Register);
6460 %}
6461 ins_pipe(ialu_reg);
6462 %}
6463
6464 // Note: Long.bitCount(long) returns an int.
6465 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6466 predicate(UsePopCountInstruction);
6467 match(Set dst (PopCountL (LoadL mem)));
6468 effect(KILL cr, TEMP tmp, TEMP dst);
6469
6470 format %{ "POPCNT $dst, $mem\n\t"
6471 "POPCNT $tmp, $mem+4\n\t"
6472 "ADD $dst, $tmp" %}
6473 ins_encode %{
6474 //__ popcntl($dst$$Register, $mem$$Address$$first);
6475 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6476 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6477 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6478 __ addl($dst$$Register, $tmp$$Register);
6479 %}
6480 ins_pipe(ialu_reg);
6481 %}
6482
6483
6484 //----------Load/Store/Move Instructions---------------------------------------
6485 //----------Load Instructions--------------------------------------------------
6486 // Load Byte (8bit signed)
6487 instruct loadB(xRegI dst, memory mem) %{
6488 match(Set dst (LoadB mem));
6489
6490 ins_cost(125);
6491 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6492
6493 ins_encode %{
6494 __ movsbl($dst$$Register, $mem$$Address);
6495 %}
6496
6497 ins_pipe(ialu_reg_mem);
6498 %}
6499
6500 // Load Byte (8bit signed) into Long Register
6501 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6502 match(Set dst (ConvI2L (LoadB mem)));
6503 effect(KILL cr);
6504
6505 ins_cost(375);
6506 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6507 "MOV $dst.hi,$dst.lo\n\t"
6508 "SAR $dst.hi,7" %}
6509
6510 ins_encode %{
6511 __ movsbl($dst$$Register, $mem$$Address);
6512 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6513 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6514 %}
6515
6516 ins_pipe(ialu_reg_mem);
6517 %}
6518
6519 // Load Unsigned Byte (8bit UNsigned)
6520 instruct loadUB(xRegI dst, memory mem) %{
6521 match(Set dst (LoadUB mem));
6522
6523 ins_cost(125);
6524 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6525
6526 ins_encode %{
6527 __ movzbl($dst$$Register, $mem$$Address);
6528 %}
6529
6530 ins_pipe(ialu_reg_mem);
6531 %}
6532
6533 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6534 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6535 match(Set dst (ConvI2L (LoadUB mem)));
6536 effect(KILL cr);
6537
6538 ins_cost(250);
6539 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6540 "XOR $dst.hi,$dst.hi" %}
6541
6542 ins_encode %{
6543 Register Rdst = $dst$$Register;
6544 __ movzbl(Rdst, $mem$$Address);
6545 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6546 %}
6547
6548 ins_pipe(ialu_reg_mem);
6549 %}
6550
6551 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6552 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6553 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6554 effect(KILL cr);
6555
6556 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6557 "XOR $dst.hi,$dst.hi\n\t"
6558 "AND $dst.lo,$mask" %}
6559 ins_encode %{
6560 Register Rdst = $dst$$Register;
6561 __ movzbl(Rdst, $mem$$Address);
6562 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6563 __ andl(Rdst, $mask$$constant);
6564 %}
6565 ins_pipe(ialu_reg_mem);
6566 %}
6567
6568 // Load Short (16bit signed)
6569 instruct loadS(eRegI dst, memory mem) %{
6570 match(Set dst (LoadS mem));
6571
6572 ins_cost(125);
6573 format %{ "MOVSX $dst,$mem\t# short" %}
6574
6575 ins_encode %{
6576 __ movswl($dst$$Register, $mem$$Address);
6577 %}
6578
6579 ins_pipe(ialu_reg_mem);
6580 %}
6581
6582 // Load Short (16 bit signed) to Byte (8 bit signed)
6583 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6584 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6585
6586 ins_cost(125);
6587 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6588 ins_encode %{
6589 __ movsbl($dst$$Register, $mem$$Address);
6590 %}
6591 ins_pipe(ialu_reg_mem);
6592 %}
6593
6594 // Load Short (16bit signed) into Long Register
6595 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6596 match(Set dst (ConvI2L (LoadS mem)));
6597 effect(KILL cr);
6598
6599 ins_cost(375);
6600 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6601 "MOV $dst.hi,$dst.lo\n\t"
6602 "SAR $dst.hi,15" %}
6603
6604 ins_encode %{
6605 __ movswl($dst$$Register, $mem$$Address);
6606 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6607 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6608 %}
6609
6610 ins_pipe(ialu_reg_mem);
6611 %}
6612
6613 // Load Unsigned Short/Char (16bit unsigned)
6614 instruct loadUS(eRegI dst, memory mem) %{
6615 match(Set dst (LoadUS mem));
6616
6617 ins_cost(125);
6618 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6619
6620 ins_encode %{
6621 __ movzwl($dst$$Register, $mem$$Address);
6622 %}
6623
6624 ins_pipe(ialu_reg_mem);
6625 %}
6626
6627 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6628 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6629 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6630
6631 ins_cost(125);
6632 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6633 ins_encode %{
6634 __ movsbl($dst$$Register, $mem$$Address);
6635 %}
6636 ins_pipe(ialu_reg_mem);
6637 %}
6638
6639 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6640 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6641 match(Set dst (ConvI2L (LoadUS mem)));
6642 effect(KILL cr);
6643
6644 ins_cost(250);
6645 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6646 "XOR $dst.hi,$dst.hi" %}
6647
6648 ins_encode %{
6649 __ movzwl($dst$$Register, $mem$$Address);
6650 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6651 %}
6652
6653 ins_pipe(ialu_reg_mem);
6654 %}
6655
6656 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6657 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6658 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6659 effect(KILL cr);
6660
6661 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6662 "XOR $dst.hi,$dst.hi" %}
6663 ins_encode %{
6664 Register Rdst = $dst$$Register;
6665 __ movzbl(Rdst, $mem$$Address);
6666 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6667 %}
6668 ins_pipe(ialu_reg_mem);
6669 %}
6670
6671 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6672 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6673 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6674 effect(KILL cr);
6675
6676 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6677 "XOR $dst.hi,$dst.hi\n\t"
6678 "AND $dst.lo,$mask" %}
6679 ins_encode %{
6680 Register Rdst = $dst$$Register;
6681 __ movzwl(Rdst, $mem$$Address);
6682 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6683 __ andl(Rdst, $mask$$constant);
6684 %}
6685 ins_pipe(ialu_reg_mem);
6686 %}
6687
6688 // Load Integer
6689 instruct loadI(eRegI dst, memory mem) %{
6690 match(Set dst (LoadI mem));
6691
6692 ins_cost(125);
6693 format %{ "MOV $dst,$mem\t# int" %}
6694
6695 ins_encode %{
6696 __ movl($dst$$Register, $mem$$Address);
6697 %}
6698
6699 ins_pipe(ialu_reg_mem);
6700 %}
6701
6702 // Load Integer (32 bit signed) to Byte (8 bit signed)
6703 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6704 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6705
6706 ins_cost(125);
6707 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6708 ins_encode %{
6709 __ movsbl($dst$$Register, $mem$$Address);
6710 %}
6711 ins_pipe(ialu_reg_mem);
6712 %}
6713
6714 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6715 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6716 match(Set dst (AndI (LoadI mem) mask));
6717
6718 ins_cost(125);
6719 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6720 ins_encode %{
6721 __ movzbl($dst$$Register, $mem$$Address);
6722 %}
6723 ins_pipe(ialu_reg_mem);
6724 %}
6725
6726 // Load Integer (32 bit signed) to Short (16 bit signed)
6727 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6728 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6729
6730 ins_cost(125);
6731 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6732 ins_encode %{
6733 __ movswl($dst$$Register, $mem$$Address);
6734 %}
6735 ins_pipe(ialu_reg_mem);
6736 %}
6737
6738 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6739 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6740 match(Set dst (AndI (LoadI mem) mask));
6741
6742 ins_cost(125);
6743 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6744 ins_encode %{
6745 __ movzwl($dst$$Register, $mem$$Address);
6746 %}
6747 ins_pipe(ialu_reg_mem);
6748 %}
6749
6750 // Load Integer into Long Register
6751 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6752 match(Set dst (ConvI2L (LoadI mem)));
6753 effect(KILL cr);
6754
6755 ins_cost(375);
6756 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6757 "MOV $dst.hi,$dst.lo\n\t"
6758 "SAR $dst.hi,31" %}
6759
6760 ins_encode %{
6761 __ movl($dst$$Register, $mem$$Address);
6762 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6763 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6764 %}
6765
6766 ins_pipe(ialu_reg_mem);
6767 %}
6768
6769 // Load Integer with mask 0xFF into Long Register
6770 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6771 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6772 effect(KILL cr);
6773
6774 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6775 "XOR $dst.hi,$dst.hi" %}
6776 ins_encode %{
6777 Register Rdst = $dst$$Register;
6778 __ movzbl(Rdst, $mem$$Address);
6779 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6780 %}
6781 ins_pipe(ialu_reg_mem);
6782 %}
6783
6784 // Load Integer with mask 0xFFFF into Long Register
6785 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6786 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6787 effect(KILL cr);
6788
6789 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6790 "XOR $dst.hi,$dst.hi" %}
6791 ins_encode %{
6792 Register Rdst = $dst$$Register;
6793 __ movzwl(Rdst, $mem$$Address);
6794 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6795 %}
6796 ins_pipe(ialu_reg_mem);
6797 %}
6798
6799 // Load Integer with 32-bit mask into Long Register
6800 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6801 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6802 effect(KILL cr);
6803
6804 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6805 "XOR $dst.hi,$dst.hi\n\t"
6806 "AND $dst.lo,$mask" %}
6807 ins_encode %{
6808 Register Rdst = $dst$$Register;
6809 __ movl(Rdst, $mem$$Address);
6810 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6811 __ andl(Rdst, $mask$$constant);
6812 %}
6813 ins_pipe(ialu_reg_mem);
6814 %}
6815
6816 // Load Unsigned Integer into Long Register
6817 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6818 match(Set dst (LoadUI2L mem));
6819 effect(KILL cr);
6820
6821 ins_cost(250);
6822 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6823 "XOR $dst.hi,$dst.hi" %}
6824
6825 ins_encode %{
6826 __ movl($dst$$Register, $mem$$Address);
6827 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6828 %}
6829
6830 ins_pipe(ialu_reg_mem);
6831 %}
6832
6833 // Load Long. Cannot clobber address while loading, so restrict address
6834 // register to ESI
6835 instruct loadL(eRegL dst, load_long_memory mem) %{
6836 predicate(!((LoadLNode*)n)->require_atomic_access());
6837 match(Set dst (LoadL mem));
6838
6839 ins_cost(250);
6840 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6841 "MOV $dst.hi,$mem+4" %}
6842
6843 ins_encode %{
6844 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6845 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6846 __ movl($dst$$Register, Amemlo);
6847 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6848 %}
6849
6850 ins_pipe(ialu_reg_long_mem);
6851 %}
6852
6853 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6854 // then store it down to the stack and reload on the int
6855 // side.
6856 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6857 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6858 match(Set dst (LoadL mem));
6859
6860 ins_cost(200);
6861 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6862 "FISTp $dst" %}
6863 ins_encode(enc_loadL_volatile(mem,dst));
6864 ins_pipe( fpu_reg_mem );
6865 %}
6866
6867 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6868 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6869 match(Set dst (LoadL mem));
6870 effect(TEMP tmp);
6871 ins_cost(180);
6872 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6873 "MOVSD $dst,$tmp" %}
6874 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6875 ins_pipe( pipe_slow );
6876 %}
6877
6878 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6879 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6880 match(Set dst (LoadL mem));
6881 effect(TEMP tmp);
6882 ins_cost(160);
6883 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6884 "MOVD $dst.lo,$tmp\n\t"
6885 "PSRLQ $tmp,32\n\t"
6886 "MOVD $dst.hi,$tmp" %}
6887 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6888 ins_pipe( pipe_slow );
6889 %}
6890
6891 // Load Range
6892 instruct loadRange(eRegI dst, memory mem) %{
6893 match(Set dst (LoadRange mem));
6894
6895 ins_cost(125);
6896 format %{ "MOV $dst,$mem" %}
6897 opcode(0x8B);
6898 ins_encode( OpcP, RegMem(dst,mem));
6899 ins_pipe( ialu_reg_mem );
6900 %}
6901
6902
6903 // Load Pointer
6904 instruct loadP(eRegP dst, memory mem) %{
6905 match(Set dst (LoadP mem));
6906
6907 ins_cost(125);
6908 format %{ "MOV $dst,$mem" %}
6909 opcode(0x8B);
6910 ins_encode( OpcP, RegMem(dst,mem));
6911 ins_pipe( ialu_reg_mem );
6912 %}
6913
6914 // Load Klass Pointer
6915 instruct loadKlass(eRegP dst, memory mem) %{
6916 match(Set dst (LoadKlass mem));
6917
6918 ins_cost(125);
6919 format %{ "MOV $dst,$mem" %}
6920 opcode(0x8B);
6921 ins_encode( OpcP, RegMem(dst,mem));
6922 ins_pipe( ialu_reg_mem );
6923 %}
6924
6925 // Load Double
6926 instruct loadD(regD dst, memory mem) %{
6927 predicate(UseSSE<=1);
6928 match(Set dst (LoadD mem));
6929
6930 ins_cost(150);
6931 format %{ "FLD_D ST,$mem\n\t"
6932 "FSTP $dst" %}
6933 opcode(0xDD); /* DD /0 */
6934 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6935 Pop_Reg_D(dst) );
6936 ins_pipe( fpu_reg_mem );
6937 %}
6938
6939 // Load Double to XMM
6940 instruct loadXD(regXD dst, memory mem) %{
6941 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6942 match(Set dst (LoadD mem));
6943 ins_cost(145);
6944 format %{ "MOVSD $dst,$mem" %}
6945 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6946 ins_pipe( pipe_slow );
6947 %}
6948
6949 instruct loadXD_partial(regXD dst, memory mem) %{
6950 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6951 match(Set dst (LoadD mem));
6952 ins_cost(145);
6953 format %{ "MOVLPD $dst,$mem" %}
6954 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6955 ins_pipe( pipe_slow );
6956 %}
6957
6958 // Load to XMM register (single-precision floating point)
6959 // MOVSS instruction
6960 instruct loadX(regX dst, memory mem) %{
6961 predicate(UseSSE>=1);
6962 match(Set dst (LoadF mem));
6963 ins_cost(145);
6964 format %{ "MOVSS $dst,$mem" %}
6965 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6966 ins_pipe( pipe_slow );
6967 %}
6968
6969 // Load Float
6970 instruct loadF(regF dst, memory mem) %{
6971 predicate(UseSSE==0);
6972 match(Set dst (LoadF mem));
6973
6974 ins_cost(150);
6975 format %{ "FLD_S ST,$mem\n\t"
6976 "FSTP $dst" %}
6977 opcode(0xD9); /* D9 /0 */
6978 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6979 Pop_Reg_F(dst) );
6980 ins_pipe( fpu_reg_mem );
6981 %}
6982
6983 // Load Aligned Packed Byte to XMM register
6984 instruct loadA8B(regXD dst, memory mem) %{
6985 predicate(UseSSE>=1);
6986 match(Set dst (Load8B mem));
6987 ins_cost(125);
6988 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6989 ins_encode( movq_ld(dst, mem));
6990 ins_pipe( pipe_slow );
6991 %}
6992
6993 // Load Aligned Packed Short to XMM register
6994 instruct loadA4S(regXD dst, memory mem) %{
6995 predicate(UseSSE>=1);
6996 match(Set dst (Load4S mem));
6997 ins_cost(125);
6998 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6999 ins_encode( movq_ld(dst, mem));
7000 ins_pipe( pipe_slow );
7001 %}
7002
7003 // Load Aligned Packed Char to XMM register
7004 instruct loadA4C(regXD dst, memory mem) %{
7005 predicate(UseSSE>=1);
7006 match(Set dst (Load4C mem));
7007 ins_cost(125);
7008 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7009 ins_encode( movq_ld(dst, mem));
7010 ins_pipe( pipe_slow );
7011 %}
7012
7013 // Load Aligned Packed Integer to XMM register
7014 instruct load2IU(regXD dst, memory mem) %{
7015 predicate(UseSSE>=1);
7016 match(Set dst (Load2I mem));
7017 ins_cost(125);
7018 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7019 ins_encode( movq_ld(dst, mem));
7020 ins_pipe( pipe_slow );
7021 %}
7022
7023 // Load Aligned Packed Single to XMM
7024 instruct loadA2F(regXD dst, memory mem) %{
7025 predicate(UseSSE>=1);
7026 match(Set dst (Load2F mem));
7027 ins_cost(145);
7028 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7029 ins_encode( movq_ld(dst, mem));
7030 ins_pipe( pipe_slow );
7031 %}
7032
7033 // Load Effective Address
7034 instruct leaP8(eRegP dst, indOffset8 mem) %{
7035 match(Set dst mem);
7036
7037 ins_cost(110);
7038 format %{ "LEA $dst,$mem" %}
7039 opcode(0x8D);
7040 ins_encode( OpcP, RegMem(dst,mem));
7041 ins_pipe( ialu_reg_reg_fat );
7042 %}
7043
7044 instruct leaP32(eRegP dst, indOffset32 mem) %{
7045 match(Set dst mem);
7046
7047 ins_cost(110);
7048 format %{ "LEA $dst,$mem" %}
7049 opcode(0x8D);
7050 ins_encode( OpcP, RegMem(dst,mem));
7051 ins_pipe( ialu_reg_reg_fat );
7052 %}
7053
7054 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7055 match(Set dst mem);
7056
7057 ins_cost(110);
7058 format %{ "LEA $dst,$mem" %}
7059 opcode(0x8D);
7060 ins_encode( OpcP, RegMem(dst,mem));
7061 ins_pipe( ialu_reg_reg_fat );
7062 %}
7063
7064 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7065 match(Set dst mem);
7066
7067 ins_cost(110);
7068 format %{ "LEA $dst,$mem" %}
7069 opcode(0x8D);
7070 ins_encode( OpcP, RegMem(dst,mem));
7071 ins_pipe( ialu_reg_reg_fat );
7072 %}
7073
7074 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7075 match(Set dst mem);
7076
7077 ins_cost(110);
7078 format %{ "LEA $dst,$mem" %}
7079 opcode(0x8D);
7080 ins_encode( OpcP, RegMem(dst,mem));
7081 ins_pipe( ialu_reg_reg_fat );
7082 %}
7083
7084 // Load Constant
7085 instruct loadConI(eRegI dst, immI src) %{
7086 match(Set dst src);
7087
7088 format %{ "MOV $dst,$src" %}
7089 ins_encode( LdImmI(dst, src) );
7090 ins_pipe( ialu_reg_fat );
7091 %}
7092
7093 // Load Constant zero
7094 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7095 match(Set dst src);
7096 effect(KILL cr);
7097
7098 ins_cost(50);
7099 format %{ "XOR $dst,$dst" %}
7100 opcode(0x33); /* + rd */
7101 ins_encode( OpcP, RegReg( dst, dst ) );
7102 ins_pipe( ialu_reg );
7103 %}
7104
7105 instruct loadConP(eRegP dst, immP src) %{
7106 match(Set dst src);
7107
7108 format %{ "MOV $dst,$src" %}
7109 opcode(0xB8); /* + rd */
7110 ins_encode( LdImmP(dst, src) );
7111 ins_pipe( ialu_reg_fat );
7112 %}
7113
7114 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7115 match(Set dst src);
7116 effect(KILL cr);
7117 ins_cost(200);
7118 format %{ "MOV $dst.lo,$src.lo\n\t"
7119 "MOV $dst.hi,$src.hi" %}
7120 opcode(0xB8);
7121 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7122 ins_pipe( ialu_reg_long_fat );
7123 %}
7124
7125 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7126 match(Set dst src);
7127 effect(KILL cr);
7128 ins_cost(150);
7129 format %{ "XOR $dst.lo,$dst.lo\n\t"
7130 "XOR $dst.hi,$dst.hi" %}
7131 opcode(0x33,0x33);
7132 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7133 ins_pipe( ialu_reg_long );
7134 %}
7135
7136 // The instruction usage is guarded by predicate in operand immF().
7137 instruct loadConF(regF dst, immF src) %{
7138 match(Set dst src);
7139 ins_cost(125);
7140
7141 format %{ "FLD_S ST,$src\n\t"
7142 "FSTP $dst" %}
7143 opcode(0xD9, 0x00); /* D9 /0 */
7144 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7145 ins_pipe( fpu_reg_con );
7146 %}
7147
7148 // The instruction usage is guarded by predicate in operand immXF().
7149 instruct loadConX(regX dst, immXF con) %{
7150 match(Set dst con);
7151 ins_cost(125);
7152 format %{ "MOVSS $dst,[$con]" %}
7153 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7154 ins_pipe( pipe_slow );
7155 %}
7156
7157 // The instruction usage is guarded by predicate in operand immXF0().
7158 instruct loadConX0(regX dst, immXF0 src) %{
7159 match(Set dst src);
7160 ins_cost(100);
7161 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7162 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7163 ins_pipe( pipe_slow );
7164 %}
7165
7166 // The instruction usage is guarded by predicate in operand immD().
7167 instruct loadConD(regD dst, immD src) %{
7168 match(Set dst src);
7169 ins_cost(125);
7170
7171 format %{ "FLD_D ST,$src\n\t"
7172 "FSTP $dst" %}
7173 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7174 ins_pipe( fpu_reg_con );
7175 %}
7176
7177 // The instruction usage is guarded by predicate in operand immXD().
7178 instruct loadConXD(regXD dst, immXD con) %{
7179 match(Set dst con);
7180 ins_cost(125);
7181 format %{ "MOVSD $dst,[$con]" %}
7182 ins_encode(load_conXD(dst, con));
7183 ins_pipe( pipe_slow );
7184 %}
7185
7186 // The instruction usage is guarded by predicate in operand immXD0().
7187 instruct loadConXD0(regXD dst, immXD0 src) %{
7188 match(Set dst src);
7189 ins_cost(100);
7190 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7191 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7192 ins_pipe( pipe_slow );
7193 %}
7194
7195 // Load Stack Slot
7196 instruct loadSSI(eRegI dst, stackSlotI src) %{
7197 match(Set dst src);
7198 ins_cost(125);
7199
7200 format %{ "MOV $dst,$src" %}
7201 opcode(0x8B);
7202 ins_encode( OpcP, RegMem(dst,src));
7203 ins_pipe( ialu_reg_mem );
7204 %}
7205
7206 instruct loadSSL(eRegL dst, stackSlotL src) %{
7207 match(Set dst src);
7208
7209 ins_cost(200);
7210 format %{ "MOV $dst,$src.lo\n\t"
7211 "MOV $dst+4,$src.hi" %}
7212 opcode(0x8B, 0x8B);
7213 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7214 ins_pipe( ialu_mem_long_reg );
7215 %}
7216
7217 // Load Stack Slot
7218 instruct loadSSP(eRegP dst, stackSlotP src) %{
7219 match(Set dst src);
7220 ins_cost(125);
7221
7222 format %{ "MOV $dst,$src" %}
7223 opcode(0x8B);
7224 ins_encode( OpcP, RegMem(dst,src));
7225 ins_pipe( ialu_reg_mem );
7226 %}
7227
7228 // Load Stack Slot
7229 instruct loadSSF(regF dst, stackSlotF src) %{
7230 match(Set dst src);
7231 ins_cost(125);
7232
7233 format %{ "FLD_S $src\n\t"
7234 "FSTP $dst" %}
7235 opcode(0xD9); /* D9 /0, FLD m32real */
7236 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7237 Pop_Reg_F(dst) );
7238 ins_pipe( fpu_reg_mem );
7239 %}
7240
7241 // Load Stack Slot
7242 instruct loadSSD(regD dst, stackSlotD src) %{
7243 match(Set dst src);
7244 ins_cost(125);
7245
7246 format %{ "FLD_D $src\n\t"
7247 "FSTP $dst" %}
7248 opcode(0xDD); /* DD /0, FLD m64real */
7249 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7250 Pop_Reg_D(dst) );
7251 ins_pipe( fpu_reg_mem );
7252 %}
7253
7254 // Prefetch instructions.
7255 // Must be safe to execute with invalid address (cannot fault).
7256
7257 instruct prefetchr0( memory mem ) %{
7258 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7259 match(PrefetchRead mem);
7260 ins_cost(0);
7261 size(0);
7262 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7263 ins_encode();
7264 ins_pipe(empty);
7265 %}
7266
7267 instruct prefetchr( memory mem ) %{
7268 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7269 match(PrefetchRead mem);
7270 ins_cost(100);
7271
7272 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7273 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7274 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7275 ins_pipe(ialu_mem);
7276 %}
7277
7278 instruct prefetchrNTA( memory mem ) %{
7279 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7280 match(PrefetchRead mem);
7281 ins_cost(100);
7282
7283 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7284 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7285 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7286 ins_pipe(ialu_mem);
7287 %}
7288
7289 instruct prefetchrT0( memory mem ) %{
7290 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7291 match(PrefetchRead mem);
7292 ins_cost(100);
7293
7294 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7295 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7296 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7297 ins_pipe(ialu_mem);
7298 %}
7299
7300 instruct prefetchrT2( memory mem ) %{
7301 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7302 match(PrefetchRead mem);
7303 ins_cost(100);
7304
7305 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7306 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7307 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7308 ins_pipe(ialu_mem);
7309 %}
7310
7311 instruct prefetchw0( memory mem ) %{
7312 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7313 match(PrefetchWrite mem);
7314 ins_cost(0);
7315 size(0);
7316 format %{ "Prefetch (non-SSE is empty encoding)" %}
7317 ins_encode();
7318 ins_pipe(empty);
7319 %}
7320
7321 instruct prefetchw( memory mem ) %{
7322 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7323 match( PrefetchWrite mem );
7324 ins_cost(100);
7325
7326 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7327 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7328 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7329 ins_pipe(ialu_mem);
7330 %}
7331
7332 instruct prefetchwNTA( memory mem ) %{
7333 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7334 match(PrefetchWrite mem);
7335 ins_cost(100);
7336
7337 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7338 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7339 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7340 ins_pipe(ialu_mem);
7341 %}
7342
7343 instruct prefetchwT0( memory mem ) %{
7344 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7345 match(PrefetchWrite mem);
7346 ins_cost(100);
7347
7348 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7349 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7350 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7351 ins_pipe(ialu_mem);
7352 %}
7353
7354 instruct prefetchwT2( memory mem ) %{
7355 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7356 match(PrefetchWrite mem);
7357 ins_cost(100);
7358
7359 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7360 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7361 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7362 ins_pipe(ialu_mem);
7363 %}
7364
7365 //----------Store Instructions-------------------------------------------------
7366
7367 // Store Byte
7368 instruct storeB(memory mem, xRegI src) %{
7369 match(Set mem (StoreB mem src));
7370
7371 ins_cost(125);
7372 format %{ "MOV8 $mem,$src" %}
7373 opcode(0x88);
7374 ins_encode( OpcP, RegMem( src, mem ) );
7375 ins_pipe( ialu_mem_reg );
7376 %}
7377
7378 // Store Char/Short
7379 instruct storeC(memory mem, eRegI src) %{
7380 match(Set mem (StoreC mem src));
7381
7382 ins_cost(125);
7383 format %{ "MOV16 $mem,$src" %}
7384 opcode(0x89, 0x66);
7385 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7386 ins_pipe( ialu_mem_reg );
7387 %}
7388
7389 // Store Integer
7390 instruct storeI(memory mem, eRegI src) %{
7391 match(Set mem (StoreI mem src));
7392
7393 ins_cost(125);
7394 format %{ "MOV $mem,$src" %}
7395 opcode(0x89);
7396 ins_encode( OpcP, RegMem( src, mem ) );
7397 ins_pipe( ialu_mem_reg );
7398 %}
7399
7400 // Store Long
7401 instruct storeL(long_memory mem, eRegL src) %{
7402 predicate(!((StoreLNode*)n)->require_atomic_access());
7403 match(Set mem (StoreL mem src));
7404
7405 ins_cost(200);
7406 format %{ "MOV $mem,$src.lo\n\t"
7407 "MOV $mem+4,$src.hi" %}
7408 opcode(0x89, 0x89);
7409 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7410 ins_pipe( ialu_mem_long_reg );
7411 %}
7412
7413 // Store Long to Integer
7414 instruct storeL2I(memory mem, eRegL src) %{
7415 match(Set mem (StoreI mem (ConvL2I src)));
7416
7417 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7418 ins_encode %{
7419 __ movl($mem$$Address, $src$$Register);
7420 %}
7421 ins_pipe(ialu_mem_reg);
7422 %}
7423
7424 // Volatile Store Long. Must be atomic, so move it into
7425 // the FP TOS and then do a 64-bit FIST. Has to probe the
7426 // target address before the store (for null-ptr checks)
7427 // so the memory operand is used twice in the encoding.
7428 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7429 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7430 match(Set mem (StoreL mem src));
7431 effect( KILL cr );
7432 ins_cost(400);
7433 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7434 "FILD $src\n\t"
7435 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7436 opcode(0x3B);
7437 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7438 ins_pipe( fpu_reg_mem );
7439 %}
7440
7441 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7442 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7443 match(Set mem (StoreL mem src));
7444 effect( TEMP tmp, KILL cr );
7445 ins_cost(380);
7446 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7447 "MOVSD $tmp,$src\n\t"
7448 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7449 opcode(0x3B);
7450 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7451 ins_pipe( pipe_slow );
7452 %}
7453
7454 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7455 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7456 match(Set mem (StoreL mem src));
7457 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7458 ins_cost(360);
7459 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7460 "MOVD $tmp,$src.lo\n\t"
7461 "MOVD $tmp2,$src.hi\n\t"
7462 "PUNPCKLDQ $tmp,$tmp2\n\t"
7463 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7464 opcode(0x3B);
7465 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7466 ins_pipe( pipe_slow );
7467 %}
7468
7469 // Store Pointer; for storing unknown oops and raw pointers
7470 instruct storeP(memory mem, anyRegP src) %{
7471 match(Set mem (StoreP mem src));
7472
7473 ins_cost(125);
7474 format %{ "MOV $mem,$src" %}
7475 opcode(0x89);
7476 ins_encode( OpcP, RegMem( src, mem ) );
7477 ins_pipe( ialu_mem_reg );
7478 %}
7479
7480 // Store Integer Immediate
7481 instruct storeImmI(memory mem, immI src) %{
7482 match(Set mem (StoreI mem src));
7483
7484 ins_cost(150);
7485 format %{ "MOV $mem,$src" %}
7486 opcode(0xC7); /* C7 /0 */
7487 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7488 ins_pipe( ialu_mem_imm );
7489 %}
7490
7491 // Store Short/Char Immediate
7492 instruct storeImmI16(memory mem, immI16 src) %{
7493 predicate(UseStoreImmI16);
7494 match(Set mem (StoreC mem src));
7495
7496 ins_cost(150);
7497 format %{ "MOV16 $mem,$src" %}
7498 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7499 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7500 ins_pipe( ialu_mem_imm );
7501 %}
7502
7503 // Store Pointer Immediate; null pointers or constant oops that do not
7504 // need card-mark barriers.
7505 instruct storeImmP(memory mem, immP src) %{
7506 match(Set mem (StoreP mem src));
7507
7508 ins_cost(150);
7509 format %{ "MOV $mem,$src" %}
7510 opcode(0xC7); /* C7 /0 */
7511 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7512 ins_pipe( ialu_mem_imm );
7513 %}
7514
7515 // Store Byte Immediate
7516 instruct storeImmB(memory mem, immI8 src) %{
7517 match(Set mem (StoreB mem src));
7518
7519 ins_cost(150);
7520 format %{ "MOV8 $mem,$src" %}
7521 opcode(0xC6); /* C6 /0 */
7522 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7523 ins_pipe( ialu_mem_imm );
7524 %}
7525
7526 // Store Aligned Packed Byte XMM register to memory
7527 instruct storeA8B(memory mem, regXD src) %{
7528 predicate(UseSSE>=1);
7529 match(Set mem (Store8B mem src));
7530 ins_cost(145);
7531 format %{ "MOVQ $mem,$src\t! packed8B" %}
7532 ins_encode( movq_st(mem, src));
7533 ins_pipe( pipe_slow );
7534 %}
7535
7536 // Store Aligned Packed Char/Short XMM register to memory
7537 instruct storeA4C(memory mem, regXD src) %{
7538 predicate(UseSSE>=1);
7539 match(Set mem (Store4C mem src));
7540 ins_cost(145);
7541 format %{ "MOVQ $mem,$src\t! packed4C" %}
7542 ins_encode( movq_st(mem, src));
7543 ins_pipe( pipe_slow );
7544 %}
7545
7546 // Store Aligned Packed Integer XMM register to memory
7547 instruct storeA2I(memory mem, regXD src) %{
7548 predicate(UseSSE>=1);
7549 match(Set mem (Store2I mem src));
7550 ins_cost(145);
7551 format %{ "MOVQ $mem,$src\t! packed2I" %}
7552 ins_encode( movq_st(mem, src));
7553 ins_pipe( pipe_slow );
7554 %}
7555
7556 // Store CMS card-mark Immediate
7557 instruct storeImmCM(memory mem, immI8 src) %{
7558 match(Set mem (StoreCM mem src));
7559
7560 ins_cost(150);
7561 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7562 opcode(0xC6); /* C6 /0 */
7563 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7564 ins_pipe( ialu_mem_imm );
7565 %}
7566
7567 // Store Double
7568 instruct storeD( memory mem, regDPR1 src) %{
7569 predicate(UseSSE<=1);
7570 match(Set mem (StoreD mem src));
7571
7572 ins_cost(100);
7573 format %{ "FST_D $mem,$src" %}
7574 opcode(0xDD); /* DD /2 */
7575 ins_encode( enc_FP_store(mem,src) );
7576 ins_pipe( fpu_mem_reg );
7577 %}
7578
7579 // Store double does rounding on x86
7580 instruct storeD_rounded( memory mem, regDPR1 src) %{
7581 predicate(UseSSE<=1);
7582 match(Set mem (StoreD mem (RoundDouble src)));
7583
7584 ins_cost(100);
7585 format %{ "FST_D $mem,$src\t# round" %}
7586 opcode(0xDD); /* DD /2 */
7587 ins_encode( enc_FP_store(mem,src) );
7588 ins_pipe( fpu_mem_reg );
7589 %}
7590
7591 // Store XMM register to memory (double-precision floating points)
7592 // MOVSD instruction
7593 instruct storeXD(memory mem, regXD src) %{
7594 predicate(UseSSE>=2);
7595 match(Set mem (StoreD mem src));
7596 ins_cost(95);
7597 format %{ "MOVSD $mem,$src" %}
7598 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7599 ins_pipe( pipe_slow );
7600 %}
7601
7602 // Store XMM register to memory (single-precision floating point)
7603 // MOVSS instruction
7604 instruct storeX(memory mem, regX src) %{
7605 predicate(UseSSE>=1);
7606 match(Set mem (StoreF mem src));
7607 ins_cost(95);
7608 format %{ "MOVSS $mem,$src" %}
7609 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7610 ins_pipe( pipe_slow );
7611 %}
7612
7613 // Store Aligned Packed Single Float XMM register to memory
7614 instruct storeA2F(memory mem, regXD src) %{
7615 predicate(UseSSE>=1);
7616 match(Set mem (Store2F mem src));
7617 ins_cost(145);
7618 format %{ "MOVQ $mem,$src\t! packed2F" %}
7619 ins_encode( movq_st(mem, src));
7620 ins_pipe( pipe_slow );
7621 %}
7622
7623 // Store Float
7624 instruct storeF( memory mem, regFPR1 src) %{
7625 predicate(UseSSE==0);
7626 match(Set mem (StoreF mem src));
7627
7628 ins_cost(100);
7629 format %{ "FST_S $mem,$src" %}
7630 opcode(0xD9); /* D9 /2 */
7631 ins_encode( enc_FP_store(mem,src) );
7632 ins_pipe( fpu_mem_reg );
7633 %}
7634
7635 // Store Float does rounding on x86
7636 instruct storeF_rounded( memory mem, regFPR1 src) %{
7637 predicate(UseSSE==0);
7638 match(Set mem (StoreF mem (RoundFloat src)));
7639
7640 ins_cost(100);
7641 format %{ "FST_S $mem,$src\t# round" %}
7642 opcode(0xD9); /* D9 /2 */
7643 ins_encode( enc_FP_store(mem,src) );
7644 ins_pipe( fpu_mem_reg );
7645 %}
7646
7647 // Store Float does rounding on x86
7648 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7649 predicate(UseSSE<=1);
7650 match(Set mem (StoreF mem (ConvD2F src)));
7651
7652 ins_cost(100);
7653 format %{ "FST_S $mem,$src\t# D-round" %}
7654 opcode(0xD9); /* D9 /2 */
7655 ins_encode( enc_FP_store(mem,src) );
7656 ins_pipe( fpu_mem_reg );
7657 %}
7658
7659 // Store immediate Float value (it is faster than store from FPU register)
7660 // The instruction usage is guarded by predicate in operand immF().
7661 instruct storeF_imm( memory mem, immF src) %{
7662 match(Set mem (StoreF mem src));
7663
7664 ins_cost(50);
7665 format %{ "MOV $mem,$src\t# store float" %}
7666 opcode(0xC7); /* C7 /0 */
7667 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7668 ins_pipe( ialu_mem_imm );
7669 %}
7670
7671 // Store immediate Float value (it is faster than store from XMM register)
7672 // The instruction usage is guarded by predicate in operand immXF().
7673 instruct storeX_imm( memory mem, immXF src) %{
7674 match(Set mem (StoreF mem src));
7675
7676 ins_cost(50);
7677 format %{ "MOV $mem,$src\t# store float" %}
7678 opcode(0xC7); /* C7 /0 */
7679 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7680 ins_pipe( ialu_mem_imm );
7681 %}
7682
7683 // Store Integer to stack slot
7684 instruct storeSSI(stackSlotI dst, eRegI src) %{
7685 match(Set dst src);
7686
7687 ins_cost(100);
7688 format %{ "MOV $dst,$src" %}
7689 opcode(0x89);
7690 ins_encode( OpcPRegSS( dst, src ) );
7691 ins_pipe( ialu_mem_reg );
7692 %}
7693
7694 // Store Integer to stack slot
7695 instruct storeSSP(stackSlotP dst, eRegP src) %{
7696 match(Set dst src);
7697
7698 ins_cost(100);
7699 format %{ "MOV $dst,$src" %}
7700 opcode(0x89);
7701 ins_encode( OpcPRegSS( dst, src ) );
7702 ins_pipe( ialu_mem_reg );
7703 %}
7704
7705 // Store Long to stack slot
7706 instruct storeSSL(stackSlotL dst, eRegL src) %{
7707 match(Set dst src);
7708
7709 ins_cost(200);
7710 format %{ "MOV $dst,$src.lo\n\t"
7711 "MOV $dst+4,$src.hi" %}
7712 opcode(0x89, 0x89);
7713 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7714 ins_pipe( ialu_mem_long_reg );
7715 %}
7716
7717 //----------MemBar Instructions-----------------------------------------------
7718 // Memory barrier flavors
7719
7720 instruct membar_acquire() %{
7721 match(MemBarAcquire);
7722 ins_cost(400);
7723
7724 size(0);
7725 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7726 ins_encode();
7727 ins_pipe(empty);
7728 %}
7729
7730 instruct membar_acquire_lock() %{
7731 match(MemBarAcquire);
7732 predicate(Matcher::prior_fast_lock(n));
7733 ins_cost(0);
7734
7735 size(0);
7736 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7737 ins_encode( );
7738 ins_pipe(empty);
7739 %}
7740
7741 instruct membar_release() %{
7742 match(MemBarRelease);
7743 ins_cost(400);
7744
7745 size(0);
7746 format %{ "MEMBAR-release ! (empty encoding)" %}
7747 ins_encode( );
7748 ins_pipe(empty);
7749 %}
7750
7751 instruct membar_release_lock() %{
7752 match(MemBarRelease);
7753 predicate(Matcher::post_fast_unlock(n));
7754 ins_cost(0);
7755
7756 size(0);
7757 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7758 ins_encode( );
7759 ins_pipe(empty);
7760 %}
7761
7762 instruct membar_volatile(eFlagsReg cr) %{
7763 match(MemBarVolatile);
7764 effect(KILL cr);
7765 ins_cost(400);
7766
7767 format %{
7768 $$template
7769 if (os::is_MP()) {
7770 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7771 } else {
7772 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7773 }
7774 %}
7775 ins_encode %{
7776 __ membar(Assembler::StoreLoad);
7777 %}
7778 ins_pipe(pipe_slow);
7779 %}
7780
7781 instruct unnecessary_membar_volatile() %{
7782 match(MemBarVolatile);
7783 predicate(Matcher::post_store_load_barrier(n));
7784 ins_cost(0);
7785
7786 size(0);
7787 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7788 ins_encode( );
7789 ins_pipe(empty);
7790 %}
7791
7792 //----------Move Instructions--------------------------------------------------
7793 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7794 match(Set dst (CastX2P src));
7795 format %{ "# X2P $dst, $src" %}
7796 ins_encode( /*empty encoding*/ );
7797 ins_cost(0);
7798 ins_pipe(empty);
7799 %}
7800
7801 instruct castP2X(eRegI dst, eRegP src ) %{
7802 match(Set dst (CastP2X src));
7803 ins_cost(50);
7804 format %{ "MOV $dst, $src\t# CastP2X" %}
7805 ins_encode( enc_Copy( dst, src) );
7806 ins_pipe( ialu_reg_reg );
7807 %}
7808
7809 //----------Conditional Move---------------------------------------------------
7810 // Conditional move
7811 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7812 predicate(VM_Version::supports_cmov() );
7813 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7814 ins_cost(200);
7815 format %{ "CMOV$cop $dst,$src" %}
7816 opcode(0x0F,0x40);
7817 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7818 ins_pipe( pipe_cmov_reg );
7819 %}
7820
7821 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7822 predicate(VM_Version::supports_cmov() );
7823 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7824 ins_cost(200);
7825 format %{ "CMOV$cop $dst,$src" %}
7826 opcode(0x0F,0x40);
7827 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7828 ins_pipe( pipe_cmov_reg );
7829 %}
7830
7831 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7832 predicate(VM_Version::supports_cmov() );
7833 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7834 ins_cost(200);
7835 expand %{
7836 cmovI_regU(cop, cr, dst, src);
7837 %}
7838 %}
7839
7840 // Conditional move
7841 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7842 predicate(VM_Version::supports_cmov() );
7843 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7844 ins_cost(250);
7845 format %{ "CMOV$cop $dst,$src" %}
7846 opcode(0x0F,0x40);
7847 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7848 ins_pipe( pipe_cmov_mem );
7849 %}
7850
7851 // Conditional move
7852 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7853 predicate(VM_Version::supports_cmov() );
7854 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7855 ins_cost(250);
7856 format %{ "CMOV$cop $dst,$src" %}
7857 opcode(0x0F,0x40);
7858 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7859 ins_pipe( pipe_cmov_mem );
7860 %}
7861
7862 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7863 predicate(VM_Version::supports_cmov() );
7864 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7865 ins_cost(250);
7866 expand %{
7867 cmovI_memU(cop, cr, dst, src);
7868 %}
7869 %}
7870
7871 // Conditional move
7872 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7873 predicate(VM_Version::supports_cmov() );
7874 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7875 ins_cost(200);
7876 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7877 opcode(0x0F,0x40);
7878 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7879 ins_pipe( pipe_cmov_reg );
7880 %}
7881
7882 // Conditional move (non-P6 version)
7883 // Note: a CMoveP is generated for stubs and native wrappers
7884 // regardless of whether we are on a P6, so we
7885 // emulate a cmov here
7886 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7887 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7888 ins_cost(300);
7889 format %{ "Jn$cop skip\n\t"
7890 "MOV $dst,$src\t# pointer\n"
7891 "skip:" %}
7892 opcode(0x8b);
7893 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7894 ins_pipe( pipe_cmov_reg );
7895 %}
7896
7897 // Conditional move
7898 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7899 predicate(VM_Version::supports_cmov() );
7900 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7901 ins_cost(200);
7902 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7903 opcode(0x0F,0x40);
7904 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7905 ins_pipe( pipe_cmov_reg );
7906 %}
7907
7908 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7909 predicate(VM_Version::supports_cmov() );
7910 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7911 ins_cost(200);
7912 expand %{
7913 cmovP_regU(cop, cr, dst, src);
7914 %}
7915 %}
7916
7917 // DISABLED: Requires the ADLC to emit a bottom_type call that
7918 // correctly meets the two pointer arguments; one is an incoming
7919 // register but the other is a memory operand. ALSO appears to
7920 // be buggy with implicit null checks.
7921 //
7922 //// Conditional move
7923 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7924 // predicate(VM_Version::supports_cmov() );
7925 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7926 // ins_cost(250);
7927 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7928 // opcode(0x0F,0x40);
7929 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7930 // ins_pipe( pipe_cmov_mem );
7931 //%}
7932 //
7933 //// Conditional move
7934 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7935 // predicate(VM_Version::supports_cmov() );
7936 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7937 // ins_cost(250);
7938 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7939 // opcode(0x0F,0x40);
7940 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7941 // ins_pipe( pipe_cmov_mem );
7942 //%}
7943
7944 // Conditional move
7945 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7946 predicate(UseSSE<=1);
7947 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7948 ins_cost(200);
7949 format %{ "FCMOV$cop $dst,$src\t# double" %}
7950 opcode(0xDA);
7951 ins_encode( enc_cmov_d(cop,src) );
7952 ins_pipe( pipe_cmovD_reg );
7953 %}
7954
7955 // Conditional move
7956 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7957 predicate(UseSSE==0);
7958 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7959 ins_cost(200);
7960 format %{ "FCMOV$cop $dst,$src\t# float" %}
7961 opcode(0xDA);
7962 ins_encode( enc_cmov_d(cop,src) );
7963 ins_pipe( pipe_cmovD_reg );
7964 %}
7965
7966 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7967 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7968 predicate(UseSSE<=1);
7969 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7970 ins_cost(200);
7971 format %{ "Jn$cop skip\n\t"
7972 "MOV $dst,$src\t# double\n"
7973 "skip:" %}
7974 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7975 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7976 ins_pipe( pipe_cmovD_reg );
7977 %}
7978
7979 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7980 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7981 predicate(UseSSE==0);
7982 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7983 ins_cost(200);
7984 format %{ "Jn$cop skip\n\t"
7985 "MOV $dst,$src\t# float\n"
7986 "skip:" %}
7987 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7988 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7989 ins_pipe( pipe_cmovD_reg );
7990 %}
7991
7992 // No CMOVE with SSE/SSE2
7993 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7994 predicate (UseSSE>=1);
7995 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7996 ins_cost(200);
7997 format %{ "Jn$cop skip\n\t"
7998 "MOVSS $dst,$src\t# float\n"
7999 "skip:" %}
8000 ins_encode %{
8001 Label skip;
8002 // Invert sense of branch from sense of CMOV
8003 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8004 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8005 __ bind(skip);
8006 %}
8007 ins_pipe( pipe_slow );
8008 %}
8009
8010 // No CMOVE with SSE/SSE2
8011 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8012 predicate (UseSSE>=2);
8013 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8014 ins_cost(200);
8015 format %{ "Jn$cop skip\n\t"
8016 "MOVSD $dst,$src\t# float\n"
8017 "skip:" %}
8018 ins_encode %{
8019 Label skip;
8020 // Invert sense of branch from sense of CMOV
8021 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8022 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8023 __ bind(skip);
8024 %}
8025 ins_pipe( pipe_slow );
8026 %}
8027
8028 // unsigned version
8029 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8030 predicate (UseSSE>=1);
8031 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8032 ins_cost(200);
8033 format %{ "Jn$cop skip\n\t"
8034 "MOVSS $dst,$src\t# float\n"
8035 "skip:" %}
8036 ins_encode %{
8037 Label skip;
8038 // Invert sense of branch from sense of CMOV
8039 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8040 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8041 __ bind(skip);
8042 %}
8043 ins_pipe( pipe_slow );
8044 %}
8045
8046 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8047 predicate (UseSSE>=1);
8048 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8049 ins_cost(200);
8050 expand %{
8051 fcmovX_regU(cop, cr, dst, src);
8052 %}
8053 %}
8054
8055 // unsigned version
8056 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8057 predicate (UseSSE>=2);
8058 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8059 ins_cost(200);
8060 format %{ "Jn$cop skip\n\t"
8061 "MOVSD $dst,$src\t# float\n"
8062 "skip:" %}
8063 ins_encode %{
8064 Label skip;
8065 // Invert sense of branch from sense of CMOV
8066 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8067 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8068 __ bind(skip);
8069 %}
8070 ins_pipe( pipe_slow );
8071 %}
8072
8073 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8074 predicate (UseSSE>=2);
8075 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8076 ins_cost(200);
8077 expand %{
8078 fcmovXD_regU(cop, cr, dst, src);
8079 %}
8080 %}
8081
8082 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8083 predicate(VM_Version::supports_cmov() );
8084 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8085 ins_cost(200);
8086 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8087 "CMOV$cop $dst.hi,$src.hi" %}
8088 opcode(0x0F,0x40);
8089 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8090 ins_pipe( pipe_cmov_reg_long );
8091 %}
8092
8093 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8094 predicate(VM_Version::supports_cmov() );
8095 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8096 ins_cost(200);
8097 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8098 "CMOV$cop $dst.hi,$src.hi" %}
8099 opcode(0x0F,0x40);
8100 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8101 ins_pipe( pipe_cmov_reg_long );
8102 %}
8103
8104 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8105 predicate(VM_Version::supports_cmov() );
8106 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8107 ins_cost(200);
8108 expand %{
8109 cmovL_regU(cop, cr, dst, src);
8110 %}
8111 %}
8112
8113 //----------Arithmetic Instructions--------------------------------------------
8114 //----------Addition Instructions----------------------------------------------
8115 // Integer Addition Instructions
8116 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8117 match(Set dst (AddI dst src));
8118 effect(KILL cr);
8119
8120 size(2);
8121 format %{ "ADD $dst,$src" %}
8122 opcode(0x03);
8123 ins_encode( OpcP, RegReg( dst, src) );
8124 ins_pipe( ialu_reg_reg );
8125 %}
8126
8127 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8128 match(Set dst (AddI dst src));
8129 effect(KILL cr);
8130
8131 format %{ "ADD $dst,$src" %}
8132 opcode(0x81, 0x00); /* /0 id */
8133 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8134 ins_pipe( ialu_reg );
8135 %}
8136
8137 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8138 predicate(UseIncDec);
8139 match(Set dst (AddI dst src));
8140 effect(KILL cr);
8141
8142 size(1);
8143 format %{ "INC $dst" %}
8144 opcode(0x40); /* */
8145 ins_encode( Opc_plus( primary, dst ) );
8146 ins_pipe( ialu_reg );
8147 %}
8148
8149 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8150 match(Set dst (AddI src0 src1));
8151 ins_cost(110);
8152
8153 format %{ "LEA $dst,[$src0 + $src1]" %}
8154 opcode(0x8D); /* 0x8D /r */
8155 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8156 ins_pipe( ialu_reg_reg );
8157 %}
8158
8159 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8160 match(Set dst (AddP src0 src1));
8161 ins_cost(110);
8162
8163 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8164 opcode(0x8D); /* 0x8D /r */
8165 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8166 ins_pipe( ialu_reg_reg );
8167 %}
8168
8169 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8170 predicate(UseIncDec);
8171 match(Set dst (AddI dst src));
8172 effect(KILL cr);
8173
8174 size(1);
8175 format %{ "DEC $dst" %}
8176 opcode(0x48); /* */
8177 ins_encode( Opc_plus( primary, dst ) );
8178 ins_pipe( ialu_reg );
8179 %}
8180
8181 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8182 match(Set dst (AddP dst src));
8183 effect(KILL cr);
8184
8185 size(2);
8186 format %{ "ADD $dst,$src" %}
8187 opcode(0x03);
8188 ins_encode( OpcP, RegReg( dst, src) );
8189 ins_pipe( ialu_reg_reg );
8190 %}
8191
8192 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8193 match(Set dst (AddP dst src));
8194 effect(KILL cr);
8195
8196 format %{ "ADD $dst,$src" %}
8197 opcode(0x81,0x00); /* Opcode 81 /0 id */
8198 // ins_encode( RegImm( dst, src) );
8199 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8200 ins_pipe( ialu_reg );
8201 %}
8202
8203 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8204 match(Set dst (AddI dst (LoadI src)));
8205 effect(KILL cr);
8206
8207 ins_cost(125);
8208 format %{ "ADD $dst,$src" %}
8209 opcode(0x03);
8210 ins_encode( OpcP, RegMem( dst, src) );
8211 ins_pipe( ialu_reg_mem );
8212 %}
8213
8214 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8215 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8216 effect(KILL cr);
8217
8218 ins_cost(150);
8219 format %{ "ADD $dst,$src" %}
8220 opcode(0x01); /* Opcode 01 /r */
8221 ins_encode( OpcP, RegMem( src, dst ) );
8222 ins_pipe( ialu_mem_reg );
8223 %}
8224
8225 // Add Memory with Immediate
8226 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8227 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8228 effect(KILL cr);
8229
8230 ins_cost(125);
8231 format %{ "ADD $dst,$src" %}
8232 opcode(0x81); /* Opcode 81 /0 id */
8233 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8234 ins_pipe( ialu_mem_imm );
8235 %}
8236
8237 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8238 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8239 effect(KILL cr);
8240
8241 ins_cost(125);
8242 format %{ "INC $dst" %}
8243 opcode(0xFF); /* Opcode FF /0 */
8244 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8245 ins_pipe( ialu_mem_imm );
8246 %}
8247
8248 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8249 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8250 effect(KILL cr);
8251
8252 ins_cost(125);
8253 format %{ "DEC $dst" %}
8254 opcode(0xFF); /* Opcode FF /1 */
8255 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8256 ins_pipe( ialu_mem_imm );
8257 %}
8258
8259
8260 instruct checkCastPP( eRegP dst ) %{
8261 match(Set dst (CheckCastPP dst));
8262
8263 size(0);
8264 format %{ "#checkcastPP of $dst" %}
8265 ins_encode( /*empty encoding*/ );
8266 ins_pipe( empty );
8267 %}
8268
8269 instruct castPP( eRegP dst ) %{
8270 match(Set dst (CastPP dst));
8271 format %{ "#castPP of $dst" %}
8272 ins_encode( /*empty encoding*/ );
8273 ins_pipe( empty );
8274 %}
8275
8276 instruct castII( eRegI dst ) %{
8277 match(Set dst (CastII dst));
8278 format %{ "#castII of $dst" %}
8279 ins_encode( /*empty encoding*/ );
8280 ins_cost(0);
8281 ins_pipe( empty );
8282 %}
8283
8284
8285 // Load-locked - same as a regular pointer load when used with compare-swap
8286 instruct loadPLocked(eRegP dst, memory mem) %{
8287 match(Set dst (LoadPLocked mem));
8288
8289 ins_cost(125);
8290 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8291 opcode(0x8B);
8292 ins_encode( OpcP, RegMem(dst,mem));
8293 ins_pipe( ialu_reg_mem );
8294 %}
8295
8296 // LoadLong-locked - same as a volatile long load when used with compare-swap
8297 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8298 predicate(UseSSE<=1);
8299 match(Set dst (LoadLLocked mem));
8300
8301 ins_cost(200);
8302 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8303 "FISTp $dst" %}
8304 ins_encode(enc_loadL_volatile(mem,dst));
8305 ins_pipe( fpu_reg_mem );
8306 %}
8307
8308 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8309 predicate(UseSSE>=2);
8310 match(Set dst (LoadLLocked mem));
8311 effect(TEMP tmp);
8312 ins_cost(180);
8313 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8314 "MOVSD $dst,$tmp" %}
8315 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8316 ins_pipe( pipe_slow );
8317 %}
8318
8319 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8320 predicate(UseSSE>=2);
8321 match(Set dst (LoadLLocked mem));
8322 effect(TEMP tmp);
8323 ins_cost(160);
8324 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8325 "MOVD $dst.lo,$tmp\n\t"
8326 "PSRLQ $tmp,32\n\t"
8327 "MOVD $dst.hi,$tmp" %}
8328 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8329 ins_pipe( pipe_slow );
8330 %}
8331
8332 // Conditional-store of the updated heap-top.
8333 // Used during allocation of the shared heap.
8334 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8335 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8336 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8337 // EAX is killed if there is contention, but then it's also unused.
8338 // In the common case of no contention, EAX holds the new oop address.
8339 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8340 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8341 ins_pipe( pipe_cmpxchg );
8342 %}
8343
8344 // Conditional-store of an int value.
8345 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8346 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8347 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8348 effect(KILL oldval);
8349 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8350 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8351 ins_pipe( pipe_cmpxchg );
8352 %}
8353
8354 // Conditional-store of a long value.
8355 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8356 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8357 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8358 effect(KILL oldval);
8359 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8360 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8361 "XCHG EBX,ECX"
8362 %}
8363 ins_encode %{
8364 // Note: we need to swap rbx, and rcx before and after the
8365 // cmpxchg8 instruction because the instruction uses
8366 // rcx as the high order word of the new value to store but
8367 // our register encoding uses rbx.
8368 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8369 if( os::is_MP() )
8370 __ lock();
8371 __ cmpxchg8($mem$$Address);
8372 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8373 %}
8374 ins_pipe( pipe_cmpxchg );
8375 %}
8376
8377 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8378
8379 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8380 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8381 effect(KILL cr, KILL oldval);
8382 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8383 "MOV $res,0\n\t"
8384 "JNE,s fail\n\t"
8385 "MOV $res,1\n"
8386 "fail:" %}
8387 ins_encode( enc_cmpxchg8(mem_ptr),
8388 enc_flags_ne_to_boolean(res) );
8389 ins_pipe( pipe_cmpxchg );
8390 %}
8391
8392 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8393 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8394 effect(KILL cr, KILL oldval);
8395 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8396 "MOV $res,0\n\t"
8397 "JNE,s fail\n\t"
8398 "MOV $res,1\n"
8399 "fail:" %}
8400 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8401 ins_pipe( pipe_cmpxchg );
8402 %}
8403
8404 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8405 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8406 effect(KILL cr, KILL oldval);
8407 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8408 "MOV $res,0\n\t"
8409 "JNE,s fail\n\t"
8410 "MOV $res,1\n"
8411 "fail:" %}
8412 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8413 ins_pipe( pipe_cmpxchg );
8414 %}
8415
8416 //----------Subtraction Instructions-------------------------------------------
8417 // Integer Subtraction Instructions
8418 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8419 match(Set dst (SubI dst src));
8420 effect(KILL cr);
8421
8422 size(2);
8423 format %{ "SUB $dst,$src" %}
8424 opcode(0x2B);
8425 ins_encode( OpcP, RegReg( dst, src) );
8426 ins_pipe( ialu_reg_reg );
8427 %}
8428
8429 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8430 match(Set dst (SubI dst src));
8431 effect(KILL cr);
8432
8433 format %{ "SUB $dst,$src" %}
8434 opcode(0x81,0x05); /* Opcode 81 /5 */
8435 // ins_encode( RegImm( dst, src) );
8436 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8437 ins_pipe( ialu_reg );
8438 %}
8439
8440 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8441 match(Set dst (SubI dst (LoadI src)));
8442 effect(KILL cr);
8443
8444 ins_cost(125);
8445 format %{ "SUB $dst,$src" %}
8446 opcode(0x2B);
8447 ins_encode( OpcP, RegMem( dst, src) );
8448 ins_pipe( ialu_reg_mem );
8449 %}
8450
8451 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8452 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8453 effect(KILL cr);
8454
8455 ins_cost(150);
8456 format %{ "SUB $dst,$src" %}
8457 opcode(0x29); /* Opcode 29 /r */
8458 ins_encode( OpcP, RegMem( src, dst ) );
8459 ins_pipe( ialu_mem_reg );
8460 %}
8461
8462 // Subtract from a pointer
8463 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8464 match(Set dst (AddP dst (SubI zero src)));
8465 effect(KILL cr);
8466
8467 size(2);
8468 format %{ "SUB $dst,$src" %}
8469 opcode(0x2B);
8470 ins_encode( OpcP, RegReg( dst, src) );
8471 ins_pipe( ialu_reg_reg );
8472 %}
8473
8474 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8475 match(Set dst (SubI zero dst));
8476 effect(KILL cr);
8477
8478 size(2);
8479 format %{ "NEG $dst" %}
8480 opcode(0xF7,0x03); // Opcode F7 /3
8481 ins_encode( OpcP, RegOpc( dst ) );
8482 ins_pipe( ialu_reg );
8483 %}
8484
8485
8486 //----------Multiplication/Division Instructions-------------------------------
8487 // Integer Multiplication Instructions
8488 // Multiply Register
8489 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8490 match(Set dst (MulI dst src));
8491 effect(KILL cr);
8492
8493 size(3);
8494 ins_cost(300);
8495 format %{ "IMUL $dst,$src" %}
8496 opcode(0xAF, 0x0F);
8497 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8498 ins_pipe( ialu_reg_reg_alu0 );
8499 %}
8500
8501 // Multiply 32-bit Immediate
8502 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8503 match(Set dst (MulI src imm));
8504 effect(KILL cr);
8505
8506 ins_cost(300);
8507 format %{ "IMUL $dst,$src,$imm" %}
8508 opcode(0x69); /* 69 /r id */
8509 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8510 ins_pipe( ialu_reg_reg_alu0 );
8511 %}
8512
8513 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8514 match(Set dst src);
8515 effect(KILL cr);
8516
8517 // Note that this is artificially increased to make it more expensive than loadConL
8518 ins_cost(250);
8519 format %{ "MOV EAX,$src\t// low word only" %}
8520 opcode(0xB8);
8521 ins_encode( LdImmL_Lo(dst, src) );
8522 ins_pipe( ialu_reg_fat );
8523 %}
8524
8525 // Multiply by 32-bit Immediate, taking the shifted high order results
8526 // (special case for shift by 32)
8527 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8528 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8529 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8530 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8531 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8532 effect(USE src1, KILL cr);
8533
8534 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8535 ins_cost(0*100 + 1*400 - 150);
8536 format %{ "IMUL EDX:EAX,$src1" %}
8537 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8538 ins_pipe( pipe_slow );
8539 %}
8540
8541 // Multiply by 32-bit Immediate, taking the shifted high order results
8542 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8543 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8544 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8545 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8546 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8547 effect(USE src1, KILL cr);
8548
8549 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8550 ins_cost(1*100 + 1*400 - 150);
8551 format %{ "IMUL EDX:EAX,$src1\n\t"
8552 "SAR EDX,$cnt-32" %}
8553 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8554 ins_pipe( pipe_slow );
8555 %}
8556
8557 // Multiply Memory 32-bit Immediate
8558 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8559 match(Set dst (MulI (LoadI src) imm));
8560 effect(KILL cr);
8561
8562 ins_cost(300);
8563 format %{ "IMUL $dst,$src,$imm" %}
8564 opcode(0x69); /* 69 /r id */
8565 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8566 ins_pipe( ialu_reg_mem_alu0 );
8567 %}
8568
8569 // Multiply Memory
8570 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8571 match(Set dst (MulI dst (LoadI src)));
8572 effect(KILL cr);
8573
8574 ins_cost(350);
8575 format %{ "IMUL $dst,$src" %}
8576 opcode(0xAF, 0x0F);
8577 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8578 ins_pipe( ialu_reg_mem_alu0 );
8579 %}
8580
8581 // Multiply Register Int to Long
8582 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8583 // Basic Idea: long = (long)int * (long)int
8584 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8585 effect(DEF dst, USE src, USE src1, KILL flags);
8586
8587 ins_cost(300);
8588 format %{ "IMUL $dst,$src1" %}
8589
8590 ins_encode( long_int_multiply( dst, src1 ) );
8591 ins_pipe( ialu_reg_reg_alu0 );
8592 %}
8593
8594 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8595 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8596 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8597 effect(KILL flags);
8598
8599 ins_cost(300);
8600 format %{ "MUL $dst,$src1" %}
8601
8602 ins_encode( long_uint_multiply(dst, src1) );
8603 ins_pipe( ialu_reg_reg_alu0 );
8604 %}
8605
8606 // Multiply Register Long
8607 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8608 match(Set dst (MulL dst src));
8609 effect(KILL cr, TEMP tmp);
8610 ins_cost(4*100+3*400);
8611 // Basic idea: lo(result) = lo(x_lo * y_lo)
8612 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8613 format %{ "MOV $tmp,$src.lo\n\t"
8614 "IMUL $tmp,EDX\n\t"
8615 "MOV EDX,$src.hi\n\t"
8616 "IMUL EDX,EAX\n\t"
8617 "ADD $tmp,EDX\n\t"
8618 "MUL EDX:EAX,$src.lo\n\t"
8619 "ADD EDX,$tmp" %}
8620 ins_encode( long_multiply( dst, src, tmp ) );
8621 ins_pipe( pipe_slow );
8622 %}
8623
8624 // Multiply Register Long where the left operand's high 32 bits are zero
8625 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8626 predicate(is_operand_hi32_zero(n->in(1)));
8627 match(Set dst (MulL dst src));
8628 effect(KILL cr, TEMP tmp);
8629 ins_cost(2*100+2*400);
8630 // Basic idea: lo(result) = lo(x_lo * y_lo)
8631 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8632 format %{ "MOV $tmp,$src.hi\n\t"
8633 "IMUL $tmp,EAX\n\t"
8634 "MUL EDX:EAX,$src.lo\n\t"
8635 "ADD EDX,$tmp" %}
8636 ins_encode %{
8637 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8638 __ imull($tmp$$Register, rax);
8639 __ mull($src$$Register);
8640 __ addl(rdx, $tmp$$Register);
8641 %}
8642 ins_pipe( pipe_slow );
8643 %}
8644
8645 // Multiply Register Long where the right operand's high 32 bits are zero
8646 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8647 predicate(is_operand_hi32_zero(n->in(2)));
8648 match(Set dst (MulL dst src));
8649 effect(KILL cr, TEMP tmp);
8650 ins_cost(2*100+2*400);
8651 // Basic idea: lo(result) = lo(x_lo * y_lo)
8652 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8653 format %{ "MOV $tmp,$src.lo\n\t"
8654 "IMUL $tmp,EDX\n\t"
8655 "MUL EDX:EAX,$src.lo\n\t"
8656 "ADD EDX,$tmp" %}
8657 ins_encode %{
8658 __ movl($tmp$$Register, $src$$Register);
8659 __ imull($tmp$$Register, rdx);
8660 __ mull($src$$Register);
8661 __ addl(rdx, $tmp$$Register);
8662 %}
8663 ins_pipe( pipe_slow );
8664 %}
8665
8666 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8667 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8668 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8669 match(Set dst (MulL dst src));
8670 effect(KILL cr);
8671 ins_cost(1*400);
8672 // Basic idea: lo(result) = lo(x_lo * y_lo)
8673 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8674 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8675 ins_encode %{
8676 __ mull($src$$Register);
8677 %}
8678 ins_pipe( pipe_slow );
8679 %}
8680
8681 // Multiply Register Long by small constant
8682 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8683 match(Set dst (MulL dst src));
8684 effect(KILL cr, TEMP tmp);
8685 ins_cost(2*100+2*400);
8686 size(12);
8687 // Basic idea: lo(result) = lo(src * EAX)
8688 // hi(result) = hi(src * EAX) + lo(src * EDX)
8689 format %{ "IMUL $tmp,EDX,$src\n\t"
8690 "MOV EDX,$src\n\t"
8691 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8692 "ADD EDX,$tmp" %}
8693 ins_encode( long_multiply_con( dst, src, tmp ) );
8694 ins_pipe( pipe_slow );
8695 %}
8696
8697 // Integer DIV with Register
8698 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8699 match(Set rax (DivI rax div));
8700 effect(KILL rdx, KILL cr);
8701 size(26);
8702 ins_cost(30*100+10*100);
8703 format %{ "CMP EAX,0x80000000\n\t"
8704 "JNE,s normal\n\t"
8705 "XOR EDX,EDX\n\t"
8706 "CMP ECX,-1\n\t"
8707 "JE,s done\n"
8708 "normal: CDQ\n\t"
8709 "IDIV $div\n\t"
8710 "done:" %}
8711 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8712 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8713 ins_pipe( ialu_reg_reg_alu0 );
8714 %}
8715
8716 // Divide Register Long
8717 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8718 match(Set dst (DivL src1 src2));
8719 effect( KILL cr, KILL cx, KILL bx );
8720 ins_cost(10000);
8721 format %{ "PUSH $src1.hi\n\t"
8722 "PUSH $src1.lo\n\t"
8723 "PUSH $src2.hi\n\t"
8724 "PUSH $src2.lo\n\t"
8725 "CALL SharedRuntime::ldiv\n\t"
8726 "ADD ESP,16" %}
8727 ins_encode( long_div(src1,src2) );
8728 ins_pipe( pipe_slow );
8729 %}
8730
8731 // Integer DIVMOD with Register, both quotient and mod results
8732 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8733 match(DivModI rax div);
8734 effect(KILL cr);
8735 size(26);
8736 ins_cost(30*100+10*100);
8737 format %{ "CMP EAX,0x80000000\n\t"
8738 "JNE,s normal\n\t"
8739 "XOR EDX,EDX\n\t"
8740 "CMP ECX,-1\n\t"
8741 "JE,s done\n"
8742 "normal: CDQ\n\t"
8743 "IDIV $div\n\t"
8744 "done:" %}
8745 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8746 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8747 ins_pipe( pipe_slow );
8748 %}
8749
8750 // Integer MOD with Register
8751 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8752 match(Set rdx (ModI rax div));
8753 effect(KILL rax, KILL cr);
8754
8755 size(26);
8756 ins_cost(300);
8757 format %{ "CDQ\n\t"
8758 "IDIV $div" %}
8759 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8760 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8761 ins_pipe( ialu_reg_reg_alu0 );
8762 %}
8763
8764 // Remainder Register Long
8765 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8766 match(Set dst (ModL src1 src2));
8767 effect( KILL cr, KILL cx, KILL bx );
8768 ins_cost(10000);
8769 format %{ "PUSH $src1.hi\n\t"
8770 "PUSH $src1.lo\n\t"
8771 "PUSH $src2.hi\n\t"
8772 "PUSH $src2.lo\n\t"
8773 "CALL SharedRuntime::lrem\n\t"
8774 "ADD ESP,16" %}
8775 ins_encode( long_mod(src1,src2) );
8776 ins_pipe( pipe_slow );
8777 %}
8778
8779 // Integer Shift Instructions
8780 // Shift Left by one
8781 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8782 match(Set dst (LShiftI dst shift));
8783 effect(KILL cr);
8784
8785 size(2);
8786 format %{ "SHL $dst,$shift" %}
8787 opcode(0xD1, 0x4); /* D1 /4 */
8788 ins_encode( OpcP, RegOpc( dst ) );
8789 ins_pipe( ialu_reg );
8790 %}
8791
8792 // Shift Left by 8-bit immediate
8793 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8794 match(Set dst (LShiftI dst shift));
8795 effect(KILL cr);
8796
8797 size(3);
8798 format %{ "SHL $dst,$shift" %}
8799 opcode(0xC1, 0x4); /* C1 /4 ib */
8800 ins_encode( RegOpcImm( dst, shift) );
8801 ins_pipe( ialu_reg );
8802 %}
8803
8804 // Shift Left by variable
8805 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8806 match(Set dst (LShiftI dst shift));
8807 effect(KILL cr);
8808
8809 size(2);
8810 format %{ "SHL $dst,$shift" %}
8811 opcode(0xD3, 0x4); /* D3 /4 */
8812 ins_encode( OpcP, RegOpc( dst ) );
8813 ins_pipe( ialu_reg_reg );
8814 %}
8815
8816 // Arithmetic shift right by one
8817 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8818 match(Set dst (RShiftI dst shift));
8819 effect(KILL cr);
8820
8821 size(2);
8822 format %{ "SAR $dst,$shift" %}
8823 opcode(0xD1, 0x7); /* D1 /7 */
8824 ins_encode( OpcP, RegOpc( dst ) );
8825 ins_pipe( ialu_reg );
8826 %}
8827
8828 // Arithmetic shift right by one
8829 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8830 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8831 effect(KILL cr);
8832 format %{ "SAR $dst,$shift" %}
8833 opcode(0xD1, 0x7); /* D1 /7 */
8834 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8835 ins_pipe( ialu_mem_imm );
8836 %}
8837
8838 // Arithmetic Shift Right by 8-bit immediate
8839 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8840 match(Set dst (RShiftI dst shift));
8841 effect(KILL cr);
8842
8843 size(3);
8844 format %{ "SAR $dst,$shift" %}
8845 opcode(0xC1, 0x7); /* C1 /7 ib */
8846 ins_encode( RegOpcImm( dst, shift ) );
8847 ins_pipe( ialu_mem_imm );
8848 %}
8849
8850 // Arithmetic Shift Right by 8-bit immediate
8851 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8852 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8853 effect(KILL cr);
8854
8855 format %{ "SAR $dst,$shift" %}
8856 opcode(0xC1, 0x7); /* C1 /7 ib */
8857 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8858 ins_pipe( ialu_mem_imm );
8859 %}
8860
8861 // Arithmetic Shift Right by variable
8862 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8863 match(Set dst (RShiftI dst shift));
8864 effect(KILL cr);
8865
8866 size(2);
8867 format %{ "SAR $dst,$shift" %}
8868 opcode(0xD3, 0x7); /* D3 /7 */
8869 ins_encode( OpcP, RegOpc( dst ) );
8870 ins_pipe( ialu_reg_reg );
8871 %}
8872
8873 // Logical shift right by one
8874 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8875 match(Set dst (URShiftI dst shift));
8876 effect(KILL cr);
8877
8878 size(2);
8879 format %{ "SHR $dst,$shift" %}
8880 opcode(0xD1, 0x5); /* D1 /5 */
8881 ins_encode( OpcP, RegOpc( dst ) );
8882 ins_pipe( ialu_reg );
8883 %}
8884
8885 // Logical Shift Right by 8-bit immediate
8886 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8887 match(Set dst (URShiftI dst shift));
8888 effect(KILL cr);
8889
8890 size(3);
8891 format %{ "SHR $dst,$shift" %}
8892 opcode(0xC1, 0x5); /* C1 /5 ib */
8893 ins_encode( RegOpcImm( dst, shift) );
8894 ins_pipe( ialu_reg );
8895 %}
8896
8897
8898 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8899 // This idiom is used by the compiler for the i2b bytecode.
8900 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8901 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8902
8903 size(3);
8904 format %{ "MOVSX $dst,$src :8" %}
8905 ins_encode %{
8906 __ movsbl($dst$$Register, $src$$Register);
8907 %}
8908 ins_pipe(ialu_reg_reg);
8909 %}
8910
8911 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8912 // This idiom is used by the compiler the i2s bytecode.
8913 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8914 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8915
8916 size(3);
8917 format %{ "MOVSX $dst,$src :16" %}
8918 ins_encode %{
8919 __ movswl($dst$$Register, $src$$Register);
8920 %}
8921 ins_pipe(ialu_reg_reg);
8922 %}
8923
8924
8925 // Logical Shift Right by variable
8926 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8927 match(Set dst (URShiftI dst shift));
8928 effect(KILL cr);
8929
8930 size(2);
8931 format %{ "SHR $dst,$shift" %}
8932 opcode(0xD3, 0x5); /* D3 /5 */
8933 ins_encode( OpcP, RegOpc( dst ) );
8934 ins_pipe( ialu_reg_reg );
8935 %}
8936
8937
8938 //----------Logical Instructions-----------------------------------------------
8939 //----------Integer Logical Instructions---------------------------------------
8940 // And Instructions
8941 // And Register with Register
8942 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8943 match(Set dst (AndI dst src));
8944 effect(KILL cr);
8945
8946 size(2);
8947 format %{ "AND $dst,$src" %}
8948 opcode(0x23);
8949 ins_encode( OpcP, RegReg( dst, src) );
8950 ins_pipe( ialu_reg_reg );
8951 %}
8952
8953 // And Register with Immediate
8954 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8955 match(Set dst (AndI dst src));
8956 effect(KILL cr);
8957
8958 format %{ "AND $dst,$src" %}
8959 opcode(0x81,0x04); /* Opcode 81 /4 */
8960 // ins_encode( RegImm( dst, src) );
8961 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8962 ins_pipe( ialu_reg );
8963 %}
8964
8965 // And Register with Memory
8966 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8967 match(Set dst (AndI dst (LoadI src)));
8968 effect(KILL cr);
8969
8970 ins_cost(125);
8971 format %{ "AND $dst,$src" %}
8972 opcode(0x23);
8973 ins_encode( OpcP, RegMem( dst, src) );
8974 ins_pipe( ialu_reg_mem );
8975 %}
8976
8977 // And Memory with Register
8978 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8979 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8980 effect(KILL cr);
8981
8982 ins_cost(150);
8983 format %{ "AND $dst,$src" %}
8984 opcode(0x21); /* Opcode 21 /r */
8985 ins_encode( OpcP, RegMem( src, dst ) );
8986 ins_pipe( ialu_mem_reg );
8987 %}
8988
8989 // And Memory with Immediate
8990 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8991 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8992 effect(KILL cr);
8993
8994 ins_cost(125);
8995 format %{ "AND $dst,$src" %}
8996 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8997 // ins_encode( MemImm( dst, src) );
8998 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8999 ins_pipe( ialu_mem_imm );
9000 %}
9001
9002 // Or Instructions
9003 // Or Register with Register
9004 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9005 match(Set dst (OrI dst src));
9006 effect(KILL cr);
9007
9008 size(2);
9009 format %{ "OR $dst,$src" %}
9010 opcode(0x0B);
9011 ins_encode( OpcP, RegReg( dst, src) );
9012 ins_pipe( ialu_reg_reg );
9013 %}
9014
9015 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9016 match(Set dst (OrI dst (CastP2X src)));
9017 effect(KILL cr);
9018
9019 size(2);
9020 format %{ "OR $dst,$src" %}
9021 opcode(0x0B);
9022 ins_encode( OpcP, RegReg( dst, src) );
9023 ins_pipe( ialu_reg_reg );
9024 %}
9025
9026
9027 // Or Register with Immediate
9028 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9029 match(Set dst (OrI dst src));
9030 effect(KILL cr);
9031
9032 format %{ "OR $dst,$src" %}
9033 opcode(0x81,0x01); /* Opcode 81 /1 id */
9034 // ins_encode( RegImm( dst, src) );
9035 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9036 ins_pipe( ialu_reg );
9037 %}
9038
9039 // Or Register with Memory
9040 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9041 match(Set dst (OrI dst (LoadI src)));
9042 effect(KILL cr);
9043
9044 ins_cost(125);
9045 format %{ "OR $dst,$src" %}
9046 opcode(0x0B);
9047 ins_encode( OpcP, RegMem( dst, src) );
9048 ins_pipe( ialu_reg_mem );
9049 %}
9050
9051 // Or Memory with Register
9052 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9053 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9054 effect(KILL cr);
9055
9056 ins_cost(150);
9057 format %{ "OR $dst,$src" %}
9058 opcode(0x09); /* Opcode 09 /r */
9059 ins_encode( OpcP, RegMem( src, dst ) );
9060 ins_pipe( ialu_mem_reg );
9061 %}
9062
9063 // Or Memory with Immediate
9064 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9065 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9066 effect(KILL cr);
9067
9068 ins_cost(125);
9069 format %{ "OR $dst,$src" %}
9070 opcode(0x81,0x1); /* Opcode 81 /1 id */
9071 // ins_encode( MemImm( dst, src) );
9072 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9073 ins_pipe( ialu_mem_imm );
9074 %}
9075
9076 // ROL/ROR
9077 // ROL expand
9078 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9079 effect(USE_DEF dst, USE shift, KILL cr);
9080
9081 format %{ "ROL $dst, $shift" %}
9082 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9083 ins_encode( OpcP, RegOpc( dst ));
9084 ins_pipe( ialu_reg );
9085 %}
9086
9087 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9088 effect(USE_DEF dst, USE shift, KILL cr);
9089
9090 format %{ "ROL $dst, $shift" %}
9091 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9092 ins_encode( RegOpcImm(dst, shift) );
9093 ins_pipe(ialu_reg);
9094 %}
9095
9096 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9097 effect(USE_DEF dst, USE shift, KILL cr);
9098
9099 format %{ "ROL $dst, $shift" %}
9100 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9101 ins_encode(OpcP, RegOpc(dst));
9102 ins_pipe( ialu_reg_reg );
9103 %}
9104 // end of ROL expand
9105
9106 // ROL 32bit by one once
9107 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9108 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9109
9110 expand %{
9111 rolI_eReg_imm1(dst, lshift, cr);
9112 %}
9113 %}
9114
9115 // ROL 32bit var by imm8 once
9116 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9117 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9118 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9119
9120 expand %{
9121 rolI_eReg_imm8(dst, lshift, cr);
9122 %}
9123 %}
9124
9125 // ROL 32bit var by var once
9126 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9127 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9128
9129 expand %{
9130 rolI_eReg_CL(dst, shift, cr);
9131 %}
9132 %}
9133
9134 // ROL 32bit var by var once
9135 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9136 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9137
9138 expand %{
9139 rolI_eReg_CL(dst, shift, cr);
9140 %}
9141 %}
9142
9143 // ROR expand
9144 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9145 effect(USE_DEF dst, USE shift, KILL cr);
9146
9147 format %{ "ROR $dst, $shift" %}
9148 opcode(0xD1,0x1); /* Opcode D1 /1 */
9149 ins_encode( OpcP, RegOpc( dst ) );
9150 ins_pipe( ialu_reg );
9151 %}
9152
9153 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9154 effect (USE_DEF dst, USE shift, KILL cr);
9155
9156 format %{ "ROR $dst, $shift" %}
9157 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9158 ins_encode( RegOpcImm(dst, shift) );
9159 ins_pipe( ialu_reg );
9160 %}
9161
9162 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9163 effect(USE_DEF dst, USE shift, KILL cr);
9164
9165 format %{ "ROR $dst, $shift" %}
9166 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9167 ins_encode(OpcP, RegOpc(dst));
9168 ins_pipe( ialu_reg_reg );
9169 %}
9170 // end of ROR expand
9171
9172 // ROR right once
9173 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9174 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9175
9176 expand %{
9177 rorI_eReg_imm1(dst, rshift, cr);
9178 %}
9179 %}
9180
9181 // ROR 32bit by immI8 once
9182 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9183 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9184 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9185
9186 expand %{
9187 rorI_eReg_imm8(dst, rshift, cr);
9188 %}
9189 %}
9190
9191 // ROR 32bit var by var once
9192 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9193 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9194
9195 expand %{
9196 rorI_eReg_CL(dst, shift, cr);
9197 %}
9198 %}
9199
9200 // ROR 32bit var by var once
9201 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9202 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9203
9204 expand %{
9205 rorI_eReg_CL(dst, shift, cr);
9206 %}
9207 %}
9208
9209 // Xor Instructions
9210 // Xor Register with Register
9211 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9212 match(Set dst (XorI dst src));
9213 effect(KILL cr);
9214
9215 size(2);
9216 format %{ "XOR $dst,$src" %}
9217 opcode(0x33);
9218 ins_encode( OpcP, RegReg( dst, src) );
9219 ins_pipe( ialu_reg_reg );
9220 %}
9221
9222 // Xor Register with Immediate -1
9223 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9224 match(Set dst (XorI dst imm));
9225
9226 size(2);
9227 format %{ "NOT $dst" %}
9228 ins_encode %{
9229 __ notl($dst$$Register);
9230 %}
9231 ins_pipe( ialu_reg );
9232 %}
9233
9234 // Xor Register with Immediate
9235 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9236 match(Set dst (XorI dst src));
9237 effect(KILL cr);
9238
9239 format %{ "XOR $dst,$src" %}
9240 opcode(0x81,0x06); /* Opcode 81 /6 id */
9241 // ins_encode( RegImm( dst, src) );
9242 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9243 ins_pipe( ialu_reg );
9244 %}
9245
9246 // Xor Register with Memory
9247 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9248 match(Set dst (XorI dst (LoadI src)));
9249 effect(KILL cr);
9250
9251 ins_cost(125);
9252 format %{ "XOR $dst,$src" %}
9253 opcode(0x33);
9254 ins_encode( OpcP, RegMem(dst, src) );
9255 ins_pipe( ialu_reg_mem );
9256 %}
9257
9258 // Xor Memory with Register
9259 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9260 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9261 effect(KILL cr);
9262
9263 ins_cost(150);
9264 format %{ "XOR $dst,$src" %}
9265 opcode(0x31); /* Opcode 31 /r */
9266 ins_encode( OpcP, RegMem( src, dst ) );
9267 ins_pipe( ialu_mem_reg );
9268 %}
9269
9270 // Xor Memory with Immediate
9271 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9272 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9273 effect(KILL cr);
9274
9275 ins_cost(125);
9276 format %{ "XOR $dst,$src" %}
9277 opcode(0x81,0x6); /* Opcode 81 /6 id */
9278 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9279 ins_pipe( ialu_mem_imm );
9280 %}
9281
9282 //----------Convert Int to Boolean---------------------------------------------
9283
9284 instruct movI_nocopy(eRegI dst, eRegI src) %{
9285 effect( DEF dst, USE src );
9286 format %{ "MOV $dst,$src" %}
9287 ins_encode( enc_Copy( dst, src) );
9288 ins_pipe( ialu_reg_reg );
9289 %}
9290
9291 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9292 effect( USE_DEF dst, USE src, KILL cr );
9293
9294 size(4);
9295 format %{ "NEG $dst\n\t"
9296 "ADC $dst,$src" %}
9297 ins_encode( neg_reg(dst),
9298 OpcRegReg(0x13,dst,src) );
9299 ins_pipe( ialu_reg_reg_long );
9300 %}
9301
9302 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9303 match(Set dst (Conv2B src));
9304
9305 expand %{
9306 movI_nocopy(dst,src);
9307 ci2b(dst,src,cr);
9308 %}
9309 %}
9310
9311 instruct movP_nocopy(eRegI dst, eRegP src) %{
9312 effect( DEF dst, USE src );
9313 format %{ "MOV $dst,$src" %}
9314 ins_encode( enc_Copy( dst, src) );
9315 ins_pipe( ialu_reg_reg );
9316 %}
9317
9318 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9319 effect( USE_DEF dst, USE src, KILL cr );
9320 format %{ "NEG $dst\n\t"
9321 "ADC $dst,$src" %}
9322 ins_encode( neg_reg(dst),
9323 OpcRegReg(0x13,dst,src) );
9324 ins_pipe( ialu_reg_reg_long );
9325 %}
9326
9327 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9328 match(Set dst (Conv2B src));
9329
9330 expand %{
9331 movP_nocopy(dst,src);
9332 cp2b(dst,src,cr);
9333 %}
9334 %}
9335
9336 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9337 match(Set dst (CmpLTMask p q));
9338 effect( KILL cr );
9339 ins_cost(400);
9340
9341 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9342 format %{ "XOR $dst,$dst\n\t"
9343 "CMP $p,$q\n\t"
9344 "SETlt $dst\n\t"
9345 "NEG $dst" %}
9346 ins_encode( OpcRegReg(0x33,dst,dst),
9347 OpcRegReg(0x3B,p,q),
9348 setLT_reg(dst), neg_reg(dst) );
9349 ins_pipe( pipe_slow );
9350 %}
9351
9352 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9353 match(Set dst (CmpLTMask dst zero));
9354 effect( DEF dst, KILL cr );
9355 ins_cost(100);
9356
9357 format %{ "SAR $dst,31" %}
9358 opcode(0xC1, 0x7); /* C1 /7 ib */
9359 ins_encode( RegOpcImm( dst, 0x1F ) );
9360 ins_pipe( ialu_reg );
9361 %}
9362
9363
9364 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9365 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9366 effect( KILL tmp, KILL cr );
9367 ins_cost(400);
9368 // annoyingly, $tmp has no edges so you cant ask for it in
9369 // any format or encoding
9370 format %{ "SUB $p,$q\n\t"
9371 "SBB ECX,ECX\n\t"
9372 "AND ECX,$y\n\t"
9373 "ADD $p,ECX" %}
9374 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9375 ins_pipe( pipe_cmplt );
9376 %}
9377
9378 /* If I enable this, I encourage spilling in the inner loop of compress.
9379 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9380 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9381 effect( USE_KILL tmp, KILL cr );
9382 ins_cost(400);
9383
9384 format %{ "SUB $p,$q\n\t"
9385 "SBB ECX,ECX\n\t"
9386 "AND ECX,$y\n\t"
9387 "ADD $p,ECX" %}
9388 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9389 %}
9390 */
9391
9392 //----------Long Instructions------------------------------------------------
9393 // Add Long Register with Register
9394 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9395 match(Set dst (AddL dst src));
9396 effect(KILL cr);
9397 ins_cost(200);
9398 format %{ "ADD $dst.lo,$src.lo\n\t"
9399 "ADC $dst.hi,$src.hi" %}
9400 opcode(0x03, 0x13);
9401 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9402 ins_pipe( ialu_reg_reg_long );
9403 %}
9404
9405 // Add Long Register with Immediate
9406 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9407 match(Set dst (AddL dst src));
9408 effect(KILL cr);
9409 format %{ "ADD $dst.lo,$src.lo\n\t"
9410 "ADC $dst.hi,$src.hi" %}
9411 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9412 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9413 ins_pipe( ialu_reg_long );
9414 %}
9415
9416 // Add Long Register with Memory
9417 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9418 match(Set dst (AddL dst (LoadL mem)));
9419 effect(KILL cr);
9420 ins_cost(125);
9421 format %{ "ADD $dst.lo,$mem\n\t"
9422 "ADC $dst.hi,$mem+4" %}
9423 opcode(0x03, 0x13);
9424 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9425 ins_pipe( ialu_reg_long_mem );
9426 %}
9427
9428 // Subtract Long Register with Register.
9429 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9430 match(Set dst (SubL dst src));
9431 effect(KILL cr);
9432 ins_cost(200);
9433 format %{ "SUB $dst.lo,$src.lo\n\t"
9434 "SBB $dst.hi,$src.hi" %}
9435 opcode(0x2B, 0x1B);
9436 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9437 ins_pipe( ialu_reg_reg_long );
9438 %}
9439
9440 // Subtract Long Register with Immediate
9441 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9442 match(Set dst (SubL dst src));
9443 effect(KILL cr);
9444 format %{ "SUB $dst.lo,$src.lo\n\t"
9445 "SBB $dst.hi,$src.hi" %}
9446 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9447 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9448 ins_pipe( ialu_reg_long );
9449 %}
9450
9451 // Subtract Long Register with Memory
9452 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9453 match(Set dst (SubL dst (LoadL mem)));
9454 effect(KILL cr);
9455 ins_cost(125);
9456 format %{ "SUB $dst.lo,$mem\n\t"
9457 "SBB $dst.hi,$mem+4" %}
9458 opcode(0x2B, 0x1B);
9459 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9460 ins_pipe( ialu_reg_long_mem );
9461 %}
9462
9463 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9464 match(Set dst (SubL zero dst));
9465 effect(KILL cr);
9466 ins_cost(300);
9467 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9468 ins_encode( neg_long(dst) );
9469 ins_pipe( ialu_reg_reg_long );
9470 %}
9471
9472 // And Long Register with Register
9473 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9474 match(Set dst (AndL dst src));
9475 effect(KILL cr);
9476 format %{ "AND $dst.lo,$src.lo\n\t"
9477 "AND $dst.hi,$src.hi" %}
9478 opcode(0x23,0x23);
9479 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9480 ins_pipe( ialu_reg_reg_long );
9481 %}
9482
9483 // And Long Register with Immediate
9484 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9485 match(Set dst (AndL dst src));
9486 effect(KILL cr);
9487 format %{ "AND $dst.lo,$src.lo\n\t"
9488 "AND $dst.hi,$src.hi" %}
9489 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9490 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9491 ins_pipe( ialu_reg_long );
9492 %}
9493
9494 // And Long Register with Memory
9495 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9496 match(Set dst (AndL dst (LoadL mem)));
9497 effect(KILL cr);
9498 ins_cost(125);
9499 format %{ "AND $dst.lo,$mem\n\t"
9500 "AND $dst.hi,$mem+4" %}
9501 opcode(0x23, 0x23);
9502 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9503 ins_pipe( ialu_reg_long_mem );
9504 %}
9505
9506 // Or Long Register with Register
9507 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9508 match(Set dst (OrL dst src));
9509 effect(KILL cr);
9510 format %{ "OR $dst.lo,$src.lo\n\t"
9511 "OR $dst.hi,$src.hi" %}
9512 opcode(0x0B,0x0B);
9513 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9514 ins_pipe( ialu_reg_reg_long );
9515 %}
9516
9517 // Or Long Register with Immediate
9518 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9519 match(Set dst (OrL dst src));
9520 effect(KILL cr);
9521 format %{ "OR $dst.lo,$src.lo\n\t"
9522 "OR $dst.hi,$src.hi" %}
9523 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9524 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9525 ins_pipe( ialu_reg_long );
9526 %}
9527
9528 // Or Long Register with Memory
9529 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9530 match(Set dst (OrL dst (LoadL mem)));
9531 effect(KILL cr);
9532 ins_cost(125);
9533 format %{ "OR $dst.lo,$mem\n\t"
9534 "OR $dst.hi,$mem+4" %}
9535 opcode(0x0B,0x0B);
9536 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9537 ins_pipe( ialu_reg_long_mem );
9538 %}
9539
9540 // Xor Long Register with Register
9541 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9542 match(Set dst (XorL dst src));
9543 effect(KILL cr);
9544 format %{ "XOR $dst.lo,$src.lo\n\t"
9545 "XOR $dst.hi,$src.hi" %}
9546 opcode(0x33,0x33);
9547 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9548 ins_pipe( ialu_reg_reg_long );
9549 %}
9550
9551 // Xor Long Register with Immediate -1
9552 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9553 match(Set dst (XorL dst imm));
9554 format %{ "NOT $dst.lo\n\t"
9555 "NOT $dst.hi" %}
9556 ins_encode %{
9557 __ notl($dst$$Register);
9558 __ notl(HIGH_FROM_LOW($dst$$Register));
9559 %}
9560 ins_pipe( ialu_reg_long );
9561 %}
9562
9563 // Xor Long Register with Immediate
9564 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9565 match(Set dst (XorL dst src));
9566 effect(KILL cr);
9567 format %{ "XOR $dst.lo,$src.lo\n\t"
9568 "XOR $dst.hi,$src.hi" %}
9569 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9570 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9571 ins_pipe( ialu_reg_long );
9572 %}
9573
9574 // Xor Long Register with Memory
9575 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9576 match(Set dst (XorL dst (LoadL mem)));
9577 effect(KILL cr);
9578 ins_cost(125);
9579 format %{ "XOR $dst.lo,$mem\n\t"
9580 "XOR $dst.hi,$mem+4" %}
9581 opcode(0x33,0x33);
9582 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9583 ins_pipe( ialu_reg_long_mem );
9584 %}
9585
9586 // Shift Left Long by 1
9587 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9588 predicate(UseNewLongLShift);
9589 match(Set dst (LShiftL dst cnt));
9590 effect(KILL cr);
9591 ins_cost(100);
9592 format %{ "ADD $dst.lo,$dst.lo\n\t"
9593 "ADC $dst.hi,$dst.hi" %}
9594 ins_encode %{
9595 __ addl($dst$$Register,$dst$$Register);
9596 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9597 %}
9598 ins_pipe( ialu_reg_long );
9599 %}
9600
9601 // Shift Left Long by 2
9602 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9603 predicate(UseNewLongLShift);
9604 match(Set dst (LShiftL dst cnt));
9605 effect(KILL cr);
9606 ins_cost(100);
9607 format %{ "ADD $dst.lo,$dst.lo\n\t"
9608 "ADC $dst.hi,$dst.hi\n\t"
9609 "ADD $dst.lo,$dst.lo\n\t"
9610 "ADC $dst.hi,$dst.hi" %}
9611 ins_encode %{
9612 __ addl($dst$$Register,$dst$$Register);
9613 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9614 __ addl($dst$$Register,$dst$$Register);
9615 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9616 %}
9617 ins_pipe( ialu_reg_long );
9618 %}
9619
9620 // Shift Left Long by 3
9621 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9622 predicate(UseNewLongLShift);
9623 match(Set dst (LShiftL dst cnt));
9624 effect(KILL cr);
9625 ins_cost(100);
9626 format %{ "ADD $dst.lo,$dst.lo\n\t"
9627 "ADC $dst.hi,$dst.hi\n\t"
9628 "ADD $dst.lo,$dst.lo\n\t"
9629 "ADC $dst.hi,$dst.hi\n\t"
9630 "ADD $dst.lo,$dst.lo\n\t"
9631 "ADC $dst.hi,$dst.hi" %}
9632 ins_encode %{
9633 __ addl($dst$$Register,$dst$$Register);
9634 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9635 __ addl($dst$$Register,$dst$$Register);
9636 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9637 __ addl($dst$$Register,$dst$$Register);
9638 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9639 %}
9640 ins_pipe( ialu_reg_long );
9641 %}
9642
9643 // Shift Left Long by 1-31
9644 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9645 match(Set dst (LShiftL dst cnt));
9646 effect(KILL cr);
9647 ins_cost(200);
9648 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9649 "SHL $dst.lo,$cnt" %}
9650 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9651 ins_encode( move_long_small_shift(dst,cnt) );
9652 ins_pipe( ialu_reg_long );
9653 %}
9654
9655 // Shift Left Long by 32-63
9656 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9657 match(Set dst (LShiftL dst cnt));
9658 effect(KILL cr);
9659 ins_cost(300);
9660 format %{ "MOV $dst.hi,$dst.lo\n"
9661 "\tSHL $dst.hi,$cnt-32\n"
9662 "\tXOR $dst.lo,$dst.lo" %}
9663 opcode(0xC1, 0x4); /* C1 /4 ib */
9664 ins_encode( move_long_big_shift_clr(dst,cnt) );
9665 ins_pipe( ialu_reg_long );
9666 %}
9667
9668 // Shift Left Long by variable
9669 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9670 match(Set dst (LShiftL dst shift));
9671 effect(KILL cr);
9672 ins_cost(500+200);
9673 size(17);
9674 format %{ "TEST $shift,32\n\t"
9675 "JEQ,s small\n\t"
9676 "MOV $dst.hi,$dst.lo\n\t"
9677 "XOR $dst.lo,$dst.lo\n"
9678 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9679 "SHL $dst.lo,$shift" %}
9680 ins_encode( shift_left_long( dst, shift ) );
9681 ins_pipe( pipe_slow );
9682 %}
9683
9684 // Shift Right Long by 1-31
9685 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9686 match(Set dst (URShiftL dst cnt));
9687 effect(KILL cr);
9688 ins_cost(200);
9689 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9690 "SHR $dst.hi,$cnt" %}
9691 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9692 ins_encode( move_long_small_shift(dst,cnt) );
9693 ins_pipe( ialu_reg_long );
9694 %}
9695
9696 // Shift Right Long by 32-63
9697 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9698 match(Set dst (URShiftL dst cnt));
9699 effect(KILL cr);
9700 ins_cost(300);
9701 format %{ "MOV $dst.lo,$dst.hi\n"
9702 "\tSHR $dst.lo,$cnt-32\n"
9703 "\tXOR $dst.hi,$dst.hi" %}
9704 opcode(0xC1, 0x5); /* C1 /5 ib */
9705 ins_encode( move_long_big_shift_clr(dst,cnt) );
9706 ins_pipe( ialu_reg_long );
9707 %}
9708
9709 // Shift Right Long by variable
9710 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9711 match(Set dst (URShiftL dst shift));
9712 effect(KILL cr);
9713 ins_cost(600);
9714 size(17);
9715 format %{ "TEST $shift,32\n\t"
9716 "JEQ,s small\n\t"
9717 "MOV $dst.lo,$dst.hi\n\t"
9718 "XOR $dst.hi,$dst.hi\n"
9719 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9720 "SHR $dst.hi,$shift" %}
9721 ins_encode( shift_right_long( dst, shift ) );
9722 ins_pipe( pipe_slow );
9723 %}
9724
9725 // Shift Right Long by 1-31
9726 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9727 match(Set dst (RShiftL dst cnt));
9728 effect(KILL cr);
9729 ins_cost(200);
9730 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9731 "SAR $dst.hi,$cnt" %}
9732 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9733 ins_encode( move_long_small_shift(dst,cnt) );
9734 ins_pipe( ialu_reg_long );
9735 %}
9736
9737 // Shift Right Long by 32-63
9738 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9739 match(Set dst (RShiftL dst cnt));
9740 effect(KILL cr);
9741 ins_cost(300);
9742 format %{ "MOV $dst.lo,$dst.hi\n"
9743 "\tSAR $dst.lo,$cnt-32\n"
9744 "\tSAR $dst.hi,31" %}
9745 opcode(0xC1, 0x7); /* C1 /7 ib */
9746 ins_encode( move_long_big_shift_sign(dst,cnt) );
9747 ins_pipe( ialu_reg_long );
9748 %}
9749
9750 // Shift Right arithmetic Long by variable
9751 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9752 match(Set dst (RShiftL dst shift));
9753 effect(KILL cr);
9754 ins_cost(600);
9755 size(18);
9756 format %{ "TEST $shift,32\n\t"
9757 "JEQ,s small\n\t"
9758 "MOV $dst.lo,$dst.hi\n\t"
9759 "SAR $dst.hi,31\n"
9760 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9761 "SAR $dst.hi,$shift" %}
9762 ins_encode( shift_right_arith_long( dst, shift ) );
9763 ins_pipe( pipe_slow );
9764 %}
9765
9766
9767 //----------Double Instructions------------------------------------------------
9768 // Double Math
9769
9770 // Compare & branch
9771
9772 // P6 version of float compare, sets condition codes in EFLAGS
9773 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9774 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9775 match(Set cr (CmpD src1 src2));
9776 effect(KILL rax);
9777 ins_cost(150);
9778 format %{ "FLD $src1\n\t"
9779 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9780 "JNP exit\n\t"
9781 "MOV ah,1 // saw a NaN, set CF\n\t"
9782 "SAHF\n"
9783 "exit:\tNOP // avoid branch to branch" %}
9784 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9785 ins_encode( Push_Reg_D(src1),
9786 OpcP, RegOpc(src2),
9787 cmpF_P6_fixup );
9788 ins_pipe( pipe_slow );
9789 %}
9790
9791 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9792 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9793 match(Set cr (CmpD src1 src2));
9794 ins_cost(150);
9795 format %{ "FLD $src1\n\t"
9796 "FUCOMIP ST,$src2 // P6 instruction" %}
9797 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9798 ins_encode( Push_Reg_D(src1),
9799 OpcP, RegOpc(src2));
9800 ins_pipe( pipe_slow );
9801 %}
9802
9803 // Compare & branch
9804 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9805 predicate(UseSSE<=1);
9806 match(Set cr (CmpD src1 src2));
9807 effect(KILL rax);
9808 ins_cost(200);
9809 format %{ "FLD $src1\n\t"
9810 "FCOMp $src2\n\t"
9811 "FNSTSW AX\n\t"
9812 "TEST AX,0x400\n\t"
9813 "JZ,s flags\n\t"
9814 "MOV AH,1\t# unordered treat as LT\n"
9815 "flags:\tSAHF" %}
9816 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9817 ins_encode( Push_Reg_D(src1),
9818 OpcP, RegOpc(src2),
9819 fpu_flags);
9820 ins_pipe( pipe_slow );
9821 %}
9822
9823 // Compare vs zero into -1,0,1
9824 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9825 predicate(UseSSE<=1);
9826 match(Set dst (CmpD3 src1 zero));
9827 effect(KILL cr, KILL rax);
9828 ins_cost(280);
9829 format %{ "FTSTD $dst,$src1" %}
9830 opcode(0xE4, 0xD9);
9831 ins_encode( Push_Reg_D(src1),
9832 OpcS, OpcP, PopFPU,
9833 CmpF_Result(dst));
9834 ins_pipe( pipe_slow );
9835 %}
9836
9837 // Compare into -1,0,1
9838 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9839 predicate(UseSSE<=1);
9840 match(Set dst (CmpD3 src1 src2));
9841 effect(KILL cr, KILL rax);
9842 ins_cost(300);
9843 format %{ "FCMPD $dst,$src1,$src2" %}
9844 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9845 ins_encode( Push_Reg_D(src1),
9846 OpcP, RegOpc(src2),
9847 CmpF_Result(dst));
9848 ins_pipe( pipe_slow );
9849 %}
9850
9851 // float compare and set condition codes in EFLAGS by XMM regs
9852 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9853 predicate(UseSSE>=2);
9854 match(Set cr (CmpD dst src));
9855 effect(KILL rax);
9856 ins_cost(125);
9857 format %{ "COMISD $dst,$src\n"
9858 "\tJNP exit\n"
9859 "\tMOV ah,1 // saw a NaN, set CF\n"
9860 "\tSAHF\n"
9861 "exit:\tNOP // avoid branch to branch" %}
9862 opcode(0x66, 0x0F, 0x2F);
9863 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9864 ins_pipe( pipe_slow );
9865 %}
9866
9867 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9868 predicate(UseSSE>=2);
9869 match(Set cr (CmpD dst src));
9870 ins_cost(100);
9871 format %{ "COMISD $dst,$src" %}
9872 opcode(0x66, 0x0F, 0x2F);
9873 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9874 ins_pipe( pipe_slow );
9875 %}
9876
9877 // float compare and set condition codes in EFLAGS by XMM regs
9878 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9879 predicate(UseSSE>=2);
9880 match(Set cr (CmpD dst (LoadD src)));
9881 effect(KILL rax);
9882 ins_cost(145);
9883 format %{ "COMISD $dst,$src\n"
9884 "\tJNP exit\n"
9885 "\tMOV ah,1 // saw a NaN, set CF\n"
9886 "\tSAHF\n"
9887 "exit:\tNOP // avoid branch to branch" %}
9888 opcode(0x66, 0x0F, 0x2F);
9889 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9890 ins_pipe( pipe_slow );
9891 %}
9892
9893 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9894 predicate(UseSSE>=2);
9895 match(Set cr (CmpD dst (LoadD src)));
9896 ins_cost(100);
9897 format %{ "COMISD $dst,$src" %}
9898 opcode(0x66, 0x0F, 0x2F);
9899 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9900 ins_pipe( pipe_slow );
9901 %}
9902
9903 // Compare into -1,0,1 in XMM
9904 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9905 predicate(UseSSE>=2);
9906 match(Set dst (CmpD3 src1 src2));
9907 effect(KILL cr);
9908 ins_cost(255);
9909 format %{ "XOR $dst,$dst\n"
9910 "\tCOMISD $src1,$src2\n"
9911 "\tJP,s nan\n"
9912 "\tJEQ,s exit\n"
9913 "\tJA,s inc\n"
9914 "nan:\tDEC $dst\n"
9915 "\tJMP,s exit\n"
9916 "inc:\tINC $dst\n"
9917 "exit:"
9918 %}
9919 opcode(0x66, 0x0F, 0x2F);
9920 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9921 CmpX_Result(dst));
9922 ins_pipe( pipe_slow );
9923 %}
9924
9925 // Compare into -1,0,1 in XMM and memory
9926 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9927 predicate(UseSSE>=2);
9928 match(Set dst (CmpD3 src1 (LoadD mem)));
9929 effect(KILL cr);
9930 ins_cost(275);
9931 format %{ "COMISD $src1,$mem\n"
9932 "\tMOV $dst,0\t\t# do not blow flags\n"
9933 "\tJP,s nan\n"
9934 "\tJEQ,s exit\n"
9935 "\tJA,s inc\n"
9936 "nan:\tDEC $dst\n"
9937 "\tJMP,s exit\n"
9938 "inc:\tINC $dst\n"
9939 "exit:"
9940 %}
9941 opcode(0x66, 0x0F, 0x2F);
9942 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9943 LdImmI(dst,0x0), CmpX_Result(dst));
9944 ins_pipe( pipe_slow );
9945 %}
9946
9947
9948 instruct subD_reg(regD dst, regD src) %{
9949 predicate (UseSSE <=1);
9950 match(Set dst (SubD dst src));
9951
9952 format %{ "FLD $src\n\t"
9953 "DSUBp $dst,ST" %}
9954 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9955 ins_cost(150);
9956 ins_encode( Push_Reg_D(src),
9957 OpcP, RegOpc(dst) );
9958 ins_pipe( fpu_reg_reg );
9959 %}
9960
9961 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9962 predicate (UseSSE <=1);
9963 match(Set dst (RoundDouble (SubD src1 src2)));
9964 ins_cost(250);
9965
9966 format %{ "FLD $src2\n\t"
9967 "DSUB ST,$src1\n\t"
9968 "FSTP_D $dst\t# D-round" %}
9969 opcode(0xD8, 0x5);
9970 ins_encode( Push_Reg_D(src2),
9971 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9972 ins_pipe( fpu_mem_reg_reg );
9973 %}
9974
9975
9976 instruct subD_reg_mem(regD dst, memory src) %{
9977 predicate (UseSSE <=1);
9978 match(Set dst (SubD dst (LoadD src)));
9979 ins_cost(150);
9980
9981 format %{ "FLD $src\n\t"
9982 "DSUBp $dst,ST" %}
9983 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9984 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9985 OpcP, RegOpc(dst) );
9986 ins_pipe( fpu_reg_mem );
9987 %}
9988
9989 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9990 predicate (UseSSE<=1);
9991 match(Set dst (AbsD src));
9992 ins_cost(100);
9993 format %{ "FABS" %}
9994 opcode(0xE1, 0xD9);
9995 ins_encode( OpcS, OpcP );
9996 ins_pipe( fpu_reg_reg );
9997 %}
9998
9999 instruct absXD_reg( regXD dst ) %{
10000 predicate(UseSSE>=2);
10001 match(Set dst (AbsD dst));
10002 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10003 ins_encode( AbsXD_encoding(dst));
10004 ins_pipe( pipe_slow );
10005 %}
10006
10007 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10008 predicate(UseSSE<=1);
10009 match(Set dst (NegD src));
10010 ins_cost(100);
10011 format %{ "FCHS" %}
10012 opcode(0xE0, 0xD9);
10013 ins_encode( OpcS, OpcP );
10014 ins_pipe( fpu_reg_reg );
10015 %}
10016
10017 instruct negXD_reg( regXD dst ) %{
10018 predicate(UseSSE>=2);
10019 match(Set dst (NegD dst));
10020 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10021 ins_encode %{
10022 __ xorpd($dst$$XMMRegister,
10023 ExternalAddress((address)double_signflip_pool));
10024 %}
10025 ins_pipe( pipe_slow );
10026 %}
10027
10028 instruct addD_reg(regD dst, regD src) %{
10029 predicate(UseSSE<=1);
10030 match(Set dst (AddD dst src));
10031 format %{ "FLD $src\n\t"
10032 "DADD $dst,ST" %}
10033 size(4);
10034 ins_cost(150);
10035 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10036 ins_encode( Push_Reg_D(src),
10037 OpcP, RegOpc(dst) );
10038 ins_pipe( fpu_reg_reg );
10039 %}
10040
10041
10042 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10043 predicate(UseSSE<=1);
10044 match(Set dst (RoundDouble (AddD src1 src2)));
10045 ins_cost(250);
10046
10047 format %{ "FLD $src2\n\t"
10048 "DADD ST,$src1\n\t"
10049 "FSTP_D $dst\t# D-round" %}
10050 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10051 ins_encode( Push_Reg_D(src2),
10052 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10053 ins_pipe( fpu_mem_reg_reg );
10054 %}
10055
10056
10057 instruct addD_reg_mem(regD dst, memory src) %{
10058 predicate(UseSSE<=1);
10059 match(Set dst (AddD dst (LoadD src)));
10060 ins_cost(150);
10061
10062 format %{ "FLD $src\n\t"
10063 "DADDp $dst,ST" %}
10064 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10065 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10066 OpcP, RegOpc(dst) );
10067 ins_pipe( fpu_reg_mem );
10068 %}
10069
10070 // add-to-memory
10071 instruct addD_mem_reg(memory dst, regD src) %{
10072 predicate(UseSSE<=1);
10073 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10074 ins_cost(150);
10075
10076 format %{ "FLD_D $dst\n\t"
10077 "DADD ST,$src\n\t"
10078 "FST_D $dst" %}
10079 opcode(0xDD, 0x0);
10080 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10081 Opcode(0xD8), RegOpc(src),
10082 set_instruction_start,
10083 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10084 ins_pipe( fpu_reg_mem );
10085 %}
10086
10087 instruct addD_reg_imm1(regD dst, immD1 src) %{
10088 predicate(UseSSE<=1);
10089 match(Set dst (AddD dst src));
10090 ins_cost(125);
10091 format %{ "FLD1\n\t"
10092 "DADDp $dst,ST" %}
10093 opcode(0xDE, 0x00);
10094 ins_encode( LdImmD(src),
10095 OpcP, RegOpc(dst) );
10096 ins_pipe( fpu_reg );
10097 %}
10098
10099 instruct addD_reg_imm(regD dst, immD src) %{
10100 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10101 match(Set dst (AddD dst src));
10102 ins_cost(200);
10103 format %{ "FLD_D [$src]\n\t"
10104 "DADDp $dst,ST" %}
10105 opcode(0xDE, 0x00); /* DE /0 */
10106 ins_encode( LdImmD(src),
10107 OpcP, RegOpc(dst));
10108 ins_pipe( fpu_reg_mem );
10109 %}
10110
10111 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10112 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10113 match(Set dst (RoundDouble (AddD src con)));
10114 ins_cost(200);
10115 format %{ "FLD_D [$con]\n\t"
10116 "DADD ST,$src\n\t"
10117 "FSTP_D $dst\t# D-round" %}
10118 opcode(0xD8, 0x00); /* D8 /0 */
10119 ins_encode( LdImmD(con),
10120 OpcP, RegOpc(src), Pop_Mem_D(dst));
10121 ins_pipe( fpu_mem_reg_con );
10122 %}
10123
10124 // Add two double precision floating point values in xmm
10125 instruct addXD_reg(regXD dst, regXD src) %{
10126 predicate(UseSSE>=2);
10127 match(Set dst (AddD dst src));
10128 format %{ "ADDSD $dst,$src" %}
10129 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10130 ins_pipe( pipe_slow );
10131 %}
10132
10133 instruct addXD_imm(regXD dst, immXD con) %{
10134 predicate(UseSSE>=2);
10135 match(Set dst (AddD dst con));
10136 format %{ "ADDSD $dst,[$con]" %}
10137 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10138 ins_pipe( pipe_slow );
10139 %}
10140
10141 instruct addXD_mem(regXD dst, memory mem) %{
10142 predicate(UseSSE>=2);
10143 match(Set dst (AddD dst (LoadD mem)));
10144 format %{ "ADDSD $dst,$mem" %}
10145 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10146 ins_pipe( pipe_slow );
10147 %}
10148
10149 // Sub two double precision floating point values in xmm
10150 instruct subXD_reg(regXD dst, regXD src) %{
10151 predicate(UseSSE>=2);
10152 match(Set dst (SubD dst src));
10153 format %{ "SUBSD $dst,$src" %}
10154 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10155 ins_pipe( pipe_slow );
10156 %}
10157
10158 instruct subXD_imm(regXD dst, immXD con) %{
10159 predicate(UseSSE>=2);
10160 match(Set dst (SubD dst con));
10161 format %{ "SUBSD $dst,[$con]" %}
10162 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10163 ins_pipe( pipe_slow );
10164 %}
10165
10166 instruct subXD_mem(regXD dst, memory mem) %{
10167 predicate(UseSSE>=2);
10168 match(Set dst (SubD dst (LoadD mem)));
10169 format %{ "SUBSD $dst,$mem" %}
10170 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10171 ins_pipe( pipe_slow );
10172 %}
10173
10174 // Mul two double precision floating point values in xmm
10175 instruct mulXD_reg(regXD dst, regXD src) %{
10176 predicate(UseSSE>=2);
10177 match(Set dst (MulD dst src));
10178 format %{ "MULSD $dst,$src" %}
10179 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10180 ins_pipe( pipe_slow );
10181 %}
10182
10183 instruct mulXD_imm(regXD dst, immXD con) %{
10184 predicate(UseSSE>=2);
10185 match(Set dst (MulD dst con));
10186 format %{ "MULSD $dst,[$con]" %}
10187 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10188 ins_pipe( pipe_slow );
10189 %}
10190
10191 instruct mulXD_mem(regXD dst, memory mem) %{
10192 predicate(UseSSE>=2);
10193 match(Set dst (MulD dst (LoadD mem)));
10194 format %{ "MULSD $dst,$mem" %}
10195 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10196 ins_pipe( pipe_slow );
10197 %}
10198
10199 // Div two double precision floating point values in xmm
10200 instruct divXD_reg(regXD dst, regXD src) %{
10201 predicate(UseSSE>=2);
10202 match(Set dst (DivD dst src));
10203 format %{ "DIVSD $dst,$src" %}
10204 opcode(0xF2, 0x0F, 0x5E);
10205 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10206 ins_pipe( pipe_slow );
10207 %}
10208
10209 instruct divXD_imm(regXD dst, immXD con) %{
10210 predicate(UseSSE>=2);
10211 match(Set dst (DivD dst con));
10212 format %{ "DIVSD $dst,[$con]" %}
10213 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10214 ins_pipe( pipe_slow );
10215 %}
10216
10217 instruct divXD_mem(regXD dst, memory mem) %{
10218 predicate(UseSSE>=2);
10219 match(Set dst (DivD dst (LoadD mem)));
10220 format %{ "DIVSD $dst,$mem" %}
10221 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10222 ins_pipe( pipe_slow );
10223 %}
10224
10225
10226 instruct mulD_reg(regD dst, regD src) %{
10227 predicate(UseSSE<=1);
10228 match(Set dst (MulD dst src));
10229 format %{ "FLD $src\n\t"
10230 "DMULp $dst,ST" %}
10231 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10232 ins_cost(150);
10233 ins_encode( Push_Reg_D(src),
10234 OpcP, RegOpc(dst) );
10235 ins_pipe( fpu_reg_reg );
10236 %}
10237
10238 // Strict FP instruction biases argument before multiply then
10239 // biases result to avoid double rounding of subnormals.
10240 //
10241 // scale arg1 by multiplying arg1 by 2^(-15360)
10242 // load arg2
10243 // multiply scaled arg1 by arg2
10244 // rescale product by 2^(15360)
10245 //
10246 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10247 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10248 match(Set dst (MulD dst src));
10249 ins_cost(1); // Select this instruction for all strict FP double multiplies
10250
10251 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10252 "DMULp $dst,ST\n\t"
10253 "FLD $src\n\t"
10254 "DMULp $dst,ST\n\t"
10255 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10256 "DMULp $dst,ST\n\t" %}
10257 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10258 ins_encode( strictfp_bias1(dst),
10259 Push_Reg_D(src),
10260 OpcP, RegOpc(dst),
10261 strictfp_bias2(dst) );
10262 ins_pipe( fpu_reg_reg );
10263 %}
10264
10265 instruct mulD_reg_imm(regD dst, immD src) %{
10266 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10267 match(Set dst (MulD dst src));
10268 ins_cost(200);
10269 format %{ "FLD_D [$src]\n\t"
10270 "DMULp $dst,ST" %}
10271 opcode(0xDE, 0x1); /* DE /1 */
10272 ins_encode( LdImmD(src),
10273 OpcP, RegOpc(dst) );
10274 ins_pipe( fpu_reg_mem );
10275 %}
10276
10277
10278 instruct mulD_reg_mem(regD dst, memory src) %{
10279 predicate( UseSSE<=1 );
10280 match(Set dst (MulD dst (LoadD src)));
10281 ins_cost(200);
10282 format %{ "FLD_D $src\n\t"
10283 "DMULp $dst,ST" %}
10284 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10285 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10286 OpcP, RegOpc(dst) );
10287 ins_pipe( fpu_reg_mem );
10288 %}
10289
10290 //
10291 // Cisc-alternate to reg-reg multiply
10292 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10293 predicate( UseSSE<=1 );
10294 match(Set dst (MulD src (LoadD mem)));
10295 ins_cost(250);
10296 format %{ "FLD_D $mem\n\t"
10297 "DMUL ST,$src\n\t"
10298 "FSTP_D $dst" %}
10299 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10300 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10301 OpcReg_F(src),
10302 Pop_Reg_D(dst) );
10303 ins_pipe( fpu_reg_reg_mem );
10304 %}
10305
10306
10307 // MACRO3 -- addD a mulD
10308 // This instruction is a '2-address' instruction in that the result goes
10309 // back to src2. This eliminates a move from the macro; possibly the
10310 // register allocator will have to add it back (and maybe not).
10311 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10312 predicate( UseSSE<=1 );
10313 match(Set src2 (AddD (MulD src0 src1) src2));
10314 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10315 "DMUL ST,$src1\n\t"
10316 "DADDp $src2,ST" %}
10317 ins_cost(250);
10318 opcode(0xDD); /* LoadD DD /0 */
10319 ins_encode( Push_Reg_F(src0),
10320 FMul_ST_reg(src1),
10321 FAddP_reg_ST(src2) );
10322 ins_pipe( fpu_reg_reg_reg );
10323 %}
10324
10325
10326 // MACRO3 -- subD a mulD
10327 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10328 predicate( UseSSE<=1 );
10329 match(Set src2 (SubD (MulD src0 src1) src2));
10330 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10331 "DMUL ST,$src1\n\t"
10332 "DSUBRp $src2,ST" %}
10333 ins_cost(250);
10334 ins_encode( Push_Reg_F(src0),
10335 FMul_ST_reg(src1),
10336 Opcode(0xDE), Opc_plus(0xE0,src2));
10337 ins_pipe( fpu_reg_reg_reg );
10338 %}
10339
10340
10341 instruct divD_reg(regD dst, regD src) %{
10342 predicate( UseSSE<=1 );
10343 match(Set dst (DivD dst src));
10344
10345 format %{ "FLD $src\n\t"
10346 "FDIVp $dst,ST" %}
10347 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10348 ins_cost(150);
10349 ins_encode( Push_Reg_D(src),
10350 OpcP, RegOpc(dst) );
10351 ins_pipe( fpu_reg_reg );
10352 %}
10353
10354 // Strict FP instruction biases argument before division then
10355 // biases result, to avoid double rounding of subnormals.
10356 //
10357 // scale dividend by multiplying dividend by 2^(-15360)
10358 // load divisor
10359 // divide scaled dividend by divisor
10360 // rescale quotient by 2^(15360)
10361 //
10362 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10363 predicate (UseSSE<=1);
10364 match(Set dst (DivD dst src));
10365 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10366 ins_cost(01);
10367
10368 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10369 "DMULp $dst,ST\n\t"
10370 "FLD $src\n\t"
10371 "FDIVp $dst,ST\n\t"
10372 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10373 "DMULp $dst,ST\n\t" %}
10374 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10375 ins_encode( strictfp_bias1(dst),
10376 Push_Reg_D(src),
10377 OpcP, RegOpc(dst),
10378 strictfp_bias2(dst) );
10379 ins_pipe( fpu_reg_reg );
10380 %}
10381
10382 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10383 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10384 match(Set dst (RoundDouble (DivD src1 src2)));
10385
10386 format %{ "FLD $src1\n\t"
10387 "FDIV ST,$src2\n\t"
10388 "FSTP_D $dst\t# D-round" %}
10389 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10390 ins_encode( Push_Reg_D(src1),
10391 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10392 ins_pipe( fpu_mem_reg_reg );
10393 %}
10394
10395
10396 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10397 predicate(UseSSE<=1);
10398 match(Set dst (ModD dst src));
10399 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10400
10401 format %{ "DMOD $dst,$src" %}
10402 ins_cost(250);
10403 ins_encode(Push_Reg_Mod_D(dst, src),
10404 emitModD(),
10405 Push_Result_Mod_D(src),
10406 Pop_Reg_D(dst));
10407 ins_pipe( pipe_slow );
10408 %}
10409
10410 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10411 predicate(UseSSE>=2);
10412 match(Set dst (ModD src0 src1));
10413 effect(KILL rax, KILL cr);
10414
10415 format %{ "SUB ESP,8\t # DMOD\n"
10416 "\tMOVSD [ESP+0],$src1\n"
10417 "\tFLD_D [ESP+0]\n"
10418 "\tMOVSD [ESP+0],$src0\n"
10419 "\tFLD_D [ESP+0]\n"
10420 "loop:\tFPREM\n"
10421 "\tFWAIT\n"
10422 "\tFNSTSW AX\n"
10423 "\tSAHF\n"
10424 "\tJP loop\n"
10425 "\tFSTP_D [ESP+0]\n"
10426 "\tMOVSD $dst,[ESP+0]\n"
10427 "\tADD ESP,8\n"
10428 "\tFSTP ST0\t # Restore FPU Stack"
10429 %}
10430 ins_cost(250);
10431 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10432 ins_pipe( pipe_slow );
10433 %}
10434
10435 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10436 predicate (UseSSE<=1);
10437 match(Set dst (SinD src));
10438 ins_cost(1800);
10439 format %{ "DSIN $dst" %}
10440 opcode(0xD9, 0xFE);
10441 ins_encode( OpcP, OpcS );
10442 ins_pipe( pipe_slow );
10443 %}
10444
10445 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10446 predicate (UseSSE>=2);
10447 match(Set dst (SinD dst));
10448 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10449 ins_cost(1800);
10450 format %{ "DSIN $dst" %}
10451 opcode(0xD9, 0xFE);
10452 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10453 ins_pipe( pipe_slow );
10454 %}
10455
10456 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10457 predicate (UseSSE<=1);
10458 match(Set dst (CosD src));
10459 ins_cost(1800);
10460 format %{ "DCOS $dst" %}
10461 opcode(0xD9, 0xFF);
10462 ins_encode( OpcP, OpcS );
10463 ins_pipe( pipe_slow );
10464 %}
10465
10466 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10467 predicate (UseSSE>=2);
10468 match(Set dst (CosD dst));
10469 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10470 ins_cost(1800);
10471 format %{ "DCOS $dst" %}
10472 opcode(0xD9, 0xFF);
10473 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10474 ins_pipe( pipe_slow );
10475 %}
10476
10477 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10478 predicate (UseSSE<=1);
10479 match(Set dst(TanD src));
10480 format %{ "DTAN $dst" %}
10481 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10482 Opcode(0xDD), Opcode(0xD8)); // fstp st
10483 ins_pipe( pipe_slow );
10484 %}
10485
10486 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10487 predicate (UseSSE>=2);
10488 match(Set dst(TanD dst));
10489 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10490 format %{ "DTAN $dst" %}
10491 ins_encode( Push_SrcXD(dst),
10492 Opcode(0xD9), Opcode(0xF2), // fptan
10493 Opcode(0xDD), Opcode(0xD8), // fstp st
10494 Push_ResultXD(dst) );
10495 ins_pipe( pipe_slow );
10496 %}
10497
10498 instruct atanD_reg(regD dst, regD src) %{
10499 predicate (UseSSE<=1);
10500 match(Set dst(AtanD dst src));
10501 format %{ "DATA $dst,$src" %}
10502 opcode(0xD9, 0xF3);
10503 ins_encode( Push_Reg_D(src),
10504 OpcP, OpcS, RegOpc(dst) );
10505 ins_pipe( pipe_slow );
10506 %}
10507
10508 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10509 predicate (UseSSE>=2);
10510 match(Set dst(AtanD dst src));
10511 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10512 format %{ "DATA $dst,$src" %}
10513 opcode(0xD9, 0xF3);
10514 ins_encode( Push_SrcXD(src),
10515 OpcP, OpcS, Push_ResultXD(dst) );
10516 ins_pipe( pipe_slow );
10517 %}
10518
10519 instruct sqrtD_reg(regD dst, regD src) %{
10520 predicate (UseSSE<=1);
10521 match(Set dst (SqrtD src));
10522 format %{ "DSQRT $dst,$src" %}
10523 opcode(0xFA, 0xD9);
10524 ins_encode( Push_Reg_D(src),
10525 OpcS, OpcP, Pop_Reg_D(dst) );
10526 ins_pipe( pipe_slow );
10527 %}
10528
10529 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10530 predicate (UseSSE<=1);
10531 match(Set Y (PowD X Y)); // Raise X to the Yth power
10532 effect(KILL rax, KILL rbx, KILL rcx);
10533 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10534 "FLD_D $X\n\t"
10535 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10536
10537 "FDUP \t\t\t# Q Q\n\t"
10538 "FRNDINT\t\t\t# int(Q) Q\n\t"
10539 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10540 "FISTP dword [ESP]\n\t"
10541 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10542 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10543 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10544 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10545 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10546 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10547 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10548 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10549 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10550 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10551 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10552 "MOV [ESP+0],0\n\t"
10553 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10554
10555 "ADD ESP,8"
10556 %}
10557 ins_encode( push_stack_temp_qword,
10558 Push_Reg_D(X),
10559 Opcode(0xD9), Opcode(0xF1), // fyl2x
10560 pow_exp_core_encoding,
10561 pop_stack_temp_qword);
10562 ins_pipe( pipe_slow );
10563 %}
10564
10565 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10566 predicate (UseSSE>=2);
10567 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10568 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10569 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10570 "MOVSD [ESP],$src1\n\t"
10571 "FLD FPR1,$src1\n\t"
10572 "MOVSD [ESP],$src0\n\t"
10573 "FLD FPR1,$src0\n\t"
10574 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10575
10576 "FDUP \t\t\t# Q Q\n\t"
10577 "FRNDINT\t\t\t# int(Q) Q\n\t"
10578 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10579 "FISTP dword [ESP]\n\t"
10580 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10581 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10582 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10583 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10584 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10585 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10586 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10587 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10588 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10589 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10590 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10591 "MOV [ESP+0],0\n\t"
10592 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10593
10594 "FST_D [ESP]\n\t"
10595 "MOVSD $dst,[ESP]\n\t"
10596 "ADD ESP,8"
10597 %}
10598 ins_encode( push_stack_temp_qword,
10599 push_xmm_to_fpr1(src1),
10600 push_xmm_to_fpr1(src0),
10601 Opcode(0xD9), Opcode(0xF1), // fyl2x
10602 pow_exp_core_encoding,
10603 Push_ResultXD(dst) );
10604 ins_pipe( pipe_slow );
10605 %}
10606
10607
10608 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10609 predicate (UseSSE<=1);
10610 match(Set dpr1 (ExpD dpr1));
10611 effect(KILL rax, KILL rbx, KILL rcx);
10612 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10613 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10614 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10615
10616 "FDUP \t\t\t# Q Q\n\t"
10617 "FRNDINT\t\t\t# int(Q) Q\n\t"
10618 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10619 "FISTP dword [ESP]\n\t"
10620 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10621 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10622 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10623 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10624 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10625 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10626 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10627 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10628 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10629 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10630 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10631 "MOV [ESP+0],0\n\t"
10632 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10633
10634 "ADD ESP,8"
10635 %}
10636 ins_encode( push_stack_temp_qword,
10637 Opcode(0xD9), Opcode(0xEA), // fldl2e
10638 Opcode(0xDE), Opcode(0xC9), // fmulp
10639 pow_exp_core_encoding,
10640 pop_stack_temp_qword);
10641 ins_pipe( pipe_slow );
10642 %}
10643
10644 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10645 predicate (UseSSE>=2);
10646 match(Set dst (ExpD src));
10647 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10648 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10649 "MOVSD [ESP],$src\n\t"
10650 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10651 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10652
10653 "FDUP \t\t\t# Q Q\n\t"
10654 "FRNDINT\t\t\t# int(Q) Q\n\t"
10655 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10656 "FISTP dword [ESP]\n\t"
10657 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10658 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10659 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10660 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10661 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10662 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10663 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10664 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10665 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10666 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10667 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10668 "MOV [ESP+0],0\n\t"
10669 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10670
10671 "FST_D [ESP]\n\t"
10672 "MOVSD $dst,[ESP]\n\t"
10673 "ADD ESP,8"
10674 %}
10675 ins_encode( Push_SrcXD(src),
10676 Opcode(0xD9), Opcode(0xEA), // fldl2e
10677 Opcode(0xDE), Opcode(0xC9), // fmulp
10678 pow_exp_core_encoding,
10679 Push_ResultXD(dst) );
10680 ins_pipe( pipe_slow );
10681 %}
10682
10683
10684
10685 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10686 predicate (UseSSE<=1);
10687 // The source Double operand on FPU stack
10688 match(Set dst (Log10D src));
10689 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10690 // fxch ; swap ST(0) with ST(1)
10691 // fyl2x ; compute log_10(2) * log_2(x)
10692 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10693 "FXCH \n\t"
10694 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10695 %}
10696 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10697 Opcode(0xD9), Opcode(0xC9), // fxch
10698 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10699
10700 ins_pipe( pipe_slow );
10701 %}
10702
10703 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10704 predicate (UseSSE>=2);
10705 effect(KILL cr);
10706 match(Set dst (Log10D src));
10707 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10708 // fyl2x ; compute log_10(2) * log_2(x)
10709 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10710 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10711 %}
10712 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10713 Push_SrcXD(src),
10714 Opcode(0xD9), Opcode(0xF1), // fyl2x
10715 Push_ResultXD(dst));
10716
10717 ins_pipe( pipe_slow );
10718 %}
10719
10720 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10721 predicate (UseSSE<=1);
10722 // The source Double operand on FPU stack
10723 match(Set dst (LogD src));
10724 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10725 // fxch ; swap ST(0) with ST(1)
10726 // fyl2x ; compute log_e(2) * log_2(x)
10727 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10728 "FXCH \n\t"
10729 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10730 %}
10731 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10732 Opcode(0xD9), Opcode(0xC9), // fxch
10733 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10734
10735 ins_pipe( pipe_slow );
10736 %}
10737
10738 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10739 predicate (UseSSE>=2);
10740 effect(KILL cr);
10741 // The source and result Double operands in XMM registers
10742 match(Set dst (LogD src));
10743 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10744 // fyl2x ; compute log_e(2) * log_2(x)
10745 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10746 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10747 %}
10748 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10749 Push_SrcXD(src),
10750 Opcode(0xD9), Opcode(0xF1), // fyl2x
10751 Push_ResultXD(dst));
10752 ins_pipe( pipe_slow );
10753 %}
10754
10755 //-------------Float Instructions-------------------------------
10756 // Float Math
10757
10758 // Code for float compare:
10759 // fcompp();
10760 // fwait(); fnstsw_ax();
10761 // sahf();
10762 // movl(dst, unordered_result);
10763 // jcc(Assembler::parity, exit);
10764 // movl(dst, less_result);
10765 // jcc(Assembler::below, exit);
10766 // movl(dst, equal_result);
10767 // jcc(Assembler::equal, exit);
10768 // movl(dst, greater_result);
10769 // exit:
10770
10771 // P6 version of float compare, sets condition codes in EFLAGS
10772 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10773 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10774 match(Set cr (CmpF src1 src2));
10775 effect(KILL rax);
10776 ins_cost(150);
10777 format %{ "FLD $src1\n\t"
10778 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10779 "JNP exit\n\t"
10780 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10781 "SAHF\n"
10782 "exit:\tNOP // avoid branch to branch" %}
10783 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10784 ins_encode( Push_Reg_D(src1),
10785 OpcP, RegOpc(src2),
10786 cmpF_P6_fixup );
10787 ins_pipe( pipe_slow );
10788 %}
10789
10790 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10791 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10792 match(Set cr (CmpF src1 src2));
10793 ins_cost(100);
10794 format %{ "FLD $src1\n\t"
10795 "FUCOMIP ST,$src2 // P6 instruction" %}
10796 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10797 ins_encode( Push_Reg_D(src1),
10798 OpcP, RegOpc(src2));
10799 ins_pipe( pipe_slow );
10800 %}
10801
10802
10803 // Compare & branch
10804 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10805 predicate(UseSSE == 0);
10806 match(Set cr (CmpF src1 src2));
10807 effect(KILL rax);
10808 ins_cost(200);
10809 format %{ "FLD $src1\n\t"
10810 "FCOMp $src2\n\t"
10811 "FNSTSW AX\n\t"
10812 "TEST AX,0x400\n\t"
10813 "JZ,s flags\n\t"
10814 "MOV AH,1\t# unordered treat as LT\n"
10815 "flags:\tSAHF" %}
10816 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10817 ins_encode( Push_Reg_D(src1),
10818 OpcP, RegOpc(src2),
10819 fpu_flags);
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823 // Compare vs zero into -1,0,1
10824 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10825 predicate(UseSSE == 0);
10826 match(Set dst (CmpF3 src1 zero));
10827 effect(KILL cr, KILL rax);
10828 ins_cost(280);
10829 format %{ "FTSTF $dst,$src1" %}
10830 opcode(0xE4, 0xD9);
10831 ins_encode( Push_Reg_D(src1),
10832 OpcS, OpcP, PopFPU,
10833 CmpF_Result(dst));
10834 ins_pipe( pipe_slow );
10835 %}
10836
10837 // Compare into -1,0,1
10838 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10839 predicate(UseSSE == 0);
10840 match(Set dst (CmpF3 src1 src2));
10841 effect(KILL cr, KILL rax);
10842 ins_cost(300);
10843 format %{ "FCMPF $dst,$src1,$src2" %}
10844 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10845 ins_encode( Push_Reg_D(src1),
10846 OpcP, RegOpc(src2),
10847 CmpF_Result(dst));
10848 ins_pipe( pipe_slow );
10849 %}
10850
10851 // float compare and set condition codes in EFLAGS by XMM regs
10852 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10853 predicate(UseSSE>=1);
10854 match(Set cr (CmpF dst src));
10855 effect(KILL rax);
10856 ins_cost(145);
10857 format %{ "COMISS $dst,$src\n"
10858 "\tJNP exit\n"
10859 "\tMOV ah,1 // saw a NaN, set CF\n"
10860 "\tSAHF\n"
10861 "exit:\tNOP // avoid branch to branch" %}
10862 opcode(0x0F, 0x2F);
10863 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10864 ins_pipe( pipe_slow );
10865 %}
10866
10867 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10868 predicate(UseSSE>=1);
10869 match(Set cr (CmpF dst src));
10870 ins_cost(100);
10871 format %{ "COMISS $dst,$src" %}
10872 opcode(0x0F, 0x2F);
10873 ins_encode(OpcP, OpcS, RegReg(dst, src));
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 // float compare and set condition codes in EFLAGS by XMM regs
10878 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10879 predicate(UseSSE>=1);
10880 match(Set cr (CmpF dst (LoadF src)));
10881 effect(KILL rax);
10882 ins_cost(165);
10883 format %{ "COMISS $dst,$src\n"
10884 "\tJNP exit\n"
10885 "\tMOV ah,1 // saw a NaN, set CF\n"
10886 "\tSAHF\n"
10887 "exit:\tNOP // avoid branch to branch" %}
10888 opcode(0x0F, 0x2F);
10889 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10890 ins_pipe( pipe_slow );
10891 %}
10892
10893 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10894 predicate(UseSSE>=1);
10895 match(Set cr (CmpF dst (LoadF src)));
10896 ins_cost(100);
10897 format %{ "COMISS $dst,$src" %}
10898 opcode(0x0F, 0x2F);
10899 ins_encode(OpcP, OpcS, RegMem(dst, src));
10900 ins_pipe( pipe_slow );
10901 %}
10902
10903 // Compare into -1,0,1 in XMM
10904 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10905 predicate(UseSSE>=1);
10906 match(Set dst (CmpF3 src1 src2));
10907 effect(KILL cr);
10908 ins_cost(255);
10909 format %{ "XOR $dst,$dst\n"
10910 "\tCOMISS $src1,$src2\n"
10911 "\tJP,s nan\n"
10912 "\tJEQ,s exit\n"
10913 "\tJA,s inc\n"
10914 "nan:\tDEC $dst\n"
10915 "\tJMP,s exit\n"
10916 "inc:\tINC $dst\n"
10917 "exit:"
10918 %}
10919 opcode(0x0F, 0x2F);
10920 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 // Compare into -1,0,1 in XMM and memory
10925 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10926 predicate(UseSSE>=1);
10927 match(Set dst (CmpF3 src1 (LoadF mem)));
10928 effect(KILL cr);
10929 ins_cost(275);
10930 format %{ "COMISS $src1,$mem\n"
10931 "\tMOV $dst,0\t\t# do not blow flags\n"
10932 "\tJP,s nan\n"
10933 "\tJEQ,s exit\n"
10934 "\tJA,s inc\n"
10935 "nan:\tDEC $dst\n"
10936 "\tJMP,s exit\n"
10937 "inc:\tINC $dst\n"
10938 "exit:"
10939 %}
10940 opcode(0x0F, 0x2F);
10941 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10942 ins_pipe( pipe_slow );
10943 %}
10944
10945 // Spill to obtain 24-bit precision
10946 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10947 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10948 match(Set dst (SubF src1 src2));
10949
10950 format %{ "FSUB $dst,$src1 - $src2" %}
10951 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10952 ins_encode( Push_Reg_F(src1),
10953 OpcReg_F(src2),
10954 Pop_Mem_F(dst) );
10955 ins_pipe( fpu_mem_reg_reg );
10956 %}
10957 //
10958 // This instruction does not round to 24-bits
10959 instruct subF_reg(regF dst, regF src) %{
10960 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10961 match(Set dst (SubF dst src));
10962
10963 format %{ "FSUB $dst,$src" %}
10964 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10965 ins_encode( Push_Reg_F(src),
10966 OpcP, RegOpc(dst) );
10967 ins_pipe( fpu_reg_reg );
10968 %}
10969
10970 // Spill to obtain 24-bit precision
10971 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10972 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10973 match(Set dst (AddF src1 src2));
10974
10975 format %{ "FADD $dst,$src1,$src2" %}
10976 opcode(0xD8, 0x0); /* D8 C0+i */
10977 ins_encode( Push_Reg_F(src2),
10978 OpcReg_F(src1),
10979 Pop_Mem_F(dst) );
10980 ins_pipe( fpu_mem_reg_reg );
10981 %}
10982 //
10983 // This instruction does not round to 24-bits
10984 instruct addF_reg(regF dst, regF src) %{
10985 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10986 match(Set dst (AddF dst src));
10987
10988 format %{ "FLD $src\n\t"
10989 "FADDp $dst,ST" %}
10990 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10991 ins_encode( Push_Reg_F(src),
10992 OpcP, RegOpc(dst) );
10993 ins_pipe( fpu_reg_reg );
10994 %}
10995
10996 // Add two single precision floating point values in xmm
10997 instruct addX_reg(regX dst, regX src) %{
10998 predicate(UseSSE>=1);
10999 match(Set dst (AddF dst src));
11000 format %{ "ADDSS $dst,$src" %}
11001 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11002 ins_pipe( pipe_slow );
11003 %}
11004
11005 instruct addX_imm(regX dst, immXF con) %{
11006 predicate(UseSSE>=1);
11007 match(Set dst (AddF dst con));
11008 format %{ "ADDSS $dst,[$con]" %}
11009 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11010 ins_pipe( pipe_slow );
11011 %}
11012
11013 instruct addX_mem(regX dst, memory mem) %{
11014 predicate(UseSSE>=1);
11015 match(Set dst (AddF dst (LoadF mem)));
11016 format %{ "ADDSS $dst,$mem" %}
11017 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11018 ins_pipe( pipe_slow );
11019 %}
11020
11021 // Subtract two single precision floating point values in xmm
11022 instruct subX_reg(regX dst, regX src) %{
11023 predicate(UseSSE>=1);
11024 match(Set dst (SubF dst src));
11025 format %{ "SUBSS $dst,$src" %}
11026 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 instruct subX_imm(regX dst, immXF con) %{
11031 predicate(UseSSE>=1);
11032 match(Set dst (SubF dst con));
11033 format %{ "SUBSS $dst,[$con]" %}
11034 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11035 ins_pipe( pipe_slow );
11036 %}
11037
11038 instruct subX_mem(regX dst, memory mem) %{
11039 predicate(UseSSE>=1);
11040 match(Set dst (SubF dst (LoadF mem)));
11041 format %{ "SUBSS $dst,$mem" %}
11042 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11043 ins_pipe( pipe_slow );
11044 %}
11045
11046 // Multiply two single precision floating point values in xmm
11047 instruct mulX_reg(regX dst, regX src) %{
11048 predicate(UseSSE>=1);
11049 match(Set dst (MulF dst src));
11050 format %{ "MULSS $dst,$src" %}
11051 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11052 ins_pipe( pipe_slow );
11053 %}
11054
11055 instruct mulX_imm(regX dst, immXF con) %{
11056 predicate(UseSSE>=1);
11057 match(Set dst (MulF dst con));
11058 format %{ "MULSS $dst,[$con]" %}
11059 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11060 ins_pipe( pipe_slow );
11061 %}
11062
11063 instruct mulX_mem(regX dst, memory mem) %{
11064 predicate(UseSSE>=1);
11065 match(Set dst (MulF dst (LoadF mem)));
11066 format %{ "MULSS $dst,$mem" %}
11067 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11068 ins_pipe( pipe_slow );
11069 %}
11070
11071 // Divide two single precision floating point values in xmm
11072 instruct divX_reg(regX dst, regX src) %{
11073 predicate(UseSSE>=1);
11074 match(Set dst (DivF dst src));
11075 format %{ "DIVSS $dst,$src" %}
11076 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11077 ins_pipe( pipe_slow );
11078 %}
11079
11080 instruct divX_imm(regX dst, immXF con) %{
11081 predicate(UseSSE>=1);
11082 match(Set dst (DivF dst con));
11083 format %{ "DIVSS $dst,[$con]" %}
11084 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11085 ins_pipe( pipe_slow );
11086 %}
11087
11088 instruct divX_mem(regX dst, memory mem) %{
11089 predicate(UseSSE>=1);
11090 match(Set dst (DivF dst (LoadF mem)));
11091 format %{ "DIVSS $dst,$mem" %}
11092 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11093 ins_pipe( pipe_slow );
11094 %}
11095
11096 // Get the square root of a single precision floating point values in xmm
11097 instruct sqrtX_reg(regX dst, regX src) %{
11098 predicate(UseSSE>=1);
11099 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11100 format %{ "SQRTSS $dst,$src" %}
11101 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11102 ins_pipe( pipe_slow );
11103 %}
11104
11105 instruct sqrtX_mem(regX dst, memory mem) %{
11106 predicate(UseSSE>=1);
11107 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11108 format %{ "SQRTSS $dst,$mem" %}
11109 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11110 ins_pipe( pipe_slow );
11111 %}
11112
11113 // Get the square root of a double precision floating point values in xmm
11114 instruct sqrtXD_reg(regXD dst, regXD src) %{
11115 predicate(UseSSE>=2);
11116 match(Set dst (SqrtD src));
11117 format %{ "SQRTSD $dst,$src" %}
11118 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11119 ins_pipe( pipe_slow );
11120 %}
11121
11122 instruct sqrtXD_mem(regXD dst, memory mem) %{
11123 predicate(UseSSE>=2);
11124 match(Set dst (SqrtD (LoadD mem)));
11125 format %{ "SQRTSD $dst,$mem" %}
11126 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11127 ins_pipe( pipe_slow );
11128 %}
11129
11130 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11131 predicate(UseSSE==0);
11132 match(Set dst (AbsF src));
11133 ins_cost(100);
11134 format %{ "FABS" %}
11135 opcode(0xE1, 0xD9);
11136 ins_encode( OpcS, OpcP );
11137 ins_pipe( fpu_reg_reg );
11138 %}
11139
11140 instruct absX_reg(regX dst ) %{
11141 predicate(UseSSE>=1);
11142 match(Set dst (AbsF dst));
11143 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11144 ins_encode( AbsXF_encoding(dst));
11145 ins_pipe( pipe_slow );
11146 %}
11147
11148 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11149 predicate(UseSSE==0);
11150 match(Set dst (NegF src));
11151 ins_cost(100);
11152 format %{ "FCHS" %}
11153 opcode(0xE0, 0xD9);
11154 ins_encode( OpcS, OpcP );
11155 ins_pipe( fpu_reg_reg );
11156 %}
11157
11158 instruct negX_reg( regX dst ) %{
11159 predicate(UseSSE>=1);
11160 match(Set dst (NegF dst));
11161 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11162 ins_encode( NegXF_encoding(dst));
11163 ins_pipe( pipe_slow );
11164 %}
11165
11166 // Cisc-alternate to addF_reg
11167 // Spill to obtain 24-bit precision
11168 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11169 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11170 match(Set dst (AddF src1 (LoadF src2)));
11171
11172 format %{ "FLD $src2\n\t"
11173 "FADD ST,$src1\n\t"
11174 "FSTP_S $dst" %}
11175 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11176 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11177 OpcReg_F(src1),
11178 Pop_Mem_F(dst) );
11179 ins_pipe( fpu_mem_reg_mem );
11180 %}
11181 //
11182 // Cisc-alternate to addF_reg
11183 // This instruction does not round to 24-bits
11184 instruct addF_reg_mem(regF dst, memory src) %{
11185 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11186 match(Set dst (AddF dst (LoadF src)));
11187
11188 format %{ "FADD $dst,$src" %}
11189 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11190 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11191 OpcP, RegOpc(dst) );
11192 ins_pipe( fpu_reg_mem );
11193 %}
11194
11195 // // Following two instructions for _222_mpegaudio
11196 // Spill to obtain 24-bit precision
11197 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11198 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11199 match(Set dst (AddF src1 src2));
11200
11201 format %{ "FADD $dst,$src1,$src2" %}
11202 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11203 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11204 OpcReg_F(src2),
11205 Pop_Mem_F(dst) );
11206 ins_pipe( fpu_mem_reg_mem );
11207 %}
11208
11209 // Cisc-spill variant
11210 // Spill to obtain 24-bit precision
11211 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11212 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11213 match(Set dst (AddF src1 (LoadF src2)));
11214
11215 format %{ "FADD $dst,$src1,$src2 cisc" %}
11216 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11217 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11218 set_instruction_start,
11219 OpcP, RMopc_Mem(secondary,src1),
11220 Pop_Mem_F(dst) );
11221 ins_pipe( fpu_mem_mem_mem );
11222 %}
11223
11224 // Spill to obtain 24-bit precision
11225 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11226 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11227 match(Set dst (AddF src1 src2));
11228
11229 format %{ "FADD $dst,$src1,$src2" %}
11230 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11231 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11232 set_instruction_start,
11233 OpcP, RMopc_Mem(secondary,src1),
11234 Pop_Mem_F(dst) );
11235 ins_pipe( fpu_mem_mem_mem );
11236 %}
11237
11238
11239 // Spill to obtain 24-bit precision
11240 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11241 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11242 match(Set dst (AddF src1 src2));
11243 format %{ "FLD $src1\n\t"
11244 "FADD $src2\n\t"
11245 "FSTP_S $dst" %}
11246 opcode(0xD8, 0x00); /* D8 /0 */
11247 ins_encode( Push_Reg_F(src1),
11248 Opc_MemImm_F(src2),
11249 Pop_Mem_F(dst));
11250 ins_pipe( fpu_mem_reg_con );
11251 %}
11252 //
11253 // This instruction does not round to 24-bits
11254 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11255 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11256 match(Set dst (AddF src1 src2));
11257 format %{ "FLD $src1\n\t"
11258 "FADD $src2\n\t"
11259 "FSTP_S $dst" %}
11260 opcode(0xD8, 0x00); /* D8 /0 */
11261 ins_encode( Push_Reg_F(src1),
11262 Opc_MemImm_F(src2),
11263 Pop_Reg_F(dst));
11264 ins_pipe( fpu_reg_reg_con );
11265 %}
11266
11267 // Spill to obtain 24-bit precision
11268 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11269 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11270 match(Set dst (MulF src1 src2));
11271
11272 format %{ "FLD $src1\n\t"
11273 "FMUL $src2\n\t"
11274 "FSTP_S $dst" %}
11275 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11276 ins_encode( Push_Reg_F(src1),
11277 OpcReg_F(src2),
11278 Pop_Mem_F(dst) );
11279 ins_pipe( fpu_mem_reg_reg );
11280 %}
11281 //
11282 // This instruction does not round to 24-bits
11283 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11284 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11285 match(Set dst (MulF src1 src2));
11286
11287 format %{ "FLD $src1\n\t"
11288 "FMUL $src2\n\t"
11289 "FSTP_S $dst" %}
11290 opcode(0xD8, 0x1); /* D8 C8+i */
11291 ins_encode( Push_Reg_F(src2),
11292 OpcReg_F(src1),
11293 Pop_Reg_F(dst) );
11294 ins_pipe( fpu_reg_reg_reg );
11295 %}
11296
11297
11298 // Spill to obtain 24-bit precision
11299 // Cisc-alternate to reg-reg multiply
11300 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11301 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11302 match(Set dst (MulF src1 (LoadF src2)));
11303
11304 format %{ "FLD_S $src2\n\t"
11305 "FMUL $src1\n\t"
11306 "FSTP_S $dst" %}
11307 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11308 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11309 OpcReg_F(src1),
11310 Pop_Mem_F(dst) );
11311 ins_pipe( fpu_mem_reg_mem );
11312 %}
11313 //
11314 // This instruction does not round to 24-bits
11315 // Cisc-alternate to reg-reg multiply
11316 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11317 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11318 match(Set dst (MulF src1 (LoadF src2)));
11319
11320 format %{ "FMUL $dst,$src1,$src2" %}
11321 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11322 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11323 OpcReg_F(src1),
11324 Pop_Reg_F(dst) );
11325 ins_pipe( fpu_reg_reg_mem );
11326 %}
11327
11328 // Spill to obtain 24-bit precision
11329 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11330 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11331 match(Set dst (MulF src1 src2));
11332
11333 format %{ "FMUL $dst,$src1,$src2" %}
11334 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11335 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11336 set_instruction_start,
11337 OpcP, RMopc_Mem(secondary,src1),
11338 Pop_Mem_F(dst) );
11339 ins_pipe( fpu_mem_mem_mem );
11340 %}
11341
11342 // Spill to obtain 24-bit precision
11343 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11344 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11345 match(Set dst (MulF src1 src2));
11346
11347 format %{ "FMULc $dst,$src1,$src2" %}
11348 opcode(0xD8, 0x1); /* D8 /1*/
11349 ins_encode( Push_Reg_F(src1),
11350 Opc_MemImm_F(src2),
11351 Pop_Mem_F(dst));
11352 ins_pipe( fpu_mem_reg_con );
11353 %}
11354 //
11355 // This instruction does not round to 24-bits
11356 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11357 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11358 match(Set dst (MulF src1 src2));
11359
11360 format %{ "FMULc $dst. $src1, $src2" %}
11361 opcode(0xD8, 0x1); /* D8 /1*/
11362 ins_encode( Push_Reg_F(src1),
11363 Opc_MemImm_F(src2),
11364 Pop_Reg_F(dst));
11365 ins_pipe( fpu_reg_reg_con );
11366 %}
11367
11368
11369 //
11370 // MACRO1 -- subsume unshared load into mulF
11371 // This instruction does not round to 24-bits
11372 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11373 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11374 match(Set dst (MulF (LoadF mem1) src));
11375
11376 format %{ "FLD $mem1 ===MACRO1===\n\t"
11377 "FMUL ST,$src\n\t"
11378 "FSTP $dst" %}
11379 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11380 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11381 OpcReg_F(src),
11382 Pop_Reg_F(dst) );
11383 ins_pipe( fpu_reg_reg_mem );
11384 %}
11385 //
11386 // MACRO2 -- addF a mulF which subsumed an unshared load
11387 // This instruction does not round to 24-bits
11388 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11389 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11390 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11391 ins_cost(95);
11392
11393 format %{ "FLD $mem1 ===MACRO2===\n\t"
11394 "FMUL ST,$src1 subsume mulF left load\n\t"
11395 "FADD ST,$src2\n\t"
11396 "FSTP $dst" %}
11397 opcode(0xD9); /* LoadF D9 /0 */
11398 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11399 FMul_ST_reg(src1),
11400 FAdd_ST_reg(src2),
11401 Pop_Reg_F(dst) );
11402 ins_pipe( fpu_reg_mem_reg_reg );
11403 %}
11404
11405 // MACRO3 -- addF a mulF
11406 // This instruction does not round to 24-bits. It is a '2-address'
11407 // instruction in that the result goes back to src2. This eliminates
11408 // a move from the macro; possibly the register allocator will have
11409 // to add it back (and maybe not).
11410 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11411 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11412 match(Set src2 (AddF (MulF src0 src1) src2));
11413
11414 format %{ "FLD $src0 ===MACRO3===\n\t"
11415 "FMUL ST,$src1\n\t"
11416 "FADDP $src2,ST" %}
11417 opcode(0xD9); /* LoadF D9 /0 */
11418 ins_encode( Push_Reg_F(src0),
11419 FMul_ST_reg(src1),
11420 FAddP_reg_ST(src2) );
11421 ins_pipe( fpu_reg_reg_reg );
11422 %}
11423
11424 // MACRO4 -- divF subF
11425 // This instruction does not round to 24-bits
11426 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11427 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11428 match(Set dst (DivF (SubF src2 src1) src3));
11429
11430 format %{ "FLD $src2 ===MACRO4===\n\t"
11431 "FSUB ST,$src1\n\t"
11432 "FDIV ST,$src3\n\t"
11433 "FSTP $dst" %}
11434 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11435 ins_encode( Push_Reg_F(src2),
11436 subF_divF_encode(src1,src3),
11437 Pop_Reg_F(dst) );
11438 ins_pipe( fpu_reg_reg_reg_reg );
11439 %}
11440
11441 // Spill to obtain 24-bit precision
11442 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11443 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11444 match(Set dst (DivF src1 src2));
11445
11446 format %{ "FDIV $dst,$src1,$src2" %}
11447 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11448 ins_encode( Push_Reg_F(src1),
11449 OpcReg_F(src2),
11450 Pop_Mem_F(dst) );
11451 ins_pipe( fpu_mem_reg_reg );
11452 %}
11453 //
11454 // This instruction does not round to 24-bits
11455 instruct divF_reg(regF dst, regF src) %{
11456 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11457 match(Set dst (DivF dst src));
11458
11459 format %{ "FDIV $dst,$src" %}
11460 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11461 ins_encode( Push_Reg_F(src),
11462 OpcP, RegOpc(dst) );
11463 ins_pipe( fpu_reg_reg );
11464 %}
11465
11466
11467 // Spill to obtain 24-bit precision
11468 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11469 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11470 match(Set dst (ModF src1 src2));
11471 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11472
11473 format %{ "FMOD $dst,$src1,$src2" %}
11474 ins_encode( Push_Reg_Mod_D(src1, src2),
11475 emitModD(),
11476 Push_Result_Mod_D(src2),
11477 Pop_Mem_F(dst));
11478 ins_pipe( pipe_slow );
11479 %}
11480 //
11481 // This instruction does not round to 24-bits
11482 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11483 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11484 match(Set dst (ModF dst src));
11485 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11486
11487 format %{ "FMOD $dst,$src" %}
11488 ins_encode(Push_Reg_Mod_D(dst, src),
11489 emitModD(),
11490 Push_Result_Mod_D(src),
11491 Pop_Reg_F(dst));
11492 ins_pipe( pipe_slow );
11493 %}
11494
11495 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11496 predicate(UseSSE>=1);
11497 match(Set dst (ModF src0 src1));
11498 effect(KILL rax, KILL cr);
11499 format %{ "SUB ESP,4\t # FMOD\n"
11500 "\tMOVSS [ESP+0],$src1\n"
11501 "\tFLD_S [ESP+0]\n"
11502 "\tMOVSS [ESP+0],$src0\n"
11503 "\tFLD_S [ESP+0]\n"
11504 "loop:\tFPREM\n"
11505 "\tFWAIT\n"
11506 "\tFNSTSW AX\n"
11507 "\tSAHF\n"
11508 "\tJP loop\n"
11509 "\tFSTP_S [ESP+0]\n"
11510 "\tMOVSS $dst,[ESP+0]\n"
11511 "\tADD ESP,4\n"
11512 "\tFSTP ST0\t # Restore FPU Stack"
11513 %}
11514 ins_cost(250);
11515 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11516 ins_pipe( pipe_slow );
11517 %}
11518
11519
11520 //----------Arithmetic Conversion Instructions---------------------------------
11521 // The conversions operations are all Alpha sorted. Please keep it that way!
11522
11523 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11524 predicate(UseSSE==0);
11525 match(Set dst (RoundFloat src));
11526 ins_cost(125);
11527 format %{ "FST_S $dst,$src\t# F-round" %}
11528 ins_encode( Pop_Mem_Reg_F(dst, src) );
11529 ins_pipe( fpu_mem_reg );
11530 %}
11531
11532 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11533 predicate(UseSSE<=1);
11534 match(Set dst (RoundDouble src));
11535 ins_cost(125);
11536 format %{ "FST_D $dst,$src\t# D-round" %}
11537 ins_encode( Pop_Mem_Reg_D(dst, src) );
11538 ins_pipe( fpu_mem_reg );
11539 %}
11540
11541 // Force rounding to 24-bit precision and 6-bit exponent
11542 instruct convD2F_reg(stackSlotF dst, regD src) %{
11543 predicate(UseSSE==0);
11544 match(Set dst (ConvD2F src));
11545 format %{ "FST_S $dst,$src\t# F-round" %}
11546 expand %{
11547 roundFloat_mem_reg(dst,src);
11548 %}
11549 %}
11550
11551 // Force rounding to 24-bit precision and 6-bit exponent
11552 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11553 predicate(UseSSE==1);
11554 match(Set dst (ConvD2F src));
11555 effect( KILL cr );
11556 format %{ "SUB ESP,4\n\t"
11557 "FST_S [ESP],$src\t# F-round\n\t"
11558 "MOVSS $dst,[ESP]\n\t"
11559 "ADD ESP,4" %}
11560 ins_encode( D2X_encoding(dst, src) );
11561 ins_pipe( pipe_slow );
11562 %}
11563
11564 // Force rounding double precision to single precision
11565 instruct convXD2X_reg(regX dst, regXD src) %{
11566 predicate(UseSSE>=2);
11567 match(Set dst (ConvD2F src));
11568 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11569 opcode(0xF2, 0x0F, 0x5A);
11570 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11571 ins_pipe( pipe_slow );
11572 %}
11573
11574 instruct convF2D_reg_reg(regD dst, regF src) %{
11575 predicate(UseSSE==0);
11576 match(Set dst (ConvF2D src));
11577 format %{ "FST_S $dst,$src\t# D-round" %}
11578 ins_encode( Pop_Reg_Reg_D(dst, src));
11579 ins_pipe( fpu_reg_reg );
11580 %}
11581
11582 instruct convF2D_reg(stackSlotD dst, regF src) %{
11583 predicate(UseSSE==1);
11584 match(Set dst (ConvF2D src));
11585 format %{ "FST_D $dst,$src\t# D-round" %}
11586 expand %{
11587 roundDouble_mem_reg(dst,src);
11588 %}
11589 %}
11590
11591 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11592 predicate(UseSSE==1);
11593 match(Set dst (ConvF2D src));
11594 effect( KILL cr );
11595 format %{ "SUB ESP,4\n\t"
11596 "MOVSS [ESP] $src\n\t"
11597 "FLD_S [ESP]\n\t"
11598 "ADD ESP,4\n\t"
11599 "FSTP $dst\t# D-round" %}
11600 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11601 ins_pipe( pipe_slow );
11602 %}
11603
11604 instruct convX2XD_reg(regXD dst, regX src) %{
11605 predicate(UseSSE>=2);
11606 match(Set dst (ConvF2D src));
11607 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11608 opcode(0xF3, 0x0F, 0x5A);
11609 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11610 ins_pipe( pipe_slow );
11611 %}
11612
11613 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11614 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11615 predicate(UseSSE<=1);
11616 match(Set dst (ConvD2I src));
11617 effect( KILL tmp, KILL cr );
11618 format %{ "FLD $src\t# Convert double to int \n\t"
11619 "FLDCW trunc mode\n\t"
11620 "SUB ESP,4\n\t"
11621 "FISTp [ESP + #0]\n\t"
11622 "FLDCW std/24-bit mode\n\t"
11623 "POP EAX\n\t"
11624 "CMP EAX,0x80000000\n\t"
11625 "JNE,s fast\n\t"
11626 "FLD_D $src\n\t"
11627 "CALL d2i_wrapper\n"
11628 "fast:" %}
11629 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11630 ins_pipe( pipe_slow );
11631 %}
11632
11633 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11634 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11635 predicate(UseSSE>=2);
11636 match(Set dst (ConvD2I src));
11637 effect( KILL tmp, KILL cr );
11638 format %{ "CVTTSD2SI $dst, $src\n\t"
11639 "CMP $dst,0x80000000\n\t"
11640 "JNE,s fast\n\t"
11641 "SUB ESP, 8\n\t"
11642 "MOVSD [ESP], $src\n\t"
11643 "FLD_D [ESP]\n\t"
11644 "ADD ESP, 8\n\t"
11645 "CALL d2i_wrapper\n"
11646 "fast:" %}
11647 opcode(0x1); // double-precision conversion
11648 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11649 ins_pipe( pipe_slow );
11650 %}
11651
11652 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11653 predicate(UseSSE<=1);
11654 match(Set dst (ConvD2L src));
11655 effect( KILL cr );
11656 format %{ "FLD $src\t# Convert double to long\n\t"
11657 "FLDCW trunc mode\n\t"
11658 "SUB ESP,8\n\t"
11659 "FISTp [ESP + #0]\n\t"
11660 "FLDCW std/24-bit mode\n\t"
11661 "POP EAX\n\t"
11662 "POP EDX\n\t"
11663 "CMP EDX,0x80000000\n\t"
11664 "JNE,s fast\n\t"
11665 "TEST EAX,EAX\n\t"
11666 "JNE,s fast\n\t"
11667 "FLD $src\n\t"
11668 "CALL d2l_wrapper\n"
11669 "fast:" %}
11670 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11671 ins_pipe( pipe_slow );
11672 %}
11673
11674 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11675 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11676 predicate (UseSSE>=2);
11677 match(Set dst (ConvD2L src));
11678 effect( KILL cr );
11679 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11680 "MOVSD [ESP],$src\n\t"
11681 "FLD_D [ESP]\n\t"
11682 "FLDCW trunc mode\n\t"
11683 "FISTp [ESP + #0]\n\t"
11684 "FLDCW std/24-bit mode\n\t"
11685 "POP EAX\n\t"
11686 "POP EDX\n\t"
11687 "CMP EDX,0x80000000\n\t"
11688 "JNE,s fast\n\t"
11689 "TEST EAX,EAX\n\t"
11690 "JNE,s fast\n\t"
11691 "SUB ESP,8\n\t"
11692 "MOVSD [ESP],$src\n\t"
11693 "FLD_D [ESP]\n\t"
11694 "CALL d2l_wrapper\n"
11695 "fast:" %}
11696 ins_encode( XD2L_encoding(src) );
11697 ins_pipe( pipe_slow );
11698 %}
11699
11700 // Convert a double to an int. Java semantics require we do complex
11701 // manglations in the corner cases. So we set the rounding mode to
11702 // 'zero', store the darned double down as an int, and reset the
11703 // rounding mode to 'nearest'. The hardware stores a flag value down
11704 // if we would overflow or converted a NAN; we check for this and
11705 // and go the slow path if needed.
11706 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11707 predicate(UseSSE==0);
11708 match(Set dst (ConvF2I src));
11709 effect( KILL tmp, KILL cr );
11710 format %{ "FLD $src\t# Convert float to int \n\t"
11711 "FLDCW trunc mode\n\t"
11712 "SUB ESP,4\n\t"
11713 "FISTp [ESP + #0]\n\t"
11714 "FLDCW std/24-bit mode\n\t"
11715 "POP EAX\n\t"
11716 "CMP EAX,0x80000000\n\t"
11717 "JNE,s fast\n\t"
11718 "FLD $src\n\t"
11719 "CALL d2i_wrapper\n"
11720 "fast:" %}
11721 // D2I_encoding works for F2I
11722 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11723 ins_pipe( pipe_slow );
11724 %}
11725
11726 // Convert a float in xmm to an int reg.
11727 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11728 predicate(UseSSE>=1);
11729 match(Set dst (ConvF2I src));
11730 effect( KILL tmp, KILL cr );
11731 format %{ "CVTTSS2SI $dst, $src\n\t"
11732 "CMP $dst,0x80000000\n\t"
11733 "JNE,s fast\n\t"
11734 "SUB ESP, 4\n\t"
11735 "MOVSS [ESP], $src\n\t"
11736 "FLD [ESP]\n\t"
11737 "ADD ESP, 4\n\t"
11738 "CALL d2i_wrapper\n"
11739 "fast:" %}
11740 opcode(0x0); // single-precision conversion
11741 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11742 ins_pipe( pipe_slow );
11743 %}
11744
11745 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11746 predicate(UseSSE==0);
11747 match(Set dst (ConvF2L src));
11748 effect( KILL cr );
11749 format %{ "FLD $src\t# Convert float to long\n\t"
11750 "FLDCW trunc mode\n\t"
11751 "SUB ESP,8\n\t"
11752 "FISTp [ESP + #0]\n\t"
11753 "FLDCW std/24-bit mode\n\t"
11754 "POP EAX\n\t"
11755 "POP EDX\n\t"
11756 "CMP EDX,0x80000000\n\t"
11757 "JNE,s fast\n\t"
11758 "TEST EAX,EAX\n\t"
11759 "JNE,s fast\n\t"
11760 "FLD $src\n\t"
11761 "CALL d2l_wrapper\n"
11762 "fast:" %}
11763 // D2L_encoding works for F2L
11764 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11765 ins_pipe( pipe_slow );
11766 %}
11767
11768 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11769 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11770 predicate (UseSSE>=1);
11771 match(Set dst (ConvF2L src));
11772 effect( KILL cr );
11773 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11774 "MOVSS [ESP],$src\n\t"
11775 "FLD_S [ESP]\n\t"
11776 "FLDCW trunc mode\n\t"
11777 "FISTp [ESP + #0]\n\t"
11778 "FLDCW std/24-bit mode\n\t"
11779 "POP EAX\n\t"
11780 "POP EDX\n\t"
11781 "CMP EDX,0x80000000\n\t"
11782 "JNE,s fast\n\t"
11783 "TEST EAX,EAX\n\t"
11784 "JNE,s fast\n\t"
11785 "SUB ESP,4\t# Convert float to long\n\t"
11786 "MOVSS [ESP],$src\n\t"
11787 "FLD_S [ESP]\n\t"
11788 "ADD ESP,4\n\t"
11789 "CALL d2l_wrapper\n"
11790 "fast:" %}
11791 ins_encode( X2L_encoding(src) );
11792 ins_pipe( pipe_slow );
11793 %}
11794
11795 instruct convI2D_reg(regD dst, stackSlotI src) %{
11796 predicate( UseSSE<=1 );
11797 match(Set dst (ConvI2D src));
11798 format %{ "FILD $src\n\t"
11799 "FSTP $dst" %}
11800 opcode(0xDB, 0x0); /* DB /0 */
11801 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11802 ins_pipe( fpu_reg_mem );
11803 %}
11804
11805 instruct convI2XD_reg(regXD dst, eRegI src) %{
11806 predicate( UseSSE>=2 && !UseXmmI2D );
11807 match(Set dst (ConvI2D src));
11808 format %{ "CVTSI2SD $dst,$src" %}
11809 opcode(0xF2, 0x0F, 0x2A);
11810 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11811 ins_pipe( pipe_slow );
11812 %}
11813
11814 instruct convI2XD_mem(regXD dst, memory mem) %{
11815 predicate( UseSSE>=2 );
11816 match(Set dst (ConvI2D (LoadI mem)));
11817 format %{ "CVTSI2SD $dst,$mem" %}
11818 opcode(0xF2, 0x0F, 0x2A);
11819 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11820 ins_pipe( pipe_slow );
11821 %}
11822
11823 instruct convXI2XD_reg(regXD dst, eRegI src)
11824 %{
11825 predicate( UseSSE>=2 && UseXmmI2D );
11826 match(Set dst (ConvI2D src));
11827
11828 format %{ "MOVD $dst,$src\n\t"
11829 "CVTDQ2PD $dst,$dst\t# i2d" %}
11830 ins_encode %{
11831 __ movdl($dst$$XMMRegister, $src$$Register);
11832 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11833 %}
11834 ins_pipe(pipe_slow); // XXX
11835 %}
11836
11837 instruct convI2D_mem(regD dst, memory mem) %{
11838 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11839 match(Set dst (ConvI2D (LoadI mem)));
11840 format %{ "FILD $mem\n\t"
11841 "FSTP $dst" %}
11842 opcode(0xDB); /* DB /0 */
11843 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11844 Pop_Reg_D(dst));
11845 ins_pipe( fpu_reg_mem );
11846 %}
11847
11848 // Convert a byte to a float; no rounding step needed.
11849 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11850 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11851 match(Set dst (ConvI2F src));
11852 format %{ "FILD $src\n\t"
11853 "FSTP $dst" %}
11854
11855 opcode(0xDB, 0x0); /* DB /0 */
11856 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11857 ins_pipe( fpu_reg_mem );
11858 %}
11859
11860 // In 24-bit mode, force exponent rounding by storing back out
11861 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11862 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11863 match(Set dst (ConvI2F src));
11864 ins_cost(200);
11865 format %{ "FILD $src\n\t"
11866 "FSTP_S $dst" %}
11867 opcode(0xDB, 0x0); /* DB /0 */
11868 ins_encode( Push_Mem_I(src),
11869 Pop_Mem_F(dst));
11870 ins_pipe( fpu_mem_mem );
11871 %}
11872
11873 // In 24-bit mode, force exponent rounding by storing back out
11874 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11875 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11876 match(Set dst (ConvI2F (LoadI mem)));
11877 ins_cost(200);
11878 format %{ "FILD $mem\n\t"
11879 "FSTP_S $dst" %}
11880 opcode(0xDB); /* DB /0 */
11881 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11882 Pop_Mem_F(dst));
11883 ins_pipe( fpu_mem_mem );
11884 %}
11885
11886 // This instruction does not round to 24-bits
11887 instruct convI2F_reg(regF dst, stackSlotI src) %{
11888 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11889 match(Set dst (ConvI2F src));
11890 format %{ "FILD $src\n\t"
11891 "FSTP $dst" %}
11892 opcode(0xDB, 0x0); /* DB /0 */
11893 ins_encode( Push_Mem_I(src),
11894 Pop_Reg_F(dst));
11895 ins_pipe( fpu_reg_mem );
11896 %}
11897
11898 // This instruction does not round to 24-bits
11899 instruct convI2F_mem(regF dst, memory mem) %{
11900 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11901 match(Set dst (ConvI2F (LoadI mem)));
11902 format %{ "FILD $mem\n\t"
11903 "FSTP $dst" %}
11904 opcode(0xDB); /* DB /0 */
11905 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11906 Pop_Reg_F(dst));
11907 ins_pipe( fpu_reg_mem );
11908 %}
11909
11910 // Convert an int to a float in xmm; no rounding step needed.
11911 instruct convI2X_reg(regX dst, eRegI src) %{
11912 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11913 match(Set dst (ConvI2F src));
11914 format %{ "CVTSI2SS $dst, $src" %}
11915
11916 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11917 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11918 ins_pipe( pipe_slow );
11919 %}
11920
11921 instruct convXI2X_reg(regX dst, eRegI src)
11922 %{
11923 predicate( UseSSE>=2 && UseXmmI2F );
11924 match(Set dst (ConvI2F src));
11925
11926 format %{ "MOVD $dst,$src\n\t"
11927 "CVTDQ2PS $dst,$dst\t# i2f" %}
11928 ins_encode %{
11929 __ movdl($dst$$XMMRegister, $src$$Register);
11930 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11931 %}
11932 ins_pipe(pipe_slow); // XXX
11933 %}
11934
11935 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11936 match(Set dst (ConvI2L src));
11937 effect(KILL cr);
11938 ins_cost(375);
11939 format %{ "MOV $dst.lo,$src\n\t"
11940 "MOV $dst.hi,$src\n\t"
11941 "SAR $dst.hi,31" %}
11942 ins_encode(convert_int_long(dst,src));
11943 ins_pipe( ialu_reg_reg_long );
11944 %}
11945
11946 // Zero-extend convert int to long
11947 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11948 match(Set dst (AndL (ConvI2L src) mask) );
11949 effect( KILL flags );
11950 ins_cost(250);
11951 format %{ "MOV $dst.lo,$src\n\t"
11952 "XOR $dst.hi,$dst.hi" %}
11953 opcode(0x33); // XOR
11954 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11955 ins_pipe( ialu_reg_reg_long );
11956 %}
11957
11958 // Zero-extend long
11959 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11960 match(Set dst (AndL src mask) );
11961 effect( KILL flags );
11962 ins_cost(250);
11963 format %{ "MOV $dst.lo,$src.lo\n\t"
11964 "XOR $dst.hi,$dst.hi\n\t" %}
11965 opcode(0x33); // XOR
11966 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11967 ins_pipe( ialu_reg_reg_long );
11968 %}
11969
11970 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11971 predicate (UseSSE<=1);
11972 match(Set dst (ConvL2D src));
11973 effect( KILL cr );
11974 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11975 "PUSH $src.lo\n\t"
11976 "FILD ST,[ESP + #0]\n\t"
11977 "ADD ESP,8\n\t"
11978 "FSTP_D $dst\t# D-round" %}
11979 opcode(0xDF, 0x5); /* DF /5 */
11980 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11981 ins_pipe( pipe_slow );
11982 %}
11983
11984 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11985 predicate (UseSSE>=2);
11986 match(Set dst (ConvL2D src));
11987 effect( KILL cr );
11988 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11989 "PUSH $src.lo\n\t"
11990 "FILD_D [ESP]\n\t"
11991 "FSTP_D [ESP]\n\t"
11992 "MOVSD $dst,[ESP]\n\t"
11993 "ADD ESP,8" %}
11994 opcode(0xDF, 0x5); /* DF /5 */
11995 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11996 ins_pipe( pipe_slow );
11997 %}
11998
11999 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12000 predicate (UseSSE>=1);
12001 match(Set dst (ConvL2F src));
12002 effect( KILL cr );
12003 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12004 "PUSH $src.lo\n\t"
12005 "FILD_D [ESP]\n\t"
12006 "FSTP_S [ESP]\n\t"
12007 "MOVSS $dst,[ESP]\n\t"
12008 "ADD ESP,8" %}
12009 opcode(0xDF, 0x5); /* DF /5 */
12010 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12011 ins_pipe( pipe_slow );
12012 %}
12013
12014 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12015 match(Set dst (ConvL2F src));
12016 effect( KILL cr );
12017 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12018 "PUSH $src.lo\n\t"
12019 "FILD ST,[ESP + #0]\n\t"
12020 "ADD ESP,8\n\t"
12021 "FSTP_S $dst\t# F-round" %}
12022 opcode(0xDF, 0x5); /* DF /5 */
12023 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12024 ins_pipe( pipe_slow );
12025 %}
12026
12027 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12028 match(Set dst (ConvL2I src));
12029 effect( DEF dst, USE src );
12030 format %{ "MOV $dst,$src.lo" %}
12031 ins_encode(enc_CopyL_Lo(dst,src));
12032 ins_pipe( ialu_reg_reg );
12033 %}
12034
12035
12036 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12037 match(Set dst (MoveF2I src));
12038 effect( DEF dst, USE src );
12039 ins_cost(100);
12040 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12041 opcode(0x8B);
12042 ins_encode( OpcP, RegMem(dst,src));
12043 ins_pipe( ialu_reg_mem );
12044 %}
12045
12046 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12047 predicate(UseSSE==0);
12048 match(Set dst (MoveF2I src));
12049 effect( DEF dst, USE src );
12050
12051 ins_cost(125);
12052 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12053 ins_encode( Pop_Mem_Reg_F(dst, src) );
12054 ins_pipe( fpu_mem_reg );
12055 %}
12056
12057 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12058 predicate(UseSSE>=1);
12059 match(Set dst (MoveF2I src));
12060 effect( DEF dst, USE src );
12061
12062 ins_cost(95);
12063 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12064 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12065 ins_pipe( pipe_slow );
12066 %}
12067
12068 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12069 predicate(UseSSE>=2);
12070 match(Set dst (MoveF2I src));
12071 effect( DEF dst, USE src );
12072 ins_cost(85);
12073 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12074 ins_encode( MovX2I_reg(dst, src));
12075 ins_pipe( pipe_slow );
12076 %}
12077
12078 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12079 match(Set dst (MoveI2F src));
12080 effect( DEF dst, USE src );
12081
12082 ins_cost(100);
12083 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12084 opcode(0x89);
12085 ins_encode( OpcPRegSS( dst, src ) );
12086 ins_pipe( ialu_mem_reg );
12087 %}
12088
12089
12090 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12091 predicate(UseSSE==0);
12092 match(Set dst (MoveI2F src));
12093 effect(DEF dst, USE src);
12094
12095 ins_cost(125);
12096 format %{ "FLD_S $src\n\t"
12097 "FSTP $dst\t# MoveI2F_stack_reg" %}
12098 opcode(0xD9); /* D9 /0, FLD m32real */
12099 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12100 Pop_Reg_F(dst) );
12101 ins_pipe( fpu_reg_mem );
12102 %}
12103
12104 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12105 predicate(UseSSE>=1);
12106 match(Set dst (MoveI2F src));
12107 effect( DEF dst, USE src );
12108
12109 ins_cost(95);
12110 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12111 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12112 ins_pipe( pipe_slow );
12113 %}
12114
12115 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12116 predicate(UseSSE>=2);
12117 match(Set dst (MoveI2F src));
12118 effect( DEF dst, USE src );
12119
12120 ins_cost(85);
12121 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12122 ins_encode( MovI2X_reg(dst, src) );
12123 ins_pipe( pipe_slow );
12124 %}
12125
12126 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12127 match(Set dst (MoveD2L src));
12128 effect(DEF dst, USE src);
12129
12130 ins_cost(250);
12131 format %{ "MOV $dst.lo,$src\n\t"
12132 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12133 opcode(0x8B, 0x8B);
12134 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12135 ins_pipe( ialu_mem_long_reg );
12136 %}
12137
12138 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12139 predicate(UseSSE<=1);
12140 match(Set dst (MoveD2L src));
12141 effect(DEF dst, USE src);
12142
12143 ins_cost(125);
12144 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12145 ins_encode( Pop_Mem_Reg_D(dst, src) );
12146 ins_pipe( fpu_mem_reg );
12147 %}
12148
12149 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12150 predicate(UseSSE>=2);
12151 match(Set dst (MoveD2L src));
12152 effect(DEF dst, USE src);
12153 ins_cost(95);
12154
12155 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12156 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12157 ins_pipe( pipe_slow );
12158 %}
12159
12160 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12161 predicate(UseSSE>=2);
12162 match(Set dst (MoveD2L src));
12163 effect(DEF dst, USE src, TEMP tmp);
12164 ins_cost(85);
12165 format %{ "MOVD $dst.lo,$src\n\t"
12166 "PSHUFLW $tmp,$src,0x4E\n\t"
12167 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12168 ins_encode( MovXD2L_reg(dst, src, tmp) );
12169 ins_pipe( pipe_slow );
12170 %}
12171
12172 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12173 match(Set dst (MoveL2D src));
12174 effect(DEF dst, USE src);
12175
12176 ins_cost(200);
12177 format %{ "MOV $dst,$src.lo\n\t"
12178 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12179 opcode(0x89, 0x89);
12180 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12181 ins_pipe( ialu_mem_long_reg );
12182 %}
12183
12184
12185 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12186 predicate(UseSSE<=1);
12187 match(Set dst (MoveL2D src));
12188 effect(DEF dst, USE src);
12189 ins_cost(125);
12190
12191 format %{ "FLD_D $src\n\t"
12192 "FSTP $dst\t# MoveL2D_stack_reg" %}
12193 opcode(0xDD); /* DD /0, FLD m64real */
12194 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12195 Pop_Reg_D(dst) );
12196 ins_pipe( fpu_reg_mem );
12197 %}
12198
12199
12200 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12201 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12202 match(Set dst (MoveL2D src));
12203 effect(DEF dst, USE src);
12204
12205 ins_cost(95);
12206 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12207 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12208 ins_pipe( pipe_slow );
12209 %}
12210
12211 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12212 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12213 match(Set dst (MoveL2D src));
12214 effect(DEF dst, USE src);
12215
12216 ins_cost(95);
12217 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12218 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12219 ins_pipe( pipe_slow );
12220 %}
12221
12222 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12223 predicate(UseSSE>=2);
12224 match(Set dst (MoveL2D src));
12225 effect(TEMP dst, USE src, TEMP tmp);
12226 ins_cost(85);
12227 format %{ "MOVD $dst,$src.lo\n\t"
12228 "MOVD $tmp,$src.hi\n\t"
12229 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12230 ins_encode( MovL2XD_reg(dst, src, tmp) );
12231 ins_pipe( pipe_slow );
12232 %}
12233
12234 // Replicate scalar to packed byte (1 byte) values in xmm
12235 instruct Repl8B_reg(regXD dst, regXD src) %{
12236 predicate(UseSSE>=2);
12237 match(Set dst (Replicate8B src));
12238 format %{ "MOVDQA $dst,$src\n\t"
12239 "PUNPCKLBW $dst,$dst\n\t"
12240 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12241 ins_encode( pshufd_8x8(dst, src));
12242 ins_pipe( pipe_slow );
12243 %}
12244
12245 // Replicate scalar to packed byte (1 byte) values in xmm
12246 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12247 predicate(UseSSE>=2);
12248 match(Set dst (Replicate8B src));
12249 format %{ "MOVD $dst,$src\n\t"
12250 "PUNPCKLBW $dst,$dst\n\t"
12251 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12252 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12253 ins_pipe( pipe_slow );
12254 %}
12255
12256 // Replicate scalar zero to packed byte (1 byte) values in xmm
12257 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12258 predicate(UseSSE>=2);
12259 match(Set dst (Replicate8B zero));
12260 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12261 ins_encode( pxor(dst, dst));
12262 ins_pipe( fpu_reg_reg );
12263 %}
12264
12265 // Replicate scalar to packed shore (2 byte) values in xmm
12266 instruct Repl4S_reg(regXD dst, regXD src) %{
12267 predicate(UseSSE>=2);
12268 match(Set dst (Replicate4S src));
12269 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12270 ins_encode( pshufd_4x16(dst, src));
12271 ins_pipe( fpu_reg_reg );
12272 %}
12273
12274 // Replicate scalar to packed shore (2 byte) values in xmm
12275 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12276 predicate(UseSSE>=2);
12277 match(Set dst (Replicate4S src));
12278 format %{ "MOVD $dst,$src\n\t"
12279 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12280 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12281 ins_pipe( fpu_reg_reg );
12282 %}
12283
12284 // Replicate scalar zero to packed short (2 byte) values in xmm
12285 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12286 predicate(UseSSE>=2);
12287 match(Set dst (Replicate4S zero));
12288 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12289 ins_encode( pxor(dst, dst));
12290 ins_pipe( fpu_reg_reg );
12291 %}
12292
12293 // Replicate scalar to packed char (2 byte) values in xmm
12294 instruct Repl4C_reg(regXD dst, regXD src) %{
12295 predicate(UseSSE>=2);
12296 match(Set dst (Replicate4C src));
12297 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12298 ins_encode( pshufd_4x16(dst, src));
12299 ins_pipe( fpu_reg_reg );
12300 %}
12301
12302 // Replicate scalar to packed char (2 byte) values in xmm
12303 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12304 predicate(UseSSE>=2);
12305 match(Set dst (Replicate4C src));
12306 format %{ "MOVD $dst,$src\n\t"
12307 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12308 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12309 ins_pipe( fpu_reg_reg );
12310 %}
12311
12312 // Replicate scalar zero to packed char (2 byte) values in xmm
12313 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12314 predicate(UseSSE>=2);
12315 match(Set dst (Replicate4C zero));
12316 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12317 ins_encode( pxor(dst, dst));
12318 ins_pipe( fpu_reg_reg );
12319 %}
12320
12321 // Replicate scalar to packed integer (4 byte) values in xmm
12322 instruct Repl2I_reg(regXD dst, regXD src) %{
12323 predicate(UseSSE>=2);
12324 match(Set dst (Replicate2I src));
12325 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12326 ins_encode( pshufd(dst, src, 0x00));
12327 ins_pipe( fpu_reg_reg );
12328 %}
12329
12330 // Replicate scalar to packed integer (4 byte) values in xmm
12331 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12332 predicate(UseSSE>=2);
12333 match(Set dst (Replicate2I src));
12334 format %{ "MOVD $dst,$src\n\t"
12335 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12336 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12337 ins_pipe( fpu_reg_reg );
12338 %}
12339
12340 // Replicate scalar zero to packed integer (2 byte) values in xmm
12341 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12342 predicate(UseSSE>=2);
12343 match(Set dst (Replicate2I zero));
12344 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12345 ins_encode( pxor(dst, dst));
12346 ins_pipe( fpu_reg_reg );
12347 %}
12348
12349 // Replicate scalar to packed single precision floating point values in xmm
12350 instruct Repl2F_reg(regXD dst, regXD src) %{
12351 predicate(UseSSE>=2);
12352 match(Set dst (Replicate2F src));
12353 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12354 ins_encode( pshufd(dst, src, 0xe0));
12355 ins_pipe( fpu_reg_reg );
12356 %}
12357
12358 // Replicate scalar to packed single precision floating point values in xmm
12359 instruct Repl2F_regX(regXD dst, regX src) %{
12360 predicate(UseSSE>=2);
12361 match(Set dst (Replicate2F src));
12362 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12363 ins_encode( pshufd(dst, src, 0xe0));
12364 ins_pipe( fpu_reg_reg );
12365 %}
12366
12367 // Replicate scalar to packed single precision floating point values in xmm
12368 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12369 predicate(UseSSE>=2);
12370 match(Set dst (Replicate2F zero));
12371 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12372 ins_encode( pxor(dst, dst));
12373 ins_pipe( fpu_reg_reg );
12374 %}
12375
12376 // =======================================================================
12377 // fast clearing of an array
12378 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12379 match(Set dummy (ClearArray cnt base));
12380 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12381 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12382 "XOR EAX,EAX\n\t"
12383 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12384 opcode(0,0x4);
12385 ins_encode( Opcode(0xD1), RegOpc(ECX),
12386 OpcRegReg(0x33,EAX,EAX),
12387 Opcode(0xF3), Opcode(0xAB) );
12388 ins_pipe( pipe_slow );
12389 %}
12390
12391 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2,
12392 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{
12393 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12394 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12395
12396 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
12397 ins_encode %{
12398 __ string_compare($str1$$Register, $str2$$Register,
12399 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12400 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12401 %}
12402 ins_pipe( pipe_slow );
12403 %}
12404
12405 // fast string equals
12406 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12407 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12408 match(Set result (StrEquals (Binary str1 str2) cnt));
12409 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12410
12411 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12412 ins_encode %{
12413 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12414 $cnt$$Register, $result$$Register, $tmp3$$Register,
12415 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12416 %}
12417 ins_pipe( pipe_slow );
12418 %}
12419
12420 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12421 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{
12422 predicate(UseSSE42Intrinsics);
12423 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12424 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
12425
12426 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %}
12427 ins_encode %{
12428 __ string_indexof($str1$$Register, $str2$$Register,
12429 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12430 $tmp1$$XMMRegister, $tmp2$$Register);
12431 %}
12432 ins_pipe( pipe_slow );
12433 %}
12434
12435 // fast array equals
12436 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12437 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12438 %{
12439 match(Set result (AryEq ary1 ary2));
12440 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12441 //ins_cost(300);
12442
12443 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12444 ins_encode %{
12445 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12446 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12447 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12448 %}
12449 ins_pipe( pipe_slow );
12450 %}
12451
12452 //----------Control Flow Instructions------------------------------------------
12453 // Signed compare Instructions
12454 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12455 match(Set cr (CmpI op1 op2));
12456 effect( DEF cr, USE op1, USE op2 );
12457 format %{ "CMP $op1,$op2" %}
12458 opcode(0x3B); /* Opcode 3B /r */
12459 ins_encode( OpcP, RegReg( op1, op2) );
12460 ins_pipe( ialu_cr_reg_reg );
12461 %}
12462
12463 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12464 match(Set cr (CmpI op1 op2));
12465 effect( DEF cr, USE op1 );
12466 format %{ "CMP $op1,$op2" %}
12467 opcode(0x81,0x07); /* Opcode 81 /7 */
12468 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12469 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12470 ins_pipe( ialu_cr_reg_imm );
12471 %}
12472
12473 // Cisc-spilled version of cmpI_eReg
12474 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12475 match(Set cr (CmpI op1 (LoadI op2)));
12476
12477 format %{ "CMP $op1,$op2" %}
12478 ins_cost(500);
12479 opcode(0x3B); /* Opcode 3B /r */
12480 ins_encode( OpcP, RegMem( op1, op2) );
12481 ins_pipe( ialu_cr_reg_mem );
12482 %}
12483
12484 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12485 match(Set cr (CmpI src zero));
12486 effect( DEF cr, USE src );
12487
12488 format %{ "TEST $src,$src" %}
12489 opcode(0x85);
12490 ins_encode( OpcP, RegReg( src, src ) );
12491 ins_pipe( ialu_cr_reg_imm );
12492 %}
12493
12494 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12495 match(Set cr (CmpI (AndI src con) zero));
12496
12497 format %{ "TEST $src,$con" %}
12498 opcode(0xF7,0x00);
12499 ins_encode( OpcP, RegOpc(src), Con32(con) );
12500 ins_pipe( ialu_cr_reg_imm );
12501 %}
12502
12503 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12504 match(Set cr (CmpI (AndI src mem) zero));
12505
12506 format %{ "TEST $src,$mem" %}
12507 opcode(0x85);
12508 ins_encode( OpcP, RegMem( src, mem ) );
12509 ins_pipe( ialu_cr_reg_mem );
12510 %}
12511
12512 // Unsigned compare Instructions; really, same as signed except they
12513 // produce an eFlagsRegU instead of eFlagsReg.
12514 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12515 match(Set cr (CmpU op1 op2));
12516
12517 format %{ "CMPu $op1,$op2" %}
12518 opcode(0x3B); /* Opcode 3B /r */
12519 ins_encode( OpcP, RegReg( op1, op2) );
12520 ins_pipe( ialu_cr_reg_reg );
12521 %}
12522
12523 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12524 match(Set cr (CmpU op1 op2));
12525
12526 format %{ "CMPu $op1,$op2" %}
12527 opcode(0x81,0x07); /* Opcode 81 /7 */
12528 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12529 ins_pipe( ialu_cr_reg_imm );
12530 %}
12531
12532 // // Cisc-spilled version of cmpU_eReg
12533 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12534 match(Set cr (CmpU op1 (LoadI op2)));
12535
12536 format %{ "CMPu $op1,$op2" %}
12537 ins_cost(500);
12538 opcode(0x3B); /* Opcode 3B /r */
12539 ins_encode( OpcP, RegMem( op1, op2) );
12540 ins_pipe( ialu_cr_reg_mem );
12541 %}
12542
12543 // // Cisc-spilled version of cmpU_eReg
12544 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12545 // match(Set cr (CmpU (LoadI op1) op2));
12546 //
12547 // format %{ "CMPu $op1,$op2" %}
12548 // ins_cost(500);
12549 // opcode(0x39); /* Opcode 39 /r */
12550 // ins_encode( OpcP, RegMem( op1, op2) );
12551 //%}
12552
12553 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12554 match(Set cr (CmpU src zero));
12555
12556 format %{ "TESTu $src,$src" %}
12557 opcode(0x85);
12558 ins_encode( OpcP, RegReg( src, src ) );
12559 ins_pipe( ialu_cr_reg_imm );
12560 %}
12561
12562 // Unsigned pointer compare Instructions
12563 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12564 match(Set cr (CmpP op1 op2));
12565
12566 format %{ "CMPu $op1,$op2" %}
12567 opcode(0x3B); /* Opcode 3B /r */
12568 ins_encode( OpcP, RegReg( op1, op2) );
12569 ins_pipe( ialu_cr_reg_reg );
12570 %}
12571
12572 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12573 match(Set cr (CmpP op1 op2));
12574
12575 format %{ "CMPu $op1,$op2" %}
12576 opcode(0x81,0x07); /* Opcode 81 /7 */
12577 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12578 ins_pipe( ialu_cr_reg_imm );
12579 %}
12580
12581 // // Cisc-spilled version of cmpP_eReg
12582 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12583 match(Set cr (CmpP op1 (LoadP op2)));
12584
12585 format %{ "CMPu $op1,$op2" %}
12586 ins_cost(500);
12587 opcode(0x3B); /* Opcode 3B /r */
12588 ins_encode( OpcP, RegMem( op1, op2) );
12589 ins_pipe( ialu_cr_reg_mem );
12590 %}
12591
12592 // // Cisc-spilled version of cmpP_eReg
12593 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12594 // match(Set cr (CmpP (LoadP op1) op2));
12595 //
12596 // format %{ "CMPu $op1,$op2" %}
12597 // ins_cost(500);
12598 // opcode(0x39); /* Opcode 39 /r */
12599 // ins_encode( OpcP, RegMem( op1, op2) );
12600 //%}
12601
12602 // Compare raw pointer (used in out-of-heap check).
12603 // Only works because non-oop pointers must be raw pointers
12604 // and raw pointers have no anti-dependencies.
12605 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12606 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12607 match(Set cr (CmpP op1 (LoadP op2)));
12608
12609 format %{ "CMPu $op1,$op2" %}
12610 opcode(0x3B); /* Opcode 3B /r */
12611 ins_encode( OpcP, RegMem( op1, op2) );
12612 ins_pipe( ialu_cr_reg_mem );
12613 %}
12614
12615 //
12616 // This will generate a signed flags result. This should be ok
12617 // since any compare to a zero should be eq/neq.
12618 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12619 match(Set cr (CmpP src zero));
12620
12621 format %{ "TEST $src,$src" %}
12622 opcode(0x85);
12623 ins_encode( OpcP, RegReg( src, src ) );
12624 ins_pipe( ialu_cr_reg_imm );
12625 %}
12626
12627 // Cisc-spilled version of testP_reg
12628 // This will generate a signed flags result. This should be ok
12629 // since any compare to a zero should be eq/neq.
12630 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12631 match(Set cr (CmpP (LoadP op) zero));
12632
12633 format %{ "TEST $op,0xFFFFFFFF" %}
12634 ins_cost(500);
12635 opcode(0xF7); /* Opcode F7 /0 */
12636 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12637 ins_pipe( ialu_cr_reg_imm );
12638 %}
12639
12640 // Yanked all unsigned pointer compare operations.
12641 // Pointer compares are done with CmpP which is already unsigned.
12642
12643 //----------Max and Min--------------------------------------------------------
12644 // Min Instructions
12645 ////
12646 // *** Min and Max using the conditional move are slower than the
12647 // *** branch version on a Pentium III.
12648 // // Conditional move for min
12649 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12650 // effect( USE_DEF op2, USE op1, USE cr );
12651 // format %{ "CMOVlt $op2,$op1\t! min" %}
12652 // opcode(0x4C,0x0F);
12653 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12654 // ins_pipe( pipe_cmov_reg );
12655 //%}
12656 //
12657 //// Min Register with Register (P6 version)
12658 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12659 // predicate(VM_Version::supports_cmov() );
12660 // match(Set op2 (MinI op1 op2));
12661 // ins_cost(200);
12662 // expand %{
12663 // eFlagsReg cr;
12664 // compI_eReg(cr,op1,op2);
12665 // cmovI_reg_lt(op2,op1,cr);
12666 // %}
12667 //%}
12668
12669 // Min Register with Register (generic version)
12670 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12671 match(Set dst (MinI dst src));
12672 effect(KILL flags);
12673 ins_cost(300);
12674
12675 format %{ "MIN $dst,$src" %}
12676 opcode(0xCC);
12677 ins_encode( min_enc(dst,src) );
12678 ins_pipe( pipe_slow );
12679 %}
12680
12681 // Max Register with Register
12682 // *** Min and Max using the conditional move are slower than the
12683 // *** branch version on a Pentium III.
12684 // // Conditional move for max
12685 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12686 // effect( USE_DEF op2, USE op1, USE cr );
12687 // format %{ "CMOVgt $op2,$op1\t! max" %}
12688 // opcode(0x4F,0x0F);
12689 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12690 // ins_pipe( pipe_cmov_reg );
12691 //%}
12692 //
12693 // // Max Register with Register (P6 version)
12694 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12695 // predicate(VM_Version::supports_cmov() );
12696 // match(Set op2 (MaxI op1 op2));
12697 // ins_cost(200);
12698 // expand %{
12699 // eFlagsReg cr;
12700 // compI_eReg(cr,op1,op2);
12701 // cmovI_reg_gt(op2,op1,cr);
12702 // %}
12703 //%}
12704
12705 // Max Register with Register (generic version)
12706 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12707 match(Set dst (MaxI dst src));
12708 effect(KILL flags);
12709 ins_cost(300);
12710
12711 format %{ "MAX $dst,$src" %}
12712 opcode(0xCC);
12713 ins_encode( max_enc(dst,src) );
12714 ins_pipe( pipe_slow );
12715 %}
12716
12717 // ============================================================================
12718 // Branch Instructions
12719 // Jump Table
12720 instruct jumpXtnd(eRegI switch_val) %{
12721 match(Jump switch_val);
12722 ins_cost(350);
12723
12724 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12725
12726 ins_encode %{
12727 address table_base = __ address_table_constant(_index2label);
12728
12729 // Jump to Address(table_base + switch_reg)
12730 InternalAddress table(table_base);
12731 Address index(noreg, $switch_val$$Register, Address::times_1);
12732 __ jump(ArrayAddress(table, index));
12733 %}
12734 ins_pc_relative(1);
12735 ins_pipe(pipe_jmp);
12736 %}
12737
12738 // Jump Direct - Label defines a relative address from JMP+1
12739 instruct jmpDir(label labl) %{
12740 match(Goto);
12741 effect(USE labl);
12742
12743 ins_cost(300);
12744 format %{ "JMP $labl" %}
12745 size(5);
12746 opcode(0xE9);
12747 ins_encode( OpcP, Lbl( labl ) );
12748 ins_pipe( pipe_jmp );
12749 ins_pc_relative(1);
12750 %}
12751
12752 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12753 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12754 match(If cop cr);
12755 effect(USE labl);
12756
12757 ins_cost(300);
12758 format %{ "J$cop $labl" %}
12759 size(6);
12760 opcode(0x0F, 0x80);
12761 ins_encode( Jcc( cop, labl) );
12762 ins_pipe( pipe_jcc );
12763 ins_pc_relative(1);
12764 %}
12765
12766 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12767 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12768 match(CountedLoopEnd cop cr);
12769 effect(USE labl);
12770
12771 ins_cost(300);
12772 format %{ "J$cop $labl\t# Loop end" %}
12773 size(6);
12774 opcode(0x0F, 0x80);
12775 ins_encode( Jcc( cop, labl) );
12776 ins_pipe( pipe_jcc );
12777 ins_pc_relative(1);
12778 %}
12779
12780 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12781 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12782 match(CountedLoopEnd cop cmp);
12783 effect(USE labl);
12784
12785 ins_cost(300);
12786 format %{ "J$cop,u $labl\t# Loop end" %}
12787 size(6);
12788 opcode(0x0F, 0x80);
12789 ins_encode( Jcc( cop, labl) );
12790 ins_pipe( pipe_jcc );
12791 ins_pc_relative(1);
12792 %}
12793
12794 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12795 match(CountedLoopEnd cop cmp);
12796 effect(USE labl);
12797
12798 ins_cost(200);
12799 format %{ "J$cop,u $labl\t# Loop end" %}
12800 size(6);
12801 opcode(0x0F, 0x80);
12802 ins_encode( Jcc( cop, labl) );
12803 ins_pipe( pipe_jcc );
12804 ins_pc_relative(1);
12805 %}
12806
12807 // Jump Direct Conditional - using unsigned comparison
12808 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12809 match(If cop cmp);
12810 effect(USE labl);
12811
12812 ins_cost(300);
12813 format %{ "J$cop,u $labl" %}
12814 size(6);
12815 opcode(0x0F, 0x80);
12816 ins_encode(Jcc(cop, labl));
12817 ins_pipe(pipe_jcc);
12818 ins_pc_relative(1);
12819 %}
12820
12821 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12822 match(If cop cmp);
12823 effect(USE labl);
12824
12825 ins_cost(200);
12826 format %{ "J$cop,u $labl" %}
12827 size(6);
12828 opcode(0x0F, 0x80);
12829 ins_encode(Jcc(cop, labl));
12830 ins_pipe(pipe_jcc);
12831 ins_pc_relative(1);
12832 %}
12833
12834 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12835 match(If cop cmp);
12836 effect(USE labl);
12837
12838 ins_cost(200);
12839 format %{ $$template
12840 if ($cop$$cmpcode == Assembler::notEqual) {
12841 $$emit$$"JP,u $labl\n\t"
12842 $$emit$$"J$cop,u $labl"
12843 } else {
12844 $$emit$$"JP,u done\n\t"
12845 $$emit$$"J$cop,u $labl\n\t"
12846 $$emit$$"done:"
12847 }
12848 %}
12849 size(12);
12850 opcode(0x0F, 0x80);
12851 ins_encode %{
12852 Label* l = $labl$$label;
12853 $$$emit8$primary;
12854 emit_cc(cbuf, $secondary, Assembler::parity);
12855 int parity_disp = -1;
12856 bool ok = false;
12857 if ($cop$$cmpcode == Assembler::notEqual) {
12858 // the two jumps 6 bytes apart so the jump distances are too
12859 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12860 } else if ($cop$$cmpcode == Assembler::equal) {
12861 parity_disp = 6;
12862 ok = true;
12863 } else {
12864 ShouldNotReachHere();
12865 }
12866 emit_d32(cbuf, parity_disp);
12867 $$$emit8$primary;
12868 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12869 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12870 emit_d32(cbuf, disp);
12871 %}
12872 ins_pipe(pipe_jcc);
12873 ins_pc_relative(1);
12874 %}
12875
12876 // ============================================================================
12877 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12878 // array for an instance of the superklass. Set a hidden internal cache on a
12879 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12880 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12881 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12882 match(Set result (PartialSubtypeCheck sub super));
12883 effect( KILL rcx, KILL cr );
12884
12885 ins_cost(1100); // slightly larger than the next version
12886 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12887 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12888 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12889 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12890 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12891 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12892 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12893 "miss:\t" %}
12894
12895 opcode(0x1); // Force a XOR of EDI
12896 ins_encode( enc_PartialSubtypeCheck() );
12897 ins_pipe( pipe_slow );
12898 %}
12899
12900 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12901 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12902 effect( KILL rcx, KILL result );
12903
12904 ins_cost(1000);
12905 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12906 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12907 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12908 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12909 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12910 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12911 "miss:\t" %}
12912
12913 opcode(0x0); // No need to XOR EDI
12914 ins_encode( enc_PartialSubtypeCheck() );
12915 ins_pipe( pipe_slow );
12916 %}
12917
12918 // ============================================================================
12919 // Branch Instructions -- short offset versions
12920 //
12921 // These instructions are used to replace jumps of a long offset (the default
12922 // match) with jumps of a shorter offset. These instructions are all tagged
12923 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12924 // match rules in general matching. Instead, the ADLC generates a conversion
12925 // method in the MachNode which can be used to do in-place replacement of the
12926 // long variant with the shorter variant. The compiler will determine if a
12927 // branch can be taken by the is_short_branch_offset() predicate in the machine
12928 // specific code section of the file.
12929
12930 // Jump Direct - Label defines a relative address from JMP+1
12931 instruct jmpDir_short(label labl) %{
12932 match(Goto);
12933 effect(USE labl);
12934
12935 ins_cost(300);
12936 format %{ "JMP,s $labl" %}
12937 size(2);
12938 opcode(0xEB);
12939 ins_encode( OpcP, LblShort( labl ) );
12940 ins_pipe( pipe_jmp );
12941 ins_pc_relative(1);
12942 ins_short_branch(1);
12943 %}
12944
12945 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12946 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12947 match(If cop cr);
12948 effect(USE labl);
12949
12950 ins_cost(300);
12951 format %{ "J$cop,s $labl" %}
12952 size(2);
12953 opcode(0x70);
12954 ins_encode( JccShort( cop, labl) );
12955 ins_pipe( pipe_jcc );
12956 ins_pc_relative(1);
12957 ins_short_branch(1);
12958 %}
12959
12960 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12961 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12962 match(CountedLoopEnd cop cr);
12963 effect(USE labl);
12964
12965 ins_cost(300);
12966 format %{ "J$cop,s $labl\t# Loop end" %}
12967 size(2);
12968 opcode(0x70);
12969 ins_encode( JccShort( cop, labl) );
12970 ins_pipe( pipe_jcc );
12971 ins_pc_relative(1);
12972 ins_short_branch(1);
12973 %}
12974
12975 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12976 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12977 match(CountedLoopEnd cop cmp);
12978 effect(USE labl);
12979
12980 ins_cost(300);
12981 format %{ "J$cop,us $labl\t# Loop end" %}
12982 size(2);
12983 opcode(0x70);
12984 ins_encode( JccShort( cop, labl) );
12985 ins_pipe( pipe_jcc );
12986 ins_pc_relative(1);
12987 ins_short_branch(1);
12988 %}
12989
12990 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12991 match(CountedLoopEnd cop cmp);
12992 effect(USE labl);
12993
12994 ins_cost(300);
12995 format %{ "J$cop,us $labl\t# Loop end" %}
12996 size(2);
12997 opcode(0x70);
12998 ins_encode( JccShort( cop, labl) );
12999 ins_pipe( pipe_jcc );
13000 ins_pc_relative(1);
13001 ins_short_branch(1);
13002 %}
13003
13004 // Jump Direct Conditional - using unsigned comparison
13005 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13006 match(If cop cmp);
13007 effect(USE labl);
13008
13009 ins_cost(300);
13010 format %{ "J$cop,us $labl" %}
13011 size(2);
13012 opcode(0x70);
13013 ins_encode( JccShort( cop, labl) );
13014 ins_pipe( pipe_jcc );
13015 ins_pc_relative(1);
13016 ins_short_branch(1);
13017 %}
13018
13019 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13020 match(If cop cmp);
13021 effect(USE labl);
13022
13023 ins_cost(300);
13024 format %{ "J$cop,us $labl" %}
13025 size(2);
13026 opcode(0x70);
13027 ins_encode( JccShort( cop, labl) );
13028 ins_pipe( pipe_jcc );
13029 ins_pc_relative(1);
13030 ins_short_branch(1);
13031 %}
13032
13033 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13034 match(If cop cmp);
13035 effect(USE labl);
13036
13037 ins_cost(300);
13038 format %{ $$template
13039 if ($cop$$cmpcode == Assembler::notEqual) {
13040 $$emit$$"JP,u,s $labl\n\t"
13041 $$emit$$"J$cop,u,s $labl"
13042 } else {
13043 $$emit$$"JP,u,s done\n\t"
13044 $$emit$$"J$cop,u,s $labl\n\t"
13045 $$emit$$"done:"
13046 }
13047 %}
13048 size(4);
13049 opcode(0x70);
13050 ins_encode %{
13051 Label* l = $labl$$label;
13052 emit_cc(cbuf, $primary, Assembler::parity);
13053 int parity_disp = -1;
13054 if ($cop$$cmpcode == Assembler::notEqual) {
13055 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13056 } else if ($cop$$cmpcode == Assembler::equal) {
13057 parity_disp = 2;
13058 } else {
13059 ShouldNotReachHere();
13060 }
13061 emit_d8(cbuf, parity_disp);
13062 emit_cc(cbuf, $primary, $cop$$cmpcode);
13063 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13064 emit_d8(cbuf, disp);
13065 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13066 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13067 %}
13068 ins_pipe(pipe_jcc);
13069 ins_pc_relative(1);
13070 ins_short_branch(1);
13071 %}
13072
13073 // ============================================================================
13074 // Long Compare
13075 //
13076 // Currently we hold longs in 2 registers. Comparing such values efficiently
13077 // is tricky. The flavor of compare used depends on whether we are testing
13078 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13079 // The GE test is the negated LT test. The LE test can be had by commuting
13080 // the operands (yielding a GE test) and then negating; negate again for the
13081 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13082 // NE test is negated from that.
13083
13084 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13085 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13086 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13087 // are collapsed internally in the ADLC's dfa-gen code. The match for
13088 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13089 // foo match ends up with the wrong leaf. One fix is to not match both
13090 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13091 // both forms beat the trinary form of long-compare and both are very useful
13092 // on Intel which has so few registers.
13093
13094 // Manifest a CmpL result in an integer register. Very painful.
13095 // This is the test to avoid.
13096 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13097 match(Set dst (CmpL3 src1 src2));
13098 effect( KILL flags );
13099 ins_cost(1000);
13100 format %{ "XOR $dst,$dst\n\t"
13101 "CMP $src1.hi,$src2.hi\n\t"
13102 "JLT,s m_one\n\t"
13103 "JGT,s p_one\n\t"
13104 "CMP $src1.lo,$src2.lo\n\t"
13105 "JB,s m_one\n\t"
13106 "JEQ,s done\n"
13107 "p_one:\tINC $dst\n\t"
13108 "JMP,s done\n"
13109 "m_one:\tDEC $dst\n"
13110 "done:" %}
13111 ins_encode %{
13112 Label p_one, m_one, done;
13113 __ xorptr($dst$$Register, $dst$$Register);
13114 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13115 __ jccb(Assembler::less, m_one);
13116 __ jccb(Assembler::greater, p_one);
13117 __ cmpl($src1$$Register, $src2$$Register);
13118 __ jccb(Assembler::below, m_one);
13119 __ jccb(Assembler::equal, done);
13120 __ bind(p_one);
13121 __ incrementl($dst$$Register);
13122 __ jmpb(done);
13123 __ bind(m_one);
13124 __ decrementl($dst$$Register);
13125 __ bind(done);
13126 %}
13127 ins_pipe( pipe_slow );
13128 %}
13129
13130 //======
13131 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13132 // compares. Can be used for LE or GT compares by reversing arguments.
13133 // NOT GOOD FOR EQ/NE tests.
13134 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13135 match( Set flags (CmpL src zero ));
13136 ins_cost(100);
13137 format %{ "TEST $src.hi,$src.hi" %}
13138 opcode(0x85);
13139 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13140 ins_pipe( ialu_cr_reg_reg );
13141 %}
13142
13143 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13144 // compares. Can be used for LE or GT compares by reversing arguments.
13145 // NOT GOOD FOR EQ/NE tests.
13146 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13147 match( Set flags (CmpL src1 src2 ));
13148 effect( TEMP tmp );
13149 ins_cost(300);
13150 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13151 "MOV $tmp,$src1.hi\n\t"
13152 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13153 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13154 ins_pipe( ialu_cr_reg_reg );
13155 %}
13156
13157 // Long compares reg < zero/req OR reg >= zero/req.
13158 // Just a wrapper for a normal branch, plus the predicate test.
13159 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13160 match(If cmp flags);
13161 effect(USE labl);
13162 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13163 expand %{
13164 jmpCon(cmp,flags,labl); // JLT or JGE...
13165 %}
13166 %}
13167
13168 // Compare 2 longs and CMOVE longs.
13169 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13170 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13171 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13172 ins_cost(400);
13173 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13174 "CMOV$cmp $dst.hi,$src.hi" %}
13175 opcode(0x0F,0x40);
13176 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13177 ins_pipe( pipe_cmov_reg_long );
13178 %}
13179
13180 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13181 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13182 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13183 ins_cost(500);
13184 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13185 "CMOV$cmp $dst.hi,$src.hi" %}
13186 opcode(0x0F,0x40);
13187 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13188 ins_pipe( pipe_cmov_reg_long );
13189 %}
13190
13191 // Compare 2 longs and CMOVE ints.
13192 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13193 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13194 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13195 ins_cost(200);
13196 format %{ "CMOV$cmp $dst,$src" %}
13197 opcode(0x0F,0x40);
13198 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13199 ins_pipe( pipe_cmov_reg );
13200 %}
13201
13202 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13203 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13204 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13205 ins_cost(250);
13206 format %{ "CMOV$cmp $dst,$src" %}
13207 opcode(0x0F,0x40);
13208 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13209 ins_pipe( pipe_cmov_mem );
13210 %}
13211
13212 // Compare 2 longs and CMOVE ints.
13213 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13214 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13215 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13216 ins_cost(200);
13217 format %{ "CMOV$cmp $dst,$src" %}
13218 opcode(0x0F,0x40);
13219 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13220 ins_pipe( pipe_cmov_reg );
13221 %}
13222
13223 // Compare 2 longs and CMOVE doubles
13224 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13225 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13226 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13227 ins_cost(200);
13228 expand %{
13229 fcmovD_regS(cmp,flags,dst,src);
13230 %}
13231 %}
13232
13233 // Compare 2 longs and CMOVE doubles
13234 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13235 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13236 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13237 ins_cost(200);
13238 expand %{
13239 fcmovXD_regS(cmp,flags,dst,src);
13240 %}
13241 %}
13242
13243 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13244 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13245 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13246 ins_cost(200);
13247 expand %{
13248 fcmovF_regS(cmp,flags,dst,src);
13249 %}
13250 %}
13251
13252 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13253 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13254 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13255 ins_cost(200);
13256 expand %{
13257 fcmovX_regS(cmp,flags,dst,src);
13258 %}
13259 %}
13260
13261 //======
13262 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13263 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13264 match( Set flags (CmpL src zero ));
13265 effect(TEMP tmp);
13266 ins_cost(200);
13267 format %{ "MOV $tmp,$src.lo\n\t"
13268 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13269 ins_encode( long_cmp_flags0( src, tmp ) );
13270 ins_pipe( ialu_reg_reg_long );
13271 %}
13272
13273 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13274 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13275 match( Set flags (CmpL src1 src2 ));
13276 ins_cost(200+300);
13277 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13278 "JNE,s skip\n\t"
13279 "CMP $src1.hi,$src2.hi\n\t"
13280 "skip:\t" %}
13281 ins_encode( long_cmp_flags1( src1, src2 ) );
13282 ins_pipe( ialu_cr_reg_reg );
13283 %}
13284
13285 // Long compare reg == zero/reg OR reg != zero/reg
13286 // Just a wrapper for a normal branch, plus the predicate test.
13287 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13288 match(If cmp flags);
13289 effect(USE labl);
13290 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13291 expand %{
13292 jmpCon(cmp,flags,labl); // JEQ or JNE...
13293 %}
13294 %}
13295
13296 // Compare 2 longs and CMOVE longs.
13297 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13298 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13299 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13300 ins_cost(400);
13301 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13302 "CMOV$cmp $dst.hi,$src.hi" %}
13303 opcode(0x0F,0x40);
13304 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13305 ins_pipe( pipe_cmov_reg_long );
13306 %}
13307
13308 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13309 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13310 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13311 ins_cost(500);
13312 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13313 "CMOV$cmp $dst.hi,$src.hi" %}
13314 opcode(0x0F,0x40);
13315 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13316 ins_pipe( pipe_cmov_reg_long );
13317 %}
13318
13319 // Compare 2 longs and CMOVE ints.
13320 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13321 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13322 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13323 ins_cost(200);
13324 format %{ "CMOV$cmp $dst,$src" %}
13325 opcode(0x0F,0x40);
13326 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13327 ins_pipe( pipe_cmov_reg );
13328 %}
13329
13330 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13331 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13332 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13333 ins_cost(250);
13334 format %{ "CMOV$cmp $dst,$src" %}
13335 opcode(0x0F,0x40);
13336 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13337 ins_pipe( pipe_cmov_mem );
13338 %}
13339
13340 // Compare 2 longs and CMOVE ints.
13341 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13342 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13343 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13344 ins_cost(200);
13345 format %{ "CMOV$cmp $dst,$src" %}
13346 opcode(0x0F,0x40);
13347 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13348 ins_pipe( pipe_cmov_reg );
13349 %}
13350
13351 // Compare 2 longs and CMOVE doubles
13352 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13353 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13354 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13355 ins_cost(200);
13356 expand %{
13357 fcmovD_regS(cmp,flags,dst,src);
13358 %}
13359 %}
13360
13361 // Compare 2 longs and CMOVE doubles
13362 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13363 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13364 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13365 ins_cost(200);
13366 expand %{
13367 fcmovXD_regS(cmp,flags,dst,src);
13368 %}
13369 %}
13370
13371 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13372 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13373 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13374 ins_cost(200);
13375 expand %{
13376 fcmovF_regS(cmp,flags,dst,src);
13377 %}
13378 %}
13379
13380 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13381 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13382 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13383 ins_cost(200);
13384 expand %{
13385 fcmovX_regS(cmp,flags,dst,src);
13386 %}
13387 %}
13388
13389 //======
13390 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13391 // Same as cmpL_reg_flags_LEGT except must negate src
13392 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13393 match( Set flags (CmpL src zero ));
13394 effect( TEMP tmp );
13395 ins_cost(300);
13396 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13397 "CMP $tmp,$src.lo\n\t"
13398 "SBB $tmp,$src.hi\n\t" %}
13399 ins_encode( long_cmp_flags3(src, tmp) );
13400 ins_pipe( ialu_reg_reg_long );
13401 %}
13402
13403 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13404 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13405 // requires a commuted test to get the same result.
13406 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13407 match( Set flags (CmpL src1 src2 ));
13408 effect( TEMP tmp );
13409 ins_cost(300);
13410 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13411 "MOV $tmp,$src2.hi\n\t"
13412 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13413 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13414 ins_pipe( ialu_cr_reg_reg );
13415 %}
13416
13417 // Long compares reg < zero/req OR reg >= zero/req.
13418 // Just a wrapper for a normal branch, plus the predicate test
13419 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13420 match(If cmp flags);
13421 effect(USE labl);
13422 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13423 ins_cost(300);
13424 expand %{
13425 jmpCon(cmp,flags,labl); // JGT or JLE...
13426 %}
13427 %}
13428
13429 // Compare 2 longs and CMOVE longs.
13430 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13431 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13432 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13433 ins_cost(400);
13434 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13435 "CMOV$cmp $dst.hi,$src.hi" %}
13436 opcode(0x0F,0x40);
13437 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13438 ins_pipe( pipe_cmov_reg_long );
13439 %}
13440
13441 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13442 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13443 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13444 ins_cost(500);
13445 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13446 "CMOV$cmp $dst.hi,$src.hi+4" %}
13447 opcode(0x0F,0x40);
13448 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13449 ins_pipe( pipe_cmov_reg_long );
13450 %}
13451
13452 // Compare 2 longs and CMOVE ints.
13453 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13454 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13455 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13456 ins_cost(200);
13457 format %{ "CMOV$cmp $dst,$src" %}
13458 opcode(0x0F,0x40);
13459 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13460 ins_pipe( pipe_cmov_reg );
13461 %}
13462
13463 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13464 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13465 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13466 ins_cost(250);
13467 format %{ "CMOV$cmp $dst,$src" %}
13468 opcode(0x0F,0x40);
13469 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13470 ins_pipe( pipe_cmov_mem );
13471 %}
13472
13473 // Compare 2 longs and CMOVE ptrs.
13474 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13475 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13476 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13477 ins_cost(200);
13478 format %{ "CMOV$cmp $dst,$src" %}
13479 opcode(0x0F,0x40);
13480 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13481 ins_pipe( pipe_cmov_reg );
13482 %}
13483
13484 // Compare 2 longs and CMOVE doubles
13485 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13486 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13487 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13488 ins_cost(200);
13489 expand %{
13490 fcmovD_regS(cmp,flags,dst,src);
13491 %}
13492 %}
13493
13494 // Compare 2 longs and CMOVE doubles
13495 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13496 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13497 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13498 ins_cost(200);
13499 expand %{
13500 fcmovXD_regS(cmp,flags,dst,src);
13501 %}
13502 %}
13503
13504 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13505 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13506 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13507 ins_cost(200);
13508 expand %{
13509 fcmovF_regS(cmp,flags,dst,src);
13510 %}
13511 %}
13512
13513
13514 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13515 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13516 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13517 ins_cost(200);
13518 expand %{
13519 fcmovX_regS(cmp,flags,dst,src);
13520 %}
13521 %}
13522
13523
13524 // ============================================================================
13525 // Procedure Call/Return Instructions
13526 // Call Java Static Instruction
13527 // Note: If this code changes, the corresponding ret_addr_offset() and
13528 // compute_padding() functions will have to be adjusted.
13529 instruct CallStaticJavaDirect(method meth) %{
13530 match(CallStaticJava);
13531 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13532 effect(USE meth);
13533
13534 ins_cost(300);
13535 format %{ "CALL,static " %}
13536 opcode(0xE8); /* E8 cd */
13537 ins_encode( pre_call_FPU,
13538 Java_Static_Call( meth ),
13539 call_epilog,
13540 post_call_FPU );
13541 ins_pipe( pipe_slow );
13542 ins_pc_relative(1);
13543 ins_alignment(4);
13544 %}
13545
13546 // Call Java Static Instruction (method handle version)
13547 // Note: If this code changes, the corresponding ret_addr_offset() and
13548 // compute_padding() functions will have to be adjusted.
13549 instruct CallStaticJavaHandle(method meth, eBPRegP ebp) %{
13550 match(CallStaticJava);
13551 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13552 effect(USE meth);
13553 // EBP is saved by all callees (for interpreter stack correction).
13554 // We use it here for a similar purpose, in {preserve,restore}_SP.
13555
13556 ins_cost(300);
13557 format %{ "CALL,static/MethodHandle " %}
13558 opcode(0xE8); /* E8 cd */
13559 ins_encode( pre_call_FPU,
13560 preserve_SP,
13561 Java_Static_Call( meth ),
13562 restore_SP,
13563 call_epilog,
13564 post_call_FPU );
13565 ins_pipe( pipe_slow );
13566 ins_pc_relative(1);
13567 ins_alignment(4);
13568 %}
13569
13570 // Call Java Dynamic Instruction
13571 // Note: If this code changes, the corresponding ret_addr_offset() and
13572 // compute_padding() functions will have to be adjusted.
13573 instruct CallDynamicJavaDirect(method meth) %{
13574 match(CallDynamicJava);
13575 effect(USE meth);
13576
13577 ins_cost(300);
13578 format %{ "MOV EAX,(oop)-1\n\t"
13579 "CALL,dynamic" %}
13580 opcode(0xE8); /* E8 cd */
13581 ins_encode( pre_call_FPU,
13582 Java_Dynamic_Call( meth ),
13583 call_epilog,
13584 post_call_FPU );
13585 ins_pipe( pipe_slow );
13586 ins_pc_relative(1);
13587 ins_alignment(4);
13588 %}
13589
13590 // Call Runtime Instruction
13591 instruct CallRuntimeDirect(method meth) %{
13592 match(CallRuntime );
13593 effect(USE meth);
13594
13595 ins_cost(300);
13596 format %{ "CALL,runtime " %}
13597 opcode(0xE8); /* E8 cd */
13598 // Use FFREEs to clear entries in float stack
13599 ins_encode( pre_call_FPU,
13600 FFree_Float_Stack_All,
13601 Java_To_Runtime( meth ),
13602 post_call_FPU );
13603 ins_pipe( pipe_slow );
13604 ins_pc_relative(1);
13605 %}
13606
13607 // Call runtime without safepoint
13608 instruct CallLeafDirect(method meth) %{
13609 match(CallLeaf);
13610 effect(USE meth);
13611
13612 ins_cost(300);
13613 format %{ "CALL_LEAF,runtime " %}
13614 opcode(0xE8); /* E8 cd */
13615 ins_encode( pre_call_FPU,
13616 FFree_Float_Stack_All,
13617 Java_To_Runtime( meth ),
13618 Verify_FPU_For_Leaf, post_call_FPU );
13619 ins_pipe( pipe_slow );
13620 ins_pc_relative(1);
13621 %}
13622
13623 instruct CallLeafNoFPDirect(method meth) %{
13624 match(CallLeafNoFP);
13625 effect(USE meth);
13626
13627 ins_cost(300);
13628 format %{ "CALL_LEAF_NOFP,runtime " %}
13629 opcode(0xE8); /* E8 cd */
13630 ins_encode(Java_To_Runtime(meth));
13631 ins_pipe( pipe_slow );
13632 ins_pc_relative(1);
13633 %}
13634
13635
13636 // Return Instruction
13637 // Remove the return address & jump to it.
13638 instruct Ret() %{
13639 match(Return);
13640 format %{ "RET" %}
13641 opcode(0xC3);
13642 ins_encode(OpcP);
13643 ins_pipe( pipe_jmp );
13644 %}
13645
13646 // Tail Call; Jump from runtime stub to Java code.
13647 // Also known as an 'interprocedural jump'.
13648 // Target of jump will eventually return to caller.
13649 // TailJump below removes the return address.
13650 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13651 match(TailCall jump_target method_oop );
13652 ins_cost(300);
13653 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13654 opcode(0xFF, 0x4); /* Opcode FF /4 */
13655 ins_encode( OpcP, RegOpc(jump_target) );
13656 ins_pipe( pipe_jmp );
13657 %}
13658
13659
13660 // Tail Jump; remove the return address; jump to target.
13661 // TailCall above leaves the return address around.
13662 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13663 match( TailJump jump_target ex_oop );
13664 ins_cost(300);
13665 format %{ "POP EDX\t# pop return address into dummy\n\t"
13666 "JMP $jump_target " %}
13667 opcode(0xFF, 0x4); /* Opcode FF /4 */
13668 ins_encode( enc_pop_rdx,
13669 OpcP, RegOpc(jump_target) );
13670 ins_pipe( pipe_jmp );
13671 %}
13672
13673 // Create exception oop: created by stack-crawling runtime code.
13674 // Created exception is now available to this handler, and is setup
13675 // just prior to jumping to this handler. No code emitted.
13676 instruct CreateException( eAXRegP ex_oop )
13677 %{
13678 match(Set ex_oop (CreateEx));
13679
13680 size(0);
13681 // use the following format syntax
13682 format %{ "# exception oop is in EAX; no code emitted" %}
13683 ins_encode();
13684 ins_pipe( empty );
13685 %}
13686
13687
13688 // Rethrow exception:
13689 // The exception oop will come in the first argument position.
13690 // Then JUMP (not call) to the rethrow stub code.
13691 instruct RethrowException()
13692 %{
13693 match(Rethrow);
13694
13695 // use the following format syntax
13696 format %{ "JMP rethrow_stub" %}
13697 ins_encode(enc_rethrow);
13698 ins_pipe( pipe_jmp );
13699 %}
13700
13701 // inlined locking and unlocking
13702
13703
13704 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13705 match( Set cr (FastLock object box) );
13706 effect( TEMP tmp, TEMP scr );
13707 ins_cost(300);
13708 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13709 ins_encode( Fast_Lock(object,box,tmp,scr) );
13710 ins_pipe( pipe_slow );
13711 ins_pc_relative(1);
13712 %}
13713
13714 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13715 match( Set cr (FastUnlock object box) );
13716 effect( TEMP tmp );
13717 ins_cost(300);
13718 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13719 ins_encode( Fast_Unlock(object,box,tmp) );
13720 ins_pipe( pipe_slow );
13721 ins_pc_relative(1);
13722 %}
13723
13724
13725
13726 // ============================================================================
13727 // Safepoint Instruction
13728 instruct safePoint_poll(eFlagsReg cr) %{
13729 match(SafePoint);
13730 effect(KILL cr);
13731
13732 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13733 // On SPARC that might be acceptable as we can generate the address with
13734 // just a sethi, saving an or. By polling at offset 0 we can end up
13735 // putting additional pressure on the index-0 in the D$. Because of
13736 // alignment (just like the situation at hand) the lower indices tend
13737 // to see more traffic. It'd be better to change the polling address
13738 // to offset 0 of the last $line in the polling page.
13739
13740 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13741 ins_cost(125);
13742 size(6) ;
13743 ins_encode( Safepoint_Poll() );
13744 ins_pipe( ialu_reg_mem );
13745 %}
13746
13747 //----------PEEPHOLE RULES-----------------------------------------------------
13748 // These must follow all instruction definitions as they use the names
13749 // defined in the instructions definitions.
13750 //
13751 // peepmatch ( root_instr_name [preceding_instruction]* );
13752 //
13753 // peepconstraint %{
13754 // (instruction_number.operand_name relational_op instruction_number.operand_name
13755 // [, ...] );
13756 // // instruction numbers are zero-based using left to right order in peepmatch
13757 //
13758 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13759 // // provide an instruction_number.operand_name for each operand that appears
13760 // // in the replacement instruction's match rule
13761 //
13762 // ---------VM FLAGS---------------------------------------------------------
13763 //
13764 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13765 //
13766 // Each peephole rule is given an identifying number starting with zero and
13767 // increasing by one in the order seen by the parser. An individual peephole
13768 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13769 // on the command-line.
13770 //
13771 // ---------CURRENT LIMITATIONS----------------------------------------------
13772 //
13773 // Only match adjacent instructions in same basic block
13774 // Only equality constraints
13775 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13776 // Only one replacement instruction
13777 //
13778 // ---------EXAMPLE----------------------------------------------------------
13779 //
13780 // // pertinent parts of existing instructions in architecture description
13781 // instruct movI(eRegI dst, eRegI src) %{
13782 // match(Set dst (CopyI src));
13783 // %}
13784 //
13785 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13786 // match(Set dst (AddI dst src));
13787 // effect(KILL cr);
13788 // %}
13789 //
13790 // // Change (inc mov) to lea
13791 // peephole %{
13792 // // increment preceeded by register-register move
13793 // peepmatch ( incI_eReg movI );
13794 // // require that the destination register of the increment
13795 // // match the destination register of the move
13796 // peepconstraint ( 0.dst == 1.dst );
13797 // // construct a replacement instruction that sets
13798 // // the destination to ( move's source register + one )
13799 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13800 // %}
13801 //
13802 // Implementation no longer uses movX instructions since
13803 // machine-independent system no longer uses CopyX nodes.
13804 //
13805 // peephole %{
13806 // peepmatch ( incI_eReg movI );
13807 // peepconstraint ( 0.dst == 1.dst );
13808 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13809 // %}
13810 //
13811 // peephole %{
13812 // peepmatch ( decI_eReg movI );
13813 // peepconstraint ( 0.dst == 1.dst );
13814 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13815 // %}
13816 //
13817 // peephole %{
13818 // peepmatch ( addI_eReg_imm movI );
13819 // peepconstraint ( 0.dst == 1.dst );
13820 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13821 // %}
13822 //
13823 // peephole %{
13824 // peepmatch ( addP_eReg_imm movP );
13825 // peepconstraint ( 0.dst == 1.dst );
13826 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13827 // %}
13828
13829 // // Change load of spilled value to only a spill
13830 // instruct storeI(memory mem, eRegI src) %{
13831 // match(Set mem (StoreI mem src));
13832 // %}
13833 //
13834 // instruct loadI(eRegI dst, memory mem) %{
13835 // match(Set dst (LoadI mem));
13836 // %}
13837 //
13838 peephole %{
13839 peepmatch ( loadI storeI );
13840 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13841 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13842 %}
13843
13844 //----------SMARTSPILL RULES---------------------------------------------------
13845 // These must follow all instruction definitions as they use the names
13846 // defined in the instructions definitions.