src/cpu/x86/vm/x86_64.ad
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*** old/src/cpu/x86/vm/x86_64.ad Tue Oct 22 14:52:23 2013
--- new/src/cpu/x86/vm/x86_64.ad Tue Oct 22 14:52:23 2013
*** 7959,7968 ****
--- 7959,7969 ----
opcode(0xF7, 0x5); /* Opcode F7 /5 */
ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
ins_pipe(ialu_reg_reg_alu0);
%}
+
instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
%{
match(MulExactI dst src);
effect(DEF cr);
*** 7972,7981 ****
--- 7973,7983 ----
__ imull($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg_reg_alu0);
%}
+
instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
%{
match(MulExactI src imm);
effect(DEF cr);
*** 7985,7998 ****
--- 7987,8013 ----
__ imull($dst$$Register, $src$$Register, $imm$$constant);
%}
ins_pipe(ialu_reg_reg_alu0);
%}
+ instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
+ %{
+ match(MulExactI dst (LoadI src));
+ effect(DEF cr);
+
+ ins_cost(350);
+ format %{ "imull $dst, $src\t# mulExact int" %}
+ ins_encode %{
+ __ imull($dst$$Register, $src$$Address);
+ %}
+ ins_pipe(ialu_reg_mem_alu0);
+ %}
+
instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
%{
match(MulExactL dst src);
! effect(KILL cr);
! effect(DEF cr);
ins_cost(300);
format %{ "imulq $dst, $src\t# mulExact long" %}
ins_encode %{
__ imulq($dst$$Register, $src$$Register);
*** 8001,8020 ****
--- 8016,8048 ----
%}
instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
%{
match(MulExactL src imm);
! effect(KILL cr);
! effect(DEF cr);
ins_cost(300);
format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
ins_encode %{
__ imulq($dst$$Register, $src$$Register, $imm$$constant);
%}
ins_pipe(ialu_reg_reg_alu0);
%}
+ instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
+ %{
+ match(MulExactL dst (LoadL src));
+ effect(DEF cr);
+
+ ins_cost(350);
+ format %{ "imulq $dst, $src\t# mulExact long" %}
+ ins_encode %{
+ __ imulq($dst$$Register, $src$$Address);
+ %}
+ ins_pipe(ialu_reg_mem_alu0);
+ %}
+
instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
rFlagsReg cr)
%{
match(Set rax (DivI rax div));
effect(KILL rdx, KILL cr);
src/cpu/x86/vm/x86_64.ad
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