1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #ifdef TARGET_ARCH_MODEL_x86_32
42 # include "adfiles/ad_x86_32.hpp"
43 #endif
44 #ifdef TARGET_ARCH_MODEL_x86_64
45 # include "adfiles/ad_x86_64.hpp"
46 #endif
47 #ifdef TARGET_ARCH_MODEL_sparc
48 # include "adfiles/ad_sparc.hpp"
49 #endif
50 #ifdef TARGET_ARCH_MODEL_zero
51 # include "adfiles/ad_zero.hpp"
52 #endif
53 #ifdef TARGET_ARCH_MODEL_arm
54 # include "adfiles/ad_arm.hpp"
55 #endif
56 #ifdef TARGET_ARCH_MODEL_ppc
57 # include "adfiles/ad_ppc.hpp"
58 #endif
59
60 OptoReg::Name OptoReg::c_frame_pointer;
61
62 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
63 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
64 RegMask Matcher::STACK_ONLY_mask;
65 RegMask Matcher::c_frame_ptr_mask;
66 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
67 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
68
69 //---------------------------Matcher-------------------------------------------
70 Matcher::Matcher()
71 : PhaseTransform( Phase::Ins_Select ),
72 #ifdef ASSERT
73 _old2new_map(C->comp_arena()),
74 _new2old_map(C->comp_arena()),
75 #endif
76 _shared_nodes(C->comp_arena()),
77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
78 _swallowed(swallowed),
79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
80 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
81 _must_clone(must_clone),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type),
85 _ruleName(ruleName),
86 _allocation_started(false),
87 _states_arena(Chunk::medium_size),
88 _visited(&_states_arena),
89 _shared(&_states_arena),
90 _dontcare(&_states_arena) {
91 C->set_matcher(this);
92
93 idealreg2spillmask [Op_RegI] = NULL;
94 idealreg2spillmask [Op_RegN] = NULL;
95 idealreg2spillmask [Op_RegL] = NULL;
96 idealreg2spillmask [Op_RegF] = NULL;
97 idealreg2spillmask [Op_RegD] = NULL;
98 idealreg2spillmask [Op_RegP] = NULL;
99 idealreg2spillmask [Op_VecS] = NULL;
100 idealreg2spillmask [Op_VecD] = NULL;
101 idealreg2spillmask [Op_VecX] = NULL;
102 idealreg2spillmask [Op_VecY] = NULL;
103
104 idealreg2debugmask [Op_RegI] = NULL;
105 idealreg2debugmask [Op_RegN] = NULL;
106 idealreg2debugmask [Op_RegL] = NULL;
107 idealreg2debugmask [Op_RegF] = NULL;
108 idealreg2debugmask [Op_RegD] = NULL;
109 idealreg2debugmask [Op_RegP] = NULL;
110 idealreg2debugmask [Op_VecS] = NULL;
111 idealreg2debugmask [Op_VecD] = NULL;
112 idealreg2debugmask [Op_VecX] = NULL;
113 idealreg2debugmask [Op_VecY] = NULL;
114
115 idealreg2mhdebugmask[Op_RegI] = NULL;
116 idealreg2mhdebugmask[Op_RegN] = NULL;
117 idealreg2mhdebugmask[Op_RegL] = NULL;
118 idealreg2mhdebugmask[Op_RegF] = NULL;
119 idealreg2mhdebugmask[Op_RegD] = NULL;
120 idealreg2mhdebugmask[Op_RegP] = NULL;
121 idealreg2mhdebugmask[Op_VecS] = NULL;
122 idealreg2mhdebugmask[Op_VecD] = NULL;
123 idealreg2mhdebugmask[Op_VecX] = NULL;
124 idealreg2mhdebugmask[Op_VecY] = NULL;
125
126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
127 }
128
129 //------------------------------warp_incoming_stk_arg------------------------
130 // This warps a VMReg into an OptoReg::Name
131 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
132 OptoReg::Name warped;
133 if( reg->is_stack() ) { // Stack slot argument?
134 warped = OptoReg::add(_old_SP, reg->reg2stack() );
135 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
136 if( warped >= _in_arg_limit )
137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
138 if (!RegMask::can_represent_arg(warped)) {
139 // the compiler cannot represent this method's calling sequence
140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
141 return OptoReg::Bad;
142 }
143 return warped;
144 }
145 return OptoReg::as_OptoReg(reg);
146 }
147
148 //---------------------------compute_old_SP------------------------------------
149 OptoReg::Name Compile::compute_old_SP() {
150 int fixed = fixed_slots();
151 int preserve = in_preserve_stack_slots();
152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
153 }
154
155
156
157 #ifdef ASSERT
158 void Matcher::verify_new_nodes_only(Node* xroot) {
159 // Make sure that the new graph only references new nodes
160 ResourceMark rm;
161 Unique_Node_List worklist;
162 VectorSet visited(Thread::current()->resource_area());
163 worklist.push(xroot);
164 while (worklist.size() > 0) {
165 Node* n = worklist.pop();
166 visited <<= n->_idx;
167 assert(C->node_arena()->contains(n), "dead node");
168 for (uint j = 0; j < n->req(); j++) {
169 Node* in = n->in(j);
170 if (in != NULL) {
171 assert(C->node_arena()->contains(in), "dead node");
172 if (!visited.test(in->_idx)) {
173 worklist.push(in);
174 }
175 }
176 }
177 }
178 }
179 #endif
180
181
182 //---------------------------match---------------------------------------------
183 void Matcher::match( ) {
184 if( MaxLabelRootDepth < 100 ) { // Too small?
185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
186 MaxLabelRootDepth = 100;
187 }
188 // One-time initialization of some register masks.
189 init_spill_mask( C->root()->in(1) );
190 _return_addr_mask = return_addr();
191 #ifdef _LP64
192 // Pointers take 2 slots in 64-bit land
193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
194 #endif
195
196 // Map a Java-signature return type into return register-value
197 // machine registers for 0, 1 and 2 returned values.
198 const TypeTuple *range = C->tf()->range();
199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
200 // Get ideal-register return type
201 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
202 // Get machine return register
203 uint sop = C->start()->Opcode();
204 OptoRegPair regs = return_value(ireg, false);
205
206 // And mask for same
207 _return_value_mask = RegMask(regs.first());
208 if( OptoReg::is_valid(regs.second()) )
209 _return_value_mask.Insert(regs.second());
210 }
211
212 // ---------------
213 // Frame Layout
214
215 // Need the method signature to determine the incoming argument types,
216 // because the types determine which registers the incoming arguments are
217 // in, and this affects the matched code.
218 const TypeTuple *domain = C->tf()->domain();
219 uint argcnt = domain->cnt() - TypeFunc::Parms;
220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
224 uint i;
225 for( i = 0; i<argcnt; i++ ) {
226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
227 }
228
229 // Pass array of ideal registers and length to USER code (from the AD file)
230 // that will convert this to an array of register numbers.
231 const StartNode *start = C->start();
232 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
233 #ifdef ASSERT
234 // Sanity check users' calling convention. Real handy while trying to
235 // get the initial port correct.
236 { for (uint i = 0; i<argcnt; i++) {
237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
239 _parm_regs[i].set_bad();
240 continue;
241 }
242 VMReg parm_reg = vm_parm_regs[i].first();
243 assert(parm_reg->is_valid(), "invalid arg?");
244 if (parm_reg->is_reg()) {
245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
246 assert(can_be_java_arg(opto_parm_reg) ||
247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
248 opto_parm_reg == inline_cache_reg(),
249 "parameters in register must be preserved by runtime stubs");
250 }
251 for (uint j = 0; j < i; j++) {
252 assert(parm_reg != vm_parm_regs[j].first(),
253 "calling conv. must produce distinct regs");
254 }
255 }
256 }
257 #endif
258
259 // Do some initial frame layout.
260
261 // Compute the old incoming SP (may be called FP) as
262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
263 _old_SP = C->compute_old_SP();
264 assert( is_even(_old_SP), "must be even" );
265
266 // Compute highest incoming stack argument as
267 // _old_SP + out_preserve_stack_slots + incoming argument size.
268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
269 assert( is_even(_in_arg_limit), "out_preserve must be even" );
270 for( i = 0; i < argcnt; i++ ) {
271 // Permit args to have no register
272 _calling_convention_mask[i].Clear();
273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
274 continue;
275 }
276 // calling_convention returns stack arguments as a count of
277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
278 // the allocators point of view, taking into account all the
279 // preserve area, locks & pad2.
280
281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
282 if( OptoReg::is_valid(reg1))
283 _calling_convention_mask[i].Insert(reg1);
284
285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
286 if( OptoReg::is_valid(reg2))
287 _calling_convention_mask[i].Insert(reg2);
288
289 // Saved biased stack-slot register number
290 _parm_regs[i].set_pair(reg2, reg1);
291 }
292
293 // Finally, make sure the incoming arguments take up an even number of
294 // words, in case the arguments or locals need to contain doubleword stack
295 // slots. The rest of the system assumes that stack slot pairs (in
296 // particular, in the spill area) which look aligned will in fact be
297 // aligned relative to the stack pointer in the target machine. Double
298 // stack slots will always be allocated aligned.
299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
300
301 // Compute highest outgoing stack argument as
302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
304 assert( is_even(_out_arg_limit), "out_preserve must be even" );
305
306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
307 // the compiler cannot represent this method's calling sequence
308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
309 }
310
311 if (C->failing()) return; // bailed out on incoming arg failure
312
313 // ---------------
314 // Collect roots of matcher trees. Every node for which
315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
316 // can be a valid interior of some tree.
317 find_shared( C->root() );
318 find_shared( C->top() );
319
320 C->print_method(PHASE_BEFORE_MATCHING);
321
322 // Create new ideal node ConP #NULL even if it does exist in old space
323 // to avoid false sharing if the corresponding mach node is not used.
324 // The corresponding mach node is only used in rare cases for derived
325 // pointers.
326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
327
328 // Swap out to old-space; emptying new-space
329 Arena *old = C->node_arena()->move_contents(C->old_arena());
330
331 // Save debug and profile information for nodes in old space:
332 _old_node_note_array = C->node_note_array();
333 if (_old_node_note_array != NULL) {
334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
335 (C->comp_arena(), _old_node_note_array->length(),
336 0, NULL));
337 }
338
339 // Pre-size the new_node table to avoid the need for range checks.
340 grow_new_node_array(C->unique());
341
342 // Reset node counter so MachNodes start with _idx at 0
343 int nodes = C->unique(); // save value
344 C->set_unique(0);
345 C->reset_dead_node_list();
346
347 // Recursively match trees from old space into new space.
348 // Correct leaves of new-space Nodes; they point to old-space.
349 _visited.Clear(); // Clear visit bits for xform call
350 C->set_cached_top_node(xform( C->top(), nodes ));
351 if (!C->failing()) {
352 Node* xroot = xform( C->root(), 1 );
353 if (xroot == NULL) {
354 Matcher::soft_match_failure(); // recursive matching process failed
355 C->record_method_not_compilable("instruction match failed");
356 } else {
357 // During matching shared constants were attached to C->root()
358 // because xroot wasn't available yet, so transfer the uses to
359 // the xroot.
360 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
361 Node* n = C->root()->fast_out(j);
362 if (C->node_arena()->contains(n)) {
363 assert(n->in(0) == C->root(), "should be control user");
364 n->set_req(0, xroot);
365 --j;
366 --jmax;
367 }
368 }
369
370 // Generate new mach node for ConP #NULL
371 assert(new_ideal_null != NULL, "sanity");
372 _mach_null = match_tree(new_ideal_null);
373 // Don't set control, it will confuse GCM since there are no uses.
374 // The control will be set when this node is used first time
375 // in find_base_for_derived().
376 assert(_mach_null != NULL, "");
377
378 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
379
380 #ifdef ASSERT
381 verify_new_nodes_only(xroot);
382 #endif
383 }
384 }
385 if (C->top() == NULL || C->root() == NULL) {
386 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
387 }
388 if (C->failing()) {
389 // delete old;
390 old->destruct_contents();
391 return;
392 }
393 assert( C->top(), "" );
394 assert( C->root(), "" );
395 validate_null_checks();
396
397 // Now smoke old-space
398 NOT_DEBUG( old->destruct_contents() );
399
400 // ------------------------
401 // Set up save-on-entry registers
402 Fixup_Save_On_Entry( );
403 }
404
405
406 //------------------------------Fixup_Save_On_Entry----------------------------
407 // The stated purpose of this routine is to take care of save-on-entry
408 // registers. However, the overall goal of the Match phase is to convert into
409 // machine-specific instructions which have RegMasks to guide allocation.
410 // So what this procedure really does is put a valid RegMask on each input
411 // to the machine-specific variations of all Return, TailCall and Halt
412 // instructions. It also adds edgs to define the save-on-entry values (and of
413 // course gives them a mask).
414
415 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
416 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
417 // Do all the pre-defined register masks
418 rms[TypeFunc::Control ] = RegMask::Empty;
419 rms[TypeFunc::I_O ] = RegMask::Empty;
420 rms[TypeFunc::Memory ] = RegMask::Empty;
421 rms[TypeFunc::ReturnAdr] = ret_adr;
422 rms[TypeFunc::FramePtr ] = fp;
423 return rms;
424 }
425
426 //---------------------------init_first_stack_mask-----------------------------
427 // Create the initial stack mask used by values spilling to the stack.
428 // Disallow any debug info in outgoing argument areas by setting the
429 // initial mask accordingly.
430 void Matcher::init_first_stack_mask() {
431
432 // Allocate storage for spill masks as masks for the appropriate load type.
433 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
434
435 idealreg2spillmask [Op_RegN] = &rms[0];
436 idealreg2spillmask [Op_RegI] = &rms[1];
437 idealreg2spillmask [Op_RegL] = &rms[2];
438 idealreg2spillmask [Op_RegF] = &rms[3];
439 idealreg2spillmask [Op_RegD] = &rms[4];
440 idealreg2spillmask [Op_RegP] = &rms[5];
441
442 idealreg2debugmask [Op_RegN] = &rms[6];
443 idealreg2debugmask [Op_RegI] = &rms[7];
444 idealreg2debugmask [Op_RegL] = &rms[8];
445 idealreg2debugmask [Op_RegF] = &rms[9];
446 idealreg2debugmask [Op_RegD] = &rms[10];
447 idealreg2debugmask [Op_RegP] = &rms[11];
448
449 idealreg2mhdebugmask[Op_RegN] = &rms[12];
450 idealreg2mhdebugmask[Op_RegI] = &rms[13];
451 idealreg2mhdebugmask[Op_RegL] = &rms[14];
452 idealreg2mhdebugmask[Op_RegF] = &rms[15];
453 idealreg2mhdebugmask[Op_RegD] = &rms[16];
454 idealreg2mhdebugmask[Op_RegP] = &rms[17];
455
456 idealreg2spillmask [Op_VecS] = &rms[18];
457 idealreg2spillmask [Op_VecD] = &rms[19];
458 idealreg2spillmask [Op_VecX] = &rms[20];
459 idealreg2spillmask [Op_VecY] = &rms[21];
460
461 OptoReg::Name i;
462
463 // At first, start with the empty mask
464 C->FIRST_STACK_mask().Clear();
465
466 // Add in the incoming argument area
467 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
468 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
469 C->FIRST_STACK_mask().Insert(i);
470
471 // Add in all bits past the outgoing argument area
472 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
473 "must be able to represent all call arguments in reg mask");
474 init = _out_arg_limit;
475 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
476 C->FIRST_STACK_mask().Insert(i);
477
478 // Finally, set the "infinite stack" bit.
479 C->FIRST_STACK_mask().set_AllStack();
480
481 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
482 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
483 // Keep spill masks aligned.
484 aligned_stack_mask.clear_to_pairs();
485 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
486
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
488 #ifdef _LP64
489 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
490 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
491 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
492 #else
493 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
494 #endif
495 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
496 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
497 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
498 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
499 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
500 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
501 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
502 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
503
504 if (Matcher::vector_size_supported(T_BYTE,4)) {
505 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
506 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
507 }
508 if (Matcher::vector_size_supported(T_FLOAT,2)) {
509 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
510 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
511 }
512 if (Matcher::vector_size_supported(T_FLOAT,4)) {
513 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
514 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
515 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
516 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
517 }
518 if (Matcher::vector_size_supported(T_FLOAT,8)) {
519 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
520 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
521 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
522 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
523 }
524 if (UseFPUForSpilling) {
525 // This mask logic assumes that the spill operations are
526 // symmetric and that the registers involved are the same size.
527 // On sparc for instance we may have to use 64 bit moves will
528 // kill 2 registers when used with F0-F31.
529 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
530 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
531 #ifdef _LP64
532 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
533 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
534 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
535 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
536 #else
537 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
538 #ifdef ARM
539 // ARM has support for moving 64bit values between a pair of
540 // integer registers and a double register
541 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
542 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
543 #endif
544 #endif
545 }
546
547 // Make up debug masks. Any spill slot plus callee-save registers.
548 // Caller-save registers are assumed to be trashable by the various
549 // inline-cache fixup routines.
550 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
551 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
552 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
553 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
554 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
555 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
556
557 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
558 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
559 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
560 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
561 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
562 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
563
564 // Prevent stub compilations from attempting to reference
565 // callee-saved registers from debug info
566 bool exclude_soe = !Compile::current()->is_method_compilation();
567
568 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
569 // registers the caller has to save do not work
570 if( _register_save_policy[i] == 'C' ||
571 _register_save_policy[i] == 'A' ||
572 (_register_save_policy[i] == 'E' && exclude_soe) ) {
573 idealreg2debugmask [Op_RegN]->Remove(i);
574 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
575 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
576 idealreg2debugmask [Op_RegF]->Remove(i); // masks
577 idealreg2debugmask [Op_RegD]->Remove(i);
578 idealreg2debugmask [Op_RegP]->Remove(i);
579
580 idealreg2mhdebugmask[Op_RegN]->Remove(i);
581 idealreg2mhdebugmask[Op_RegI]->Remove(i);
582 idealreg2mhdebugmask[Op_RegL]->Remove(i);
583 idealreg2mhdebugmask[Op_RegF]->Remove(i);
584 idealreg2mhdebugmask[Op_RegD]->Remove(i);
585 idealreg2mhdebugmask[Op_RegP]->Remove(i);
586 }
587 }
588
589 // Subtract the register we use to save the SP for MethodHandle
590 // invokes to from the debug mask.
591 const RegMask save_mask = method_handle_invoke_SP_save_mask();
592 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
593 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
594 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
595 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
596 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
597 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
598 }
599
600 //---------------------------is_save_on_entry----------------------------------
601 bool Matcher::is_save_on_entry( int reg ) {
602 return
603 _register_save_policy[reg] == 'E' ||
604 _register_save_policy[reg] == 'A' || // Save-on-entry register?
605 // Also save argument registers in the trampolining stubs
606 (C->save_argument_registers() && is_spillable_arg(reg));
607 }
608
609 //---------------------------Fixup_Save_On_Entry-------------------------------
610 void Matcher::Fixup_Save_On_Entry( ) {
611 init_first_stack_mask();
612
613 Node *root = C->root(); // Short name for root
614 // Count number of save-on-entry registers.
615 uint soe_cnt = number_of_saved_registers();
616 uint i;
617
618 // Find the procedure Start Node
619 StartNode *start = C->start();
620 assert( start, "Expect a start node" );
621
622 // Save argument registers in the trampolining stubs
623 if( C->save_argument_registers() )
624 for( i = 0; i < _last_Mach_Reg; i++ )
625 if( is_spillable_arg(i) )
626 soe_cnt++;
627
628 // Input RegMask array shared by all Returns.
629 // The type for doubles and longs has a count of 2, but
630 // there is only 1 returned value
631 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
632 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
633 // Returns have 0 or 1 returned values depending on call signature.
634 // Return register is specified by return_value in the AD file.
635 if (ret_edge_cnt > TypeFunc::Parms)
636 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
637
638 // Input RegMask array shared by all Rethrows.
639 uint reth_edge_cnt = TypeFunc::Parms+1;
640 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
641 // Rethrow takes exception oop only, but in the argument 0 slot.
642 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
643 #ifdef _LP64
644 // Need two slots for ptrs in 64-bit land
645 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
646 #endif
647
648 // Input RegMask array shared by all TailCalls
649 uint tail_call_edge_cnt = TypeFunc::Parms+2;
650 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
651
652 // Input RegMask array shared by all TailJumps
653 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
654 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
655
656 // TailCalls have 2 returned values (target & moop), whose masks come
657 // from the usual MachNode/MachOper mechanism. Find a sample
658 // TailCall to extract these masks and put the correct masks into
659 // the tail_call_rms array.
660 for( i=1; i < root->req(); i++ ) {
661 MachReturnNode *m = root->in(i)->as_MachReturn();
662 if( m->ideal_Opcode() == Op_TailCall ) {
663 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
664 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
665 break;
666 }
667 }
668
669 // TailJumps have 2 returned values (target & ex_oop), whose masks come
670 // from the usual MachNode/MachOper mechanism. Find a sample
671 // TailJump to extract these masks and put the correct masks into
672 // the tail_jump_rms array.
673 for( i=1; i < root->req(); i++ ) {
674 MachReturnNode *m = root->in(i)->as_MachReturn();
675 if( m->ideal_Opcode() == Op_TailJump ) {
676 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
677 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
678 break;
679 }
680 }
681
682 // Input RegMask array shared by all Halts
683 uint halt_edge_cnt = TypeFunc::Parms;
684 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
685
686 // Capture the return input masks into each exit flavor
687 for( i=1; i < root->req(); i++ ) {
688 MachReturnNode *exit = root->in(i)->as_MachReturn();
689 switch( exit->ideal_Opcode() ) {
690 case Op_Return : exit->_in_rms = ret_rms; break;
691 case Op_Rethrow : exit->_in_rms = reth_rms; break;
692 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
693 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
694 case Op_Halt : exit->_in_rms = halt_rms; break;
695 default : ShouldNotReachHere();
696 }
697 }
698
699 // Next unused projection number from Start.
700 int proj_cnt = C->tf()->domain()->cnt();
701
702 // Do all the save-on-entry registers. Make projections from Start for
703 // them, and give them a use at the exit points. To the allocator, they
704 // look like incoming register arguments.
705 for( i = 0; i < _last_Mach_Reg; i++ ) {
706 if( is_save_on_entry(i) ) {
707
708 // Add the save-on-entry to the mask array
709 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
710 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
711 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
712 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
713 // Halts need the SOE registers, but only in the stack as debug info.
714 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
715 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
716
717 Node *mproj;
718
719 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
720 // into a single RegD.
721 if( (i&1) == 0 &&
722 _register_save_type[i ] == Op_RegF &&
723 _register_save_type[i+1] == Op_RegF &&
724 is_save_on_entry(i+1) ) {
725 // Add other bit for double
726 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
727 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
728 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
729 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
730 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
731 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
732 proj_cnt += 2; // Skip 2 for doubles
733 }
734 else if( (i&1) == 1 && // Else check for high half of double
735 _register_save_type[i-1] == Op_RegF &&
736 _register_save_type[i ] == Op_RegF &&
737 is_save_on_entry(i-1) ) {
738 ret_rms [ ret_edge_cnt] = RegMask::Empty;
739 reth_rms [ reth_edge_cnt] = RegMask::Empty;
740 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
741 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
742 halt_rms [ halt_edge_cnt] = RegMask::Empty;
743 mproj = C->top();
744 }
745 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
746 // into a single RegL.
747 else if( (i&1) == 0 &&
748 _register_save_type[i ] == Op_RegI &&
749 _register_save_type[i+1] == Op_RegI &&
750 is_save_on_entry(i+1) ) {
751 // Add other bit for long
752 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
753 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
754 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
755 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
756 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
757 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
758 proj_cnt += 2; // Skip 2 for longs
759 }
760 else if( (i&1) == 1 && // Else check for high half of long
761 _register_save_type[i-1] == Op_RegI &&
762 _register_save_type[i ] == Op_RegI &&
763 is_save_on_entry(i-1) ) {
764 ret_rms [ ret_edge_cnt] = RegMask::Empty;
765 reth_rms [ reth_edge_cnt] = RegMask::Empty;
766 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
767 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
768 halt_rms [ halt_edge_cnt] = RegMask::Empty;
769 mproj = C->top();
770 } else {
771 // Make a projection for it off the Start
772 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
773 }
774
775 ret_edge_cnt ++;
776 reth_edge_cnt ++;
777 tail_call_edge_cnt ++;
778 tail_jump_edge_cnt ++;
779 halt_edge_cnt ++;
780
781 // Add a use of the SOE register to all exit paths
782 for( uint j=1; j < root->req(); j++ )
783 root->in(j)->add_req(mproj);
784 } // End of if a save-on-entry register
785 } // End of for all machine registers
786 }
787
788 //------------------------------init_spill_mask--------------------------------
789 void Matcher::init_spill_mask( Node *ret ) {
790 if( idealreg2regmask[Op_RegI] ) return; // One time only init
791
792 OptoReg::c_frame_pointer = c_frame_pointer();
793 c_frame_ptr_mask = c_frame_pointer();
794 #ifdef _LP64
795 // pointers are twice as big
796 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
797 #endif
798
799 // Start at OptoReg::stack0()
800 STACK_ONLY_mask.Clear();
801 OptoReg::Name init = OptoReg::stack2reg(0);
802 // STACK_ONLY_mask is all stack bits
803 OptoReg::Name i;
804 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
805 STACK_ONLY_mask.Insert(i);
806 // Also set the "infinite stack" bit.
807 STACK_ONLY_mask.set_AllStack();
808
809 // Copy the register names over into the shared world
810 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
811 // SharedInfo::regName[i] = regName[i];
812 // Handy RegMasks per machine register
813 mreg2regmask[i].Insert(i);
814 }
815
816 // Grab the Frame Pointer
817 Node *fp = ret->in(TypeFunc::FramePtr);
818 Node *mem = ret->in(TypeFunc::Memory);
819 const TypePtr* atp = TypePtr::BOTTOM;
820 // Share frame pointer while making spill ops
821 set_shared(fp);
822
823 // Compute generic short-offset Loads
824 #ifdef _LP64
825 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
826 #endif
827 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp));
828 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp));
829 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp));
830 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp));
831 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
832 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
833 spillD != NULL && spillP != NULL, "");
834
835 // Get the ADLC notion of the right regmask, for each basic type.
836 #ifdef _LP64
837 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
838 #endif
839 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
840 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
841 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
842 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
843 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
844
845 // Vector regmasks.
846 if (Matcher::vector_size_supported(T_BYTE,4)) {
847 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
848 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
849 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
850 }
851 if (Matcher::vector_size_supported(T_FLOAT,2)) {
852 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
853 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
854 }
855 if (Matcher::vector_size_supported(T_FLOAT,4)) {
856 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
857 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
858 }
859 if (Matcher::vector_size_supported(T_FLOAT,8)) {
860 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
861 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
862 }
863 }
864
865 #ifdef ASSERT
866 static void match_alias_type(Compile* C, Node* n, Node* m) {
867 if (!VerifyAliases) return; // do not go looking for trouble by default
868 const TypePtr* nat = n->adr_type();
869 const TypePtr* mat = m->adr_type();
870 int nidx = C->get_alias_index(nat);
871 int midx = C->get_alias_index(mat);
872 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
873 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
874 for (uint i = 1; i < n->req(); i++) {
875 Node* n1 = n->in(i);
876 const TypePtr* n1at = n1->adr_type();
877 if (n1at != NULL) {
878 nat = n1at;
879 nidx = C->get_alias_index(n1at);
880 }
881 }
882 }
883 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
884 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
885 switch (n->Opcode()) {
886 case Op_PrefetchRead:
887 case Op_PrefetchWrite:
888 case Op_PrefetchAllocation:
889 nidx = Compile::AliasIdxRaw;
890 nat = TypeRawPtr::BOTTOM;
891 break;
892 }
893 }
894 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
895 switch (n->Opcode()) {
896 case Op_ClearArray:
897 midx = Compile::AliasIdxRaw;
898 mat = TypeRawPtr::BOTTOM;
899 break;
900 }
901 }
902 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
903 switch (n->Opcode()) {
904 case Op_Return:
905 case Op_Rethrow:
906 case Op_Halt:
907 case Op_TailCall:
908 case Op_TailJump:
909 nidx = Compile::AliasIdxBot;
910 nat = TypePtr::BOTTOM;
911 break;
912 }
913 }
914 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
915 switch (n->Opcode()) {
916 case Op_StrComp:
917 case Op_StrEquals:
918 case Op_StrIndexOf:
919 case Op_AryEq:
920 case Op_MemBarVolatile:
921 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
922 case Op_EncodeISOArray:
923 nidx = Compile::AliasIdxTop;
924 nat = NULL;
925 break;
926 }
927 }
928 if (nidx != midx) {
929 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
930 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
931 n->dump();
932 m->dump();
933 }
934 assert(C->subsume_loads() && C->must_alias(nat, midx),
935 "must not lose alias info when matching");
936 }
937 }
938 #endif
939
940
941 //------------------------------MStack-----------------------------------------
942 // State and MStack class used in xform() and find_shared() iterative methods.
943 enum Node_State { Pre_Visit, // node has to be pre-visited
944 Visit, // visit node
945 Post_Visit, // post-visit node
946 Alt_Post_Visit // alternative post-visit path
947 };
948
949 class MStack: public Node_Stack {
950 public:
951 MStack(int size) : Node_Stack(size) { }
952
953 void push(Node *n, Node_State ns) {
954 Node_Stack::push(n, (uint)ns);
955 }
956 void push(Node *n, Node_State ns, Node *parent, int indx) {
957 ++_inode_top;
958 if ((_inode_top + 1) >= _inode_max) grow();
959 _inode_top->node = parent;
960 _inode_top->indx = (uint)indx;
961 ++_inode_top;
962 _inode_top->node = n;
963 _inode_top->indx = (uint)ns;
964 }
965 Node *parent() {
966 pop();
967 return node();
968 }
969 Node_State state() const {
970 return (Node_State)index();
971 }
972 void set_state(Node_State ns) {
973 set_index((uint)ns);
974 }
975 };
976
977
978 //------------------------------xform------------------------------------------
979 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
980 // Node in new-space. Given a new-space Node, recursively walk his children.
981 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
982 Node *Matcher::xform( Node *n, int max_stack ) {
983 // Use one stack to keep both: child's node/state and parent's node/index
984 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
985 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
986
987 while (mstack.is_nonempty()) {
988 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
989 if (C->failing()) return NULL;
990 n = mstack.node(); // Leave node on stack
991 Node_State nstate = mstack.state();
992 if (nstate == Visit) {
993 mstack.set_state(Post_Visit);
994 Node *oldn = n;
995 // Old-space or new-space check
996 if (!C->node_arena()->contains(n)) {
997 // Old space!
998 Node* m;
999 if (has_new_node(n)) { // Not yet Label/Reduced
1000 m = new_node(n);
1001 } else {
1002 if (!is_dontcare(n)) { // Matcher can match this guy
1003 // Calls match special. They match alone with no children.
1004 // Their children, the incoming arguments, match normally.
1005 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1006 if (C->failing()) return NULL;
1007 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1008 } else { // Nothing the matcher cares about
1009 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1010 // Convert to machine-dependent projection
1011 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1012 #ifdef ASSERT
1013 _new2old_map.map(m->_idx, n);
1014 #endif
1015 if (m->in(0) != NULL) // m might be top
1016 collect_null_checks(m, n);
1017 } else { // Else just a regular 'ol guy
1018 m = n->clone(); // So just clone into new-space
1019 #ifdef ASSERT
1020 _new2old_map.map(m->_idx, n);
1021 #endif
1022 // Def-Use edges will be added incrementally as Uses
1023 // of this node are matched.
1024 assert(m->outcnt() == 0, "no Uses of this clone yet");
1025 }
1026 }
1027
1028 set_new_node(n, m); // Map old to new
1029 if (_old_node_note_array != NULL) {
1030 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1031 n->_idx);
1032 C->set_node_notes_at(m->_idx, nn);
1033 }
1034 debug_only(match_alias_type(C, n, m));
1035 }
1036 n = m; // n is now a new-space node
1037 mstack.set_node(n);
1038 }
1039
1040 // New space!
1041 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1042
1043 int i;
1044 // Put precedence edges on stack first (match them last).
1045 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1046 Node *m = oldn->in(i);
1047 if (m == NULL) break;
1048 // set -1 to call add_prec() instead of set_req() during Step1
1049 mstack.push(m, Visit, n, -1);
1050 }
1051
1052 // For constant debug info, I'd rather have unmatched constants.
1053 int cnt = n->req();
1054 JVMState* jvms = n->jvms();
1055 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1056
1057 // Now do only debug info. Clone constants rather than matching.
1058 // Constants are represented directly in the debug info without
1059 // the need for executable machine instructions.
1060 // Monitor boxes are also represented directly.
1061 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1062 Node *m = n->in(i); // Get input
1063 int op = m->Opcode();
1064 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1065 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1066 op == Op_ConF || op == Op_ConD || op == Op_ConL
1067 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1068 ) {
1069 m = m->clone();
1070 #ifdef ASSERT
1071 _new2old_map.map(m->_idx, n);
1072 #endif
1073 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1074 mstack.push(m->in(0), Visit, m, 0);
1075 } else {
1076 mstack.push(m, Visit, n, i);
1077 }
1078 }
1079
1080 // And now walk his children, and convert his inputs to new-space.
1081 for( ; i >= 0; --i ) { // For all normal inputs do
1082 Node *m = n->in(i); // Get input
1083 if(m != NULL)
1084 mstack.push(m, Visit, n, i);
1085 }
1086
1087 }
1088 else if (nstate == Post_Visit) {
1089 // Set xformed input
1090 Node *p = mstack.parent();
1091 if (p != NULL) { // root doesn't have parent
1092 int i = (int)mstack.index();
1093 if (i >= 0)
1094 p->set_req(i, n); // required input
1095 else if (i == -1)
1096 p->add_prec(n); // precedence input
1097 else
1098 ShouldNotReachHere();
1099 }
1100 mstack.pop(); // remove processed node from stack
1101 }
1102 else {
1103 ShouldNotReachHere();
1104 }
1105 } // while (mstack.is_nonempty())
1106 return n; // Return new-space Node
1107 }
1108
1109 //------------------------------warp_outgoing_stk_arg------------------------
1110 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1111 // Convert outgoing argument location to a pre-biased stack offset
1112 if (reg->is_stack()) {
1113 OptoReg::Name warped = reg->reg2stack();
1114 // Adjust the stack slot offset to be the register number used
1115 // by the allocator.
1116 warped = OptoReg::add(begin_out_arg_area, warped);
1117 // Keep track of the largest numbered stack slot used for an arg.
1118 // Largest used slot per call-site indicates the amount of stack
1119 // that is killed by the call.
1120 if( warped >= out_arg_limit_per_call )
1121 out_arg_limit_per_call = OptoReg::add(warped,1);
1122 if (!RegMask::can_represent_arg(warped)) {
1123 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1124 return OptoReg::Bad;
1125 }
1126 return warped;
1127 }
1128 return OptoReg::as_OptoReg(reg);
1129 }
1130
1131
1132 //------------------------------match_sfpt-------------------------------------
1133 // Helper function to match call instructions. Calls match special.
1134 // They match alone with no children. Their children, the incoming
1135 // arguments, match normally.
1136 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1137 MachSafePointNode *msfpt = NULL;
1138 MachCallNode *mcall = NULL;
1139 uint cnt;
1140 // Split out case for SafePoint vs Call
1141 CallNode *call;
1142 const TypeTuple *domain;
1143 ciMethod* method = NULL;
1144 bool is_method_handle_invoke = false; // for special kill effects
1145 if( sfpt->is_Call() ) {
1146 call = sfpt->as_Call();
1147 domain = call->tf()->domain();
1148 cnt = domain->cnt();
1149
1150 // Match just the call, nothing else
1151 MachNode *m = match_tree(call);
1152 if (C->failing()) return NULL;
1153 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1154
1155 // Copy data from the Ideal SafePoint to the machine version
1156 mcall = m->as_MachCall();
1157
1158 mcall->set_tf( call->tf());
1159 mcall->set_entry_point(call->entry_point());
1160 mcall->set_cnt( call->cnt());
1161
1162 if( mcall->is_MachCallJava() ) {
1163 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1164 const CallJavaNode *call_java = call->as_CallJava();
1165 method = call_java->method();
1166 mcall_java->_method = method;
1167 mcall_java->_bci = call_java->_bci;
1168 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1169 is_method_handle_invoke = call_java->is_method_handle_invoke();
1170 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1171 if (is_method_handle_invoke) {
1172 C->set_has_method_handle_invokes(true);
1173 }
1174 if( mcall_java->is_MachCallStaticJava() )
1175 mcall_java->as_MachCallStaticJava()->_name =
1176 call_java->as_CallStaticJava()->_name;
1177 if( mcall_java->is_MachCallDynamicJava() )
1178 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1179 call_java->as_CallDynamicJava()->_vtable_index;
1180 }
1181 else if( mcall->is_MachCallRuntime() ) {
1182 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1183 }
1184 msfpt = mcall;
1185 }
1186 // This is a non-call safepoint
1187 else {
1188 call = NULL;
1189 domain = NULL;
1190 MachNode *mn = match_tree(sfpt);
1191 if (C->failing()) return NULL;
1192 msfpt = mn->as_MachSafePoint();
1193 cnt = TypeFunc::Parms;
1194 }
1195
1196 // Advertise the correct memory effects (for anti-dependence computation).
1197 msfpt->set_adr_type(sfpt->adr_type());
1198
1199 // Allocate a private array of RegMasks. These RegMasks are not shared.
1200 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1201 // Empty them all.
1202 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1203
1204 // Do all the pre-defined non-Empty register masks
1205 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1206 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1207
1208 // Place first outgoing argument can possibly be put.
1209 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1210 assert( is_even(begin_out_arg_area), "" );
1211 // Compute max outgoing register number per call site.
1212 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1213 // Calls to C may hammer extra stack slots above and beyond any arguments.
1214 // These are usually backing store for register arguments for varargs.
1215 if( call != NULL && call->is_CallRuntime() )
1216 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1217
1218
1219 // Do the normal argument list (parameters) register masks
1220 int argcnt = cnt - TypeFunc::Parms;
1221 if( argcnt > 0 ) { // Skip it all if we have no args
1222 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1223 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1224 int i;
1225 for( i = 0; i < argcnt; i++ ) {
1226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1227 }
1228 // V-call to pick proper calling convention
1229 call->calling_convention( sig_bt, parm_regs, argcnt );
1230
1231 #ifdef ASSERT
1232 // Sanity check users' calling convention. Really handy during
1233 // the initial porting effort. Fairly expensive otherwise.
1234 { for (int i = 0; i<argcnt; i++) {
1235 if( !parm_regs[i].first()->is_valid() &&
1236 !parm_regs[i].second()->is_valid() ) continue;
1237 VMReg reg1 = parm_regs[i].first();
1238 VMReg reg2 = parm_regs[i].second();
1239 for (int j = 0; j < i; j++) {
1240 if( !parm_regs[j].first()->is_valid() &&
1241 !parm_regs[j].second()->is_valid() ) continue;
1242 VMReg reg3 = parm_regs[j].first();
1243 VMReg reg4 = parm_regs[j].second();
1244 if( !reg1->is_valid() ) {
1245 assert( !reg2->is_valid(), "valid halvsies" );
1246 } else if( !reg3->is_valid() ) {
1247 assert( !reg4->is_valid(), "valid halvsies" );
1248 } else {
1249 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1250 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1251 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1252 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1253 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1254 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1255 }
1256 }
1257 }
1258 }
1259 #endif
1260
1261 // Visit each argument. Compute its outgoing register mask.
1262 // Return results now can have 2 bits returned.
1263 // Compute max over all outgoing arguments both per call-site
1264 // and over the entire method.
1265 for( i = 0; i < argcnt; i++ ) {
1266 // Address of incoming argument mask to fill in
1267 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1268 if( !parm_regs[i].first()->is_valid() &&
1269 !parm_regs[i].second()->is_valid() ) {
1270 continue; // Avoid Halves
1271 }
1272 // Grab first register, adjust stack slots and insert in mask.
1273 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1274 if (OptoReg::is_valid(reg1))
1275 rm->Insert( reg1 );
1276 // Grab second register (if any), adjust stack slots and insert in mask.
1277 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1278 if (OptoReg::is_valid(reg2))
1279 rm->Insert( reg2 );
1280 } // End of for all arguments
1281
1282 // Compute number of stack slots needed to restore stack in case of
1283 // Pascal-style argument popping.
1284 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1285 }
1286
1287 // Compute the max stack slot killed by any call. These will not be
1288 // available for debug info, and will be used to adjust FIRST_STACK_mask
1289 // after all call sites have been visited.
1290 if( _out_arg_limit < out_arg_limit_per_call)
1291 _out_arg_limit = out_arg_limit_per_call;
1292
1293 if (mcall) {
1294 // Kill the outgoing argument area, including any non-argument holes and
1295 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1296 // Since the max-per-method covers the max-per-call-site and debug info
1297 // is excluded on the max-per-method basis, debug info cannot land in
1298 // this killed area.
1299 uint r_cnt = mcall->tf()->range()->cnt();
1300 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1301 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1302 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1303 } else {
1304 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1305 proj->_rout.Insert(OptoReg::Name(i));
1306 }
1307 if (proj->_rout.is_NotEmpty()) {
1308 push_projection(proj);
1309 }
1310 }
1311 // Transfer the safepoint information from the call to the mcall
1312 // Move the JVMState list
1313 msfpt->set_jvms(sfpt->jvms());
1314 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1315 jvms->set_map(sfpt);
1316 }
1317
1318 // Debug inputs begin just after the last incoming parameter
1319 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1320 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1321
1322 // Move the OopMap
1323 msfpt->_oop_map = sfpt->_oop_map;
1324
1325 // Registers killed by the call are set in the local scheduling pass
1326 // of Global Code Motion.
1327 return msfpt;
1328 }
1329
1330 //---------------------------match_tree----------------------------------------
1331 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1332 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1333 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1334 // a Load's result RegMask for memoization in idealreg2regmask[]
1335 MachNode *Matcher::match_tree( const Node *n ) {
1336 assert( n->Opcode() != Op_Phi, "cannot match" );
1337 assert( !n->is_block_start(), "cannot match" );
1338 // Set the mark for all locally allocated State objects.
1339 // When this call returns, the _states_arena arena will be reset
1340 // freeing all State objects.
1341 ResourceMark rm( &_states_arena );
1342
1343 LabelRootDepth = 0;
1344
1345 // StoreNodes require their Memory input to match any LoadNodes
1346 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1347 #ifdef ASSERT
1348 Node* save_mem_node = _mem_node;
1349 _mem_node = n->is_Store() ? (Node*)n : NULL;
1350 #endif
1351 // State object for root node of match tree
1352 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1353 State *s = new (&_states_arena) State;
1354 s->_kids[0] = NULL;
1355 s->_kids[1] = NULL;
1356 s->_leaf = (Node*)n;
1357 // Label the input tree, allocating labels from top-level arena
1358 Label_Root( n, s, n->in(0), mem );
1359 if (C->failing()) return NULL;
1360
1361 // The minimum cost match for the whole tree is found at the root State
1362 uint mincost = max_juint;
1363 uint cost = max_juint;
1364 uint i;
1365 for( i = 0; i < NUM_OPERANDS; i++ ) {
1366 if( s->valid(i) && // valid entry and
1367 s->_cost[i] < cost && // low cost and
1368 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1369 cost = s->_cost[mincost=i];
1370 }
1371 if (mincost == max_juint) {
1372 #ifndef PRODUCT
1373 tty->print("No matching rule for:");
1374 s->dump();
1375 #endif
1376 Matcher::soft_match_failure();
1377 return NULL;
1378 }
1379 // Reduce input tree based upon the state labels to machine Nodes
1380 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1381 #ifdef ASSERT
1382 _old2new_map.map(n->_idx, m);
1383 _new2old_map.map(m->_idx, (Node*)n);
1384 #endif
1385
1386 // Add any Matcher-ignored edges
1387 uint cnt = n->req();
1388 uint start = 1;
1389 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1390 if( n->is_AddP() ) {
1391 assert( mem == (Node*)1, "" );
1392 start = AddPNode::Base+1;
1393 }
1394 for( i = start; i < cnt; i++ ) {
1395 if( !n->match_edge(i) ) {
1396 if( i < m->req() )
1397 m->ins_req( i, n->in(i) );
1398 else
1399 m->add_req( n->in(i) );
1400 }
1401 }
1402
1403 debug_only( _mem_node = save_mem_node; )
1404 return m;
1405 }
1406
1407
1408 //------------------------------match_into_reg---------------------------------
1409 // Choose to either match this Node in a register or part of the current
1410 // match tree. Return true for requiring a register and false for matching
1411 // as part of the current match tree.
1412 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1413
1414 const Type *t = m->bottom_type();
1415
1416 if (t->singleton()) {
1417 // Never force constants into registers. Allow them to match as
1418 // constants or registers. Copies of the same value will share
1419 // the same register. See find_shared_node.
1420 return false;
1421 } else { // Not a constant
1422 // Stop recursion if they have different Controls.
1423 Node* m_control = m->in(0);
1424 // Control of load's memory can post-dominates load's control.
1425 // So use it since load can't float above its memory.
1426 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1427 if (control && m_control && control != m_control && control != mem_control) {
1428
1429 // Actually, we can live with the most conservative control we
1430 // find, if it post-dominates the others. This allows us to
1431 // pick up load/op/store trees where the load can float a little
1432 // above the store.
1433 Node *x = control;
1434 const uint max_scan = 6; // Arbitrary scan cutoff
1435 uint j;
1436 for (j=0; j<max_scan; j++) {
1437 if (x->is_Region()) // Bail out at merge points
1438 return true;
1439 x = x->in(0);
1440 if (x == m_control) // Does 'control' post-dominate
1441 break; // m->in(0)? If so, we can use it
1442 if (x == mem_control) // Does 'control' post-dominate
1443 break; // mem_control? If so, we can use it
1444 }
1445 if (j == max_scan) // No post-domination before scan end?
1446 return true; // Then break the match tree up
1447 }
1448 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1449 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1450 // These are commonly used in address expressions and can
1451 // efficiently fold into them on X64 in some cases.
1452 return false;
1453 }
1454 }
1455
1456 // Not forceable cloning. If shared, put it into a register.
1457 return shared;
1458 }
1459
1460
1461 //------------------------------Instruction Selection--------------------------
1462 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1463 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1464 // things the Matcher does not match (e.g., Memory), and things with different
1465 // Controls (hence forced into different blocks). We pass in the Control
1466 // selected for this entire State tree.
1467
1468 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1469 // Store and the Load must have identical Memories (as well as identical
1470 // pointers). Since the Matcher does not have anything for Memory (and
1471 // does not handle DAGs), I have to match the Memory input myself. If the
1472 // Tree root is a Store, I require all Loads to have the identical memory.
1473 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1474 // Since Label_Root is a recursive function, its possible that we might run
1475 // out of stack space. See bugs 6272980 & 6227033 for more info.
1476 LabelRootDepth++;
1477 if (LabelRootDepth > MaxLabelRootDepth) {
1478 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1479 return NULL;
1480 }
1481 uint care = 0; // Edges matcher cares about
1482 uint cnt = n->req();
1483 uint i = 0;
1484
1485 // Examine children for memory state
1486 // Can only subsume a child into your match-tree if that child's memory state
1487 // is not modified along the path to another input.
1488 // It is unsafe even if the other inputs are separate roots.
1489 Node *input_mem = NULL;
1490 for( i = 1; i < cnt; i++ ) {
1491 if( !n->match_edge(i) ) continue;
1492 Node *m = n->in(i); // Get ith input
1493 assert( m, "expect non-null children" );
1494 if( m->is_Load() ) {
1495 if( input_mem == NULL ) {
1496 input_mem = m->in(MemNode::Memory);
1497 } else if( input_mem != m->in(MemNode::Memory) ) {
1498 input_mem = NodeSentinel;
1499 }
1500 }
1501 }
1502
1503 for( i = 1; i < cnt; i++ ){// For my children
1504 if( !n->match_edge(i) ) continue;
1505 Node *m = n->in(i); // Get ith input
1506 // Allocate states out of a private arena
1507 State *s = new (&_states_arena) State;
1508 svec->_kids[care++] = s;
1509 assert( care <= 2, "binary only for now" );
1510
1511 // Recursively label the State tree.
1512 s->_kids[0] = NULL;
1513 s->_kids[1] = NULL;
1514 s->_leaf = m;
1515
1516 // Check for leaves of the State Tree; things that cannot be a part of
1517 // the current tree. If it finds any, that value is matched as a
1518 // register operand. If not, then the normal matching is used.
1519 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1520 //
1521 // Stop recursion if this is LoadNode and the root of this tree is a
1522 // StoreNode and the load & store have different memories.
1523 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1524 // Can NOT include the match of a subtree when its memory state
1525 // is used by any of the other subtrees
1526 (input_mem == NodeSentinel) ) {
1527 #ifndef PRODUCT
1528 // Print when we exclude matching due to different memory states at input-loads
1529 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1530 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1531 tty->print_cr("invalid input_mem");
1532 }
1533 #endif
1534 // Switch to a register-only opcode; this value must be in a register
1535 // and cannot be subsumed as part of a larger instruction.
1536 s->DFA( m->ideal_reg(), m );
1537
1538 } else {
1539 // If match tree has no control and we do, adopt it for entire tree
1540 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1541 control = m->in(0); // Pick up control
1542 // Else match as a normal part of the match tree.
1543 control = Label_Root(m,s,control,mem);
1544 if (C->failing()) return NULL;
1545 }
1546 }
1547
1548
1549 // Call DFA to match this node, and return
1550 svec->DFA( n->Opcode(), n );
1551
1552 #ifdef ASSERT
1553 uint x;
1554 for( x = 0; x < _LAST_MACH_OPER; x++ )
1555 if( svec->valid(x) )
1556 break;
1557
1558 if (x >= _LAST_MACH_OPER) {
1559 n->dump();
1560 svec->dump();
1561 assert( false, "bad AD file" );
1562 }
1563 #endif
1564 return control;
1565 }
1566
1567
1568 // Con nodes reduced using the same rule can share their MachNode
1569 // which reduces the number of copies of a constant in the final
1570 // program. The register allocator is free to split uses later to
1571 // split live ranges.
1572 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1573 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1574
1575 // See if this Con has already been reduced using this rule.
1576 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1577 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1578 if (last != NULL && rule == last->rule()) {
1579 // Don't expect control change for DecodeN
1580 if (leaf->is_DecodeNarrowPtr())
1581 return last;
1582 // Get the new space root.
1583 Node* xroot = new_node(C->root());
1584 if (xroot == NULL) {
1585 // This shouldn't happen give the order of matching.
1586 return NULL;
1587 }
1588
1589 // Shared constants need to have their control be root so they
1590 // can be scheduled properly.
1591 Node* control = last->in(0);
1592 if (control != xroot) {
1593 if (control == NULL || control == C->root()) {
1594 last->set_req(0, xroot);
1595 } else {
1596 assert(false, "unexpected control");
1597 return NULL;
1598 }
1599 }
1600 return last;
1601 }
1602 return NULL;
1603 }
1604
1605
1606 //------------------------------ReduceInst-------------------------------------
1607 // Reduce a State tree (with given Control) into a tree of MachNodes.
1608 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1609 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1610 // Each MachNode has a number of complicated MachOper operands; each
1611 // MachOper also covers a further tree of Ideal Nodes.
1612
1613 // The root of the Ideal match tree is always an instruction, so we enter
1614 // the recursion here. After building the MachNode, we need to recurse
1615 // the tree checking for these cases:
1616 // (1) Child is an instruction -
1617 // Build the instruction (recursively), add it as an edge.
1618 // Build a simple operand (register) to hold the result of the instruction.
1619 // (2) Child is an interior part of an instruction -
1620 // Skip over it (do nothing)
1621 // (3) Child is the start of a operand -
1622 // Build the operand, place it inside the instruction
1623 // Call ReduceOper.
1624 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1625 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1626
1627 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1628 if (shared_node != NULL) {
1629 return shared_node;
1630 }
1631
1632 // Build the object to represent this state & prepare for recursive calls
1633 MachNode *mach = s->MachNodeGenerator( rule, C );
1634 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1635 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1636 Node *leaf = s->_leaf;
1637 // Check for instruction or instruction chain rule
1638 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1639 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1640 "duplicating node that's already been matched");
1641 // Instruction
1642 mach->add_req( leaf->in(0) ); // Set initial control
1643 // Reduce interior of complex instruction
1644 ReduceInst_Interior( s, rule, mem, mach, 1 );
1645 } else {
1646 // Instruction chain rules are data-dependent on their inputs
1647 mach->add_req(0); // Set initial control to none
1648 ReduceInst_Chain_Rule( s, rule, mem, mach );
1649 }
1650
1651 // If a Memory was used, insert a Memory edge
1652 if( mem != (Node*)1 ) {
1653 mach->ins_req(MemNode::Memory,mem);
1654 #ifdef ASSERT
1655 // Verify adr type after matching memory operation
1656 const MachOper* oper = mach->memory_operand();
1657 if (oper != NULL && oper != (MachOper*)-1) {
1658 // It has a unique memory operand. Find corresponding ideal mem node.
1659 Node* m = NULL;
1660 if (leaf->is_Mem()) {
1661 m = leaf;
1662 } else {
1663 m = _mem_node;
1664 assert(m != NULL && m->is_Mem(), "expecting memory node");
1665 }
1666 const Type* mach_at = mach->adr_type();
1667 // DecodeN node consumed by an address may have different type
1668 // then its input. Don't compare types for such case.
1669 if (m->adr_type() != mach_at &&
1670 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1671 m->in(MemNode::Address)->is_AddP() &&
1672 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1673 m->in(MemNode::Address)->is_AddP() &&
1674 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1675 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1676 mach_at = m->adr_type();
1677 }
1678 if (m->adr_type() != mach_at) {
1679 m->dump();
1680 tty->print_cr("mach:");
1681 mach->dump(1);
1682 }
1683 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1684 }
1685 #endif
1686 }
1687
1688 // If the _leaf is an AddP, insert the base edge
1689 if (leaf->is_AddP()) {
1690 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1691 }
1692
1693 uint number_of_projections_prior = number_of_projections();
1694
1695 // Perform any 1-to-many expansions required
1696 MachNode *ex = mach->Expand(s, _projection_list, mem);
1697 if (ex != mach) {
1698 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1699 if( ex->in(1)->is_Con() )
1700 ex->in(1)->set_req(0, C->root());
1701 // Remove old node from the graph
1702 for( uint i=0; i<mach->req(); i++ ) {
1703 mach->set_req(i,NULL);
1704 }
1705 #ifdef ASSERT
1706 _new2old_map.map(ex->_idx, s->_leaf);
1707 #endif
1708 }
1709
1710 // PhaseChaitin::fixup_spills will sometimes generate spill code
1711 // via the matcher. By the time, nodes have been wired into the CFG,
1712 // and any further nodes generated by expand rules will be left hanging
1713 // in space, and will not get emitted as output code. Catch this.
1714 // Also, catch any new register allocation constraints ("projections")
1715 // generated belatedly during spill code generation.
1716 if (_allocation_started) {
1717 guarantee(ex == mach, "no expand rules during spill generation");
1718 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1719 }
1720
1721 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1722 // Record the con for sharing
1723 _shared_nodes.map(leaf->_idx, ex);
1724 }
1725
1726 return ex;
1727 }
1728
1729 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1730 // 'op' is what I am expecting to receive
1731 int op = _leftOp[rule];
1732 // Operand type to catch childs result
1733 // This is what my child will give me.
1734 int opnd_class_instance = s->_rule[op];
1735 // Choose between operand class or not.
1736 // This is what I will receive.
1737 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1738 // New rule for child. Chase operand classes to get the actual rule.
1739 int newrule = s->_rule[catch_op];
1740
1741 if( newrule < NUM_OPERANDS ) {
1742 // Chain from operand or operand class, may be output of shared node
1743 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1744 "Bad AD file: Instruction chain rule must chain from operand");
1745 // Insert operand into array of operands for this instruction
1746 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1747
1748 ReduceOper( s, newrule, mem, mach );
1749 } else {
1750 // Chain from the result of an instruction
1751 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1752 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1753 Node *mem1 = (Node*)1;
1754 debug_only(Node *save_mem_node = _mem_node;)
1755 mach->add_req( ReduceInst(s, newrule, mem1) );
1756 debug_only(_mem_node = save_mem_node;)
1757 }
1758 return;
1759 }
1760
1761
1762 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1763 if( s->_leaf->is_Load() ) {
1764 Node *mem2 = s->_leaf->in(MemNode::Memory);
1765 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1766 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1767 mem = mem2;
1768 }
1769 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1770 if( mach->in(0) == NULL )
1771 mach->set_req(0, s->_leaf->in(0));
1772 }
1773
1774 // Now recursively walk the state tree & add operand list.
1775 for( uint i=0; i<2; i++ ) { // binary tree
1776 State *newstate = s->_kids[i];
1777 if( newstate == NULL ) break; // Might only have 1 child
1778 // 'op' is what I am expecting to receive
1779 int op;
1780 if( i == 0 ) {
1781 op = _leftOp[rule];
1782 } else {
1783 op = _rightOp[rule];
1784 }
1785 // Operand type to catch childs result
1786 // This is what my child will give me.
1787 int opnd_class_instance = newstate->_rule[op];
1788 // Choose between operand class or not.
1789 // This is what I will receive.
1790 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1791 // New rule for child. Chase operand classes to get the actual rule.
1792 int newrule = newstate->_rule[catch_op];
1793
1794 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1795 // Operand/operandClass
1796 // Insert operand into array of operands for this instruction
1797 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1798 ReduceOper( newstate, newrule, mem, mach );
1799
1800 } else { // Child is internal operand or new instruction
1801 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1802 // internal operand --> call ReduceInst_Interior
1803 // Interior of complex instruction. Do nothing but recurse.
1804 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1805 } else {
1806 // instruction --> call build operand( ) to catch result
1807 // --> ReduceInst( newrule )
1808 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1809 Node *mem1 = (Node*)1;
1810 debug_only(Node *save_mem_node = _mem_node;)
1811 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1812 debug_only(_mem_node = save_mem_node;)
1813 }
1814 }
1815 assert( mach->_opnds[num_opnds-1], "" );
1816 }
1817 return num_opnds;
1818 }
1819
1820 // This routine walks the interior of possible complex operands.
1821 // At each point we check our children in the match tree:
1822 // (1) No children -
1823 // We are a leaf; add _leaf field as an input to the MachNode
1824 // (2) Child is an internal operand -
1825 // Skip over it ( do nothing )
1826 // (3) Child is an instruction -
1827 // Call ReduceInst recursively and
1828 // and instruction as an input to the MachNode
1829 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1830 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1831 State *kid = s->_kids[0];
1832 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1833
1834 // Leaf? And not subsumed?
1835 if( kid == NULL && !_swallowed[rule] ) {
1836 mach->add_req( s->_leaf ); // Add leaf pointer
1837 return; // Bail out
1838 }
1839
1840 if( s->_leaf->is_Load() ) {
1841 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1842 mem = s->_leaf->in(MemNode::Memory);
1843 debug_only(_mem_node = s->_leaf;)
1844 }
1845 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1846 if( !mach->in(0) )
1847 mach->set_req(0,s->_leaf->in(0));
1848 else {
1849 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1850 }
1851 }
1852
1853 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1854 int newrule;
1855 if( i == 0)
1856 newrule = kid->_rule[_leftOp[rule]];
1857 else
1858 newrule = kid->_rule[_rightOp[rule]];
1859
1860 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1861 // Internal operand; recurse but do nothing else
1862 ReduceOper( kid, newrule, mem, mach );
1863
1864 } else { // Child is a new instruction
1865 // Reduce the instruction, and add a direct pointer from this
1866 // machine instruction to the newly reduced one.
1867 Node *mem1 = (Node*)1;
1868 debug_only(Node *save_mem_node = _mem_node;)
1869 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1870 debug_only(_mem_node = save_mem_node;)
1871 }
1872 }
1873 }
1874
1875
1876 // -------------------------------------------------------------------------
1877 // Java-Java calling convention
1878 // (what you use when Java calls Java)
1879
1880 //------------------------------find_receiver----------------------------------
1881 // For a given signature, return the OptoReg for parameter 0.
1882 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1883 VMRegPair regs;
1884 BasicType sig_bt = T_OBJECT;
1885 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1886 // Return argument 0 register. In the LP64 build pointers
1887 // take 2 registers, but the VM wants only the 'main' name.
1888 return OptoReg::as_OptoReg(regs.first());
1889 }
1890
1891 // A method-klass-holder may be passed in the inline_cache_reg
1892 // and then expanded into the inline_cache_reg and a method_oop register
1893 // defined in ad_<arch>.cpp
1894
1895
1896 //------------------------------find_shared------------------------------------
1897 // Set bits if Node is shared or otherwise a root
1898 void Matcher::find_shared( Node *n ) {
1899 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1900 MStack mstack(C->unique() * 2);
1901 // Mark nodes as address_visited if they are inputs to an address expression
1902 VectorSet address_visited(Thread::current()->resource_area());
1903 mstack.push(n, Visit); // Don't need to pre-visit root node
1904 while (mstack.is_nonempty()) {
1905 n = mstack.node(); // Leave node on stack
1906 Node_State nstate = mstack.state();
1907 uint nop = n->Opcode();
1908 if (nstate == Pre_Visit) {
1909 if (address_visited.test(n->_idx)) { // Visited in address already?
1910 // Flag as visited and shared now.
1911 set_visited(n);
1912 }
1913 if (is_visited(n)) { // Visited already?
1914 // Node is shared and has no reason to clone. Flag it as shared.
1915 // This causes it to match into a register for the sharing.
1916 set_shared(n); // Flag as shared and
1917 mstack.pop(); // remove node from stack
1918 continue;
1919 }
1920 nstate = Visit; // Not already visited; so visit now
1921 }
1922 if (nstate == Visit) {
1923 mstack.set_state(Post_Visit);
1924 set_visited(n); // Flag as visited now
1925 bool mem_op = false;
1926
1927 switch( nop ) { // Handle some opcodes special
1928 case Op_Phi: // Treat Phis as shared roots
1929 case Op_Parm:
1930 case Op_Proj: // All handled specially during matching
1931 case Op_SafePointScalarObject:
1932 set_shared(n);
1933 set_dontcare(n);
1934 break;
1935 case Op_If:
1936 case Op_CountedLoopEnd:
1937 mstack.set_state(Alt_Post_Visit); // Alternative way
1938 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1939 // with matching cmp/branch in 1 instruction. The Matcher needs the
1940 // Bool and CmpX side-by-side, because it can only get at constants
1941 // that are at the leaves of Match trees, and the Bool's condition acts
1942 // as a constant here.
1943 mstack.push(n->in(1), Visit); // Clone the Bool
1944 mstack.push(n->in(0), Pre_Visit); // Visit control input
1945 continue; // while (mstack.is_nonempty())
1946 case Op_ConvI2D: // These forms efficiently match with a prior
1947 case Op_ConvI2F: // Load but not a following Store
1948 if( n->in(1)->is_Load() && // Prior load
1949 n->outcnt() == 1 && // Not already shared
1950 n->unique_out()->is_Store() ) // Following store
1951 set_shared(n); // Force it to be a root
1952 break;
1953 case Op_ReverseBytesI:
1954 case Op_ReverseBytesL:
1955 if( n->in(1)->is_Load() && // Prior load
1956 n->outcnt() == 1 ) // Not already shared
1957 set_shared(n); // Force it to be a root
1958 break;
1959 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1960 case Op_IfFalse:
1961 case Op_IfTrue:
1962 case Op_MachProj:
1963 case Op_MergeMem:
1964 case Op_Catch:
1965 case Op_CatchProj:
1966 case Op_CProj:
1967 case Op_FlagsProj:
1968 case Op_JumpProj:
1969 case Op_JProj:
1970 case Op_NeverBranch:
1971 set_dontcare(n);
1972 break;
1973 case Op_Jump:
1974 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
1975 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1976 continue; // while (mstack.is_nonempty())
1977 case Op_StrComp:
1978 case Op_StrEquals:
1979 case Op_StrIndexOf:
1980 case Op_AryEq:
1981 case Op_EncodeISOArray:
1982 set_shared(n); // Force result into register (it will be anyways)
1983 break;
1984 case Op_ConP: { // Convert pointers above the centerline to NUL
1985 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1986 const TypePtr* tp = tn->type()->is_ptr();
1987 if (tp->_ptr == TypePtr::AnyNull) {
1988 tn->set_type(TypePtr::NULL_PTR);
1989 }
1990 break;
1991 }
1992 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1993 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1994 const TypePtr* tp = tn->type()->make_ptr();
1995 if (tp && tp->_ptr == TypePtr::AnyNull) {
1996 tn->set_type(TypeNarrowOop::NULL_PTR);
1997 }
1998 break;
1999 }
2000 case Op_Binary: // These are introduced in the Post_Visit state.
2001 ShouldNotReachHere();
2002 break;
2003 case Op_ClearArray:
2004 case Op_SafePoint:
2005 mem_op = true;
2006 break;
2007 default:
2008 if( n->is_Store() ) {
2009 // Do match stores, despite no ideal reg
2010 mem_op = true;
2011 break;
2012 }
2013 if( n->is_Mem() ) { // Loads and LoadStores
2014 mem_op = true;
2015 // Loads must be root of match tree due to prior load conflict
2016 if( C->subsume_loads() == false )
2017 set_shared(n);
2018 }
2019 // Fall into default case
2020 if( !n->ideal_reg() )
2021 set_dontcare(n); // Unmatchable Nodes
2022 } // end_switch
2023
2024 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2025 Node *m = n->in(i); // Get ith input
2026 if (m == NULL) continue; // Ignore NULLs
2027 uint mop = m->Opcode();
2028
2029 // Only push the input of a FlagsProj if it only has the FlagsProj
2030 // as output. Otherwise all inputs to the node that produces FlagsProj
2031 // will be marked as shared.
2032 if (n->is_FlagsProj()) {
2033 if (m->outcnt() == 1) {
2034 mstack.push(m, Visit);
2035 }
2036 continue; // for(int i = ...)
2037 }
2038 // Must clone all producers of flags, or we will not match correctly.
2039 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2040 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2041 // are also there, so we may match a float-branch to int-flags and
2042 // expect the allocator to haul the flags from the int-side to the
2043 // fp-side. No can do.
2044 if( _must_clone[mop] ) {
2045 mstack.push(m, Visit);
2046 continue; // for(int i = ...)
2047 }
2048
2049 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2050 // Bases used in addresses must be shared but since
2051 // they are shared through a DecodeN they may appear
2052 // to have a single use so force sharing here.
2053 set_shared(m->in(AddPNode::Base)->in(1));
2054 }
2055
2056 // Clone addressing expressions as they are "free" in memory access instructions
2057 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2058 // Some inputs for address expression are not put on stack
2059 // to avoid marking them as shared and forcing them into register
2060 // if they are used only in address expressions.
2061 // But they should be marked as shared if there are other uses
2062 // besides address expressions.
2063
2064 Node *off = m->in(AddPNode::Offset);
2065 if( off->is_Con() &&
2066 // When there are other uses besides address expressions
2067 // put it on stack and mark as shared.
2068 !is_visited(m) ) {
2069 address_visited.test_set(m->_idx); // Flag as address_visited
2070 Node *adr = m->in(AddPNode::Address);
2071
2072 // Intel, ARM and friends can handle 2 adds in addressing mode
2073 if( clone_shift_expressions && adr->is_AddP() &&
2074 // AtomicAdd is not an addressing expression.
2075 // Cheap to find it by looking for screwy base.
2076 !adr->in(AddPNode::Base)->is_top() &&
2077 // Are there other uses besides address expressions?
2078 !is_visited(adr) ) {
2079 address_visited.set(adr->_idx); // Flag as address_visited
2080 Node *shift = adr->in(AddPNode::Offset);
2081 // Check for shift by small constant as well
2082 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2083 shift->in(2)->get_int() <= 3 &&
2084 // Are there other uses besides address expressions?
2085 !is_visited(shift) ) {
2086 address_visited.set(shift->_idx); // Flag as address_visited
2087 mstack.push(shift->in(2), Visit);
2088 Node *conv = shift->in(1);
2089 #ifdef _LP64
2090 // Allow Matcher to match the rule which bypass
2091 // ConvI2L operation for an array index on LP64
2092 // if the index value is positive.
2093 if( conv->Opcode() == Op_ConvI2L &&
2094 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2095 // Are there other uses besides address expressions?
2096 !is_visited(conv) ) {
2097 address_visited.set(conv->_idx); // Flag as address_visited
2098 mstack.push(conv->in(1), Pre_Visit);
2099 } else
2100 #endif
2101 mstack.push(conv, Pre_Visit);
2102 } else {
2103 mstack.push(shift, Pre_Visit);
2104 }
2105 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2106 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2107 } else { // Sparc, Alpha, PPC and friends
2108 mstack.push(adr, Pre_Visit);
2109 }
2110
2111 // Clone X+offset as it also folds into most addressing expressions
2112 mstack.push(off, Visit);
2113 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2114 continue; // for(int i = ...)
2115 } // if( off->is_Con() )
2116 } // if( mem_op &&
2117 mstack.push(m, Pre_Visit);
2118 } // for(int i = ...)
2119 }
2120 else if (nstate == Alt_Post_Visit) {
2121 mstack.pop(); // Remove node from stack
2122 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2123 // shared and all users of the Bool need to move the Cmp in parallel.
2124 // This leaves both the Bool and the If pointing at the Cmp. To
2125 // prevent the Matcher from trying to Match the Cmp along both paths
2126 // BoolNode::match_edge always returns a zero.
2127
2128 // We reorder the Op_If in a pre-order manner, so we can visit without
2129 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2130 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2131 }
2132 else if (nstate == Post_Visit) {
2133 mstack.pop(); // Remove node from stack
2134
2135 // Now hack a few special opcodes
2136 switch( n->Opcode() ) { // Handle some opcodes special
2137 case Op_StorePConditional:
2138 case Op_StoreIConditional:
2139 case Op_StoreLConditional:
2140 case Op_CompareAndSwapI:
2141 case Op_CompareAndSwapL:
2142 case Op_CompareAndSwapP:
2143 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2144 Node *newval = n->in(MemNode::ValueIn );
2145 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2146 Node *pair = new (C) BinaryNode( oldval, newval );
2147 n->set_req(MemNode::ValueIn,pair);
2148 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2149 break;
2150 }
2151 case Op_CMoveD: // Convert trinary to binary-tree
2152 case Op_CMoveF:
2153 case Op_CMoveI:
2154 case Op_CMoveL:
2155 case Op_CMoveN:
2156 case Op_CMoveP: {
2157 // Restructure into a binary tree for Matching. It's possible that
2158 // we could move this code up next to the graph reshaping for IfNodes
2159 // or vice-versa, but I do not want to debug this for Ladybird.
2160 // 10/2/2000 CNC.
2161 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2162 n->set_req(1,pair1);
2163 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2164 n->set_req(2,pair2);
2165 n->del_req(3);
2166 break;
2167 }
2168 case Op_LoopLimit: {
2169 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2170 n->set_req(1,pair1);
2171 n->set_req(2,n->in(3));
2172 n->del_req(3);
2173 break;
2174 }
2175 case Op_StrEquals: {
2176 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2177 n->set_req(2,pair1);
2178 n->set_req(3,n->in(4));
2179 n->del_req(4);
2180 break;
2181 }
2182 case Op_StrComp:
2183 case Op_StrIndexOf: {
2184 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2185 n->set_req(2,pair1);
2186 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2187 n->set_req(3,pair2);
2188 n->del_req(5);
2189 n->del_req(4);
2190 break;
2191 }
2192 case Op_EncodeISOArray: {
2193 // Restructure into a binary tree for Matching.
2194 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2195 n->set_req(3, pair);
2196 n->del_req(4);
2197 break;
2198 }
2199 default:
2200 break;
2201 }
2202 }
2203 else {
2204 ShouldNotReachHere();
2205 }
2206 } // end of while (mstack.is_nonempty())
2207 }
2208
2209 #ifdef ASSERT
2210 // machine-independent root to machine-dependent root
2211 void Matcher::dump_old2new_map() {
2212 _old2new_map.dump();
2213 }
2214 #endif
2215
2216 //---------------------------collect_null_checks-------------------------------
2217 // Find null checks in the ideal graph; write a machine-specific node for
2218 // it. Used by later implicit-null-check handling. Actually collects
2219 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2220 // value being tested.
2221 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2222 Node *iff = proj->in(0);
2223 if( iff->Opcode() == Op_If ) {
2224 // During matching If's have Bool & Cmp side-by-side
2225 BoolNode *b = iff->in(1)->as_Bool();
2226 Node *cmp = iff->in(2);
2227 int opc = cmp->Opcode();
2228 if (opc != Op_CmpP && opc != Op_CmpN) return;
2229
2230 const Type* ct = cmp->in(2)->bottom_type();
2231 if (ct == TypePtr::NULL_PTR ||
2232 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2233
2234 bool push_it = false;
2235 if( proj->Opcode() == Op_IfTrue ) {
2236 extern int all_null_checks_found;
2237 all_null_checks_found++;
2238 if( b->_test._test == BoolTest::ne ) {
2239 push_it = true;
2240 }
2241 } else {
2242 assert( proj->Opcode() == Op_IfFalse, "" );
2243 if( b->_test._test == BoolTest::eq ) {
2244 push_it = true;
2245 }
2246 }
2247 if( push_it ) {
2248 _null_check_tests.push(proj);
2249 Node* val = cmp->in(1);
2250 #ifdef _LP64
2251 if (val->bottom_type()->isa_narrowoop() &&
2252 !Matcher::narrow_oop_use_complex_address()) {
2253 //
2254 // Look for DecodeN node which should be pinned to orig_proj.
2255 // On platforms (Sparc) which can not handle 2 adds
2256 // in addressing mode we have to keep a DecodeN node and
2257 // use it to do implicit NULL check in address.
2258 //
2259 // DecodeN node was pinned to non-null path (orig_proj) during
2260 // CastPP transformation in final_graph_reshaping_impl().
2261 //
2262 uint cnt = orig_proj->outcnt();
2263 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2264 Node* d = orig_proj->raw_out(i);
2265 if (d->is_DecodeN() && d->in(1) == val) {
2266 val = d;
2267 val->set_req(0, NULL); // Unpin now.
2268 // Mark this as special case to distinguish from
2269 // a regular case: CmpP(DecodeN, NULL).
2270 val = (Node*)(((intptr_t)val) | 1);
2271 break;
2272 }
2273 }
2274 }
2275 #endif
2276 _null_check_tests.push(val);
2277 }
2278 }
2279 }
2280 }
2281
2282 //---------------------------validate_null_checks------------------------------
2283 // Its possible that the value being NULL checked is not the root of a match
2284 // tree. If so, I cannot use the value in an implicit null check.
2285 void Matcher::validate_null_checks( ) {
2286 uint cnt = _null_check_tests.size();
2287 for( uint i=0; i < cnt; i+=2 ) {
2288 Node *test = _null_check_tests[i];
2289 Node *val = _null_check_tests[i+1];
2290 bool is_decoden = ((intptr_t)val) & 1;
2291 val = (Node*)(((intptr_t)val) & ~1);
2292 if (has_new_node(val)) {
2293 Node* new_val = new_node(val);
2294 if (is_decoden) {
2295 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2296 // Note: new_val may have a control edge if
2297 // the original ideal node DecodeN was matched before
2298 // it was unpinned in Matcher::collect_null_checks().
2299 // Unpin the mach node and mark it.
2300 new_val->set_req(0, NULL);
2301 new_val = (Node*)(((intptr_t)new_val) | 1);
2302 }
2303 // Is a match-tree root, so replace with the matched value
2304 _null_check_tests.map(i+1, new_val);
2305 } else {
2306 // Yank from candidate list
2307 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2308 _null_check_tests.map(i,_null_check_tests[--cnt]);
2309 _null_check_tests.pop();
2310 _null_check_tests.pop();
2311 i-=2;
2312 }
2313 }
2314 }
2315
2316 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2317 // atomic instruction acting as a store_load barrier without any
2318 // intervening volatile load, and thus we don't need a barrier here.
2319 // We retain the Node to act as a compiler ordering barrier.
2320 bool Matcher::post_store_load_barrier(const Node* vmb) {
2321 Compile* C = Compile::current();
2322 assert(vmb->is_MemBar(), "");
2323 assert(vmb->Opcode() != Op_MemBarAcquire, "");
2324 const MemBarNode* membar = vmb->as_MemBar();
2325
2326 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2327 Node* ctrl = NULL;
2328 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2329 Node* p = membar->fast_out(i);
2330 assert(p->is_Proj(), "only projections here");
2331 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2332 !C->node_arena()->contains(p)) { // Unmatched old-space only
2333 ctrl = p;
2334 break;
2335 }
2336 }
2337 assert((ctrl != NULL), "missing control projection");
2338
2339 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2340 Node *x = ctrl->fast_out(j);
2341 int xop = x->Opcode();
2342
2343 // We don't need current barrier if we see another or a lock
2344 // before seeing volatile load.
2345 //
2346 // Op_Fastunlock previously appeared in the Op_* list below.
2347 // With the advent of 1-0 lock operations we're no longer guaranteed
2348 // that a monitor exit operation contains a serializing instruction.
2349
2350 if (xop == Op_MemBarVolatile ||
2351 xop == Op_CompareAndSwapL ||
2352 xop == Op_CompareAndSwapP ||
2353 xop == Op_CompareAndSwapN ||
2354 xop == Op_CompareAndSwapI) {
2355 return true;
2356 }
2357
2358 // Op_FastLock previously appeared in the Op_* list above.
2359 // With biased locking we're no longer guaranteed that a monitor
2360 // enter operation contains a serializing instruction.
2361 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2362 return true;
2363 }
2364
2365 if (x->is_MemBar()) {
2366 // We must retain this membar if there is an upcoming volatile
2367 // load, which will be followed by acquire membar.
2368 if (xop == Op_MemBarAcquire) {
2369 return false;
2370 } else {
2371 // For other kinds of barriers, check by pretending we
2372 // are them, and seeing if we can be removed.
2373 return post_store_load_barrier(x->as_MemBar());
2374 }
2375 }
2376
2377 // probably not necessary to check for these
2378 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2379 return false;
2380 }
2381 }
2382 return false;
2383 }
2384
2385 //=============================================================================
2386 //---------------------------State---------------------------------------------
2387 State::State(void) {
2388 #ifdef ASSERT
2389 _id = 0;
2390 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2391 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2392 //memset(_cost, -1, sizeof(_cost));
2393 //memset(_rule, -1, sizeof(_rule));
2394 #endif
2395 memset(_valid, 0, sizeof(_valid));
2396 }
2397
2398 #ifdef ASSERT
2399 State::~State() {
2400 _id = 99;
2401 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2402 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2403 memset(_cost, -3, sizeof(_cost));
2404 memset(_rule, -3, sizeof(_rule));
2405 }
2406 #endif
2407
2408 #ifndef PRODUCT
2409 //---------------------------dump----------------------------------------------
2410 void State::dump() {
2411 tty->print("\n");
2412 dump(0);
2413 }
2414
2415 void State::dump(int depth) {
2416 for( int j = 0; j < depth; j++ )
2417 tty->print(" ");
2418 tty->print("--N: ");
2419 _leaf->dump();
2420 uint i;
2421 for( i = 0; i < _LAST_MACH_OPER; i++ )
2422 // Check for valid entry
2423 if( valid(i) ) {
2424 for( int j = 0; j < depth; j++ )
2425 tty->print(" ");
2426 assert(_cost[i] != max_juint, "cost must be a valid value");
2427 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2428 tty->print_cr("%s %d %s",
2429 ruleName[i], _cost[i], ruleName[_rule[i]] );
2430 }
2431 tty->print_cr("");
2432
2433 for( i=0; i<2; i++ )
2434 if( _kids[i] )
2435 _kids[i]->dump(depth+1);
2436 }
2437 #endif