1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding
492 }
493
494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
495 return 0;
496 }
497
498 #ifndef PRODUCT
499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
500 st->print("# MachConstantBaseNode (empty encoding)");
501 }
502 #endif
503
504
505 //=============================================================================
506 #ifndef PRODUCT
507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
508 Compile* C = ra_->C;
509
510 int framesize = C->frame_slots() << LogBytesPerInt;
511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
512 // Remove wordSize for return addr which is already pushed.
513 framesize -= wordSize;
514
515 if (C->need_stack_bang(framesize)) {
516 framesize -= wordSize;
517 st->print("# stack bang");
518 st->print("\n\t");
519 st->print("PUSH EBP\t# Save EBP");
520 if (framesize) {
521 st->print("\n\t");
522 st->print("SUB ESP, #%d\t# Create frame",framesize);
523 }
524 } else {
525 st->print("SUB ESP, #%d\t# Create frame",framesize);
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
529 }
530
531 if (VerifyStackAtCalls) {
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
535 }
536
537 if( C->in_24_bit_fp_mode() ) {
538 st->print("\n\t");
539 st->print("FLDCW \t# load 24 bit fpu control word");
540 }
541 if (UseSSE >= 2 && VerifyFPU) {
542 st->print("\n\t");
543 st->print("# verify FPU stack (must be clean on entry)");
544 }
545
546 #ifdef ASSERT
547 if (VerifyStackAtCalls) {
548 st->print("\n\t");
549 st->print("# stack alignment check");
550 }
551 #endif
552 st->cr();
553 }
554 #endif
555
556
557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
558 Compile* C = ra_->C;
559 MacroAssembler _masm(&cbuf);
560
561 int framesize = C->frame_slots() << LogBytesPerInt;
562
563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
564
565 C->set_frame_complete(cbuf.insts_size());
566
567 if (C->has_mach_constant_base_node()) {
568 // NOTE: We set the table base offset here because users might be
569 // emitted before MachConstantBaseNode.
570 Compile::ConstantTable& constant_table = C->constant_table();
571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
572 }
573 }
574
575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
576 return MachNode::size(ra_); // too many variables; just compute it the hard way
577 }
578
579 int MachPrologNode::reloc() const {
580 return 0; // a large enough number
581 }
582
583 //=============================================================================
584 #ifndef PRODUCT
585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
586 Compile *C = ra_->C;
587 int framesize = C->frame_slots() << LogBytesPerInt;
588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
589 // Remove two words for return addr and rbp,
590 framesize -= 2*wordSize;
591
592 if (C->max_vector_size() > 16) {
593 st->print("VZEROUPPER");
594 st->cr(); st->print("\t");
595 }
596 if (C->in_24_bit_fp_mode()) {
597 st->print("FLDCW standard control word");
598 st->cr(); st->print("\t");
599 }
600 if (framesize) {
601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
602 st->cr(); st->print("\t");
603 }
604 st->print_cr("POPL EBP"); st->print("\t");
605 if (do_polling() && C->is_method_compilation()) {
606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
607 st->cr(); st->print("\t");
608 }
609 }
610 #endif
611
612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
613 Compile *C = ra_->C;
614
615 if (C->max_vector_size() > 16) {
616 // Clear upper bits of YMM registers when current compiled code uses
617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
618 MacroAssembler masm(&cbuf);
619 masm.vzeroupper();
620 }
621 // If method set FPU control word, restore to standard control word
622 if (C->in_24_bit_fp_mode()) {
623 MacroAssembler masm(&cbuf);
624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
625 }
626
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
631
632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
633
634 if (framesize >= 128) {
635 emit_opcode(cbuf, 0x81); // add SP, #framesize
636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
637 emit_d32(cbuf, framesize);
638 } else if (framesize) {
639 emit_opcode(cbuf, 0x83); // add SP, #framesize
640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
643
644 emit_opcode(cbuf, 0x58 | EBP_enc);
645
646 if (do_polling() && C->is_method_compilation()) {
647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
648 emit_opcode(cbuf,0x85);
649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
651 }
652 }
653
654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656 // If method set FPU control word, restore to standard control word
657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
659 if (do_polling() && C->is_method_compilation()) size += 6;
660
661 int framesize = C->frame_slots() << LogBytesPerInt;
662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
663 // Remove two words for return addr and rbp,
664 framesize -= 2*wordSize;
665
666 size++; // popl rbp,
667
668 if (framesize >= 128) {
669 size += 6;
670 } else {
671 size += framesize ? 3 : 0;
672 }
673 return size;
674 }
675
676 int MachEpilogNode::reloc() const {
677 return 0; // a large enough number
678 }
679
680 const Pipeline * MachEpilogNode::pipeline() const {
681 return MachNode::pipeline_class();
682 }
683
684 int MachEpilogNode::safepoint_offset() const { return 0; }
685
686 //=============================================================================
687
688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
689 static enum RC rc_class( OptoReg::Name reg ) {
690
691 if( !OptoReg::is_valid(reg) ) return rc_bad;
692 if (OptoReg::is_stack(reg)) return rc_stack;
693
694 VMReg r = OptoReg::as_VMReg(reg);
695 if (r->is_Register()) return rc_int;
696 if (r->is_FloatRegister()) {
697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
698 return rc_float;
699 }
700 assert(r->is_XMMRegister(), "must be");
701 return rc_xmm;
702 }
703
704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
705 int opcode, const char *op_str, int size, outputStream* st ) {
706 if( cbuf ) {
707 emit_opcode (*cbuf, opcode );
708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
709 #ifndef PRODUCT
710 } else if( !do_size ) {
711 if( size != 0 ) st->print("\n\t");
712 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
715 } else { // FLD, FST, PUSH, POP
716 st->print("%s [ESP + #%d]",op_str,offset);
717 }
718 #endif
719 }
720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
721 return size+3+offset_size;
722 }
723
724 // Helper for XMM registers. Extra opcode bits, limited syntax.
725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
727 if (cbuf) {
728 MacroAssembler _masm(cbuf);
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) {
731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
732 } else {
733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
734 }
735 } else {
736 if (is_load) {
737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
738 } else {
739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
740 }
741 }
742 #ifndef PRODUCT
743 } else if (!do_size) {
744 if (size != 0) st->print("\n\t");
745 if (reg_lo+1 == reg_hi) { // double move?
746 if (is_load) st->print("%s %s,[ESP + #%d]",
747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
748 Matcher::regName[reg_lo], offset);
749 else st->print("MOVSD [ESP + #%d],%s",
750 offset, Matcher::regName[reg_lo]);
751 } else {
752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSS [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 }
757 #endif
758 }
759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
761 return size+5+offset_size;
762 }
763
764
765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
766 int src_hi, int dst_hi, int size, outputStream* st ) {
767 if (cbuf) {
768 MacroAssembler _masm(cbuf);
769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
771 as_XMMRegister(Matcher::_regEncode[src_lo]));
772 } else {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
774 as_XMMRegister(Matcher::_regEncode[src_lo]));
775 }
776 #ifndef PRODUCT
777 } else if (!do_size) {
778 if (size != 0) st->print("\n\t");
779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
782 } else {
783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
784 }
785 } else {
786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
788 } else {
789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
790 }
791 }
792 #endif
793 }
794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
795 // Only MOVAPS SSE prefix uses 1 byte.
796 int sz = 4;
797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
799 return size + sz;
800 }
801
802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
808 as_Register(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817
818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 int src_hi, int dst_hi, int size, outputStream* st ) {
820 // 32-bit
821 if (cbuf) {
822 MacroAssembler _masm(cbuf);
823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
824 as_XMMRegister(Matcher::_regEncode[src_lo]));
825 #ifndef PRODUCT
826 } else if (!do_size) {
827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
828 #endif
829 }
830 return 4;
831 }
832
833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
834 if( cbuf ) {
835 emit_opcode(*cbuf, 0x8B );
836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
837 #ifndef PRODUCT
838 } else if( !do_size ) {
839 if( size != 0 ) st->print("\n\t");
840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
841 #endif
842 }
843 return size+2;
844 }
845
846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
847 int offset, int size, outputStream* st ) {
848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
849 if( cbuf ) {
850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
852 #ifndef PRODUCT
853 } else if( !do_size ) {
854 if( size != 0 ) st->print("\n\t");
855 st->print("FLD %s",Matcher::regName[src_lo]);
856 #endif
857 }
858 size += 2;
859 }
860
861 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
862 const char *op_str;
863 int op;
864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
866 op = 0xDD;
867 } else { // 32-bit store
868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
869 op = 0xD9;
870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
871 }
872
873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
874 }
875
876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
878 int src_hi, int dst_hi, uint ireg, outputStream* st);
879
880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
881 int stack_offset, int reg, uint ireg, outputStream* st);
882
883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
884 int dst_offset, uint ireg, outputStream* st) {
885 int calc_size = 0;
886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
888 switch (ireg) {
889 case Op_VecS:
890 calc_size = 3+src_offset_size + 3+dst_offset_size;
891 break;
892 case Op_VecD:
893 calc_size = 3+src_offset_size + 3+dst_offset_size;
894 src_offset += 4;
895 dst_offset += 4;
896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
898 calc_size += 3+src_offset_size + 3+dst_offset_size;
899 break;
900 case Op_VecX:
901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
902 break;
903 case Op_VecY:
904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
905 break;
906 default:
907 ShouldNotReachHere();
908 }
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 int offset = __ offset();
912 switch (ireg) {
913 case Op_VecS:
914 __ pushl(Address(rsp, src_offset));
915 __ popl (Address(rsp, dst_offset));
916 break;
917 case Op_VecD:
918 __ pushl(Address(rsp, src_offset));
919 __ popl (Address(rsp, dst_offset));
920 __ pushl(Address(rsp, src_offset+4));
921 __ popl (Address(rsp, dst_offset+4));
922 break;
923 case Op_VecX:
924 __ movdqu(Address(rsp, -16), xmm0);
925 __ movdqu(xmm0, Address(rsp, src_offset));
926 __ movdqu(Address(rsp, dst_offset), xmm0);
927 __ movdqu(xmm0, Address(rsp, -16));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 int size = __ offset() - offset;
939 assert(size == calc_size, "incorrect size calculattion");
940 return size;
941 #ifndef PRODUCT
942 } else if (!do_size) {
943 switch (ireg) {
944 case Op_VecS:
945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
946 "popl [rsp + #%d]",
947 src_offset, dst_offset);
948 break;
949 case Op_VecD:
950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
951 "popq [rsp + #%d]\n\t"
952 "pushl [rsp + #%d]\n\t"
953 "popq [rsp + #%d]",
954 src_offset, dst_offset, src_offset+4, dst_offset+4);
955 break;
956 case Op_VecX:
957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
958 "movdqu xmm0, [rsp + #%d]\n\t"
959 "movdqu [rsp + #%d], xmm0\n\t"
960 "movdqu xmm0, [rsp - #16]",
961 src_offset, dst_offset);
962 break;
963 case Op_VecY:
964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
965 "vmovdqu xmm0, [rsp + #%d]\n\t"
966 "vmovdqu [rsp + #%d], xmm0\n\t"
967 "vmovdqu xmm0, [rsp - #32]",
968 src_offset, dst_offset);
969 break;
970 default:
971 ShouldNotReachHere();
972 }
973 #endif
974 }
975 return calc_size;
976 }
977
978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this );
983 OptoReg::Name dst_first = ra_->get_reg_first(this );
984
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
989
990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
991
992 // Generate spill code!
993 int size = 0;
994
995 if( src_first == dst_first && src_second == dst_second )
996 return size; // Self copy, no move
997
998 if (bottom_type()->isa_vect() != NULL) {
999 uint ireg = ideal_reg();
1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004 // mem -> mem
1005 int src_offset = ra_->reg2offset(src_first);
1006 int dst_offset = ra_->reg2offset(dst_first);
1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011 int stack_offset = ra_->reg2offset(dst_first);
1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014 int stack_offset = ra_->reg2offset(src_first);
1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1016 } else {
1017 ShouldNotReachHere();
1018 }
1019 }
1020
1021 // --------------------------------------
1022 // Check for mem-mem move. push/pop to move.
1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024 if( src_second == dst_first ) { // overlapping stack copy ranges
1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1029 }
1030 // move low bits
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1036 }
1037 return size;
1038 }
1039
1040 // --------------------------------------
1041 // Check for integer reg-reg copy
1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044
1045 // Check for integer store
1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048
1049 // Check for integer load
1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052
1053 // Check for integer reg-xmm reg copy
1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056 "no 64 bit integer-float reg moves" );
1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1059 // --------------------------------------
1060 // Check for float reg-reg copy
1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064 if( cbuf ) {
1065
1066 // Note the mucking with the register encode to compensate for the 0/1
1067 // indexing issue mentioned in a comment in the reg_def sections
1068 // for FPR registers many lines above here.
1069
1070 if( src_first != FPR1L_num ) {
1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 } else {
1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078 }
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083 else st->print( "FST %s", Matcher::regName[dst_first]);
1084 #endif
1085 }
1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087 }
1088
1089 // Check for float store
1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092 }
1093
1094 // Check for float load
1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096 int offset = ra_->reg2offset(src_first);
1097 const char *op_str;
1098 int op;
1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100 op_str = "FLD_D";
1101 op = 0xDD;
1102 } else { // 32-bit load
1103 op_str = "FLD_S";
1104 op = 0xD9;
1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106 }
1107 if( cbuf ) {
1108 emit_opcode (*cbuf, op );
1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113 } else if( !do_size ) {
1114 if( size != 0 ) st->print("\n\t");
1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117 }
1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119 return size + 3+offset_size+2;
1120 }
1121
1122 // Check for xmm reg-reg copy
1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125 (src_first+1 == src_second && dst_first+1 == dst_second),
1126 "no non-adjacent float-moves" );
1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128 }
1129
1130 // Check for xmm reg-integer reg copy
1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133 "no 64 bit float-integer reg moves" );
1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm store
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140 }
1141
1142 // Check for float xmm load
1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145 }
1146
1147 // Copy from float reg to xmm reg
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149 // copy to the top of stack from floating point reg
1150 // and use LEA to preserve flags
1151 if( cbuf ) {
1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155 emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157 } else if( !do_size ) {
1158 if( size != 0 ) st->print("\n\t");
1159 st->print("LEA ESP,[ESP-8]");
1160 #endif
1161 }
1162 size += 4;
1163
1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165
1166 // Copy from the temp memory to the xmm reg.
1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168
1169 if( cbuf ) {
1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173 emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175 } else if( !do_size ) {
1176 if( size != 0 ) st->print("\n\t");
1177 st->print("LEA ESP,[ESP+8]");
1178 #endif
1179 }
1180 size += 4;
1181 return size;
1182 }
1183
1184 assert( size > 0, "missed a case" );
1185
1186 // --------------------------------------------------------------------
1187 // Check for second bits still needing moving.
1188 if( src_second == dst_second )
1189 return size; // Self copy; no move
1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191
1192 // Check for second word int-int move
1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195
1196 // Check for second word integer store
1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199
1200 // Check for second word integer load
1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203
1204
1205 Unimplemented();
1206 }
1207
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210 implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215 implementation( &cbuf, ra_, false, NULL );
1216 }
1217
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219 return implementation( NULL, ra_, true, NULL );
1220 }
1221
1222
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227 int reg = ra_->get_reg_first(this);
1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_encode(this);
1235 if( offset >= 128 ) {
1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1237 emit_rm(cbuf, 0x2, reg, 0x04);
1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239 emit_d32(cbuf, offset);
1240 }
1241 else {
1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1243 emit_rm(cbuf, 0x1, reg, 0x04);
1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245 emit_d8(cbuf, offset);
1246 }
1247 }
1248
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 if( offset >= 128 ) {
1252 return 7;
1253 }
1254 else {
1255 return 4;
1256 }
1257 }
1258
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1264 st->print_cr("\tNOP");
1265 st->print_cr("\tNOP");
1266 if( !OptoBreakpoint )
1267 st->print_cr("\tNOP");
1268 }
1269 #endif
1270
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272 MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274 uint insts_size = cbuf.insts_size();
1275 #endif
1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277 masm.jump_cc(Assembler::notEqual,
1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279 /* WARNING these NOPs are critical so that verified entry point is properly
1280 aligned for patching by NativeJump::patch_verified_entry() */
1281 int nops_cnt = 2;
1282 if( !OptoBreakpoint ) // Leave space for int3
1283 nops_cnt += 1;
1284 masm.nop(nops_cnt);
1285
1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290 return OptoBreakpoint ? 11 : 12;
1291 }
1292
1293
1294 //=============================================================================
1295 uint size_exception_handler() {
1296 // NativeCall instruction size is the same as NativeJump.
1297 // exception handler starts out as jump and can be patched to
1298 // a call be deoptimization. (4932387)
1299 // Note that this value is also credited (in output.cpp) to
1300 // the size of the code section.
1301 return NativeJump::instruction_size;
1302 }
1303
1304 // Emit exception handler code. Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307
1308 // Note that the code buffer's insts_mark is always relative to insts.
1309 // That's why we must use the macroassembler to generate a handler.
1310 MacroAssembler _masm(&cbuf);
1311 address base =
1312 __ start_a_stub(size_exception_handler());
1313 if (base == NULL) return 0; // CodeBuffer::expand failed
1314 int offset = __ offset();
1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317 __ end_a_stub();
1318 return offset;
1319 }
1320
1321 uint size_deopt_handler() {
1322 // NativeCall instruction size is the same as NativeJump.
1323 // exception handler starts out as jump and can be patched to
1324 // a call be deoptimization. (4932387)
1325 // Note that this value is also credited (in output.cpp) to
1326 // the size of the code section.
1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 InternalAddress here(__ pc());
1341 __ pushptr(here.addr());
1342
1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345 __ end_a_stub();
1346 return offset;
1347 }
1348
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1352
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1357
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 // this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363 // The passed offset is relative to address of the branch.
1364 // On 86 a branch displacement is calculated relative to address
1365 // of a next instruction.
1366 offset -= br_size;
1367
1368 // the short version of jmpConUCF2 contains multiple branches,
1369 // making the reach slightly less
1370 if (rule == jmpConUCF2_rule)
1371 return (-126 <= offset && offset <= 125);
1372 return (-128 <= offset && offset <= 127);
1373 }
1374
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377 return false;
1378 }
1379
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400
1401 bool Matcher::narrow_oop_use_complex_address() {
1402 ShouldNotCallThis();
1403 return true;
1404 }
1405
1406 bool Matcher::narrow_klass_use_complex_address() {
1407 ShouldNotCallThis();
1408 return true;
1409 }
1410
1411
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers. Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed. Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece. Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423
1424
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426 // Get the memory operand from the node
1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430 uint opcnt = 1; // First operand
1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432 while( idx >= skipped+num_edges ) {
1433 skipped += num_edges;
1434 opcnt++; // Bump operand count
1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437 }
1438
1439 MachOper *memory = node->_opnds[opcnt];
1440 MachOper *new_memory = NULL;
1441 switch (memory->opcode()) {
1442 case DIRECT:
1443 case INDOFFSET32X:
1444 // No transformation necessary.
1445 return;
1446 case INDIRECT:
1447 new_memory = new (C) indirect_win95_safeOper( );
1448 break;
1449 case INDOFFSET8:
1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDOFFSET32:
1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXOFFSET:
1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457 break;
1458 case INDINDEXSCALE:
1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460 break;
1461 case INDINDEXSCALEOFFSET:
1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463 break;
1464 case LOAD_LONG_INDIRECT:
1465 case LOAD_LONG_INDOFFSET32:
1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467 return;
1468 default:
1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470 return;
1471 }
1472 node->_opnds[opcnt] = new_memory;
1473 }
1474
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485
1486 // Return whether or not this register is ever used as an argument. This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491 if( reg == ECX_num || reg == EDX_num ) return true;
1492 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494 return false;
1495 }
1496
1497 bool Matcher::is_spillable_arg( int reg ) {
1498 return can_be_java_arg(reg);
1499 }
1500
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502 // Use hardware integer DIV instruction when
1503 // it is faster than a code which use multiply.
1504 // Only when constant divisor fits into 32 bit
1505 // (min_jint is excluded to get only correct
1506 // positive 32 bit values from negative).
1507 return VM_Version::has_fast_idiv() &&
1508 (divisor == (int)divisor && divisor != min_jint);
1509 }
1510
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513 return EAX_REG_mask();
1514 }
1515
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518 return EDX_REG_mask();
1519 }
1520
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1540
1541 const RegMask Matcher::mathExactI_flags_proj_mask() {
1542 return INT_FLAGS_mask();
1543 }
1544
1545 // Returns true if the high 32 bits of the value is known to be zero.
1546 bool is_operand_hi32_zero(Node* n) {
1547 int opc = n->Opcode();
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1559
1560 %}
1561
1562 //----------ENCODING BLOCK-----------------------------------------------------
1563 // This block specifies the encoding classes used by the compiler to output
1564 // byte streams. Encoding classes generate functions which are called by
1565 // Machine Instruction Nodes in order to generate the bit encoding of the
1566 // instruction. Operands specify their base encoding interface with the
1567 // interface keyword. There are currently supported four interfaces,
1568 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1569 // operand to generate a function which returns its register number when
1570 // queried. CONST_INTER causes an operand to generate a function which
1571 // returns the value of the constant when queried. MEMORY_INTER causes an
1572 // operand to generate four functions which return the Base Register, the
1573 // Index Register, the Scale Value, and the Offset Value of the operand when
1574 // queried. COND_INTER causes an operand to generate six functions which
1575 // return the encoding code (ie - encoding bits for the instruction)
1576 // associated with each basic boolean condition for a conditional instruction.
1577 // Instructions specify two basic values for encoding. They use the
1578 // ins_encode keyword to specify their encoding class (which must be one of
1579 // the class names specified in the encoding block), and they use the
1580 // opcode keyword to specify, in order, their primary, secondary, and
1581 // tertiary opcode. Only the opcode sections which a particular instruction
1582 // needs for encoding need to be specified.
1583 encode %{
1584 // Build emit functions for each basic byte or larger field in the intel
1585 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1586 // code in the enc_class source block. Emit functions will live in the
1587 // main source block for now. In future, we can generalize this by
1588 // adding a syntax that specifies the sizes of fields in an order,
1589 // so that the adlc can build the emit functions automagically
1590
1591 // Emit primary opcode
1592 enc_class OpcP %{
1593 emit_opcode(cbuf, $primary);
1594 %}
1595
1596 // Emit secondary opcode
1597 enc_class OpcS %{
1598 emit_opcode(cbuf, $secondary);
1599 %}
1600
1601 // Emit opcode directly
1602 enc_class Opcode(immI d8) %{
1603 emit_opcode(cbuf, $d8$$constant);
1604 %}
1605
1606 enc_class SizePrefix %{
1607 emit_opcode(cbuf,0x66);
1608 %}
1609
1610 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1611 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1612 %}
1613
1614 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1615 emit_opcode(cbuf,$opcode$$constant);
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1618
1619 enc_class mov_r32_imm0( rRegI dst ) %{
1620 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1621 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1622 %}
1623
1624 enc_class cdq_enc %{
1625 // Full implementation of Java idiv and irem; checks for
1626 // special case as described in JVM spec., p.243 & p.271.
1627 //
1628 // normal case special case
1629 //
1630 // input : rax,: dividend min_int
1631 // reg: divisor -1
1632 //
1633 // output: rax,: quotient (= rax, idiv reg) min_int
1634 // rdx: remainder (= rax, irem reg) 0
1635 //
1636 // Code sequnce:
1637 //
1638 // 81 F8 00 00 00 80 cmp rax,80000000h
1639 // 0F 85 0B 00 00 00 jne normal_case
1640 // 33 D2 xor rdx,edx
1641 // 83 F9 FF cmp rcx,0FFh
1642 // 0F 84 03 00 00 00 je done
1643 // normal_case:
1644 // 99 cdq
1645 // F7 F9 idiv rax,ecx
1646 // done:
1647 //
1648 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1649 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1651 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1652 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1653 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1654 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1655 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1657 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1659 // normal_case:
1660 emit_opcode(cbuf,0x99); // cdq
1661 // idiv (note: must be emitted by the user of this rule)
1662 // normal:
1663 %}
1664
1665 // Dense encoding for older common ops
1666 enc_class Opc_plus(immI opcode, rRegI reg) %{
1667 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1668 %}
1669
1670
1671 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1672 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1673 // Check for 8-bit immediate, and set sign extend bit in opcode
1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1675 emit_opcode(cbuf, $primary | 0x02);
1676 }
1677 else { // If 32-bit immediate
1678 emit_opcode(cbuf, $primary);
1679 }
1680 %}
1681
1682 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1683 // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02); }
1687 else { // If 32-bit immediate
1688 emit_opcode(cbuf, $primary);
1689 }
1690 // Emit r/m byte with secondary opcode, after primary opcode.
1691 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1692 %}
1693
1694 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 $$$emit8$imm$$constant;
1698 }
1699 else { // If 32-bit immediate
1700 // Output immediate
1701 $$$emit32$imm$$constant;
1702 }
1703 %}
1704
1705 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1706 // Emit primary opcode and set sign-extend bit
1707 // Check for 8-bit immediate, and set sign extend bit in opcode
1708 int con = (int)$imm$$constant; // Throw away top bits
1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1710 // Emit r/m byte with secondary opcode, after primary opcode.
1711 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1713 else emit_d32(cbuf,con);
1714 %}
1715
1716 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with tertiary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1726
1727 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1728 emit_cc(cbuf, $secondary, $dst$$reg );
1729 %}
1730
1731 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1732 int destlo = $dst$$reg;
1733 int desthi = HIGH_FROM_LOW(destlo);
1734 // bswap lo
1735 emit_opcode(cbuf, 0x0F);
1736 emit_cc(cbuf, 0xC8, destlo);
1737 // bswap hi
1738 emit_opcode(cbuf, 0x0F);
1739 emit_cc(cbuf, 0xC8, desthi);
1740 // xchg lo and hi
1741 emit_opcode(cbuf, 0x87);
1742 emit_rm(cbuf, 0x3, destlo, desthi);
1743 %}
1744
1745 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1746 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1747 %}
1748
1749 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1750 $$$emit8$primary;
1751 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1752 %}
1753
1754 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1755 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1756 emit_d8(cbuf, op >> 8 );
1757 emit_d8(cbuf, op & 255);
1758 %}
1759
1760 // emulate a CMOV with a conditional branch around a MOV
1761 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1762 // Invert sense of branch from sense of CMOV
1763 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1764 emit_d8( cbuf, $brOffs$$constant );
1765 %}
1766
1767 enc_class enc_PartialSubtypeCheck( ) %{
1768 Register Redi = as_Register(EDI_enc); // result register
1769 Register Reax = as_Register(EAX_enc); // super class
1770 Register Recx = as_Register(ECX_enc); // killed
1771 Register Resi = as_Register(ESI_enc); // sub class
1772 Label miss;
1773
1774 MacroAssembler _masm(&cbuf);
1775 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1776 NULL, &miss,
1777 /*set_cond_codes:*/ true);
1778 if ($primary) {
1779 __ xorptr(Redi, Redi);
1780 }
1781 __ bind(miss);
1782 %}
1783
1784 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1785 MacroAssembler masm(&cbuf);
1786 int start = masm.offset();
1787 if (UseSSE >= 2) {
1788 if (VerifyFPU) {
1789 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1790 }
1791 } else {
1792 // External c_calling_convention expects the FPU stack to be 'clean'.
1793 // Compiled code leaves it dirty. Do cleanup now.
1794 masm.empty_FPU_stack();
1795 }
1796 if (sizeof_FFree_Float_Stack_All == -1) {
1797 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1798 } else {
1799 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1800 }
1801 %}
1802
1803 enc_class Verify_FPU_For_Leaf %{
1804 if( VerifyFPU ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1807 }
1808 %}
1809
1810 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1811 // This is the instruction starting address for relocation info.
1812 cbuf.set_insts_mark();
1813 $$$emit8$primary;
1814 // CALL directly to the runtime
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1816 runtime_call_Relocation::spec(), RELOC_IMM32 );
1817
1818 if (UseSSE >= 2) {
1819 MacroAssembler _masm(&cbuf);
1820 BasicType rt = tf()->return_type();
1821
1822 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1823 // A C runtime call where the return value is unused. In SSE2+
1824 // mode the result needs to be removed from the FPU stack. It's
1825 // likely that this function call could be removed by the
1826 // optimizer if the C function is a pure function.
1827 __ ffree(0);
1828 } else if (rt == T_FLOAT) {
1829 __ lea(rsp, Address(rsp, -4));
1830 __ fstp_s(Address(rsp, 0));
1831 __ movflt(xmm0, Address(rsp, 0));
1832 __ lea(rsp, Address(rsp, 4));
1833 } else if (rt == T_DOUBLE) {
1834 __ lea(rsp, Address(rsp, -8));
1835 __ fstp_d(Address(rsp, 0));
1836 __ movdbl(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 8));
1838 }
1839 }
1840 %}
1841
1842
1843 enc_class pre_call_resets %{
1844 // If method sets FPU control word restore it here
1845 debug_only(int off0 = cbuf.insts_size());
1846 if (ra_->C->in_24_bit_fp_mode()) {
1847 MacroAssembler _masm(&cbuf);
1848 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1849 }
1850 if (ra_->C->max_vector_size() > 16) {
1851 // Clear upper bits of YMM registers when current compiled code uses
1852 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1853 MacroAssembler _masm(&cbuf);
1854 __ vzeroupper();
1855 }
1856 debug_only(int off1 = cbuf.insts_size());
1857 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1858 %}
1859
1860 enc_class post_call_FPU %{
1861 // If method sets FPU control word do it here also
1862 if (Compile::current()->in_24_bit_fp_mode()) {
1863 MacroAssembler masm(&cbuf);
1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1865 }
1866 %}
1867
1868 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1869 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1870 // who we intended to call.
1871 cbuf.set_insts_mark();
1872 $$$emit8$primary;
1873 if (!_method) {
1874 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1875 runtime_call_Relocation::spec(), RELOC_IMM32 );
1876 } else if (_optimized_virtual) {
1877 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1878 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1879 } else {
1880 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1881 static_call_Relocation::spec(), RELOC_IMM32 );
1882 }
1883 if (_method) { // Emit stub for static call.
1884 CompiledStaticCall::emit_to_interp_stub(cbuf);
1885 }
1886 %}
1887
1888 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1889 MacroAssembler _masm(&cbuf);
1890 __ ic_call((address)$meth$$method);
1891 %}
1892
1893 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1894 int disp = in_bytes(Method::from_compiled_offset());
1895 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1896
1897 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1898 cbuf.set_insts_mark();
1899 $$$emit8$primary;
1900 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1901 emit_d8(cbuf, disp); // Displacement
1902
1903 %}
1904
1905 // Following encoding is no longer used, but may be restored if calling
1906 // convention changes significantly.
1907 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1908 //
1909 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1910 // // int ic_reg = Matcher::inline_cache_reg();
1911 // // int ic_encode = Matcher::_regEncode[ic_reg];
1912 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1913 // // int imo_encode = Matcher::_regEncode[imo_reg];
1914 //
1915 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1916 // // // so we load it immediately before the call
1917 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1918 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1919 //
1920 // // xor rbp,ebp
1921 // emit_opcode(cbuf, 0x33);
1922 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1923 //
1924 // // CALL to interpreter.
1925 // cbuf.set_insts_mark();
1926 // $$$emit8$primary;
1927 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1928 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1929 // %}
1930
1931 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1932 $$$emit8$primary;
1933 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1934 $$$emit8$shift$$constant;
1935 %}
1936
1937 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1941 $$$emit32$src$$constant;
1942 %}
1943
1944 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 emit_opcode(cbuf, $primary + $dst$$reg);
1948 $$$emit32$src$$constant;
1949 %}
1950
1951 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1952 // Load immediate does not have a zero or sign extended version
1953 // for 8-bit immediates
1954 int dst_enc = $dst$$reg;
1955 int src_con = $src$$constant & 0x0FFFFFFFFL;
1956 if (src_con == 0) {
1957 // xor dst, dst
1958 emit_opcode(cbuf, 0x33);
1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1960 } else {
1961 emit_opcode(cbuf, $primary + dst_enc);
1962 emit_d32(cbuf, src_con);
1963 }
1964 %}
1965
1966 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1967 // Load immediate does not have a zero or sign extended version
1968 // for 8-bit immediates
1969 int dst_enc = $dst$$reg + 2;
1970 int src_con = ((julong)($src$$constant)) >> 32;
1971 if (src_con == 0) {
1972 // xor dst, dst
1973 emit_opcode(cbuf, 0x33);
1974 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1975 } else {
1976 emit_opcode(cbuf, $primary + dst_enc);
1977 emit_d32(cbuf, src_con);
1978 }
1979 %}
1980
1981
1982 // Encode a reg-reg copy. If it is useless, then empty encoding.
1983 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1984 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1985 %}
1986
1987 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1988 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1989 %}
1990
1991 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 %}
1994
1995 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1996 $$$emit8$primary;
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
1999
2000 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$secondary;
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2007 %}
2008
2009 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2010 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2011 %}
2012
2013 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2014 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2015 %}
2016
2017 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2018 // Output immediate
2019 $$$emit32$src$$constant;
2020 %}
2021
2022 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2023 // Output Float immediate bits
2024 jfloat jf = $src$$constant;
2025 int jf_as_bits = jint_cast( jf );
2026 emit_d32(cbuf, jf_as_bits);
2027 %}
2028
2029 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2030 // Output Float immediate bits
2031 jfloat jf = $src$$constant;
2032 int jf_as_bits = jint_cast( jf );
2033 emit_d32(cbuf, jf_as_bits);
2034 %}
2035
2036 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2037 // Output immediate
2038 $$$emit16$src$$constant;
2039 %}
2040
2041 enc_class Con_d32(immI src) %{
2042 emit_d32(cbuf,$src$$constant);
2043 %}
2044
2045 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2046 // Output immediate memory reference
2047 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2048 emit_d32(cbuf, 0x00);
2049 %}
2050
2051 enc_class lock_prefix( ) %{
2052 if( os::is_MP() )
2053 emit_opcode(cbuf,0xF0); // [Lock]
2054 %}
2055
2056 // Cmp-xchg long value.
2057 // Note: we need to swap rbx, and rcx before and after the
2058 // cmpxchg8 instruction because the instruction uses
2059 // rcx as the high order word of the new value to store but
2060 // our register encoding uses rbx,.
2061 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2062
2063 // XCHG rbx,ecx
2064 emit_opcode(cbuf,0x87);
2065 emit_opcode(cbuf,0xD9);
2066 // [Lock]
2067 if( os::is_MP() )
2068 emit_opcode(cbuf,0xF0);
2069 // CMPXCHG8 [Eptr]
2070 emit_opcode(cbuf,0x0F);
2071 emit_opcode(cbuf,0xC7);
2072 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2073 // XCHG rbx,ecx
2074 emit_opcode(cbuf,0x87);
2075 emit_opcode(cbuf,0xD9);
2076 %}
2077
2078 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082
2083 // CMPXCHG [Eptr]
2084 emit_opcode(cbuf,0x0F);
2085 emit_opcode(cbuf,0xB1);
2086 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2087 %}
2088
2089 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2090 int res_encoding = $res$$reg;
2091
2092 // MOV res,0
2093 emit_opcode( cbuf, 0xB8 + res_encoding);
2094 emit_d32( cbuf, 0 );
2095 // JNE,s fail
2096 emit_opcode(cbuf,0x75);
2097 emit_d8(cbuf, 5 );
2098 // MOV res,1
2099 emit_opcode( cbuf, 0xB8 + res_encoding);
2100 emit_d32( cbuf, 1 );
2101 // fail:
2102 %}
2103
2104 enc_class set_instruction_start( ) %{
2105 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2106 %}
2107
2108 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2109 int reg_encoding = $ereg$$reg;
2110 int base = $mem$$base;
2111 int index = $mem$$index;
2112 int scale = $mem$$scale;
2113 int displace = $mem$$disp;
2114 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2115 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2116 %}
2117
2118 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2119 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2120 int base = $mem$$base;
2121 int index = $mem$$index;
2122 int scale = $mem$$scale;
2123 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2124 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2125 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2126 %}
2127
2128 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2129 int r1, r2;
2130 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2131 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2132 emit_opcode(cbuf,0x0F);
2133 emit_opcode(cbuf,$tertiary);
2134 emit_rm(cbuf, 0x3, r1, r2);
2135 emit_d8(cbuf,$cnt$$constant);
2136 emit_d8(cbuf,$primary);
2137 emit_rm(cbuf, 0x3, $secondary, r1);
2138 emit_d8(cbuf,$cnt$$constant);
2139 %}
2140
2141 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2142 emit_opcode( cbuf, 0x8B ); // Move
2143 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2144 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2145 emit_d8(cbuf,$primary);
2146 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2147 emit_d8(cbuf,$cnt$$constant-32);
2148 }
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2151 emit_d8(cbuf,31);
2152 %}
2153
2154 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2155 int r1, r2;
2156 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2157 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2158
2159 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2160 emit_rm(cbuf, 0x3, r1, r2);
2161 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2162 emit_opcode(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, r1);
2164 emit_d8(cbuf,$cnt$$constant-32);
2165 }
2166 emit_opcode(cbuf,0x33); // XOR r2,r2
2167 emit_rm(cbuf, 0x3, r2, r2);
2168 %}
2169
2170 // Clone of RegMem but accepts an extra parameter to access each
2171 // half of a double in memory; it never needs relocation info.
2172 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2173 emit_opcode(cbuf,$opcode$$constant);
2174 int reg_encoding = $rm_reg$$reg;
2175 int base = $mem$$base;
2176 int index = $mem$$index;
2177 int scale = $mem$$scale;
2178 int displace = $mem$$disp + $disp_for_half$$constant;
2179 relocInfo::relocType disp_reloc = relocInfo::none;
2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2181 %}
2182
2183 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2184 //
2185 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2186 // and it never needs relocation information.
2187 // Frequently used to move data between FPU's Stack Top and memory.
2188 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2189 int rm_byte_opcode = $rm_opcode$$constant;
2190 int base = $mem$$base;
2191 int index = $mem$$index;
2192 int scale = $mem$$scale;
2193 int displace = $mem$$disp;
2194 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2195 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2196 %}
2197
2198 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2199 int rm_byte_opcode = $rm_opcode$$constant;
2200 int base = $mem$$base;
2201 int index = $mem$$index;
2202 int scale = $mem$$scale;
2203 int displace = $mem$$disp;
2204 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2205 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2206 %}
2207
2208 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2209 int reg_encoding = $dst$$reg;
2210 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2211 int index = 0x04; // 0x04 indicates no index
2212 int scale = 0x00; // 0x00 indicates no scale
2213 int displace = $src1$$constant; // 0x00 indicates no displacement
2214 relocInfo::relocType disp_reloc = relocInfo::none;
2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2216 %}
2217
2218 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2219 // Compare dst,src
2220 emit_opcode(cbuf,0x3B);
2221 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2222 // jmp dst < src around move
2223 emit_opcode(cbuf,0x7C);
2224 emit_d8(cbuf,2);
2225 // move dst,src
2226 emit_opcode(cbuf,0x8B);
2227 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2228 %}
2229
2230 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2231 // Compare dst,src
2232 emit_opcode(cbuf,0x3B);
2233 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2234 // jmp dst > src around move
2235 emit_opcode(cbuf,0x7F);
2236 emit_d8(cbuf,2);
2237 // move dst,src
2238 emit_opcode(cbuf,0x8B);
2239 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2240 %}
2241
2242 enc_class enc_FPR_store(memory mem, regDPR src) %{
2243 // If src is FPR1, we can just FST to store it.
2244 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2245 int reg_encoding = 0x2; // Just store
2246 int base = $mem$$base;
2247 int index = $mem$$index;
2248 int scale = $mem$$scale;
2249 int displace = $mem$$disp;
2250 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2251 if( $src$$reg != FPR1L_enc ) {
2252 reg_encoding = 0x3; // Store & pop
2253 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2254 emit_d8( cbuf, 0xC0-1+$src$$reg );
2255 }
2256 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2257 emit_opcode(cbuf,$primary);
2258 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2259 %}
2260
2261 enc_class neg_reg(rRegI dst) %{
2262 // NEG $dst
2263 emit_opcode(cbuf,0xF7);
2264 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2265 %}
2266
2267 enc_class setLT_reg(eCXRegI dst) %{
2268 // SETLT $dst
2269 emit_opcode(cbuf,0x0F);
2270 emit_opcode(cbuf,0x9C);
2271 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2272 %}
2273
2274 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2275 int tmpReg = $tmp$$reg;
2276
2277 // SUB $p,$q
2278 emit_opcode(cbuf,0x2B);
2279 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2280 // SBB $tmp,$tmp
2281 emit_opcode(cbuf,0x1B);
2282 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2283 // AND $tmp,$y
2284 emit_opcode(cbuf,0x23);
2285 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2286 // ADD $p,$tmp
2287 emit_opcode(cbuf,0x03);
2288 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2289 %}
2290
2291 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2292 // TEST shift,32
2293 emit_opcode(cbuf,0xF7);
2294 emit_rm(cbuf, 0x3, 0, ECX_enc);
2295 emit_d32(cbuf,0x20);
2296 // JEQ,s small
2297 emit_opcode(cbuf, 0x74);
2298 emit_d8(cbuf, 0x04);
2299 // MOV $dst.hi,$dst.lo
2300 emit_opcode( cbuf, 0x8B );
2301 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2302 // CLR $dst.lo
2303 emit_opcode(cbuf, 0x33);
2304 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2305 // small:
2306 // SHLD $dst.hi,$dst.lo,$shift
2307 emit_opcode(cbuf,0x0F);
2308 emit_opcode(cbuf,0xA5);
2309 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2310 // SHL $dst.lo,$shift"
2311 emit_opcode(cbuf,0xD3);
2312 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2313 %}
2314
2315 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2316 // TEST shift,32
2317 emit_opcode(cbuf,0xF7);
2318 emit_rm(cbuf, 0x3, 0, ECX_enc);
2319 emit_d32(cbuf,0x20);
2320 // JEQ,s small
2321 emit_opcode(cbuf, 0x74);
2322 emit_d8(cbuf, 0x04);
2323 // MOV $dst.lo,$dst.hi
2324 emit_opcode( cbuf, 0x8B );
2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2326 // CLR $dst.hi
2327 emit_opcode(cbuf, 0x33);
2328 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2329 // small:
2330 // SHRD $dst.lo,$dst.hi,$shift
2331 emit_opcode(cbuf,0x0F);
2332 emit_opcode(cbuf,0xAD);
2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2334 // SHR $dst.hi,$shift"
2335 emit_opcode(cbuf,0xD3);
2336 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2337 %}
2338
2339 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2340 // TEST shift,32
2341 emit_opcode(cbuf,0xF7);
2342 emit_rm(cbuf, 0x3, 0, ECX_enc);
2343 emit_d32(cbuf,0x20);
2344 // JEQ,s small
2345 emit_opcode(cbuf, 0x74);
2346 emit_d8(cbuf, 0x05);
2347 // MOV $dst.lo,$dst.hi
2348 emit_opcode( cbuf, 0x8B );
2349 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2350 // SAR $dst.hi,31
2351 emit_opcode(cbuf, 0xC1);
2352 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2353 emit_d8(cbuf, 0x1F );
2354 // small:
2355 // SHRD $dst.lo,$dst.hi,$shift
2356 emit_opcode(cbuf,0x0F);
2357 emit_opcode(cbuf,0xAD);
2358 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2359 // SAR $dst.hi,$shift"
2360 emit_opcode(cbuf,0xD3);
2361 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2362 %}
2363
2364
2365 // ----------------- Encodings for floating point unit -----------------
2366 // May leave result in FPU-TOS or FPU reg depending on opcodes
2367 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2368 $$$emit8$primary;
2369 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2370 %}
2371
2372 // Pop argument in FPR0 with FSTP ST(0)
2373 enc_class PopFPU() %{
2374 emit_opcode( cbuf, 0xDD );
2375 emit_d8( cbuf, 0xD8 );
2376 %}
2377
2378 // !!!!! equivalent to Pop_Reg_F
2379 enc_class Pop_Reg_DPR( regDPR dst ) %{
2380 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2381 emit_d8( cbuf, 0xD8+$dst$$reg );
2382 %}
2383
2384 enc_class Push_Reg_DPR( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xD9 );
2386 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2387 %}
2388
2389 enc_class strictfp_bias1( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xDB ); // FLD m80real
2391 emit_opcode( cbuf, 0x2D );
2392 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2393 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2394 emit_opcode( cbuf, 0xC8+$dst$$reg );
2395 %}
2396
2397 enc_class strictfp_bias2( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xDB ); // FLD m80real
2399 emit_opcode( cbuf, 0x2D );
2400 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2401 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2402 emit_opcode( cbuf, 0xC8+$dst$$reg );
2403 %}
2404
2405 // Special case for moving an integer register to a stack slot.
2406 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2407 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2408 %}
2409
2410 // Special case for moving a register to a stack slot.
2411 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2412 // Opcode already emitted
2413 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2414 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2415 emit_d32(cbuf, $dst$$disp); // Displacement
2416 %}
2417
2418 // Push the integer in stackSlot 'src' onto FP-stack
2419 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2420 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2421 %}
2422
2423 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2424 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2425 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2426 %}
2427
2428 // Same as Pop_Mem_F except for opcode
2429 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2430 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2431 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2432 %}
2433
2434 enc_class Pop_Reg_FPR( regFPR dst ) %{
2435 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2436 emit_d8( cbuf, 0xD8+$dst$$reg );
2437 %}
2438
2439 enc_class Push_Reg_FPR( regFPR dst ) %{
2440 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2441 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2442 %}
2443
2444 // Push FPU's float to a stack-slot, and pop FPU-stack
2445 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2446 int pop = 0x02;
2447 if ($src$$reg != FPR1L_enc) {
2448 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2449 emit_d8( cbuf, 0xC0-1+$src$$reg );
2450 pop = 0x03;
2451 }
2452 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2453 %}
2454
2455 // Push FPU's double to a stack-slot, and pop FPU-stack
2456 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2457 int pop = 0x02;
2458 if ($src$$reg != FPR1L_enc) {
2459 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2460 emit_d8( cbuf, 0xC0-1+$src$$reg );
2461 pop = 0x03;
2462 }
2463 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2464 %}
2465
2466 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2467 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2468 int pop = 0xD0 - 1; // -1 since we skip FLD
2469 if ($src$$reg != FPR1L_enc) {
2470 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2471 emit_d8( cbuf, 0xC0-1+$src$$reg );
2472 pop = 0xD8;
2473 }
2474 emit_opcode( cbuf, 0xDD );
2475 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2476 %}
2477
2478
2479 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2480 // load dst in FPR0
2481 emit_opcode( cbuf, 0xD9 );
2482 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2483 if ($src$$reg != FPR1L_enc) {
2484 // fincstp
2485 emit_opcode (cbuf, 0xD9);
2486 emit_opcode (cbuf, 0xF7);
2487 // swap src with FPR1:
2488 // FXCH FPR1 with src
2489 emit_opcode(cbuf, 0xD9);
2490 emit_d8(cbuf, 0xC8-1+$src$$reg );
2491 // fdecstp
2492 emit_opcode (cbuf, 0xD9);
2493 emit_opcode (cbuf, 0xF6);
2494 }
2495 %}
2496
2497 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2498 MacroAssembler _masm(&cbuf);
2499 __ subptr(rsp, 8);
2500 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2501 __ fld_d(Address(rsp, 0));
2502 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2503 __ fld_d(Address(rsp, 0));
2504 %}
2505
2506 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2507 MacroAssembler _masm(&cbuf);
2508 __ subptr(rsp, 4);
2509 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2510 __ fld_s(Address(rsp, 0));
2511 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2512 __ fld_s(Address(rsp, 0));
2513 %}
2514
2515 enc_class Push_ResultD(regD dst) %{
2516 MacroAssembler _masm(&cbuf);
2517 __ fstp_d(Address(rsp, 0));
2518 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2519 __ addptr(rsp, 8);
2520 %}
2521
2522 enc_class Push_ResultF(regF dst, immI d8) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ fstp_s(Address(rsp, 0));
2525 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2526 __ addptr(rsp, $d8$$constant);
2527 %}
2528
2529 enc_class Push_SrcD(regD src) %{
2530 MacroAssembler _masm(&cbuf);
2531 __ subptr(rsp, 8);
2532 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2533 __ fld_d(Address(rsp, 0));
2534 %}
2535
2536 enc_class push_stack_temp_qword() %{
2537 MacroAssembler _masm(&cbuf);
2538 __ subptr(rsp, 8);
2539 %}
2540
2541 enc_class pop_stack_temp_qword() %{
2542 MacroAssembler _masm(&cbuf);
2543 __ addptr(rsp, 8);
2544 %}
2545
2546 enc_class push_xmm_to_fpr1(regD src) %{
2547 MacroAssembler _masm(&cbuf);
2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2549 __ fld_d(Address(rsp, 0));
2550 %}
2551
2552 enc_class Push_Result_Mod_DPR( regDPR src) %{
2553 if ($src$$reg != FPR1L_enc) {
2554 // fincstp
2555 emit_opcode (cbuf, 0xD9);
2556 emit_opcode (cbuf, 0xF7);
2557 // FXCH FPR1 with src
2558 emit_opcode(cbuf, 0xD9);
2559 emit_d8(cbuf, 0xC8-1+$src$$reg );
2560 // fdecstp
2561 emit_opcode (cbuf, 0xD9);
2562 emit_opcode (cbuf, 0xF6);
2563 }
2564 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2565 // // FSTP FPR$dst$$reg
2566 // emit_opcode( cbuf, 0xDD );
2567 // emit_d8( cbuf, 0xD8+$dst$$reg );
2568 %}
2569
2570 enc_class fnstsw_sahf_skip_parity() %{
2571 // fnstsw ax
2572 emit_opcode( cbuf, 0xDF );
2573 emit_opcode( cbuf, 0xE0 );
2574 // sahf
2575 emit_opcode( cbuf, 0x9E );
2576 // jnp ::skip
2577 emit_opcode( cbuf, 0x7B );
2578 emit_opcode( cbuf, 0x05 );
2579 %}
2580
2581 enc_class emitModDPR() %{
2582 // fprem must be iterative
2583 // :: loop
2584 // fprem
2585 emit_opcode( cbuf, 0xD9 );
2586 emit_opcode( cbuf, 0xF8 );
2587 // wait
2588 emit_opcode( cbuf, 0x9b );
2589 // fnstsw ax
2590 emit_opcode( cbuf, 0xDF );
2591 emit_opcode( cbuf, 0xE0 );
2592 // sahf
2593 emit_opcode( cbuf, 0x9E );
2594 // jp ::loop
2595 emit_opcode( cbuf, 0x0F );
2596 emit_opcode( cbuf, 0x8A );
2597 emit_opcode( cbuf, 0xF4 );
2598 emit_opcode( cbuf, 0xFF );
2599 emit_opcode( cbuf, 0xFF );
2600 emit_opcode( cbuf, 0xFF );
2601 %}
2602
2603 enc_class fpu_flags() %{
2604 // fnstsw_ax
2605 emit_opcode( cbuf, 0xDF);
2606 emit_opcode( cbuf, 0xE0);
2607 // test ax,0x0400
2608 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2609 emit_opcode( cbuf, 0xA9 );
2610 emit_d16 ( cbuf, 0x0400 );
2611 // // // This sequence works, but stalls for 12-16 cycles on PPro
2612 // // test rax,0x0400
2613 // emit_opcode( cbuf, 0xA9 );
2614 // emit_d32 ( cbuf, 0x00000400 );
2615 //
2616 // jz exit (no unordered comparison)
2617 emit_opcode( cbuf, 0x74 );
2618 emit_d8 ( cbuf, 0x02 );
2619 // mov ah,1 - treat as LT case (set carry flag)
2620 emit_opcode( cbuf, 0xB4 );
2621 emit_d8 ( cbuf, 0x01 );
2622 // sahf
2623 emit_opcode( cbuf, 0x9E);
2624 %}
2625
2626 enc_class cmpF_P6_fixup() %{
2627 // Fixup the integer flags in case comparison involved a NaN
2628 //
2629 // JNP exit (no unordered comparison, P-flag is set by NaN)
2630 emit_opcode( cbuf, 0x7B );
2631 emit_d8 ( cbuf, 0x03 );
2632 // MOV AH,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // SAHF
2636 emit_opcode( cbuf, 0x9E);
2637 // NOP // target for branch to avoid branch to branch
2638 emit_opcode( cbuf, 0x90);
2639 %}
2640
2641 // fnstsw_ax();
2642 // sahf();
2643 // movl(dst, nan_result);
2644 // jcc(Assembler::parity, exit);
2645 // movl(dst, less_result);
2646 // jcc(Assembler::below, exit);
2647 // movl(dst, equal_result);
2648 // jcc(Assembler::equal, exit);
2649 // movl(dst, greater_result);
2650
2651 // less_result = 1;
2652 // greater_result = -1;
2653 // equal_result = 0;
2654 // nan_result = -1;
2655
2656 enc_class CmpF_Result(rRegI dst) %{
2657 // fnstsw_ax();
2658 emit_opcode( cbuf, 0xDF);
2659 emit_opcode( cbuf, 0xE0);
2660 // sahf
2661 emit_opcode( cbuf, 0x9E);
2662 // movl(dst, nan_result);
2663 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2664 emit_d32( cbuf, -1 );
2665 // jcc(Assembler::parity, exit);
2666 emit_opcode( cbuf, 0x7A );
2667 emit_d8 ( cbuf, 0x13 );
2668 // movl(dst, less_result);
2669 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2670 emit_d32( cbuf, -1 );
2671 // jcc(Assembler::below, exit);
2672 emit_opcode( cbuf, 0x72 );
2673 emit_d8 ( cbuf, 0x0C );
2674 // movl(dst, equal_result);
2675 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2676 emit_d32( cbuf, 0 );
2677 // jcc(Assembler::equal, exit);
2678 emit_opcode( cbuf, 0x74 );
2679 emit_d8 ( cbuf, 0x05 );
2680 // movl(dst, greater_result);
2681 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2682 emit_d32( cbuf, 1 );
2683 %}
2684
2685
2686 // Compare the longs and set flags
2687 // BROKEN! Do Not use as-is
2688 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2689 // CMP $src1.hi,$src2.hi
2690 emit_opcode( cbuf, 0x3B );
2691 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2692 // JNE,s done
2693 emit_opcode(cbuf,0x75);
2694 emit_d8(cbuf, 2 );
2695 // CMP $src1.lo,$src2.lo
2696 emit_opcode( cbuf, 0x3B );
2697 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2698 // done:
2699 %}
2700
2701 enc_class convert_int_long( regL dst, rRegI src ) %{
2702 // mov $dst.lo,$src
2703 int dst_encoding = $dst$$reg;
2704 int src_encoding = $src$$reg;
2705 encode_Copy( cbuf, dst_encoding , src_encoding );
2706 // mov $dst.hi,$src
2707 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2708 // sar $dst.hi,31
2709 emit_opcode( cbuf, 0xC1 );
2710 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2711 emit_d8(cbuf, 0x1F );
2712 %}
2713
2714 enc_class convert_long_double( eRegL src ) %{
2715 // push $src.hi
2716 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2717 // push $src.lo
2718 emit_opcode(cbuf, 0x50+$src$$reg );
2719 // fild 64-bits at [SP]
2720 emit_opcode(cbuf,0xdf);
2721 emit_d8(cbuf, 0x6C);
2722 emit_d8(cbuf, 0x24);
2723 emit_d8(cbuf, 0x00);
2724 // pop stack
2725 emit_opcode(cbuf, 0x83); // add SP, #8
2726 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2727 emit_d8(cbuf, 0x8);
2728 %}
2729
2730 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2731 // IMUL EDX:EAX,$src1
2732 emit_opcode( cbuf, 0xF7 );
2733 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2734 // SAR EDX,$cnt-32
2735 int shift_count = ((int)$cnt$$constant) - 32;
2736 if (shift_count > 0) {
2737 emit_opcode(cbuf, 0xC1);
2738 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2739 emit_d8(cbuf, shift_count);
2740 }
2741 %}
2742
2743 // this version doesn't have add sp, 8
2744 enc_class convert_long_double2( eRegL src ) %{
2745 // push $src.hi
2746 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2747 // push $src.lo
2748 emit_opcode(cbuf, 0x50+$src$$reg );
2749 // fild 64-bits at [SP]
2750 emit_opcode(cbuf,0xdf);
2751 emit_d8(cbuf, 0x6C);
2752 emit_d8(cbuf, 0x24);
2753 emit_d8(cbuf, 0x00);
2754 %}
2755
2756 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2757 // Basic idea: long = (long)int * (long)int
2758 // IMUL EDX:EAX, src
2759 emit_opcode( cbuf, 0xF7 );
2760 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2761 %}
2762
2763 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2764 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2765 // MUL EDX:EAX, src
2766 emit_opcode( cbuf, 0xF7 );
2767 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2768 %}
2769
2770 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2771 // Basic idea: lo(result) = lo(x_lo * y_lo)
2772 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2773 // MOV $tmp,$src.lo
2774 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2775 // IMUL $tmp,EDX
2776 emit_opcode( cbuf, 0x0F );
2777 emit_opcode( cbuf, 0xAF );
2778 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2779 // MOV EDX,$src.hi
2780 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2781 // IMUL EDX,EAX
2782 emit_opcode( cbuf, 0x0F );
2783 emit_opcode( cbuf, 0xAF );
2784 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2785 // ADD $tmp,EDX
2786 emit_opcode( cbuf, 0x03 );
2787 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2788 // MUL EDX:EAX,$src.lo
2789 emit_opcode( cbuf, 0xF7 );
2790 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2791 // ADD EDX,ESI
2792 emit_opcode( cbuf, 0x03 );
2793 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2794 %}
2795
2796 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2797 // Basic idea: lo(result) = lo(src * y_lo)
2798 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2799 // IMUL $tmp,EDX,$src
2800 emit_opcode( cbuf, 0x6B );
2801 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2802 emit_d8( cbuf, (int)$src$$constant );
2803 // MOV EDX,$src
2804 emit_opcode(cbuf, 0xB8 + EDX_enc);
2805 emit_d32( cbuf, (int)$src$$constant );
2806 // MUL EDX:EAX,EDX
2807 emit_opcode( cbuf, 0xF7 );
2808 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2809 // ADD EDX,ESI
2810 emit_opcode( cbuf, 0x03 );
2811 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2812 %}
2813
2814 enc_class long_div( eRegL src1, eRegL src2 ) %{
2815 // PUSH src1.hi
2816 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2817 // PUSH src1.lo
2818 emit_opcode(cbuf, 0x50+$src1$$reg );
2819 // PUSH src2.hi
2820 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2821 // PUSH src2.lo
2822 emit_opcode(cbuf, 0x50+$src2$$reg );
2823 // CALL directly to the runtime
2824 cbuf.set_insts_mark();
2825 emit_opcode(cbuf,0xE8); // Call into runtime
2826 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2827 // Restore stack
2828 emit_opcode(cbuf, 0x83); // add SP, #framesize
2829 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2830 emit_d8(cbuf, 4*4);
2831 %}
2832
2833 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2834 // PUSH src1.hi
2835 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2836 // PUSH src1.lo
2837 emit_opcode(cbuf, 0x50+$src1$$reg );
2838 // PUSH src2.hi
2839 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2840 // PUSH src2.lo
2841 emit_opcode(cbuf, 0x50+$src2$$reg );
2842 // CALL directly to the runtime
2843 cbuf.set_insts_mark();
2844 emit_opcode(cbuf,0xE8); // Call into runtime
2845 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2846 // Restore stack
2847 emit_opcode(cbuf, 0x83); // add SP, #framesize
2848 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2849 emit_d8(cbuf, 4*4);
2850 %}
2851
2852 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2853 // MOV $tmp,$src.lo
2854 emit_opcode(cbuf, 0x8B);
2855 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2856 // OR $tmp,$src.hi
2857 emit_opcode(cbuf, 0x0B);
2858 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2859 %}
2860
2861 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2862 // CMP $src1.lo,$src2.lo
2863 emit_opcode( cbuf, 0x3B );
2864 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2865 // JNE,s skip
2866 emit_cc(cbuf, 0x70, 0x5);
2867 emit_d8(cbuf,2);
2868 // CMP $src1.hi,$src2.hi
2869 emit_opcode( cbuf, 0x3B );
2870 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2871 %}
2872
2873 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2874 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2875 emit_opcode( cbuf, 0x3B );
2876 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2877 // MOV $tmp,$src1.hi
2878 emit_opcode( cbuf, 0x8B );
2879 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2880 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2881 emit_opcode( cbuf, 0x1B );
2882 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2883 %}
2884
2885 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2886 // XOR $tmp,$tmp
2887 emit_opcode(cbuf,0x33); // XOR
2888 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2889 // CMP $tmp,$src.lo
2890 emit_opcode( cbuf, 0x3B );
2891 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2892 // SBB $tmp,$src.hi
2893 emit_opcode( cbuf, 0x1B );
2894 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2895 %}
2896
2897 // Sniff, sniff... smells like Gnu Superoptimizer
2898 enc_class neg_long( eRegL dst ) %{
2899 emit_opcode(cbuf,0xF7); // NEG hi
2900 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2901 emit_opcode(cbuf,0xF7); // NEG lo
2902 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2903 emit_opcode(cbuf,0x83); // SBB hi,0
2904 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2905 emit_d8 (cbuf,0 );
2906 %}
2907
2908
2909 // Because the transitions from emitted code to the runtime
2910 // monitorenter/exit helper stubs are so slow it's critical that
2911 // we inline both the stack-locking fast-path and the inflated fast path.
2912 //
2913 // See also: cmpFastLock and cmpFastUnlock.
2914 //
2915 // What follows is a specialized inline transliteration of the code
2916 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2917 // another option would be to emit TrySlowEnter and TrySlowExit methods
2918 // at startup-time. These methods would accept arguments as
2919 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2920 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2921 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2922 // In practice, however, the # of lock sites is bounded and is usually small.
2923 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2924 // if the processor uses simple bimodal branch predictors keyed by EIP
2925 // Since the helper routines would be called from multiple synchronization
2926 // sites.
2927 //
2928 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2929 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2930 // to those specialized methods. That'd give us a mostly platform-independent
2931 // implementation that the JITs could optimize and inline at their pleasure.
2932 // Done correctly, the only time we'd need to cross to native could would be
2933 // to park() or unpark() threads. We'd also need a few more unsafe operators
2934 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2935 // (b) explicit barriers or fence operations.
2936 //
2937 // TODO:
2938 //
2939 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2940 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2941 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2942 // the lock operators would typically be faster than reifying Self.
2943 //
2944 // * Ideally I'd define the primitives as:
2945 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2946 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2947 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2948 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2949 // Furthermore the register assignments are overconstrained, possibly resulting in
2950 // sub-optimal code near the synchronization site.
2951 //
2952 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2953 // Alternately, use a better sp-proximity test.
2954 //
2955 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2956 // Either one is sufficient to uniquely identify a thread.
2957 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2958 //
2959 // * Intrinsify notify() and notifyAll() for the common cases where the
2960 // object is locked by the calling thread but the waitlist is empty.
2961 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2962 //
2963 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2964 // But beware of excessive branch density on AMD Opterons.
2965 //
2966 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2967 // or failure of the fast-path. If the fast-path fails then we pass
2968 // control to the slow-path, typically in C. In Fast_Lock and
2969 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2970 // will emit a conditional branch immediately after the node.
2971 // So we have branches to branches and lots of ICC.ZF games.
2972 // Instead, it might be better to have C2 pass a "FailureLabel"
2973 // into Fast_Lock and Fast_Unlock. In the case of success, control
2974 // will drop through the node. ICC.ZF is undefined at exit.
2975 // In the case of failure, the node will branch directly to the
2976 // FailureLabel
2977
2978
2979 // obj: object to lock
2980 // box: on-stack box address (displaced header location) - KILLED
2981 // rax,: tmp -- KILLED
2982 // scr: tmp -- KILLED
2983 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2984
2985 Register objReg = as_Register($obj$$reg);
2986 Register boxReg = as_Register($box$$reg);
2987 Register tmpReg = as_Register($tmp$$reg);
2988 Register scrReg = as_Register($scr$$reg);
2989
2990 // Ensure the register assignents are disjoint
2991 guarantee (objReg != boxReg, "") ;
2992 guarantee (objReg != tmpReg, "") ;
2993 guarantee (objReg != scrReg, "") ;
2994 guarantee (boxReg != tmpReg, "") ;
2995 guarantee (boxReg != scrReg, "") ;
2996 guarantee (tmpReg == as_Register(EAX_enc), "") ;
2997
2998 MacroAssembler masm(&cbuf);
2999
3000 if (_counters != NULL) {
3001 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3002 }
3003 if (EmitSync & 1) {
3004 // set box->dhw = unused_mark (3)
3005 // Force all sync thru slow-path: slow_enter() and slow_exit()
3006 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3007 masm.cmpptr (rsp, (int32_t)0) ;
3008 } else
3009 if (EmitSync & 2) {
3010 Label DONE_LABEL ;
3011 if (UseBiasedLocking) {
3012 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3013 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3014 }
3015
3016 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3017 masm.orptr (tmpReg, 0x1);
3018 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3019 if (os::is_MP()) { masm.lock(); }
3020 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3021 masm.jcc(Assembler::equal, DONE_LABEL);
3022 // Recursive locking
3023 masm.subptr(tmpReg, rsp);
3024 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3025 masm.movptr(Address(boxReg, 0), tmpReg);
3026 masm.bind(DONE_LABEL) ;
3027 } else {
3028 // Possible cases that we'll encounter in fast_lock
3029 // ------------------------------------------------
3030 // * Inflated
3031 // -- unlocked
3032 // -- Locked
3033 // = by self
3034 // = by other
3035 // * biased
3036 // -- by Self
3037 // -- by other
3038 // * neutral
3039 // * stack-locked
3040 // -- by self
3041 // = sp-proximity test hits
3042 // = sp-proximity test generates false-negative
3043 // -- by other
3044 //
3045
3046 Label IsInflated, DONE_LABEL, PopDone ;
3047
3048 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3049 // order to reduce the number of conditional branches in the most common cases.
3050 // Beware -- there's a subtle invariant that fetch of the markword
3051 // at [FETCH], below, will never observe a biased encoding (*101b).
3052 // If this invariant is not held we risk exclusion (safety) failure.
3053 if (UseBiasedLocking && !UseOptoBiasInlining) {
3054 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3055 }
3056
3057 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3058 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3059 masm.jccb (Assembler::notZero, IsInflated) ;
3060
3061 // Attempt stack-locking ...
3062 masm.orptr (tmpReg, 0x1);
3063 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3064 if (os::is_MP()) { masm.lock(); }
3065 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3066 if (_counters != NULL) {
3067 masm.cond_inc32(Assembler::equal,
3068 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3069 }
3070 masm.jccb (Assembler::equal, DONE_LABEL);
3071
3072 // Recursive locking
3073 masm.subptr(tmpReg, rsp);
3074 masm.andptr(tmpReg, 0xFFFFF003 );
3075 masm.movptr(Address(boxReg, 0), tmpReg);
3076 if (_counters != NULL) {
3077 masm.cond_inc32(Assembler::equal,
3078 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3079 }
3080 masm.jmp (DONE_LABEL) ;
3081
3082 masm.bind (IsInflated) ;
3083
3084 // The object is inflated.
3085 //
3086 // TODO-FIXME: eliminate the ugly use of manifest constants:
3087 // Use markOopDesc::monitor_value instead of "2".
3088 // use markOop::unused_mark() instead of "3".
3089 // The tmpReg value is an objectMonitor reference ORed with
3090 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3091 // objectmonitor pointer by masking off the "2" bit or we can just
3092 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3093 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3094 //
3095 // I use the latter as it avoids AGI stalls.
3096 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3097 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3098 //
3099 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3100
3101 // boxReg refers to the on-stack BasicLock in the current frame.
3102 // We'd like to write:
3103 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3104 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3105 // additional latency as we have another ST in the store buffer that must drain.
3106
3107 if (EmitSync & 8192) {
3108 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3109 masm.get_thread (scrReg) ;
3110 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3111 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3112 if (os::is_MP()) { masm.lock(); }
3113 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3114 } else
3115 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3116 masm.movptr(scrReg, boxReg) ;
3117 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3118
3119 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3120 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3121 // prefetchw [eax + Offset(_owner)-2]
3122 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3123 }
3124
3125 if ((EmitSync & 64) == 0) {
3126 // Optimistic form: consider XORL tmpReg,tmpReg
3127 masm.movptr(tmpReg, NULL_WORD) ;
3128 } else {
3129 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3130 // Test-And-CAS instead of CAS
3131 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3132 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3133 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3134 }
3135
3136 // Appears unlocked - try to swing _owner from null to non-null.
3137 // Ideally, I'd manifest "Self" with get_thread and then attempt
3138 // to CAS the register containing Self into m->Owner.
3139 // But we don't have enough registers, so instead we can either try to CAS
3140 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3141 // we later store "Self" into m->Owner. Transiently storing a stack address
3142 // (rsp or the address of the box) into m->owner is harmless.
3143 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3144 if (os::is_MP()) { masm.lock(); }
3145 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3146 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3147 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3148 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3149 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3150 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3151
3152 // If the CAS fails we can either retry or pass control to the slow-path.
3153 // We use the latter tactic.
3154 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3155 // If the CAS was successful ...
3156 // Self has acquired the lock
3157 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3158 // Intentional fall-through into DONE_LABEL ...
3159 } else {
3160 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3161 masm.movptr(boxReg, tmpReg) ;
3162
3163 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3164 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3165 // prefetchw [eax + Offset(_owner)-2]
3166 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3167 }
3168
3169 if ((EmitSync & 64) == 0) {
3170 // Optimistic form
3171 masm.xorptr (tmpReg, tmpReg) ;
3172 } else {
3173 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3174 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3175 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3176 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3177 }
3178
3179 // Appears unlocked - try to swing _owner from null to non-null.
3180 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3181 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3182 masm.get_thread (scrReg) ;
3183 if (os::is_MP()) { masm.lock(); }
3184 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3185
3186 // If the CAS fails we can either retry or pass control to the slow-path.
3187 // We use the latter tactic.
3188 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3189 // If the CAS was successful ...
3190 // Self has acquired the lock
3191 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3192 // Intentional fall-through into DONE_LABEL ...
3193 }
3194
3195 // DONE_LABEL is a hot target - we'd really like to place it at the
3196 // start of cache line by padding with NOPs.
3197 // See the AMD and Intel software optimization manuals for the
3198 // most efficient "long" NOP encodings.
3199 // Unfortunately none of our alignment mechanisms suffice.
3200 masm.bind(DONE_LABEL);
3201
3202 // Avoid branch-to-branch on AMD processors
3203 // This appears to be superstition.
3204 if (EmitSync & 32) masm.nop() ;
3205
3206
3207 // At DONE_LABEL the icc ZFlag is set as follows ...
3208 // Fast_Unlock uses the same protocol.
3209 // ZFlag == 1 -> Success
3210 // ZFlag == 0 -> Failure - force control through the slow-path
3211 }
3212 %}
3213
3214 // obj: object to unlock
3215 // box: box address (displaced header location), killed. Must be EAX.
3216 // rbx,: killed tmp; cannot be obj nor box.
3217 //
3218 // Some commentary on balanced locking:
3219 //
3220 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3221 // Methods that don't have provably balanced locking are forced to run in the
3222 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3223 // The interpreter provides two properties:
3224 // I1: At return-time the interpreter automatically and quietly unlocks any
3225 // objects acquired the current activation (frame). Recall that the
3226 // interpreter maintains an on-stack list of locks currently held by
3227 // a frame.
3228 // I2: If a method attempts to unlock an object that is not held by the
3229 // the frame the interpreter throws IMSX.
3230 //
3231 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3232 // B() doesn't have provably balanced locking so it runs in the interpreter.
3233 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3234 // is still locked by A().
3235 //
3236 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3237 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3238 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3239 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3240
3241 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3242
3243 Register objReg = as_Register($obj$$reg);
3244 Register boxReg = as_Register($box$$reg);
3245 Register tmpReg = as_Register($tmp$$reg);
3246
3247 guarantee (objReg != boxReg, "") ;
3248 guarantee (objReg != tmpReg, "") ;
3249 guarantee (boxReg != tmpReg, "") ;
3250 guarantee (boxReg == as_Register(EAX_enc), "") ;
3251 MacroAssembler masm(&cbuf);
3252
3253 if (EmitSync & 4) {
3254 // Disable - inhibit all inlining. Force control through the slow-path
3255 masm.cmpptr (rsp, 0) ;
3256 } else
3257 if (EmitSync & 8) {
3258 Label DONE_LABEL ;
3259 if (UseBiasedLocking) {
3260 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3261 }
3262 // classic stack-locking code ...
3263 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3264 masm.testptr(tmpReg, tmpReg) ;
3265 masm.jcc (Assembler::zero, DONE_LABEL) ;
3266 if (os::is_MP()) { masm.lock(); }
3267 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3268 masm.bind(DONE_LABEL);
3269 } else {
3270 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3271
3272 // Critically, the biased locking test must have precedence over
3273 // and appear before the (box->dhw == 0) recursive stack-lock test.
3274 if (UseBiasedLocking && !UseOptoBiasInlining) {
3275 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3276 }
3277
3278 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3279 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3280 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3281
3282 masm.testptr(tmpReg, 0x02) ; // Inflated?
3283 masm.jccb (Assembler::zero, Stacked) ;
3284
3285 masm.bind (Inflated) ;
3286 // It's inflated.
3287 // Despite our balanced locking property we still check that m->_owner == Self
3288 // as java routines or native JNI code called by this thread might
3289 // have released the lock.
3290 // Refer to the comments in synchronizer.cpp for how we might encode extra
3291 // state in _succ so we can avoid fetching EntryList|cxq.
3292 //
3293 // I'd like to add more cases in fast_lock() and fast_unlock() --
3294 // such as recursive enter and exit -- but we have to be wary of
3295 // I$ bloat, T$ effects and BP$ effects.
3296 //
3297 // If there's no contention try a 1-0 exit. That is, exit without
3298 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3299 // we detect and recover from the race that the 1-0 exit admits.
3300 //
3301 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3302 // before it STs null into _owner, releasing the lock. Updates
3303 // to data protected by the critical section must be visible before
3304 // we drop the lock (and thus before any other thread could acquire
3305 // the lock and observe the fields protected by the lock).
3306 // IA32's memory-model is SPO, so STs are ordered with respect to
3307 // each other and there's no need for an explicit barrier (fence).
3308 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3309
3310 masm.get_thread (boxReg) ;
3311 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3312 // prefetchw [ebx + Offset(_owner)-2]
3313 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3314 }
3315
3316 // Note that we could employ various encoding schemes to reduce
3317 // the number of loads below (currently 4) to just 2 or 3.
3318 // Refer to the comments in synchronizer.cpp.
3319 // In practice the chain of fetches doesn't seem to impact performance, however.
3320 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3321 // Attempt to reduce branch density - AMD's branch predictor.
3322 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3323 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3324 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3325 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3326 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3327 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3328 masm.jmpb (DONE_LABEL) ;
3329 } else {
3330 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3331 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3332 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3333 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3334 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3335 masm.jccb (Assembler::notZero, CheckSucc) ;
3336 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3337 masm.jmpb (DONE_LABEL) ;
3338 }
3339
3340 // The Following code fragment (EmitSync & 65536) improves the performance of
3341 // contended applications and contended synchronization microbenchmarks.
3342 // Unfortunately the emission of the code - even though not executed - causes regressions
3343 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3344 // with an equal number of never-executed NOPs results in the same regression.
3345 // We leave it off by default.
3346
3347 if ((EmitSync & 65536) != 0) {
3348 Label LSuccess, LGoSlowPath ;
3349
3350 masm.bind (CheckSucc) ;
3351
3352 // Optional pre-test ... it's safe to elide this
3353 if ((EmitSync & 16) == 0) {
3354 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3355 masm.jccb (Assembler::zero, LGoSlowPath) ;
3356 }
3357
3358 // We have a classic Dekker-style idiom:
3359 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3360 // There are a number of ways to implement the barrier:
3361 // (1) lock:andl &m->_owner, 0
3362 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3363 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3364 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3365 // (2) If supported, an explicit MFENCE is appealing.
3366 // In older IA32 processors MFENCE is slower than lock:add or xchg
3367 // particularly if the write-buffer is full as might be the case if
3368 // if stores closely precede the fence or fence-equivalent instruction.
3369 // In more modern implementations MFENCE appears faster, however.
3370 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3371 // The $lines underlying the top-of-stack should be in M-state.
3372 // The locked add instruction is serializing, of course.
3373 // (4) Use xchg, which is serializing
3374 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3375 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3376 // The integer condition codes will tell us if succ was 0.
3377 // Since _succ and _owner should reside in the same $line and
3378 // we just stored into _owner, it's likely that the $line
3379 // remains in M-state for the lock:orl.
3380 //
3381 // We currently use (3), although it's likely that switching to (2)
3382 // is correct for the future.
3383
3384 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3385 if (os::is_MP()) {
3386 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3387 masm.mfence();
3388 } else {
3389 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3390 }
3391 }
3392 // Ratify _succ remains non-null
3393 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3394 masm.jccb (Assembler::notZero, LSuccess) ;
3395
3396 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3397 if (os::is_MP()) { masm.lock(); }
3398 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3399 masm.jccb (Assembler::notEqual, LSuccess) ;
3400 // Since we're low on registers we installed rsp as a placeholding in _owner.
3401 // Now install Self over rsp. This is safe as we're transitioning from
3402 // non-null to non=null
3403 masm.get_thread (boxReg) ;
3404 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3405 // Intentional fall-through into LGoSlowPath ...
3406
3407 masm.bind (LGoSlowPath) ;
3408 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3409 masm.jmpb (DONE_LABEL) ;
3410
3411 masm.bind (LSuccess) ;
3412 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3413 masm.jmpb (DONE_LABEL) ;
3414 }
3415
3416 masm.bind (Stacked) ;
3417 // It's not inflated and it's not recursively stack-locked and it's not biased.
3418 // It must be stack-locked.
3419 // Try to reset the header to displaced header.
3420 // The "box" value on the stack is stable, so we can reload
3421 // and be assured we observe the same value as above.
3422 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3423 if (os::is_MP()) { masm.lock(); }
3424 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3425 // Intention fall-thru into DONE_LABEL
3426
3427
3428 // DONE_LABEL is a hot target - we'd really like to place it at the
3429 // start of cache line by padding with NOPs.
3430 // See the AMD and Intel software optimization manuals for the
3431 // most efficient "long" NOP encodings.
3432 // Unfortunately none of our alignment mechanisms suffice.
3433 if ((EmitSync & 65536) == 0) {
3434 masm.bind (CheckSucc) ;
3435 }
3436 masm.bind(DONE_LABEL);
3437
3438 // Avoid branch to branch on AMD processors
3439 if (EmitSync & 32768) { masm.nop() ; }
3440 }
3441 %}
3442
3443
3444 enc_class enc_pop_rdx() %{
3445 emit_opcode(cbuf,0x5A);
3446 %}
3447
3448 enc_class enc_rethrow() %{
3449 cbuf.set_insts_mark();
3450 emit_opcode(cbuf, 0xE9); // jmp entry
3451 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3452 runtime_call_Relocation::spec(), RELOC_IMM32 );
3453 %}
3454
3455
3456 // Convert a double to an int. Java semantics require we do complex
3457 // manglelations in the corner cases. So we set the rounding mode to
3458 // 'zero', store the darned double down as an int, and reset the
3459 // rounding mode to 'nearest'. The hardware throws an exception which
3460 // patches up the correct value directly to the stack.
3461 enc_class DPR2I_encoding( regDPR src ) %{
3462 // Flip to round-to-zero mode. We attempted to allow invalid-op
3463 // exceptions here, so that a NAN or other corner-case value will
3464 // thrown an exception (but normal values get converted at full speed).
3465 // However, I2C adapters and other float-stack manglers leave pending
3466 // invalid-op exceptions hanging. We would have to clear them before
3467 // enabling them and that is more expensive than just testing for the
3468 // invalid value Intel stores down in the corner cases.
3469 emit_opcode(cbuf,0xD9); // FLDCW trunc
3470 emit_opcode(cbuf,0x2D);
3471 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3472 // Allocate a word
3473 emit_opcode(cbuf,0x83); // SUB ESP,4
3474 emit_opcode(cbuf,0xEC);
3475 emit_d8(cbuf,0x04);
3476 // Encoding assumes a double has been pushed into FPR0.
3477 // Store down the double as an int, popping the FPU stack
3478 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3479 emit_opcode(cbuf,0x1C);
3480 emit_d8(cbuf,0x24);
3481 // Restore the rounding mode; mask the exception
3482 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3483 emit_opcode(cbuf,0x2D);
3484 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3485 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3486 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3487
3488 // Load the converted int; adjust CPU stack
3489 emit_opcode(cbuf,0x58); // POP EAX
3490 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3491 emit_d32 (cbuf,0x80000000); // 0x80000000
3492 emit_opcode(cbuf,0x75); // JNE around_slow_call
3493 emit_d8 (cbuf,0x07); // Size of slow_call
3494 // Push src onto stack slow-path
3495 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3496 emit_d8 (cbuf,0xC0-1+$src$$reg );
3497 // CALL directly to the runtime
3498 cbuf.set_insts_mark();
3499 emit_opcode(cbuf,0xE8); // Call into runtime
3500 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3501 // Carry on here...
3502 %}
3503
3504 enc_class DPR2L_encoding( regDPR src ) %{
3505 emit_opcode(cbuf,0xD9); // FLDCW trunc
3506 emit_opcode(cbuf,0x2D);
3507 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3508 // Allocate a word
3509 emit_opcode(cbuf,0x83); // SUB ESP,8
3510 emit_opcode(cbuf,0xEC);
3511 emit_d8(cbuf,0x08);
3512 // Encoding assumes a double has been pushed into FPR0.
3513 // Store down the double as a long, popping the FPU stack
3514 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3515 emit_opcode(cbuf,0x3C);
3516 emit_d8(cbuf,0x24);
3517 // Restore the rounding mode; mask the exception
3518 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3519 emit_opcode(cbuf,0x2D);
3520 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3521 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3522 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3523
3524 // Load the converted int; adjust CPU stack
3525 emit_opcode(cbuf,0x58); // POP EAX
3526 emit_opcode(cbuf,0x5A); // POP EDX
3527 emit_opcode(cbuf,0x81); // CMP EDX,imm
3528 emit_d8 (cbuf,0xFA); // rdx
3529 emit_d32 (cbuf,0x80000000); // 0x80000000
3530 emit_opcode(cbuf,0x75); // JNE around_slow_call
3531 emit_d8 (cbuf,0x07+4); // Size of slow_call
3532 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3533 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3534 emit_opcode(cbuf,0x75); // JNE around_slow_call
3535 emit_d8 (cbuf,0x07); // Size of slow_call
3536 // Push src onto stack slow-path
3537 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3538 emit_d8 (cbuf,0xC0-1+$src$$reg );
3539 // CALL directly to the runtime
3540 cbuf.set_insts_mark();
3541 emit_opcode(cbuf,0xE8); // Call into runtime
3542 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3543 // Carry on here...
3544 %}
3545
3546 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3547 // Operand was loaded from memory into fp ST (stack top)
3548 // FMUL ST,$src /* D8 C8+i */
3549 emit_opcode(cbuf, 0xD8);
3550 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3551 %}
3552
3553 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3554 // FADDP ST,src2 /* D8 C0+i */
3555 emit_opcode(cbuf, 0xD8);
3556 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3557 //could use FADDP src2,fpST /* DE C0+i */
3558 %}
3559
3560 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3561 // FADDP src2,ST /* DE C0+i */
3562 emit_opcode(cbuf, 0xDE);
3563 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3564 %}
3565
3566 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3567 // Operand has been loaded into fp ST (stack top)
3568 // FSUB ST,$src1
3569 emit_opcode(cbuf, 0xD8);
3570 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3571
3572 // FDIV
3573 emit_opcode(cbuf, 0xD8);
3574 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3575 %}
3576
3577 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3578 // Operand was loaded from memory into fp ST (stack top)
3579 // FADD ST,$src /* D8 C0+i */
3580 emit_opcode(cbuf, 0xD8);
3581 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3582
3583 // FMUL ST,src2 /* D8 C*+i */
3584 emit_opcode(cbuf, 0xD8);
3585 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3586 %}
3587
3588
3589 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3590 // Operand was loaded from memory into fp ST (stack top)
3591 // FADD ST,$src /* D8 C0+i */
3592 emit_opcode(cbuf, 0xD8);
3593 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3594
3595 // FMULP src2,ST /* DE C8+i */
3596 emit_opcode(cbuf, 0xDE);
3597 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3598 %}
3599
3600 // Atomically load the volatile long
3601 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3602 emit_opcode(cbuf,0xDF);
3603 int rm_byte_opcode = 0x05;
3604 int base = $mem$$base;
3605 int index = $mem$$index;
3606 int scale = $mem$$scale;
3607 int displace = $mem$$disp;
3608 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3609 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3610 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3611 %}
3612
3613 // Volatile Store Long. Must be atomic, so move it into
3614 // the FP TOS and then do a 64-bit FIST. Has to probe the
3615 // target address before the store (for null-ptr checks)
3616 // so the memory operand is used twice in the encoding.
3617 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3618 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3619 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3620 emit_opcode(cbuf,0xDF);
3621 int rm_byte_opcode = 0x07;
3622 int base = $mem$$base;
3623 int index = $mem$$index;
3624 int scale = $mem$$scale;
3625 int displace = $mem$$disp;
3626 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3627 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3628 %}
3629
3630 // Safepoint Poll. This polls the safepoint page, and causes an
3631 // exception if it is not readable. Unfortunately, it kills the condition code
3632 // in the process
3633 // We current use TESTL [spp],EDI
3634 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3635
3636 enc_class Safepoint_Poll() %{
3637 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3638 emit_opcode(cbuf,0x85);
3639 emit_rm (cbuf, 0x0, 0x7, 0x5);
3640 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3641 %}
3642 %}
3643
3644
3645 //----------FRAME--------------------------------------------------------------
3646 // Definition of frame structure and management information.
3647 //
3648 // S T A C K L A Y O U T Allocators stack-slot number
3649 // | (to get allocators register number
3650 // G Owned by | | v add OptoReg::stack0())
3651 // r CALLER | |
3652 // o | +--------+ pad to even-align allocators stack-slot
3653 // w V | pad0 | numbers; owned by CALLER
3654 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3655 // h ^ | in | 5
3656 // | | args | 4 Holes in incoming args owned by SELF
3657 // | | | | 3
3658 // | | +--------+
3659 // V | | old out| Empty on Intel, window on Sparc
3660 // | old |preserve| Must be even aligned.
3661 // | SP-+--------+----> Matcher::_old_SP, even aligned
3662 // | | in | 3 area for Intel ret address
3663 // Owned by |preserve| Empty on Sparc.
3664 // SELF +--------+
3665 // | | pad2 | 2 pad to align old SP
3666 // | +--------+ 1
3667 // | | locks | 0
3668 // | +--------+----> OptoReg::stack0(), even aligned
3669 // | | pad1 | 11 pad to align new SP
3670 // | +--------+
3671 // | | | 10
3672 // | | spills | 9 spills
3673 // V | | 8 (pad0 slot for callee)
3674 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3675 // ^ | out | 7
3676 // | | args | 6 Holes in outgoing args owned by CALLEE
3677 // Owned by +--------+
3678 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3679 // | new |preserve| Must be even-aligned.
3680 // | SP-+--------+----> Matcher::_new_SP, even aligned
3681 // | | |
3682 //
3683 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3684 // known from SELF's arguments and the Java calling convention.
3685 // Region 6-7 is determined per call site.
3686 // Note 2: If the calling convention leaves holes in the incoming argument
3687 // area, those holes are owned by SELF. Holes in the outgoing area
3688 // are owned by the CALLEE. Holes should not be nessecary in the
3689 // incoming area, as the Java calling convention is completely under
3690 // the control of the AD file. Doubles can be sorted and packed to
3691 // avoid holes. Holes in the outgoing arguments may be nessecary for
3692 // varargs C calling conventions.
3693 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3694 // even aligned with pad0 as needed.
3695 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3696 // region 6-11 is even aligned; it may be padded out more so that
3697 // the region from SP to FP meets the minimum stack alignment.
3698
3699 frame %{
3700 // What direction does stack grow in (assumed to be same for C & Java)
3701 stack_direction(TOWARDS_LOW);
3702
3703 // These three registers define part of the calling convention
3704 // between compiled code and the interpreter.
3705 inline_cache_reg(EAX); // Inline Cache Register
3706 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3707
3708 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3709 cisc_spilling_operand_name(indOffset32);
3710
3711 // Number of stack slots consumed by locking an object
3712 sync_stack_slots(1);
3713
3714 // Compiled code's Frame Pointer
3715 frame_pointer(ESP);
3716 // Interpreter stores its frame pointer in a register which is
3717 // stored to the stack by I2CAdaptors.
3718 // I2CAdaptors convert from interpreted java to compiled java.
3719 interpreter_frame_pointer(EBP);
3720
3721 // Stack alignment requirement
3722 // Alignment size in bytes (128-bit -> 16 bytes)
3723 stack_alignment(StackAlignmentInBytes);
3724
3725 // Number of stack slots between incoming argument block and the start of
3726 // a new frame. The PROLOG must add this many slots to the stack. The
3727 // EPILOG must remove this many slots. Intel needs one slot for
3728 // return address and one for rbp, (must save rbp)
3729 in_preserve_stack_slots(2+VerifyStackAtCalls);
3730
3731 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3732 // for calls to C. Supports the var-args backing area for register parms.
3733 varargs_C_out_slots_killed(0);
3734
3735 // The after-PROLOG location of the return address. Location of
3736 // return address specifies a type (REG or STACK) and a number
3737 // representing the register number (i.e. - use a register name) or
3738 // stack slot.
3739 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3740 // Otherwise, it is above the locks and verification slot and alignment word
3741 return_addr(STACK - 1 +
3742 round_to((Compile::current()->in_preserve_stack_slots() +
3743 Compile::current()->fixed_slots()),
3744 stack_alignment_in_slots()));
3745
3746 // Body of function which returns an integer array locating
3747 // arguments either in registers or in stack slots. Passed an array
3748 // of ideal registers called "sig" and a "length" count. Stack-slot
3749 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3750 // arguments for a CALLEE. Incoming stack arguments are
3751 // automatically biased by the preserve_stack_slots field above.
3752 calling_convention %{
3753 // No difference between ingoing/outgoing just pass false
3754 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3755 %}
3756
3757
3758 // Body of function which returns an integer array locating
3759 // arguments either in registers or in stack slots. Passed an array
3760 // of ideal registers called "sig" and a "length" count. Stack-slot
3761 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3762 // arguments for a CALLEE. Incoming stack arguments are
3763 // automatically biased by the preserve_stack_slots field above.
3764 c_calling_convention %{
3765 // This is obviously always outgoing
3766 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3767 %}
3768
3769 // Location of C & interpreter return values
3770 c_return_value %{
3771 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3772 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3773 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3774
3775 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3776 // that C functions return float and double results in XMM0.
3777 if( ideal_reg == Op_RegD && UseSSE>=2 )
3778 return OptoRegPair(XMM0b_num,XMM0_num);
3779 if( ideal_reg == Op_RegF && UseSSE>=2 )
3780 return OptoRegPair(OptoReg::Bad,XMM0_num);
3781
3782 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3783 %}
3784
3785 // Location of return values
3786 return_value %{
3787 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3788 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3789 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3790 if( ideal_reg == Op_RegD && UseSSE>=2 )
3791 return OptoRegPair(XMM0b_num,XMM0_num);
3792 if( ideal_reg == Op_RegF && UseSSE>=1 )
3793 return OptoRegPair(OptoReg::Bad,XMM0_num);
3794 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3795 %}
3796
3797 %}
3798
3799 //----------ATTRIBUTES---------------------------------------------------------
3800 //----------Operand Attributes-------------------------------------------------
3801 op_attrib op_cost(0); // Required cost attribute
3802
3803 //----------Instruction Attributes---------------------------------------------
3804 ins_attrib ins_cost(100); // Required cost attribute
3805 ins_attrib ins_size(8); // Required size attribute (in bits)
3806 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3807 // non-matching short branch variant of some
3808 // long branch?
3809 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3810 // specifies the alignment that some part of the instruction (not
3811 // necessarily the start) requires. If > 1, a compute_padding()
3812 // function must be provided for the instruction
3813
3814 //----------OPERANDS-----------------------------------------------------------
3815 // Operand definitions must precede instruction definitions for correct parsing
3816 // in the ADLC because operands constitute user defined types which are used in
3817 // instruction definitions.
3818
3819 //----------Simple Operands----------------------------------------------------
3820 // Immediate Operands
3821 // Integer Immediate
3822 operand immI() %{
3823 match(ConI);
3824
3825 op_cost(10);
3826 format %{ %}
3827 interface(CONST_INTER);
3828 %}
3829
3830 // Constant for test vs zero
3831 operand immI0() %{
3832 predicate(n->get_int() == 0);
3833 match(ConI);
3834
3835 op_cost(0);
3836 format %{ %}
3837 interface(CONST_INTER);
3838 %}
3839
3840 // Constant for increment
3841 operand immI1() %{
3842 predicate(n->get_int() == 1);
3843 match(ConI);
3844
3845 op_cost(0);
3846 format %{ %}
3847 interface(CONST_INTER);
3848 %}
3849
3850 // Constant for decrement
3851 operand immI_M1() %{
3852 predicate(n->get_int() == -1);
3853 match(ConI);
3854
3855 op_cost(0);
3856 format %{ %}
3857 interface(CONST_INTER);
3858 %}
3859
3860 // Valid scale values for addressing modes
3861 operand immI2() %{
3862 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3863 match(ConI);
3864
3865 format %{ %}
3866 interface(CONST_INTER);
3867 %}
3868
3869 operand immI8() %{
3870 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3871 match(ConI);
3872
3873 op_cost(5);
3874 format %{ %}
3875 interface(CONST_INTER);
3876 %}
3877
3878 operand immI16() %{
3879 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3880 match(ConI);
3881
3882 op_cost(10);
3883 format %{ %}
3884 interface(CONST_INTER);
3885 %}
3886
3887 // Constant for long shifts
3888 operand immI_32() %{
3889 predicate( n->get_int() == 32 );
3890 match(ConI);
3891
3892 op_cost(0);
3893 format %{ %}
3894 interface(CONST_INTER);
3895 %}
3896
3897 operand immI_1_31() %{
3898 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3899 match(ConI);
3900
3901 op_cost(0);
3902 format %{ %}
3903 interface(CONST_INTER);
3904 %}
3905
3906 operand immI_32_63() %{
3907 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3908 match(ConI);
3909 op_cost(0);
3910
3911 format %{ %}
3912 interface(CONST_INTER);
3913 %}
3914
3915 operand immI_1() %{
3916 predicate( n->get_int() == 1 );
3917 match(ConI);
3918
3919 op_cost(0);
3920 format %{ %}
3921 interface(CONST_INTER);
3922 %}
3923
3924 operand immI_2() %{
3925 predicate( n->get_int() == 2 );
3926 match(ConI);
3927
3928 op_cost(0);
3929 format %{ %}
3930 interface(CONST_INTER);
3931 %}
3932
3933 operand immI_3() %{
3934 predicate( n->get_int() == 3 );
3935 match(ConI);
3936
3937 op_cost(0);
3938 format %{ %}
3939 interface(CONST_INTER);
3940 %}
3941
3942 // Pointer Immediate
3943 operand immP() %{
3944 match(ConP);
3945
3946 op_cost(10);
3947 format %{ %}
3948 interface(CONST_INTER);
3949 %}
3950
3951 // NULL Pointer Immediate
3952 operand immP0() %{
3953 predicate( n->get_ptr() == 0 );
3954 match(ConP);
3955 op_cost(0);
3956
3957 format %{ %}
3958 interface(CONST_INTER);
3959 %}
3960
3961 // Long Immediate
3962 operand immL() %{
3963 match(ConL);
3964
3965 op_cost(20);
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3969
3970 // Long Immediate zero
3971 operand immL0() %{
3972 predicate( n->get_long() == 0L );
3973 match(ConL);
3974 op_cost(0);
3975
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3979
3980 // Long Immediate zero
3981 operand immL_M1() %{
3982 predicate( n->get_long() == -1L );
3983 match(ConL);
3984 op_cost(0);
3985
3986 format %{ %}
3987 interface(CONST_INTER);
3988 %}
3989
3990 // Long immediate from 0 to 127.
3991 // Used for a shorter form of long mul by 10.
3992 operand immL_127() %{
3993 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3994 match(ConL);
3995 op_cost(0);
3996
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4000
4001 // Long Immediate: low 32-bit mask
4002 operand immL_32bits() %{
4003 predicate(n->get_long() == 0xFFFFFFFFL);
4004 match(ConL);
4005 op_cost(0);
4006
4007 format %{ %}
4008 interface(CONST_INTER);
4009 %}
4010
4011 // Long Immediate: low 32-bit mask
4012 operand immL32() %{
4013 predicate(n->get_long() == (int)(n->get_long()));
4014 match(ConL);
4015 op_cost(20);
4016
4017 format %{ %}
4018 interface(CONST_INTER);
4019 %}
4020
4021 //Double Immediate zero
4022 operand immDPR0() %{
4023 // Do additional (and counter-intuitive) test against NaN to work around VC++
4024 // bug that generates code such that NaNs compare equal to 0.0
4025 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4026 match(ConD);
4027
4028 op_cost(5);
4029 format %{ %}
4030 interface(CONST_INTER);
4031 %}
4032
4033 // Double Immediate one
4034 operand immDPR1() %{
4035 predicate( UseSSE<=1 && n->getd() == 1.0 );
4036 match(ConD);
4037
4038 op_cost(5);
4039 format %{ %}
4040 interface(CONST_INTER);
4041 %}
4042
4043 // Double Immediate
4044 operand immDPR() %{
4045 predicate(UseSSE<=1);
4046 match(ConD);
4047
4048 op_cost(5);
4049 format %{ %}
4050 interface(CONST_INTER);
4051 %}
4052
4053 operand immD() %{
4054 predicate(UseSSE>=2);
4055 match(ConD);
4056
4057 op_cost(5);
4058 format %{ %}
4059 interface(CONST_INTER);
4060 %}
4061
4062 // Double Immediate zero
4063 operand immD0() %{
4064 // Do additional (and counter-intuitive) test against NaN to work around VC++
4065 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4066 // compare equal to -0.0.
4067 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4068 match(ConD);
4069
4070 format %{ %}
4071 interface(CONST_INTER);
4072 %}
4073
4074 // Float Immediate zero
4075 operand immFPR0() %{
4076 predicate(UseSSE == 0 && n->getf() == 0.0F);
4077 match(ConF);
4078
4079 op_cost(5);
4080 format %{ %}
4081 interface(CONST_INTER);
4082 %}
4083
4084 // Float Immediate one
4085 operand immFPR1() %{
4086 predicate(UseSSE == 0 && n->getf() == 1.0F);
4087 match(ConF);
4088
4089 op_cost(5);
4090 format %{ %}
4091 interface(CONST_INTER);
4092 %}
4093
4094 // Float Immediate
4095 operand immFPR() %{
4096 predicate( UseSSE == 0 );
4097 match(ConF);
4098
4099 op_cost(5);
4100 format %{ %}
4101 interface(CONST_INTER);
4102 %}
4103
4104 // Float Immediate
4105 operand immF() %{
4106 predicate(UseSSE >= 1);
4107 match(ConF);
4108
4109 op_cost(5);
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 // Float Immediate zero. Zero and not -0.0
4115 operand immF0() %{
4116 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4117 match(ConF);
4118
4119 op_cost(5);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4123
4124 // Immediates for special shifts (sign extend)
4125
4126 // Constants for increment
4127 operand immI_16() %{
4128 predicate( n->get_int() == 16 );
4129 match(ConI);
4130
4131 format %{ %}
4132 interface(CONST_INTER);
4133 %}
4134
4135 operand immI_24() %{
4136 predicate( n->get_int() == 24 );
4137 match(ConI);
4138
4139 format %{ %}
4140 interface(CONST_INTER);
4141 %}
4142
4143 // Constant for byte-wide masking
4144 operand immI_255() %{
4145 predicate( n->get_int() == 255 );
4146 match(ConI);
4147
4148 format %{ %}
4149 interface(CONST_INTER);
4150 %}
4151
4152 // Constant for short-wide masking
4153 operand immI_65535() %{
4154 predicate(n->get_int() == 65535);
4155 match(ConI);
4156
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4160
4161 // Register Operands
4162 // Integer Register
4163 operand rRegI() %{
4164 constraint(ALLOC_IN_RC(int_reg));
4165 match(RegI);
4166 match(xRegI);
4167 match(eAXRegI);
4168 match(eBXRegI);
4169 match(eCXRegI);
4170 match(eDXRegI);
4171 match(eDIRegI);
4172 match(eSIRegI);
4173
4174 format %{ %}
4175 interface(REG_INTER);
4176 %}
4177
4178 // Subset of Integer Register
4179 operand xRegI(rRegI reg) %{
4180 constraint(ALLOC_IN_RC(int_x_reg));
4181 match(reg);
4182 match(eAXRegI);
4183 match(eBXRegI);
4184 match(eCXRegI);
4185 match(eDXRegI);
4186
4187 format %{ %}
4188 interface(REG_INTER);
4189 %}
4190
4191 // Special Registers
4192 operand eAXRegI(xRegI reg) %{
4193 constraint(ALLOC_IN_RC(eax_reg));
4194 match(reg);
4195 match(rRegI);
4196
4197 format %{ "EAX" %}
4198 interface(REG_INTER);
4199 %}
4200
4201 // Special Registers
4202 operand eBXRegI(xRegI reg) %{
4203 constraint(ALLOC_IN_RC(ebx_reg));
4204 match(reg);
4205 match(rRegI);
4206
4207 format %{ "EBX" %}
4208 interface(REG_INTER);
4209 %}
4210
4211 operand eCXRegI(xRegI reg) %{
4212 constraint(ALLOC_IN_RC(ecx_reg));
4213 match(reg);
4214 match(rRegI);
4215
4216 format %{ "ECX" %}
4217 interface(REG_INTER);
4218 %}
4219
4220 operand eDXRegI(xRegI reg) %{
4221 constraint(ALLOC_IN_RC(edx_reg));
4222 match(reg);
4223 match(rRegI);
4224
4225 format %{ "EDX" %}
4226 interface(REG_INTER);
4227 %}
4228
4229 operand eDIRegI(xRegI reg) %{
4230 constraint(ALLOC_IN_RC(edi_reg));
4231 match(reg);
4232 match(rRegI);
4233
4234 format %{ "EDI" %}
4235 interface(REG_INTER);
4236 %}
4237
4238 operand naxRegI() %{
4239 constraint(ALLOC_IN_RC(nax_reg));
4240 match(RegI);
4241 match(eCXRegI);
4242 match(eDXRegI);
4243 match(eSIRegI);
4244 match(eDIRegI);
4245
4246 format %{ %}
4247 interface(REG_INTER);
4248 %}
4249
4250 operand nadxRegI() %{
4251 constraint(ALLOC_IN_RC(nadx_reg));
4252 match(RegI);
4253 match(eBXRegI);
4254 match(eCXRegI);
4255 match(eSIRegI);
4256 match(eDIRegI);
4257
4258 format %{ %}
4259 interface(REG_INTER);
4260 %}
4261
4262 operand ncxRegI() %{
4263 constraint(ALLOC_IN_RC(ncx_reg));
4264 match(RegI);
4265 match(eAXRegI);
4266 match(eDXRegI);
4267 match(eSIRegI);
4268 match(eDIRegI);
4269
4270 format %{ %}
4271 interface(REG_INTER);
4272 %}
4273
4274 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4275 // //
4276 operand eSIRegI(xRegI reg) %{
4277 constraint(ALLOC_IN_RC(esi_reg));
4278 match(reg);
4279 match(rRegI);
4280
4281 format %{ "ESI" %}
4282 interface(REG_INTER);
4283 %}
4284
4285 // Pointer Register
4286 operand anyRegP() %{
4287 constraint(ALLOC_IN_RC(any_reg));
4288 match(RegP);
4289 match(eAXRegP);
4290 match(eBXRegP);
4291 match(eCXRegP);
4292 match(eDIRegP);
4293 match(eRegP);
4294
4295 format %{ %}
4296 interface(REG_INTER);
4297 %}
4298
4299 operand eRegP() %{
4300 constraint(ALLOC_IN_RC(int_reg));
4301 match(RegP);
4302 match(eAXRegP);
4303 match(eBXRegP);
4304 match(eCXRegP);
4305 match(eDIRegP);
4306
4307 format %{ %}
4308 interface(REG_INTER);
4309 %}
4310
4311 // On windows95, EBP is not safe to use for implicit null tests.
4312 operand eRegP_no_EBP() %{
4313 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4314 match(RegP);
4315 match(eAXRegP);
4316 match(eBXRegP);
4317 match(eCXRegP);
4318 match(eDIRegP);
4319
4320 op_cost(100);
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4324
4325 operand naxRegP() %{
4326 constraint(ALLOC_IN_RC(nax_reg));
4327 match(RegP);
4328 match(eBXRegP);
4329 match(eDXRegP);
4330 match(eCXRegP);
4331 match(eSIRegP);
4332 match(eDIRegP);
4333
4334 format %{ %}
4335 interface(REG_INTER);
4336 %}
4337
4338 operand nabxRegP() %{
4339 constraint(ALLOC_IN_RC(nabx_reg));
4340 match(RegP);
4341 match(eCXRegP);
4342 match(eDXRegP);
4343 match(eSIRegP);
4344 match(eDIRegP);
4345
4346 format %{ %}
4347 interface(REG_INTER);
4348 %}
4349
4350 operand pRegP() %{
4351 constraint(ALLOC_IN_RC(p_reg));
4352 match(RegP);
4353 match(eBXRegP);
4354 match(eDXRegP);
4355 match(eSIRegP);
4356 match(eDIRegP);
4357
4358 format %{ %}
4359 interface(REG_INTER);
4360 %}
4361
4362 // Special Registers
4363 // Return a pointer value
4364 operand eAXRegP(eRegP reg) %{
4365 constraint(ALLOC_IN_RC(eax_reg));
4366 match(reg);
4367 format %{ "EAX" %}
4368 interface(REG_INTER);
4369 %}
4370
4371 // Used in AtomicAdd
4372 operand eBXRegP(eRegP reg) %{
4373 constraint(ALLOC_IN_RC(ebx_reg));
4374 match(reg);
4375 format %{ "EBX" %}
4376 interface(REG_INTER);
4377 %}
4378
4379 // Tail-call (interprocedural jump) to interpreter
4380 operand eCXRegP(eRegP reg) %{
4381 constraint(ALLOC_IN_RC(ecx_reg));
4382 match(reg);
4383 format %{ "ECX" %}
4384 interface(REG_INTER);
4385 %}
4386
4387 operand eSIRegP(eRegP reg) %{
4388 constraint(ALLOC_IN_RC(esi_reg));
4389 match(reg);
4390 format %{ "ESI" %}
4391 interface(REG_INTER);
4392 %}
4393
4394 // Used in rep stosw
4395 operand eDIRegP(eRegP reg) %{
4396 constraint(ALLOC_IN_RC(edi_reg));
4397 match(reg);
4398 format %{ "EDI" %}
4399 interface(REG_INTER);
4400 %}
4401
4402 operand eBPRegP() %{
4403 constraint(ALLOC_IN_RC(ebp_reg));
4404 match(RegP);
4405 format %{ "EBP" %}
4406 interface(REG_INTER);
4407 %}
4408
4409 operand eRegL() %{
4410 constraint(ALLOC_IN_RC(long_reg));
4411 match(RegL);
4412 match(eADXRegL);
4413
4414 format %{ %}
4415 interface(REG_INTER);
4416 %}
4417
4418 operand eADXRegL( eRegL reg ) %{
4419 constraint(ALLOC_IN_RC(eadx_reg));
4420 match(reg);
4421
4422 format %{ "EDX:EAX" %}
4423 interface(REG_INTER);
4424 %}
4425
4426 operand eBCXRegL( eRegL reg ) %{
4427 constraint(ALLOC_IN_RC(ebcx_reg));
4428 match(reg);
4429
4430 format %{ "EBX:ECX" %}
4431 interface(REG_INTER);
4432 %}
4433
4434 // Special case for integer high multiply
4435 operand eADXRegL_low_only() %{
4436 constraint(ALLOC_IN_RC(eadx_reg));
4437 match(RegL);
4438
4439 format %{ "EAX" %}
4440 interface(REG_INTER);
4441 %}
4442
4443 // Flags register, used as output of compare instructions
4444 operand eFlagsReg() %{
4445 constraint(ALLOC_IN_RC(int_flags));
4446 match(RegFlags);
4447
4448 format %{ "EFLAGS" %}
4449 interface(REG_INTER);
4450 %}
4451
4452 // Flags register, used as output of FLOATING POINT compare instructions
4453 operand eFlagsRegU() %{
4454 constraint(ALLOC_IN_RC(int_flags));
4455 match(RegFlags);
4456
4457 format %{ "EFLAGS_U" %}
4458 interface(REG_INTER);
4459 %}
4460
4461 operand eFlagsRegUCF() %{
4462 constraint(ALLOC_IN_RC(int_flags));
4463 match(RegFlags);
4464 predicate(false);
4465
4466 format %{ "EFLAGS_U_CF" %}
4467 interface(REG_INTER);
4468 %}
4469
4470 // Condition Code Register used by long compare
4471 operand flagsReg_long_LTGE() %{
4472 constraint(ALLOC_IN_RC(int_flags));
4473 match(RegFlags);
4474 format %{ "FLAGS_LTGE" %}
4475 interface(REG_INTER);
4476 %}
4477 operand flagsReg_long_EQNE() %{
4478 constraint(ALLOC_IN_RC(int_flags));
4479 match(RegFlags);
4480 format %{ "FLAGS_EQNE" %}
4481 interface(REG_INTER);
4482 %}
4483 operand flagsReg_long_LEGT() %{
4484 constraint(ALLOC_IN_RC(int_flags));
4485 match(RegFlags);
4486 format %{ "FLAGS_LEGT" %}
4487 interface(REG_INTER);
4488 %}
4489
4490 // Float register operands
4491 operand regDPR() %{
4492 predicate( UseSSE < 2 );
4493 constraint(ALLOC_IN_RC(fp_dbl_reg));
4494 match(RegD);
4495 match(regDPR1);
4496 match(regDPR2);
4497 format %{ %}
4498 interface(REG_INTER);
4499 %}
4500
4501 operand regDPR1(regDPR reg) %{
4502 predicate( UseSSE < 2 );
4503 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4504 match(reg);
4505 format %{ "FPR1" %}
4506 interface(REG_INTER);
4507 %}
4508
4509 operand regDPR2(regDPR reg) %{
4510 predicate( UseSSE < 2 );
4511 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4512 match(reg);
4513 format %{ "FPR2" %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand regnotDPR1(regDPR reg) %{
4518 predicate( UseSSE < 2 );
4519 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4520 match(reg);
4521 format %{ %}
4522 interface(REG_INTER);
4523 %}
4524
4525 // Float register operands
4526 operand regFPR() %{
4527 predicate( UseSSE < 2 );
4528 constraint(ALLOC_IN_RC(fp_flt_reg));
4529 match(RegF);
4530 match(regFPR1);
4531 format %{ %}
4532 interface(REG_INTER);
4533 %}
4534
4535 // Float register operands
4536 operand regFPR1(regFPR reg) %{
4537 predicate( UseSSE < 2 );
4538 constraint(ALLOC_IN_RC(fp_flt_reg0));
4539 match(reg);
4540 format %{ "FPR1" %}
4541 interface(REG_INTER);
4542 %}
4543
4544 // XMM Float register operands
4545 operand regF() %{
4546 predicate( UseSSE>=1 );
4547 constraint(ALLOC_IN_RC(float_reg));
4548 match(RegF);
4549 format %{ %}
4550 interface(REG_INTER);
4551 %}
4552
4553 // XMM Double register operands
4554 operand regD() %{
4555 predicate( UseSSE>=2 );
4556 constraint(ALLOC_IN_RC(double_reg));
4557 match(RegD);
4558 format %{ %}
4559 interface(REG_INTER);
4560 %}
4561
4562
4563 //----------Memory Operands----------------------------------------------------
4564 // Direct Memory Operand
4565 operand direct(immP addr) %{
4566 match(addr);
4567
4568 format %{ "[$addr]" %}
4569 interface(MEMORY_INTER) %{
4570 base(0xFFFFFFFF);
4571 index(0x4);
4572 scale(0x0);
4573 disp($addr);
4574 %}
4575 %}
4576
4577 // Indirect Memory Operand
4578 operand indirect(eRegP reg) %{
4579 constraint(ALLOC_IN_RC(int_reg));
4580 match(reg);
4581
4582 format %{ "[$reg]" %}
4583 interface(MEMORY_INTER) %{
4584 base($reg);
4585 index(0x4);
4586 scale(0x0);
4587 disp(0x0);
4588 %}
4589 %}
4590
4591 // Indirect Memory Plus Short Offset Operand
4592 operand indOffset8(eRegP reg, immI8 off) %{
4593 match(AddP reg off);
4594
4595 format %{ "[$reg + $off]" %}
4596 interface(MEMORY_INTER) %{
4597 base($reg);
4598 index(0x4);
4599 scale(0x0);
4600 disp($off);
4601 %}
4602 %}
4603
4604 // Indirect Memory Plus Long Offset Operand
4605 operand indOffset32(eRegP reg, immI off) %{
4606 match(AddP reg off);
4607
4608 format %{ "[$reg + $off]" %}
4609 interface(MEMORY_INTER) %{
4610 base($reg);
4611 index(0x4);
4612 scale(0x0);
4613 disp($off);
4614 %}
4615 %}
4616
4617 // Indirect Memory Plus Long Offset Operand
4618 operand indOffset32X(rRegI reg, immP off) %{
4619 match(AddP off reg);
4620
4621 format %{ "[$reg + $off]" %}
4622 interface(MEMORY_INTER) %{
4623 base($reg);
4624 index(0x4);
4625 scale(0x0);
4626 disp($off);
4627 %}
4628 %}
4629
4630 // Indirect Memory Plus Index Register Plus Offset Operand
4631 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4632 match(AddP (AddP reg ireg) off);
4633
4634 op_cost(10);
4635 format %{"[$reg + $off + $ireg]" %}
4636 interface(MEMORY_INTER) %{
4637 base($reg);
4638 index($ireg);
4639 scale(0x0);
4640 disp($off);
4641 %}
4642 %}
4643
4644 // Indirect Memory Plus Index Register Plus Offset Operand
4645 operand indIndex(eRegP reg, rRegI ireg) %{
4646 match(AddP reg ireg);
4647
4648 op_cost(10);
4649 format %{"[$reg + $ireg]" %}
4650 interface(MEMORY_INTER) %{
4651 base($reg);
4652 index($ireg);
4653 scale(0x0);
4654 disp(0x0);
4655 %}
4656 %}
4657
4658 // // -------------------------------------------------------------------------
4659 // // 486 architecture doesn't support "scale * index + offset" with out a base
4660 // // -------------------------------------------------------------------------
4661 // // Scaled Memory Operands
4662 // // Indirect Memory Times Scale Plus Offset Operand
4663 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4664 // match(AddP off (LShiftI ireg scale));
4665 //
4666 // op_cost(10);
4667 // format %{"[$off + $ireg << $scale]" %}
4668 // interface(MEMORY_INTER) %{
4669 // base(0x4);
4670 // index($ireg);
4671 // scale($scale);
4672 // disp($off);
4673 // %}
4674 // %}
4675
4676 // Indirect Memory Times Scale Plus Index Register
4677 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4678 match(AddP reg (LShiftI ireg scale));
4679
4680 op_cost(10);
4681 format %{"[$reg + $ireg << $scale]" %}
4682 interface(MEMORY_INTER) %{
4683 base($reg);
4684 index($ireg);
4685 scale($scale);
4686 disp(0x0);
4687 %}
4688 %}
4689
4690 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4691 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4692 match(AddP (AddP reg (LShiftI ireg scale)) off);
4693
4694 op_cost(10);
4695 format %{"[$reg + $off + $ireg << $scale]" %}
4696 interface(MEMORY_INTER) %{
4697 base($reg);
4698 index($ireg);
4699 scale($scale);
4700 disp($off);
4701 %}
4702 %}
4703
4704 //----------Load Long Memory Operands------------------------------------------
4705 // The load-long idiom will use it's address expression again after loading
4706 // the first word of the long. If the load-long destination overlaps with
4707 // registers used in the addressing expression, the 2nd half will be loaded
4708 // from a clobbered address. Fix this by requiring that load-long use
4709 // address registers that do not overlap with the load-long target.
4710
4711 // load-long support
4712 operand load_long_RegP() %{
4713 constraint(ALLOC_IN_RC(esi_reg));
4714 match(RegP);
4715 match(eSIRegP);
4716 op_cost(100);
4717 format %{ %}
4718 interface(REG_INTER);
4719 %}
4720
4721 // Indirect Memory Operand Long
4722 operand load_long_indirect(load_long_RegP reg) %{
4723 constraint(ALLOC_IN_RC(esi_reg));
4724 match(reg);
4725
4726 format %{ "[$reg]" %}
4727 interface(MEMORY_INTER) %{
4728 base($reg);
4729 index(0x4);
4730 scale(0x0);
4731 disp(0x0);
4732 %}
4733 %}
4734
4735 // Indirect Memory Plus Long Offset Operand
4736 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4737 match(AddP reg off);
4738
4739 format %{ "[$reg + $off]" %}
4740 interface(MEMORY_INTER) %{
4741 base($reg);
4742 index(0x4);
4743 scale(0x0);
4744 disp($off);
4745 %}
4746 %}
4747
4748 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4749
4750
4751 //----------Special Memory Operands--------------------------------------------
4752 // Stack Slot Operand - This operand is used for loading and storing temporary
4753 // values on the stack where a match requires a value to
4754 // flow through memory.
4755 operand stackSlotP(sRegP reg) %{
4756 constraint(ALLOC_IN_RC(stack_slots));
4757 // No match rule because this operand is only generated in matching
4758 format %{ "[$reg]" %}
4759 interface(MEMORY_INTER) %{
4760 base(0x4); // ESP
4761 index(0x4); // No Index
4762 scale(0x0); // No Scale
4763 disp($reg); // Stack Offset
4764 %}
4765 %}
4766
4767 operand stackSlotI(sRegI reg) %{
4768 constraint(ALLOC_IN_RC(stack_slots));
4769 // No match rule because this operand is only generated in matching
4770 format %{ "[$reg]" %}
4771 interface(MEMORY_INTER) %{
4772 base(0x4); // ESP
4773 index(0x4); // No Index
4774 scale(0x0); // No Scale
4775 disp($reg); // Stack Offset
4776 %}
4777 %}
4778
4779 operand stackSlotF(sRegF reg) %{
4780 constraint(ALLOC_IN_RC(stack_slots));
4781 // No match rule because this operand is only generated in matching
4782 format %{ "[$reg]" %}
4783 interface(MEMORY_INTER) %{
4784 base(0x4); // ESP
4785 index(0x4); // No Index
4786 scale(0x0); // No Scale
4787 disp($reg); // Stack Offset
4788 %}
4789 %}
4790
4791 operand stackSlotD(sRegD reg) %{
4792 constraint(ALLOC_IN_RC(stack_slots));
4793 // No match rule because this operand is only generated in matching
4794 format %{ "[$reg]" %}
4795 interface(MEMORY_INTER) %{
4796 base(0x4); // ESP
4797 index(0x4); // No Index
4798 scale(0x0); // No Scale
4799 disp($reg); // Stack Offset
4800 %}
4801 %}
4802
4803 operand stackSlotL(sRegL reg) %{
4804 constraint(ALLOC_IN_RC(stack_slots));
4805 // No match rule because this operand is only generated in matching
4806 format %{ "[$reg]" %}
4807 interface(MEMORY_INTER) %{
4808 base(0x4); // ESP
4809 index(0x4); // No Index
4810 scale(0x0); // No Scale
4811 disp($reg); // Stack Offset
4812 %}
4813 %}
4814
4815 //----------Memory Operands - Win95 Implicit Null Variants----------------
4816 // Indirect Memory Operand
4817 operand indirect_win95_safe(eRegP_no_EBP reg)
4818 %{
4819 constraint(ALLOC_IN_RC(int_reg));
4820 match(reg);
4821
4822 op_cost(100);
4823 format %{ "[$reg]" %}
4824 interface(MEMORY_INTER) %{
4825 base($reg);
4826 index(0x4);
4827 scale(0x0);
4828 disp(0x0);
4829 %}
4830 %}
4831
4832 // Indirect Memory Plus Short Offset Operand
4833 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4834 %{
4835 match(AddP reg off);
4836
4837 op_cost(100);
4838 format %{ "[$reg + $off]" %}
4839 interface(MEMORY_INTER) %{
4840 base($reg);
4841 index(0x4);
4842 scale(0x0);
4843 disp($off);
4844 %}
4845 %}
4846
4847 // Indirect Memory Plus Long Offset Operand
4848 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4849 %{
4850 match(AddP reg off);
4851
4852 op_cost(100);
4853 format %{ "[$reg + $off]" %}
4854 interface(MEMORY_INTER) %{
4855 base($reg);
4856 index(0x4);
4857 scale(0x0);
4858 disp($off);
4859 %}
4860 %}
4861
4862 // Indirect Memory Plus Index Register Plus Offset Operand
4863 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4864 %{
4865 match(AddP (AddP reg ireg) off);
4866
4867 op_cost(100);
4868 format %{"[$reg + $off + $ireg]" %}
4869 interface(MEMORY_INTER) %{
4870 base($reg);
4871 index($ireg);
4872 scale(0x0);
4873 disp($off);
4874 %}
4875 %}
4876
4877 // Indirect Memory Times Scale Plus Index Register
4878 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4879 %{
4880 match(AddP reg (LShiftI ireg scale));
4881
4882 op_cost(100);
4883 format %{"[$reg + $ireg << $scale]" %}
4884 interface(MEMORY_INTER) %{
4885 base($reg);
4886 index($ireg);
4887 scale($scale);
4888 disp(0x0);
4889 %}
4890 %}
4891
4892 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4893 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4894 %{
4895 match(AddP (AddP reg (LShiftI ireg scale)) off);
4896
4897 op_cost(100);
4898 format %{"[$reg + $off + $ireg << $scale]" %}
4899 interface(MEMORY_INTER) %{
4900 base($reg);
4901 index($ireg);
4902 scale($scale);
4903 disp($off);
4904 %}
4905 %}
4906
4907 //----------Conditional Branch Operands----------------------------------------
4908 // Comparison Op - This is the operation of the comparison, and is limited to
4909 // the following set of codes:
4910 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4911 //
4912 // Other attributes of the comparison, such as unsignedness, are specified
4913 // by the comparison instruction that sets a condition code flags register.
4914 // That result is represented by a flags operand whose subtype is appropriate
4915 // to the unsignedness (etc.) of the comparison.
4916 //
4917 // Later, the instruction which matches both the Comparison Op (a Bool) and
4918 // the flags (produced by the Cmp) specifies the coding of the comparison op
4919 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4920
4921 // Comparision Code
4922 operand cmpOp() %{
4923 match(Bool);
4924
4925 format %{ "" %}
4926 interface(COND_INTER) %{
4927 equal(0x4, "e");
4928 not_equal(0x5, "ne");
4929 less(0xC, "l");
4930 greater_equal(0xD, "ge");
4931 less_equal(0xE, "le");
4932 greater(0xF, "g");
4933 overflow(0x0, "o");
4934 no_overflow(0x1, "no");
4935 %}
4936 %}
4937
4938 // Comparison Code, unsigned compare. Used by FP also, with
4939 // C2 (unordered) turned into GT or LT already. The other bits
4940 // C0 and C3 are turned into Carry & Zero flags.
4941 operand cmpOpU() %{
4942 match(Bool);
4943
4944 format %{ "" %}
4945 interface(COND_INTER) %{
4946 equal(0x4, "e");
4947 not_equal(0x5, "ne");
4948 less(0x2, "b");
4949 greater_equal(0x3, "nb");
4950 less_equal(0x6, "be");
4951 greater(0x7, "nbe");
4952 overflow(0x0, "o");
4953 no_overflow(0x1, "no");
4954 %}
4955 %}
4956
4957 // Floating comparisons that don't require any fixup for the unordered case
4958 operand cmpOpUCF() %{
4959 match(Bool);
4960 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4961 n->as_Bool()->_test._test == BoolTest::ge ||
4962 n->as_Bool()->_test._test == BoolTest::le ||
4963 n->as_Bool()->_test._test == BoolTest::gt);
4964 format %{ "" %}
4965 interface(COND_INTER) %{
4966 equal(0x4, "e");
4967 not_equal(0x5, "ne");
4968 less(0x2, "b");
4969 greater_equal(0x3, "nb");
4970 less_equal(0x6, "be");
4971 greater(0x7, "nbe");
4972 overflow(0x0, "o");
4973 no_overflow(0x1, "no");
4974 %}
4975 %}
4976
4977
4978 // Floating comparisons that can be fixed up with extra conditional jumps
4979 operand cmpOpUCF2() %{
4980 match(Bool);
4981 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4982 n->as_Bool()->_test._test == BoolTest::eq);
4983 format %{ "" %}
4984 interface(COND_INTER) %{
4985 equal(0x4, "e");
4986 not_equal(0x5, "ne");
4987 less(0x2, "b");
4988 greater_equal(0x3, "nb");
4989 less_equal(0x6, "be");
4990 greater(0x7, "nbe");
4991 overflow(0x0, "o");
4992 no_overflow(0x1, "no");
4993 %}
4994 %}
4995
4996 // Comparison Code for FP conditional move
4997 operand cmpOp_fcmov() %{
4998 match(Bool);
4999
5000 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5001 n->as_Bool()->_test._test != BoolTest::no_overflow);
5002 format %{ "" %}
5003 interface(COND_INTER) %{
5004 equal (0x0C8);
5005 not_equal (0x1C8);
5006 less (0x0C0);
5007 greater_equal(0x1C0);
5008 less_equal (0x0D0);
5009 greater (0x1D0);
5010 overflow(0x0, "o"); // not really supported by the instruction
5011 no_overflow(0x1, "no"); // not really supported by the instruction
5012 %}
5013 %}
5014
5015 // Comparision Code used in long compares
5016 operand cmpOp_commute() %{
5017 match(Bool);
5018
5019 format %{ "" %}
5020 interface(COND_INTER) %{
5021 equal(0x4, "e");
5022 not_equal(0x5, "ne");
5023 less(0xF, "g");
5024 greater_equal(0xE, "le");
5025 less_equal(0xD, "ge");
5026 greater(0xC, "l");
5027 overflow(0x0, "o");
5028 no_overflow(0x1, "no");
5029 %}
5030 %}
5031
5032 //----------OPERAND CLASSES----------------------------------------------------
5033 // Operand Classes are groups of operands that are used as to simplify
5034 // instruction definitions by not requiring the AD writer to specify separate
5035 // instructions for every form of operand when the instruction accepts
5036 // multiple operand types with the same basic encoding and format. The classic
5037 // case of this is memory operands.
5038
5039 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5040 indIndex, indIndexScale, indIndexScaleOffset);
5041
5042 // Long memory operations are encoded in 2 instructions and a +4 offset.
5043 // This means some kind of offset is always required and you cannot use
5044 // an oop as the offset (done when working on static globals).
5045 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5046 indIndex, indIndexScale, indIndexScaleOffset);
5047
5048
5049 //----------PIPELINE-----------------------------------------------------------
5050 // Rules which define the behavior of the target architectures pipeline.
5051 pipeline %{
5052
5053 //----------ATTRIBUTES---------------------------------------------------------
5054 attributes %{
5055 variable_size_instructions; // Fixed size instructions
5056 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5057 instruction_unit_size = 1; // An instruction is 1 bytes long
5058 instruction_fetch_unit_size = 16; // The processor fetches one line
5059 instruction_fetch_units = 1; // of 16 bytes
5060
5061 // List of nop instructions
5062 nops( MachNop );
5063 %}
5064
5065 //----------RESOURCES----------------------------------------------------------
5066 // Resources are the functional units available to the machine
5067
5068 // Generic P2/P3 pipeline
5069 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5070 // 3 instructions decoded per cycle.
5071 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5072 // 2 ALU op, only ALU0 handles mul/div instructions.
5073 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5074 MS0, MS1, MEM = MS0 | MS1,
5075 BR, FPU,
5076 ALU0, ALU1, ALU = ALU0 | ALU1 );
5077
5078 //----------PIPELINE DESCRIPTION-----------------------------------------------
5079 // Pipeline Description specifies the stages in the machine's pipeline
5080
5081 // Generic P2/P3 pipeline
5082 pipe_desc(S0, S1, S2, S3, S4, S5);
5083
5084 //----------PIPELINE CLASSES---------------------------------------------------
5085 // Pipeline Classes describe the stages in which input and output are
5086 // referenced by the hardware pipeline.
5087
5088 // Naming convention: ialu or fpu
5089 // Then: _reg
5090 // Then: _reg if there is a 2nd register
5091 // Then: _long if it's a pair of instructions implementing a long
5092 // Then: _fat if it requires the big decoder
5093 // Or: _mem if it requires the big decoder and a memory unit.
5094
5095 // Integer ALU reg operation
5096 pipe_class ialu_reg(rRegI dst) %{
5097 single_instruction;
5098 dst : S4(write);
5099 dst : S3(read);
5100 DECODE : S0; // any decoder
5101 ALU : S3; // any alu
5102 %}
5103
5104 // Long ALU reg operation
5105 pipe_class ialu_reg_long(eRegL dst) %{
5106 instruction_count(2);
5107 dst : S4(write);
5108 dst : S3(read);
5109 DECODE : S0(2); // any 2 decoders
5110 ALU : S3(2); // both alus
5111 %}
5112
5113 // Integer ALU reg operation using big decoder
5114 pipe_class ialu_reg_fat(rRegI dst) %{
5115 single_instruction;
5116 dst : S4(write);
5117 dst : S3(read);
5118 D0 : S0; // big decoder only
5119 ALU : S3; // any alu
5120 %}
5121
5122 // Long ALU reg operation using big decoder
5123 pipe_class ialu_reg_long_fat(eRegL dst) %{
5124 instruction_count(2);
5125 dst : S4(write);
5126 dst : S3(read);
5127 D0 : S0(2); // big decoder only; twice
5128 ALU : S3(2); // any 2 alus
5129 %}
5130
5131 // Integer ALU reg-reg operation
5132 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5133 single_instruction;
5134 dst : S4(write);
5135 src : S3(read);
5136 DECODE : S0; // any decoder
5137 ALU : S3; // any alu
5138 %}
5139
5140 // Long ALU reg-reg operation
5141 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5142 instruction_count(2);
5143 dst : S4(write);
5144 src : S3(read);
5145 DECODE : S0(2); // any 2 decoders
5146 ALU : S3(2); // both alus
5147 %}
5148
5149 // Integer ALU reg-reg operation
5150 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5151 single_instruction;
5152 dst : S4(write);
5153 src : S3(read);
5154 D0 : S0; // big decoder only
5155 ALU : S3; // any alu
5156 %}
5157
5158 // Long ALU reg-reg operation
5159 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5160 instruction_count(2);
5161 dst : S4(write);
5162 src : S3(read);
5163 D0 : S0(2); // big decoder only; twice
5164 ALU : S3(2); // both alus
5165 %}
5166
5167 // Integer ALU reg-mem operation
5168 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5169 single_instruction;
5170 dst : S5(write);
5171 mem : S3(read);
5172 D0 : S0; // big decoder only
5173 ALU : S4; // any alu
5174 MEM : S3; // any mem
5175 %}
5176
5177 // Long ALU reg-mem operation
5178 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5179 instruction_count(2);
5180 dst : S5(write);
5181 mem : S3(read);
5182 D0 : S0(2); // big decoder only; twice
5183 ALU : S4(2); // any 2 alus
5184 MEM : S3(2); // both mems
5185 %}
5186
5187 // Integer mem operation (prefetch)
5188 pipe_class ialu_mem(memory mem)
5189 %{
5190 single_instruction;
5191 mem : S3(read);
5192 D0 : S0; // big decoder only
5193 MEM : S3; // any mem
5194 %}
5195
5196 // Integer Store to Memory
5197 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5198 single_instruction;
5199 mem : S3(read);
5200 src : S5(read);
5201 D0 : S0; // big decoder only
5202 ALU : S4; // any alu
5203 MEM : S3;
5204 %}
5205
5206 // Long Store to Memory
5207 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5208 instruction_count(2);
5209 mem : S3(read);
5210 src : S5(read);
5211 D0 : S0(2); // big decoder only; twice
5212 ALU : S4(2); // any 2 alus
5213 MEM : S3(2); // Both mems
5214 %}
5215
5216 // Integer Store to Memory
5217 pipe_class ialu_mem_imm(memory mem) %{
5218 single_instruction;
5219 mem : S3(read);
5220 D0 : S0; // big decoder only
5221 ALU : S4; // any alu
5222 MEM : S3;
5223 %}
5224
5225 // Integer ALU0 reg-reg operation
5226 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5227 single_instruction;
5228 dst : S4(write);
5229 src : S3(read);
5230 D0 : S0; // Big decoder only
5231 ALU0 : S3; // only alu0
5232 %}
5233
5234 // Integer ALU0 reg-mem operation
5235 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5236 single_instruction;
5237 dst : S5(write);
5238 mem : S3(read);
5239 D0 : S0; // big decoder only
5240 ALU0 : S4; // ALU0 only
5241 MEM : S3; // any mem
5242 %}
5243
5244 // Integer ALU reg-reg operation
5245 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5246 single_instruction;
5247 cr : S4(write);
5248 src1 : S3(read);
5249 src2 : S3(read);
5250 DECODE : S0; // any decoder
5251 ALU : S3; // any alu
5252 %}
5253
5254 // Integer ALU reg-imm operation
5255 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5256 single_instruction;
5257 cr : S4(write);
5258 src1 : S3(read);
5259 DECODE : S0; // any decoder
5260 ALU : S3; // any alu
5261 %}
5262
5263 // Integer ALU reg-mem operation
5264 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5265 single_instruction;
5266 cr : S4(write);
5267 src1 : S3(read);
5268 src2 : S3(read);
5269 D0 : S0; // big decoder only
5270 ALU : S4; // any alu
5271 MEM : S3;
5272 %}
5273
5274 // Conditional move reg-reg
5275 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5276 instruction_count(4);
5277 y : S4(read);
5278 q : S3(read);
5279 p : S3(read);
5280 DECODE : S0(4); // any decoder
5281 %}
5282
5283 // Conditional move reg-reg
5284 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5285 single_instruction;
5286 dst : S4(write);
5287 src : S3(read);
5288 cr : S3(read);
5289 DECODE : S0; // any decoder
5290 %}
5291
5292 // Conditional move reg-mem
5293 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5294 single_instruction;
5295 dst : S4(write);
5296 src : S3(read);
5297 cr : S3(read);
5298 DECODE : S0; // any decoder
5299 MEM : S3;
5300 %}
5301
5302 // Conditional move reg-reg long
5303 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5304 single_instruction;
5305 dst : S4(write);
5306 src : S3(read);
5307 cr : S3(read);
5308 DECODE : S0(2); // any 2 decoders
5309 %}
5310
5311 // Conditional move double reg-reg
5312 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5313 single_instruction;
5314 dst : S4(write);
5315 src : S3(read);
5316 cr : S3(read);
5317 DECODE : S0; // any decoder
5318 %}
5319
5320 // Float reg-reg operation
5321 pipe_class fpu_reg(regDPR dst) %{
5322 instruction_count(2);
5323 dst : S3(read);
5324 DECODE : S0(2); // any 2 decoders
5325 FPU : S3;
5326 %}
5327
5328 // Float reg-reg operation
5329 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5330 instruction_count(2);
5331 dst : S4(write);
5332 src : S3(read);
5333 DECODE : S0(2); // any 2 decoders
5334 FPU : S3;
5335 %}
5336
5337 // Float reg-reg operation
5338 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5339 instruction_count(3);
5340 dst : S4(write);
5341 src1 : S3(read);
5342 src2 : S3(read);
5343 DECODE : S0(3); // any 3 decoders
5344 FPU : S3(2);
5345 %}
5346
5347 // Float reg-reg operation
5348 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5349 instruction_count(4);
5350 dst : S4(write);
5351 src1 : S3(read);
5352 src2 : S3(read);
5353 src3 : S3(read);
5354 DECODE : S0(4); // any 3 decoders
5355 FPU : S3(2);
5356 %}
5357
5358 // Float reg-reg operation
5359 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5360 instruction_count(4);
5361 dst : S4(write);
5362 src1 : S3(read);
5363 src2 : S3(read);
5364 src3 : S3(read);
5365 DECODE : S1(3); // any 3 decoders
5366 D0 : S0; // Big decoder only
5367 FPU : S3(2);
5368 MEM : S3;
5369 %}
5370
5371 // Float reg-mem operation
5372 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5373 instruction_count(2);
5374 dst : S5(write);
5375 mem : S3(read);
5376 D0 : S0; // big decoder only
5377 DECODE : S1; // any decoder for FPU POP
5378 FPU : S4;
5379 MEM : S3; // any mem
5380 %}
5381
5382 // Float reg-mem operation
5383 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5384 instruction_count(3);
5385 dst : S5(write);
5386 src1 : S3(read);
5387 mem : S3(read);
5388 D0 : S0; // big decoder only
5389 DECODE : S1(2); // any decoder for FPU POP
5390 FPU : S4;
5391 MEM : S3; // any mem
5392 %}
5393
5394 // Float mem-reg operation
5395 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5396 instruction_count(2);
5397 src : S5(read);
5398 mem : S3(read);
5399 DECODE : S0; // any decoder for FPU PUSH
5400 D0 : S1; // big decoder only
5401 FPU : S4;
5402 MEM : S3; // any mem
5403 %}
5404
5405 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5406 instruction_count(3);
5407 src1 : S3(read);
5408 src2 : S3(read);
5409 mem : S3(read);
5410 DECODE : S0(2); // any decoder for FPU PUSH
5411 D0 : S1; // big decoder only
5412 FPU : S4;
5413 MEM : S3; // any mem
5414 %}
5415
5416 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5417 instruction_count(3);
5418 src1 : S3(read);
5419 src2 : S3(read);
5420 mem : S4(read);
5421 DECODE : S0; // any decoder for FPU PUSH
5422 D0 : S0(2); // big decoder only
5423 FPU : S4;
5424 MEM : S3(2); // any mem
5425 %}
5426
5427 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5428 instruction_count(2);
5429 src1 : S3(read);
5430 dst : S4(read);
5431 D0 : S0(2); // big decoder only
5432 MEM : S3(2); // any mem
5433 %}
5434
5435 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5436 instruction_count(3);
5437 src1 : S3(read);
5438 src2 : S3(read);
5439 dst : S4(read);
5440 D0 : S0(3); // big decoder only
5441 FPU : S4;
5442 MEM : S3(3); // any mem
5443 %}
5444
5445 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5446 instruction_count(3);
5447 src1 : S4(read);
5448 mem : S4(read);
5449 DECODE : S0; // any decoder for FPU PUSH
5450 D0 : S0(2); // big decoder only
5451 FPU : S4;
5452 MEM : S3(2); // any mem
5453 %}
5454
5455 // Float load constant
5456 pipe_class fpu_reg_con(regDPR dst) %{
5457 instruction_count(2);
5458 dst : S5(write);
5459 D0 : S0; // big decoder only for the load
5460 DECODE : S1; // any decoder for FPU POP
5461 FPU : S4;
5462 MEM : S3; // any mem
5463 %}
5464
5465 // Float load constant
5466 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5467 instruction_count(3);
5468 dst : S5(write);
5469 src : S3(read);
5470 D0 : S0; // big decoder only for the load
5471 DECODE : S1(2); // any decoder for FPU POP
5472 FPU : S4;
5473 MEM : S3; // any mem
5474 %}
5475
5476 // UnConditional branch
5477 pipe_class pipe_jmp( label labl ) %{
5478 single_instruction;
5479 BR : S3;
5480 %}
5481
5482 // Conditional branch
5483 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5484 single_instruction;
5485 cr : S1(read);
5486 BR : S3;
5487 %}
5488
5489 // Allocation idiom
5490 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5491 instruction_count(1); force_serialization;
5492 fixed_latency(6);
5493 heap_ptr : S3(read);
5494 DECODE : S0(3);
5495 D0 : S2;
5496 MEM : S3;
5497 ALU : S3(2);
5498 dst : S5(write);
5499 BR : S5;
5500 %}
5501
5502 // Generic big/slow expanded idiom
5503 pipe_class pipe_slow( ) %{
5504 instruction_count(10); multiple_bundles; force_serialization;
5505 fixed_latency(100);
5506 D0 : S0(2);
5507 MEM : S3(2);
5508 %}
5509
5510 // The real do-nothing guy
5511 pipe_class empty( ) %{
5512 instruction_count(0);
5513 %}
5514
5515 // Define the class for the Nop node
5516 define %{
5517 MachNop = empty;
5518 %}
5519
5520 %}
5521
5522 //----------INSTRUCTIONS-------------------------------------------------------
5523 //
5524 // match -- States which machine-independent subtree may be replaced
5525 // by this instruction.
5526 // ins_cost -- The estimated cost of this instruction is used by instruction
5527 // selection to identify a minimum cost tree of machine
5528 // instructions that matches a tree of machine-independent
5529 // instructions.
5530 // format -- A string providing the disassembly for this instruction.
5531 // The value of an instruction's operand may be inserted
5532 // by referring to it with a '$' prefix.
5533 // opcode -- Three instruction opcodes may be provided. These are referred
5534 // to within an encode class as $primary, $secondary, and $tertiary
5535 // respectively. The primary opcode is commonly used to
5536 // indicate the type of machine instruction, while secondary
5537 // and tertiary are often used for prefix options or addressing
5538 // modes.
5539 // ins_encode -- A list of encode classes with parameters. The encode class
5540 // name must have been defined in an 'enc_class' specification
5541 // in the encode section of the architecture description.
5542
5543 //----------BSWAP-Instruction--------------------------------------------------
5544 instruct bytes_reverse_int(rRegI dst) %{
5545 match(Set dst (ReverseBytesI dst));
5546
5547 format %{ "BSWAP $dst" %}
5548 opcode(0x0F, 0xC8);
5549 ins_encode( OpcP, OpcSReg(dst) );
5550 ins_pipe( ialu_reg );
5551 %}
5552
5553 instruct bytes_reverse_long(eRegL dst) %{
5554 match(Set dst (ReverseBytesL dst));
5555
5556 format %{ "BSWAP $dst.lo\n\t"
5557 "BSWAP $dst.hi\n\t"
5558 "XCHG $dst.lo $dst.hi" %}
5559
5560 ins_cost(125);
5561 ins_encode( bswap_long_bytes(dst) );
5562 ins_pipe( ialu_reg_reg);
5563 %}
5564
5565 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5566 match(Set dst (ReverseBytesUS dst));
5567 effect(KILL cr);
5568
5569 format %{ "BSWAP $dst\n\t"
5570 "SHR $dst,16\n\t" %}
5571 ins_encode %{
5572 __ bswapl($dst$$Register);
5573 __ shrl($dst$$Register, 16);
5574 %}
5575 ins_pipe( ialu_reg );
5576 %}
5577
5578 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5579 match(Set dst (ReverseBytesS dst));
5580 effect(KILL cr);
5581
5582 format %{ "BSWAP $dst\n\t"
5583 "SAR $dst,16\n\t" %}
5584 ins_encode %{
5585 __ bswapl($dst$$Register);
5586 __ sarl($dst$$Register, 16);
5587 %}
5588 ins_pipe( ialu_reg );
5589 %}
5590
5591
5592 //---------- Zeros Count Instructions ------------------------------------------
5593
5594 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5595 predicate(UseCountLeadingZerosInstruction);
5596 match(Set dst (CountLeadingZerosI src));
5597 effect(KILL cr);
5598
5599 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5600 ins_encode %{
5601 __ lzcntl($dst$$Register, $src$$Register);
5602 %}
5603 ins_pipe(ialu_reg);
5604 %}
5605
5606 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5607 predicate(!UseCountLeadingZerosInstruction);
5608 match(Set dst (CountLeadingZerosI src));
5609 effect(KILL cr);
5610
5611 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5612 "JNZ skip\n\t"
5613 "MOV $dst, -1\n"
5614 "skip:\n\t"
5615 "NEG $dst\n\t"
5616 "ADD $dst, 31" %}
5617 ins_encode %{
5618 Register Rdst = $dst$$Register;
5619 Register Rsrc = $src$$Register;
5620 Label skip;
5621 __ bsrl(Rdst, Rsrc);
5622 __ jccb(Assembler::notZero, skip);
5623 __ movl(Rdst, -1);
5624 __ bind(skip);
5625 __ negl(Rdst);
5626 __ addl(Rdst, BitsPerInt - 1);
5627 %}
5628 ins_pipe(ialu_reg);
5629 %}
5630
5631 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5632 predicate(UseCountLeadingZerosInstruction);
5633 match(Set dst (CountLeadingZerosL src));
5634 effect(TEMP dst, KILL cr);
5635
5636 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5637 "JNC done\n\t"
5638 "LZCNT $dst, $src.lo\n\t"
5639 "ADD $dst, 32\n"
5640 "done:" %}
5641 ins_encode %{
5642 Register Rdst = $dst$$Register;
5643 Register Rsrc = $src$$Register;
5644 Label done;
5645 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5646 __ jccb(Assembler::carryClear, done);
5647 __ lzcntl(Rdst, Rsrc);
5648 __ addl(Rdst, BitsPerInt);
5649 __ bind(done);
5650 %}
5651 ins_pipe(ialu_reg);
5652 %}
5653
5654 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5655 predicate(!UseCountLeadingZerosInstruction);
5656 match(Set dst (CountLeadingZerosL src));
5657 effect(TEMP dst, KILL cr);
5658
5659 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5660 "JZ msw_is_zero\n\t"
5661 "ADD $dst, 32\n\t"
5662 "JMP not_zero\n"
5663 "msw_is_zero:\n\t"
5664 "BSR $dst, $src.lo\n\t"
5665 "JNZ not_zero\n\t"
5666 "MOV $dst, -1\n"
5667 "not_zero:\n\t"
5668 "NEG $dst\n\t"
5669 "ADD $dst, 63\n" %}
5670 ins_encode %{
5671 Register Rdst = $dst$$Register;
5672 Register Rsrc = $src$$Register;
5673 Label msw_is_zero;
5674 Label not_zero;
5675 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5676 __ jccb(Assembler::zero, msw_is_zero);
5677 __ addl(Rdst, BitsPerInt);
5678 __ jmpb(not_zero);
5679 __ bind(msw_is_zero);
5680 __ bsrl(Rdst, Rsrc);
5681 __ jccb(Assembler::notZero, not_zero);
5682 __ movl(Rdst, -1);
5683 __ bind(not_zero);
5684 __ negl(Rdst);
5685 __ addl(Rdst, BitsPerLong - 1);
5686 %}
5687 ins_pipe(ialu_reg);
5688 %}
5689
5690 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5691 match(Set dst (CountTrailingZerosI src));
5692 effect(KILL cr);
5693
5694 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5695 "JNZ done\n\t"
5696 "MOV $dst, 32\n"
5697 "done:" %}
5698 ins_encode %{
5699 Register Rdst = $dst$$Register;
5700 Label done;
5701 __ bsfl(Rdst, $src$$Register);
5702 __ jccb(Assembler::notZero, done);
5703 __ movl(Rdst, BitsPerInt);
5704 __ bind(done);
5705 %}
5706 ins_pipe(ialu_reg);
5707 %}
5708
5709 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5710 match(Set dst (CountTrailingZerosL src));
5711 effect(TEMP dst, KILL cr);
5712
5713 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5714 "JNZ done\n\t"
5715 "BSF $dst, $src.hi\n\t"
5716 "JNZ msw_not_zero\n\t"
5717 "MOV $dst, 32\n"
5718 "msw_not_zero:\n\t"
5719 "ADD $dst, 32\n"
5720 "done:" %}
5721 ins_encode %{
5722 Register Rdst = $dst$$Register;
5723 Register Rsrc = $src$$Register;
5724 Label msw_not_zero;
5725 Label done;
5726 __ bsfl(Rdst, Rsrc);
5727 __ jccb(Assembler::notZero, done);
5728 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5729 __ jccb(Assembler::notZero, msw_not_zero);
5730 __ movl(Rdst, BitsPerInt);
5731 __ bind(msw_not_zero);
5732 __ addl(Rdst, BitsPerInt);
5733 __ bind(done);
5734 %}
5735 ins_pipe(ialu_reg);
5736 %}
5737
5738
5739 //---------- Population Count Instructions -------------------------------------
5740
5741 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5742 predicate(UsePopCountInstruction);
5743 match(Set dst (PopCountI src));
5744 effect(KILL cr);
5745
5746 format %{ "POPCNT $dst, $src" %}
5747 ins_encode %{
5748 __ popcntl($dst$$Register, $src$$Register);
5749 %}
5750 ins_pipe(ialu_reg);
5751 %}
5752
5753 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5754 predicate(UsePopCountInstruction);
5755 match(Set dst (PopCountI (LoadI mem)));
5756 effect(KILL cr);
5757
5758 format %{ "POPCNT $dst, $mem" %}
5759 ins_encode %{
5760 __ popcntl($dst$$Register, $mem$$Address);
5761 %}
5762 ins_pipe(ialu_reg);
5763 %}
5764
5765 // Note: Long.bitCount(long) returns an int.
5766 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5767 predicate(UsePopCountInstruction);
5768 match(Set dst (PopCountL src));
5769 effect(KILL cr, TEMP tmp, TEMP dst);
5770
5771 format %{ "POPCNT $dst, $src.lo\n\t"
5772 "POPCNT $tmp, $src.hi\n\t"
5773 "ADD $dst, $tmp" %}
5774 ins_encode %{
5775 __ popcntl($dst$$Register, $src$$Register);
5776 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5777 __ addl($dst$$Register, $tmp$$Register);
5778 %}
5779 ins_pipe(ialu_reg);
5780 %}
5781
5782 // Note: Long.bitCount(long) returns an int.
5783 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5784 predicate(UsePopCountInstruction);
5785 match(Set dst (PopCountL (LoadL mem)));
5786 effect(KILL cr, TEMP tmp, TEMP dst);
5787
5788 format %{ "POPCNT $dst, $mem\n\t"
5789 "POPCNT $tmp, $mem+4\n\t"
5790 "ADD $dst, $tmp" %}
5791 ins_encode %{
5792 //__ popcntl($dst$$Register, $mem$$Address$$first);
5793 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5794 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5795 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5796 __ addl($dst$$Register, $tmp$$Register);
5797 %}
5798 ins_pipe(ialu_reg);
5799 %}
5800
5801
5802 //----------Load/Store/Move Instructions---------------------------------------
5803 //----------Load Instructions--------------------------------------------------
5804 // Load Byte (8bit signed)
5805 instruct loadB(xRegI dst, memory mem) %{
5806 match(Set dst (LoadB mem));
5807
5808 ins_cost(125);
5809 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5810
5811 ins_encode %{
5812 __ movsbl($dst$$Register, $mem$$Address);
5813 %}
5814
5815 ins_pipe(ialu_reg_mem);
5816 %}
5817
5818 // Load Byte (8bit signed) into Long Register
5819 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5820 match(Set dst (ConvI2L (LoadB mem)));
5821 effect(KILL cr);
5822
5823 ins_cost(375);
5824 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5825 "MOV $dst.hi,$dst.lo\n\t"
5826 "SAR $dst.hi,7" %}
5827
5828 ins_encode %{
5829 __ movsbl($dst$$Register, $mem$$Address);
5830 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5831 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5832 %}
5833
5834 ins_pipe(ialu_reg_mem);
5835 %}
5836
5837 // Load Unsigned Byte (8bit UNsigned)
5838 instruct loadUB(xRegI dst, memory mem) %{
5839 match(Set dst (LoadUB mem));
5840
5841 ins_cost(125);
5842 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5843
5844 ins_encode %{
5845 __ movzbl($dst$$Register, $mem$$Address);
5846 %}
5847
5848 ins_pipe(ialu_reg_mem);
5849 %}
5850
5851 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5852 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5853 match(Set dst (ConvI2L (LoadUB mem)));
5854 effect(KILL cr);
5855
5856 ins_cost(250);
5857 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5858 "XOR $dst.hi,$dst.hi" %}
5859
5860 ins_encode %{
5861 Register Rdst = $dst$$Register;
5862 __ movzbl(Rdst, $mem$$Address);
5863 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5864 %}
5865
5866 ins_pipe(ialu_reg_mem);
5867 %}
5868
5869 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5870 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5871 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5872 effect(KILL cr);
5873
5874 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5875 "XOR $dst.hi,$dst.hi\n\t"
5876 "AND $dst.lo,$mask" %}
5877 ins_encode %{
5878 Register Rdst = $dst$$Register;
5879 __ movzbl(Rdst, $mem$$Address);
5880 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5881 __ andl(Rdst, $mask$$constant);
5882 %}
5883 ins_pipe(ialu_reg_mem);
5884 %}
5885
5886 // Load Short (16bit signed)
5887 instruct loadS(rRegI dst, memory mem) %{
5888 match(Set dst (LoadS mem));
5889
5890 ins_cost(125);
5891 format %{ "MOVSX $dst,$mem\t# short" %}
5892
5893 ins_encode %{
5894 __ movswl($dst$$Register, $mem$$Address);
5895 %}
5896
5897 ins_pipe(ialu_reg_mem);
5898 %}
5899
5900 // Load Short (16 bit signed) to Byte (8 bit signed)
5901 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5902 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5903
5904 ins_cost(125);
5905 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5906 ins_encode %{
5907 __ movsbl($dst$$Register, $mem$$Address);
5908 %}
5909 ins_pipe(ialu_reg_mem);
5910 %}
5911
5912 // Load Short (16bit signed) into Long Register
5913 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5914 match(Set dst (ConvI2L (LoadS mem)));
5915 effect(KILL cr);
5916
5917 ins_cost(375);
5918 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5919 "MOV $dst.hi,$dst.lo\n\t"
5920 "SAR $dst.hi,15" %}
5921
5922 ins_encode %{
5923 __ movswl($dst$$Register, $mem$$Address);
5924 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5925 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5926 %}
5927
5928 ins_pipe(ialu_reg_mem);
5929 %}
5930
5931 // Load Unsigned Short/Char (16bit unsigned)
5932 instruct loadUS(rRegI dst, memory mem) %{
5933 match(Set dst (LoadUS mem));
5934
5935 ins_cost(125);
5936 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5937
5938 ins_encode %{
5939 __ movzwl($dst$$Register, $mem$$Address);
5940 %}
5941
5942 ins_pipe(ialu_reg_mem);
5943 %}
5944
5945 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5946 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5947 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5948
5949 ins_cost(125);
5950 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5951 ins_encode %{
5952 __ movsbl($dst$$Register, $mem$$Address);
5953 %}
5954 ins_pipe(ialu_reg_mem);
5955 %}
5956
5957 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5958 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5959 match(Set dst (ConvI2L (LoadUS mem)));
5960 effect(KILL cr);
5961
5962 ins_cost(250);
5963 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5964 "XOR $dst.hi,$dst.hi" %}
5965
5966 ins_encode %{
5967 __ movzwl($dst$$Register, $mem$$Address);
5968 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5969 %}
5970
5971 ins_pipe(ialu_reg_mem);
5972 %}
5973
5974 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5975 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5976 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5977 effect(KILL cr);
5978
5979 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5980 "XOR $dst.hi,$dst.hi" %}
5981 ins_encode %{
5982 Register Rdst = $dst$$Register;
5983 __ movzbl(Rdst, $mem$$Address);
5984 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5985 %}
5986 ins_pipe(ialu_reg_mem);
5987 %}
5988
5989 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5990 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5991 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5992 effect(KILL cr);
5993
5994 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5995 "XOR $dst.hi,$dst.hi\n\t"
5996 "AND $dst.lo,$mask" %}
5997 ins_encode %{
5998 Register Rdst = $dst$$Register;
5999 __ movzwl(Rdst, $mem$$Address);
6000 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6001 __ andl(Rdst, $mask$$constant);
6002 %}
6003 ins_pipe(ialu_reg_mem);
6004 %}
6005
6006 // Load Integer
6007 instruct loadI(rRegI dst, memory mem) %{
6008 match(Set dst (LoadI mem));
6009
6010 ins_cost(125);
6011 format %{ "MOV $dst,$mem\t# int" %}
6012
6013 ins_encode %{
6014 __ movl($dst$$Register, $mem$$Address);
6015 %}
6016
6017 ins_pipe(ialu_reg_mem);
6018 %}
6019
6020 // Load Integer (32 bit signed) to Byte (8 bit signed)
6021 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6022 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6023
6024 ins_cost(125);
6025 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6026 ins_encode %{
6027 __ movsbl($dst$$Register, $mem$$Address);
6028 %}
6029 ins_pipe(ialu_reg_mem);
6030 %}
6031
6032 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6033 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6034 match(Set dst (AndI (LoadI mem) mask));
6035
6036 ins_cost(125);
6037 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6038 ins_encode %{
6039 __ movzbl($dst$$Register, $mem$$Address);
6040 %}
6041 ins_pipe(ialu_reg_mem);
6042 %}
6043
6044 // Load Integer (32 bit signed) to Short (16 bit signed)
6045 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6046 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6047
6048 ins_cost(125);
6049 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6050 ins_encode %{
6051 __ movswl($dst$$Register, $mem$$Address);
6052 %}
6053 ins_pipe(ialu_reg_mem);
6054 %}
6055
6056 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6057 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6058 match(Set dst (AndI (LoadI mem) mask));
6059
6060 ins_cost(125);
6061 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6062 ins_encode %{
6063 __ movzwl($dst$$Register, $mem$$Address);
6064 %}
6065 ins_pipe(ialu_reg_mem);
6066 %}
6067
6068 // Load Integer into Long Register
6069 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6070 match(Set dst (ConvI2L (LoadI mem)));
6071 effect(KILL cr);
6072
6073 ins_cost(375);
6074 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6075 "MOV $dst.hi,$dst.lo\n\t"
6076 "SAR $dst.hi,31" %}
6077
6078 ins_encode %{
6079 __ movl($dst$$Register, $mem$$Address);
6080 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6081 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6082 %}
6083
6084 ins_pipe(ialu_reg_mem);
6085 %}
6086
6087 // Load Integer with mask 0xFF into Long Register
6088 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6089 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6090 effect(KILL cr);
6091
6092 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6093 "XOR $dst.hi,$dst.hi" %}
6094 ins_encode %{
6095 Register Rdst = $dst$$Register;
6096 __ movzbl(Rdst, $mem$$Address);
6097 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6098 %}
6099 ins_pipe(ialu_reg_mem);
6100 %}
6101
6102 // Load Integer with mask 0xFFFF into Long Register
6103 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6104 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6105 effect(KILL cr);
6106
6107 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6108 "XOR $dst.hi,$dst.hi" %}
6109 ins_encode %{
6110 Register Rdst = $dst$$Register;
6111 __ movzwl(Rdst, $mem$$Address);
6112 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6113 %}
6114 ins_pipe(ialu_reg_mem);
6115 %}
6116
6117 // Load Integer with 32-bit mask into Long Register
6118 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6119 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6120 effect(KILL cr);
6121
6122 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6123 "XOR $dst.hi,$dst.hi\n\t"
6124 "AND $dst.lo,$mask" %}
6125 ins_encode %{
6126 Register Rdst = $dst$$Register;
6127 __ movl(Rdst, $mem$$Address);
6128 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6129 __ andl(Rdst, $mask$$constant);
6130 %}
6131 ins_pipe(ialu_reg_mem);
6132 %}
6133
6134 // Load Unsigned Integer into Long Register
6135 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6136 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6137 effect(KILL cr);
6138
6139 ins_cost(250);
6140 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6141 "XOR $dst.hi,$dst.hi" %}
6142
6143 ins_encode %{
6144 __ movl($dst$$Register, $mem$$Address);
6145 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6146 %}
6147
6148 ins_pipe(ialu_reg_mem);
6149 %}
6150
6151 // Load Long. Cannot clobber address while loading, so restrict address
6152 // register to ESI
6153 instruct loadL(eRegL dst, load_long_memory mem) %{
6154 predicate(!((LoadLNode*)n)->require_atomic_access());
6155 match(Set dst (LoadL mem));
6156
6157 ins_cost(250);
6158 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6159 "MOV $dst.hi,$mem+4" %}
6160
6161 ins_encode %{
6162 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6163 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6164 __ movl($dst$$Register, Amemlo);
6165 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6166 %}
6167
6168 ins_pipe(ialu_reg_long_mem);
6169 %}
6170
6171 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6172 // then store it down to the stack and reload on the int
6173 // side.
6174 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6175 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6176 match(Set dst (LoadL mem));
6177
6178 ins_cost(200);
6179 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6180 "FISTp $dst" %}
6181 ins_encode(enc_loadL_volatile(mem,dst));
6182 ins_pipe( fpu_reg_mem );
6183 %}
6184
6185 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6186 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6187 match(Set dst (LoadL mem));
6188 effect(TEMP tmp);
6189 ins_cost(180);
6190 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6191 "MOVSD $dst,$tmp" %}
6192 ins_encode %{
6193 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6194 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6195 %}
6196 ins_pipe( pipe_slow );
6197 %}
6198
6199 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6200 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6201 match(Set dst (LoadL mem));
6202 effect(TEMP tmp);
6203 ins_cost(160);
6204 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6205 "MOVD $dst.lo,$tmp\n\t"
6206 "PSRLQ $tmp,32\n\t"
6207 "MOVD $dst.hi,$tmp" %}
6208 ins_encode %{
6209 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6210 __ movdl($dst$$Register, $tmp$$XMMRegister);
6211 __ psrlq($tmp$$XMMRegister, 32);
6212 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6213 %}
6214 ins_pipe( pipe_slow );
6215 %}
6216
6217 // Load Range
6218 instruct loadRange(rRegI dst, memory mem) %{
6219 match(Set dst (LoadRange mem));
6220
6221 ins_cost(125);
6222 format %{ "MOV $dst,$mem" %}
6223 opcode(0x8B);
6224 ins_encode( OpcP, RegMem(dst,mem));
6225 ins_pipe( ialu_reg_mem );
6226 %}
6227
6228
6229 // Load Pointer
6230 instruct loadP(eRegP dst, memory mem) %{
6231 match(Set dst (LoadP mem));
6232
6233 ins_cost(125);
6234 format %{ "MOV $dst,$mem" %}
6235 opcode(0x8B);
6236 ins_encode( OpcP, RegMem(dst,mem));
6237 ins_pipe( ialu_reg_mem );
6238 %}
6239
6240 // Load Klass Pointer
6241 instruct loadKlass(eRegP dst, memory mem) %{
6242 match(Set dst (LoadKlass mem));
6243
6244 ins_cost(125);
6245 format %{ "MOV $dst,$mem" %}
6246 opcode(0x8B);
6247 ins_encode( OpcP, RegMem(dst,mem));
6248 ins_pipe( ialu_reg_mem );
6249 %}
6250
6251 // Load Double
6252 instruct loadDPR(regDPR dst, memory mem) %{
6253 predicate(UseSSE<=1);
6254 match(Set dst (LoadD mem));
6255
6256 ins_cost(150);
6257 format %{ "FLD_D ST,$mem\n\t"
6258 "FSTP $dst" %}
6259 opcode(0xDD); /* DD /0 */
6260 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6261 Pop_Reg_DPR(dst) );
6262 ins_pipe( fpu_reg_mem );
6263 %}
6264
6265 // Load Double to XMM
6266 instruct loadD(regD dst, memory mem) %{
6267 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6268 match(Set dst (LoadD mem));
6269 ins_cost(145);
6270 format %{ "MOVSD $dst,$mem" %}
6271 ins_encode %{
6272 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6273 %}
6274 ins_pipe( pipe_slow );
6275 %}
6276
6277 instruct loadD_partial(regD dst, memory mem) %{
6278 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6279 match(Set dst (LoadD mem));
6280 ins_cost(145);
6281 format %{ "MOVLPD $dst,$mem" %}
6282 ins_encode %{
6283 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6284 %}
6285 ins_pipe( pipe_slow );
6286 %}
6287
6288 // Load to XMM register (single-precision floating point)
6289 // MOVSS instruction
6290 instruct loadF(regF dst, memory mem) %{
6291 predicate(UseSSE>=1);
6292 match(Set dst (LoadF mem));
6293 ins_cost(145);
6294 format %{ "MOVSS $dst,$mem" %}
6295 ins_encode %{
6296 __ movflt ($dst$$XMMRegister, $mem$$Address);
6297 %}
6298 ins_pipe( pipe_slow );
6299 %}
6300
6301 // Load Float
6302 instruct loadFPR(regFPR dst, memory mem) %{
6303 predicate(UseSSE==0);
6304 match(Set dst (LoadF mem));
6305
6306 ins_cost(150);
6307 format %{ "FLD_S ST,$mem\n\t"
6308 "FSTP $dst" %}
6309 opcode(0xD9); /* D9 /0 */
6310 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6311 Pop_Reg_FPR(dst) );
6312 ins_pipe( fpu_reg_mem );
6313 %}
6314
6315 // Load Effective Address
6316 instruct leaP8(eRegP dst, indOffset8 mem) %{
6317 match(Set dst mem);
6318
6319 ins_cost(110);
6320 format %{ "LEA $dst,$mem" %}
6321 opcode(0x8D);
6322 ins_encode( OpcP, RegMem(dst,mem));
6323 ins_pipe( ialu_reg_reg_fat );
6324 %}
6325
6326 instruct leaP32(eRegP dst, indOffset32 mem) %{
6327 match(Set dst mem);
6328
6329 ins_cost(110);
6330 format %{ "LEA $dst,$mem" %}
6331 opcode(0x8D);
6332 ins_encode( OpcP, RegMem(dst,mem));
6333 ins_pipe( ialu_reg_reg_fat );
6334 %}
6335
6336 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6337 match(Set dst mem);
6338
6339 ins_cost(110);
6340 format %{ "LEA $dst,$mem" %}
6341 opcode(0x8D);
6342 ins_encode( OpcP, RegMem(dst,mem));
6343 ins_pipe( ialu_reg_reg_fat );
6344 %}
6345
6346 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6347 match(Set dst mem);
6348
6349 ins_cost(110);
6350 format %{ "LEA $dst,$mem" %}
6351 opcode(0x8D);
6352 ins_encode( OpcP, RegMem(dst,mem));
6353 ins_pipe( ialu_reg_reg_fat );
6354 %}
6355
6356 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6357 match(Set dst mem);
6358
6359 ins_cost(110);
6360 format %{ "LEA $dst,$mem" %}
6361 opcode(0x8D);
6362 ins_encode( OpcP, RegMem(dst,mem));
6363 ins_pipe( ialu_reg_reg_fat );
6364 %}
6365
6366 // Load Constant
6367 instruct loadConI(rRegI dst, immI src) %{
6368 match(Set dst src);
6369
6370 format %{ "MOV $dst,$src" %}
6371 ins_encode( LdImmI(dst, src) );
6372 ins_pipe( ialu_reg_fat );
6373 %}
6374
6375 // Load Constant zero
6376 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6377 match(Set dst src);
6378 effect(KILL cr);
6379
6380 ins_cost(50);
6381 format %{ "XOR $dst,$dst" %}
6382 opcode(0x33); /* + rd */
6383 ins_encode( OpcP, RegReg( dst, dst ) );
6384 ins_pipe( ialu_reg );
6385 %}
6386
6387 instruct loadConP(eRegP dst, immP src) %{
6388 match(Set dst src);
6389
6390 format %{ "MOV $dst,$src" %}
6391 opcode(0xB8); /* + rd */
6392 ins_encode( LdImmP(dst, src) );
6393 ins_pipe( ialu_reg_fat );
6394 %}
6395
6396 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6397 match(Set dst src);
6398 effect(KILL cr);
6399 ins_cost(200);
6400 format %{ "MOV $dst.lo,$src.lo\n\t"
6401 "MOV $dst.hi,$src.hi" %}
6402 opcode(0xB8);
6403 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6404 ins_pipe( ialu_reg_long_fat );
6405 %}
6406
6407 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6408 match(Set dst src);
6409 effect(KILL cr);
6410 ins_cost(150);
6411 format %{ "XOR $dst.lo,$dst.lo\n\t"
6412 "XOR $dst.hi,$dst.hi" %}
6413 opcode(0x33,0x33);
6414 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6415 ins_pipe( ialu_reg_long );
6416 %}
6417
6418 // The instruction usage is guarded by predicate in operand immFPR().
6419 instruct loadConFPR(regFPR dst, immFPR con) %{
6420 match(Set dst con);
6421 ins_cost(125);
6422 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6423 "FSTP $dst" %}
6424 ins_encode %{
6425 __ fld_s($constantaddress($con));
6426 __ fstp_d($dst$$reg);
6427 %}
6428 ins_pipe(fpu_reg_con);
6429 %}
6430
6431 // The instruction usage is guarded by predicate in operand immFPR0().
6432 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6433 match(Set dst con);
6434 ins_cost(125);
6435 format %{ "FLDZ ST\n\t"
6436 "FSTP $dst" %}
6437 ins_encode %{
6438 __ fldz();
6439 __ fstp_d($dst$$reg);
6440 %}
6441 ins_pipe(fpu_reg_con);
6442 %}
6443
6444 // The instruction usage is guarded by predicate in operand immFPR1().
6445 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6446 match(Set dst con);
6447 ins_cost(125);
6448 format %{ "FLD1 ST\n\t"
6449 "FSTP $dst" %}
6450 ins_encode %{
6451 __ fld1();
6452 __ fstp_d($dst$$reg);
6453 %}
6454 ins_pipe(fpu_reg_con);
6455 %}
6456
6457 // The instruction usage is guarded by predicate in operand immF().
6458 instruct loadConF(regF dst, immF con) %{
6459 match(Set dst con);
6460 ins_cost(125);
6461 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6462 ins_encode %{
6463 __ movflt($dst$$XMMRegister, $constantaddress($con));
6464 %}
6465 ins_pipe(pipe_slow);
6466 %}
6467
6468 // The instruction usage is guarded by predicate in operand immF0().
6469 instruct loadConF0(regF dst, immF0 src) %{
6470 match(Set dst src);
6471 ins_cost(100);
6472 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6473 ins_encode %{
6474 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6475 %}
6476 ins_pipe(pipe_slow);
6477 %}
6478
6479 // The instruction usage is guarded by predicate in operand immDPR().
6480 instruct loadConDPR(regDPR dst, immDPR con) %{
6481 match(Set dst con);
6482 ins_cost(125);
6483
6484 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6485 "FSTP $dst" %}
6486 ins_encode %{
6487 __ fld_d($constantaddress($con));
6488 __ fstp_d($dst$$reg);
6489 %}
6490 ins_pipe(fpu_reg_con);
6491 %}
6492
6493 // The instruction usage is guarded by predicate in operand immDPR0().
6494 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6495 match(Set dst con);
6496 ins_cost(125);
6497
6498 format %{ "FLDZ ST\n\t"
6499 "FSTP $dst" %}
6500 ins_encode %{
6501 __ fldz();
6502 __ fstp_d($dst$$reg);
6503 %}
6504 ins_pipe(fpu_reg_con);
6505 %}
6506
6507 // The instruction usage is guarded by predicate in operand immDPR1().
6508 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6509 match(Set dst con);
6510 ins_cost(125);
6511
6512 format %{ "FLD1 ST\n\t"
6513 "FSTP $dst" %}
6514 ins_encode %{
6515 __ fld1();
6516 __ fstp_d($dst$$reg);
6517 %}
6518 ins_pipe(fpu_reg_con);
6519 %}
6520
6521 // The instruction usage is guarded by predicate in operand immD().
6522 instruct loadConD(regD dst, immD con) %{
6523 match(Set dst con);
6524 ins_cost(125);
6525 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6526 ins_encode %{
6527 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6528 %}
6529 ins_pipe(pipe_slow);
6530 %}
6531
6532 // The instruction usage is guarded by predicate in operand immD0().
6533 instruct loadConD0(regD dst, immD0 src) %{
6534 match(Set dst src);
6535 ins_cost(100);
6536 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6537 ins_encode %{
6538 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6539 %}
6540 ins_pipe( pipe_slow );
6541 %}
6542
6543 // Load Stack Slot
6544 instruct loadSSI(rRegI dst, stackSlotI src) %{
6545 match(Set dst src);
6546 ins_cost(125);
6547
6548 format %{ "MOV $dst,$src" %}
6549 opcode(0x8B);
6550 ins_encode( OpcP, RegMem(dst,src));
6551 ins_pipe( ialu_reg_mem );
6552 %}
6553
6554 instruct loadSSL(eRegL dst, stackSlotL src) %{
6555 match(Set dst src);
6556
6557 ins_cost(200);
6558 format %{ "MOV $dst,$src.lo\n\t"
6559 "MOV $dst+4,$src.hi" %}
6560 opcode(0x8B, 0x8B);
6561 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6562 ins_pipe( ialu_mem_long_reg );
6563 %}
6564
6565 // Load Stack Slot
6566 instruct loadSSP(eRegP dst, stackSlotP src) %{
6567 match(Set dst src);
6568 ins_cost(125);
6569
6570 format %{ "MOV $dst,$src" %}
6571 opcode(0x8B);
6572 ins_encode( OpcP, RegMem(dst,src));
6573 ins_pipe( ialu_reg_mem );
6574 %}
6575
6576 // Load Stack Slot
6577 instruct loadSSF(regFPR dst, stackSlotF src) %{
6578 match(Set dst src);
6579 ins_cost(125);
6580
6581 format %{ "FLD_S $src\n\t"
6582 "FSTP $dst" %}
6583 opcode(0xD9); /* D9 /0, FLD m32real */
6584 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6585 Pop_Reg_FPR(dst) );
6586 ins_pipe( fpu_reg_mem );
6587 %}
6588
6589 // Load Stack Slot
6590 instruct loadSSD(regDPR dst, stackSlotD src) %{
6591 match(Set dst src);
6592 ins_cost(125);
6593
6594 format %{ "FLD_D $src\n\t"
6595 "FSTP $dst" %}
6596 opcode(0xDD); /* DD /0, FLD m64real */
6597 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6598 Pop_Reg_DPR(dst) );
6599 ins_pipe( fpu_reg_mem );
6600 %}
6601
6602 // Prefetch instructions.
6603 // Must be safe to execute with invalid address (cannot fault).
6604
6605 instruct prefetchr0( memory mem ) %{
6606 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6607 match(PrefetchRead mem);
6608 ins_cost(0);
6609 size(0);
6610 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6611 ins_encode();
6612 ins_pipe(empty);
6613 %}
6614
6615 instruct prefetchr( memory mem ) %{
6616 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6617 match(PrefetchRead mem);
6618 ins_cost(100);
6619
6620 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6621 ins_encode %{
6622 __ prefetchr($mem$$Address);
6623 %}
6624 ins_pipe(ialu_mem);
6625 %}
6626
6627 instruct prefetchrNTA( memory mem ) %{
6628 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6629 match(PrefetchRead mem);
6630 ins_cost(100);
6631
6632 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6633 ins_encode %{
6634 __ prefetchnta($mem$$Address);
6635 %}
6636 ins_pipe(ialu_mem);
6637 %}
6638
6639 instruct prefetchrT0( memory mem ) %{
6640 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6641 match(PrefetchRead mem);
6642 ins_cost(100);
6643
6644 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6645 ins_encode %{
6646 __ prefetcht0($mem$$Address);
6647 %}
6648 ins_pipe(ialu_mem);
6649 %}
6650
6651 instruct prefetchrT2( memory mem ) %{
6652 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6653 match(PrefetchRead mem);
6654 ins_cost(100);
6655
6656 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6657 ins_encode %{
6658 __ prefetcht2($mem$$Address);
6659 %}
6660 ins_pipe(ialu_mem);
6661 %}
6662
6663 instruct prefetchw0( memory mem ) %{
6664 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6665 match(PrefetchWrite mem);
6666 ins_cost(0);
6667 size(0);
6668 format %{ "Prefetch (non-SSE is empty encoding)" %}
6669 ins_encode();
6670 ins_pipe(empty);
6671 %}
6672
6673 instruct prefetchw( memory mem ) %{
6674 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6675 match( PrefetchWrite mem );
6676 ins_cost(100);
6677
6678 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6679 ins_encode %{
6680 __ prefetchw($mem$$Address);
6681 %}
6682 ins_pipe(ialu_mem);
6683 %}
6684
6685 instruct prefetchwNTA( memory mem ) %{
6686 predicate(UseSSE>=1);
6687 match(PrefetchWrite mem);
6688 ins_cost(100);
6689
6690 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6691 ins_encode %{
6692 __ prefetchnta($mem$$Address);
6693 %}
6694 ins_pipe(ialu_mem);
6695 %}
6696
6697 // Prefetch instructions for allocation.
6698
6699 instruct prefetchAlloc0( memory mem ) %{
6700 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6701 match(PrefetchAllocation mem);
6702 ins_cost(0);
6703 size(0);
6704 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6705 ins_encode();
6706 ins_pipe(empty);
6707 %}
6708
6709 instruct prefetchAlloc( memory mem ) %{
6710 predicate(AllocatePrefetchInstr==3);
6711 match( PrefetchAllocation mem );
6712 ins_cost(100);
6713
6714 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6715 ins_encode %{
6716 __ prefetchw($mem$$Address);
6717 %}
6718 ins_pipe(ialu_mem);
6719 %}
6720
6721 instruct prefetchAllocNTA( memory mem ) %{
6722 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6723 match(PrefetchAllocation mem);
6724 ins_cost(100);
6725
6726 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6727 ins_encode %{
6728 __ prefetchnta($mem$$Address);
6729 %}
6730 ins_pipe(ialu_mem);
6731 %}
6732
6733 instruct prefetchAllocT0( memory mem ) %{
6734 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6735 match(PrefetchAllocation mem);
6736 ins_cost(100);
6737
6738 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6739 ins_encode %{
6740 __ prefetcht0($mem$$Address);
6741 %}
6742 ins_pipe(ialu_mem);
6743 %}
6744
6745 instruct prefetchAllocT2( memory mem ) %{
6746 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6747 match(PrefetchAllocation mem);
6748 ins_cost(100);
6749
6750 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6751 ins_encode %{
6752 __ prefetcht2($mem$$Address);
6753 %}
6754 ins_pipe(ialu_mem);
6755 %}
6756
6757 //----------Store Instructions-------------------------------------------------
6758
6759 // Store Byte
6760 instruct storeB(memory mem, xRegI src) %{
6761 match(Set mem (StoreB mem src));
6762
6763 ins_cost(125);
6764 format %{ "MOV8 $mem,$src" %}
6765 opcode(0x88);
6766 ins_encode( OpcP, RegMem( src, mem ) );
6767 ins_pipe( ialu_mem_reg );
6768 %}
6769
6770 // Store Char/Short
6771 instruct storeC(memory mem, rRegI src) %{
6772 match(Set mem (StoreC mem src));
6773
6774 ins_cost(125);
6775 format %{ "MOV16 $mem,$src" %}
6776 opcode(0x89, 0x66);
6777 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6778 ins_pipe( ialu_mem_reg );
6779 %}
6780
6781 // Store Integer
6782 instruct storeI(memory mem, rRegI src) %{
6783 match(Set mem (StoreI mem src));
6784
6785 ins_cost(125);
6786 format %{ "MOV $mem,$src" %}
6787 opcode(0x89);
6788 ins_encode( OpcP, RegMem( src, mem ) );
6789 ins_pipe( ialu_mem_reg );
6790 %}
6791
6792 // Store Long
6793 instruct storeL(long_memory mem, eRegL src) %{
6794 predicate(!((StoreLNode*)n)->require_atomic_access());
6795 match(Set mem (StoreL mem src));
6796
6797 ins_cost(200);
6798 format %{ "MOV $mem,$src.lo\n\t"
6799 "MOV $mem+4,$src.hi" %}
6800 opcode(0x89, 0x89);
6801 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6802 ins_pipe( ialu_mem_long_reg );
6803 %}
6804
6805 // Store Long to Integer
6806 instruct storeL2I(memory mem, eRegL src) %{
6807 match(Set mem (StoreI mem (ConvL2I src)));
6808
6809 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6810 ins_encode %{
6811 __ movl($mem$$Address, $src$$Register);
6812 %}
6813 ins_pipe(ialu_mem_reg);
6814 %}
6815
6816 // Volatile Store Long. Must be atomic, so move it into
6817 // the FP TOS and then do a 64-bit FIST. Has to probe the
6818 // target address before the store (for null-ptr checks)
6819 // so the memory operand is used twice in the encoding.
6820 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6821 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6822 match(Set mem (StoreL mem src));
6823 effect( KILL cr );
6824 ins_cost(400);
6825 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6826 "FILD $src\n\t"
6827 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6828 opcode(0x3B);
6829 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6830 ins_pipe( fpu_reg_mem );
6831 %}
6832
6833 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6834 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6835 match(Set mem (StoreL mem src));
6836 effect( TEMP tmp, KILL cr );
6837 ins_cost(380);
6838 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6839 "MOVSD $tmp,$src\n\t"
6840 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6841 ins_encode %{
6842 __ cmpl(rax, $mem$$Address);
6843 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6844 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6845 %}
6846 ins_pipe( pipe_slow );
6847 %}
6848
6849 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6850 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6851 match(Set mem (StoreL mem src));
6852 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6853 ins_cost(360);
6854 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6855 "MOVD $tmp,$src.lo\n\t"
6856 "MOVD $tmp2,$src.hi\n\t"
6857 "PUNPCKLDQ $tmp,$tmp2\n\t"
6858 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6859 ins_encode %{
6860 __ cmpl(rax, $mem$$Address);
6861 __ movdl($tmp$$XMMRegister, $src$$Register);
6862 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6863 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6864 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6865 %}
6866 ins_pipe( pipe_slow );
6867 %}
6868
6869 // Store Pointer; for storing unknown oops and raw pointers
6870 instruct storeP(memory mem, anyRegP src) %{
6871 match(Set mem (StoreP mem src));
6872
6873 ins_cost(125);
6874 format %{ "MOV $mem,$src" %}
6875 opcode(0x89);
6876 ins_encode( OpcP, RegMem( src, mem ) );
6877 ins_pipe( ialu_mem_reg );
6878 %}
6879
6880 // Store Integer Immediate
6881 instruct storeImmI(memory mem, immI src) %{
6882 match(Set mem (StoreI mem src));
6883
6884 ins_cost(150);
6885 format %{ "MOV $mem,$src" %}
6886 opcode(0xC7); /* C7 /0 */
6887 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6888 ins_pipe( ialu_mem_imm );
6889 %}
6890
6891 // Store Short/Char Immediate
6892 instruct storeImmI16(memory mem, immI16 src) %{
6893 predicate(UseStoreImmI16);
6894 match(Set mem (StoreC mem src));
6895
6896 ins_cost(150);
6897 format %{ "MOV16 $mem,$src" %}
6898 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6899 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6900 ins_pipe( ialu_mem_imm );
6901 %}
6902
6903 // Store Pointer Immediate; null pointers or constant oops that do not
6904 // need card-mark barriers.
6905 instruct storeImmP(memory mem, immP src) %{
6906 match(Set mem (StoreP mem src));
6907
6908 ins_cost(150);
6909 format %{ "MOV $mem,$src" %}
6910 opcode(0xC7); /* C7 /0 */
6911 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6912 ins_pipe( ialu_mem_imm );
6913 %}
6914
6915 // Store Byte Immediate
6916 instruct storeImmB(memory mem, immI8 src) %{
6917 match(Set mem (StoreB mem src));
6918
6919 ins_cost(150);
6920 format %{ "MOV8 $mem,$src" %}
6921 opcode(0xC6); /* C6 /0 */
6922 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6923 ins_pipe( ialu_mem_imm );
6924 %}
6925
6926 // Store CMS card-mark Immediate
6927 instruct storeImmCM(memory mem, immI8 src) %{
6928 match(Set mem (StoreCM mem src));
6929
6930 ins_cost(150);
6931 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6932 opcode(0xC6); /* C6 /0 */
6933 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6934 ins_pipe( ialu_mem_imm );
6935 %}
6936
6937 // Store Double
6938 instruct storeDPR( memory mem, regDPR1 src) %{
6939 predicate(UseSSE<=1);
6940 match(Set mem (StoreD mem src));
6941
6942 ins_cost(100);
6943 format %{ "FST_D $mem,$src" %}
6944 opcode(0xDD); /* DD /2 */
6945 ins_encode( enc_FPR_store(mem,src) );
6946 ins_pipe( fpu_mem_reg );
6947 %}
6948
6949 // Store double does rounding on x86
6950 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6951 predicate(UseSSE<=1);
6952 match(Set mem (StoreD mem (RoundDouble src)));
6953
6954 ins_cost(100);
6955 format %{ "FST_D $mem,$src\t# round" %}
6956 opcode(0xDD); /* DD /2 */
6957 ins_encode( enc_FPR_store(mem,src) );
6958 ins_pipe( fpu_mem_reg );
6959 %}
6960
6961 // Store XMM register to memory (double-precision floating points)
6962 // MOVSD instruction
6963 instruct storeD(memory mem, regD src) %{
6964 predicate(UseSSE>=2);
6965 match(Set mem (StoreD mem src));
6966 ins_cost(95);
6967 format %{ "MOVSD $mem,$src" %}
6968 ins_encode %{
6969 __ movdbl($mem$$Address, $src$$XMMRegister);
6970 %}
6971 ins_pipe( pipe_slow );
6972 %}
6973
6974 // Store XMM register to memory (single-precision floating point)
6975 // MOVSS instruction
6976 instruct storeF(memory mem, regF src) %{
6977 predicate(UseSSE>=1);
6978 match(Set mem (StoreF mem src));
6979 ins_cost(95);
6980 format %{ "MOVSS $mem,$src" %}
6981 ins_encode %{
6982 __ movflt($mem$$Address, $src$$XMMRegister);
6983 %}
6984 ins_pipe( pipe_slow );
6985 %}
6986
6987 // Store Float
6988 instruct storeFPR( memory mem, regFPR1 src) %{
6989 predicate(UseSSE==0);
6990 match(Set mem (StoreF mem src));
6991
6992 ins_cost(100);
6993 format %{ "FST_S $mem,$src" %}
6994 opcode(0xD9); /* D9 /2 */
6995 ins_encode( enc_FPR_store(mem,src) );
6996 ins_pipe( fpu_mem_reg );
6997 %}
6998
6999 // Store Float does rounding on x86
7000 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7001 predicate(UseSSE==0);
7002 match(Set mem (StoreF mem (RoundFloat src)));
7003
7004 ins_cost(100);
7005 format %{ "FST_S $mem,$src\t# round" %}
7006 opcode(0xD9); /* D9 /2 */
7007 ins_encode( enc_FPR_store(mem,src) );
7008 ins_pipe( fpu_mem_reg );
7009 %}
7010
7011 // Store Float does rounding on x86
7012 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7013 predicate(UseSSE<=1);
7014 match(Set mem (StoreF mem (ConvD2F src)));
7015
7016 ins_cost(100);
7017 format %{ "FST_S $mem,$src\t# D-round" %}
7018 opcode(0xD9); /* D9 /2 */
7019 ins_encode( enc_FPR_store(mem,src) );
7020 ins_pipe( fpu_mem_reg );
7021 %}
7022
7023 // Store immediate Float value (it is faster than store from FPU register)
7024 // The instruction usage is guarded by predicate in operand immFPR().
7025 instruct storeFPR_imm( memory mem, immFPR src) %{
7026 match(Set mem (StoreF mem src));
7027
7028 ins_cost(50);
7029 format %{ "MOV $mem,$src\t# store float" %}
7030 opcode(0xC7); /* C7 /0 */
7031 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7032 ins_pipe( ialu_mem_imm );
7033 %}
7034
7035 // Store immediate Float value (it is faster than store from XMM register)
7036 // The instruction usage is guarded by predicate in operand immF().
7037 instruct storeF_imm( memory mem, immF src) %{
7038 match(Set mem (StoreF mem src));
7039
7040 ins_cost(50);
7041 format %{ "MOV $mem,$src\t# store float" %}
7042 opcode(0xC7); /* C7 /0 */
7043 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7044 ins_pipe( ialu_mem_imm );
7045 %}
7046
7047 // Store Integer to stack slot
7048 instruct storeSSI(stackSlotI dst, rRegI src) %{
7049 match(Set dst src);
7050
7051 ins_cost(100);
7052 format %{ "MOV $dst,$src" %}
7053 opcode(0x89);
7054 ins_encode( OpcPRegSS( dst, src ) );
7055 ins_pipe( ialu_mem_reg );
7056 %}
7057
7058 // Store Integer to stack slot
7059 instruct storeSSP(stackSlotP dst, eRegP src) %{
7060 match(Set dst src);
7061
7062 ins_cost(100);
7063 format %{ "MOV $dst,$src" %}
7064 opcode(0x89);
7065 ins_encode( OpcPRegSS( dst, src ) );
7066 ins_pipe( ialu_mem_reg );
7067 %}
7068
7069 // Store Long to stack slot
7070 instruct storeSSL(stackSlotL dst, eRegL src) %{
7071 match(Set dst src);
7072
7073 ins_cost(200);
7074 format %{ "MOV $dst,$src.lo\n\t"
7075 "MOV $dst+4,$src.hi" %}
7076 opcode(0x89, 0x89);
7077 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7078 ins_pipe( ialu_mem_long_reg );
7079 %}
7080
7081 //----------MemBar Instructions-----------------------------------------------
7082 // Memory barrier flavors
7083
7084 instruct membar_acquire() %{
7085 match(MemBarAcquire);
7086 ins_cost(400);
7087
7088 size(0);
7089 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7090 ins_encode();
7091 ins_pipe(empty);
7092 %}
7093
7094 instruct membar_acquire_lock() %{
7095 match(MemBarAcquireLock);
7096 ins_cost(0);
7097
7098 size(0);
7099 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7100 ins_encode( );
7101 ins_pipe(empty);
7102 %}
7103
7104 instruct membar_release() %{
7105 match(MemBarRelease);
7106 ins_cost(400);
7107
7108 size(0);
7109 format %{ "MEMBAR-release ! (empty encoding)" %}
7110 ins_encode( );
7111 ins_pipe(empty);
7112 %}
7113
7114 instruct membar_release_lock() %{
7115 match(MemBarReleaseLock);
7116 ins_cost(0);
7117
7118 size(0);
7119 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7120 ins_encode( );
7121 ins_pipe(empty);
7122 %}
7123
7124 instruct membar_volatile(eFlagsReg cr) %{
7125 match(MemBarVolatile);
7126 effect(KILL cr);
7127 ins_cost(400);
7128
7129 format %{
7130 $$template
7131 if (os::is_MP()) {
7132 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7133 } else {
7134 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7135 }
7136 %}
7137 ins_encode %{
7138 __ membar(Assembler::StoreLoad);
7139 %}
7140 ins_pipe(pipe_slow);
7141 %}
7142
7143 instruct unnecessary_membar_volatile() %{
7144 match(MemBarVolatile);
7145 predicate(Matcher::post_store_load_barrier(n));
7146 ins_cost(0);
7147
7148 size(0);
7149 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7150 ins_encode( );
7151 ins_pipe(empty);
7152 %}
7153
7154 instruct membar_storestore() %{
7155 match(MemBarStoreStore);
7156 ins_cost(0);
7157
7158 size(0);
7159 format %{ "MEMBAR-storestore (empty encoding)" %}
7160 ins_encode( );
7161 ins_pipe(empty);
7162 %}
7163
7164 //----------Move Instructions--------------------------------------------------
7165 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7166 match(Set dst (CastX2P src));
7167 format %{ "# X2P $dst, $src" %}
7168 ins_encode( /*empty encoding*/ );
7169 ins_cost(0);
7170 ins_pipe(empty);
7171 %}
7172
7173 instruct castP2X(rRegI dst, eRegP src ) %{
7174 match(Set dst (CastP2X src));
7175 ins_cost(50);
7176 format %{ "MOV $dst, $src\t# CastP2X" %}
7177 ins_encode( enc_Copy( dst, src) );
7178 ins_pipe( ialu_reg_reg );
7179 %}
7180
7181 //----------Conditional Move---------------------------------------------------
7182 // Conditional move
7183 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7184 predicate(!VM_Version::supports_cmov() );
7185 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7186 ins_cost(200);
7187 format %{ "J$cop,us skip\t# signed cmove\n\t"
7188 "MOV $dst,$src\n"
7189 "skip:" %}
7190 ins_encode %{
7191 Label Lskip;
7192 // Invert sense of branch from sense of CMOV
7193 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7194 __ movl($dst$$Register, $src$$Register);
7195 __ bind(Lskip);
7196 %}
7197 ins_pipe( pipe_cmov_reg );
7198 %}
7199
7200 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7201 predicate(!VM_Version::supports_cmov() );
7202 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7203 ins_cost(200);
7204 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7205 "MOV $dst,$src\n"
7206 "skip:" %}
7207 ins_encode %{
7208 Label Lskip;
7209 // Invert sense of branch from sense of CMOV
7210 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7211 __ movl($dst$$Register, $src$$Register);
7212 __ bind(Lskip);
7213 %}
7214 ins_pipe( pipe_cmov_reg );
7215 %}
7216
7217 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7218 predicate(VM_Version::supports_cmov() );
7219 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7220 ins_cost(200);
7221 format %{ "CMOV$cop $dst,$src" %}
7222 opcode(0x0F,0x40);
7223 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7224 ins_pipe( pipe_cmov_reg );
7225 %}
7226
7227 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7228 predicate(VM_Version::supports_cmov() );
7229 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7230 ins_cost(200);
7231 format %{ "CMOV$cop $dst,$src" %}
7232 opcode(0x0F,0x40);
7233 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7234 ins_pipe( pipe_cmov_reg );
7235 %}
7236
7237 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7238 predicate(VM_Version::supports_cmov() );
7239 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7240 ins_cost(200);
7241 expand %{
7242 cmovI_regU(cop, cr, dst, src);
7243 %}
7244 %}
7245
7246 // Conditional move
7247 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7248 predicate(VM_Version::supports_cmov() );
7249 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7250 ins_cost(250);
7251 format %{ "CMOV$cop $dst,$src" %}
7252 opcode(0x0F,0x40);
7253 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7254 ins_pipe( pipe_cmov_mem );
7255 %}
7256
7257 // Conditional move
7258 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7259 predicate(VM_Version::supports_cmov() );
7260 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7261 ins_cost(250);
7262 format %{ "CMOV$cop $dst,$src" %}
7263 opcode(0x0F,0x40);
7264 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7265 ins_pipe( pipe_cmov_mem );
7266 %}
7267
7268 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7269 predicate(VM_Version::supports_cmov() );
7270 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7271 ins_cost(250);
7272 expand %{
7273 cmovI_memU(cop, cr, dst, src);
7274 %}
7275 %}
7276
7277 // Conditional move
7278 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7279 predicate(VM_Version::supports_cmov() );
7280 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7281 ins_cost(200);
7282 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7283 opcode(0x0F,0x40);
7284 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7285 ins_pipe( pipe_cmov_reg );
7286 %}
7287
7288 // Conditional move (non-P6 version)
7289 // Note: a CMoveP is generated for stubs and native wrappers
7290 // regardless of whether we are on a P6, so we
7291 // emulate a cmov here
7292 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7293 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7294 ins_cost(300);
7295 format %{ "Jn$cop skip\n\t"
7296 "MOV $dst,$src\t# pointer\n"
7297 "skip:" %}
7298 opcode(0x8b);
7299 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7300 ins_pipe( pipe_cmov_reg );
7301 %}
7302
7303 // Conditional move
7304 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7305 predicate(VM_Version::supports_cmov() );
7306 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7307 ins_cost(200);
7308 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7309 opcode(0x0F,0x40);
7310 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7311 ins_pipe( pipe_cmov_reg );
7312 %}
7313
7314 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7315 predicate(VM_Version::supports_cmov() );
7316 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7317 ins_cost(200);
7318 expand %{
7319 cmovP_regU(cop, cr, dst, src);
7320 %}
7321 %}
7322
7323 // DISABLED: Requires the ADLC to emit a bottom_type call that
7324 // correctly meets the two pointer arguments; one is an incoming
7325 // register but the other is a memory operand. ALSO appears to
7326 // be buggy with implicit null checks.
7327 //
7328 //// Conditional move
7329 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7330 // predicate(VM_Version::supports_cmov() );
7331 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7332 // ins_cost(250);
7333 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7334 // opcode(0x0F,0x40);
7335 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7336 // ins_pipe( pipe_cmov_mem );
7337 //%}
7338 //
7339 //// Conditional move
7340 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7341 // predicate(VM_Version::supports_cmov() );
7342 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7343 // ins_cost(250);
7344 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7345 // opcode(0x0F,0x40);
7346 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7347 // ins_pipe( pipe_cmov_mem );
7348 //%}
7349
7350 // Conditional move
7351 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7352 predicate(UseSSE<=1);
7353 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7354 ins_cost(200);
7355 format %{ "FCMOV$cop $dst,$src\t# double" %}
7356 opcode(0xDA);
7357 ins_encode( enc_cmov_dpr(cop,src) );
7358 ins_pipe( pipe_cmovDPR_reg );
7359 %}
7360
7361 // Conditional move
7362 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7363 predicate(UseSSE==0);
7364 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7365 ins_cost(200);
7366 format %{ "FCMOV$cop $dst,$src\t# float" %}
7367 opcode(0xDA);
7368 ins_encode( enc_cmov_dpr(cop,src) );
7369 ins_pipe( pipe_cmovDPR_reg );
7370 %}
7371
7372 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7373 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7374 predicate(UseSSE<=1);
7375 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7376 ins_cost(200);
7377 format %{ "Jn$cop skip\n\t"
7378 "MOV $dst,$src\t# double\n"
7379 "skip:" %}
7380 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7381 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7382 ins_pipe( pipe_cmovDPR_reg );
7383 %}
7384
7385 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7386 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7387 predicate(UseSSE==0);
7388 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7389 ins_cost(200);
7390 format %{ "Jn$cop skip\n\t"
7391 "MOV $dst,$src\t# float\n"
7392 "skip:" %}
7393 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7394 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7395 ins_pipe( pipe_cmovDPR_reg );
7396 %}
7397
7398 // No CMOVE with SSE/SSE2
7399 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7400 predicate (UseSSE>=1);
7401 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7402 ins_cost(200);
7403 format %{ "Jn$cop skip\n\t"
7404 "MOVSS $dst,$src\t# float\n"
7405 "skip:" %}
7406 ins_encode %{
7407 Label skip;
7408 // Invert sense of branch from sense of CMOV
7409 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7410 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7411 __ bind(skip);
7412 %}
7413 ins_pipe( pipe_slow );
7414 %}
7415
7416 // No CMOVE with SSE/SSE2
7417 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7418 predicate (UseSSE>=2);
7419 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7420 ins_cost(200);
7421 format %{ "Jn$cop skip\n\t"
7422 "MOVSD $dst,$src\t# float\n"
7423 "skip:" %}
7424 ins_encode %{
7425 Label skip;
7426 // Invert sense of branch from sense of CMOV
7427 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7428 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7429 __ bind(skip);
7430 %}
7431 ins_pipe( pipe_slow );
7432 %}
7433
7434 // unsigned version
7435 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7436 predicate (UseSSE>=1);
7437 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7438 ins_cost(200);
7439 format %{ "Jn$cop skip\n\t"
7440 "MOVSS $dst,$src\t# float\n"
7441 "skip:" %}
7442 ins_encode %{
7443 Label skip;
7444 // Invert sense of branch from sense of CMOV
7445 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7446 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7447 __ bind(skip);
7448 %}
7449 ins_pipe( pipe_slow );
7450 %}
7451
7452 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7453 predicate (UseSSE>=1);
7454 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7455 ins_cost(200);
7456 expand %{
7457 fcmovF_regU(cop, cr, dst, src);
7458 %}
7459 %}
7460
7461 // unsigned version
7462 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7463 predicate (UseSSE>=2);
7464 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7465 ins_cost(200);
7466 format %{ "Jn$cop skip\n\t"
7467 "MOVSD $dst,$src\t# float\n"
7468 "skip:" %}
7469 ins_encode %{
7470 Label skip;
7471 // Invert sense of branch from sense of CMOV
7472 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7473 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7474 __ bind(skip);
7475 %}
7476 ins_pipe( pipe_slow );
7477 %}
7478
7479 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7480 predicate (UseSSE>=2);
7481 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7482 ins_cost(200);
7483 expand %{
7484 fcmovD_regU(cop, cr, dst, src);
7485 %}
7486 %}
7487
7488 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7489 predicate(VM_Version::supports_cmov() );
7490 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7491 ins_cost(200);
7492 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7493 "CMOV$cop $dst.hi,$src.hi" %}
7494 opcode(0x0F,0x40);
7495 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7496 ins_pipe( pipe_cmov_reg_long );
7497 %}
7498
7499 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7500 predicate(VM_Version::supports_cmov() );
7501 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7502 ins_cost(200);
7503 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7504 "CMOV$cop $dst.hi,$src.hi" %}
7505 opcode(0x0F,0x40);
7506 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7507 ins_pipe( pipe_cmov_reg_long );
7508 %}
7509
7510 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7511 predicate(VM_Version::supports_cmov() );
7512 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7513 ins_cost(200);
7514 expand %{
7515 cmovL_regU(cop, cr, dst, src);
7516 %}
7517 %}
7518
7519 //----------Arithmetic Instructions--------------------------------------------
7520 //----------Addition Instructions----------------------------------------------
7521
7522 instruct addExactI_rReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7523 %{
7524 match(AddExactI dst src);
7525 effect(DEF cr);
7526
7527 format %{ "ADD $dst, $src\t# addExact int" %}
7528 ins_encode %{
7529 __ addl($dst$$Register, $src$$Register);
7530 %}
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 instruct addExactI_rReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7535 %{
7536 match(AddExactI dst src);
7537 effect(DEF cr);
7538
7539 format %{ "ADD $dst, $src\t# addExact int" %}
7540 ins_encode %{
7541 __ addl($dst$$Register, $src$$constant);
7542 %}
7543 ins_pipe(ialu_reg_reg);
7544 %}
7545
7546 // Integer Addition Instructions
7547 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7548 match(Set dst (AddI dst src));
7549 effect(KILL cr);
7550
7551 size(2);
7552 format %{ "ADD $dst,$src" %}
7553 opcode(0x03);
7554 ins_encode( OpcP, RegReg( dst, src) );
7555 ins_pipe( ialu_reg_reg );
7556 %}
7557
7558 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7559 match(Set dst (AddI dst src));
7560 effect(KILL cr);
7561
7562 format %{ "ADD $dst,$src" %}
7563 opcode(0x81, 0x00); /* /0 id */
7564 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7565 ins_pipe( ialu_reg );
7566 %}
7567
7568 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7569 predicate(UseIncDec);
7570 match(Set dst (AddI dst src));
7571 effect(KILL cr);
7572
7573 size(1);
7574 format %{ "INC $dst" %}
7575 opcode(0x40); /* */
7576 ins_encode( Opc_plus( primary, dst ) );
7577 ins_pipe( ialu_reg );
7578 %}
7579
7580 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7581 match(Set dst (AddI src0 src1));
7582 ins_cost(110);
7583
7584 format %{ "LEA $dst,[$src0 + $src1]" %}
7585 opcode(0x8D); /* 0x8D /r */
7586 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7587 ins_pipe( ialu_reg_reg );
7588 %}
7589
7590 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7591 match(Set dst (AddP src0 src1));
7592 ins_cost(110);
7593
7594 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7595 opcode(0x8D); /* 0x8D /r */
7596 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7597 ins_pipe( ialu_reg_reg );
7598 %}
7599
7600 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7601 predicate(UseIncDec);
7602 match(Set dst (AddI dst src));
7603 effect(KILL cr);
7604
7605 size(1);
7606 format %{ "DEC $dst" %}
7607 opcode(0x48); /* */
7608 ins_encode( Opc_plus( primary, dst ) );
7609 ins_pipe( ialu_reg );
7610 %}
7611
7612 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7613 match(Set dst (AddP dst src));
7614 effect(KILL cr);
7615
7616 size(2);
7617 format %{ "ADD $dst,$src" %}
7618 opcode(0x03);
7619 ins_encode( OpcP, RegReg( dst, src) );
7620 ins_pipe( ialu_reg_reg );
7621 %}
7622
7623 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7624 match(Set dst (AddP dst src));
7625 effect(KILL cr);
7626
7627 format %{ "ADD $dst,$src" %}
7628 opcode(0x81,0x00); /* Opcode 81 /0 id */
7629 // ins_encode( RegImm( dst, src) );
7630 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7631 ins_pipe( ialu_reg );
7632 %}
7633
7634 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7635 match(Set dst (AddI dst (LoadI src)));
7636 effect(KILL cr);
7637
7638 ins_cost(125);
7639 format %{ "ADD $dst,$src" %}
7640 opcode(0x03);
7641 ins_encode( OpcP, RegMem( dst, src) );
7642 ins_pipe( ialu_reg_mem );
7643 %}
7644
7645 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7646 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7647 effect(KILL cr);
7648
7649 ins_cost(150);
7650 format %{ "ADD $dst,$src" %}
7651 opcode(0x01); /* Opcode 01 /r */
7652 ins_encode( OpcP, RegMem( src, dst ) );
7653 ins_pipe( ialu_mem_reg );
7654 %}
7655
7656 // Add Memory with Immediate
7657 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7658 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7659 effect(KILL cr);
7660
7661 ins_cost(125);
7662 format %{ "ADD $dst,$src" %}
7663 opcode(0x81); /* Opcode 81 /0 id */
7664 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7665 ins_pipe( ialu_mem_imm );
7666 %}
7667
7668 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7669 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7670 effect(KILL cr);
7671
7672 ins_cost(125);
7673 format %{ "INC $dst" %}
7674 opcode(0xFF); /* Opcode FF /0 */
7675 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7676 ins_pipe( ialu_mem_imm );
7677 %}
7678
7679 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7680 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7681 effect(KILL cr);
7682
7683 ins_cost(125);
7684 format %{ "DEC $dst" %}
7685 opcode(0xFF); /* Opcode FF /1 */
7686 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7687 ins_pipe( ialu_mem_imm );
7688 %}
7689
7690
7691 instruct checkCastPP( eRegP dst ) %{
7692 match(Set dst (CheckCastPP dst));
7693
7694 size(0);
7695 format %{ "#checkcastPP of $dst" %}
7696 ins_encode( /*empty encoding*/ );
7697 ins_pipe( empty );
7698 %}
7699
7700 instruct castPP( eRegP dst ) %{
7701 match(Set dst (CastPP dst));
7702 format %{ "#castPP of $dst" %}
7703 ins_encode( /*empty encoding*/ );
7704 ins_pipe( empty );
7705 %}
7706
7707 instruct castII( rRegI dst ) %{
7708 match(Set dst (CastII dst));
7709 format %{ "#castII of $dst" %}
7710 ins_encode( /*empty encoding*/ );
7711 ins_cost(0);
7712 ins_pipe( empty );
7713 %}
7714
7715
7716 // Load-locked - same as a regular pointer load when used with compare-swap
7717 instruct loadPLocked(eRegP dst, memory mem) %{
7718 match(Set dst (LoadPLocked mem));
7719
7720 ins_cost(125);
7721 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7722 opcode(0x8B);
7723 ins_encode( OpcP, RegMem(dst,mem));
7724 ins_pipe( ialu_reg_mem );
7725 %}
7726
7727 // Conditional-store of the updated heap-top.
7728 // Used during allocation of the shared heap.
7729 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7730 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7731 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7732 // EAX is killed if there is contention, but then it's also unused.
7733 // In the common case of no contention, EAX holds the new oop address.
7734 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7735 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7736 ins_pipe( pipe_cmpxchg );
7737 %}
7738
7739 // Conditional-store of an int value.
7740 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7741 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7742 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7743 effect(KILL oldval);
7744 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7745 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7746 ins_pipe( pipe_cmpxchg );
7747 %}
7748
7749 // Conditional-store of a long value.
7750 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7751 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7752 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7753 effect(KILL oldval);
7754 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7755 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7756 "XCHG EBX,ECX"
7757 %}
7758 ins_encode %{
7759 // Note: we need to swap rbx, and rcx before and after the
7760 // cmpxchg8 instruction because the instruction uses
7761 // rcx as the high order word of the new value to store but
7762 // our register encoding uses rbx.
7763 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7764 if( os::is_MP() )
7765 __ lock();
7766 __ cmpxchg8($mem$$Address);
7767 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7768 %}
7769 ins_pipe( pipe_cmpxchg );
7770 %}
7771
7772 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7773
7774 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7775 predicate(VM_Version::supports_cx8());
7776 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7777 effect(KILL cr, KILL oldval);
7778 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7779 "MOV $res,0\n\t"
7780 "JNE,s fail\n\t"
7781 "MOV $res,1\n"
7782 "fail:" %}
7783 ins_encode( enc_cmpxchg8(mem_ptr),
7784 enc_flags_ne_to_boolean(res) );
7785 ins_pipe( pipe_cmpxchg );
7786 %}
7787
7788 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7789 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7790 effect(KILL cr, KILL oldval);
7791 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7792 "MOV $res,0\n\t"
7793 "JNE,s fail\n\t"
7794 "MOV $res,1\n"
7795 "fail:" %}
7796 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7797 ins_pipe( pipe_cmpxchg );
7798 %}
7799
7800 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7801 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7802 effect(KILL cr, KILL oldval);
7803 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7804 "MOV $res,0\n\t"
7805 "JNE,s fail\n\t"
7806 "MOV $res,1\n"
7807 "fail:" %}
7808 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7809 ins_pipe( pipe_cmpxchg );
7810 %}
7811
7812 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7813 predicate(n->as_LoadStore()->result_not_used());
7814 match(Set dummy (GetAndAddI mem add));
7815 effect(KILL cr);
7816 format %{ "ADDL [$mem],$add" %}
7817 ins_encode %{
7818 if (os::is_MP()) { __ lock(); }
7819 __ addl($mem$$Address, $add$$constant);
7820 %}
7821 ins_pipe( pipe_cmpxchg );
7822 %}
7823
7824 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7825 match(Set newval (GetAndAddI mem newval));
7826 effect(KILL cr);
7827 format %{ "XADDL [$mem],$newval" %}
7828 ins_encode %{
7829 if (os::is_MP()) { __ lock(); }
7830 __ xaddl($mem$$Address, $newval$$Register);
7831 %}
7832 ins_pipe( pipe_cmpxchg );
7833 %}
7834
7835 instruct xchgI( memory mem, rRegI newval) %{
7836 match(Set newval (GetAndSetI mem newval));
7837 format %{ "XCHGL $newval,[$mem]" %}
7838 ins_encode %{
7839 __ xchgl($newval$$Register, $mem$$Address);
7840 %}
7841 ins_pipe( pipe_cmpxchg );
7842 %}
7843
7844 instruct xchgP( memory mem, pRegP newval) %{
7845 match(Set newval (GetAndSetP mem newval));
7846 format %{ "XCHGL $newval,[$mem]" %}
7847 ins_encode %{
7848 __ xchgl($newval$$Register, $mem$$Address);
7849 %}
7850 ins_pipe( pipe_cmpxchg );
7851 %}
7852
7853 //----------Subtraction Instructions-------------------------------------------
7854 // Integer Subtraction Instructions
7855 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7856 match(Set dst (SubI dst src));
7857 effect(KILL cr);
7858
7859 size(2);
7860 format %{ "SUB $dst,$src" %}
7861 opcode(0x2B);
7862 ins_encode( OpcP, RegReg( dst, src) );
7863 ins_pipe( ialu_reg_reg );
7864 %}
7865
7866 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7867 match(Set dst (SubI dst src));
7868 effect(KILL cr);
7869
7870 format %{ "SUB $dst,$src" %}
7871 opcode(0x81,0x05); /* Opcode 81 /5 */
7872 // ins_encode( RegImm( dst, src) );
7873 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7874 ins_pipe( ialu_reg );
7875 %}
7876
7877 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7878 match(Set dst (SubI dst (LoadI src)));
7879 effect(KILL cr);
7880
7881 ins_cost(125);
7882 format %{ "SUB $dst,$src" %}
7883 opcode(0x2B);
7884 ins_encode( OpcP, RegMem( dst, src) );
7885 ins_pipe( ialu_reg_mem );
7886 %}
7887
7888 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7889 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7890 effect(KILL cr);
7891
7892 ins_cost(150);
7893 format %{ "SUB $dst,$src" %}
7894 opcode(0x29); /* Opcode 29 /r */
7895 ins_encode( OpcP, RegMem( src, dst ) );
7896 ins_pipe( ialu_mem_reg );
7897 %}
7898
7899 // Subtract from a pointer
7900 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7901 match(Set dst (AddP dst (SubI zero src)));
7902 effect(KILL cr);
7903
7904 size(2);
7905 format %{ "SUB $dst,$src" %}
7906 opcode(0x2B);
7907 ins_encode( OpcP, RegReg( dst, src) );
7908 ins_pipe( ialu_reg_reg );
7909 %}
7910
7911 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7912 match(Set dst (SubI zero dst));
7913 effect(KILL cr);
7914
7915 size(2);
7916 format %{ "NEG $dst" %}
7917 opcode(0xF7,0x03); // Opcode F7 /3
7918 ins_encode( OpcP, RegOpc( dst ) );
7919 ins_pipe( ialu_reg );
7920 %}
7921
7922
7923 //----------Multiplication/Division Instructions-------------------------------
7924 // Integer Multiplication Instructions
7925 // Multiply Register
7926 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7927 match(Set dst (MulI dst src));
7928 effect(KILL cr);
7929
7930 size(3);
7931 ins_cost(300);
7932 format %{ "IMUL $dst,$src" %}
7933 opcode(0xAF, 0x0F);
7934 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7935 ins_pipe( ialu_reg_reg_alu0 );
7936 %}
7937
7938 // Multiply 32-bit Immediate
7939 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7940 match(Set dst (MulI src imm));
7941 effect(KILL cr);
7942
7943 ins_cost(300);
7944 format %{ "IMUL $dst,$src,$imm" %}
7945 opcode(0x69); /* 69 /r id */
7946 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7947 ins_pipe( ialu_reg_reg_alu0 );
7948 %}
7949
7950 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7951 match(Set dst src);
7952 effect(KILL cr);
7953
7954 // Note that this is artificially increased to make it more expensive than loadConL
7955 ins_cost(250);
7956 format %{ "MOV EAX,$src\t// low word only" %}
7957 opcode(0xB8);
7958 ins_encode( LdImmL_Lo(dst, src) );
7959 ins_pipe( ialu_reg_fat );
7960 %}
7961
7962 // Multiply by 32-bit Immediate, taking the shifted high order results
7963 // (special case for shift by 32)
7964 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7965 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7966 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7967 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7968 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7969 effect(USE src1, KILL cr);
7970
7971 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7972 ins_cost(0*100 + 1*400 - 150);
7973 format %{ "IMUL EDX:EAX,$src1" %}
7974 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7975 ins_pipe( pipe_slow );
7976 %}
7977
7978 // Multiply by 32-bit Immediate, taking the shifted high order results
7979 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7980 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7981 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7982 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7983 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7984 effect(USE src1, KILL cr);
7985
7986 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7987 ins_cost(1*100 + 1*400 - 150);
7988 format %{ "IMUL EDX:EAX,$src1\n\t"
7989 "SAR EDX,$cnt-32" %}
7990 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7991 ins_pipe( pipe_slow );
7992 %}
7993
7994 // Multiply Memory 32-bit Immediate
7995 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7996 match(Set dst (MulI (LoadI src) imm));
7997 effect(KILL cr);
7998
7999 ins_cost(300);
8000 format %{ "IMUL $dst,$src,$imm" %}
8001 opcode(0x69); /* 69 /r id */
8002 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8003 ins_pipe( ialu_reg_mem_alu0 );
8004 %}
8005
8006 // Multiply Memory
8007 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8008 match(Set dst (MulI dst (LoadI src)));
8009 effect(KILL cr);
8010
8011 ins_cost(350);
8012 format %{ "IMUL $dst,$src" %}
8013 opcode(0xAF, 0x0F);
8014 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8015 ins_pipe( ialu_reg_mem_alu0 );
8016 %}
8017
8018 // Multiply Register Int to Long
8019 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8020 // Basic Idea: long = (long)int * (long)int
8021 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8022 effect(DEF dst, USE src, USE src1, KILL flags);
8023
8024 ins_cost(300);
8025 format %{ "IMUL $dst,$src1" %}
8026
8027 ins_encode( long_int_multiply( dst, src1 ) );
8028 ins_pipe( ialu_reg_reg_alu0 );
8029 %}
8030
8031 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8032 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8033 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8034 effect(KILL flags);
8035
8036 ins_cost(300);
8037 format %{ "MUL $dst,$src1" %}
8038
8039 ins_encode( long_uint_multiply(dst, src1) );
8040 ins_pipe( ialu_reg_reg_alu0 );
8041 %}
8042
8043 // Multiply Register Long
8044 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8045 match(Set dst (MulL dst src));
8046 effect(KILL cr, TEMP tmp);
8047 ins_cost(4*100+3*400);
8048 // Basic idea: lo(result) = lo(x_lo * y_lo)
8049 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8050 format %{ "MOV $tmp,$src.lo\n\t"
8051 "IMUL $tmp,EDX\n\t"
8052 "MOV EDX,$src.hi\n\t"
8053 "IMUL EDX,EAX\n\t"
8054 "ADD $tmp,EDX\n\t"
8055 "MUL EDX:EAX,$src.lo\n\t"
8056 "ADD EDX,$tmp" %}
8057 ins_encode( long_multiply( dst, src, tmp ) );
8058 ins_pipe( pipe_slow );
8059 %}
8060
8061 // Multiply Register Long where the left operand's high 32 bits are zero
8062 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8063 predicate(is_operand_hi32_zero(n->in(1)));
8064 match(Set dst (MulL dst src));
8065 effect(KILL cr, TEMP tmp);
8066 ins_cost(2*100+2*400);
8067 // Basic idea: lo(result) = lo(x_lo * y_lo)
8068 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8069 format %{ "MOV $tmp,$src.hi\n\t"
8070 "IMUL $tmp,EAX\n\t"
8071 "MUL EDX:EAX,$src.lo\n\t"
8072 "ADD EDX,$tmp" %}
8073 ins_encode %{
8074 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8075 __ imull($tmp$$Register, rax);
8076 __ mull($src$$Register);
8077 __ addl(rdx, $tmp$$Register);
8078 %}
8079 ins_pipe( pipe_slow );
8080 %}
8081
8082 // Multiply Register Long where the right operand's high 32 bits are zero
8083 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8084 predicate(is_operand_hi32_zero(n->in(2)));
8085 match(Set dst (MulL dst src));
8086 effect(KILL cr, TEMP tmp);
8087 ins_cost(2*100+2*400);
8088 // Basic idea: lo(result) = lo(x_lo * y_lo)
8089 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8090 format %{ "MOV $tmp,$src.lo\n\t"
8091 "IMUL $tmp,EDX\n\t"
8092 "MUL EDX:EAX,$src.lo\n\t"
8093 "ADD EDX,$tmp" %}
8094 ins_encode %{
8095 __ movl($tmp$$Register, $src$$Register);
8096 __ imull($tmp$$Register, rdx);
8097 __ mull($src$$Register);
8098 __ addl(rdx, $tmp$$Register);
8099 %}
8100 ins_pipe( pipe_slow );
8101 %}
8102
8103 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8104 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8105 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8106 match(Set dst (MulL dst src));
8107 effect(KILL cr);
8108 ins_cost(1*400);
8109 // Basic idea: lo(result) = lo(x_lo * y_lo)
8110 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8111 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8112 ins_encode %{
8113 __ mull($src$$Register);
8114 %}
8115 ins_pipe( pipe_slow );
8116 %}
8117
8118 // Multiply Register Long by small constant
8119 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8120 match(Set dst (MulL dst src));
8121 effect(KILL cr, TEMP tmp);
8122 ins_cost(2*100+2*400);
8123 size(12);
8124 // Basic idea: lo(result) = lo(src * EAX)
8125 // hi(result) = hi(src * EAX) + lo(src * EDX)
8126 format %{ "IMUL $tmp,EDX,$src\n\t"
8127 "MOV EDX,$src\n\t"
8128 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8129 "ADD EDX,$tmp" %}
8130 ins_encode( long_multiply_con( dst, src, tmp ) );
8131 ins_pipe( pipe_slow );
8132 %}
8133
8134 // Integer DIV with Register
8135 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8136 match(Set rax (DivI rax div));
8137 effect(KILL rdx, KILL cr);
8138 size(26);
8139 ins_cost(30*100+10*100);
8140 format %{ "CMP EAX,0x80000000\n\t"
8141 "JNE,s normal\n\t"
8142 "XOR EDX,EDX\n\t"
8143 "CMP ECX,-1\n\t"
8144 "JE,s done\n"
8145 "normal: CDQ\n\t"
8146 "IDIV $div\n\t"
8147 "done:" %}
8148 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8149 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8150 ins_pipe( ialu_reg_reg_alu0 );
8151 %}
8152
8153 // Divide Register Long
8154 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8155 match(Set dst (DivL src1 src2));
8156 effect( KILL cr, KILL cx, KILL bx );
8157 ins_cost(10000);
8158 format %{ "PUSH $src1.hi\n\t"
8159 "PUSH $src1.lo\n\t"
8160 "PUSH $src2.hi\n\t"
8161 "PUSH $src2.lo\n\t"
8162 "CALL SharedRuntime::ldiv\n\t"
8163 "ADD ESP,16" %}
8164 ins_encode( long_div(src1,src2) );
8165 ins_pipe( pipe_slow );
8166 %}
8167
8168 // Integer DIVMOD with Register, both quotient and mod results
8169 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8170 match(DivModI rax div);
8171 effect(KILL cr);
8172 size(26);
8173 ins_cost(30*100+10*100);
8174 format %{ "CMP EAX,0x80000000\n\t"
8175 "JNE,s normal\n\t"
8176 "XOR EDX,EDX\n\t"
8177 "CMP ECX,-1\n\t"
8178 "JE,s done\n"
8179 "normal: CDQ\n\t"
8180 "IDIV $div\n\t"
8181 "done:" %}
8182 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8183 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8184 ins_pipe( pipe_slow );
8185 %}
8186
8187 // Integer MOD with Register
8188 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8189 match(Set rdx (ModI rax div));
8190 effect(KILL rax, KILL cr);
8191
8192 size(26);
8193 ins_cost(300);
8194 format %{ "CDQ\n\t"
8195 "IDIV $div" %}
8196 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8197 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8198 ins_pipe( ialu_reg_reg_alu0 );
8199 %}
8200
8201 // Remainder Register Long
8202 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8203 match(Set dst (ModL src1 src2));
8204 effect( KILL cr, KILL cx, KILL bx );
8205 ins_cost(10000);
8206 format %{ "PUSH $src1.hi\n\t"
8207 "PUSH $src1.lo\n\t"
8208 "PUSH $src2.hi\n\t"
8209 "PUSH $src2.lo\n\t"
8210 "CALL SharedRuntime::lrem\n\t"
8211 "ADD ESP,16" %}
8212 ins_encode( long_mod(src1,src2) );
8213 ins_pipe( pipe_slow );
8214 %}
8215
8216 // Divide Register Long (no special case since divisor != -1)
8217 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8218 match(Set dst (DivL dst imm));
8219 effect( TEMP tmp, TEMP tmp2, KILL cr );
8220 ins_cost(1000);
8221 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8222 "XOR $tmp2,$tmp2\n\t"
8223 "CMP $tmp,EDX\n\t"
8224 "JA,s fast\n\t"
8225 "MOV $tmp2,EAX\n\t"
8226 "MOV EAX,EDX\n\t"
8227 "MOV EDX,0\n\t"
8228 "JLE,s pos\n\t"
8229 "LNEG EAX : $tmp2\n\t"
8230 "DIV $tmp # unsigned division\n\t"
8231 "XCHG EAX,$tmp2\n\t"
8232 "DIV $tmp\n\t"
8233 "LNEG $tmp2 : EAX\n\t"
8234 "JMP,s done\n"
8235 "pos:\n\t"
8236 "DIV $tmp\n\t"
8237 "XCHG EAX,$tmp2\n"
8238 "fast:\n\t"
8239 "DIV $tmp\n"
8240 "done:\n\t"
8241 "MOV EDX,$tmp2\n\t"
8242 "NEG EDX:EAX # if $imm < 0" %}
8243 ins_encode %{
8244 int con = (int)$imm$$constant;
8245 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8246 int pcon = (con > 0) ? con : -con;
8247 Label Lfast, Lpos, Ldone;
8248
8249 __ movl($tmp$$Register, pcon);
8250 __ xorl($tmp2$$Register,$tmp2$$Register);
8251 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8252 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8253
8254 __ movl($tmp2$$Register, $dst$$Register); // save
8255 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8256 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8257 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8258
8259 // Negative dividend.
8260 // convert value to positive to use unsigned division
8261 __ lneg($dst$$Register, $tmp2$$Register);
8262 __ divl($tmp$$Register);
8263 __ xchgl($dst$$Register, $tmp2$$Register);
8264 __ divl($tmp$$Register);
8265 // revert result back to negative
8266 __ lneg($tmp2$$Register, $dst$$Register);
8267 __ jmpb(Ldone);
8268
8269 __ bind(Lpos);
8270 __ divl($tmp$$Register); // Use unsigned division
8271 __ xchgl($dst$$Register, $tmp2$$Register);
8272 // Fallthrow for final divide, tmp2 has 32 bit hi result
8273
8274 __ bind(Lfast);
8275 // fast path: src is positive
8276 __ divl($tmp$$Register); // Use unsigned division
8277
8278 __ bind(Ldone);
8279 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8280 if (con < 0) {
8281 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8282 }
8283 %}
8284 ins_pipe( pipe_slow );
8285 %}
8286
8287 // Remainder Register Long (remainder fit into 32 bits)
8288 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8289 match(Set dst (ModL dst imm));
8290 effect( TEMP tmp, TEMP tmp2, KILL cr );
8291 ins_cost(1000);
8292 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8293 "CMP $tmp,EDX\n\t"
8294 "JA,s fast\n\t"
8295 "MOV $tmp2,EAX\n\t"
8296 "MOV EAX,EDX\n\t"
8297 "MOV EDX,0\n\t"
8298 "JLE,s pos\n\t"
8299 "LNEG EAX : $tmp2\n\t"
8300 "DIV $tmp # unsigned division\n\t"
8301 "MOV EAX,$tmp2\n\t"
8302 "DIV $tmp\n\t"
8303 "NEG EDX\n\t"
8304 "JMP,s done\n"
8305 "pos:\n\t"
8306 "DIV $tmp\n\t"
8307 "MOV EAX,$tmp2\n"
8308 "fast:\n\t"
8309 "DIV $tmp\n"
8310 "done:\n\t"
8311 "MOV EAX,EDX\n\t"
8312 "SAR EDX,31\n\t" %}
8313 ins_encode %{
8314 int con = (int)$imm$$constant;
8315 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8316 int pcon = (con > 0) ? con : -con;
8317 Label Lfast, Lpos, Ldone;
8318
8319 __ movl($tmp$$Register, pcon);
8320 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8321 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8322
8323 __ movl($tmp2$$Register, $dst$$Register); // save
8324 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8325 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8326 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8327
8328 // Negative dividend.
8329 // convert value to positive to use unsigned division
8330 __ lneg($dst$$Register, $tmp2$$Register);
8331 __ divl($tmp$$Register);
8332 __ movl($dst$$Register, $tmp2$$Register);
8333 __ divl($tmp$$Register);
8334 // revert remainder back to negative
8335 __ negl(HIGH_FROM_LOW($dst$$Register));
8336 __ jmpb(Ldone);
8337
8338 __ bind(Lpos);
8339 __ divl($tmp$$Register);
8340 __ movl($dst$$Register, $tmp2$$Register);
8341
8342 __ bind(Lfast);
8343 // fast path: src is positive
8344 __ divl($tmp$$Register);
8345
8346 __ bind(Ldone);
8347 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8348 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8349
8350 %}
8351 ins_pipe( pipe_slow );
8352 %}
8353
8354 // Integer Shift Instructions
8355 // Shift Left by one
8356 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8357 match(Set dst (LShiftI dst shift));
8358 effect(KILL cr);
8359
8360 size(2);
8361 format %{ "SHL $dst,$shift" %}
8362 opcode(0xD1, 0x4); /* D1 /4 */
8363 ins_encode( OpcP, RegOpc( dst ) );
8364 ins_pipe( ialu_reg );
8365 %}
8366
8367 // Shift Left by 8-bit immediate
8368 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8369 match(Set dst (LShiftI dst shift));
8370 effect(KILL cr);
8371
8372 size(3);
8373 format %{ "SHL $dst,$shift" %}
8374 opcode(0xC1, 0x4); /* C1 /4 ib */
8375 ins_encode( RegOpcImm( dst, shift) );
8376 ins_pipe( ialu_reg );
8377 %}
8378
8379 // Shift Left by variable
8380 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8381 match(Set dst (LShiftI dst shift));
8382 effect(KILL cr);
8383
8384 size(2);
8385 format %{ "SHL $dst,$shift" %}
8386 opcode(0xD3, 0x4); /* D3 /4 */
8387 ins_encode( OpcP, RegOpc( dst ) );
8388 ins_pipe( ialu_reg_reg );
8389 %}
8390
8391 // Arithmetic shift right by one
8392 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8393 match(Set dst (RShiftI dst shift));
8394 effect(KILL cr);
8395
8396 size(2);
8397 format %{ "SAR $dst,$shift" %}
8398 opcode(0xD1, 0x7); /* D1 /7 */
8399 ins_encode( OpcP, RegOpc( dst ) );
8400 ins_pipe( ialu_reg );
8401 %}
8402
8403 // Arithmetic shift right by one
8404 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8405 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8406 effect(KILL cr);
8407 format %{ "SAR $dst,$shift" %}
8408 opcode(0xD1, 0x7); /* D1 /7 */
8409 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8410 ins_pipe( ialu_mem_imm );
8411 %}
8412
8413 // Arithmetic Shift Right by 8-bit immediate
8414 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8415 match(Set dst (RShiftI dst shift));
8416 effect(KILL cr);
8417
8418 size(3);
8419 format %{ "SAR $dst,$shift" %}
8420 opcode(0xC1, 0x7); /* C1 /7 ib */
8421 ins_encode( RegOpcImm( dst, shift ) );
8422 ins_pipe( ialu_mem_imm );
8423 %}
8424
8425 // Arithmetic Shift Right by 8-bit immediate
8426 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8427 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8428 effect(KILL cr);
8429
8430 format %{ "SAR $dst,$shift" %}
8431 opcode(0xC1, 0x7); /* C1 /7 ib */
8432 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8433 ins_pipe( ialu_mem_imm );
8434 %}
8435
8436 // Arithmetic Shift Right by variable
8437 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8438 match(Set dst (RShiftI dst shift));
8439 effect(KILL cr);
8440
8441 size(2);
8442 format %{ "SAR $dst,$shift" %}
8443 opcode(0xD3, 0x7); /* D3 /7 */
8444 ins_encode( OpcP, RegOpc( dst ) );
8445 ins_pipe( ialu_reg_reg );
8446 %}
8447
8448 // Logical shift right by one
8449 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8450 match(Set dst (URShiftI dst shift));
8451 effect(KILL cr);
8452
8453 size(2);
8454 format %{ "SHR $dst,$shift" %}
8455 opcode(0xD1, 0x5); /* D1 /5 */
8456 ins_encode( OpcP, RegOpc( dst ) );
8457 ins_pipe( ialu_reg );
8458 %}
8459
8460 // Logical Shift Right by 8-bit immediate
8461 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8462 match(Set dst (URShiftI dst shift));
8463 effect(KILL cr);
8464
8465 size(3);
8466 format %{ "SHR $dst,$shift" %}
8467 opcode(0xC1, 0x5); /* C1 /5 ib */
8468 ins_encode( RegOpcImm( dst, shift) );
8469 ins_pipe( ialu_reg );
8470 %}
8471
8472
8473 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8474 // This idiom is used by the compiler for the i2b bytecode.
8475 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8476 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8477
8478 size(3);
8479 format %{ "MOVSX $dst,$src :8" %}
8480 ins_encode %{
8481 __ movsbl($dst$$Register, $src$$Register);
8482 %}
8483 ins_pipe(ialu_reg_reg);
8484 %}
8485
8486 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8487 // This idiom is used by the compiler the i2s bytecode.
8488 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8489 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8490
8491 size(3);
8492 format %{ "MOVSX $dst,$src :16" %}
8493 ins_encode %{
8494 __ movswl($dst$$Register, $src$$Register);
8495 %}
8496 ins_pipe(ialu_reg_reg);
8497 %}
8498
8499
8500 // Logical Shift Right by variable
8501 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8502 match(Set dst (URShiftI dst shift));
8503 effect(KILL cr);
8504
8505 size(2);
8506 format %{ "SHR $dst,$shift" %}
8507 opcode(0xD3, 0x5); /* D3 /5 */
8508 ins_encode( OpcP, RegOpc( dst ) );
8509 ins_pipe( ialu_reg_reg );
8510 %}
8511
8512
8513 //----------Logical Instructions-----------------------------------------------
8514 //----------Integer Logical Instructions---------------------------------------
8515 // And Instructions
8516 // And Register with Register
8517 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8518 match(Set dst (AndI dst src));
8519 effect(KILL cr);
8520
8521 size(2);
8522 format %{ "AND $dst,$src" %}
8523 opcode(0x23);
8524 ins_encode( OpcP, RegReg( dst, src) );
8525 ins_pipe( ialu_reg_reg );
8526 %}
8527
8528 // And Register with Immediate
8529 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8530 match(Set dst (AndI dst src));
8531 effect(KILL cr);
8532
8533 format %{ "AND $dst,$src" %}
8534 opcode(0x81,0x04); /* Opcode 81 /4 */
8535 // ins_encode( RegImm( dst, src) );
8536 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8537 ins_pipe( ialu_reg );
8538 %}
8539
8540 // And Register with Memory
8541 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8542 match(Set dst (AndI dst (LoadI src)));
8543 effect(KILL cr);
8544
8545 ins_cost(125);
8546 format %{ "AND $dst,$src" %}
8547 opcode(0x23);
8548 ins_encode( OpcP, RegMem( dst, src) );
8549 ins_pipe( ialu_reg_mem );
8550 %}
8551
8552 // And Memory with Register
8553 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8554 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8555 effect(KILL cr);
8556
8557 ins_cost(150);
8558 format %{ "AND $dst,$src" %}
8559 opcode(0x21); /* Opcode 21 /r */
8560 ins_encode( OpcP, RegMem( src, dst ) );
8561 ins_pipe( ialu_mem_reg );
8562 %}
8563
8564 // And Memory with Immediate
8565 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8566 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8567 effect(KILL cr);
8568
8569 ins_cost(125);
8570 format %{ "AND $dst,$src" %}
8571 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8572 // ins_encode( MemImm( dst, src) );
8573 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8574 ins_pipe( ialu_mem_imm );
8575 %}
8576
8577 // Or Instructions
8578 // Or Register with Register
8579 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8580 match(Set dst (OrI dst src));
8581 effect(KILL cr);
8582
8583 size(2);
8584 format %{ "OR $dst,$src" %}
8585 opcode(0x0B);
8586 ins_encode( OpcP, RegReg( dst, src) );
8587 ins_pipe( ialu_reg_reg );
8588 %}
8589
8590 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8591 match(Set dst (OrI dst (CastP2X src)));
8592 effect(KILL cr);
8593
8594 size(2);
8595 format %{ "OR $dst,$src" %}
8596 opcode(0x0B);
8597 ins_encode( OpcP, RegReg( dst, src) );
8598 ins_pipe( ialu_reg_reg );
8599 %}
8600
8601
8602 // Or Register with Immediate
8603 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8604 match(Set dst (OrI dst src));
8605 effect(KILL cr);
8606
8607 format %{ "OR $dst,$src" %}
8608 opcode(0x81,0x01); /* Opcode 81 /1 id */
8609 // ins_encode( RegImm( dst, src) );
8610 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8611 ins_pipe( ialu_reg );
8612 %}
8613
8614 // Or Register with Memory
8615 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8616 match(Set dst (OrI dst (LoadI src)));
8617 effect(KILL cr);
8618
8619 ins_cost(125);
8620 format %{ "OR $dst,$src" %}
8621 opcode(0x0B);
8622 ins_encode( OpcP, RegMem( dst, src) );
8623 ins_pipe( ialu_reg_mem );
8624 %}
8625
8626 // Or Memory with Register
8627 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8628 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8629 effect(KILL cr);
8630
8631 ins_cost(150);
8632 format %{ "OR $dst,$src" %}
8633 opcode(0x09); /* Opcode 09 /r */
8634 ins_encode( OpcP, RegMem( src, dst ) );
8635 ins_pipe( ialu_mem_reg );
8636 %}
8637
8638 // Or Memory with Immediate
8639 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8640 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8641 effect(KILL cr);
8642
8643 ins_cost(125);
8644 format %{ "OR $dst,$src" %}
8645 opcode(0x81,0x1); /* Opcode 81 /1 id */
8646 // ins_encode( MemImm( dst, src) );
8647 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8648 ins_pipe( ialu_mem_imm );
8649 %}
8650
8651 // ROL/ROR
8652 // ROL expand
8653 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8654 effect(USE_DEF dst, USE shift, KILL cr);
8655
8656 format %{ "ROL $dst, $shift" %}
8657 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8658 ins_encode( OpcP, RegOpc( dst ));
8659 ins_pipe( ialu_reg );
8660 %}
8661
8662 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8663 effect(USE_DEF dst, USE shift, KILL cr);
8664
8665 format %{ "ROL $dst, $shift" %}
8666 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8667 ins_encode( RegOpcImm(dst, shift) );
8668 ins_pipe(ialu_reg);
8669 %}
8670
8671 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8672 effect(USE_DEF dst, USE shift, KILL cr);
8673
8674 format %{ "ROL $dst, $shift" %}
8675 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8676 ins_encode(OpcP, RegOpc(dst));
8677 ins_pipe( ialu_reg_reg );
8678 %}
8679 // end of ROL expand
8680
8681 // ROL 32bit by one once
8682 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8683 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8684
8685 expand %{
8686 rolI_eReg_imm1(dst, lshift, cr);
8687 %}
8688 %}
8689
8690 // ROL 32bit var by imm8 once
8691 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8692 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8693 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8694
8695 expand %{
8696 rolI_eReg_imm8(dst, lshift, cr);
8697 %}
8698 %}
8699
8700 // ROL 32bit var by var once
8701 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8702 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8703
8704 expand %{
8705 rolI_eReg_CL(dst, shift, cr);
8706 %}
8707 %}
8708
8709 // ROL 32bit var by var once
8710 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8711 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8712
8713 expand %{
8714 rolI_eReg_CL(dst, shift, cr);
8715 %}
8716 %}
8717
8718 // ROR expand
8719 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8720 effect(USE_DEF dst, USE shift, KILL cr);
8721
8722 format %{ "ROR $dst, $shift" %}
8723 opcode(0xD1,0x1); /* Opcode D1 /1 */
8724 ins_encode( OpcP, RegOpc( dst ) );
8725 ins_pipe( ialu_reg );
8726 %}
8727
8728 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8729 effect (USE_DEF dst, USE shift, KILL cr);
8730
8731 format %{ "ROR $dst, $shift" %}
8732 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8733 ins_encode( RegOpcImm(dst, shift) );
8734 ins_pipe( ialu_reg );
8735 %}
8736
8737 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8738 effect(USE_DEF dst, USE shift, KILL cr);
8739
8740 format %{ "ROR $dst, $shift" %}
8741 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8742 ins_encode(OpcP, RegOpc(dst));
8743 ins_pipe( ialu_reg_reg );
8744 %}
8745 // end of ROR expand
8746
8747 // ROR right once
8748 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8749 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8750
8751 expand %{
8752 rorI_eReg_imm1(dst, rshift, cr);
8753 %}
8754 %}
8755
8756 // ROR 32bit by immI8 once
8757 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8758 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8759 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8760
8761 expand %{
8762 rorI_eReg_imm8(dst, rshift, cr);
8763 %}
8764 %}
8765
8766 // ROR 32bit var by var once
8767 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8768 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8769
8770 expand %{
8771 rorI_eReg_CL(dst, shift, cr);
8772 %}
8773 %}
8774
8775 // ROR 32bit var by var once
8776 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8777 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8778
8779 expand %{
8780 rorI_eReg_CL(dst, shift, cr);
8781 %}
8782 %}
8783
8784 // Xor Instructions
8785 // Xor Register with Register
8786 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8787 match(Set dst (XorI dst src));
8788 effect(KILL cr);
8789
8790 size(2);
8791 format %{ "XOR $dst,$src" %}
8792 opcode(0x33);
8793 ins_encode( OpcP, RegReg( dst, src) );
8794 ins_pipe( ialu_reg_reg );
8795 %}
8796
8797 // Xor Register with Immediate -1
8798 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8799 match(Set dst (XorI dst imm));
8800
8801 size(2);
8802 format %{ "NOT $dst" %}
8803 ins_encode %{
8804 __ notl($dst$$Register);
8805 %}
8806 ins_pipe( ialu_reg );
8807 %}
8808
8809 // Xor Register with Immediate
8810 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8811 match(Set dst (XorI dst src));
8812 effect(KILL cr);
8813
8814 format %{ "XOR $dst,$src" %}
8815 opcode(0x81,0x06); /* Opcode 81 /6 id */
8816 // ins_encode( RegImm( dst, src) );
8817 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8818 ins_pipe( ialu_reg );
8819 %}
8820
8821 // Xor Register with Memory
8822 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8823 match(Set dst (XorI dst (LoadI src)));
8824 effect(KILL cr);
8825
8826 ins_cost(125);
8827 format %{ "XOR $dst,$src" %}
8828 opcode(0x33);
8829 ins_encode( OpcP, RegMem(dst, src) );
8830 ins_pipe( ialu_reg_mem );
8831 %}
8832
8833 // Xor Memory with Register
8834 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8835 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8836 effect(KILL cr);
8837
8838 ins_cost(150);
8839 format %{ "XOR $dst,$src" %}
8840 opcode(0x31); /* Opcode 31 /r */
8841 ins_encode( OpcP, RegMem( src, dst ) );
8842 ins_pipe( ialu_mem_reg );
8843 %}
8844
8845 // Xor Memory with Immediate
8846 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8847 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8848 effect(KILL cr);
8849
8850 ins_cost(125);
8851 format %{ "XOR $dst,$src" %}
8852 opcode(0x81,0x6); /* Opcode 81 /6 id */
8853 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8854 ins_pipe( ialu_mem_imm );
8855 %}
8856
8857 //----------Convert Int to Boolean---------------------------------------------
8858
8859 instruct movI_nocopy(rRegI dst, rRegI src) %{
8860 effect( DEF dst, USE src );
8861 format %{ "MOV $dst,$src" %}
8862 ins_encode( enc_Copy( dst, src) );
8863 ins_pipe( ialu_reg_reg );
8864 %}
8865
8866 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8867 effect( USE_DEF dst, USE src, KILL cr );
8868
8869 size(4);
8870 format %{ "NEG $dst\n\t"
8871 "ADC $dst,$src" %}
8872 ins_encode( neg_reg(dst),
8873 OpcRegReg(0x13,dst,src) );
8874 ins_pipe( ialu_reg_reg_long );
8875 %}
8876
8877 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8878 match(Set dst (Conv2B src));
8879
8880 expand %{
8881 movI_nocopy(dst,src);
8882 ci2b(dst,src,cr);
8883 %}
8884 %}
8885
8886 instruct movP_nocopy(rRegI dst, eRegP src) %{
8887 effect( DEF dst, USE src );
8888 format %{ "MOV $dst,$src" %}
8889 ins_encode( enc_Copy( dst, src) );
8890 ins_pipe( ialu_reg_reg );
8891 %}
8892
8893 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8894 effect( USE_DEF dst, USE src, KILL cr );
8895 format %{ "NEG $dst\n\t"
8896 "ADC $dst,$src" %}
8897 ins_encode( neg_reg(dst),
8898 OpcRegReg(0x13,dst,src) );
8899 ins_pipe( ialu_reg_reg_long );
8900 %}
8901
8902 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8903 match(Set dst (Conv2B src));
8904
8905 expand %{
8906 movP_nocopy(dst,src);
8907 cp2b(dst,src,cr);
8908 %}
8909 %}
8910
8911 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8912 match(Set dst (CmpLTMask p q));
8913 effect(KILL cr);
8914 ins_cost(400);
8915
8916 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8917 format %{ "XOR $dst,$dst\n\t"
8918 "CMP $p,$q\n\t"
8919 "SETlt $dst\n\t"
8920 "NEG $dst" %}
8921 ins_encode %{
8922 Register Rp = $p$$Register;
8923 Register Rq = $q$$Register;
8924 Register Rd = $dst$$Register;
8925 Label done;
8926 __ xorl(Rd, Rd);
8927 __ cmpl(Rp, Rq);
8928 __ setb(Assembler::less, Rd);
8929 __ negl(Rd);
8930 %}
8931
8932 ins_pipe(pipe_slow);
8933 %}
8934
8935 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8936 match(Set dst (CmpLTMask dst zero));
8937 effect(DEF dst, KILL cr);
8938 ins_cost(100);
8939
8940 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8941 ins_encode %{
8942 __ sarl($dst$$Register, 31);
8943 %}
8944 ins_pipe(ialu_reg);
8945 %}
8946
8947 /* better to save a register than avoid a branch */
8948 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8949 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8950 effect(KILL cr);
8951 ins_cost(400);
8952 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8953 "JGE done\n\t"
8954 "ADD $p,$y\n"
8955 "done: " %}
8956 ins_encode %{
8957 Register Rp = $p$$Register;
8958 Register Rq = $q$$Register;
8959 Register Ry = $y$$Register;
8960 Label done;
8961 __ subl(Rp, Rq);
8962 __ jccb(Assembler::greaterEqual, done);
8963 __ addl(Rp, Ry);
8964 __ bind(done);
8965 %}
8966
8967 ins_pipe(pipe_cmplt);
8968 %}
8969
8970 /* better to save a register than avoid a branch */
8971 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8972 match(Set y (AndI (CmpLTMask p q) y));
8973 effect(KILL cr);
8974
8975 ins_cost(300);
8976
8977 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8978 "JLT done\n\t"
8979 "XORL $y, $y\n"
8980 "done: " %}
8981 ins_encode %{
8982 Register Rp = $p$$Register;
8983 Register Rq = $q$$Register;
8984 Register Ry = $y$$Register;
8985 Label done;
8986 __ cmpl(Rp, Rq);
8987 __ jccb(Assembler::less, done);
8988 __ xorl(Ry, Ry);
8989 __ bind(done);
8990 %}
8991
8992 ins_pipe(pipe_cmplt);
8993 %}
8994
8995 /* If I enable this, I encourage spilling in the inner loop of compress.
8996 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8997 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8998 */
8999
9000 //----------Long Instructions------------------------------------------------
9001 // Add Long Register with Register
9002 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9003 match(Set dst (AddL dst src));
9004 effect(KILL cr);
9005 ins_cost(200);
9006 format %{ "ADD $dst.lo,$src.lo\n\t"
9007 "ADC $dst.hi,$src.hi" %}
9008 opcode(0x03, 0x13);
9009 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9010 ins_pipe( ialu_reg_reg_long );
9011 %}
9012
9013 // Add Long Register with Immediate
9014 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9015 match(Set dst (AddL dst src));
9016 effect(KILL cr);
9017 format %{ "ADD $dst.lo,$src.lo\n\t"
9018 "ADC $dst.hi,$src.hi" %}
9019 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9020 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9021 ins_pipe( ialu_reg_long );
9022 %}
9023
9024 // Add Long Register with Memory
9025 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9026 match(Set dst (AddL dst (LoadL mem)));
9027 effect(KILL cr);
9028 ins_cost(125);
9029 format %{ "ADD $dst.lo,$mem\n\t"
9030 "ADC $dst.hi,$mem+4" %}
9031 opcode(0x03, 0x13);
9032 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9033 ins_pipe( ialu_reg_long_mem );
9034 %}
9035
9036 // Subtract Long Register with Register.
9037 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9038 match(Set dst (SubL dst src));
9039 effect(KILL cr);
9040 ins_cost(200);
9041 format %{ "SUB $dst.lo,$src.lo\n\t"
9042 "SBB $dst.hi,$src.hi" %}
9043 opcode(0x2B, 0x1B);
9044 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9045 ins_pipe( ialu_reg_reg_long );
9046 %}
9047
9048 // Subtract Long Register with Immediate
9049 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9050 match(Set dst (SubL dst src));
9051 effect(KILL cr);
9052 format %{ "SUB $dst.lo,$src.lo\n\t"
9053 "SBB $dst.hi,$src.hi" %}
9054 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9055 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9056 ins_pipe( ialu_reg_long );
9057 %}
9058
9059 // Subtract Long Register with Memory
9060 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9061 match(Set dst (SubL dst (LoadL mem)));
9062 effect(KILL cr);
9063 ins_cost(125);
9064 format %{ "SUB $dst.lo,$mem\n\t"
9065 "SBB $dst.hi,$mem+4" %}
9066 opcode(0x2B, 0x1B);
9067 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9068 ins_pipe( ialu_reg_long_mem );
9069 %}
9070
9071 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9072 match(Set dst (SubL zero dst));
9073 effect(KILL cr);
9074 ins_cost(300);
9075 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9076 ins_encode( neg_long(dst) );
9077 ins_pipe( ialu_reg_reg_long );
9078 %}
9079
9080 // And Long Register with Register
9081 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9082 match(Set dst (AndL dst src));
9083 effect(KILL cr);
9084 format %{ "AND $dst.lo,$src.lo\n\t"
9085 "AND $dst.hi,$src.hi" %}
9086 opcode(0x23,0x23);
9087 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9088 ins_pipe( ialu_reg_reg_long );
9089 %}
9090
9091 // And Long Register with Immediate
9092 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9093 match(Set dst (AndL dst src));
9094 effect(KILL cr);
9095 format %{ "AND $dst.lo,$src.lo\n\t"
9096 "AND $dst.hi,$src.hi" %}
9097 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9098 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9099 ins_pipe( ialu_reg_long );
9100 %}
9101
9102 // And Long Register with Memory
9103 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9104 match(Set dst (AndL dst (LoadL mem)));
9105 effect(KILL cr);
9106 ins_cost(125);
9107 format %{ "AND $dst.lo,$mem\n\t"
9108 "AND $dst.hi,$mem+4" %}
9109 opcode(0x23, 0x23);
9110 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9111 ins_pipe( ialu_reg_long_mem );
9112 %}
9113
9114 // Or Long Register with Register
9115 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9116 match(Set dst (OrL dst src));
9117 effect(KILL cr);
9118 format %{ "OR $dst.lo,$src.lo\n\t"
9119 "OR $dst.hi,$src.hi" %}
9120 opcode(0x0B,0x0B);
9121 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9122 ins_pipe( ialu_reg_reg_long );
9123 %}
9124
9125 // Or Long Register with Immediate
9126 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9127 match(Set dst (OrL dst src));
9128 effect(KILL cr);
9129 format %{ "OR $dst.lo,$src.lo\n\t"
9130 "OR $dst.hi,$src.hi" %}
9131 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9132 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9133 ins_pipe( ialu_reg_long );
9134 %}
9135
9136 // Or Long Register with Memory
9137 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9138 match(Set dst (OrL dst (LoadL mem)));
9139 effect(KILL cr);
9140 ins_cost(125);
9141 format %{ "OR $dst.lo,$mem\n\t"
9142 "OR $dst.hi,$mem+4" %}
9143 opcode(0x0B,0x0B);
9144 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9145 ins_pipe( ialu_reg_long_mem );
9146 %}
9147
9148 // Xor Long Register with Register
9149 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9150 match(Set dst (XorL dst src));
9151 effect(KILL cr);
9152 format %{ "XOR $dst.lo,$src.lo\n\t"
9153 "XOR $dst.hi,$src.hi" %}
9154 opcode(0x33,0x33);
9155 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9156 ins_pipe( ialu_reg_reg_long );
9157 %}
9158
9159 // Xor Long Register with Immediate -1
9160 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9161 match(Set dst (XorL dst imm));
9162 format %{ "NOT $dst.lo\n\t"
9163 "NOT $dst.hi" %}
9164 ins_encode %{
9165 __ notl($dst$$Register);
9166 __ notl(HIGH_FROM_LOW($dst$$Register));
9167 %}
9168 ins_pipe( ialu_reg_long );
9169 %}
9170
9171 // Xor Long Register with Immediate
9172 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9173 match(Set dst (XorL dst src));
9174 effect(KILL cr);
9175 format %{ "XOR $dst.lo,$src.lo\n\t"
9176 "XOR $dst.hi,$src.hi" %}
9177 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9178 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9179 ins_pipe( ialu_reg_long );
9180 %}
9181
9182 // Xor Long Register with Memory
9183 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9184 match(Set dst (XorL dst (LoadL mem)));
9185 effect(KILL cr);
9186 ins_cost(125);
9187 format %{ "XOR $dst.lo,$mem\n\t"
9188 "XOR $dst.hi,$mem+4" %}
9189 opcode(0x33,0x33);
9190 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9191 ins_pipe( ialu_reg_long_mem );
9192 %}
9193
9194 // Shift Left Long by 1
9195 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9196 predicate(UseNewLongLShift);
9197 match(Set dst (LShiftL dst cnt));
9198 effect(KILL cr);
9199 ins_cost(100);
9200 format %{ "ADD $dst.lo,$dst.lo\n\t"
9201 "ADC $dst.hi,$dst.hi" %}
9202 ins_encode %{
9203 __ addl($dst$$Register,$dst$$Register);
9204 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9205 %}
9206 ins_pipe( ialu_reg_long );
9207 %}
9208
9209 // Shift Left Long by 2
9210 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9211 predicate(UseNewLongLShift);
9212 match(Set dst (LShiftL dst cnt));
9213 effect(KILL cr);
9214 ins_cost(100);
9215 format %{ "ADD $dst.lo,$dst.lo\n\t"
9216 "ADC $dst.hi,$dst.hi\n\t"
9217 "ADD $dst.lo,$dst.lo\n\t"
9218 "ADC $dst.hi,$dst.hi" %}
9219 ins_encode %{
9220 __ addl($dst$$Register,$dst$$Register);
9221 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9222 __ addl($dst$$Register,$dst$$Register);
9223 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9224 %}
9225 ins_pipe( ialu_reg_long );
9226 %}
9227
9228 // Shift Left Long by 3
9229 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9230 predicate(UseNewLongLShift);
9231 match(Set dst (LShiftL dst cnt));
9232 effect(KILL cr);
9233 ins_cost(100);
9234 format %{ "ADD $dst.lo,$dst.lo\n\t"
9235 "ADC $dst.hi,$dst.hi\n\t"
9236 "ADD $dst.lo,$dst.lo\n\t"
9237 "ADC $dst.hi,$dst.hi\n\t"
9238 "ADD $dst.lo,$dst.lo\n\t"
9239 "ADC $dst.hi,$dst.hi" %}
9240 ins_encode %{
9241 __ addl($dst$$Register,$dst$$Register);
9242 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9243 __ addl($dst$$Register,$dst$$Register);
9244 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9245 __ addl($dst$$Register,$dst$$Register);
9246 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9247 %}
9248 ins_pipe( ialu_reg_long );
9249 %}
9250
9251 // Shift Left Long by 1-31
9252 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9253 match(Set dst (LShiftL dst cnt));
9254 effect(KILL cr);
9255 ins_cost(200);
9256 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9257 "SHL $dst.lo,$cnt" %}
9258 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9259 ins_encode( move_long_small_shift(dst,cnt) );
9260 ins_pipe( ialu_reg_long );
9261 %}
9262
9263 // Shift Left Long by 32-63
9264 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9265 match(Set dst (LShiftL dst cnt));
9266 effect(KILL cr);
9267 ins_cost(300);
9268 format %{ "MOV $dst.hi,$dst.lo\n"
9269 "\tSHL $dst.hi,$cnt-32\n"
9270 "\tXOR $dst.lo,$dst.lo" %}
9271 opcode(0xC1, 0x4); /* C1 /4 ib */
9272 ins_encode( move_long_big_shift_clr(dst,cnt) );
9273 ins_pipe( ialu_reg_long );
9274 %}
9275
9276 // Shift Left Long by variable
9277 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9278 match(Set dst (LShiftL dst shift));
9279 effect(KILL cr);
9280 ins_cost(500+200);
9281 size(17);
9282 format %{ "TEST $shift,32\n\t"
9283 "JEQ,s small\n\t"
9284 "MOV $dst.hi,$dst.lo\n\t"
9285 "XOR $dst.lo,$dst.lo\n"
9286 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9287 "SHL $dst.lo,$shift" %}
9288 ins_encode( shift_left_long( dst, shift ) );
9289 ins_pipe( pipe_slow );
9290 %}
9291
9292 // Shift Right Long by 1-31
9293 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9294 match(Set dst (URShiftL dst cnt));
9295 effect(KILL cr);
9296 ins_cost(200);
9297 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9298 "SHR $dst.hi,$cnt" %}
9299 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9300 ins_encode( move_long_small_shift(dst,cnt) );
9301 ins_pipe( ialu_reg_long );
9302 %}
9303
9304 // Shift Right Long by 32-63
9305 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9306 match(Set dst (URShiftL dst cnt));
9307 effect(KILL cr);
9308 ins_cost(300);
9309 format %{ "MOV $dst.lo,$dst.hi\n"
9310 "\tSHR $dst.lo,$cnt-32\n"
9311 "\tXOR $dst.hi,$dst.hi" %}
9312 opcode(0xC1, 0x5); /* C1 /5 ib */
9313 ins_encode( move_long_big_shift_clr(dst,cnt) );
9314 ins_pipe( ialu_reg_long );
9315 %}
9316
9317 // Shift Right Long by variable
9318 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9319 match(Set dst (URShiftL dst shift));
9320 effect(KILL cr);
9321 ins_cost(600);
9322 size(17);
9323 format %{ "TEST $shift,32\n\t"
9324 "JEQ,s small\n\t"
9325 "MOV $dst.lo,$dst.hi\n\t"
9326 "XOR $dst.hi,$dst.hi\n"
9327 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9328 "SHR $dst.hi,$shift" %}
9329 ins_encode( shift_right_long( dst, shift ) );
9330 ins_pipe( pipe_slow );
9331 %}
9332
9333 // Shift Right Long by 1-31
9334 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9335 match(Set dst (RShiftL dst cnt));
9336 effect(KILL cr);
9337 ins_cost(200);
9338 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9339 "SAR $dst.hi,$cnt" %}
9340 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9341 ins_encode( move_long_small_shift(dst,cnt) );
9342 ins_pipe( ialu_reg_long );
9343 %}
9344
9345 // Shift Right Long by 32-63
9346 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9347 match(Set dst (RShiftL dst cnt));
9348 effect(KILL cr);
9349 ins_cost(300);
9350 format %{ "MOV $dst.lo,$dst.hi\n"
9351 "\tSAR $dst.lo,$cnt-32\n"
9352 "\tSAR $dst.hi,31" %}
9353 opcode(0xC1, 0x7); /* C1 /7 ib */
9354 ins_encode( move_long_big_shift_sign(dst,cnt) );
9355 ins_pipe( ialu_reg_long );
9356 %}
9357
9358 // Shift Right arithmetic Long by variable
9359 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9360 match(Set dst (RShiftL dst shift));
9361 effect(KILL cr);
9362 ins_cost(600);
9363 size(18);
9364 format %{ "TEST $shift,32\n\t"
9365 "JEQ,s small\n\t"
9366 "MOV $dst.lo,$dst.hi\n\t"
9367 "SAR $dst.hi,31\n"
9368 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9369 "SAR $dst.hi,$shift" %}
9370 ins_encode( shift_right_arith_long( dst, shift ) );
9371 ins_pipe( pipe_slow );
9372 %}
9373
9374
9375 //----------Double Instructions------------------------------------------------
9376 // Double Math
9377
9378 // Compare & branch
9379
9380 // P6 version of float compare, sets condition codes in EFLAGS
9381 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9382 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9383 match(Set cr (CmpD src1 src2));
9384 effect(KILL rax);
9385 ins_cost(150);
9386 format %{ "FLD $src1\n\t"
9387 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9388 "JNP exit\n\t"
9389 "MOV ah,1 // saw a NaN, set CF\n\t"
9390 "SAHF\n"
9391 "exit:\tNOP // avoid branch to branch" %}
9392 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9393 ins_encode( Push_Reg_DPR(src1),
9394 OpcP, RegOpc(src2),
9395 cmpF_P6_fixup );
9396 ins_pipe( pipe_slow );
9397 %}
9398
9399 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9400 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9401 match(Set cr (CmpD src1 src2));
9402 ins_cost(150);
9403 format %{ "FLD $src1\n\t"
9404 "FUCOMIP ST,$src2 // P6 instruction" %}
9405 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9406 ins_encode( Push_Reg_DPR(src1),
9407 OpcP, RegOpc(src2));
9408 ins_pipe( pipe_slow );
9409 %}
9410
9411 // Compare & branch
9412 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9413 predicate(UseSSE<=1);
9414 match(Set cr (CmpD src1 src2));
9415 effect(KILL rax);
9416 ins_cost(200);
9417 format %{ "FLD $src1\n\t"
9418 "FCOMp $src2\n\t"
9419 "FNSTSW AX\n\t"
9420 "TEST AX,0x400\n\t"
9421 "JZ,s flags\n\t"
9422 "MOV AH,1\t# unordered treat as LT\n"
9423 "flags:\tSAHF" %}
9424 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9425 ins_encode( Push_Reg_DPR(src1),
9426 OpcP, RegOpc(src2),
9427 fpu_flags);
9428 ins_pipe( pipe_slow );
9429 %}
9430
9431 // Compare vs zero into -1,0,1
9432 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9433 predicate(UseSSE<=1);
9434 match(Set dst (CmpD3 src1 zero));
9435 effect(KILL cr, KILL rax);
9436 ins_cost(280);
9437 format %{ "FTSTD $dst,$src1" %}
9438 opcode(0xE4, 0xD9);
9439 ins_encode( Push_Reg_DPR(src1),
9440 OpcS, OpcP, PopFPU,
9441 CmpF_Result(dst));
9442 ins_pipe( pipe_slow );
9443 %}
9444
9445 // Compare into -1,0,1
9446 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9447 predicate(UseSSE<=1);
9448 match(Set dst (CmpD3 src1 src2));
9449 effect(KILL cr, KILL rax);
9450 ins_cost(300);
9451 format %{ "FCMPD $dst,$src1,$src2" %}
9452 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9453 ins_encode( Push_Reg_DPR(src1),
9454 OpcP, RegOpc(src2),
9455 CmpF_Result(dst));
9456 ins_pipe( pipe_slow );
9457 %}
9458
9459 // float compare and set condition codes in EFLAGS by XMM regs
9460 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9461 predicate(UseSSE>=2);
9462 match(Set cr (CmpD src1 src2));
9463 ins_cost(145);
9464 format %{ "UCOMISD $src1,$src2\n\t"
9465 "JNP,s exit\n\t"
9466 "PUSHF\t# saw NaN, set CF\n\t"
9467 "AND [rsp], #0xffffff2b\n\t"
9468 "POPF\n"
9469 "exit:" %}
9470 ins_encode %{
9471 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9472 emit_cmpfp_fixup(_masm);
9473 %}
9474 ins_pipe( pipe_slow );
9475 %}
9476
9477 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9478 predicate(UseSSE>=2);
9479 match(Set cr (CmpD src1 src2));
9480 ins_cost(100);
9481 format %{ "UCOMISD $src1,$src2" %}
9482 ins_encode %{
9483 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9484 %}
9485 ins_pipe( pipe_slow );
9486 %}
9487
9488 // float compare and set condition codes in EFLAGS by XMM regs
9489 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9490 predicate(UseSSE>=2);
9491 match(Set cr (CmpD src1 (LoadD src2)));
9492 ins_cost(145);
9493 format %{ "UCOMISD $src1,$src2\n\t"
9494 "JNP,s exit\n\t"
9495 "PUSHF\t# saw NaN, set CF\n\t"
9496 "AND [rsp], #0xffffff2b\n\t"
9497 "POPF\n"
9498 "exit:" %}
9499 ins_encode %{
9500 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9501 emit_cmpfp_fixup(_masm);
9502 %}
9503 ins_pipe( pipe_slow );
9504 %}
9505
9506 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9507 predicate(UseSSE>=2);
9508 match(Set cr (CmpD src1 (LoadD src2)));
9509 ins_cost(100);
9510 format %{ "UCOMISD $src1,$src2" %}
9511 ins_encode %{
9512 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9513 %}
9514 ins_pipe( pipe_slow );
9515 %}
9516
9517 // Compare into -1,0,1 in XMM
9518 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9519 predicate(UseSSE>=2);
9520 match(Set dst (CmpD3 src1 src2));
9521 effect(KILL cr);
9522 ins_cost(255);
9523 format %{ "UCOMISD $src1, $src2\n\t"
9524 "MOV $dst, #-1\n\t"
9525 "JP,s done\n\t"
9526 "JB,s done\n\t"
9527 "SETNE $dst\n\t"
9528 "MOVZB $dst, $dst\n"
9529 "done:" %}
9530 ins_encode %{
9531 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9532 emit_cmpfp3(_masm, $dst$$Register);
9533 %}
9534 ins_pipe( pipe_slow );
9535 %}
9536
9537 // Compare into -1,0,1 in XMM and memory
9538 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9539 predicate(UseSSE>=2);
9540 match(Set dst (CmpD3 src1 (LoadD src2)));
9541 effect(KILL cr);
9542 ins_cost(275);
9543 format %{ "UCOMISD $src1, $src2\n\t"
9544 "MOV $dst, #-1\n\t"
9545 "JP,s done\n\t"
9546 "JB,s done\n\t"
9547 "SETNE $dst\n\t"
9548 "MOVZB $dst, $dst\n"
9549 "done:" %}
9550 ins_encode %{
9551 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9552 emit_cmpfp3(_masm, $dst$$Register);
9553 %}
9554 ins_pipe( pipe_slow );
9555 %}
9556
9557
9558 instruct subDPR_reg(regDPR dst, regDPR src) %{
9559 predicate (UseSSE <=1);
9560 match(Set dst (SubD dst src));
9561
9562 format %{ "FLD $src\n\t"
9563 "DSUBp $dst,ST" %}
9564 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9565 ins_cost(150);
9566 ins_encode( Push_Reg_DPR(src),
9567 OpcP, RegOpc(dst) );
9568 ins_pipe( fpu_reg_reg );
9569 %}
9570
9571 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9572 predicate (UseSSE <=1);
9573 match(Set dst (RoundDouble (SubD src1 src2)));
9574 ins_cost(250);
9575
9576 format %{ "FLD $src2\n\t"
9577 "DSUB ST,$src1\n\t"
9578 "FSTP_D $dst\t# D-round" %}
9579 opcode(0xD8, 0x5);
9580 ins_encode( Push_Reg_DPR(src2),
9581 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9582 ins_pipe( fpu_mem_reg_reg );
9583 %}
9584
9585
9586 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9587 predicate (UseSSE <=1);
9588 match(Set dst (SubD dst (LoadD src)));
9589 ins_cost(150);
9590
9591 format %{ "FLD $src\n\t"
9592 "DSUBp $dst,ST" %}
9593 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9594 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9595 OpcP, RegOpc(dst) );
9596 ins_pipe( fpu_reg_mem );
9597 %}
9598
9599 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9600 predicate (UseSSE<=1);
9601 match(Set dst (AbsD src));
9602 ins_cost(100);
9603 format %{ "FABS" %}
9604 opcode(0xE1, 0xD9);
9605 ins_encode( OpcS, OpcP );
9606 ins_pipe( fpu_reg_reg );
9607 %}
9608
9609 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9610 predicate(UseSSE<=1);
9611 match(Set dst (NegD src));
9612 ins_cost(100);
9613 format %{ "FCHS" %}
9614 opcode(0xE0, 0xD9);
9615 ins_encode( OpcS, OpcP );
9616 ins_pipe( fpu_reg_reg );
9617 %}
9618
9619 instruct addDPR_reg(regDPR dst, regDPR src) %{
9620 predicate(UseSSE<=1);
9621 match(Set dst (AddD dst src));
9622 format %{ "FLD $src\n\t"
9623 "DADD $dst,ST" %}
9624 size(4);
9625 ins_cost(150);
9626 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9627 ins_encode( Push_Reg_DPR(src),
9628 OpcP, RegOpc(dst) );
9629 ins_pipe( fpu_reg_reg );
9630 %}
9631
9632
9633 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9634 predicate(UseSSE<=1);
9635 match(Set dst (RoundDouble (AddD src1 src2)));
9636 ins_cost(250);
9637
9638 format %{ "FLD $src2\n\t"
9639 "DADD ST,$src1\n\t"
9640 "FSTP_D $dst\t# D-round" %}
9641 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9642 ins_encode( Push_Reg_DPR(src2),
9643 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9644 ins_pipe( fpu_mem_reg_reg );
9645 %}
9646
9647
9648 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9649 predicate(UseSSE<=1);
9650 match(Set dst (AddD dst (LoadD src)));
9651 ins_cost(150);
9652
9653 format %{ "FLD $src\n\t"
9654 "DADDp $dst,ST" %}
9655 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9656 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9657 OpcP, RegOpc(dst) );
9658 ins_pipe( fpu_reg_mem );
9659 %}
9660
9661 // add-to-memory
9662 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9663 predicate(UseSSE<=1);
9664 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9665 ins_cost(150);
9666
9667 format %{ "FLD_D $dst\n\t"
9668 "DADD ST,$src\n\t"
9669 "FST_D $dst" %}
9670 opcode(0xDD, 0x0);
9671 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9672 Opcode(0xD8), RegOpc(src),
9673 set_instruction_start,
9674 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9675 ins_pipe( fpu_reg_mem );
9676 %}
9677
9678 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9679 predicate(UseSSE<=1);
9680 match(Set dst (AddD dst con));
9681 ins_cost(125);
9682 format %{ "FLD1\n\t"
9683 "DADDp $dst,ST" %}
9684 ins_encode %{
9685 __ fld1();
9686 __ faddp($dst$$reg);
9687 %}
9688 ins_pipe(fpu_reg);
9689 %}
9690
9691 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9692 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9693 match(Set dst (AddD dst con));
9694 ins_cost(200);
9695 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9696 "DADDp $dst,ST" %}
9697 ins_encode %{
9698 __ fld_d($constantaddress($con));
9699 __ faddp($dst$$reg);
9700 %}
9701 ins_pipe(fpu_reg_mem);
9702 %}
9703
9704 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9705 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9706 match(Set dst (RoundDouble (AddD src con)));
9707 ins_cost(200);
9708 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9709 "DADD ST,$src\n\t"
9710 "FSTP_D $dst\t# D-round" %}
9711 ins_encode %{
9712 __ fld_d($constantaddress($con));
9713 __ fadd($src$$reg);
9714 __ fstp_d(Address(rsp, $dst$$disp));
9715 %}
9716 ins_pipe(fpu_mem_reg_con);
9717 %}
9718
9719 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9720 predicate(UseSSE<=1);
9721 match(Set dst (MulD dst src));
9722 format %{ "FLD $src\n\t"
9723 "DMULp $dst,ST" %}
9724 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9725 ins_cost(150);
9726 ins_encode( Push_Reg_DPR(src),
9727 OpcP, RegOpc(dst) );
9728 ins_pipe( fpu_reg_reg );
9729 %}
9730
9731 // Strict FP instruction biases argument before multiply then
9732 // biases result to avoid double rounding of subnormals.
9733 //
9734 // scale arg1 by multiplying arg1 by 2^(-15360)
9735 // load arg2
9736 // multiply scaled arg1 by arg2
9737 // rescale product by 2^(15360)
9738 //
9739 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9740 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9741 match(Set dst (MulD dst src));
9742 ins_cost(1); // Select this instruction for all strict FP double multiplies
9743
9744 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9745 "DMULp $dst,ST\n\t"
9746 "FLD $src\n\t"
9747 "DMULp $dst,ST\n\t"
9748 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9749 "DMULp $dst,ST\n\t" %}
9750 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9751 ins_encode( strictfp_bias1(dst),
9752 Push_Reg_DPR(src),
9753 OpcP, RegOpc(dst),
9754 strictfp_bias2(dst) );
9755 ins_pipe( fpu_reg_reg );
9756 %}
9757
9758 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9759 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9760 match(Set dst (MulD dst con));
9761 ins_cost(200);
9762 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9763 "DMULp $dst,ST" %}
9764 ins_encode %{
9765 __ fld_d($constantaddress($con));
9766 __ fmulp($dst$$reg);
9767 %}
9768 ins_pipe(fpu_reg_mem);
9769 %}
9770
9771
9772 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9773 predicate( UseSSE<=1 );
9774 match(Set dst (MulD dst (LoadD src)));
9775 ins_cost(200);
9776 format %{ "FLD_D $src\n\t"
9777 "DMULp $dst,ST" %}
9778 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9779 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9780 OpcP, RegOpc(dst) );
9781 ins_pipe( fpu_reg_mem );
9782 %}
9783
9784 //
9785 // Cisc-alternate to reg-reg multiply
9786 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9787 predicate( UseSSE<=1 );
9788 match(Set dst (MulD src (LoadD mem)));
9789 ins_cost(250);
9790 format %{ "FLD_D $mem\n\t"
9791 "DMUL ST,$src\n\t"
9792 "FSTP_D $dst" %}
9793 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9794 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9795 OpcReg_FPR(src),
9796 Pop_Reg_DPR(dst) );
9797 ins_pipe( fpu_reg_reg_mem );
9798 %}
9799
9800
9801 // MACRO3 -- addDPR a mulDPR
9802 // This instruction is a '2-address' instruction in that the result goes
9803 // back to src2. This eliminates a move from the macro; possibly the
9804 // register allocator will have to add it back (and maybe not).
9805 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9806 predicate( UseSSE<=1 );
9807 match(Set src2 (AddD (MulD src0 src1) src2));
9808 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9809 "DMUL ST,$src1\n\t"
9810 "DADDp $src2,ST" %}
9811 ins_cost(250);
9812 opcode(0xDD); /* LoadD DD /0 */
9813 ins_encode( Push_Reg_FPR(src0),
9814 FMul_ST_reg(src1),
9815 FAddP_reg_ST(src2) );
9816 ins_pipe( fpu_reg_reg_reg );
9817 %}
9818
9819
9820 // MACRO3 -- subDPR a mulDPR
9821 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9822 predicate( UseSSE<=1 );
9823 match(Set src2 (SubD (MulD src0 src1) src2));
9824 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9825 "DMUL ST,$src1\n\t"
9826 "DSUBRp $src2,ST" %}
9827 ins_cost(250);
9828 ins_encode( Push_Reg_FPR(src0),
9829 FMul_ST_reg(src1),
9830 Opcode(0xDE), Opc_plus(0xE0,src2));
9831 ins_pipe( fpu_reg_reg_reg );
9832 %}
9833
9834
9835 instruct divDPR_reg(regDPR dst, regDPR src) %{
9836 predicate( UseSSE<=1 );
9837 match(Set dst (DivD dst src));
9838
9839 format %{ "FLD $src\n\t"
9840 "FDIVp $dst,ST" %}
9841 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9842 ins_cost(150);
9843 ins_encode( Push_Reg_DPR(src),
9844 OpcP, RegOpc(dst) );
9845 ins_pipe( fpu_reg_reg );
9846 %}
9847
9848 // Strict FP instruction biases argument before division then
9849 // biases result, to avoid double rounding of subnormals.
9850 //
9851 // scale dividend by multiplying dividend by 2^(-15360)
9852 // load divisor
9853 // divide scaled dividend by divisor
9854 // rescale quotient by 2^(15360)
9855 //
9856 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9857 predicate (UseSSE<=1);
9858 match(Set dst (DivD dst src));
9859 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9860 ins_cost(01);
9861
9862 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9863 "DMULp $dst,ST\n\t"
9864 "FLD $src\n\t"
9865 "FDIVp $dst,ST\n\t"
9866 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9867 "DMULp $dst,ST\n\t" %}
9868 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9869 ins_encode( strictfp_bias1(dst),
9870 Push_Reg_DPR(src),
9871 OpcP, RegOpc(dst),
9872 strictfp_bias2(dst) );
9873 ins_pipe( fpu_reg_reg );
9874 %}
9875
9876 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9877 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9878 match(Set dst (RoundDouble (DivD src1 src2)));
9879
9880 format %{ "FLD $src1\n\t"
9881 "FDIV ST,$src2\n\t"
9882 "FSTP_D $dst\t# D-round" %}
9883 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9884 ins_encode( Push_Reg_DPR(src1),
9885 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9886 ins_pipe( fpu_mem_reg_reg );
9887 %}
9888
9889
9890 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9891 predicate(UseSSE<=1);
9892 match(Set dst (ModD dst src));
9893 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9894
9895 format %{ "DMOD $dst,$src" %}
9896 ins_cost(250);
9897 ins_encode(Push_Reg_Mod_DPR(dst, src),
9898 emitModDPR(),
9899 Push_Result_Mod_DPR(src),
9900 Pop_Reg_DPR(dst));
9901 ins_pipe( pipe_slow );
9902 %}
9903
9904 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9905 predicate(UseSSE>=2);
9906 match(Set dst (ModD src0 src1));
9907 effect(KILL rax, KILL cr);
9908
9909 format %{ "SUB ESP,8\t # DMOD\n"
9910 "\tMOVSD [ESP+0],$src1\n"
9911 "\tFLD_D [ESP+0]\n"
9912 "\tMOVSD [ESP+0],$src0\n"
9913 "\tFLD_D [ESP+0]\n"
9914 "loop:\tFPREM\n"
9915 "\tFWAIT\n"
9916 "\tFNSTSW AX\n"
9917 "\tSAHF\n"
9918 "\tJP loop\n"
9919 "\tFSTP_D [ESP+0]\n"
9920 "\tMOVSD $dst,[ESP+0]\n"
9921 "\tADD ESP,8\n"
9922 "\tFSTP ST0\t # Restore FPU Stack"
9923 %}
9924 ins_cost(250);
9925 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9926 ins_pipe( pipe_slow );
9927 %}
9928
9929 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9930 predicate (UseSSE<=1);
9931 match(Set dst (SinD src));
9932 ins_cost(1800);
9933 format %{ "DSIN $dst" %}
9934 opcode(0xD9, 0xFE);
9935 ins_encode( OpcP, OpcS );
9936 ins_pipe( pipe_slow );
9937 %}
9938
9939 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9940 predicate (UseSSE>=2);
9941 match(Set dst (SinD dst));
9942 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9943 ins_cost(1800);
9944 format %{ "DSIN $dst" %}
9945 opcode(0xD9, 0xFE);
9946 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9947 ins_pipe( pipe_slow );
9948 %}
9949
9950 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9951 predicate (UseSSE<=1);
9952 match(Set dst (CosD src));
9953 ins_cost(1800);
9954 format %{ "DCOS $dst" %}
9955 opcode(0xD9, 0xFF);
9956 ins_encode( OpcP, OpcS );
9957 ins_pipe( pipe_slow );
9958 %}
9959
9960 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9961 predicate (UseSSE>=2);
9962 match(Set dst (CosD dst));
9963 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9964 ins_cost(1800);
9965 format %{ "DCOS $dst" %}
9966 opcode(0xD9, 0xFF);
9967 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9968 ins_pipe( pipe_slow );
9969 %}
9970
9971 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9972 predicate (UseSSE<=1);
9973 match(Set dst(TanD src));
9974 format %{ "DTAN $dst" %}
9975 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9976 Opcode(0xDD), Opcode(0xD8)); // fstp st
9977 ins_pipe( pipe_slow );
9978 %}
9979
9980 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9981 predicate (UseSSE>=2);
9982 match(Set dst(TanD dst));
9983 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9984 format %{ "DTAN $dst" %}
9985 ins_encode( Push_SrcD(dst),
9986 Opcode(0xD9), Opcode(0xF2), // fptan
9987 Opcode(0xDD), Opcode(0xD8), // fstp st
9988 Push_ResultD(dst) );
9989 ins_pipe( pipe_slow );
9990 %}
9991
9992 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9993 predicate (UseSSE<=1);
9994 match(Set dst(AtanD dst src));
9995 format %{ "DATA $dst,$src" %}
9996 opcode(0xD9, 0xF3);
9997 ins_encode( Push_Reg_DPR(src),
9998 OpcP, OpcS, RegOpc(dst) );
9999 ins_pipe( pipe_slow );
10000 %}
10001
10002 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10003 predicate (UseSSE>=2);
10004 match(Set dst(AtanD dst src));
10005 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10006 format %{ "DATA $dst,$src" %}
10007 opcode(0xD9, 0xF3);
10008 ins_encode( Push_SrcD(src),
10009 OpcP, OpcS, Push_ResultD(dst) );
10010 ins_pipe( pipe_slow );
10011 %}
10012
10013 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10014 predicate (UseSSE<=1);
10015 match(Set dst (SqrtD src));
10016 format %{ "DSQRT $dst,$src" %}
10017 opcode(0xFA, 0xD9);
10018 ins_encode( Push_Reg_DPR(src),
10019 OpcS, OpcP, Pop_Reg_DPR(dst) );
10020 ins_pipe( pipe_slow );
10021 %}
10022
10023 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10024 predicate (UseSSE<=1);
10025 match(Set Y (PowD X Y)); // Raise X to the Yth power
10026 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10027 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10028 ins_encode %{
10029 __ subptr(rsp, 8);
10030 __ fld_s($X$$reg - 1);
10031 __ fast_pow();
10032 __ addptr(rsp, 8);
10033 %}
10034 ins_pipe( pipe_slow );
10035 %}
10036
10037 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10038 predicate (UseSSE>=2);
10039 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10040 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10041 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10042 ins_encode %{
10043 __ subptr(rsp, 8);
10044 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10045 __ fld_d(Address(rsp, 0));
10046 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10047 __ fld_d(Address(rsp, 0));
10048 __ fast_pow();
10049 __ fstp_d(Address(rsp, 0));
10050 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10051 __ addptr(rsp, 8);
10052 %}
10053 ins_pipe( pipe_slow );
10054 %}
10055
10056
10057 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10058 predicate (UseSSE<=1);
10059 match(Set dpr1 (ExpD dpr1));
10060 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10061 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10062 ins_encode %{
10063 __ fast_exp();
10064 %}
10065 ins_pipe( pipe_slow );
10066 %}
10067
10068 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10069 predicate (UseSSE>=2);
10070 match(Set dst (ExpD src));
10071 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10072 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10073 ins_encode %{
10074 __ subptr(rsp, 8);
10075 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10076 __ fld_d(Address(rsp, 0));
10077 __ fast_exp();
10078 __ fstp_d(Address(rsp, 0));
10079 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10080 __ addptr(rsp, 8);
10081 %}
10082 ins_pipe( pipe_slow );
10083 %}
10084
10085 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10086 predicate (UseSSE<=1);
10087 // The source Double operand on FPU stack
10088 match(Set dst (Log10D src));
10089 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10090 // fxch ; swap ST(0) with ST(1)
10091 // fyl2x ; compute log_10(2) * log_2(x)
10092 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10093 "FXCH \n\t"
10094 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10095 %}
10096 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10097 Opcode(0xD9), Opcode(0xC9), // fxch
10098 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10099
10100 ins_pipe( pipe_slow );
10101 %}
10102
10103 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10104 predicate (UseSSE>=2);
10105 effect(KILL cr);
10106 match(Set dst (Log10D src));
10107 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10108 // fyl2x ; compute log_10(2) * log_2(x)
10109 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10110 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10111 %}
10112 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10113 Push_SrcD(src),
10114 Opcode(0xD9), Opcode(0xF1), // fyl2x
10115 Push_ResultD(dst));
10116
10117 ins_pipe( pipe_slow );
10118 %}
10119
10120 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10121 predicate (UseSSE<=1);
10122 // The source Double operand on FPU stack
10123 match(Set dst (LogD src));
10124 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10125 // fxch ; swap ST(0) with ST(1)
10126 // fyl2x ; compute log_e(2) * log_2(x)
10127 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10128 "FXCH \n\t"
10129 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10130 %}
10131 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10132 Opcode(0xD9), Opcode(0xC9), // fxch
10133 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10134
10135 ins_pipe( pipe_slow );
10136 %}
10137
10138 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10139 predicate (UseSSE>=2);
10140 effect(KILL cr);
10141 // The source and result Double operands in XMM registers
10142 match(Set dst (LogD src));
10143 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10144 // fyl2x ; compute log_e(2) * log_2(x)
10145 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10146 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10147 %}
10148 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10149 Push_SrcD(src),
10150 Opcode(0xD9), Opcode(0xF1), // fyl2x
10151 Push_ResultD(dst));
10152 ins_pipe( pipe_slow );
10153 %}
10154
10155 //-------------Float Instructions-------------------------------
10156 // Float Math
10157
10158 // Code for float compare:
10159 // fcompp();
10160 // fwait(); fnstsw_ax();
10161 // sahf();
10162 // movl(dst, unordered_result);
10163 // jcc(Assembler::parity, exit);
10164 // movl(dst, less_result);
10165 // jcc(Assembler::below, exit);
10166 // movl(dst, equal_result);
10167 // jcc(Assembler::equal, exit);
10168 // movl(dst, greater_result);
10169 // exit:
10170
10171 // P6 version of float compare, sets condition codes in EFLAGS
10172 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10173 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10174 match(Set cr (CmpF src1 src2));
10175 effect(KILL rax);
10176 ins_cost(150);
10177 format %{ "FLD $src1\n\t"
10178 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10179 "JNP exit\n\t"
10180 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10181 "SAHF\n"
10182 "exit:\tNOP // avoid branch to branch" %}
10183 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10184 ins_encode( Push_Reg_DPR(src1),
10185 OpcP, RegOpc(src2),
10186 cmpF_P6_fixup );
10187 ins_pipe( pipe_slow );
10188 %}
10189
10190 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10191 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10192 match(Set cr (CmpF src1 src2));
10193 ins_cost(100);
10194 format %{ "FLD $src1\n\t"
10195 "FUCOMIP ST,$src2 // P6 instruction" %}
10196 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10197 ins_encode( Push_Reg_DPR(src1),
10198 OpcP, RegOpc(src2));
10199 ins_pipe( pipe_slow );
10200 %}
10201
10202
10203 // Compare & branch
10204 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10205 predicate(UseSSE == 0);
10206 match(Set cr (CmpF src1 src2));
10207 effect(KILL rax);
10208 ins_cost(200);
10209 format %{ "FLD $src1\n\t"
10210 "FCOMp $src2\n\t"
10211 "FNSTSW AX\n\t"
10212 "TEST AX,0x400\n\t"
10213 "JZ,s flags\n\t"
10214 "MOV AH,1\t# unordered treat as LT\n"
10215 "flags:\tSAHF" %}
10216 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10217 ins_encode( Push_Reg_DPR(src1),
10218 OpcP, RegOpc(src2),
10219 fpu_flags);
10220 ins_pipe( pipe_slow );
10221 %}
10222
10223 // Compare vs zero into -1,0,1
10224 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10225 predicate(UseSSE == 0);
10226 match(Set dst (CmpF3 src1 zero));
10227 effect(KILL cr, KILL rax);
10228 ins_cost(280);
10229 format %{ "FTSTF $dst,$src1" %}
10230 opcode(0xE4, 0xD9);
10231 ins_encode( Push_Reg_DPR(src1),
10232 OpcS, OpcP, PopFPU,
10233 CmpF_Result(dst));
10234 ins_pipe( pipe_slow );
10235 %}
10236
10237 // Compare into -1,0,1
10238 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10239 predicate(UseSSE == 0);
10240 match(Set dst (CmpF3 src1 src2));
10241 effect(KILL cr, KILL rax);
10242 ins_cost(300);
10243 format %{ "FCMPF $dst,$src1,$src2" %}
10244 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10245 ins_encode( Push_Reg_DPR(src1),
10246 OpcP, RegOpc(src2),
10247 CmpF_Result(dst));
10248 ins_pipe( pipe_slow );
10249 %}
10250
10251 // float compare and set condition codes in EFLAGS by XMM regs
10252 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10253 predicate(UseSSE>=1);
10254 match(Set cr (CmpF src1 src2));
10255 ins_cost(145);
10256 format %{ "UCOMISS $src1,$src2\n\t"
10257 "JNP,s exit\n\t"
10258 "PUSHF\t# saw NaN, set CF\n\t"
10259 "AND [rsp], #0xffffff2b\n\t"
10260 "POPF\n"
10261 "exit:" %}
10262 ins_encode %{
10263 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10264 emit_cmpfp_fixup(_masm);
10265 %}
10266 ins_pipe( pipe_slow );
10267 %}
10268
10269 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10270 predicate(UseSSE>=1);
10271 match(Set cr (CmpF src1 src2));
10272 ins_cost(100);
10273 format %{ "UCOMISS $src1,$src2" %}
10274 ins_encode %{
10275 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10276 %}
10277 ins_pipe( pipe_slow );
10278 %}
10279
10280 // float compare and set condition codes in EFLAGS by XMM regs
10281 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10282 predicate(UseSSE>=1);
10283 match(Set cr (CmpF src1 (LoadF src2)));
10284 ins_cost(165);
10285 format %{ "UCOMISS $src1,$src2\n\t"
10286 "JNP,s exit\n\t"
10287 "PUSHF\t# saw NaN, set CF\n\t"
10288 "AND [rsp], #0xffffff2b\n\t"
10289 "POPF\n"
10290 "exit:" %}
10291 ins_encode %{
10292 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10293 emit_cmpfp_fixup(_masm);
10294 %}
10295 ins_pipe( pipe_slow );
10296 %}
10297
10298 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10299 predicate(UseSSE>=1);
10300 match(Set cr (CmpF src1 (LoadF src2)));
10301 ins_cost(100);
10302 format %{ "UCOMISS $src1,$src2" %}
10303 ins_encode %{
10304 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10305 %}
10306 ins_pipe( pipe_slow );
10307 %}
10308
10309 // Compare into -1,0,1 in XMM
10310 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10311 predicate(UseSSE>=1);
10312 match(Set dst (CmpF3 src1 src2));
10313 effect(KILL cr);
10314 ins_cost(255);
10315 format %{ "UCOMISS $src1, $src2\n\t"
10316 "MOV $dst, #-1\n\t"
10317 "JP,s done\n\t"
10318 "JB,s done\n\t"
10319 "SETNE $dst\n\t"
10320 "MOVZB $dst, $dst\n"
10321 "done:" %}
10322 ins_encode %{
10323 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10324 emit_cmpfp3(_masm, $dst$$Register);
10325 %}
10326 ins_pipe( pipe_slow );
10327 %}
10328
10329 // Compare into -1,0,1 in XMM and memory
10330 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10331 predicate(UseSSE>=1);
10332 match(Set dst (CmpF3 src1 (LoadF src2)));
10333 effect(KILL cr);
10334 ins_cost(275);
10335 format %{ "UCOMISS $src1, $src2\n\t"
10336 "MOV $dst, #-1\n\t"
10337 "JP,s done\n\t"
10338 "JB,s done\n\t"
10339 "SETNE $dst\n\t"
10340 "MOVZB $dst, $dst\n"
10341 "done:" %}
10342 ins_encode %{
10343 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10344 emit_cmpfp3(_masm, $dst$$Register);
10345 %}
10346 ins_pipe( pipe_slow );
10347 %}
10348
10349 // Spill to obtain 24-bit precision
10350 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10351 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10352 match(Set dst (SubF src1 src2));
10353
10354 format %{ "FSUB $dst,$src1 - $src2" %}
10355 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10356 ins_encode( Push_Reg_FPR(src1),
10357 OpcReg_FPR(src2),
10358 Pop_Mem_FPR(dst) );
10359 ins_pipe( fpu_mem_reg_reg );
10360 %}
10361 //
10362 // This instruction does not round to 24-bits
10363 instruct subFPR_reg(regFPR dst, regFPR src) %{
10364 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10365 match(Set dst (SubF dst src));
10366
10367 format %{ "FSUB $dst,$src" %}
10368 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10369 ins_encode( Push_Reg_FPR(src),
10370 OpcP, RegOpc(dst) );
10371 ins_pipe( fpu_reg_reg );
10372 %}
10373
10374 // Spill to obtain 24-bit precision
10375 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10376 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10377 match(Set dst (AddF src1 src2));
10378
10379 format %{ "FADD $dst,$src1,$src2" %}
10380 opcode(0xD8, 0x0); /* D8 C0+i */
10381 ins_encode( Push_Reg_FPR(src2),
10382 OpcReg_FPR(src1),
10383 Pop_Mem_FPR(dst) );
10384 ins_pipe( fpu_mem_reg_reg );
10385 %}
10386 //
10387 // This instruction does not round to 24-bits
10388 instruct addFPR_reg(regFPR dst, regFPR src) %{
10389 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10390 match(Set dst (AddF dst src));
10391
10392 format %{ "FLD $src\n\t"
10393 "FADDp $dst,ST" %}
10394 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10395 ins_encode( Push_Reg_FPR(src),
10396 OpcP, RegOpc(dst) );
10397 ins_pipe( fpu_reg_reg );
10398 %}
10399
10400 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10401 predicate(UseSSE==0);
10402 match(Set dst (AbsF src));
10403 ins_cost(100);
10404 format %{ "FABS" %}
10405 opcode(0xE1, 0xD9);
10406 ins_encode( OpcS, OpcP );
10407 ins_pipe( fpu_reg_reg );
10408 %}
10409
10410 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10411 predicate(UseSSE==0);
10412 match(Set dst (NegF src));
10413 ins_cost(100);
10414 format %{ "FCHS" %}
10415 opcode(0xE0, 0xD9);
10416 ins_encode( OpcS, OpcP );
10417 ins_pipe( fpu_reg_reg );
10418 %}
10419
10420 // Cisc-alternate to addFPR_reg
10421 // Spill to obtain 24-bit precision
10422 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10423 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10424 match(Set dst (AddF src1 (LoadF src2)));
10425
10426 format %{ "FLD $src2\n\t"
10427 "FADD ST,$src1\n\t"
10428 "FSTP_S $dst" %}
10429 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10430 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10431 OpcReg_FPR(src1),
10432 Pop_Mem_FPR(dst) );
10433 ins_pipe( fpu_mem_reg_mem );
10434 %}
10435 //
10436 // Cisc-alternate to addFPR_reg
10437 // This instruction does not round to 24-bits
10438 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10439 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10440 match(Set dst (AddF dst (LoadF src)));
10441
10442 format %{ "FADD $dst,$src" %}
10443 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10444 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10445 OpcP, RegOpc(dst) );
10446 ins_pipe( fpu_reg_mem );
10447 %}
10448
10449 // // Following two instructions for _222_mpegaudio
10450 // Spill to obtain 24-bit precision
10451 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10452 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10453 match(Set dst (AddF src1 src2));
10454
10455 format %{ "FADD $dst,$src1,$src2" %}
10456 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10457 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10458 OpcReg_FPR(src2),
10459 Pop_Mem_FPR(dst) );
10460 ins_pipe( fpu_mem_reg_mem );
10461 %}
10462
10463 // Cisc-spill variant
10464 // Spill to obtain 24-bit precision
10465 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10466 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10467 match(Set dst (AddF src1 (LoadF src2)));
10468
10469 format %{ "FADD $dst,$src1,$src2 cisc" %}
10470 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10471 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10472 set_instruction_start,
10473 OpcP, RMopc_Mem(secondary,src1),
10474 Pop_Mem_FPR(dst) );
10475 ins_pipe( fpu_mem_mem_mem );
10476 %}
10477
10478 // Spill to obtain 24-bit precision
10479 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10480 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10481 match(Set dst (AddF src1 src2));
10482
10483 format %{ "FADD $dst,$src1,$src2" %}
10484 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10485 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10486 set_instruction_start,
10487 OpcP, RMopc_Mem(secondary,src1),
10488 Pop_Mem_FPR(dst) );
10489 ins_pipe( fpu_mem_mem_mem );
10490 %}
10491
10492
10493 // Spill to obtain 24-bit precision
10494 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10495 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10496 match(Set dst (AddF src con));
10497 format %{ "FLD $src\n\t"
10498 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10499 "FSTP_S $dst" %}
10500 ins_encode %{
10501 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10502 __ fadd_s($constantaddress($con));
10503 __ fstp_s(Address(rsp, $dst$$disp));
10504 %}
10505 ins_pipe(fpu_mem_reg_con);
10506 %}
10507 //
10508 // This instruction does not round to 24-bits
10509 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10510 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10511 match(Set dst (AddF src con));
10512 format %{ "FLD $src\n\t"
10513 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10514 "FSTP $dst" %}
10515 ins_encode %{
10516 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10517 __ fadd_s($constantaddress($con));
10518 __ fstp_d($dst$$reg);
10519 %}
10520 ins_pipe(fpu_reg_reg_con);
10521 %}
10522
10523 // Spill to obtain 24-bit precision
10524 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10525 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10526 match(Set dst (MulF src1 src2));
10527
10528 format %{ "FLD $src1\n\t"
10529 "FMUL $src2\n\t"
10530 "FSTP_S $dst" %}
10531 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10532 ins_encode( Push_Reg_FPR(src1),
10533 OpcReg_FPR(src2),
10534 Pop_Mem_FPR(dst) );
10535 ins_pipe( fpu_mem_reg_reg );
10536 %}
10537 //
10538 // This instruction does not round to 24-bits
10539 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10540 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10541 match(Set dst (MulF src1 src2));
10542
10543 format %{ "FLD $src1\n\t"
10544 "FMUL $src2\n\t"
10545 "FSTP_S $dst" %}
10546 opcode(0xD8, 0x1); /* D8 C8+i */
10547 ins_encode( Push_Reg_FPR(src2),
10548 OpcReg_FPR(src1),
10549 Pop_Reg_FPR(dst) );
10550 ins_pipe( fpu_reg_reg_reg );
10551 %}
10552
10553
10554 // Spill to obtain 24-bit precision
10555 // Cisc-alternate to reg-reg multiply
10556 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10557 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10558 match(Set dst (MulF src1 (LoadF src2)));
10559
10560 format %{ "FLD_S $src2\n\t"
10561 "FMUL $src1\n\t"
10562 "FSTP_S $dst" %}
10563 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10564 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10565 OpcReg_FPR(src1),
10566 Pop_Mem_FPR(dst) );
10567 ins_pipe( fpu_mem_reg_mem );
10568 %}
10569 //
10570 // This instruction does not round to 24-bits
10571 // Cisc-alternate to reg-reg multiply
10572 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10573 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10574 match(Set dst (MulF src1 (LoadF src2)));
10575
10576 format %{ "FMUL $dst,$src1,$src2" %}
10577 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10578 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10579 OpcReg_FPR(src1),
10580 Pop_Reg_FPR(dst) );
10581 ins_pipe( fpu_reg_reg_mem );
10582 %}
10583
10584 // Spill to obtain 24-bit precision
10585 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10586 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10587 match(Set dst (MulF src1 src2));
10588
10589 format %{ "FMUL $dst,$src1,$src2" %}
10590 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10591 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10592 set_instruction_start,
10593 OpcP, RMopc_Mem(secondary,src1),
10594 Pop_Mem_FPR(dst) );
10595 ins_pipe( fpu_mem_mem_mem );
10596 %}
10597
10598 // Spill to obtain 24-bit precision
10599 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10600 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10601 match(Set dst (MulF src con));
10602
10603 format %{ "FLD $src\n\t"
10604 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10605 "FSTP_S $dst" %}
10606 ins_encode %{
10607 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10608 __ fmul_s($constantaddress($con));
10609 __ fstp_s(Address(rsp, $dst$$disp));
10610 %}
10611 ins_pipe(fpu_mem_reg_con);
10612 %}
10613 //
10614 // This instruction does not round to 24-bits
10615 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10616 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10617 match(Set dst (MulF src con));
10618
10619 format %{ "FLD $src\n\t"
10620 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10621 "FSTP $dst" %}
10622 ins_encode %{
10623 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10624 __ fmul_s($constantaddress($con));
10625 __ fstp_d($dst$$reg);
10626 %}
10627 ins_pipe(fpu_reg_reg_con);
10628 %}
10629
10630
10631 //
10632 // MACRO1 -- subsume unshared load into mulFPR
10633 // This instruction does not round to 24-bits
10634 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10635 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10636 match(Set dst (MulF (LoadF mem1) src));
10637
10638 format %{ "FLD $mem1 ===MACRO1===\n\t"
10639 "FMUL ST,$src\n\t"
10640 "FSTP $dst" %}
10641 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10642 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10643 OpcReg_FPR(src),
10644 Pop_Reg_FPR(dst) );
10645 ins_pipe( fpu_reg_reg_mem );
10646 %}
10647 //
10648 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10649 // This instruction does not round to 24-bits
10650 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10651 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10652 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10653 ins_cost(95);
10654
10655 format %{ "FLD $mem1 ===MACRO2===\n\t"
10656 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10657 "FADD ST,$src2\n\t"
10658 "FSTP $dst" %}
10659 opcode(0xD9); /* LoadF D9 /0 */
10660 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10661 FMul_ST_reg(src1),
10662 FAdd_ST_reg(src2),
10663 Pop_Reg_FPR(dst) );
10664 ins_pipe( fpu_reg_mem_reg_reg );
10665 %}
10666
10667 // MACRO3 -- addFPR a mulFPR
10668 // This instruction does not round to 24-bits. It is a '2-address'
10669 // instruction in that the result goes back to src2. This eliminates
10670 // a move from the macro; possibly the register allocator will have
10671 // to add it back (and maybe not).
10672 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10673 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10674 match(Set src2 (AddF (MulF src0 src1) src2));
10675
10676 format %{ "FLD $src0 ===MACRO3===\n\t"
10677 "FMUL ST,$src1\n\t"
10678 "FADDP $src2,ST" %}
10679 opcode(0xD9); /* LoadF D9 /0 */
10680 ins_encode( Push_Reg_FPR(src0),
10681 FMul_ST_reg(src1),
10682 FAddP_reg_ST(src2) );
10683 ins_pipe( fpu_reg_reg_reg );
10684 %}
10685
10686 // MACRO4 -- divFPR subFPR
10687 // This instruction does not round to 24-bits
10688 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10689 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10690 match(Set dst (DivF (SubF src2 src1) src3));
10691
10692 format %{ "FLD $src2 ===MACRO4===\n\t"
10693 "FSUB ST,$src1\n\t"
10694 "FDIV ST,$src3\n\t"
10695 "FSTP $dst" %}
10696 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10697 ins_encode( Push_Reg_FPR(src2),
10698 subFPR_divFPR_encode(src1,src3),
10699 Pop_Reg_FPR(dst) );
10700 ins_pipe( fpu_reg_reg_reg_reg );
10701 %}
10702
10703 // Spill to obtain 24-bit precision
10704 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10705 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10706 match(Set dst (DivF src1 src2));
10707
10708 format %{ "FDIV $dst,$src1,$src2" %}
10709 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10710 ins_encode( Push_Reg_FPR(src1),
10711 OpcReg_FPR(src2),
10712 Pop_Mem_FPR(dst) );
10713 ins_pipe( fpu_mem_reg_reg );
10714 %}
10715 //
10716 // This instruction does not round to 24-bits
10717 instruct divFPR_reg(regFPR dst, regFPR src) %{
10718 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10719 match(Set dst (DivF dst src));
10720
10721 format %{ "FDIV $dst,$src" %}
10722 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10723 ins_encode( Push_Reg_FPR(src),
10724 OpcP, RegOpc(dst) );
10725 ins_pipe( fpu_reg_reg );
10726 %}
10727
10728
10729 // Spill to obtain 24-bit precision
10730 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10731 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10732 match(Set dst (ModF src1 src2));
10733 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10734
10735 format %{ "FMOD $dst,$src1,$src2" %}
10736 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10737 emitModDPR(),
10738 Push_Result_Mod_DPR(src2),
10739 Pop_Mem_FPR(dst));
10740 ins_pipe( pipe_slow );
10741 %}
10742 //
10743 // This instruction does not round to 24-bits
10744 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10745 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10746 match(Set dst (ModF dst src));
10747 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10748
10749 format %{ "FMOD $dst,$src" %}
10750 ins_encode(Push_Reg_Mod_DPR(dst, src),
10751 emitModDPR(),
10752 Push_Result_Mod_DPR(src),
10753 Pop_Reg_FPR(dst));
10754 ins_pipe( pipe_slow );
10755 %}
10756
10757 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10758 predicate(UseSSE>=1);
10759 match(Set dst (ModF src0 src1));
10760 effect(KILL rax, KILL cr);
10761 format %{ "SUB ESP,4\t # FMOD\n"
10762 "\tMOVSS [ESP+0],$src1\n"
10763 "\tFLD_S [ESP+0]\n"
10764 "\tMOVSS [ESP+0],$src0\n"
10765 "\tFLD_S [ESP+0]\n"
10766 "loop:\tFPREM\n"
10767 "\tFWAIT\n"
10768 "\tFNSTSW AX\n"
10769 "\tSAHF\n"
10770 "\tJP loop\n"
10771 "\tFSTP_S [ESP+0]\n"
10772 "\tMOVSS $dst,[ESP+0]\n"
10773 "\tADD ESP,4\n"
10774 "\tFSTP ST0\t # Restore FPU Stack"
10775 %}
10776 ins_cost(250);
10777 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10778 ins_pipe( pipe_slow );
10779 %}
10780
10781
10782 //----------Arithmetic Conversion Instructions---------------------------------
10783 // The conversions operations are all Alpha sorted. Please keep it that way!
10784
10785 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10786 predicate(UseSSE==0);
10787 match(Set dst (RoundFloat src));
10788 ins_cost(125);
10789 format %{ "FST_S $dst,$src\t# F-round" %}
10790 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10791 ins_pipe( fpu_mem_reg );
10792 %}
10793
10794 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10795 predicate(UseSSE<=1);
10796 match(Set dst (RoundDouble src));
10797 ins_cost(125);
10798 format %{ "FST_D $dst,$src\t# D-round" %}
10799 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10800 ins_pipe( fpu_mem_reg );
10801 %}
10802
10803 // Force rounding to 24-bit precision and 6-bit exponent
10804 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10805 predicate(UseSSE==0);
10806 match(Set dst (ConvD2F src));
10807 format %{ "FST_S $dst,$src\t# F-round" %}
10808 expand %{
10809 roundFloat_mem_reg(dst,src);
10810 %}
10811 %}
10812
10813 // Force rounding to 24-bit precision and 6-bit exponent
10814 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10815 predicate(UseSSE==1);
10816 match(Set dst (ConvD2F src));
10817 effect( KILL cr );
10818 format %{ "SUB ESP,4\n\t"
10819 "FST_S [ESP],$src\t# F-round\n\t"
10820 "MOVSS $dst,[ESP]\n\t"
10821 "ADD ESP,4" %}
10822 ins_encode %{
10823 __ subptr(rsp, 4);
10824 if ($src$$reg != FPR1L_enc) {
10825 __ fld_s($src$$reg-1);
10826 __ fstp_s(Address(rsp, 0));
10827 } else {
10828 __ fst_s(Address(rsp, 0));
10829 }
10830 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10831 __ addptr(rsp, 4);
10832 %}
10833 ins_pipe( pipe_slow );
10834 %}
10835
10836 // Force rounding double precision to single precision
10837 instruct convD2F_reg(regF dst, regD src) %{
10838 predicate(UseSSE>=2);
10839 match(Set dst (ConvD2F src));
10840 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10841 ins_encode %{
10842 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10843 %}
10844 ins_pipe( pipe_slow );
10845 %}
10846
10847 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10848 predicate(UseSSE==0);
10849 match(Set dst (ConvF2D src));
10850 format %{ "FST_S $dst,$src\t# D-round" %}
10851 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10852 ins_pipe( fpu_reg_reg );
10853 %}
10854
10855 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10856 predicate(UseSSE==1);
10857 match(Set dst (ConvF2D src));
10858 format %{ "FST_D $dst,$src\t# D-round" %}
10859 expand %{
10860 roundDouble_mem_reg(dst,src);
10861 %}
10862 %}
10863
10864 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10865 predicate(UseSSE==1);
10866 match(Set dst (ConvF2D src));
10867 effect( KILL cr );
10868 format %{ "SUB ESP,4\n\t"
10869 "MOVSS [ESP] $src\n\t"
10870 "FLD_S [ESP]\n\t"
10871 "ADD ESP,4\n\t"
10872 "FSTP $dst\t# D-round" %}
10873 ins_encode %{
10874 __ subptr(rsp, 4);
10875 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10876 __ fld_s(Address(rsp, 0));
10877 __ addptr(rsp, 4);
10878 __ fstp_d($dst$$reg);
10879 %}
10880 ins_pipe( pipe_slow );
10881 %}
10882
10883 instruct convF2D_reg(regD dst, regF src) %{
10884 predicate(UseSSE>=2);
10885 match(Set dst (ConvF2D src));
10886 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10887 ins_encode %{
10888 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10889 %}
10890 ins_pipe( pipe_slow );
10891 %}
10892
10893 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10894 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10895 predicate(UseSSE<=1);
10896 match(Set dst (ConvD2I src));
10897 effect( KILL tmp, KILL cr );
10898 format %{ "FLD $src\t# Convert double to int \n\t"
10899 "FLDCW trunc mode\n\t"
10900 "SUB ESP,4\n\t"
10901 "FISTp [ESP + #0]\n\t"
10902 "FLDCW std/24-bit mode\n\t"
10903 "POP EAX\n\t"
10904 "CMP EAX,0x80000000\n\t"
10905 "JNE,s fast\n\t"
10906 "FLD_D $src\n\t"
10907 "CALL d2i_wrapper\n"
10908 "fast:" %}
10909 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10910 ins_pipe( pipe_slow );
10911 %}
10912
10913 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10914 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10915 predicate(UseSSE>=2);
10916 match(Set dst (ConvD2I src));
10917 effect( KILL tmp, KILL cr );
10918 format %{ "CVTTSD2SI $dst, $src\n\t"
10919 "CMP $dst,0x80000000\n\t"
10920 "JNE,s fast\n\t"
10921 "SUB ESP, 8\n\t"
10922 "MOVSD [ESP], $src\n\t"
10923 "FLD_D [ESP]\n\t"
10924 "ADD ESP, 8\n\t"
10925 "CALL d2i_wrapper\n"
10926 "fast:" %}
10927 ins_encode %{
10928 Label fast;
10929 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10930 __ cmpl($dst$$Register, 0x80000000);
10931 __ jccb(Assembler::notEqual, fast);
10932 __ subptr(rsp, 8);
10933 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10934 __ fld_d(Address(rsp, 0));
10935 __ addptr(rsp, 8);
10936 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10937 __ bind(fast);
10938 %}
10939 ins_pipe( pipe_slow );
10940 %}
10941
10942 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10943 predicate(UseSSE<=1);
10944 match(Set dst (ConvD2L src));
10945 effect( KILL cr );
10946 format %{ "FLD $src\t# Convert double to long\n\t"
10947 "FLDCW trunc mode\n\t"
10948 "SUB ESP,8\n\t"
10949 "FISTp [ESP + #0]\n\t"
10950 "FLDCW std/24-bit mode\n\t"
10951 "POP EAX\n\t"
10952 "POP EDX\n\t"
10953 "CMP EDX,0x80000000\n\t"
10954 "JNE,s fast\n\t"
10955 "TEST EAX,EAX\n\t"
10956 "JNE,s fast\n\t"
10957 "FLD $src\n\t"
10958 "CALL d2l_wrapper\n"
10959 "fast:" %}
10960 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10961 ins_pipe( pipe_slow );
10962 %}
10963
10964 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10965 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10966 predicate (UseSSE>=2);
10967 match(Set dst (ConvD2L src));
10968 effect( KILL cr );
10969 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10970 "MOVSD [ESP],$src\n\t"
10971 "FLD_D [ESP]\n\t"
10972 "FLDCW trunc mode\n\t"
10973 "FISTp [ESP + #0]\n\t"
10974 "FLDCW std/24-bit mode\n\t"
10975 "POP EAX\n\t"
10976 "POP EDX\n\t"
10977 "CMP EDX,0x80000000\n\t"
10978 "JNE,s fast\n\t"
10979 "TEST EAX,EAX\n\t"
10980 "JNE,s fast\n\t"
10981 "SUB ESP,8\n\t"
10982 "MOVSD [ESP],$src\n\t"
10983 "FLD_D [ESP]\n\t"
10984 "ADD ESP,8\n\t"
10985 "CALL d2l_wrapper\n"
10986 "fast:" %}
10987 ins_encode %{
10988 Label fast;
10989 __ subptr(rsp, 8);
10990 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10991 __ fld_d(Address(rsp, 0));
10992 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10993 __ fistp_d(Address(rsp, 0));
10994 // Restore the rounding mode, mask the exception
10995 if (Compile::current()->in_24_bit_fp_mode()) {
10996 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10997 } else {
10998 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10999 }
11000 // Load the converted long, adjust CPU stack
11001 __ pop(rax);
11002 __ pop(rdx);
11003 __ cmpl(rdx, 0x80000000);
11004 __ jccb(Assembler::notEqual, fast);
11005 __ testl(rax, rax);
11006 __ jccb(Assembler::notEqual, fast);
11007 __ subptr(rsp, 8);
11008 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11009 __ fld_d(Address(rsp, 0));
11010 __ addptr(rsp, 8);
11011 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11012 __ bind(fast);
11013 %}
11014 ins_pipe( pipe_slow );
11015 %}
11016
11017 // Convert a double to an int. Java semantics require we do complex
11018 // manglations in the corner cases. So we set the rounding mode to
11019 // 'zero', store the darned double down as an int, and reset the
11020 // rounding mode to 'nearest'. The hardware stores a flag value down
11021 // if we would overflow or converted a NAN; we check for this and
11022 // and go the slow path if needed.
11023 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11024 predicate(UseSSE==0);
11025 match(Set dst (ConvF2I src));
11026 effect( KILL tmp, KILL cr );
11027 format %{ "FLD $src\t# Convert float to int \n\t"
11028 "FLDCW trunc mode\n\t"
11029 "SUB ESP,4\n\t"
11030 "FISTp [ESP + #0]\n\t"
11031 "FLDCW std/24-bit mode\n\t"
11032 "POP EAX\n\t"
11033 "CMP EAX,0x80000000\n\t"
11034 "JNE,s fast\n\t"
11035 "FLD $src\n\t"
11036 "CALL d2i_wrapper\n"
11037 "fast:" %}
11038 // DPR2I_encoding works for FPR2I
11039 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11040 ins_pipe( pipe_slow );
11041 %}
11042
11043 // Convert a float in xmm to an int reg.
11044 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11045 predicate(UseSSE>=1);
11046 match(Set dst (ConvF2I src));
11047 effect( KILL tmp, KILL cr );
11048 format %{ "CVTTSS2SI $dst, $src\n\t"
11049 "CMP $dst,0x80000000\n\t"
11050 "JNE,s fast\n\t"
11051 "SUB ESP, 4\n\t"
11052 "MOVSS [ESP], $src\n\t"
11053 "FLD [ESP]\n\t"
11054 "ADD ESP, 4\n\t"
11055 "CALL d2i_wrapper\n"
11056 "fast:" %}
11057 ins_encode %{
11058 Label fast;
11059 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11060 __ cmpl($dst$$Register, 0x80000000);
11061 __ jccb(Assembler::notEqual, fast);
11062 __ subptr(rsp, 4);
11063 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11064 __ fld_s(Address(rsp, 0));
11065 __ addptr(rsp, 4);
11066 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11067 __ bind(fast);
11068 %}
11069 ins_pipe( pipe_slow );
11070 %}
11071
11072 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11073 predicate(UseSSE==0);
11074 match(Set dst (ConvF2L src));
11075 effect( KILL cr );
11076 format %{ "FLD $src\t# Convert float to long\n\t"
11077 "FLDCW trunc mode\n\t"
11078 "SUB ESP,8\n\t"
11079 "FISTp [ESP + #0]\n\t"
11080 "FLDCW std/24-bit mode\n\t"
11081 "POP EAX\n\t"
11082 "POP EDX\n\t"
11083 "CMP EDX,0x80000000\n\t"
11084 "JNE,s fast\n\t"
11085 "TEST EAX,EAX\n\t"
11086 "JNE,s fast\n\t"
11087 "FLD $src\n\t"
11088 "CALL d2l_wrapper\n"
11089 "fast:" %}
11090 // DPR2L_encoding works for FPR2L
11091 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11092 ins_pipe( pipe_slow );
11093 %}
11094
11095 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11096 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11097 predicate (UseSSE>=1);
11098 match(Set dst (ConvF2L src));
11099 effect( KILL cr );
11100 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11101 "MOVSS [ESP],$src\n\t"
11102 "FLD_S [ESP]\n\t"
11103 "FLDCW trunc mode\n\t"
11104 "FISTp [ESP + #0]\n\t"
11105 "FLDCW std/24-bit mode\n\t"
11106 "POP EAX\n\t"
11107 "POP EDX\n\t"
11108 "CMP EDX,0x80000000\n\t"
11109 "JNE,s fast\n\t"
11110 "TEST EAX,EAX\n\t"
11111 "JNE,s fast\n\t"
11112 "SUB ESP,4\t# Convert float to long\n\t"
11113 "MOVSS [ESP],$src\n\t"
11114 "FLD_S [ESP]\n\t"
11115 "ADD ESP,4\n\t"
11116 "CALL d2l_wrapper\n"
11117 "fast:" %}
11118 ins_encode %{
11119 Label fast;
11120 __ subptr(rsp, 8);
11121 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11122 __ fld_s(Address(rsp, 0));
11123 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11124 __ fistp_d(Address(rsp, 0));
11125 // Restore the rounding mode, mask the exception
11126 if (Compile::current()->in_24_bit_fp_mode()) {
11127 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11128 } else {
11129 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11130 }
11131 // Load the converted long, adjust CPU stack
11132 __ pop(rax);
11133 __ pop(rdx);
11134 __ cmpl(rdx, 0x80000000);
11135 __ jccb(Assembler::notEqual, fast);
11136 __ testl(rax, rax);
11137 __ jccb(Assembler::notEqual, fast);
11138 __ subptr(rsp, 4);
11139 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11140 __ fld_s(Address(rsp, 0));
11141 __ addptr(rsp, 4);
11142 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11143 __ bind(fast);
11144 %}
11145 ins_pipe( pipe_slow );
11146 %}
11147
11148 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11149 predicate( UseSSE<=1 );
11150 match(Set dst (ConvI2D src));
11151 format %{ "FILD $src\n\t"
11152 "FSTP $dst" %}
11153 opcode(0xDB, 0x0); /* DB /0 */
11154 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11155 ins_pipe( fpu_reg_mem );
11156 %}
11157
11158 instruct convI2D_reg(regD dst, rRegI src) %{
11159 predicate( UseSSE>=2 && !UseXmmI2D );
11160 match(Set dst (ConvI2D src));
11161 format %{ "CVTSI2SD $dst,$src" %}
11162 ins_encode %{
11163 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11164 %}
11165 ins_pipe( pipe_slow );
11166 %}
11167
11168 instruct convI2D_mem(regD dst, memory mem) %{
11169 predicate( UseSSE>=2 );
11170 match(Set dst (ConvI2D (LoadI mem)));
11171 format %{ "CVTSI2SD $dst,$mem" %}
11172 ins_encode %{
11173 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11174 %}
11175 ins_pipe( pipe_slow );
11176 %}
11177
11178 instruct convXI2D_reg(regD dst, rRegI src)
11179 %{
11180 predicate( UseSSE>=2 && UseXmmI2D );
11181 match(Set dst (ConvI2D src));
11182
11183 format %{ "MOVD $dst,$src\n\t"
11184 "CVTDQ2PD $dst,$dst\t# i2d" %}
11185 ins_encode %{
11186 __ movdl($dst$$XMMRegister, $src$$Register);
11187 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11188 %}
11189 ins_pipe(pipe_slow); // XXX
11190 %}
11191
11192 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11193 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11194 match(Set dst (ConvI2D (LoadI mem)));
11195 format %{ "FILD $mem\n\t"
11196 "FSTP $dst" %}
11197 opcode(0xDB); /* DB /0 */
11198 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11199 Pop_Reg_DPR(dst));
11200 ins_pipe( fpu_reg_mem );
11201 %}
11202
11203 // Convert a byte to a float; no rounding step needed.
11204 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11205 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11206 match(Set dst (ConvI2F src));
11207 format %{ "FILD $src\n\t"
11208 "FSTP $dst" %}
11209
11210 opcode(0xDB, 0x0); /* DB /0 */
11211 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11212 ins_pipe( fpu_reg_mem );
11213 %}
11214
11215 // In 24-bit mode, force exponent rounding by storing back out
11216 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11217 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11218 match(Set dst (ConvI2F src));
11219 ins_cost(200);
11220 format %{ "FILD $src\n\t"
11221 "FSTP_S $dst" %}
11222 opcode(0xDB, 0x0); /* DB /0 */
11223 ins_encode( Push_Mem_I(src),
11224 Pop_Mem_FPR(dst));
11225 ins_pipe( fpu_mem_mem );
11226 %}
11227
11228 // In 24-bit mode, force exponent rounding by storing back out
11229 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11230 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11231 match(Set dst (ConvI2F (LoadI mem)));
11232 ins_cost(200);
11233 format %{ "FILD $mem\n\t"
11234 "FSTP_S $dst" %}
11235 opcode(0xDB); /* DB /0 */
11236 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11237 Pop_Mem_FPR(dst));
11238 ins_pipe( fpu_mem_mem );
11239 %}
11240
11241 // This instruction does not round to 24-bits
11242 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11243 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11244 match(Set dst (ConvI2F src));
11245 format %{ "FILD $src\n\t"
11246 "FSTP $dst" %}
11247 opcode(0xDB, 0x0); /* DB /0 */
11248 ins_encode( Push_Mem_I(src),
11249 Pop_Reg_FPR(dst));
11250 ins_pipe( fpu_reg_mem );
11251 %}
11252
11253 // This instruction does not round to 24-bits
11254 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11255 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11256 match(Set dst (ConvI2F (LoadI mem)));
11257 format %{ "FILD $mem\n\t"
11258 "FSTP $dst" %}
11259 opcode(0xDB); /* DB /0 */
11260 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11261 Pop_Reg_FPR(dst));
11262 ins_pipe( fpu_reg_mem );
11263 %}
11264
11265 // Convert an int to a float in xmm; no rounding step needed.
11266 instruct convI2F_reg(regF dst, rRegI src) %{
11267 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11268 match(Set dst (ConvI2F src));
11269 format %{ "CVTSI2SS $dst, $src" %}
11270 ins_encode %{
11271 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11272 %}
11273 ins_pipe( pipe_slow );
11274 %}
11275
11276 instruct convXI2F_reg(regF dst, rRegI src)
11277 %{
11278 predicate( UseSSE>=2 && UseXmmI2F );
11279 match(Set dst (ConvI2F src));
11280
11281 format %{ "MOVD $dst,$src\n\t"
11282 "CVTDQ2PS $dst,$dst\t# i2f" %}
11283 ins_encode %{
11284 __ movdl($dst$$XMMRegister, $src$$Register);
11285 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11286 %}
11287 ins_pipe(pipe_slow); // XXX
11288 %}
11289
11290 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11291 match(Set dst (ConvI2L src));
11292 effect(KILL cr);
11293 ins_cost(375);
11294 format %{ "MOV $dst.lo,$src\n\t"
11295 "MOV $dst.hi,$src\n\t"
11296 "SAR $dst.hi,31" %}
11297 ins_encode(convert_int_long(dst,src));
11298 ins_pipe( ialu_reg_reg_long );
11299 %}
11300
11301 // Zero-extend convert int to long
11302 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11303 match(Set dst (AndL (ConvI2L src) mask) );
11304 effect( KILL flags );
11305 ins_cost(250);
11306 format %{ "MOV $dst.lo,$src\n\t"
11307 "XOR $dst.hi,$dst.hi" %}
11308 opcode(0x33); // XOR
11309 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11310 ins_pipe( ialu_reg_reg_long );
11311 %}
11312
11313 // Zero-extend long
11314 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11315 match(Set dst (AndL src mask) );
11316 effect( KILL flags );
11317 ins_cost(250);
11318 format %{ "MOV $dst.lo,$src.lo\n\t"
11319 "XOR $dst.hi,$dst.hi\n\t" %}
11320 opcode(0x33); // XOR
11321 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11322 ins_pipe( ialu_reg_reg_long );
11323 %}
11324
11325 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11326 predicate (UseSSE<=1);
11327 match(Set dst (ConvL2D src));
11328 effect( KILL cr );
11329 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11330 "PUSH $src.lo\n\t"
11331 "FILD ST,[ESP + #0]\n\t"
11332 "ADD ESP,8\n\t"
11333 "FSTP_D $dst\t# D-round" %}
11334 opcode(0xDF, 0x5); /* DF /5 */
11335 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11336 ins_pipe( pipe_slow );
11337 %}
11338
11339 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11340 predicate (UseSSE>=2);
11341 match(Set dst (ConvL2D src));
11342 effect( KILL cr );
11343 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11344 "PUSH $src.lo\n\t"
11345 "FILD_D [ESP]\n\t"
11346 "FSTP_D [ESP]\n\t"
11347 "MOVSD $dst,[ESP]\n\t"
11348 "ADD ESP,8" %}
11349 opcode(0xDF, 0x5); /* DF /5 */
11350 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11351 ins_pipe( pipe_slow );
11352 %}
11353
11354 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11355 predicate (UseSSE>=1);
11356 match(Set dst (ConvL2F src));
11357 effect( KILL cr );
11358 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11359 "PUSH $src.lo\n\t"
11360 "FILD_D [ESP]\n\t"
11361 "FSTP_S [ESP]\n\t"
11362 "MOVSS $dst,[ESP]\n\t"
11363 "ADD ESP,8" %}
11364 opcode(0xDF, 0x5); /* DF /5 */
11365 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11366 ins_pipe( pipe_slow );
11367 %}
11368
11369 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11370 match(Set dst (ConvL2F src));
11371 effect( KILL cr );
11372 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11373 "PUSH $src.lo\n\t"
11374 "FILD ST,[ESP + #0]\n\t"
11375 "ADD ESP,8\n\t"
11376 "FSTP_S $dst\t# F-round" %}
11377 opcode(0xDF, 0x5); /* DF /5 */
11378 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11379 ins_pipe( pipe_slow );
11380 %}
11381
11382 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11383 match(Set dst (ConvL2I src));
11384 effect( DEF dst, USE src );
11385 format %{ "MOV $dst,$src.lo" %}
11386 ins_encode(enc_CopyL_Lo(dst,src));
11387 ins_pipe( ialu_reg_reg );
11388 %}
11389
11390
11391 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11392 match(Set dst (MoveF2I src));
11393 effect( DEF dst, USE src );
11394 ins_cost(100);
11395 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11396 ins_encode %{
11397 __ movl($dst$$Register, Address(rsp, $src$$disp));
11398 %}
11399 ins_pipe( ialu_reg_mem );
11400 %}
11401
11402 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11403 predicate(UseSSE==0);
11404 match(Set dst (MoveF2I src));
11405 effect( DEF dst, USE src );
11406
11407 ins_cost(125);
11408 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11409 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11410 ins_pipe( fpu_mem_reg );
11411 %}
11412
11413 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11414 predicate(UseSSE>=1);
11415 match(Set dst (MoveF2I src));
11416 effect( DEF dst, USE src );
11417
11418 ins_cost(95);
11419 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11420 ins_encode %{
11421 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11422 %}
11423 ins_pipe( pipe_slow );
11424 %}
11425
11426 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11427 predicate(UseSSE>=2);
11428 match(Set dst (MoveF2I src));
11429 effect( DEF dst, USE src );
11430 ins_cost(85);
11431 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11432 ins_encode %{
11433 __ movdl($dst$$Register, $src$$XMMRegister);
11434 %}
11435 ins_pipe( pipe_slow );
11436 %}
11437
11438 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11439 match(Set dst (MoveI2F src));
11440 effect( DEF dst, USE src );
11441
11442 ins_cost(100);
11443 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11444 ins_encode %{
11445 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11446 %}
11447 ins_pipe( ialu_mem_reg );
11448 %}
11449
11450
11451 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11452 predicate(UseSSE==0);
11453 match(Set dst (MoveI2F src));
11454 effect(DEF dst, USE src);
11455
11456 ins_cost(125);
11457 format %{ "FLD_S $src\n\t"
11458 "FSTP $dst\t# MoveI2F_stack_reg" %}
11459 opcode(0xD9); /* D9 /0, FLD m32real */
11460 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11461 Pop_Reg_FPR(dst) );
11462 ins_pipe( fpu_reg_mem );
11463 %}
11464
11465 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11466 predicate(UseSSE>=1);
11467 match(Set dst (MoveI2F src));
11468 effect( DEF dst, USE src );
11469
11470 ins_cost(95);
11471 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11472 ins_encode %{
11473 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11474 %}
11475 ins_pipe( pipe_slow );
11476 %}
11477
11478 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11479 predicate(UseSSE>=2);
11480 match(Set dst (MoveI2F src));
11481 effect( DEF dst, USE src );
11482
11483 ins_cost(85);
11484 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11485 ins_encode %{
11486 __ movdl($dst$$XMMRegister, $src$$Register);
11487 %}
11488 ins_pipe( pipe_slow );
11489 %}
11490
11491 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11492 match(Set dst (MoveD2L src));
11493 effect(DEF dst, USE src);
11494
11495 ins_cost(250);
11496 format %{ "MOV $dst.lo,$src\n\t"
11497 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11498 opcode(0x8B, 0x8B);
11499 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11500 ins_pipe( ialu_mem_long_reg );
11501 %}
11502
11503 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11504 predicate(UseSSE<=1);
11505 match(Set dst (MoveD2L src));
11506 effect(DEF dst, USE src);
11507
11508 ins_cost(125);
11509 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11510 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11511 ins_pipe( fpu_mem_reg );
11512 %}
11513
11514 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11515 predicate(UseSSE>=2);
11516 match(Set dst (MoveD2L src));
11517 effect(DEF dst, USE src);
11518 ins_cost(95);
11519 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11520 ins_encode %{
11521 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11522 %}
11523 ins_pipe( pipe_slow );
11524 %}
11525
11526 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11527 predicate(UseSSE>=2);
11528 match(Set dst (MoveD2L src));
11529 effect(DEF dst, USE src, TEMP tmp);
11530 ins_cost(85);
11531 format %{ "MOVD $dst.lo,$src\n\t"
11532 "PSHUFLW $tmp,$src,0x4E\n\t"
11533 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11534 ins_encode %{
11535 __ movdl($dst$$Register, $src$$XMMRegister);
11536 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11537 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11538 %}
11539 ins_pipe( pipe_slow );
11540 %}
11541
11542 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11543 match(Set dst (MoveL2D src));
11544 effect(DEF dst, USE src);
11545
11546 ins_cost(200);
11547 format %{ "MOV $dst,$src.lo\n\t"
11548 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11549 opcode(0x89, 0x89);
11550 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11551 ins_pipe( ialu_mem_long_reg );
11552 %}
11553
11554
11555 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11556 predicate(UseSSE<=1);
11557 match(Set dst (MoveL2D src));
11558 effect(DEF dst, USE src);
11559 ins_cost(125);
11560
11561 format %{ "FLD_D $src\n\t"
11562 "FSTP $dst\t# MoveL2D_stack_reg" %}
11563 opcode(0xDD); /* DD /0, FLD m64real */
11564 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11565 Pop_Reg_DPR(dst) );
11566 ins_pipe( fpu_reg_mem );
11567 %}
11568
11569
11570 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11571 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11572 match(Set dst (MoveL2D src));
11573 effect(DEF dst, USE src);
11574
11575 ins_cost(95);
11576 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11577 ins_encode %{
11578 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11579 %}
11580 ins_pipe( pipe_slow );
11581 %}
11582
11583 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11584 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11585 match(Set dst (MoveL2D src));
11586 effect(DEF dst, USE src);
11587
11588 ins_cost(95);
11589 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11590 ins_encode %{
11591 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11592 %}
11593 ins_pipe( pipe_slow );
11594 %}
11595
11596 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11597 predicate(UseSSE>=2);
11598 match(Set dst (MoveL2D src));
11599 effect(TEMP dst, USE src, TEMP tmp);
11600 ins_cost(85);
11601 format %{ "MOVD $dst,$src.lo\n\t"
11602 "MOVD $tmp,$src.hi\n\t"
11603 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11604 ins_encode %{
11605 __ movdl($dst$$XMMRegister, $src$$Register);
11606 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11607 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11608 %}
11609 ins_pipe( pipe_slow );
11610 %}
11611
11612
11613 // =======================================================================
11614 // fast clearing of an array
11615 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11616 predicate(!UseFastStosb);
11617 match(Set dummy (ClearArray cnt base));
11618 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11619 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11620 "SHL ECX,1\t# Convert doublewords to words\n\t"
11621 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11622 ins_encode %{
11623 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11624 %}
11625 ins_pipe( pipe_slow );
11626 %}
11627
11628 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11629 predicate(UseFastStosb);
11630 match(Set dummy (ClearArray cnt base));
11631 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11632 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11633 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11634 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11635 ins_encode %{
11636 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11637 %}
11638 ins_pipe( pipe_slow );
11639 %}
11640
11641 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11642 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11643 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11644 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11645
11646 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11647 ins_encode %{
11648 __ string_compare($str1$$Register, $str2$$Register,
11649 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11650 $tmp1$$XMMRegister);
11651 %}
11652 ins_pipe( pipe_slow );
11653 %}
11654
11655 // fast string equals
11656 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11657 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11658 match(Set result (StrEquals (Binary str1 str2) cnt));
11659 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11660
11661 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11662 ins_encode %{
11663 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11664 $cnt$$Register, $result$$Register, $tmp3$$Register,
11665 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11666 %}
11667 ins_pipe( pipe_slow );
11668 %}
11669
11670 // fast search of substring with known size.
11671 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11672 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11673 predicate(UseSSE42Intrinsics);
11674 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11675 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11676
11677 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11678 ins_encode %{
11679 int icnt2 = (int)$int_cnt2$$constant;
11680 if (icnt2 >= 8) {
11681 // IndexOf for constant substrings with size >= 8 elements
11682 // which don't need to be loaded through stack.
11683 __ string_indexofC8($str1$$Register, $str2$$Register,
11684 $cnt1$$Register, $cnt2$$Register,
11685 icnt2, $result$$Register,
11686 $vec$$XMMRegister, $tmp$$Register);
11687 } else {
11688 // Small strings are loaded through stack if they cross page boundary.
11689 __ string_indexof($str1$$Register, $str2$$Register,
11690 $cnt1$$Register, $cnt2$$Register,
11691 icnt2, $result$$Register,
11692 $vec$$XMMRegister, $tmp$$Register);
11693 }
11694 %}
11695 ins_pipe( pipe_slow );
11696 %}
11697
11698 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11699 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11700 predicate(UseSSE42Intrinsics);
11701 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11702 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11703
11704 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11705 ins_encode %{
11706 __ string_indexof($str1$$Register, $str2$$Register,
11707 $cnt1$$Register, $cnt2$$Register,
11708 (-1), $result$$Register,
11709 $vec$$XMMRegister, $tmp$$Register);
11710 %}
11711 ins_pipe( pipe_slow );
11712 %}
11713
11714 // fast array equals
11715 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11716 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11717 %{
11718 match(Set result (AryEq ary1 ary2));
11719 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11720 //ins_cost(300);
11721
11722 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11723 ins_encode %{
11724 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11725 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11726 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11727 %}
11728 ins_pipe( pipe_slow );
11729 %}
11730
11731 // encode char[] to byte[] in ISO_8859_1
11732 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11733 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11734 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11735 match(Set result (EncodeISOArray src (Binary dst len)));
11736 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11737
11738 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11739 ins_encode %{
11740 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11741 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11742 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11743 %}
11744 ins_pipe( pipe_slow );
11745 %}
11746
11747
11748 //----------Control Flow Instructions------------------------------------------
11749 // Signed compare Instructions
11750 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11751 match(Set cr (CmpI op1 op2));
11752 effect( DEF cr, USE op1, USE op2 );
11753 format %{ "CMP $op1,$op2" %}
11754 opcode(0x3B); /* Opcode 3B /r */
11755 ins_encode( OpcP, RegReg( op1, op2) );
11756 ins_pipe( ialu_cr_reg_reg );
11757 %}
11758
11759 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11760 match(Set cr (CmpI op1 op2));
11761 effect( DEF cr, USE op1 );
11762 format %{ "CMP $op1,$op2" %}
11763 opcode(0x81,0x07); /* Opcode 81 /7 */
11764 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11765 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11766 ins_pipe( ialu_cr_reg_imm );
11767 %}
11768
11769 // Cisc-spilled version of cmpI_eReg
11770 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11771 match(Set cr (CmpI op1 (LoadI op2)));
11772
11773 format %{ "CMP $op1,$op2" %}
11774 ins_cost(500);
11775 opcode(0x3B); /* Opcode 3B /r */
11776 ins_encode( OpcP, RegMem( op1, op2) );
11777 ins_pipe( ialu_cr_reg_mem );
11778 %}
11779
11780 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11781 match(Set cr (CmpI src zero));
11782 effect( DEF cr, USE src );
11783
11784 format %{ "TEST $src,$src" %}
11785 opcode(0x85);
11786 ins_encode( OpcP, RegReg( src, src ) );
11787 ins_pipe( ialu_cr_reg_imm );
11788 %}
11789
11790 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11791 match(Set cr (CmpI (AndI src con) zero));
11792
11793 format %{ "TEST $src,$con" %}
11794 opcode(0xF7,0x00);
11795 ins_encode( OpcP, RegOpc(src), Con32(con) );
11796 ins_pipe( ialu_cr_reg_imm );
11797 %}
11798
11799 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11800 match(Set cr (CmpI (AndI src mem) zero));
11801
11802 format %{ "TEST $src,$mem" %}
11803 opcode(0x85);
11804 ins_encode( OpcP, RegMem( src, mem ) );
11805 ins_pipe( ialu_cr_reg_mem );
11806 %}
11807
11808 // Unsigned compare Instructions; really, same as signed except they
11809 // produce an eFlagsRegU instead of eFlagsReg.
11810 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11811 match(Set cr (CmpU op1 op2));
11812
11813 format %{ "CMPu $op1,$op2" %}
11814 opcode(0x3B); /* Opcode 3B /r */
11815 ins_encode( OpcP, RegReg( op1, op2) );
11816 ins_pipe( ialu_cr_reg_reg );
11817 %}
11818
11819 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11820 match(Set cr (CmpU op1 op2));
11821
11822 format %{ "CMPu $op1,$op2" %}
11823 opcode(0x81,0x07); /* Opcode 81 /7 */
11824 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11825 ins_pipe( ialu_cr_reg_imm );
11826 %}
11827
11828 // // Cisc-spilled version of cmpU_eReg
11829 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11830 match(Set cr (CmpU op1 (LoadI op2)));
11831
11832 format %{ "CMPu $op1,$op2" %}
11833 ins_cost(500);
11834 opcode(0x3B); /* Opcode 3B /r */
11835 ins_encode( OpcP, RegMem( op1, op2) );
11836 ins_pipe( ialu_cr_reg_mem );
11837 %}
11838
11839 // // Cisc-spilled version of cmpU_eReg
11840 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11841 // match(Set cr (CmpU (LoadI op1) op2));
11842 //
11843 // format %{ "CMPu $op1,$op2" %}
11844 // ins_cost(500);
11845 // opcode(0x39); /* Opcode 39 /r */
11846 // ins_encode( OpcP, RegMem( op1, op2) );
11847 //%}
11848
11849 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11850 match(Set cr (CmpU src zero));
11851
11852 format %{ "TESTu $src,$src" %}
11853 opcode(0x85);
11854 ins_encode( OpcP, RegReg( src, src ) );
11855 ins_pipe( ialu_cr_reg_imm );
11856 %}
11857
11858 // Unsigned pointer compare Instructions
11859 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11860 match(Set cr (CmpP op1 op2));
11861
11862 format %{ "CMPu $op1,$op2" %}
11863 opcode(0x3B); /* Opcode 3B /r */
11864 ins_encode( OpcP, RegReg( op1, op2) );
11865 ins_pipe( ialu_cr_reg_reg );
11866 %}
11867
11868 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11869 match(Set cr (CmpP op1 op2));
11870
11871 format %{ "CMPu $op1,$op2" %}
11872 opcode(0x81,0x07); /* Opcode 81 /7 */
11873 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11874 ins_pipe( ialu_cr_reg_imm );
11875 %}
11876
11877 // // Cisc-spilled version of cmpP_eReg
11878 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11879 match(Set cr (CmpP op1 (LoadP op2)));
11880
11881 format %{ "CMPu $op1,$op2" %}
11882 ins_cost(500);
11883 opcode(0x3B); /* Opcode 3B /r */
11884 ins_encode( OpcP, RegMem( op1, op2) );
11885 ins_pipe( ialu_cr_reg_mem );
11886 %}
11887
11888 // // Cisc-spilled version of cmpP_eReg
11889 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11890 // match(Set cr (CmpP (LoadP op1) op2));
11891 //
11892 // format %{ "CMPu $op1,$op2" %}
11893 // ins_cost(500);
11894 // opcode(0x39); /* Opcode 39 /r */
11895 // ins_encode( OpcP, RegMem( op1, op2) );
11896 //%}
11897
11898 // Compare raw pointer (used in out-of-heap check).
11899 // Only works because non-oop pointers must be raw pointers
11900 // and raw pointers have no anti-dependencies.
11901 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11902 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11903 match(Set cr (CmpP op1 (LoadP op2)));
11904
11905 format %{ "CMPu $op1,$op2" %}
11906 opcode(0x3B); /* Opcode 3B /r */
11907 ins_encode( OpcP, RegMem( op1, op2) );
11908 ins_pipe( ialu_cr_reg_mem );
11909 %}
11910
11911 //
11912 // This will generate a signed flags result. This should be ok
11913 // since any compare to a zero should be eq/neq.
11914 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11915 match(Set cr (CmpP src zero));
11916
11917 format %{ "TEST $src,$src" %}
11918 opcode(0x85);
11919 ins_encode( OpcP, RegReg( src, src ) );
11920 ins_pipe( ialu_cr_reg_imm );
11921 %}
11922
11923 // Cisc-spilled version of testP_reg
11924 // This will generate a signed flags result. This should be ok
11925 // since any compare to a zero should be eq/neq.
11926 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11927 match(Set cr (CmpP (LoadP op) zero));
11928
11929 format %{ "TEST $op,0xFFFFFFFF" %}
11930 ins_cost(500);
11931 opcode(0xF7); /* Opcode F7 /0 */
11932 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11933 ins_pipe( ialu_cr_reg_imm );
11934 %}
11935
11936 // Yanked all unsigned pointer compare operations.
11937 // Pointer compares are done with CmpP which is already unsigned.
11938
11939 //----------Max and Min--------------------------------------------------------
11940 // Min Instructions
11941 ////
11942 // *** Min and Max using the conditional move are slower than the
11943 // *** branch version on a Pentium III.
11944 // // Conditional move for min
11945 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11946 // effect( USE_DEF op2, USE op1, USE cr );
11947 // format %{ "CMOVlt $op2,$op1\t! min" %}
11948 // opcode(0x4C,0x0F);
11949 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11950 // ins_pipe( pipe_cmov_reg );
11951 //%}
11952 //
11953 //// Min Register with Register (P6 version)
11954 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11955 // predicate(VM_Version::supports_cmov() );
11956 // match(Set op2 (MinI op1 op2));
11957 // ins_cost(200);
11958 // expand %{
11959 // eFlagsReg cr;
11960 // compI_eReg(cr,op1,op2);
11961 // cmovI_reg_lt(op2,op1,cr);
11962 // %}
11963 //%}
11964
11965 // Min Register with Register (generic version)
11966 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11967 match(Set dst (MinI dst src));
11968 effect(KILL flags);
11969 ins_cost(300);
11970
11971 format %{ "MIN $dst,$src" %}
11972 opcode(0xCC);
11973 ins_encode( min_enc(dst,src) );
11974 ins_pipe( pipe_slow );
11975 %}
11976
11977 // Max Register with Register
11978 // *** Min and Max using the conditional move are slower than the
11979 // *** branch version on a Pentium III.
11980 // // Conditional move for max
11981 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11982 // effect( USE_DEF op2, USE op1, USE cr );
11983 // format %{ "CMOVgt $op2,$op1\t! max" %}
11984 // opcode(0x4F,0x0F);
11985 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11986 // ins_pipe( pipe_cmov_reg );
11987 //%}
11988 //
11989 // // Max Register with Register (P6 version)
11990 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11991 // predicate(VM_Version::supports_cmov() );
11992 // match(Set op2 (MaxI op1 op2));
11993 // ins_cost(200);
11994 // expand %{
11995 // eFlagsReg cr;
11996 // compI_eReg(cr,op1,op2);
11997 // cmovI_reg_gt(op2,op1,cr);
11998 // %}
11999 //%}
12000
12001 // Max Register with Register (generic version)
12002 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12003 match(Set dst (MaxI dst src));
12004 effect(KILL flags);
12005 ins_cost(300);
12006
12007 format %{ "MAX $dst,$src" %}
12008 opcode(0xCC);
12009 ins_encode( max_enc(dst,src) );
12010 ins_pipe( pipe_slow );
12011 %}
12012
12013 // ============================================================================
12014 // Counted Loop limit node which represents exact final iterator value.
12015 // Note: the resulting value should fit into integer range since
12016 // counted loops have limit check on overflow.
12017 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12018 match(Set limit (LoopLimit (Binary init limit) stride));
12019 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12020 ins_cost(300);
12021
12022 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12023 ins_encode %{
12024 int strd = (int)$stride$$constant;
12025 assert(strd != 1 && strd != -1, "sanity");
12026 int m1 = (strd > 0) ? 1 : -1;
12027 // Convert limit to long (EAX:EDX)
12028 __ cdql();
12029 // Convert init to long (init:tmp)
12030 __ movl($tmp$$Register, $init$$Register);
12031 __ sarl($tmp$$Register, 31);
12032 // $limit - $init
12033 __ subl($limit$$Register, $init$$Register);
12034 __ sbbl($limit_hi$$Register, $tmp$$Register);
12035 // + ($stride - 1)
12036 if (strd > 0) {
12037 __ addl($limit$$Register, (strd - 1));
12038 __ adcl($limit_hi$$Register, 0);
12039 __ movl($tmp$$Register, strd);
12040 } else {
12041 __ addl($limit$$Register, (strd + 1));
12042 __ adcl($limit_hi$$Register, -1);
12043 __ lneg($limit_hi$$Register, $limit$$Register);
12044 __ movl($tmp$$Register, -strd);
12045 }
12046 // signed devision: (EAX:EDX) / pos_stride
12047 __ idivl($tmp$$Register);
12048 if (strd < 0) {
12049 // restore sign
12050 __ negl($tmp$$Register);
12051 }
12052 // (EAX) * stride
12053 __ mull($tmp$$Register);
12054 // + init (ignore upper bits)
12055 __ addl($limit$$Register, $init$$Register);
12056 %}
12057 ins_pipe( pipe_slow );
12058 %}
12059
12060 // ============================================================================
12061 // Branch Instructions
12062 // Jump Table
12063 instruct jumpXtnd(rRegI switch_val) %{
12064 match(Jump switch_val);
12065 ins_cost(350);
12066 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12067 ins_encode %{
12068 // Jump to Address(table_base + switch_reg)
12069 Address index(noreg, $switch_val$$Register, Address::times_1);
12070 __ jump(ArrayAddress($constantaddress, index));
12071 %}
12072 ins_pipe(pipe_jmp);
12073 %}
12074
12075 // Jump Direct - Label defines a relative address from JMP+1
12076 instruct jmpDir(label labl) %{
12077 match(Goto);
12078 effect(USE labl);
12079
12080 ins_cost(300);
12081 format %{ "JMP $labl" %}
12082 size(5);
12083 ins_encode %{
12084 Label* L = $labl$$label;
12085 __ jmp(*L, false); // Always long jump
12086 %}
12087 ins_pipe( pipe_jmp );
12088 %}
12089
12090 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12091 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12092 match(If cop cr);
12093 effect(USE labl);
12094
12095 ins_cost(300);
12096 format %{ "J$cop $labl" %}
12097 size(6);
12098 ins_encode %{
12099 Label* L = $labl$$label;
12100 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12101 %}
12102 ins_pipe( pipe_jcc );
12103 %}
12104
12105 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12106 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12107 match(CountedLoopEnd cop cr);
12108 effect(USE labl);
12109
12110 ins_cost(300);
12111 format %{ "J$cop $labl\t# Loop end" %}
12112 size(6);
12113 ins_encode %{
12114 Label* L = $labl$$label;
12115 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12116 %}
12117 ins_pipe( pipe_jcc );
12118 %}
12119
12120 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12121 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12122 match(CountedLoopEnd cop cmp);
12123 effect(USE labl);
12124
12125 ins_cost(300);
12126 format %{ "J$cop,u $labl\t# Loop end" %}
12127 size(6);
12128 ins_encode %{
12129 Label* L = $labl$$label;
12130 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12131 %}
12132 ins_pipe( pipe_jcc );
12133 %}
12134
12135 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12136 match(CountedLoopEnd cop cmp);
12137 effect(USE labl);
12138
12139 ins_cost(200);
12140 format %{ "J$cop,u $labl\t# Loop end" %}
12141 size(6);
12142 ins_encode %{
12143 Label* L = $labl$$label;
12144 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12145 %}
12146 ins_pipe( pipe_jcc );
12147 %}
12148
12149 // Jump Direct Conditional - using unsigned comparison
12150 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12151 match(If cop cmp);
12152 effect(USE labl);
12153
12154 ins_cost(300);
12155 format %{ "J$cop,u $labl" %}
12156 size(6);
12157 ins_encode %{
12158 Label* L = $labl$$label;
12159 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12160 %}
12161 ins_pipe(pipe_jcc);
12162 %}
12163
12164 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12165 match(If cop cmp);
12166 effect(USE labl);
12167
12168 ins_cost(200);
12169 format %{ "J$cop,u $labl" %}
12170 size(6);
12171 ins_encode %{
12172 Label* L = $labl$$label;
12173 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12174 %}
12175 ins_pipe(pipe_jcc);
12176 %}
12177
12178 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12179 match(If cop cmp);
12180 effect(USE labl);
12181
12182 ins_cost(200);
12183 format %{ $$template
12184 if ($cop$$cmpcode == Assembler::notEqual) {
12185 $$emit$$"JP,u $labl\n\t"
12186 $$emit$$"J$cop,u $labl"
12187 } else {
12188 $$emit$$"JP,u done\n\t"
12189 $$emit$$"J$cop,u $labl\n\t"
12190 $$emit$$"done:"
12191 }
12192 %}
12193 ins_encode %{
12194 Label* l = $labl$$label;
12195 if ($cop$$cmpcode == Assembler::notEqual) {
12196 __ jcc(Assembler::parity, *l, false);
12197 __ jcc(Assembler::notEqual, *l, false);
12198 } else if ($cop$$cmpcode == Assembler::equal) {
12199 Label done;
12200 __ jccb(Assembler::parity, done);
12201 __ jcc(Assembler::equal, *l, false);
12202 __ bind(done);
12203 } else {
12204 ShouldNotReachHere();
12205 }
12206 %}
12207 ins_pipe(pipe_jcc);
12208 %}
12209
12210 // ============================================================================
12211 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12212 // array for an instance of the superklass. Set a hidden internal cache on a
12213 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12214 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12215 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12216 match(Set result (PartialSubtypeCheck sub super));
12217 effect( KILL rcx, KILL cr );
12218
12219 ins_cost(1100); // slightly larger than the next version
12220 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12221 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12222 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12223 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12224 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12225 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12226 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12227 "miss:\t" %}
12228
12229 opcode(0x1); // Force a XOR of EDI
12230 ins_encode( enc_PartialSubtypeCheck() );
12231 ins_pipe( pipe_slow );
12232 %}
12233
12234 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12235 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12236 effect( KILL rcx, KILL result );
12237
12238 ins_cost(1000);
12239 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12240 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12241 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12242 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12243 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12244 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12245 "miss:\t" %}
12246
12247 opcode(0x0); // No need to XOR EDI
12248 ins_encode( enc_PartialSubtypeCheck() );
12249 ins_pipe( pipe_slow );
12250 %}
12251
12252 // ============================================================================
12253 // Branch Instructions -- short offset versions
12254 //
12255 // These instructions are used to replace jumps of a long offset (the default
12256 // match) with jumps of a shorter offset. These instructions are all tagged
12257 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12258 // match rules in general matching. Instead, the ADLC generates a conversion
12259 // method in the MachNode which can be used to do in-place replacement of the
12260 // long variant with the shorter variant. The compiler will determine if a
12261 // branch can be taken by the is_short_branch_offset() predicate in the machine
12262 // specific code section of the file.
12263
12264 // Jump Direct - Label defines a relative address from JMP+1
12265 instruct jmpDir_short(label labl) %{
12266 match(Goto);
12267 effect(USE labl);
12268
12269 ins_cost(300);
12270 format %{ "JMP,s $labl" %}
12271 size(2);
12272 ins_encode %{
12273 Label* L = $labl$$label;
12274 __ jmpb(*L);
12275 %}
12276 ins_pipe( pipe_jmp );
12277 ins_short_branch(1);
12278 %}
12279
12280 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12281 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12282 match(If cop cr);
12283 effect(USE labl);
12284
12285 ins_cost(300);
12286 format %{ "J$cop,s $labl" %}
12287 size(2);
12288 ins_encode %{
12289 Label* L = $labl$$label;
12290 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12291 %}
12292 ins_pipe( pipe_jcc );
12293 ins_short_branch(1);
12294 %}
12295
12296 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12297 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12298 match(CountedLoopEnd cop cr);
12299 effect(USE labl);
12300
12301 ins_cost(300);
12302 format %{ "J$cop,s $labl\t# Loop end" %}
12303 size(2);
12304 ins_encode %{
12305 Label* L = $labl$$label;
12306 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12307 %}
12308 ins_pipe( pipe_jcc );
12309 ins_short_branch(1);
12310 %}
12311
12312 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12313 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12314 match(CountedLoopEnd cop cmp);
12315 effect(USE labl);
12316
12317 ins_cost(300);
12318 format %{ "J$cop,us $labl\t# Loop end" %}
12319 size(2);
12320 ins_encode %{
12321 Label* L = $labl$$label;
12322 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12323 %}
12324 ins_pipe( pipe_jcc );
12325 ins_short_branch(1);
12326 %}
12327
12328 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12329 match(CountedLoopEnd cop cmp);
12330 effect(USE labl);
12331
12332 ins_cost(300);
12333 format %{ "J$cop,us $labl\t# Loop end" %}
12334 size(2);
12335 ins_encode %{
12336 Label* L = $labl$$label;
12337 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12338 %}
12339 ins_pipe( pipe_jcc );
12340 ins_short_branch(1);
12341 %}
12342
12343 // Jump Direct Conditional - using unsigned comparison
12344 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12345 match(If cop cmp);
12346 effect(USE labl);
12347
12348 ins_cost(300);
12349 format %{ "J$cop,us $labl" %}
12350 size(2);
12351 ins_encode %{
12352 Label* L = $labl$$label;
12353 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12354 %}
12355 ins_pipe( pipe_jcc );
12356 ins_short_branch(1);
12357 %}
12358
12359 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12360 match(If cop cmp);
12361 effect(USE labl);
12362
12363 ins_cost(300);
12364 format %{ "J$cop,us $labl" %}
12365 size(2);
12366 ins_encode %{
12367 Label* L = $labl$$label;
12368 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12369 %}
12370 ins_pipe( pipe_jcc );
12371 ins_short_branch(1);
12372 %}
12373
12374 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12375 match(If cop cmp);
12376 effect(USE labl);
12377
12378 ins_cost(300);
12379 format %{ $$template
12380 if ($cop$$cmpcode == Assembler::notEqual) {
12381 $$emit$$"JP,u,s $labl\n\t"
12382 $$emit$$"J$cop,u,s $labl"
12383 } else {
12384 $$emit$$"JP,u,s done\n\t"
12385 $$emit$$"J$cop,u,s $labl\n\t"
12386 $$emit$$"done:"
12387 }
12388 %}
12389 size(4);
12390 ins_encode %{
12391 Label* l = $labl$$label;
12392 if ($cop$$cmpcode == Assembler::notEqual) {
12393 __ jccb(Assembler::parity, *l);
12394 __ jccb(Assembler::notEqual, *l);
12395 } else if ($cop$$cmpcode == Assembler::equal) {
12396 Label done;
12397 __ jccb(Assembler::parity, done);
12398 __ jccb(Assembler::equal, *l);
12399 __ bind(done);
12400 } else {
12401 ShouldNotReachHere();
12402 }
12403 %}
12404 ins_pipe(pipe_jcc);
12405 ins_short_branch(1);
12406 %}
12407
12408 // ============================================================================
12409 // Long Compare
12410 //
12411 // Currently we hold longs in 2 registers. Comparing such values efficiently
12412 // is tricky. The flavor of compare used depends on whether we are testing
12413 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12414 // The GE test is the negated LT test. The LE test can be had by commuting
12415 // the operands (yielding a GE test) and then negating; negate again for the
12416 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12417 // NE test is negated from that.
12418
12419 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12420 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12421 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12422 // are collapsed internally in the ADLC's dfa-gen code. The match for
12423 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12424 // foo match ends up with the wrong leaf. One fix is to not match both
12425 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12426 // both forms beat the trinary form of long-compare and both are very useful
12427 // on Intel which has so few registers.
12428
12429 // Manifest a CmpL result in an integer register. Very painful.
12430 // This is the test to avoid.
12431 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12432 match(Set dst (CmpL3 src1 src2));
12433 effect( KILL flags );
12434 ins_cost(1000);
12435 format %{ "XOR $dst,$dst\n\t"
12436 "CMP $src1.hi,$src2.hi\n\t"
12437 "JLT,s m_one\n\t"
12438 "JGT,s p_one\n\t"
12439 "CMP $src1.lo,$src2.lo\n\t"
12440 "JB,s m_one\n\t"
12441 "JEQ,s done\n"
12442 "p_one:\tINC $dst\n\t"
12443 "JMP,s done\n"
12444 "m_one:\tDEC $dst\n"
12445 "done:" %}
12446 ins_encode %{
12447 Label p_one, m_one, done;
12448 __ xorptr($dst$$Register, $dst$$Register);
12449 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12450 __ jccb(Assembler::less, m_one);
12451 __ jccb(Assembler::greater, p_one);
12452 __ cmpl($src1$$Register, $src2$$Register);
12453 __ jccb(Assembler::below, m_one);
12454 __ jccb(Assembler::equal, done);
12455 __ bind(p_one);
12456 __ incrementl($dst$$Register);
12457 __ jmpb(done);
12458 __ bind(m_one);
12459 __ decrementl($dst$$Register);
12460 __ bind(done);
12461 %}
12462 ins_pipe( pipe_slow );
12463 %}
12464
12465 //======
12466 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12467 // compares. Can be used for LE or GT compares by reversing arguments.
12468 // NOT GOOD FOR EQ/NE tests.
12469 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12470 match( Set flags (CmpL src zero ));
12471 ins_cost(100);
12472 format %{ "TEST $src.hi,$src.hi" %}
12473 opcode(0x85);
12474 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12475 ins_pipe( ialu_cr_reg_reg );
12476 %}
12477
12478 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12479 // compares. Can be used for LE or GT compares by reversing arguments.
12480 // NOT GOOD FOR EQ/NE tests.
12481 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12482 match( Set flags (CmpL src1 src2 ));
12483 effect( TEMP tmp );
12484 ins_cost(300);
12485 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12486 "MOV $tmp,$src1.hi\n\t"
12487 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12488 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12489 ins_pipe( ialu_cr_reg_reg );
12490 %}
12491
12492 // Long compares reg < zero/req OR reg >= zero/req.
12493 // Just a wrapper for a normal branch, plus the predicate test.
12494 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12495 match(If cmp flags);
12496 effect(USE labl);
12497 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12498 expand %{
12499 jmpCon(cmp,flags,labl); // JLT or JGE...
12500 %}
12501 %}
12502
12503 // Compare 2 longs and CMOVE longs.
12504 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12505 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12506 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12507 ins_cost(400);
12508 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12509 "CMOV$cmp $dst.hi,$src.hi" %}
12510 opcode(0x0F,0x40);
12511 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12512 ins_pipe( pipe_cmov_reg_long );
12513 %}
12514
12515 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12516 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12517 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12518 ins_cost(500);
12519 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12520 "CMOV$cmp $dst.hi,$src.hi" %}
12521 opcode(0x0F,0x40);
12522 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12523 ins_pipe( pipe_cmov_reg_long );
12524 %}
12525
12526 // Compare 2 longs and CMOVE ints.
12527 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12528 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12529 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12530 ins_cost(200);
12531 format %{ "CMOV$cmp $dst,$src" %}
12532 opcode(0x0F,0x40);
12533 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12534 ins_pipe( pipe_cmov_reg );
12535 %}
12536
12537 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12538 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12539 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12540 ins_cost(250);
12541 format %{ "CMOV$cmp $dst,$src" %}
12542 opcode(0x0F,0x40);
12543 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12544 ins_pipe( pipe_cmov_mem );
12545 %}
12546
12547 // Compare 2 longs and CMOVE ints.
12548 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12549 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12550 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12551 ins_cost(200);
12552 format %{ "CMOV$cmp $dst,$src" %}
12553 opcode(0x0F,0x40);
12554 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12555 ins_pipe( pipe_cmov_reg );
12556 %}
12557
12558 // Compare 2 longs and CMOVE doubles
12559 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12560 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12561 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12562 ins_cost(200);
12563 expand %{
12564 fcmovDPR_regS(cmp,flags,dst,src);
12565 %}
12566 %}
12567
12568 // Compare 2 longs and CMOVE doubles
12569 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12570 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12571 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12572 ins_cost(200);
12573 expand %{
12574 fcmovD_regS(cmp,flags,dst,src);
12575 %}
12576 %}
12577
12578 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12579 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12580 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12581 ins_cost(200);
12582 expand %{
12583 fcmovFPR_regS(cmp,flags,dst,src);
12584 %}
12585 %}
12586
12587 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12588 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12589 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12590 ins_cost(200);
12591 expand %{
12592 fcmovF_regS(cmp,flags,dst,src);
12593 %}
12594 %}
12595
12596 //======
12597 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12598 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12599 match( Set flags (CmpL src zero ));
12600 effect(TEMP tmp);
12601 ins_cost(200);
12602 format %{ "MOV $tmp,$src.lo\n\t"
12603 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12604 ins_encode( long_cmp_flags0( src, tmp ) );
12605 ins_pipe( ialu_reg_reg_long );
12606 %}
12607
12608 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12609 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12610 match( Set flags (CmpL src1 src2 ));
12611 ins_cost(200+300);
12612 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12613 "JNE,s skip\n\t"
12614 "CMP $src1.hi,$src2.hi\n\t"
12615 "skip:\t" %}
12616 ins_encode( long_cmp_flags1( src1, src2 ) );
12617 ins_pipe( ialu_cr_reg_reg );
12618 %}
12619
12620 // Long compare reg == zero/reg OR reg != zero/reg
12621 // Just a wrapper for a normal branch, plus the predicate test.
12622 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12623 match(If cmp flags);
12624 effect(USE labl);
12625 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12626 expand %{
12627 jmpCon(cmp,flags,labl); // JEQ or JNE...
12628 %}
12629 %}
12630
12631 // Compare 2 longs and CMOVE longs.
12632 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12633 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12634 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12635 ins_cost(400);
12636 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12637 "CMOV$cmp $dst.hi,$src.hi" %}
12638 opcode(0x0F,0x40);
12639 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12640 ins_pipe( pipe_cmov_reg_long );
12641 %}
12642
12643 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12644 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12645 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12646 ins_cost(500);
12647 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12648 "CMOV$cmp $dst.hi,$src.hi" %}
12649 opcode(0x0F,0x40);
12650 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12651 ins_pipe( pipe_cmov_reg_long );
12652 %}
12653
12654 // Compare 2 longs and CMOVE ints.
12655 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12657 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12658 ins_cost(200);
12659 format %{ "CMOV$cmp $dst,$src" %}
12660 opcode(0x0F,0x40);
12661 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12662 ins_pipe( pipe_cmov_reg );
12663 %}
12664
12665 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12666 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12667 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12668 ins_cost(250);
12669 format %{ "CMOV$cmp $dst,$src" %}
12670 opcode(0x0F,0x40);
12671 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12672 ins_pipe( pipe_cmov_mem );
12673 %}
12674
12675 // Compare 2 longs and CMOVE ints.
12676 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12677 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12678 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12679 ins_cost(200);
12680 format %{ "CMOV$cmp $dst,$src" %}
12681 opcode(0x0F,0x40);
12682 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12683 ins_pipe( pipe_cmov_reg );
12684 %}
12685
12686 // Compare 2 longs and CMOVE doubles
12687 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12688 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12689 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12690 ins_cost(200);
12691 expand %{
12692 fcmovDPR_regS(cmp,flags,dst,src);
12693 %}
12694 %}
12695
12696 // Compare 2 longs and CMOVE doubles
12697 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12698 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12699 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12700 ins_cost(200);
12701 expand %{
12702 fcmovD_regS(cmp,flags,dst,src);
12703 %}
12704 %}
12705
12706 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12707 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12708 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12709 ins_cost(200);
12710 expand %{
12711 fcmovFPR_regS(cmp,flags,dst,src);
12712 %}
12713 %}
12714
12715 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12716 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12717 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12718 ins_cost(200);
12719 expand %{
12720 fcmovF_regS(cmp,flags,dst,src);
12721 %}
12722 %}
12723
12724 //======
12725 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12726 // Same as cmpL_reg_flags_LEGT except must negate src
12727 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12728 match( Set flags (CmpL src zero ));
12729 effect( TEMP tmp );
12730 ins_cost(300);
12731 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12732 "CMP $tmp,$src.lo\n\t"
12733 "SBB $tmp,$src.hi\n\t" %}
12734 ins_encode( long_cmp_flags3(src, tmp) );
12735 ins_pipe( ialu_reg_reg_long );
12736 %}
12737
12738 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12739 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12740 // requires a commuted test to get the same result.
12741 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12742 match( Set flags (CmpL src1 src2 ));
12743 effect( TEMP tmp );
12744 ins_cost(300);
12745 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12746 "MOV $tmp,$src2.hi\n\t"
12747 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12748 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12749 ins_pipe( ialu_cr_reg_reg );
12750 %}
12751
12752 // Long compares reg < zero/req OR reg >= zero/req.
12753 // Just a wrapper for a normal branch, plus the predicate test
12754 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12755 match(If cmp flags);
12756 effect(USE labl);
12757 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12758 ins_cost(300);
12759 expand %{
12760 jmpCon(cmp,flags,labl); // JGT or JLE...
12761 %}
12762 %}
12763
12764 // Compare 2 longs and CMOVE longs.
12765 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12766 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12767 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12768 ins_cost(400);
12769 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12770 "CMOV$cmp $dst.hi,$src.hi" %}
12771 opcode(0x0F,0x40);
12772 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12773 ins_pipe( pipe_cmov_reg_long );
12774 %}
12775
12776 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12777 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12778 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12779 ins_cost(500);
12780 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12781 "CMOV$cmp $dst.hi,$src.hi+4" %}
12782 opcode(0x0F,0x40);
12783 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12784 ins_pipe( pipe_cmov_reg_long );
12785 %}
12786
12787 // Compare 2 longs and CMOVE ints.
12788 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12789 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12790 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12791 ins_cost(200);
12792 format %{ "CMOV$cmp $dst,$src" %}
12793 opcode(0x0F,0x40);
12794 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12795 ins_pipe( pipe_cmov_reg );
12796 %}
12797
12798 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12799 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12800 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12801 ins_cost(250);
12802 format %{ "CMOV$cmp $dst,$src" %}
12803 opcode(0x0F,0x40);
12804 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12805 ins_pipe( pipe_cmov_mem );
12806 %}
12807
12808 // Compare 2 longs and CMOVE ptrs.
12809 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12810 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12811 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12812 ins_cost(200);
12813 format %{ "CMOV$cmp $dst,$src" %}
12814 opcode(0x0F,0x40);
12815 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12816 ins_pipe( pipe_cmov_reg );
12817 %}
12818
12819 // Compare 2 longs and CMOVE doubles
12820 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12821 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12822 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12823 ins_cost(200);
12824 expand %{
12825 fcmovDPR_regS(cmp,flags,dst,src);
12826 %}
12827 %}
12828
12829 // Compare 2 longs and CMOVE doubles
12830 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12831 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12832 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12833 ins_cost(200);
12834 expand %{
12835 fcmovD_regS(cmp,flags,dst,src);
12836 %}
12837 %}
12838
12839 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12840 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12841 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12842 ins_cost(200);
12843 expand %{
12844 fcmovFPR_regS(cmp,flags,dst,src);
12845 %}
12846 %}
12847
12848
12849 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12850 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12851 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12852 ins_cost(200);
12853 expand %{
12854 fcmovF_regS(cmp,flags,dst,src);
12855 %}
12856 %}
12857
12858
12859 // ============================================================================
12860 // Procedure Call/Return Instructions
12861 // Call Java Static Instruction
12862 // Note: If this code changes, the corresponding ret_addr_offset() and
12863 // compute_padding() functions will have to be adjusted.
12864 instruct CallStaticJavaDirect(method meth) %{
12865 match(CallStaticJava);
12866 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12867 effect(USE meth);
12868
12869 ins_cost(300);
12870 format %{ "CALL,static " %}
12871 opcode(0xE8); /* E8 cd */
12872 ins_encode( pre_call_resets,
12873 Java_Static_Call( meth ),
12874 call_epilog,
12875 post_call_FPU );
12876 ins_pipe( pipe_slow );
12877 ins_alignment(4);
12878 %}
12879
12880 // Call Java Static Instruction (method handle version)
12881 // Note: If this code changes, the corresponding ret_addr_offset() and
12882 // compute_padding() functions will have to be adjusted.
12883 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12884 match(CallStaticJava);
12885 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12886 effect(USE meth);
12887 // EBP is saved by all callees (for interpreter stack correction).
12888 // We use it here for a similar purpose, in {preserve,restore}_SP.
12889
12890 ins_cost(300);
12891 format %{ "CALL,static/MethodHandle " %}
12892 opcode(0xE8); /* E8 cd */
12893 ins_encode( pre_call_resets,
12894 preserve_SP,
12895 Java_Static_Call( meth ),
12896 restore_SP,
12897 call_epilog,
12898 post_call_FPU );
12899 ins_pipe( pipe_slow );
12900 ins_alignment(4);
12901 %}
12902
12903 // Call Java Dynamic Instruction
12904 // Note: If this code changes, the corresponding ret_addr_offset() and
12905 // compute_padding() functions will have to be adjusted.
12906 instruct CallDynamicJavaDirect(method meth) %{
12907 match(CallDynamicJava);
12908 effect(USE meth);
12909
12910 ins_cost(300);
12911 format %{ "MOV EAX,(oop)-1\n\t"
12912 "CALL,dynamic" %}
12913 opcode(0xE8); /* E8 cd */
12914 ins_encode( pre_call_resets,
12915 Java_Dynamic_Call( meth ),
12916 call_epilog,
12917 post_call_FPU );
12918 ins_pipe( pipe_slow );
12919 ins_alignment(4);
12920 %}
12921
12922 // Call Runtime Instruction
12923 instruct CallRuntimeDirect(method meth) %{
12924 match(CallRuntime );
12925 effect(USE meth);
12926
12927 ins_cost(300);
12928 format %{ "CALL,runtime " %}
12929 opcode(0xE8); /* E8 cd */
12930 // Use FFREEs to clear entries in float stack
12931 ins_encode( pre_call_resets,
12932 FFree_Float_Stack_All,
12933 Java_To_Runtime( meth ),
12934 post_call_FPU );
12935 ins_pipe( pipe_slow );
12936 %}
12937
12938 // Call runtime without safepoint
12939 instruct CallLeafDirect(method meth) %{
12940 match(CallLeaf);
12941 effect(USE meth);
12942
12943 ins_cost(300);
12944 format %{ "CALL_LEAF,runtime " %}
12945 opcode(0xE8); /* E8 cd */
12946 ins_encode( pre_call_resets,
12947 FFree_Float_Stack_All,
12948 Java_To_Runtime( meth ),
12949 Verify_FPU_For_Leaf, post_call_FPU );
12950 ins_pipe( pipe_slow );
12951 %}
12952
12953 instruct CallLeafNoFPDirect(method meth) %{
12954 match(CallLeafNoFP);
12955 effect(USE meth);
12956
12957 ins_cost(300);
12958 format %{ "CALL_LEAF_NOFP,runtime " %}
12959 opcode(0xE8); /* E8 cd */
12960 ins_encode(Java_To_Runtime(meth));
12961 ins_pipe( pipe_slow );
12962 %}
12963
12964
12965 // Return Instruction
12966 // Remove the return address & jump to it.
12967 instruct Ret() %{
12968 match(Return);
12969 format %{ "RET" %}
12970 opcode(0xC3);
12971 ins_encode(OpcP);
12972 ins_pipe( pipe_jmp );
12973 %}
12974
12975 // Tail Call; Jump from runtime stub to Java code.
12976 // Also known as an 'interprocedural jump'.
12977 // Target of jump will eventually return to caller.
12978 // TailJump below removes the return address.
12979 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12980 match(TailCall jump_target method_oop );
12981 ins_cost(300);
12982 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12983 opcode(0xFF, 0x4); /* Opcode FF /4 */
12984 ins_encode( OpcP, RegOpc(jump_target) );
12985 ins_pipe( pipe_jmp );
12986 %}
12987
12988
12989 // Tail Jump; remove the return address; jump to target.
12990 // TailCall above leaves the return address around.
12991 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12992 match( TailJump jump_target ex_oop );
12993 ins_cost(300);
12994 format %{ "POP EDX\t# pop return address into dummy\n\t"
12995 "JMP $jump_target " %}
12996 opcode(0xFF, 0x4); /* Opcode FF /4 */
12997 ins_encode( enc_pop_rdx,
12998 OpcP, RegOpc(jump_target) );
12999 ins_pipe( pipe_jmp );
13000 %}
13001
13002 // Create exception oop: created by stack-crawling runtime code.
13003 // Created exception is now available to this handler, and is setup
13004 // just prior to jumping to this handler. No code emitted.
13005 instruct CreateException( eAXRegP ex_oop )
13006 %{
13007 match(Set ex_oop (CreateEx));
13008
13009 size(0);
13010 // use the following format syntax
13011 format %{ "# exception oop is in EAX; no code emitted" %}
13012 ins_encode();
13013 ins_pipe( empty );
13014 %}
13015
13016
13017 // Rethrow exception:
13018 // The exception oop will come in the first argument position.
13019 // Then JUMP (not call) to the rethrow stub code.
13020 instruct RethrowException()
13021 %{
13022 match(Rethrow);
13023
13024 // use the following format syntax
13025 format %{ "JMP rethrow_stub" %}
13026 ins_encode(enc_rethrow);
13027 ins_pipe( pipe_jmp );
13028 %}
13029
13030 // inlined locking and unlocking
13031
13032
13033 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13034 match( Set cr (FastLock object box) );
13035 effect( TEMP tmp, TEMP scr, USE_KILL box );
13036 ins_cost(300);
13037 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13038 ins_encode( Fast_Lock(object,box,tmp,scr) );
13039 ins_pipe( pipe_slow );
13040 %}
13041
13042 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13043 match( Set cr (FastUnlock object box) );
13044 effect( TEMP tmp, USE_KILL box );
13045 ins_cost(300);
13046 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13047 ins_encode( Fast_Unlock(object,box,tmp) );
13048 ins_pipe( pipe_slow );
13049 %}
13050
13051
13052
13053 // ============================================================================
13054 // Safepoint Instruction
13055 instruct safePoint_poll(eFlagsReg cr) %{
13056 match(SafePoint);
13057 effect(KILL cr);
13058
13059 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13060 // On SPARC that might be acceptable as we can generate the address with
13061 // just a sethi, saving an or. By polling at offset 0 we can end up
13062 // putting additional pressure on the index-0 in the D$. Because of
13063 // alignment (just like the situation at hand) the lower indices tend
13064 // to see more traffic. It'd be better to change the polling address
13065 // to offset 0 of the last $line in the polling page.
13066
13067 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13068 ins_cost(125);
13069 size(6) ;
13070 ins_encode( Safepoint_Poll() );
13071 ins_pipe( ialu_reg_mem );
13072 %}
13073
13074
13075 // ============================================================================
13076 // This name is KNOWN by the ADLC and cannot be changed.
13077 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13078 // for this guy.
13079 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13080 match(Set dst (ThreadLocal));
13081 effect(DEF dst, KILL cr);
13082
13083 format %{ "MOV $dst, Thread::current()" %}
13084 ins_encode %{
13085 Register dstReg = as_Register($dst$$reg);
13086 __ get_thread(dstReg);
13087 %}
13088 ins_pipe( ialu_reg_fat );
13089 %}
13090
13091
13092
13093 //----------PEEPHOLE RULES-----------------------------------------------------
13094 // These must follow all instruction definitions as they use the names
13095 // defined in the instructions definitions.
13096 //
13097 // peepmatch ( root_instr_name [preceding_instruction]* );
13098 //
13099 // peepconstraint %{
13100 // (instruction_number.operand_name relational_op instruction_number.operand_name
13101 // [, ...] );
13102 // // instruction numbers are zero-based using left to right order in peepmatch
13103 //
13104 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13105 // // provide an instruction_number.operand_name for each operand that appears
13106 // // in the replacement instruction's match rule
13107 //
13108 // ---------VM FLAGS---------------------------------------------------------
13109 //
13110 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13111 //
13112 // Each peephole rule is given an identifying number starting with zero and
13113 // increasing by one in the order seen by the parser. An individual peephole
13114 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13115 // on the command-line.
13116 //
13117 // ---------CURRENT LIMITATIONS----------------------------------------------
13118 //
13119 // Only match adjacent instructions in same basic block
13120 // Only equality constraints
13121 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13122 // Only one replacement instruction
13123 //
13124 // ---------EXAMPLE----------------------------------------------------------
13125 //
13126 // // pertinent parts of existing instructions in architecture description
13127 // instruct movI(rRegI dst, rRegI src) %{
13128 // match(Set dst (CopyI src));
13129 // %}
13130 //
13131 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13132 // match(Set dst (AddI dst src));
13133 // effect(KILL cr);
13134 // %}
13135 //
13136 // // Change (inc mov) to lea
13137 // peephole %{
13138 // // increment preceeded by register-register move
13139 // peepmatch ( incI_eReg movI );
13140 // // require that the destination register of the increment
13141 // // match the destination register of the move
13142 // peepconstraint ( 0.dst == 1.dst );
13143 // // construct a replacement instruction that sets
13144 // // the destination to ( move's source register + one )
13145 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13146 // %}
13147 //
13148 // Implementation no longer uses movX instructions since
13149 // machine-independent system no longer uses CopyX nodes.
13150 //
13151 // peephole %{
13152 // peepmatch ( incI_eReg movI );
13153 // peepconstraint ( 0.dst == 1.dst );
13154 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13155 // %}
13156 //
13157 // peephole %{
13158 // peepmatch ( decI_eReg movI );
13159 // peepconstraint ( 0.dst == 1.dst );
13160 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13161 // %}
13162 //
13163 // peephole %{
13164 // peepmatch ( addI_eReg_imm movI );
13165 // peepconstraint ( 0.dst == 1.dst );
13166 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13167 // %}
13168 //
13169 // peephole %{
13170 // peepmatch ( addP_eReg_imm movP );
13171 // peepconstraint ( 0.dst == 1.dst );
13172 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13173 // %}
13174
13175 // // Change load of spilled value to only a spill
13176 // instruct storeI(memory mem, rRegI src) %{
13177 // match(Set mem (StoreI mem src));
13178 // %}
13179 //
13180 // instruct loadI(rRegI dst, memory mem) %{
13181 // match(Set dst (LoadI mem));
13182 // %}
13183 //
13184 peephole %{
13185 peepmatch ( loadI storeI );
13186 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13187 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13188 %}
13189
13190 //----------SMARTSPILL RULES---------------------------------------------------
13191 // These must follow all instruction definitions as they use the names
13192 // defined in the instructions definitions.