src/cpu/x86/vm/x86_32.ad

rev 5513 : 8026844: Various Math functions needs intrinsification
Reviewed-by: duke

*** 1536,1545 ****
--- 1536,1550 ----
  
  const RegMask Matcher::mathExactI_result_proj_mask() {
    return EAX_REG_mask();
  }
  
+ const RegMask Matcher::mathExactL_result_proj_mask() {
+   ShouldNotReachHere();
+   return RegMask();
+ }
+ 
  const RegMask Matcher::mathExactI_flags_proj_mask() {
    return INT_FLAGS_mask();
  }
  
  // Returns true if the high 32 bits of the value is known to be zero.
*** 7517,7527 ****
  %}
  
  //----------Arithmetic Instructions--------------------------------------------
  //----------Addition Instructions----------------------------------------------
  
! instruct addExactI_rReg(eAXRegI dst, rRegI src, eFlagsReg cr)
  %{
    match(AddExactI dst src);
    effect(DEF cr);
  
    format %{ "ADD    $dst, $src\t# addExact int" %}
--- 7522,7532 ----
  %}
  
  //----------Arithmetic Instructions--------------------------------------------
  //----------Addition Instructions----------------------------------------------
  
! instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
  %{
    match(AddExactI dst src);
    effect(DEF cr);
  
    format %{ "ADD    $dst, $src\t# addExact int" %}
*** 7529,7539 ****
      __ addl($dst$$Register, $src$$Register);
    %}
    ins_pipe(ialu_reg_reg);
  %}
  
! instruct addExactI_rReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
  %{
    match(AddExactI dst src);
    effect(DEF cr);
  
    format %{ "ADD    $dst, $src\t# addExact int" %}
--- 7534,7544 ----
      __ addl($dst$$Register, $src$$Register);
    %}
    ins_pipe(ialu_reg_reg);
  %}
  
! instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
  %{
    match(AddExactI dst src);
    effect(DEF cr);
  
    format %{ "ADD    $dst, $src\t# addExact int" %}
*** 7541,7550 ****
--- 7546,7569 ----
      __ addl($dst$$Register, $src$$constant);
    %}
    ins_pipe(ialu_reg_reg);
  %}
  
+ instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
+ %{
+   match(AddExactI dst (LoadI src));
+   effect(DEF cr);
+ 
+   ins_cost(125);
+   format %{ "ADD    $dst,$src\t# addExact int" %}
+   ins_encode %{
+     __ addl($dst$$Register, $src$$Address);
+   %}
+   ins_pipe( ialu_reg_mem );
+ %}
+ 
+ 
  // Integer Addition Instructions
  instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
    match(Set dst (AddI dst src));
    effect(KILL cr);
  
*** 7849,7858 ****
--- 7868,7915 ----
    %}
    ins_pipe( pipe_cmpxchg );
  %}
  
  //----------Subtraction Instructions-------------------------------------------
+ 
+ instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
+ %{
+   match(SubExactI dst src);
+   effect(DEF cr);
+ 
+   format %{ "SUB    $dst, $src\t# subExact int" %}
+   ins_encode %{
+     __ subl($dst$$Register, $src$$Register);
+   %}
+   ins_pipe(ialu_reg_reg);
+ %}
+ 
+ instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
+ %{
+   match(SubExactI dst src);
+   effect(DEF cr);
+ 
+   format %{ "SUB    $dst, $src\t# subExact int" %}
+   ins_encode %{
+     __ subl($dst$$Register, $src$$constant);
+   %}
+   ins_pipe(ialu_reg_reg);
+ %}
+ 
+ instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
+ %{
+   match(SubExactI dst (LoadI src));
+   effect(DEF cr);
+ 
+   ins_cost(125);
+   format %{ "SUB    $dst,$src\t# subExact int" %}
+   ins_encode %{
+     __ subl($dst$$Register, $src$$Address);
+   %}
+   ins_pipe( ialu_reg_mem );
+ %}
+ 
  // Integer Subtraction Instructions
  instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
    match(Set dst (SubI dst src));
    effect(KILL cr);
  
*** 7917,7926 ****
--- 7974,7993 ----
    opcode(0xF7,0x03);  // Opcode F7 /3
    ins_encode( OpcP, RegOpc( dst ) );
    ins_pipe( ialu_reg );
  %}
  
+ instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
+   match(NegExactI dst);
+   effect(DEF cr);
+ 
+   format %{ "NEG    $dst\t# negExact int"%}
+   ins_encode %{
+     __ negl($dst$$Register);
+   %}
+   ins_pipe(ialu_reg);
+ %}
  
  //----------Multiplication/Division Instructions-------------------------------
  // Integer Multiplication Instructions
  // Multiply Register
  instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
*** 8129,8138 ****
--- 8196,8245 ----
              "ADD    EDX,$tmp" %}
    ins_encode( long_multiply_con( dst, src, tmp ) );
    ins_pipe( pipe_slow );
  %}
  
+ instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
+ %{
+   match(MulExactI dst src);
+   effect(DEF cr);
+ 
+   ins_cost(300);
+   format %{ "IMUL   $dst, $src\t# mulExact int" %}
+   ins_encode %{
+     __ imull($dst$$Register, $src$$Register);
+   %}
+   ins_pipe(ialu_reg_reg_alu0);
+ %}
+ 
+ instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
+ %{
+   match(MulExactI src imm);
+   effect(DEF cr);
+ 
+   ins_cost(300);
+   format %{ "IMUL   $dst, $src, $imm\t# mulExact int" %}
+   ins_encode %{
+     __ imull($dst$$Register, $src$$Register, $imm$$constant);
+   %}
+   ins_pipe(ialu_reg_reg_alu0);
+ %}
+ 
+ instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
+ %{
+   match(MulExactI dst (LoadI src));
+   effect(DEF cr);
+ 
+   ins_cost(350);
+   format %{ "IMUL   $dst, $src\t# mulExact int" %}
+   ins_encode %{
+     __ imull($dst$$Register, $src$$Address);
+   %}
+   ins_pipe(ialu_reg_mem_alu0);
+ %}
+ 
+ 
  // Integer DIV with Register
  instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
    match(Set rax (DivI rax div));
    effect(KILL rdx, KILL cr);
    size(26);