1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1540
1541 const RegMask Matcher::mathExactI_flags_proj_mask() {
1542 return INT_FLAGS_mask();
1543 }
1544
1545 // Returns true if the high 32 bits of the value is known to be zero.
1546 bool is_operand_hi32_zero(Node* n) {
1547 int opc = n->Opcode();
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1559
1560 %}
7502 ins_cost(200);
7503 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7504 "CMOV$cop $dst.hi,$src.hi" %}
7505 opcode(0x0F,0x40);
7506 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7507 ins_pipe( pipe_cmov_reg_long );
7508 %}
7509
7510 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7511 predicate(VM_Version::supports_cmov() );
7512 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7513 ins_cost(200);
7514 expand %{
7515 cmovL_regU(cop, cr, dst, src);
7516 %}
7517 %}
7518
7519 //----------Arithmetic Instructions--------------------------------------------
7520 //----------Addition Instructions----------------------------------------------
7521
7522 instruct addExactI_rReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7523 %{
7524 match(AddExactI dst src);
7525 effect(DEF cr);
7526
7527 format %{ "ADD $dst, $src\t# addExact int" %}
7528 ins_encode %{
7529 __ addl($dst$$Register, $src$$Register);
7530 %}
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 instruct addExactI_rReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7535 %{
7536 match(AddExactI dst src);
7537 effect(DEF cr);
7538
7539 format %{ "ADD $dst, $src\t# addExact int" %}
7540 ins_encode %{
7541 __ addl($dst$$Register, $src$$constant);
7542 %}
7543 ins_pipe(ialu_reg_reg);
7544 %}
7545
7546 // Integer Addition Instructions
7547 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7548 match(Set dst (AddI dst src));
7549 effect(KILL cr);
7550
7551 size(2);
7552 format %{ "ADD $dst,$src" %}
7553 opcode(0x03);
7554 ins_encode( OpcP, RegReg( dst, src) );
7555 ins_pipe( ialu_reg_reg );
7556 %}
7557
7558 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7559 match(Set dst (AddI dst src));
7560 effect(KILL cr);
7561
7562 format %{ "ADD $dst,$src" %}
7563 opcode(0x81, 0x00); /* /0 id */
7564 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7565 ins_pipe( ialu_reg );
7834
7835 instruct xchgI( memory mem, rRegI newval) %{
7836 match(Set newval (GetAndSetI mem newval));
7837 format %{ "XCHGL $newval,[$mem]" %}
7838 ins_encode %{
7839 __ xchgl($newval$$Register, $mem$$Address);
7840 %}
7841 ins_pipe( pipe_cmpxchg );
7842 %}
7843
7844 instruct xchgP( memory mem, pRegP newval) %{
7845 match(Set newval (GetAndSetP mem newval));
7846 format %{ "XCHGL $newval,[$mem]" %}
7847 ins_encode %{
7848 __ xchgl($newval$$Register, $mem$$Address);
7849 %}
7850 ins_pipe( pipe_cmpxchg );
7851 %}
7852
7853 //----------Subtraction Instructions-------------------------------------------
7854 // Integer Subtraction Instructions
7855 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7856 match(Set dst (SubI dst src));
7857 effect(KILL cr);
7858
7859 size(2);
7860 format %{ "SUB $dst,$src" %}
7861 opcode(0x2B);
7862 ins_encode( OpcP, RegReg( dst, src) );
7863 ins_pipe( ialu_reg_reg );
7864 %}
7865
7866 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7867 match(Set dst (SubI dst src));
7868 effect(KILL cr);
7869
7870 format %{ "SUB $dst,$src" %}
7871 opcode(0x81,0x05); /* Opcode 81 /5 */
7872 // ins_encode( RegImm( dst, src) );
7873 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7902 effect(KILL cr);
7903
7904 size(2);
7905 format %{ "SUB $dst,$src" %}
7906 opcode(0x2B);
7907 ins_encode( OpcP, RegReg( dst, src) );
7908 ins_pipe( ialu_reg_reg );
7909 %}
7910
7911 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7912 match(Set dst (SubI zero dst));
7913 effect(KILL cr);
7914
7915 size(2);
7916 format %{ "NEG $dst" %}
7917 opcode(0xF7,0x03); // Opcode F7 /3
7918 ins_encode( OpcP, RegOpc( dst ) );
7919 ins_pipe( ialu_reg );
7920 %}
7921
7922
7923 //----------Multiplication/Division Instructions-------------------------------
7924 // Integer Multiplication Instructions
7925 // Multiply Register
7926 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7927 match(Set dst (MulI dst src));
7928 effect(KILL cr);
7929
7930 size(3);
7931 ins_cost(300);
7932 format %{ "IMUL $dst,$src" %}
7933 opcode(0xAF, 0x0F);
7934 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7935 ins_pipe( ialu_reg_reg_alu0 );
7936 %}
7937
7938 // Multiply 32-bit Immediate
7939 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7940 match(Set dst (MulI src imm));
7941 effect(KILL cr);
8113 __ mull($src$$Register);
8114 %}
8115 ins_pipe( pipe_slow );
8116 %}
8117
8118 // Multiply Register Long by small constant
8119 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8120 match(Set dst (MulL dst src));
8121 effect(KILL cr, TEMP tmp);
8122 ins_cost(2*100+2*400);
8123 size(12);
8124 // Basic idea: lo(result) = lo(src * EAX)
8125 // hi(result) = hi(src * EAX) + lo(src * EDX)
8126 format %{ "IMUL $tmp,EDX,$src\n\t"
8127 "MOV EDX,$src\n\t"
8128 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8129 "ADD EDX,$tmp" %}
8130 ins_encode( long_multiply_con( dst, src, tmp ) );
8131 ins_pipe( pipe_slow );
8132 %}
8133
8134 // Integer DIV with Register
8135 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8136 match(Set rax (DivI rax div));
8137 effect(KILL rdx, KILL cr);
8138 size(26);
8139 ins_cost(30*100+10*100);
8140 format %{ "CMP EAX,0x80000000\n\t"
8141 "JNE,s normal\n\t"
8142 "XOR EDX,EDX\n\t"
8143 "CMP ECX,-1\n\t"
8144 "JE,s done\n"
8145 "normal: CDQ\n\t"
8146 "IDIV $div\n\t"
8147 "done:" %}
8148 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8149 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8150 ins_pipe( ialu_reg_reg_alu0 );
8151 %}
8152
|
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1540
1541 const RegMask Matcher::mathExactL_result_proj_mask() {
1542 ShouldNotReachHere();
1543 return RegMask();
1544 }
1545
1546 const RegMask Matcher::mathExactI_flags_proj_mask() {
1547 return INT_FLAGS_mask();
1548 }
1549
1550 // Returns true if the high 32 bits of the value is known to be zero.
1551 bool is_operand_hi32_zero(Node* n) {
1552 int opc = n->Opcode();
1553 if (opc == Op_AndL) {
1554 Node* o2 = n->in(2);
1555 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1556 return true;
1557 }
1558 }
1559 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1560 return true;
1561 }
1562 return false;
1563 }
1564
1565 %}
7507 ins_cost(200);
7508 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7509 "CMOV$cop $dst.hi,$src.hi" %}
7510 opcode(0x0F,0x40);
7511 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7512 ins_pipe( pipe_cmov_reg_long );
7513 %}
7514
7515 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7516 predicate(VM_Version::supports_cmov() );
7517 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7518 ins_cost(200);
7519 expand %{
7520 cmovL_regU(cop, cr, dst, src);
7521 %}
7522 %}
7523
7524 //----------Arithmetic Instructions--------------------------------------------
7525 //----------Addition Instructions----------------------------------------------
7526
7527 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7528 %{
7529 match(AddExactI dst src);
7530 effect(DEF cr);
7531
7532 format %{ "ADD $dst, $src\t# addExact int" %}
7533 ins_encode %{
7534 __ addl($dst$$Register, $src$$Register);
7535 %}
7536 ins_pipe(ialu_reg_reg);
7537 %}
7538
7539 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7540 %{
7541 match(AddExactI dst src);
7542 effect(DEF cr);
7543
7544 format %{ "ADD $dst, $src\t# addExact int" %}
7545 ins_encode %{
7546 __ addl($dst$$Register, $src$$constant);
7547 %}
7548 ins_pipe(ialu_reg_reg);
7549 %}
7550
7551 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7552 %{
7553 match(AddExactI dst (LoadI src));
7554 effect(DEF cr);
7555
7556 ins_cost(125);
7557 format %{ "ADD $dst,$src\t# addExact int" %}
7558 ins_encode %{
7559 __ addl($dst$$Register, $src$$Address);
7560 %}
7561 ins_pipe( ialu_reg_mem );
7562 %}
7563
7564
7565 // Integer Addition Instructions
7566 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7567 match(Set dst (AddI dst src));
7568 effect(KILL cr);
7569
7570 size(2);
7571 format %{ "ADD $dst,$src" %}
7572 opcode(0x03);
7573 ins_encode( OpcP, RegReg( dst, src) );
7574 ins_pipe( ialu_reg_reg );
7575 %}
7576
7577 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7578 match(Set dst (AddI dst src));
7579 effect(KILL cr);
7580
7581 format %{ "ADD $dst,$src" %}
7582 opcode(0x81, 0x00); /* /0 id */
7583 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7584 ins_pipe( ialu_reg );
7853
7854 instruct xchgI( memory mem, rRegI newval) %{
7855 match(Set newval (GetAndSetI mem newval));
7856 format %{ "XCHGL $newval,[$mem]" %}
7857 ins_encode %{
7858 __ xchgl($newval$$Register, $mem$$Address);
7859 %}
7860 ins_pipe( pipe_cmpxchg );
7861 %}
7862
7863 instruct xchgP( memory mem, pRegP newval) %{
7864 match(Set newval (GetAndSetP mem newval));
7865 format %{ "XCHGL $newval,[$mem]" %}
7866 ins_encode %{
7867 __ xchgl($newval$$Register, $mem$$Address);
7868 %}
7869 ins_pipe( pipe_cmpxchg );
7870 %}
7871
7872 //----------Subtraction Instructions-------------------------------------------
7873
7874 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7875 %{
7876 match(SubExactI dst src);
7877 effect(DEF cr);
7878
7879 format %{ "SUB $dst, $src\t# subExact int" %}
7880 ins_encode %{
7881 __ subl($dst$$Register, $src$$Register);
7882 %}
7883 ins_pipe(ialu_reg_reg);
7884 %}
7885
7886 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7887 %{
7888 match(SubExactI dst src);
7889 effect(DEF cr);
7890
7891 format %{ "SUB $dst, $src\t# subExact int" %}
7892 ins_encode %{
7893 __ subl($dst$$Register, $src$$constant);
7894 %}
7895 ins_pipe(ialu_reg_reg);
7896 %}
7897
7898 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7899 %{
7900 match(SubExactI dst (LoadI src));
7901 effect(DEF cr);
7902
7903 ins_cost(125);
7904 format %{ "SUB $dst,$src\t# subExact int" %}
7905 ins_encode %{
7906 __ subl($dst$$Register, $src$$Address);
7907 %}
7908 ins_pipe( ialu_reg_mem );
7909 %}
7910
7911 // Integer Subtraction Instructions
7912 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7913 match(Set dst (SubI dst src));
7914 effect(KILL cr);
7915
7916 size(2);
7917 format %{ "SUB $dst,$src" %}
7918 opcode(0x2B);
7919 ins_encode( OpcP, RegReg( dst, src) );
7920 ins_pipe( ialu_reg_reg );
7921 %}
7922
7923 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7924 match(Set dst (SubI dst src));
7925 effect(KILL cr);
7926
7927 format %{ "SUB $dst,$src" %}
7928 opcode(0x81,0x05); /* Opcode 81 /5 */
7929 // ins_encode( RegImm( dst, src) );
7930 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7959 effect(KILL cr);
7960
7961 size(2);
7962 format %{ "SUB $dst,$src" %}
7963 opcode(0x2B);
7964 ins_encode( OpcP, RegReg( dst, src) );
7965 ins_pipe( ialu_reg_reg );
7966 %}
7967
7968 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7969 match(Set dst (SubI zero dst));
7970 effect(KILL cr);
7971
7972 size(2);
7973 format %{ "NEG $dst" %}
7974 opcode(0xF7,0x03); // Opcode F7 /3
7975 ins_encode( OpcP, RegOpc( dst ) );
7976 ins_pipe( ialu_reg );
7977 %}
7978
7979 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7980 match(NegExactI dst);
7981 effect(DEF cr);
7982
7983 format %{ "NEG $dst\t# negExact int"%}
7984 ins_encode %{
7985 __ negl($dst$$Register);
7986 %}
7987 ins_pipe(ialu_reg);
7988 %}
7989
7990 //----------Multiplication/Division Instructions-------------------------------
7991 // Integer Multiplication Instructions
7992 // Multiply Register
7993 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7994 match(Set dst (MulI dst src));
7995 effect(KILL cr);
7996
7997 size(3);
7998 ins_cost(300);
7999 format %{ "IMUL $dst,$src" %}
8000 opcode(0xAF, 0x0F);
8001 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8002 ins_pipe( ialu_reg_reg_alu0 );
8003 %}
8004
8005 // Multiply 32-bit Immediate
8006 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8007 match(Set dst (MulI src imm));
8008 effect(KILL cr);
8180 __ mull($src$$Register);
8181 %}
8182 ins_pipe( pipe_slow );
8183 %}
8184
8185 // Multiply Register Long by small constant
8186 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8187 match(Set dst (MulL dst src));
8188 effect(KILL cr, TEMP tmp);
8189 ins_cost(2*100+2*400);
8190 size(12);
8191 // Basic idea: lo(result) = lo(src * EAX)
8192 // hi(result) = hi(src * EAX) + lo(src * EDX)
8193 format %{ "IMUL $tmp,EDX,$src\n\t"
8194 "MOV EDX,$src\n\t"
8195 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8196 "ADD EDX,$tmp" %}
8197 ins_encode( long_multiply_con( dst, src, tmp ) );
8198 ins_pipe( pipe_slow );
8199 %}
8200
8201 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8202 %{
8203 match(MulExactI dst src);
8204 effect(DEF cr);
8205
8206 ins_cost(300);
8207 format %{ "IMUL $dst, $src\t# mulExact int" %}
8208 ins_encode %{
8209 __ imull($dst$$Register, $src$$Register);
8210 %}
8211 ins_pipe(ialu_reg_reg_alu0);
8212 %}
8213
8214 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8215 %{
8216 match(MulExactI src imm);
8217 effect(DEF cr);
8218
8219 ins_cost(300);
8220 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8221 ins_encode %{
8222 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8223 %}
8224 ins_pipe(ialu_reg_reg_alu0);
8225 %}
8226
8227 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8228 %{
8229 match(MulExactI dst (LoadI src));
8230 effect(DEF cr);
8231
8232 ins_cost(350);
8233 format %{ "IMUL $dst, $src\t# mulExact int" %}
8234 ins_encode %{
8235 __ imull($dst$$Register, $src$$Address);
8236 %}
8237 ins_pipe(ialu_reg_mem_alu0);
8238 %}
8239
8240
8241 // Integer DIV with Register
8242 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8243 match(Set rax (DivI rax div));
8244 effect(KILL rdx, KILL cr);
8245 size(26);
8246 ins_cost(30*100+10*100);
8247 format %{ "CMP EAX,0x80000000\n\t"
8248 "JNE,s normal\n\t"
8249 "XOR EDX,EDX\n\t"
8250 "CMP ECX,-1\n\t"
8251 "JE,s done\n"
8252 "normal: CDQ\n\t"
8253 "IDIV $div\n\t"
8254 "done:" %}
8255 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8256 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8257 ins_pipe( ialu_reg_reg_alu0 );
8258 %}
8259
|