1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
577
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
589
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
595
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
601
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
607
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
611
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
615
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
623
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
631
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
636
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
641
642
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
645
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
656
657
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
660
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
675
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
688
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
697
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
710
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
721
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
732
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
744
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
749
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
758
759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
773
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
780
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
797
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
809
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
830
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
865
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
905
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
911
912 uint index = src2_enc;
913 int disp = disp32;
914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
916 disp += STACK_BIAS;
917
918 // We should have a compiler bailout here rather than a guarantee.
919 // Better yet would be some mechanism to handle variable-size matches correctly.
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
921
922 if( disp == 0 ) {
923 // use reg-reg form
924 // bit 13 is already zero
925 instr |= index;
926 } else {
927 // use reg-imm form
928 instr |= 0x00002000; // set bit 13 to one
929 instr |= disp & 0x1FFF;
930 }
931
932 cbuf.insts()->emit_int32(instr);
933
934 #ifdef ASSERT
935 {
936 MacroAssembler _masm(&cbuf);
937 if (is_verified_oop_base) {
938 __ verify_oop(reg_to_register_object(src1_enc));
939 }
940 if (is_verified_oop_store) {
941 __ verify_oop(reg_to_register_object(dst_enc));
942 }
943 if (tmp_enc != -1) {
944 __ mov(O7, reg_to_register_object(tmp_enc));
945 }
946 if (is_verified_oop_load) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 }
950 #endif
951 }
952
953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
954 // The method which records debug information at every safepoint
955 // expects the call to be the first instruction in the snippet as
956 // it creates a PcDesc structure which tracks the offset of a call
957 // from the start of the codeBlob. This offset is computed as
958 // code_end() - code_begin() of the code which has been emitted
959 // so far.
960 // In this particular case we have skirted around the problem by
961 // putting the "mov" instruction in the delay slot but the problem
962 // may bite us again at some other point and a cleaner/generic
963 // solution using relocations would be needed.
964 MacroAssembler _masm(&cbuf);
965 __ set_inst_mark();
966
967 // We flush the current window just so that there is a valid stack copy
968 // the fact that the current window becomes active again instantly is
969 // not a problem there is nothing live in it.
970
971 #ifdef ASSERT
972 int startpos = __ offset();
973 #endif /* ASSERT */
974
975 __ call((address)entry_point, rtype);
976
977 if (preserve_g2) __ delayed()->mov(G2, L7);
978 else __ delayed()->nop();
979
980 if (preserve_g2) __ mov(L7, G2);
981
982 #ifdef ASSERT
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
984 #ifdef _LP64
985 // Trash argument dump slots.
986 __ set(0xb0b8ac0db0b8ac0d, G1);
987 __ mov(G1, G5);
988 __ stx(G1, SP, STACK_BIAS + 0x80);
989 __ stx(G1, SP, STACK_BIAS + 0x88);
990 __ stx(G1, SP, STACK_BIAS + 0x90);
991 __ stx(G1, SP, STACK_BIAS + 0x98);
992 __ stx(G1, SP, STACK_BIAS + 0xA0);
993 __ stx(G1, SP, STACK_BIAS + 0xA8);
994 #else // _LP64
995 // this is also a native call, so smash the first 7 stack locations,
996 // and the various registers
997
998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
999 // while [SP+0x44..0x58] are the argument dump slots.
1000 __ set((intptr_t)0xbaadf00d, G1);
1001 __ mov(G1, G5);
1002 __ sllx(G1, 32, G1);
1003 __ or3(G1, G5, G1);
1004 __ mov(G1, G5);
1005 __ stx(G1, SP, 0x40);
1006 __ stx(G1, SP, 0x48);
1007 __ stx(G1, SP, 0x50);
1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1009 #endif // _LP64
1010 }
1011 #endif /*ASSERT*/
1012 }
1013
1014 //=============================================================================
1015 // REQUIRED FUNCTIONALITY for encoding
1016 void emit_lo(CodeBuffer &cbuf, int val) { }
1017 void emit_hi(CodeBuffer &cbuf, int val) { }
1018
1019
1020 //=============================================================================
1021 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1022
1023 int Compile::ConstantTable::calculate_table_base_offset() const {
1024 if (UseRDPCForConstantTableBase) {
1025 // The table base offset might be less but then it fits into
1026 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1027 return Assembler::min_simm13();
1028 } else {
1029 int offset = -(size() / 2);
1030 if (!Assembler::is_simm13(offset)) {
1031 offset = Assembler::min_simm13();
1032 }
1033 return offset;
1034 }
1035 }
1036
1037 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1038 Compile* C = ra_->C;
1039 Compile::ConstantTable& constant_table = C->constant_table();
1040 MacroAssembler _masm(&cbuf);
1041
1042 Register r = as_Register(ra_->get_encode(this));
1043 CodeSection* consts_section = __ code()->consts();
1044 int consts_size = consts_section->align_at_start(consts_section->size());
1045 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1046
1047 if (UseRDPCForConstantTableBase) {
1048 // For the following RDPC logic to work correctly the consts
1049 // section must be allocated right before the insts section. This
1050 // assert checks for that. The layout and the SECT_* constants
1051 // are defined in src/share/vm/asm/codeBuffer.hpp.
1052 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1053 int insts_offset = __ offset();
1054
1055 // Layout:
1056 //
1057 // |----------- consts section ------------|----------- insts section -----------...
1058 // |------ constant table -----|- padding -|------------------x----
1059 // \ current PC (RDPC instruction)
1060 // |<------------- consts_size ----------->|<- insts_offset ->|
1061 // \ table base
1062 // The table base offset is later added to the load displacement
1063 // so it has to be negative.
1064 int table_base_offset = -(consts_size + insts_offset);
1065 int disp;
1066
1067 // If the displacement from the current PC to the constant table
1068 // base fits into simm13 we set the constant table base to the
1069 // current PC.
1070 if (Assembler::is_simm13(table_base_offset)) {
1071 constant_table.set_table_base_offset(table_base_offset);
1072 disp = 0;
1073 } else {
1074 // Otherwise we set the constant table base offset to the
1075 // maximum negative displacement of load instructions to keep
1076 // the disp as small as possible:
1077 //
1078 // |<------------- consts_size ----------->|<- insts_offset ->|
1079 // |<--------- min_simm13 --------->|<-------- disp --------->|
1080 // \ table base
1081 table_base_offset = Assembler::min_simm13();
1082 constant_table.set_table_base_offset(table_base_offset);
1083 disp = (consts_size + insts_offset) + table_base_offset;
1084 }
1085
1086 __ rdpc(r);
1087
1088 if (disp != 0) {
1089 assert(r != O7, "need temporary");
1090 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1091 }
1092 }
1093 else {
1094 // Materialize the constant table base.
1095 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1096 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1097 AddressLiteral base(baseaddr, rspec);
1098 __ set(base, r);
1099 }
1100 }
1101
1102 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1103 if (UseRDPCForConstantTableBase) {
1104 // This is really the worst case but generally it's only 1 instruction.
1105 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1106 } else {
1107 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1108 }
1109 }
1110
1111 #ifndef PRODUCT
1112 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1113 char reg[128];
1114 ra_->dump_register(this, reg);
1115 if (UseRDPCForConstantTableBase) {
1116 st->print("RDPC %s\t! constant table base", reg);
1117 } else {
1118 st->print("SET &constanttable,%s\t! constant table base", reg);
1119 }
1120 }
1121 #endif
1122
1123
1124 //=============================================================================
1125
1126 #ifndef PRODUCT
1127 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1128 Compile* C = ra_->C;
1129
1130 for (int i = 0; i < OptoPrologueNops; i++) {
1131 st->print_cr("NOP"); st->print("\t");
1132 }
1133
1134 if( VerifyThread ) {
1135 st->print_cr("Verify_Thread"); st->print("\t");
1136 }
1137
1138 size_t framesize = C->frame_slots() << LogBytesPerInt;
1139
1140 // Calls to C2R adapters often do not accept exceptional returns.
1141 // We require that their callers must bang for them. But be careful, because
1142 // some VM calls (such as call site linkage) can use several kilobytes of
1143 // stack. But the stack safety zone should account for that.
1144 // See bugs 4446381, 4468289, 4497237.
1145 if (C->need_stack_bang(framesize)) {
1146 st->print_cr("! stack bang"); st->print("\t");
1147 }
1148
1149 if (Assembler::is_simm13(-framesize)) {
1150 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1151 } else {
1152 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1153 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1154 st->print ("SAVE R_SP,R_G3,R_SP");
1155 }
1156
1157 }
1158 #endif
1159
1160 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1161 Compile* C = ra_->C;
1162 MacroAssembler _masm(&cbuf);
1163
1164 for (int i = 0; i < OptoPrologueNops; i++) {
1165 __ nop();
1166 }
1167
1168 __ verify_thread();
1169
1170 size_t framesize = C->frame_slots() << LogBytesPerInt;
1171 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1172 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1173
1174 // Calls to C2R adapters often do not accept exceptional returns.
1175 // We require that their callers must bang for them. But be careful, because
1176 // some VM calls (such as call site linkage) can use several kilobytes of
1177 // stack. But the stack safety zone should account for that.
1178 // See bugs 4446381, 4468289, 4497237.
1179 if (C->need_stack_bang(framesize)) {
1180 __ generate_stack_overflow_check(framesize);
1181 }
1182
1183 if (Assembler::is_simm13(-framesize)) {
1184 __ save(SP, -framesize, SP);
1185 } else {
1186 __ sethi(-framesize & ~0x3ff, G3);
1187 __ add(G3, -framesize & 0x3ff, G3);
1188 __ save(SP, G3, SP);
1189 }
1190 C->set_frame_complete( __ offset() );
1191
1192 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1193 // NOTE: We set the table base offset here because users might be
1194 // emitted before MachConstantBaseNode.
1195 Compile::ConstantTable& constant_table = C->constant_table();
1196 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1197 }
1198 }
1199
1200 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1201 return MachNode::size(ra_);
1202 }
1203
1204 int MachPrologNode::reloc() const {
1205 return 10; // a large enough number
1206 }
1207
1208 //=============================================================================
1209 #ifndef PRODUCT
1210 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1211 Compile* C = ra_->C;
1212
1213 if( do_polling() && ra_->C->is_method_compilation() ) {
1214 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1215 #ifdef _LP64
1216 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1217 #else
1218 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1219 #endif
1220 }
1221
1222 if( do_polling() )
1223 st->print("RET\n\t");
1224
1225 st->print("RESTORE");
1226 }
1227 #endif
1228
1229 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1230 MacroAssembler _masm(&cbuf);
1231 Compile* C = ra_->C;
1232
1233 __ verify_thread();
1234
1235 // If this does safepoint polling, then do it here
1236 if( do_polling() && ra_->C->is_method_compilation() ) {
1237 AddressLiteral polling_page(os::get_polling_page());
1238 __ sethi(polling_page, L0);
1239 __ relocate(relocInfo::poll_return_type);
1240 __ ld_ptr( L0, 0, G0 );
1241 }
1242
1243 // If this is a return, then stuff the restore in the delay slot
1244 if( do_polling() ) {
1245 __ ret();
1246 __ delayed()->restore();
1247 } else {
1248 __ restore();
1249 }
1250 }
1251
1252 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1253 return MachNode::size(ra_);
1254 }
1255
1256 int MachEpilogNode::reloc() const {
1257 return 16; // a large enough number
1258 }
1259
1260 const Pipeline * MachEpilogNode::pipeline() const {
1261 return MachNode::pipeline_class();
1262 }
1263
1264 int MachEpilogNode::safepoint_offset() const {
1265 assert( do_polling(), "no return for this epilog node");
1266 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1267 }
1268
1269 //=============================================================================
1270
1271 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1272 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1273 static enum RC rc_class( OptoReg::Name reg ) {
1274 if( !OptoReg::is_valid(reg) ) return rc_bad;
1275 if (OptoReg::is_stack(reg)) return rc_stack;
1276 VMReg r = OptoReg::as_VMReg(reg);
1277 if (r->is_Register()) return rc_int;
1278 assert(r->is_FloatRegister(), "must be");
1279 return rc_float;
1280 }
1281
1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1283 if( cbuf ) {
1284 // Better yet would be some mechanism to handle variable-size matches correctly
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1287 } else {
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1289 }
1290 }
1291 #ifndef PRODUCT
1292 else if( !do_size ) {
1293 if( size != 0 ) st->print("\n\t");
1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1296 }
1297 #endif
1298 return size+4;
1299 }
1300
1301 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1302 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1303 #ifndef PRODUCT
1304 else if( !do_size ) {
1305 if( size != 0 ) st->print("\n\t");
1306 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1307 }
1308 #endif
1309 return size+4;
1310 }
1311
1312 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1313 PhaseRegAlloc *ra_,
1314 bool do_size,
1315 outputStream* st ) const {
1316 // Get registers to move
1317 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1318 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1319 OptoReg::Name dst_second = ra_->get_reg_second(this );
1320 OptoReg::Name dst_first = ra_->get_reg_first(this );
1321
1322 enum RC src_second_rc = rc_class(src_second);
1323 enum RC src_first_rc = rc_class(src_first);
1324 enum RC dst_second_rc = rc_class(dst_second);
1325 enum RC dst_first_rc = rc_class(dst_first);
1326
1327 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1328
1329 // Generate spill code!
1330 int size = 0;
1331
1332 if( src_first == dst_first && src_second == dst_second )
1333 return size; // Self copy, no move
1334
1335 // --------------------------------------
1336 // Check for mem-mem move. Load into unused float registers and fall into
1337 // the float-store case.
1338 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1339 int offset = ra_->reg2offset(src_first);
1340 // Further check for aligned-adjacent pair, so we can use a double load
1341 if( (src_first&1)==0 && src_first+1 == src_second ) {
1342 src_second = OptoReg::Name(R_F31_num);
1343 src_second_rc = rc_float;
1344 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1345 } else {
1346 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1347 }
1348 src_first = OptoReg::Name(R_F30_num);
1349 src_first_rc = rc_float;
1350 }
1351
1352 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1353 int offset = ra_->reg2offset(src_second);
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1355 src_second = OptoReg::Name(R_F31_num);
1356 src_second_rc = rc_float;
1357 }
1358
1359 // --------------------------------------
1360 // Check for float->int copy; requires a trip through memory
1361 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1362 int offset = frame::register_save_words*wordSize;
1363 if (cbuf) {
1364 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1365 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1366 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1368 }
1369 #ifndef PRODUCT
1370 else if (!do_size) {
1371 if (size != 0) st->print("\n\t");
1372 st->print( "SUB R_SP,16,R_SP\n");
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1375 st->print("\tADD R_SP,16,R_SP\n");
1376 }
1377 #endif
1378 size += 16;
1379 }
1380
1381 // Check for float->int copy on T4
1382 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1383 // Further check for aligned-adjacent pair, so we can use a double move
1384 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1385 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1386 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1387 }
1388 // Check for int->float copy on T4
1389 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1390 // Further check for aligned-adjacent pair, so we can use a double move
1391 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1392 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1393 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1394 }
1395
1396 // --------------------------------------
1397 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1398 // In such cases, I have to do the big-endian swap. For aligned targets, the
1399 // hardware does the flop for me. Doubles are always aligned, so no problem
1400 // there. Misaligned sources only come from native-long-returns (handled
1401 // special below).
1402 #ifndef _LP64
1403 if( src_first_rc == rc_int && // source is already big-endian
1404 src_second_rc != rc_bad && // 64-bit move
1405 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1406 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1407 // Do the big-endian flop.
1408 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1409 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1410 }
1411 #endif
1412
1413 // --------------------------------------
1414 // Check for integer reg-reg copy
1415 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1416 #ifndef _LP64
1417 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1418 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1419 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1420 // operand contains the least significant word of the 64-bit value and vice versa.
1421 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1422 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1423 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1424 if( cbuf ) {
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1428 #ifndef PRODUCT
1429 } else if( !do_size ) {
1430 if( size != 0 ) st->print("\n\t");
1431 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1432 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1433 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1434 #endif
1435 }
1436 return size+12;
1437 }
1438 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1439 // returning a long value in I0/I1
1440 // a SpillCopy must be able to target a return instruction's reg_class
1441 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1442 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1443 // operand contains the least significant word of the 64-bit value and vice versa.
1444 OptoReg::Name tdest = dst_first;
1445
1446 if (src_first == dst_first) {
1447 tdest = OptoReg::Name(R_O7_num);
1448 size += 4;
1449 }
1450
1451 if( cbuf ) {
1452 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1453 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1454 // ShrL_reg_imm6
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1456 // ShrR_reg_imm6 src, 0, dst
1457 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1458 if (tdest != dst_first) {
1459 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1460 }
1461 }
1462 #ifndef PRODUCT
1463 else if( !do_size ) {
1464 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1465 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1466 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1467 if (tdest != dst_first) {
1468 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1469 }
1470 }
1471 #endif // PRODUCT
1472 return size+8;
1473 }
1474 #endif // !_LP64
1475 // Else normal reg-reg copy
1476 assert( src_second != dst_first, "smashed second before evacuating it" );
1477 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1478 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1479 // This moves an aligned adjacent pair.
1480 // See if we are done.
1481 if( src_first+1 == src_second && dst_first+1 == dst_second )
1482 return size;
1483 }
1484
1485 // Check for integer store
1486 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1487 int offset = ra_->reg2offset(dst_first);
1488 // Further check for aligned-adjacent pair, so we can use a double store
1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1490 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1491 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1492 }
1493
1494 // Check for integer load
1495 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1496 int offset = ra_->reg2offset(src_first);
1497 // Further check for aligned-adjacent pair, so we can use a double load
1498 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1499 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1500 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1501 }
1502
1503 // Check for float reg-reg copy
1504 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1505 // Further check for aligned-adjacent pair, so we can use a double move
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1507 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1508 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1509 }
1510
1511 // Check for float store
1512 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1513 int offset = ra_->reg2offset(dst_first);
1514 // Further check for aligned-adjacent pair, so we can use a double store
1515 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1516 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1517 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1518 }
1519
1520 // Check for float load
1521 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1522 int offset = ra_->reg2offset(src_first);
1523 // Further check for aligned-adjacent pair, so we can use a double load
1524 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1525 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1526 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1527 }
1528
1529 // --------------------------------------------------------------------
1530 // Check for hi bits still needing moving. Only happens for misaligned
1531 // arguments to native calls.
1532 if( src_second == dst_second )
1533 return size; // Self copy; no move
1534 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1535
1536 #ifndef _LP64
1537 // In the LP64 build, all registers can be moved as aligned/adjacent
1538 // pairs, so there's never any need to move the high bits separately.
1539 // The 32-bit builds have to deal with the 32-bit ABI which can force
1540 // all sorts of silly alignment problems.
1541
1542 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1543 // 32-bits of a 64-bit register, but are needed in low bits of another
1544 // register (else it's a hi-bits-to-hi-bits copy which should have
1545 // happened already as part of a 64-bit move)
1546 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1547 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1548 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1549 // Shift src_second down to dst_second's low bits.
1550 if( cbuf ) {
1551 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1552 #ifndef PRODUCT
1553 } else if( !do_size ) {
1554 if( size != 0 ) st->print("\n\t");
1555 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1556 #endif
1557 }
1558 return size+4;
1559 }
1560
1561 // Check for high word integer store. Must down-shift the hi bits
1562 // into a temp register, then fall into the case of storing int bits.
1563 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1564 // Shift src_second down to dst_second's low bits.
1565 if( cbuf ) {
1566 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1567 #ifndef PRODUCT
1568 } else if( !do_size ) {
1569 if( size != 0 ) st->print("\n\t");
1570 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1571 #endif
1572 }
1573 size+=4;
1574 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1575 }
1576
1577 // Check for high word integer load
1578 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1579 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1580
1581 // Check for high word integer store
1582 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1583 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1584
1585 // Check for high word float store
1586 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1587 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1588
1589 #endif // !_LP64
1590
1591 Unimplemented();
1592 }
1593
1594 #ifndef PRODUCT
1595 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1596 implementation( NULL, ra_, false, st );
1597 }
1598 #endif
1599
1600 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1601 implementation( &cbuf, ra_, false, NULL );
1602 }
1603
1604 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1605 return implementation( NULL, ra_, true, NULL );
1606 }
1607
1608 //=============================================================================
1609 #ifndef PRODUCT
1610 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1611 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1612 }
1613 #endif
1614
1615 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1616 MacroAssembler _masm(&cbuf);
1617 for(int i = 0; i < _count; i += 1) {
1618 __ nop();
1619 }
1620 }
1621
1622 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1623 return 4 * _count;
1624 }
1625
1626
1627 //=============================================================================
1628 #ifndef PRODUCT
1629 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1630 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1631 int reg = ra_->get_reg_first(this);
1632 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1633 }
1634 #endif
1635
1636 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1637 MacroAssembler _masm(&cbuf);
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1639 int reg = ra_->get_encode(this);
1640
1641 if (Assembler::is_simm13(offset)) {
1642 __ add(SP, offset, reg_to_register_object(reg));
1643 } else {
1644 __ set(offset, O7);
1645 __ add(SP, O7, reg_to_register_object(reg));
1646 }
1647 }
1648
1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1650 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1651 assert(ra_ == ra_->C->regalloc(), "sanity");
1652 return ra_->C->scratch_emit_size(this);
1653 }
1654
1655 //=============================================================================
1656 #ifndef PRODUCT
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 st->print_cr("\nUEP:");
1659 #ifdef _LP64
1660 if (UseCompressedClassPointers) {
1661 assert(Universe::heap() != NULL, "java heap should be initialized");
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1663 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1664 if (Universe::narrow_klass_shift() != 0) {
1665 st->print_cr("\tSLL R_G5,3,R_G5");
1666 }
1667 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1668 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1669 } else {
1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1671 }
1672 st->print_cr("\tCMP R_G5,R_G3" );
1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1674 #else // _LP64
1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 st->print_cr("\tCMP R_G5,R_G3" );
1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1678 #endif // _LP64
1679 }
1680 #endif
1681
1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1683 MacroAssembler _masm(&cbuf);
1684 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1685 Register temp_reg = G3;
1686 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1687
1688 // Load klass from receiver
1689 __ load_klass(O0, temp_reg);
1690 // Compare against expected klass
1691 __ cmp(temp_reg, G5_ic_reg);
1692 // Branch to miss code, checks xcc or icc depending
1693 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1694 }
1695
1696 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1697 return MachNode::size(ra_);
1698 }
1699
1700
1701 //=============================================================================
1702
1703 uint size_exception_handler() {
1704 if (TraceJumps) {
1705 return (400); // just a guess
1706 }
1707 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1708 }
1709
1710 uint size_deopt_handler() {
1711 if (TraceJumps) {
1712 return (400); // just a guess
1713 }
1714 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1715 }
1716
1717 // Emit exception handler code.
1718 int emit_exception_handler(CodeBuffer& cbuf) {
1719 Register temp_reg = G3;
1720 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1721 MacroAssembler _masm(&cbuf);
1722
1723 address base =
1724 __ start_a_stub(size_exception_handler());
1725 if (base == NULL) return 0; // CodeBuffer::expand failed
1726
1727 int offset = __ offset();
1728
1729 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1730 __ delayed()->nop();
1731
1732 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1733
1734 __ end_a_stub();
1735
1736 return offset;
1737 }
1738
1739 int emit_deopt_handler(CodeBuffer& cbuf) {
1740 // Can't use any of the current frame's registers as we may have deopted
1741 // at a poll and everything (including G3) can be live.
1742 Register temp_reg = L0;
1743 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1744 MacroAssembler _masm(&cbuf);
1745
1746 address base =
1747 __ start_a_stub(size_deopt_handler());
1748 if (base == NULL) return 0; // CodeBuffer::expand failed
1749
1750 int offset = __ offset();
1751 __ save_frame(0);
1752 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1753 __ delayed()->restore();
1754
1755 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1756
1757 __ end_a_stub();
1758 return offset;
1759
1760 }
1761
1762 // Given a register encoding, produce a Integer Register object
1763 static Register reg_to_register_object(int register_encoding) {
1764 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1765 return as_Register(register_encoding);
1766 }
1767
1768 // Given a register encoding, produce a single-precision Float Register object
1769 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1770 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1771 return as_SingleFloatRegister(register_encoding);
1772 }
1773
1774 // Given a register encoding, produce a double-precision Float Register object
1775 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1776 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1777 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1778 return as_DoubleFloatRegister(register_encoding);
1779 }
1780
1781 const bool Matcher::match_rule_supported(int opcode) {
1782 if (!has_match_rule(opcode))
1783 return false;
1784
1785 switch (opcode) {
1786 case Op_CountLeadingZerosI:
1787 case Op_CountLeadingZerosL:
1788 case Op_CountTrailingZerosI:
1789 case Op_CountTrailingZerosL:
1790 case Op_PopCountI:
1791 case Op_PopCountL:
1792 if (!UsePopCountInstruction)
1793 return false;
1794 case Op_CompareAndSwapL:
1795 #ifdef _LP64
1796 case Op_CompareAndSwapP:
1797 #endif
1798 if (!VM_Version::supports_cx8())
1799 return false;
1800 break;
1801 }
1802
1803 return true; // Per default match rules are supported.
1804 }
1805
1806 int Matcher::regnum_to_fpu_offset(int regnum) {
1807 return regnum - 32; // The FP registers are in the second chunk
1808 }
1809
1810 #ifdef ASSERT
1811 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1812 #endif
1813
1814 // Vector width in bytes
1815 const int Matcher::vector_width_in_bytes(BasicType bt) {
1816 assert(MaxVectorSize == 8, "");
1817 return 8;
1818 }
1819
1820 // Vector ideal reg
1821 const int Matcher::vector_ideal_reg(int size) {
1822 assert(MaxVectorSize == 8, "");
1823 return Op_RegD;
1824 }
1825
1826 const int Matcher::vector_shift_count_ideal_reg(int size) {
1827 fatal("vector shift is not supported");
1828 return Node::NotAMachineReg;
1829 }
1830
1831 // Limits on vector size (number of elements) loaded into vector.
1832 const int Matcher::max_vector_size(const BasicType bt) {
1833 assert(is_java_primitive(bt), "only primitive type vectors");
1834 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1835 }
1836
1837 const int Matcher::min_vector_size(const BasicType bt) {
1838 return max_vector_size(bt); // Same as max.
1839 }
1840
1841 // SPARC doesn't support misaligned vectors store/load.
1842 const bool Matcher::misaligned_vectors_ok() {
1843 return false;
1844 }
1845
1846 // USII supports fxtof through the whole range of number, USIII doesn't
1847 const bool Matcher::convL2FSupported(void) {
1848 return VM_Version::has_fast_fxtof();
1849 }
1850
1851 // Is this branch offset short enough that a short branch can be used?
1852 //
1853 // NOTE: If the platform does not provide any short branch variants, then
1854 // this method should return false for offset 0.
1855 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1856 // The passed offset is relative to address of the branch.
1857 // Don't need to adjust the offset.
1858 return UseCBCond && Assembler::is_simm12(offset);
1859 }
1860
1861 const bool Matcher::isSimpleConstant64(jlong value) {
1862 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1863 // Depends on optimizations in MacroAssembler::setx.
1864 int hi = (int)(value >> 32);
1865 int lo = (int)(value & ~0);
1866 return (hi == 0) || (hi == -1) || (lo == 0);
1867 }
1868
1869 // No scaling for the parameter the ClearArray node.
1870 const bool Matcher::init_array_count_is_in_bytes = true;
1871
1872 // Threshold size for cleararray.
1873 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1874
1875 // No additional cost for CMOVL.
1876 const int Matcher::long_cmove_cost() { return 0; }
1877
1878 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1879 const int Matcher::float_cmove_cost() {
1880 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1881 }
1882
1883 // Should the Matcher clone shifts on addressing modes, expecting them to
1884 // be subsumed into complex addressing expressions or compute them into
1885 // registers? True for Intel but false for most RISCs
1886 const bool Matcher::clone_shift_expressions = false;
1887
1888 // Do we need to mask the count passed to shift instructions or does
1889 // the cpu only look at the lower 5/6 bits anyway?
1890 const bool Matcher::need_masked_shift_count = false;
1891
1892 bool Matcher::narrow_oop_use_complex_address() {
1893 NOT_LP64(ShouldNotCallThis());
1894 assert(UseCompressedOops, "only for compressed oops code");
1895 return false;
1896 }
1897
1898 bool Matcher::narrow_klass_use_complex_address() {
1899 NOT_LP64(ShouldNotCallThis());
1900 assert(UseCompressedClassPointers, "only for compressed klass code");
1901 return false;
1902 }
1903
1904 // Is it better to copy float constants, or load them directly from memory?
1905 // Intel can load a float constant from a direct address, requiring no
1906 // extra registers. Most RISCs will have to materialize an address into a
1907 // register first, so they would do better to copy the constant from stack.
1908 const bool Matcher::rematerialize_float_constants = false;
1909
1910 // If CPU can load and store mis-aligned doubles directly then no fixup is
1911 // needed. Else we split the double into 2 integer pieces and move it
1912 // piece-by-piece. Only happens when passing doubles into C code as the
1913 // Java calling convention forces doubles to be aligned.
1914 #ifdef _LP64
1915 const bool Matcher::misaligned_doubles_ok = true;
1916 #else
1917 const bool Matcher::misaligned_doubles_ok = false;
1918 #endif
1919
1920 // No-op on SPARC.
1921 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1922 }
1923
1924 // Advertise here if the CPU requires explicit rounding operations
1925 // to implement the UseStrictFP mode.
1926 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1927
1928 // Are floats conerted to double when stored to stack during deoptimization?
1929 // Sparc does not handle callee-save floats.
1930 bool Matcher::float_in_double() { return false; }
1931
1932 // Do ints take an entire long register or just half?
1933 // Note that we if-def off of _LP64.
1934 // The relevant question is how the int is callee-saved. In _LP64
1935 // the whole long is written but de-opt'ing will have to extract
1936 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1937 #ifdef _LP64
1938 const bool Matcher::int_in_long = true;
1939 #else
1940 const bool Matcher::int_in_long = false;
1941 #endif
1942
1943 // Return whether or not this register is ever used as an argument. This
1944 // function is used on startup to build the trampoline stubs in generateOptoStub.
1945 // Registers not mentioned will be killed by the VM call in the trampoline, and
1946 // arguments in those registers not be available to the callee.
1947 bool Matcher::can_be_java_arg( int reg ) {
1948 // Standard sparc 6 args in registers
1949 if( reg == R_I0_num ||
1950 reg == R_I1_num ||
1951 reg == R_I2_num ||
1952 reg == R_I3_num ||
1953 reg == R_I4_num ||
1954 reg == R_I5_num ) return true;
1955 #ifdef _LP64
1956 // 64-bit builds can pass 64-bit pointers and longs in
1957 // the high I registers
1958 if( reg == R_I0H_num ||
1959 reg == R_I1H_num ||
1960 reg == R_I2H_num ||
1961 reg == R_I3H_num ||
1962 reg == R_I4H_num ||
1963 reg == R_I5H_num ) return true;
1964
1965 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1966 return true;
1967 }
1968
1969 #else
1970 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1971 // Longs cannot be passed in O regs, because O regs become I regs
1972 // after a 'save' and I regs get their high bits chopped off on
1973 // interrupt.
1974 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1975 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1976 #endif
1977 // A few float args in registers
1978 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1979
1980 return false;
1981 }
1982
1983 bool Matcher::is_spillable_arg( int reg ) {
1984 return can_be_java_arg(reg);
1985 }
1986
1987 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1988 // Use hardware SDIVX instruction when it is
1989 // faster than a code which use multiply.
1990 return VM_Version::has_fast_idiv();
1991 }
1992
1993 // Register for DIVI projection of divmodI
1994 RegMask Matcher::divI_proj_mask() {
1995 ShouldNotReachHere();
1996 return RegMask();
1997 }
1998
1999 // Register for MODI projection of divmodI
2000 RegMask Matcher::modI_proj_mask() {
2001 ShouldNotReachHere();
2002 return RegMask();
2003 }
2004
2005 // Register for DIVL projection of divmodL
2006 RegMask Matcher::divL_proj_mask() {
2007 ShouldNotReachHere();
2008 return RegMask();
2009 }
2010
2011 // Register for MODL projection of divmodL
2012 RegMask Matcher::modL_proj_mask() {
2013 ShouldNotReachHere();
2014 return RegMask();
2015 }
2016
2017 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2018 return L7_REGP_mask();
2019 }
2020
2021 const RegMask Matcher::mathExactI_result_proj_mask() {
2022 return G1_REGI_mask();
2023 }
2024
2025 const RegMask Matcher::mathExactL_result_proj_mask() {
2026 return G1_REGL_mask();
2027 }
2028
2029 const RegMask Matcher::mathExactI_flags_proj_mask() {
2030 return INT_FLAGS_mask();
2031 }
2032
2033
2034 %}
2035
2036
2037 // The intptr_t operand types, defined by textual substitution.
2038 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2039 #ifdef _LP64
2040 #define immX immL
2041 #define immX13 immL13
2042 #define immX13m7 immL13m7
2043 #define iRegX iRegL
2044 #define g1RegX g1RegL
2045 #else
2046 #define immX immI
2047 #define immX13 immI13
2048 #define immX13m7 immI13m7
2049 #define iRegX iRegI
2050 #define g1RegX g1RegI
2051 #endif
2052
2053 //----------ENCODING BLOCK-----------------------------------------------------
2054 // This block specifies the encoding classes used by the compiler to output
2055 // byte streams. Encoding classes are parameterized macros used by
2056 // Machine Instruction Nodes in order to generate the bit encoding of the
2057 // instruction. Operands specify their base encoding interface with the
2058 // interface keyword. There are currently supported four interfaces,
2059 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2060 // operand to generate a function which returns its register number when
2061 // queried. CONST_INTER causes an operand to generate a function which
2062 // returns the value of the constant when queried. MEMORY_INTER causes an
2063 // operand to generate four functions which return the Base Register, the
2064 // Index Register, the Scale Value, and the Offset Value of the operand when
2065 // queried. COND_INTER causes an operand to generate six functions which
2066 // return the encoding code (ie - encoding bits for the instruction)
2067 // associated with each basic boolean condition for a conditional instruction.
2068 //
2069 // Instructions specify two basic values for encoding. Again, a function
2070 // is available to check if the constant displacement is an oop. They use the
2071 // ins_encode keyword to specify their encoding classes (which must be
2072 // a sequence of enc_class names, and their parameters, specified in
2073 // the encoding block), and they use the
2074 // opcode keyword to specify, in order, their primary, secondary, and
2075 // tertiary opcode. Only the opcode sections which a particular instruction
2076 // needs for encoding need to be specified.
2077 encode %{
2078 enc_class enc_untested %{
2079 #ifdef ASSERT
2080 MacroAssembler _masm(&cbuf);
2081 __ untested("encoding");
2082 #endif
2083 %}
2084
2085 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2086 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2087 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2088 %}
2089
2090 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2091 emit_form3_mem_reg(cbuf, this, $primary, -1,
2092 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2093 %}
2094
2095 enc_class form3_mem_prefetch_read( memory mem ) %{
2096 emit_form3_mem_reg(cbuf, this, $primary, -1,
2097 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2098 %}
2099
2100 enc_class form3_mem_prefetch_write( memory mem ) %{
2101 emit_form3_mem_reg(cbuf, this, $primary, -1,
2102 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2103 %}
2104
2105 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2106 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2107 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2108 guarantee($mem$$index == R_G0_enc, "double index?");
2109 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2110 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2111 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2112 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2113 %}
2114
2115 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2116 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2117 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2118 guarantee($mem$$index == R_G0_enc, "double index?");
2119 // Load long with 2 instructions
2120 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2121 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2122 %}
2123
2124 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2125 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2126 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2127 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2128 %}
2129
2130 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2131 // Encode a reg-reg copy. If it is useless, then empty encoding.
2132 if( $rs2$$reg != $rd$$reg )
2133 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2134 %}
2135
2136 // Target lo half of long
2137 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2138 // Encode a reg-reg copy. If it is useless, then empty encoding.
2139 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2140 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2141 %}
2142
2143 // Source lo half of long
2144 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2145 // Encode a reg-reg copy. If it is useless, then empty encoding.
2146 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2147 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2148 %}
2149
2150 // Target hi half of long
2151 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2152 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2153 %}
2154
2155 // Source lo half of long, and leave it sign extended.
2156 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2157 // Sign extend low half
2158 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2159 %}
2160
2161 // Source hi half of long, and leave it sign extended.
2162 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2163 // Shift high half to low half
2164 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2165 %}
2166
2167 // Source hi half of long
2168 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2169 // Encode a reg-reg copy. If it is useless, then empty encoding.
2170 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2171 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2172 %}
2173
2174 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2175 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2176 %}
2177
2178 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2179 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2180 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2181 %}
2182
2183 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2184 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2185 // clear if nothing else is happening
2186 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2187 // blt,a,pn done
2188 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2189 // mov dst,-1 in delay slot
2190 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2191 %}
2192
2193 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2194 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2195 %}
2196
2197 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2198 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2199 %}
2200
2201 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2202 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2203 %}
2204
2205 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2206 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2207 %}
2208
2209 enc_class move_return_pc_to_o1() %{
2210 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2211 %}
2212
2213 #ifdef _LP64
2214 /* %%% merge with enc_to_bool */
2215 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2216 MacroAssembler _masm(&cbuf);
2217
2218 Register src_reg = reg_to_register_object($src$$reg);
2219 Register dst_reg = reg_to_register_object($dst$$reg);
2220 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2221 %}
2222 #endif
2223
2224 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2225 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2226 MacroAssembler _masm(&cbuf);
2227
2228 Register p_reg = reg_to_register_object($p$$reg);
2229 Register q_reg = reg_to_register_object($q$$reg);
2230 Register y_reg = reg_to_register_object($y$$reg);
2231 Register tmp_reg = reg_to_register_object($tmp$$reg);
2232
2233 __ subcc( p_reg, q_reg, p_reg );
2234 __ add ( p_reg, y_reg, tmp_reg );
2235 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2236 %}
2237
2238 enc_class form_d2i_helper(regD src, regF dst) %{
2239 // fcmp %fcc0,$src,$src
2240 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2241 // branch %fcc0 not-nan, predict taken
2242 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2243 // fdtoi $src,$dst
2244 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2245 // fitos $dst,$dst (if nan)
2246 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2247 // clear $dst (if nan)
2248 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2249 // carry on here...
2250 %}
2251
2252 enc_class form_d2l_helper(regD src, regD dst) %{
2253 // fcmp %fcc0,$src,$src check for NAN
2254 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2255 // branch %fcc0 not-nan, predict taken
2256 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2257 // fdtox $src,$dst convert in delay slot
2258 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2259 // fxtod $dst,$dst (if nan)
2260 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2261 // clear $dst (if nan)
2262 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2263 // carry on here...
2264 %}
2265
2266 enc_class form_f2i_helper(regF src, regF dst) %{
2267 // fcmps %fcc0,$src,$src
2268 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2269 // branch %fcc0 not-nan, predict taken
2270 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2271 // fstoi $src,$dst
2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2273 // fitos $dst,$dst (if nan)
2274 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2275 // clear $dst (if nan)
2276 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2277 // carry on here...
2278 %}
2279
2280 enc_class form_f2l_helper(regF src, regD dst) %{
2281 // fcmps %fcc0,$src,$src
2282 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2283 // branch %fcc0 not-nan, predict taken
2284 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2285 // fstox $src,$dst
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2287 // fxtod $dst,$dst (if nan)
2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2289 // clear $dst (if nan)
2290 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2291 // carry on here...
2292 %}
2293
2294 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2295 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2296 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2297 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2298
2299 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2300
2301 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2302 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2303
2304 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2305 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2306 %}
2307
2308 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2309 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2310 %}
2311
2312 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2313 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2314 %}
2315
2316 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2317 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2318 %}
2319
2320 enc_class form3_convI2F(regF rs2, regF rd) %{
2321 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2322 %}
2323
2324 // Encloding class for traceable jumps
2325 enc_class form_jmpl(g3RegP dest) %{
2326 emit_jmpl(cbuf, $dest$$reg);
2327 %}
2328
2329 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2330 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2331 %}
2332
2333 enc_class form2_nop() %{
2334 emit_nop(cbuf);
2335 %}
2336
2337 enc_class form2_illtrap() %{
2338 emit_illtrap(cbuf);
2339 %}
2340
2341
2342 // Compare longs and convert into -1, 0, 1.
2343 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2344 // CMP $src1,$src2
2345 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2346 // blt,a,pn done
2347 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2348 // mov dst,-1 in delay slot
2349 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2350 // bgt,a,pn done
2351 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2352 // mov dst,1 in delay slot
2353 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2354 // CLR $dst
2355 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2356 %}
2357
2358 enc_class enc_PartialSubtypeCheck() %{
2359 MacroAssembler _masm(&cbuf);
2360 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2361 __ delayed()->nop();
2362 %}
2363
2364 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2365 MacroAssembler _masm(&cbuf);
2366 Label* L = $labl$$label;
2367 Assembler::Predict predict_taken =
2368 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2369
2370 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2371 __ delayed()->nop();
2372 %}
2373
2374 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2375 MacroAssembler _masm(&cbuf);
2376 Label* L = $labl$$label;
2377 Assembler::Predict predict_taken =
2378 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2379
2380 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2381 __ delayed()->nop();
2382 %}
2383
2384 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2385 int op = (Assembler::arith_op << 30) |
2386 ($dst$$reg << 25) |
2387 (Assembler::movcc_op3 << 19) |
2388 (1 << 18) | // cc2 bit for 'icc'
2389 ($cmp$$cmpcode << 14) |
2390 (0 << 13) | // select register move
2391 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2392 ($src$$reg << 0);
2393 cbuf.insts()->emit_int32(op);
2394 %}
2395
2396 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2397 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2398 int op = (Assembler::arith_op << 30) |
2399 ($dst$$reg << 25) |
2400 (Assembler::movcc_op3 << 19) |
2401 (1 << 18) | // cc2 bit for 'icc'
2402 ($cmp$$cmpcode << 14) |
2403 (1 << 13) | // select immediate move
2404 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2405 (simm11 << 0);
2406 cbuf.insts()->emit_int32(op);
2407 %}
2408
2409 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2410 int op = (Assembler::arith_op << 30) |
2411 ($dst$$reg << 25) |
2412 (Assembler::movcc_op3 << 19) |
2413 (0 << 18) | // cc2 bit for 'fccX'
2414 ($cmp$$cmpcode << 14) |
2415 (0 << 13) | // select register move
2416 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2417 ($src$$reg << 0);
2418 cbuf.insts()->emit_int32(op);
2419 %}
2420
2421 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2422 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2423 int op = (Assembler::arith_op << 30) |
2424 ($dst$$reg << 25) |
2425 (Assembler::movcc_op3 << 19) |
2426 (0 << 18) | // cc2 bit for 'fccX'
2427 ($cmp$$cmpcode << 14) |
2428 (1 << 13) | // select immediate move
2429 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2430 (simm11 << 0);
2431 cbuf.insts()->emit_int32(op);
2432 %}
2433
2434 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2435 int op = (Assembler::arith_op << 30) |
2436 ($dst$$reg << 25) |
2437 (Assembler::fpop2_op3 << 19) |
2438 (0 << 18) |
2439 ($cmp$$cmpcode << 14) |
2440 (1 << 13) | // select register move
2441 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2442 ($primary << 5) | // select single, double or quad
2443 ($src$$reg << 0);
2444 cbuf.insts()->emit_int32(op);
2445 %}
2446
2447 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2448 int op = (Assembler::arith_op << 30) |
2449 ($dst$$reg << 25) |
2450 (Assembler::fpop2_op3 << 19) |
2451 (0 << 18) |
2452 ($cmp$$cmpcode << 14) |
2453 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2454 ($primary << 5) | // select single, double or quad
2455 ($src$$reg << 0);
2456 cbuf.insts()->emit_int32(op);
2457 %}
2458
2459 // Used by the MIN/MAX encodings. Same as a CMOV, but
2460 // the condition comes from opcode-field instead of an argument.
2461 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2462 int op = (Assembler::arith_op << 30) |
2463 ($dst$$reg << 25) |
2464 (Assembler::movcc_op3 << 19) |
2465 (1 << 18) | // cc2 bit for 'icc'
2466 ($primary << 14) |
2467 (0 << 13) | // select register move
2468 (0 << 11) | // cc1, cc0 bits for 'icc'
2469 ($src$$reg << 0);
2470 cbuf.insts()->emit_int32(op);
2471 %}
2472
2473 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2474 int op = (Assembler::arith_op << 30) |
2475 ($dst$$reg << 25) |
2476 (Assembler::movcc_op3 << 19) |
2477 (6 << 16) | // cc2 bit for 'xcc'
2478 ($primary << 14) |
2479 (0 << 13) | // select register move
2480 (0 << 11) | // cc1, cc0 bits for 'icc'
2481 ($src$$reg << 0);
2482 cbuf.insts()->emit_int32(op);
2483 %}
2484
2485 enc_class Set13( immI13 src, iRegI rd ) %{
2486 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2487 %}
2488
2489 enc_class SetHi22( immI src, iRegI rd ) %{
2490 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2491 %}
2492
2493 enc_class Set32( immI src, iRegI rd ) %{
2494 MacroAssembler _masm(&cbuf);
2495 __ set($src$$constant, reg_to_register_object($rd$$reg));
2496 %}
2497
2498 enc_class call_epilog %{
2499 if( VerifyStackAtCalls ) {
2500 MacroAssembler _masm(&cbuf);
2501 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2502 Register temp_reg = G3;
2503 __ add(SP, framesize, temp_reg);
2504 __ cmp(temp_reg, FP);
2505 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2506 }
2507 %}
2508
2509 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2510 // to G1 so the register allocator will not have to deal with the misaligned register
2511 // pair.
2512 enc_class adjust_long_from_native_call %{
2513 #ifndef _LP64
2514 if (returns_long()) {
2515 // sllx O0,32,O0
2516 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2517 // srl O1,0,O1
2518 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2519 // or O0,O1,G1
2520 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2521 }
2522 #endif
2523 %}
2524
2525 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2526 // CALL directly to the runtime
2527 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2528 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2529 /*preserve_g2=*/true);
2530 %}
2531
2532 enc_class preserve_SP %{
2533 MacroAssembler _masm(&cbuf);
2534 __ mov(SP, L7_mh_SP_save);
2535 %}
2536
2537 enc_class restore_SP %{
2538 MacroAssembler _masm(&cbuf);
2539 __ mov(L7_mh_SP_save, SP);
2540 %}
2541
2542 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2543 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2544 // who we intended to call.
2545 if (!_method) {
2546 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2547 } else if (_optimized_virtual) {
2548 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2549 } else {
2550 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2551 }
2552 if (_method) { // Emit stub for static call.
2553 CompiledStaticCall::emit_to_interp_stub(cbuf);
2554 }
2555 %}
2556
2557 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2558 MacroAssembler _masm(&cbuf);
2559 __ set_inst_mark();
2560 int vtable_index = this->_vtable_index;
2561 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2562 if (vtable_index < 0) {
2563 // must be invalid_vtable_index, not nonvirtual_vtable_index
2564 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2565 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2566 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2567 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2568 __ ic_call((address)$meth$$method);
2569 } else {
2570 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2571 // Just go thru the vtable
2572 // get receiver klass (receiver already checked for non-null)
2573 // If we end up going thru a c2i adapter interpreter expects method in G5
2574 int off = __ offset();
2575 __ load_klass(O0, G3_scratch);
2576 int klass_load_size;
2577 if (UseCompressedClassPointers) {
2578 assert(Universe::heap() != NULL, "java heap should be initialized");
2579 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2580 } else {
2581 klass_load_size = 1*BytesPerInstWord;
2582 }
2583 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2584 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2585 if (Assembler::is_simm13(v_off)) {
2586 __ ld_ptr(G3, v_off, G5_method);
2587 } else {
2588 // Generate 2 instructions
2589 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2590 __ or3(G5_method, v_off & 0x3ff, G5_method);
2591 // ld_ptr, set_hi, set
2592 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2593 "Unexpected instruction size(s)");
2594 __ ld_ptr(G3, G5_method, G5_method);
2595 }
2596 // NOTE: for vtable dispatches, the vtable entry will never be null.
2597 // However it may very well end up in handle_wrong_method if the
2598 // method is abstract for the particular class.
2599 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2600 // jump to target (either compiled code or c2iadapter)
2601 __ jmpl(G3_scratch, G0, O7);
2602 __ delayed()->nop();
2603 }
2604 %}
2605
2606 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2607 MacroAssembler _masm(&cbuf);
2608
2609 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2610 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2611 // we might be calling a C2I adapter which needs it.
2612
2613 assert(temp_reg != G5_ic_reg, "conflicting registers");
2614 // Load nmethod
2615 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2616
2617 // CALL to compiled java, indirect the contents of G3
2618 __ set_inst_mark();
2619 __ callr(temp_reg, G0);
2620 __ delayed()->nop();
2621 %}
2622
2623 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2624 MacroAssembler _masm(&cbuf);
2625 Register Rdividend = reg_to_register_object($src1$$reg);
2626 Register Rdivisor = reg_to_register_object($src2$$reg);
2627 Register Rresult = reg_to_register_object($dst$$reg);
2628
2629 __ sra(Rdivisor, 0, Rdivisor);
2630 __ sra(Rdividend, 0, Rdividend);
2631 __ sdivx(Rdividend, Rdivisor, Rresult);
2632 %}
2633
2634 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2635 MacroAssembler _masm(&cbuf);
2636
2637 Register Rdividend = reg_to_register_object($src1$$reg);
2638 int divisor = $imm$$constant;
2639 Register Rresult = reg_to_register_object($dst$$reg);
2640
2641 __ sra(Rdividend, 0, Rdividend);
2642 __ sdivx(Rdividend, divisor, Rresult);
2643 %}
2644
2645 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2646 MacroAssembler _masm(&cbuf);
2647 Register Rsrc1 = reg_to_register_object($src1$$reg);
2648 Register Rsrc2 = reg_to_register_object($src2$$reg);
2649 Register Rdst = reg_to_register_object($dst$$reg);
2650
2651 __ sra( Rsrc1, 0, Rsrc1 );
2652 __ sra( Rsrc2, 0, Rsrc2 );
2653 __ mulx( Rsrc1, Rsrc2, Rdst );
2654 __ srlx( Rdst, 32, Rdst );
2655 %}
2656
2657 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2658 MacroAssembler _masm(&cbuf);
2659 Register Rdividend = reg_to_register_object($src1$$reg);
2660 Register Rdivisor = reg_to_register_object($src2$$reg);
2661 Register Rresult = reg_to_register_object($dst$$reg);
2662 Register Rscratch = reg_to_register_object($scratch$$reg);
2663
2664 assert(Rdividend != Rscratch, "");
2665 assert(Rdivisor != Rscratch, "");
2666
2667 __ sra(Rdividend, 0, Rdividend);
2668 __ sra(Rdivisor, 0, Rdivisor);
2669 __ sdivx(Rdividend, Rdivisor, Rscratch);
2670 __ mulx(Rscratch, Rdivisor, Rscratch);
2671 __ sub(Rdividend, Rscratch, Rresult);
2672 %}
2673
2674 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2675 MacroAssembler _masm(&cbuf);
2676
2677 Register Rdividend = reg_to_register_object($src1$$reg);
2678 int divisor = $imm$$constant;
2679 Register Rresult = reg_to_register_object($dst$$reg);
2680 Register Rscratch = reg_to_register_object($scratch$$reg);
2681
2682 assert(Rdividend != Rscratch, "");
2683
2684 __ sra(Rdividend, 0, Rdividend);
2685 __ sdivx(Rdividend, divisor, Rscratch);
2686 __ mulx(Rscratch, divisor, Rscratch);
2687 __ sub(Rdividend, Rscratch, Rresult);
2688 %}
2689
2690 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2691 MacroAssembler _masm(&cbuf);
2692
2693 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2694 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2695
2696 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2697 %}
2698
2699 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2700 MacroAssembler _masm(&cbuf);
2701
2702 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2703 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2704
2705 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2706 %}
2707
2708 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2709 MacroAssembler _masm(&cbuf);
2710
2711 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2712 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2713
2714 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2715 %}
2716
2717 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2718 MacroAssembler _masm(&cbuf);
2719
2720 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2721 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2722
2723 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2724 %}
2725
2726 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2727 MacroAssembler _masm(&cbuf);
2728
2729 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2730 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2731
2732 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2733 %}
2734
2735 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2736 MacroAssembler _masm(&cbuf);
2737
2738 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2739 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2740
2741 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2742 %}
2743
2744 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2745 MacroAssembler _masm(&cbuf);
2746
2747 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2748 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2749
2750 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2751 %}
2752
2753 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2754 MacroAssembler _masm(&cbuf);
2755
2756 Register Roop = reg_to_register_object($oop$$reg);
2757 Register Rbox = reg_to_register_object($box$$reg);
2758 Register Rscratch = reg_to_register_object($scratch$$reg);
2759 Register Rmark = reg_to_register_object($scratch2$$reg);
2760
2761 assert(Roop != Rscratch, "");
2762 assert(Roop != Rmark, "");
2763 assert(Rbox != Rscratch, "");
2764 assert(Rbox != Rmark, "");
2765
2766 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2767 %}
2768
2769 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2770 MacroAssembler _masm(&cbuf);
2771
2772 Register Roop = reg_to_register_object($oop$$reg);
2773 Register Rbox = reg_to_register_object($box$$reg);
2774 Register Rscratch = reg_to_register_object($scratch$$reg);
2775 Register Rmark = reg_to_register_object($scratch2$$reg);
2776
2777 assert(Roop != Rscratch, "");
2778 assert(Roop != Rmark, "");
2779 assert(Rbox != Rscratch, "");
2780 assert(Rbox != Rmark, "");
2781
2782 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2783 %}
2784
2785 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2786 MacroAssembler _masm(&cbuf);
2787 Register Rmem = reg_to_register_object($mem$$reg);
2788 Register Rold = reg_to_register_object($old$$reg);
2789 Register Rnew = reg_to_register_object($new$$reg);
2790
2791 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2792 __ cmp( Rold, Rnew );
2793 %}
2794
2795 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2796 Register Rmem = reg_to_register_object($mem$$reg);
2797 Register Rold = reg_to_register_object($old$$reg);
2798 Register Rnew = reg_to_register_object($new$$reg);
2799
2800 MacroAssembler _masm(&cbuf);
2801 __ mov(Rnew, O7);
2802 __ casx(Rmem, Rold, O7);
2803 __ cmp( Rold, O7 );
2804 %}
2805
2806 // raw int cas, used for compareAndSwap
2807 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2808 Register Rmem = reg_to_register_object($mem$$reg);
2809 Register Rold = reg_to_register_object($old$$reg);
2810 Register Rnew = reg_to_register_object($new$$reg);
2811
2812 MacroAssembler _masm(&cbuf);
2813 __ mov(Rnew, O7);
2814 __ cas(Rmem, Rold, O7);
2815 __ cmp( Rold, O7 );
2816 %}
2817
2818 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2819 Register Rres = reg_to_register_object($res$$reg);
2820
2821 MacroAssembler _masm(&cbuf);
2822 __ mov(1, Rres);
2823 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2824 %}
2825
2826 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2827 Register Rres = reg_to_register_object($res$$reg);
2828
2829 MacroAssembler _masm(&cbuf);
2830 __ mov(1, Rres);
2831 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2832 %}
2833
2834 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2835 MacroAssembler _masm(&cbuf);
2836 Register Rdst = reg_to_register_object($dst$$reg);
2837 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2838 : reg_to_DoubleFloatRegister_object($src1$$reg);
2839 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2840 : reg_to_DoubleFloatRegister_object($src2$$reg);
2841
2842 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2843 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2844 %}
2845
2846
2847 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2848 Label Ldone, Lloop;
2849 MacroAssembler _masm(&cbuf);
2850
2851 Register str1_reg = reg_to_register_object($str1$$reg);
2852 Register str2_reg = reg_to_register_object($str2$$reg);
2853 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2854 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2855 Register result_reg = reg_to_register_object($result$$reg);
2856
2857 assert(result_reg != str1_reg &&
2858 result_reg != str2_reg &&
2859 result_reg != cnt1_reg &&
2860 result_reg != cnt2_reg ,
2861 "need different registers");
2862
2863 // Compute the minimum of the string lengths(str1_reg) and the
2864 // difference of the string lengths (stack)
2865
2866 // See if the lengths are different, and calculate min in str1_reg.
2867 // Stash diff in O7 in case we need it for a tie-breaker.
2868 Label Lskip;
2869 __ subcc(cnt1_reg, cnt2_reg, O7);
2870 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2871 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2872 // cnt2 is shorter, so use its count:
2873 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2874 __ bind(Lskip);
2875
2876 // reallocate cnt1_reg, cnt2_reg, result_reg
2877 // Note: limit_reg holds the string length pre-scaled by 2
2878 Register limit_reg = cnt1_reg;
2879 Register chr2_reg = cnt2_reg;
2880 Register chr1_reg = result_reg;
2881 // str{12} are the base pointers
2882
2883 // Is the minimum length zero?
2884 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2885 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2886 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2887
2888 // Load first characters
2889 __ lduh(str1_reg, 0, chr1_reg);
2890 __ lduh(str2_reg, 0, chr2_reg);
2891
2892 // Compare first characters
2893 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2894 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2895 assert(chr1_reg == result_reg, "result must be pre-placed");
2896 __ delayed()->nop();
2897
2898 {
2899 // Check after comparing first character to see if strings are equivalent
2900 Label LSkip2;
2901 // Check if the strings start at same location
2902 __ cmp(str1_reg, str2_reg);
2903 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2904 __ delayed()->nop();
2905
2906 // Check if the length difference is zero (in O7)
2907 __ cmp(G0, O7);
2908 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2909 __ delayed()->mov(G0, result_reg); // result is zero
2910
2911 // Strings might not be equal
2912 __ bind(LSkip2);
2913 }
2914
2915 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2916 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2917 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2918
2919 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2920 __ add(str1_reg, limit_reg, str1_reg);
2921 __ add(str2_reg, limit_reg, str2_reg);
2922 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2923
2924 // Compare the rest of the characters
2925 __ lduh(str1_reg, limit_reg, chr1_reg);
2926 __ bind(Lloop);
2927 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2928 __ lduh(str2_reg, limit_reg, chr2_reg);
2929 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2930 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2931 assert(chr1_reg == result_reg, "result must be pre-placed");
2932 __ delayed()->inccc(limit_reg, sizeof(jchar));
2933 // annul LDUH if branch is not taken to prevent access past end of string
2934 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2935 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2936
2937 // If strings are equal up to min length, return the length difference.
2938 __ mov(O7, result_reg);
2939
2940 // Otherwise, return the difference between the first mismatched chars.
2941 __ bind(Ldone);
2942 %}
2943
2944 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2945 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2946 MacroAssembler _masm(&cbuf);
2947
2948 Register str1_reg = reg_to_register_object($str1$$reg);
2949 Register str2_reg = reg_to_register_object($str2$$reg);
2950 Register cnt_reg = reg_to_register_object($cnt$$reg);
2951 Register tmp1_reg = O7;
2952 Register result_reg = reg_to_register_object($result$$reg);
2953
2954 assert(result_reg != str1_reg &&
2955 result_reg != str2_reg &&
2956 result_reg != cnt_reg &&
2957 result_reg != tmp1_reg ,
2958 "need different registers");
2959
2960 __ cmp(str1_reg, str2_reg); //same char[] ?
2961 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2962 __ delayed()->add(G0, 1, result_reg);
2963
2964 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2965 __ delayed()->add(G0, 1, result_reg); // count == 0
2966
2967 //rename registers
2968 Register limit_reg = cnt_reg;
2969 Register chr1_reg = result_reg;
2970 Register chr2_reg = tmp1_reg;
2971
2972 //check for alignment and position the pointers to the ends
2973 __ or3(str1_reg, str2_reg, chr1_reg);
2974 __ andcc(chr1_reg, 0x3, chr1_reg);
2975 // notZero means at least one not 4-byte aligned.
2976 // We could optimize the case when both arrays are not aligned
2977 // but it is not frequent case and it requires additional checks.
2978 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2979 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2980
2981 // Compare char[] arrays aligned to 4 bytes.
2982 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2983 chr1_reg, chr2_reg, Ldone);
2984 __ ba(Ldone);
2985 __ delayed()->add(G0, 1, result_reg);
2986
2987 // char by char compare
2988 __ bind(Lchar);
2989 __ add(str1_reg, limit_reg, str1_reg);
2990 __ add(str2_reg, limit_reg, str2_reg);
2991 __ neg(limit_reg); //negate count
2992
2993 __ lduh(str1_reg, limit_reg, chr1_reg);
2994 // Lchar_loop
2995 __ bind(Lchar_loop);
2996 __ lduh(str2_reg, limit_reg, chr2_reg);
2997 __ cmp(chr1_reg, chr2_reg);
2998 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2999 __ delayed()->mov(G0, result_reg); //not equal
3000 __ inccc(limit_reg, sizeof(jchar));
3001 // annul LDUH if branch is not taken to prevent access past end of string
3002 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3003 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3004
3005 __ add(G0, 1, result_reg); //equal
3006
3007 __ bind(Ldone);
3008 %}
3009
3010 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3011 Label Lvector, Ldone, Lloop;
3012 MacroAssembler _masm(&cbuf);
3013
3014 Register ary1_reg = reg_to_register_object($ary1$$reg);
3015 Register ary2_reg = reg_to_register_object($ary2$$reg);
3016 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3017 Register tmp2_reg = O7;
3018 Register result_reg = reg_to_register_object($result$$reg);
3019
3020 int length_offset = arrayOopDesc::length_offset_in_bytes();
3021 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3022
3023 // return true if the same array
3024 __ cmp(ary1_reg, ary2_reg);
3025 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3026 __ delayed()->add(G0, 1, result_reg); // equal
3027
3028 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3029 __ delayed()->mov(G0, result_reg); // not equal
3030
3031 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3032 __ delayed()->mov(G0, result_reg); // not equal
3033
3034 //load the lengths of arrays
3035 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3036 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3037
3038 // return false if the two arrays are not equal length
3039 __ cmp(tmp1_reg, tmp2_reg);
3040 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3041 __ delayed()->mov(G0, result_reg); // not equal
3042
3043 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3044 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3045
3046 // load array addresses
3047 __ add(ary1_reg, base_offset, ary1_reg);
3048 __ add(ary2_reg, base_offset, ary2_reg);
3049
3050 // renaming registers
3051 Register chr1_reg = result_reg; // for characters in ary1
3052 Register chr2_reg = tmp2_reg; // for characters in ary2
3053 Register limit_reg = tmp1_reg; // length
3054
3055 // set byte count
3056 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3057
3058 // Compare char[] arrays aligned to 4 bytes.
3059 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3060 chr1_reg, chr2_reg, Ldone);
3061 __ add(G0, 1, result_reg); // equals
3062
3063 __ bind(Ldone);
3064 %}
3065
3066 enc_class enc_rethrow() %{
3067 cbuf.set_insts_mark();
3068 Register temp_reg = G3;
3069 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3070 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3071 MacroAssembler _masm(&cbuf);
3072 #ifdef ASSERT
3073 __ save_frame(0);
3074 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3075 __ sethi(last_rethrow_addrlit, L1);
3076 Address addr(L1, last_rethrow_addrlit.low10());
3077 __ rdpc(L2);
3078 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3079 __ st_ptr(L2, addr);
3080 __ restore();
3081 #endif
3082 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3083 __ delayed()->nop();
3084 %}
3085
3086 enc_class emit_mem_nop() %{
3087 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3088 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3089 %}
3090
3091 enc_class emit_fadd_nop() %{
3092 // Generates the instruction FMOVS f31,f31
3093 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3094 %}
3095
3096 enc_class emit_br_nop() %{
3097 // Generates the instruction BPN,PN .
3098 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3099 %}
3100
3101 enc_class enc_membar_acquire %{
3102 MacroAssembler _masm(&cbuf);
3103 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3104 %}
3105
3106 enc_class enc_membar_release %{
3107 MacroAssembler _masm(&cbuf);
3108 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3109 %}
3110
3111 enc_class enc_membar_volatile %{
3112 MacroAssembler _masm(&cbuf);
3113 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3114 %}
3115
3116 %}
3117
3118 //----------FRAME--------------------------------------------------------------
3119 // Definition of frame structure and management information.
3120 //
3121 // S T A C K L A Y O U T Allocators stack-slot number
3122 // | (to get allocators register number
3123 // G Owned by | | v add VMRegImpl::stack0)
3124 // r CALLER | |
3125 // o | +--------+ pad to even-align allocators stack-slot
3126 // w V | pad0 | numbers; owned by CALLER
3127 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3128 // h ^ | in | 5
3129 // | | args | 4 Holes in incoming args owned by SELF
3130 // | | | | 3
3131 // | | +--------+
3132 // V | | old out| Empty on Intel, window on Sparc
3133 // | old |preserve| Must be even aligned.
3134 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3135 // | | in | 3 area for Intel ret address
3136 // Owned by |preserve| Empty on Sparc.
3137 // SELF +--------+
3138 // | | pad2 | 2 pad to align old SP
3139 // | +--------+ 1
3140 // | | locks | 0
3141 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3142 // | | pad1 | 11 pad to align new SP
3143 // | +--------+
3144 // | | | 10
3145 // | | spills | 9 spills
3146 // V | | 8 (pad0 slot for callee)
3147 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3148 // ^ | out | 7
3149 // | | args | 6 Holes in outgoing args owned by CALLEE
3150 // Owned by +--------+
3151 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3152 // | new |preserve| Must be even-aligned.
3153 // | SP-+--------+----> Matcher::_new_SP, even aligned
3154 // | | |
3155 //
3156 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3157 // known from SELF's arguments and the Java calling convention.
3158 // Region 6-7 is determined per call site.
3159 // Note 2: If the calling convention leaves holes in the incoming argument
3160 // area, those holes are owned by SELF. Holes in the outgoing area
3161 // are owned by the CALLEE. Holes should not be nessecary in the
3162 // incoming area, as the Java calling convention is completely under
3163 // the control of the AD file. Doubles can be sorted and packed to
3164 // avoid holes. Holes in the outgoing arguments may be nessecary for
3165 // varargs C calling conventions.
3166 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3167 // even aligned with pad0 as needed.
3168 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3169 // region 6-11 is even aligned; it may be padded out more so that
3170 // the region from SP to FP meets the minimum stack alignment.
3171
3172 frame %{
3173 // What direction does stack grow in (assumed to be same for native & Java)
3174 stack_direction(TOWARDS_LOW);
3175
3176 // These two registers define part of the calling convention
3177 // between compiled code and the interpreter.
3178 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3179 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3180
3181 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3182 cisc_spilling_operand_name(indOffset);
3183
3184 // Number of stack slots consumed by a Monitor enter
3185 #ifdef _LP64
3186 sync_stack_slots(2);
3187 #else
3188 sync_stack_slots(1);
3189 #endif
3190
3191 // Compiled code's Frame Pointer
3192 frame_pointer(R_SP);
3193
3194 // Stack alignment requirement
3195 stack_alignment(StackAlignmentInBytes);
3196 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3197 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3198
3199 // Number of stack slots between incoming argument block and the start of
3200 // a new frame. The PROLOG must add this many slots to the stack. The
3201 // EPILOG must remove this many slots.
3202 in_preserve_stack_slots(0);
3203
3204 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3205 // for calls to C. Supports the var-args backing area for register parms.
3206 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3207 #ifdef _LP64
3208 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3209 varargs_C_out_slots_killed(12);
3210 #else
3211 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3212 varargs_C_out_slots_killed( 7);
3213 #endif
3214
3215 // The after-PROLOG location of the return address. Location of
3216 // return address specifies a type (REG or STACK) and a number
3217 // representing the register number (i.e. - use a register name) or
3218 // stack slot.
3219 return_addr(REG R_I7); // Ret Addr is in register I7
3220
3221 // Body of function which returns an OptoRegs array locating
3222 // arguments either in registers or in stack slots for calling
3223 // java
3224 calling_convention %{
3225 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3226
3227 %}
3228
3229 // Body of function which returns an OptoRegs array locating
3230 // arguments either in registers or in stack slots for callin
3231 // C.
3232 c_calling_convention %{
3233 // This is obviously always outgoing
3234 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3235 %}
3236
3237 // Location of native (C/C++) and interpreter return values. This is specified to
3238 // be the same as Java. In the 32-bit VM, long values are actually returned from
3239 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3240 // to and from the register pairs is done by the appropriate call and epilog
3241 // opcodes. This simplifies the register allocator.
3242 c_return_value %{
3243 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3244 #ifdef _LP64
3245 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3246 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3247 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3248 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3249 #else // !_LP64
3250 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3251 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3252 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3253 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3254 #endif
3255 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3256 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3257 %}
3258
3259 // Location of compiled Java return values. Same as C
3260 return_value %{
3261 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3262 #ifdef _LP64
3263 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3264 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3265 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3266 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3267 #else // !_LP64
3268 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3269 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3270 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3271 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3272 #endif
3273 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3274 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3275 %}
3276
3277 %}
3278
3279
3280 //----------ATTRIBUTES---------------------------------------------------------
3281 //----------Operand Attributes-------------------------------------------------
3282 op_attrib op_cost(1); // Required cost attribute
3283
3284 //----------Instruction Attributes---------------------------------------------
3285 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3286 ins_attrib ins_size(32); // Required size attribute (in bits)
3287 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3288 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3289 // non-matching short branch variant of some
3290 // long branch?
3291
3292 //----------OPERANDS-----------------------------------------------------------
3293 // Operand definitions must precede instruction definitions for correct parsing
3294 // in the ADLC because operands constitute user defined types which are used in
3295 // instruction definitions.
3296
3297 //----------Simple Operands----------------------------------------------------
3298 // Immediate Operands
3299 // Integer Immediate: 32-bit
3300 operand immI() %{
3301 match(ConI);
3302
3303 op_cost(0);
3304 // formats are generated automatically for constants and base registers
3305 format %{ %}
3306 interface(CONST_INTER);
3307 %}
3308
3309 // Integer Immediate: 8-bit
3310 operand immI8() %{
3311 predicate(Assembler::is_simm8(n->get_int()));
3312 match(ConI);
3313 op_cost(0);
3314 format %{ %}
3315 interface(CONST_INTER);
3316 %}
3317
3318 // Integer Immediate: 13-bit
3319 operand immI13() %{
3320 predicate(Assembler::is_simm13(n->get_int()));
3321 match(ConI);
3322 op_cost(0);
3323
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3327
3328 // Integer Immediate: 13-bit minus 7
3329 operand immI13m7() %{
3330 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3331 match(ConI);
3332 op_cost(0);
3333
3334 format %{ %}
3335 interface(CONST_INTER);
3336 %}
3337
3338 // Integer Immediate: 16-bit
3339 operand immI16() %{
3340 predicate(Assembler::is_simm16(n->get_int()));
3341 match(ConI);
3342 op_cost(0);
3343 format %{ %}
3344 interface(CONST_INTER);
3345 %}
3346
3347 // Unsigned (positive) Integer Immediate: 13-bit
3348 operand immU13() %{
3349 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3350 match(ConI);
3351 op_cost(0);
3352
3353 format %{ %}
3354 interface(CONST_INTER);
3355 %}
3356
3357 // Integer Immediate: 6-bit
3358 operand immU6() %{
3359 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3360 match(ConI);
3361 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3365
3366 // Integer Immediate: 11-bit
3367 operand immI11() %{
3368 predicate(Assembler::is_simm11(n->get_int()));
3369 match(ConI);
3370 op_cost(0);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // Integer Immediate: 5-bit
3376 operand immI5() %{
3377 predicate(Assembler::is_simm5(n->get_int()));
3378 match(ConI);
3379 op_cost(0);
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Integer Immediate: 0-bit
3385 operand immI0() %{
3386 predicate(n->get_int() == 0);
3387 match(ConI);
3388 op_cost(0);
3389
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Integer Immediate: the value 10
3395 operand immI10() %{
3396 predicate(n->get_int() == 10);
3397 match(ConI);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Integer Immediate: the values 0-31
3405 operand immU5() %{
3406 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3407 match(ConI);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Integer Immediate: the values 1-31
3415 operand immI_1_31() %{
3416 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3417 match(ConI);
3418 op_cost(0);
3419
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 // Integer Immediate: the values 32-63
3425 operand immI_32_63() %{
3426 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3427 match(ConI);
3428 op_cost(0);
3429
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3433
3434 // Immediates for special shifts (sign extend)
3435
3436 // Integer Immediate: the value 16
3437 operand immI_16() %{
3438 predicate(n->get_int() == 16);
3439 match(ConI);
3440 op_cost(0);
3441
3442 format %{ %}
3443 interface(CONST_INTER);
3444 %}
3445
3446 // Integer Immediate: the value 24
3447 operand immI_24() %{
3448 predicate(n->get_int() == 24);
3449 match(ConI);
3450 op_cost(0);
3451
3452 format %{ %}
3453 interface(CONST_INTER);
3454 %}
3455
3456 // Integer Immediate: the value 255
3457 operand immI_255() %{
3458 predicate( n->get_int() == 255 );
3459 match(ConI);
3460 op_cost(0);
3461
3462 format %{ %}
3463 interface(CONST_INTER);
3464 %}
3465
3466 // Integer Immediate: the value 65535
3467 operand immI_65535() %{
3468 predicate(n->get_int() == 65535);
3469 match(ConI);
3470 op_cost(0);
3471
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // Long Immediate: the value FF
3477 operand immL_FF() %{
3478 predicate( n->get_long() == 0xFFL );
3479 match(ConL);
3480 op_cost(0);
3481
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 // Long Immediate: the value FFFF
3487 operand immL_FFFF() %{
3488 predicate( n->get_long() == 0xFFFFL );
3489 match(ConL);
3490 op_cost(0);
3491
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 // Pointer Immediate: 32 or 64-bit
3497 operand immP() %{
3498 match(ConP);
3499
3500 op_cost(5);
3501 // formats are generated automatically for constants and base registers
3502 format %{ %}
3503 interface(CONST_INTER);
3504 %}
3505
3506 #ifdef _LP64
3507 // Pointer Immediate: 64-bit
3508 operand immP_set() %{
3509 predicate(!VM_Version::is_niagara_plus());
3510 match(ConP);
3511
3512 op_cost(5);
3513 // formats are generated automatically for constants and base registers
3514 format %{ %}
3515 interface(CONST_INTER);
3516 %}
3517
3518 // Pointer Immediate: 64-bit
3519 // From Niagara2 processors on a load should be better than materializing.
3520 operand immP_load() %{
3521 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3522 match(ConP);
3523
3524 op_cost(5);
3525 // formats are generated automatically for constants and base registers
3526 format %{ %}
3527 interface(CONST_INTER);
3528 %}
3529
3530 // Pointer Immediate: 64-bit
3531 operand immP_no_oop_cheap() %{
3532 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3533 match(ConP);
3534
3535 op_cost(5);
3536 // formats are generated automatically for constants and base registers
3537 format %{ %}
3538 interface(CONST_INTER);
3539 %}
3540 #endif
3541
3542 operand immP13() %{
3543 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3544 match(ConP);
3545 op_cost(0);
3546
3547 format %{ %}
3548 interface(CONST_INTER);
3549 %}
3550
3551 operand immP0() %{
3552 predicate(n->get_ptr() == 0);
3553 match(ConP);
3554 op_cost(0);
3555
3556 format %{ %}
3557 interface(CONST_INTER);
3558 %}
3559
3560 operand immP_poll() %{
3561 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3562 match(ConP);
3563
3564 // formats are generated automatically for constants and base registers
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Pointer Immediate
3570 operand immN()
3571 %{
3572 match(ConN);
3573
3574 op_cost(10);
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 operand immNKlass()
3580 %{
3581 match(ConNKlass);
3582
3583 op_cost(10);
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3587
3588 // NULL Pointer Immediate
3589 operand immN0()
3590 %{
3591 predicate(n->get_narrowcon() == 0);
3592 match(ConN);
3593
3594 op_cost(0);
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 operand immL() %{
3600 match(ConL);
3601 op_cost(40);
3602 // formats are generated automatically for constants and base registers
3603 format %{ %}
3604 interface(CONST_INTER);
3605 %}
3606
3607 operand immL0() %{
3608 predicate(n->get_long() == 0L);
3609 match(ConL);
3610 op_cost(0);
3611 // formats are generated automatically for constants and base registers
3612 format %{ %}
3613 interface(CONST_INTER);
3614 %}
3615
3616 // Integer Immediate: 5-bit
3617 operand immL5() %{
3618 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3619 match(ConL);
3620 op_cost(0);
3621 format %{ %}
3622 interface(CONST_INTER);
3623 %}
3624
3625 // Long Immediate: 13-bit
3626 operand immL13() %{
3627 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3628 match(ConL);
3629 op_cost(0);
3630
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 // Long Immediate: 13-bit minus 7
3636 operand immL13m7() %{
3637 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3638 match(ConL);
3639 op_cost(0);
3640
3641 format %{ %}
3642 interface(CONST_INTER);
3643 %}
3644
3645 // Long Immediate: low 32-bit mask
3646 operand immL_32bits() %{
3647 predicate(n->get_long() == 0xFFFFFFFFL);
3648 match(ConL);
3649 op_cost(0);
3650
3651 format %{ %}
3652 interface(CONST_INTER);
3653 %}
3654
3655 // Long Immediate: cheap (materialize in <= 3 instructions)
3656 operand immL_cheap() %{
3657 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3658 match(ConL);
3659 op_cost(0);
3660
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3664
3665 // Long Immediate: expensive (materialize in > 3 instructions)
3666 operand immL_expensive() %{
3667 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3668 match(ConL);
3669 op_cost(0);
3670
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3674
3675 // Double Immediate
3676 operand immD() %{
3677 match(ConD);
3678
3679 op_cost(40);
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 operand immD0() %{
3685 #ifdef _LP64
3686 // on 64-bit architectures this comparision is faster
3687 predicate(jlong_cast(n->getd()) == 0);
3688 #else
3689 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3690 #endif
3691 match(ConD);
3692
3693 op_cost(0);
3694 format %{ %}
3695 interface(CONST_INTER);
3696 %}
3697
3698 // Float Immediate
3699 operand immF() %{
3700 match(ConF);
3701
3702 op_cost(20);
3703 format %{ %}
3704 interface(CONST_INTER);
3705 %}
3706
3707 // Float Immediate: 0
3708 operand immF0() %{
3709 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3710 match(ConF);
3711
3712 op_cost(0);
3713 format %{ %}
3714 interface(CONST_INTER);
3715 %}
3716
3717 // Integer Register Operands
3718 // Integer Register
3719 operand iRegI() %{
3720 constraint(ALLOC_IN_RC(int_reg));
3721 match(RegI);
3722
3723 match(notemp_iRegI);
3724 match(g1RegI);
3725 match(o0RegI);
3726 match(iRegIsafe);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand notemp_iRegI() %{
3733 constraint(ALLOC_IN_RC(notemp_int_reg));
3734 match(RegI);
3735
3736 match(o0RegI);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 operand o0RegI() %{
3743 constraint(ALLOC_IN_RC(o0_regI));
3744 match(iRegI);
3745
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 // Pointer Register
3751 operand iRegP() %{
3752 constraint(ALLOC_IN_RC(ptr_reg));
3753 match(RegP);
3754
3755 match(lock_ptr_RegP);
3756 match(g1RegP);
3757 match(g2RegP);
3758 match(g3RegP);
3759 match(g4RegP);
3760 match(i0RegP);
3761 match(o0RegP);
3762 match(o1RegP);
3763 match(l7RegP);
3764
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3768
3769 operand sp_ptr_RegP() %{
3770 constraint(ALLOC_IN_RC(sp_ptr_reg));
3771 match(RegP);
3772 match(iRegP);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 operand lock_ptr_RegP() %{
3779 constraint(ALLOC_IN_RC(lock_ptr_reg));
3780 match(RegP);
3781 match(i0RegP);
3782 match(o0RegP);
3783 match(o1RegP);
3784 match(l7RegP);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 operand g1RegP() %{
3791 constraint(ALLOC_IN_RC(g1_regP));
3792 match(iRegP);
3793
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3797
3798 operand g2RegP() %{
3799 constraint(ALLOC_IN_RC(g2_regP));
3800 match(iRegP);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand g3RegP() %{
3807 constraint(ALLOC_IN_RC(g3_regP));
3808 match(iRegP);
3809
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3813
3814 operand g1RegI() %{
3815 constraint(ALLOC_IN_RC(g1_regI));
3816 match(iRegI);
3817
3818 format %{ %}
3819 interface(REG_INTER);
3820 %}
3821
3822 operand g3RegI() %{
3823 constraint(ALLOC_IN_RC(g3_regI));
3824 match(iRegI);
3825
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3829
3830 operand g4RegI() %{
3831 constraint(ALLOC_IN_RC(g4_regI));
3832 match(iRegI);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand g4RegP() %{
3839 constraint(ALLOC_IN_RC(g4_regP));
3840 match(iRegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand i0RegP() %{
3847 constraint(ALLOC_IN_RC(i0_regP));
3848 match(iRegP);
3849
3850 format %{ %}
3851 interface(REG_INTER);
3852 %}
3853
3854 operand o0RegP() %{
3855 constraint(ALLOC_IN_RC(o0_regP));
3856 match(iRegP);
3857
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand o1RegP() %{
3863 constraint(ALLOC_IN_RC(o1_regP));
3864 match(iRegP);
3865
3866 format %{ %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand o2RegP() %{
3871 constraint(ALLOC_IN_RC(o2_regP));
3872 match(iRegP);
3873
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3877
3878 operand o7RegP() %{
3879 constraint(ALLOC_IN_RC(o7_regP));
3880 match(iRegP);
3881
3882 format %{ %}
3883 interface(REG_INTER);
3884 %}
3885
3886 operand l7RegP() %{
3887 constraint(ALLOC_IN_RC(l7_regP));
3888 match(iRegP);
3889
3890 format %{ %}
3891 interface(REG_INTER);
3892 %}
3893
3894 operand o7RegI() %{
3895 constraint(ALLOC_IN_RC(o7_regI));
3896 match(iRegI);
3897
3898 format %{ %}
3899 interface(REG_INTER);
3900 %}
3901
3902 operand iRegN() %{
3903 constraint(ALLOC_IN_RC(int_reg));
3904 match(RegN);
3905
3906 format %{ %}
3907 interface(REG_INTER);
3908 %}
3909
3910 // Long Register
3911 operand iRegL() %{
3912 constraint(ALLOC_IN_RC(long_reg));
3913 match(RegL);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand o2RegL() %{
3920 constraint(ALLOC_IN_RC(o2_regL));
3921 match(iRegL);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 operand o7RegL() %{
3928 constraint(ALLOC_IN_RC(o7_regL));
3929 match(iRegL);
3930
3931 format %{ %}
3932 interface(REG_INTER);
3933 %}
3934
3935 operand g1RegL() %{
3936 constraint(ALLOC_IN_RC(g1_regL));
3937 match(iRegL);
3938
3939 format %{ %}
3940 interface(REG_INTER);
3941 %}
3942
3943 operand g3RegL() %{
3944 constraint(ALLOC_IN_RC(g3_regL));
3945 match(iRegL);
3946
3947 format %{ %}
3948 interface(REG_INTER);
3949 %}
3950
3951 // Int Register safe
3952 // This is 64bit safe
3953 operand iRegIsafe() %{
3954 constraint(ALLOC_IN_RC(long_reg));
3955
3956 match(iRegI);
3957
3958 format %{ %}
3959 interface(REG_INTER);
3960 %}
3961
3962 // Condition Code Flag Register
3963 operand flagsReg() %{
3964 constraint(ALLOC_IN_RC(int_flags));
3965 match(RegFlags);
3966
3967 format %{ "ccr" %} // both ICC and XCC
3968 interface(REG_INTER);
3969 %}
3970
3971 // Condition Code Register, unsigned comparisons.
3972 operand flagsRegU() %{
3973 constraint(ALLOC_IN_RC(int_flags));
3974 match(RegFlags);
3975
3976 format %{ "icc_U" %}
3977 interface(REG_INTER);
3978 %}
3979
3980 // Condition Code Register, pointer comparisons.
3981 operand flagsRegP() %{
3982 constraint(ALLOC_IN_RC(int_flags));
3983 match(RegFlags);
3984
3985 #ifdef _LP64
3986 format %{ "xcc_P" %}
3987 #else
3988 format %{ "icc_P" %}
3989 #endif
3990 interface(REG_INTER);
3991 %}
3992
3993 // Condition Code Register, long comparisons.
3994 operand flagsRegL() %{
3995 constraint(ALLOC_IN_RC(int_flags));
3996 match(RegFlags);
3997
3998 format %{ "xcc_L" %}
3999 interface(REG_INTER);
4000 %}
4001
4002 // Condition Code Register, floating comparisons, unordered same as "less".
4003 operand flagsRegF() %{
4004 constraint(ALLOC_IN_RC(float_flags));
4005 match(RegFlags);
4006 match(flagsRegF0);
4007
4008 format %{ %}
4009 interface(REG_INTER);
4010 %}
4011
4012 operand flagsRegF0() %{
4013 constraint(ALLOC_IN_RC(float_flag0));
4014 match(RegFlags);
4015
4016 format %{ %}
4017 interface(REG_INTER);
4018 %}
4019
4020
4021 // Condition Code Flag Register used by long compare
4022 operand flagsReg_long_LTGE() %{
4023 constraint(ALLOC_IN_RC(int_flags));
4024 match(RegFlags);
4025 format %{ "icc_LTGE" %}
4026 interface(REG_INTER);
4027 %}
4028 operand flagsReg_long_EQNE() %{
4029 constraint(ALLOC_IN_RC(int_flags));
4030 match(RegFlags);
4031 format %{ "icc_EQNE" %}
4032 interface(REG_INTER);
4033 %}
4034 operand flagsReg_long_LEGT() %{
4035 constraint(ALLOC_IN_RC(int_flags));
4036 match(RegFlags);
4037 format %{ "icc_LEGT" %}
4038 interface(REG_INTER);
4039 %}
4040
4041
4042 operand regD() %{
4043 constraint(ALLOC_IN_RC(dflt_reg));
4044 match(RegD);
4045
4046 match(regD_low);
4047
4048 format %{ %}
4049 interface(REG_INTER);
4050 %}
4051
4052 operand regF() %{
4053 constraint(ALLOC_IN_RC(sflt_reg));
4054 match(RegF);
4055
4056 format %{ %}
4057 interface(REG_INTER);
4058 %}
4059
4060 operand regD_low() %{
4061 constraint(ALLOC_IN_RC(dflt_low_reg));
4062 match(regD);
4063
4064 format %{ %}
4065 interface(REG_INTER);
4066 %}
4067
4068 // Special Registers
4069
4070 // Method Register
4071 operand inline_cache_regP(iRegP reg) %{
4072 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4073 match(reg);
4074 format %{ %}
4075 interface(REG_INTER);
4076 %}
4077
4078 operand interpreter_method_oop_regP(iRegP reg) %{
4079 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4080 match(reg);
4081 format %{ %}
4082 interface(REG_INTER);
4083 %}
4084
4085
4086 //----------Complex Operands---------------------------------------------------
4087 // Indirect Memory Reference
4088 operand indirect(sp_ptr_RegP reg) %{
4089 constraint(ALLOC_IN_RC(sp_ptr_reg));
4090 match(reg);
4091
4092 op_cost(100);
4093 format %{ "[$reg]" %}
4094 interface(MEMORY_INTER) %{
4095 base($reg);
4096 index(0x0);
4097 scale(0x0);
4098 disp(0x0);
4099 %}
4100 %}
4101
4102 // Indirect with simm13 Offset
4103 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4104 constraint(ALLOC_IN_RC(sp_ptr_reg));
4105 match(AddP reg offset);
4106
4107 op_cost(100);
4108 format %{ "[$reg + $offset]" %}
4109 interface(MEMORY_INTER) %{
4110 base($reg);
4111 index(0x0);
4112 scale(0x0);
4113 disp($offset);
4114 %}
4115 %}
4116
4117 // Indirect with simm13 Offset minus 7
4118 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4119 constraint(ALLOC_IN_RC(sp_ptr_reg));
4120 match(AddP reg offset);
4121
4122 op_cost(100);
4123 format %{ "[$reg + $offset]" %}
4124 interface(MEMORY_INTER) %{
4125 base($reg);
4126 index(0x0);
4127 scale(0x0);
4128 disp($offset);
4129 %}
4130 %}
4131
4132 // Note: Intel has a swapped version also, like this:
4133 //operand indOffsetX(iRegI reg, immP offset) %{
4134 // constraint(ALLOC_IN_RC(int_reg));
4135 // match(AddP offset reg);
4136 //
4137 // op_cost(100);
4138 // format %{ "[$reg + $offset]" %}
4139 // interface(MEMORY_INTER) %{
4140 // base($reg);
4141 // index(0x0);
4142 // scale(0x0);
4143 // disp($offset);
4144 // %}
4145 //%}
4146 //// However, it doesn't make sense for SPARC, since
4147 // we have no particularly good way to embed oops in
4148 // single instructions.
4149
4150 // Indirect with Register Index
4151 operand indIndex(iRegP addr, iRegX index) %{
4152 constraint(ALLOC_IN_RC(ptr_reg));
4153 match(AddP addr index);
4154
4155 op_cost(100);
4156 format %{ "[$addr + $index]" %}
4157 interface(MEMORY_INTER) %{
4158 base($addr);
4159 index($index);
4160 scale(0x0);
4161 disp(0x0);
4162 %}
4163 %}
4164
4165 //----------Special Memory Operands--------------------------------------------
4166 // Stack Slot Operand - This operand is used for loading and storing temporary
4167 // values on the stack where a match requires a value to
4168 // flow through memory.
4169 operand stackSlotI(sRegI reg) %{
4170 constraint(ALLOC_IN_RC(stack_slots));
4171 op_cost(100);
4172 //match(RegI);
4173 format %{ "[$reg]" %}
4174 interface(MEMORY_INTER) %{
4175 base(0xE); // R_SP
4176 index(0x0);
4177 scale(0x0);
4178 disp($reg); // Stack Offset
4179 %}
4180 %}
4181
4182 operand stackSlotP(sRegP reg) %{
4183 constraint(ALLOC_IN_RC(stack_slots));
4184 op_cost(100);
4185 //match(RegP);
4186 format %{ "[$reg]" %}
4187 interface(MEMORY_INTER) %{
4188 base(0xE); // R_SP
4189 index(0x0);
4190 scale(0x0);
4191 disp($reg); // Stack Offset
4192 %}
4193 %}
4194
4195 operand stackSlotF(sRegF reg) %{
4196 constraint(ALLOC_IN_RC(stack_slots));
4197 op_cost(100);
4198 //match(RegF);
4199 format %{ "[$reg]" %}
4200 interface(MEMORY_INTER) %{
4201 base(0xE); // R_SP
4202 index(0x0);
4203 scale(0x0);
4204 disp($reg); // Stack Offset
4205 %}
4206 %}
4207 operand stackSlotD(sRegD reg) %{
4208 constraint(ALLOC_IN_RC(stack_slots));
4209 op_cost(100);
4210 //match(RegD);
4211 format %{ "[$reg]" %}
4212 interface(MEMORY_INTER) %{
4213 base(0xE); // R_SP
4214 index(0x0);
4215 scale(0x0);
4216 disp($reg); // Stack Offset
4217 %}
4218 %}
4219 operand stackSlotL(sRegL reg) %{
4220 constraint(ALLOC_IN_RC(stack_slots));
4221 op_cost(100);
4222 //match(RegL);
4223 format %{ "[$reg]" %}
4224 interface(MEMORY_INTER) %{
4225 base(0xE); // R_SP
4226 index(0x0);
4227 scale(0x0);
4228 disp($reg); // Stack Offset
4229 %}
4230 %}
4231
4232 // Operands for expressing Control Flow
4233 // NOTE: Label is a predefined operand which should not be redefined in
4234 // the AD file. It is generically handled within the ADLC.
4235
4236 //----------Conditional Branch Operands----------------------------------------
4237 // Comparison Op - This is the operation of the comparison, and is limited to
4238 // the following set of codes:
4239 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4240 //
4241 // Other attributes of the comparison, such as unsignedness, are specified
4242 // by the comparison instruction that sets a condition code flags register.
4243 // That result is represented by a flags operand whose subtype is appropriate
4244 // to the unsignedness (etc.) of the comparison.
4245 //
4246 // Later, the instruction which matches both the Comparison Op (a Bool) and
4247 // the flags (produced by the Cmp) specifies the coding of the comparison op
4248 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4249
4250 operand cmpOp() %{
4251 match(Bool);
4252
4253 format %{ "" %}
4254 interface(COND_INTER) %{
4255 equal(0x1);
4256 not_equal(0x9);
4257 less(0x3);
4258 greater_equal(0xB);
4259 less_equal(0x2);
4260 greater(0xA);
4261 overflow(0x7);
4262 no_overflow(0xF);
4263 %}
4264 %}
4265
4266 // Comparison Op, unsigned
4267 operand cmpOpU() %{
4268 match(Bool);
4269 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4270 n->as_Bool()->_test._test != BoolTest::no_overflow);
4271
4272 format %{ "u" %}
4273 interface(COND_INTER) %{
4274 equal(0x1);
4275 not_equal(0x9);
4276 less(0x5);
4277 greater_equal(0xD);
4278 less_equal(0x4);
4279 greater(0xC);
4280 overflow(0x7);
4281 no_overflow(0xF);
4282 %}
4283 %}
4284
4285 // Comparison Op, pointer (same as unsigned)
4286 operand cmpOpP() %{
4287 match(Bool);
4288 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4289 n->as_Bool()->_test._test != BoolTest::no_overflow);
4290
4291 format %{ "p" %}
4292 interface(COND_INTER) %{
4293 equal(0x1);
4294 not_equal(0x9);
4295 less(0x5);
4296 greater_equal(0xD);
4297 less_equal(0x4);
4298 greater(0xC);
4299 overflow(0x7);
4300 no_overflow(0xF);
4301 %}
4302 %}
4303
4304 // Comparison Op, branch-register encoding
4305 operand cmpOp_reg() %{
4306 match(Bool);
4307 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4308 n->as_Bool()->_test._test != BoolTest::no_overflow);
4309
4310 format %{ "" %}
4311 interface(COND_INTER) %{
4312 equal (0x1);
4313 not_equal (0x5);
4314 less (0x3);
4315 greater_equal(0x7);
4316 less_equal (0x2);
4317 greater (0x6);
4318 overflow(0x7); // not supported
4319 no_overflow(0xF); // not supported
4320 %}
4321 %}
4322
4323 // Comparison Code, floating, unordered same as less
4324 operand cmpOpF() %{
4325 match(Bool);
4326 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4327 n->as_Bool()->_test._test != BoolTest::no_overflow);
4328
4329 format %{ "fl" %}
4330 interface(COND_INTER) %{
4331 equal(0x9);
4332 not_equal(0x1);
4333 less(0x3);
4334 greater_equal(0xB);
4335 less_equal(0xE);
4336 greater(0x6);
4337
4338 overflow(0x7); // not supported
4339 no_overflow(0xF); // not supported
4340 %}
4341 %}
4342
4343 // Used by long compare
4344 operand cmpOp_commute() %{
4345 match(Bool);
4346 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4347 n->as_Bool()->_test._test != BoolTest::no_overflow);
4348
4349 format %{ "" %}
4350 interface(COND_INTER) %{
4351 equal(0x1);
4352 not_equal(0x9);
4353 less(0xA);
4354 greater_equal(0x2);
4355 less_equal(0xB);
4356 greater(0x3);
4357 overflow(0x7);
4358 no_overflow(0xF);
4359 %}
4360 %}
4361
4362 //----------OPERAND CLASSES----------------------------------------------------
4363 // Operand Classes are groups of operands that are used to simplify
4364 // instruction definitions by not requiring the AD writer to specify separate
4365 // instructions for every form of operand when the instruction accepts
4366 // multiple operand types with the same basic encoding and format. The classic
4367 // case of this is memory operands.
4368 opclass memory( indirect, indOffset13, indIndex );
4369 opclass indIndexMemory( indIndex );
4370
4371 //----------PIPELINE-----------------------------------------------------------
4372 pipeline %{
4373
4374 //----------ATTRIBUTES---------------------------------------------------------
4375 attributes %{
4376 fixed_size_instructions; // Fixed size instructions
4377 branch_has_delay_slot; // Branch has delay slot following
4378 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4379 instruction_unit_size = 4; // An instruction is 4 bytes long
4380 instruction_fetch_unit_size = 16; // The processor fetches one line
4381 instruction_fetch_units = 1; // of 16 bytes
4382
4383 // List of nop instructions
4384 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4385 %}
4386
4387 //----------RESOURCES----------------------------------------------------------
4388 // Resources are the functional units available to the machine
4389 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4390
4391 //----------PIPELINE DESCRIPTION-----------------------------------------------
4392 // Pipeline Description specifies the stages in the machine's pipeline
4393
4394 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4395
4396 //----------PIPELINE CLASSES---------------------------------------------------
4397 // Pipeline Classes describe the stages in which input and output are
4398 // referenced by the hardware pipeline.
4399
4400 // Integer ALU reg-reg operation
4401 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4402 single_instruction;
4403 dst : E(write);
4404 src1 : R(read);
4405 src2 : R(read);
4406 IALU : R;
4407 %}
4408
4409 // Integer ALU reg-reg long operation
4410 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4411 instruction_count(2);
4412 dst : E(write);
4413 src1 : R(read);
4414 src2 : R(read);
4415 IALU : R;
4416 IALU : R;
4417 %}
4418
4419 // Integer ALU reg-reg long dependent operation
4420 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4421 instruction_count(1); multiple_bundles;
4422 dst : E(write);
4423 src1 : R(read);
4424 src2 : R(read);
4425 cr : E(write);
4426 IALU : R(2);
4427 %}
4428
4429 // Integer ALU reg-imm operaion
4430 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4431 single_instruction;
4432 dst : E(write);
4433 src1 : R(read);
4434 IALU : R;
4435 %}
4436
4437 // Integer ALU reg-reg operation with condition code
4438 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4439 single_instruction;
4440 dst : E(write);
4441 cr : E(write);
4442 src1 : R(read);
4443 src2 : R(read);
4444 IALU : R;
4445 %}
4446
4447 // Integer ALU reg-imm operation with condition code
4448 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4449 single_instruction;
4450 dst : E(write);
4451 cr : E(write);
4452 src1 : R(read);
4453 IALU : R;
4454 %}
4455
4456 // Integer ALU zero-reg operation
4457 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4458 single_instruction;
4459 dst : E(write);
4460 src2 : R(read);
4461 IALU : R;
4462 %}
4463
4464 // Integer ALU zero-reg operation with condition code only
4465 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4466 single_instruction;
4467 cr : E(write);
4468 src : R(read);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU reg-reg operation with condition code only
4473 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4474 single_instruction;
4475 cr : E(write);
4476 src1 : R(read);
4477 src2 : R(read);
4478 IALU : R;
4479 %}
4480
4481 // Integer ALU reg-imm operation with condition code only
4482 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4483 single_instruction;
4484 cr : E(write);
4485 src1 : R(read);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU reg-reg-zero operation with condition code only
4490 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4491 single_instruction;
4492 cr : E(write);
4493 src1 : R(read);
4494 src2 : R(read);
4495 IALU : R;
4496 %}
4497
4498 // Integer ALU reg-imm-zero operation with condition code only
4499 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4500 single_instruction;
4501 cr : E(write);
4502 src1 : R(read);
4503 IALU : R;
4504 %}
4505
4506 // Integer ALU reg-reg operation with condition code, src1 modified
4507 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4508 single_instruction;
4509 cr : E(write);
4510 src1 : E(write);
4511 src1 : R(read);
4512 src2 : R(read);
4513 IALU : R;
4514 %}
4515
4516 // Integer ALU reg-imm operation with condition code, src1 modified
4517 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4518 single_instruction;
4519 cr : E(write);
4520 src1 : E(write);
4521 src1 : R(read);
4522 IALU : R;
4523 %}
4524
4525 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4526 multiple_bundles;
4527 dst : E(write)+4;
4528 cr : E(write);
4529 src1 : R(read);
4530 src2 : R(read);
4531 IALU : R(3);
4532 BR : R(2);
4533 %}
4534
4535 // Integer ALU operation
4536 pipe_class ialu_none(iRegI dst) %{
4537 single_instruction;
4538 dst : E(write);
4539 IALU : R;
4540 %}
4541
4542 // Integer ALU reg operation
4543 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4544 single_instruction; may_have_no_code;
4545 dst : E(write);
4546 src : R(read);
4547 IALU : R;
4548 %}
4549
4550 // Integer ALU reg conditional operation
4551 // This instruction has a 1 cycle stall, and cannot execute
4552 // in the same cycle as the instruction setting the condition
4553 // code. We kludge this by pretending to read the condition code
4554 // 1 cycle earlier, and by marking the functional units as busy
4555 // for 2 cycles with the result available 1 cycle later than
4556 // is really the case.
4557 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4558 single_instruction;
4559 op2_out : C(write);
4560 op1 : R(read);
4561 cr : R(read); // This is really E, with a 1 cycle stall
4562 BR : R(2);
4563 MS : R(2);
4564 %}
4565
4566 #ifdef _LP64
4567 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4568 instruction_count(1); multiple_bundles;
4569 dst : C(write)+1;
4570 src : R(read)+1;
4571 IALU : R(1);
4572 BR : E(2);
4573 MS : E(2);
4574 %}
4575 #endif
4576
4577 // Integer ALU reg operation
4578 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4579 single_instruction; may_have_no_code;
4580 dst : E(write);
4581 src : R(read);
4582 IALU : R;
4583 %}
4584 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4585 single_instruction; may_have_no_code;
4586 dst : E(write);
4587 src : R(read);
4588 IALU : R;
4589 %}
4590
4591 // Two integer ALU reg operations
4592 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4593 instruction_count(2);
4594 dst : E(write);
4595 src : R(read);
4596 A0 : R;
4597 A1 : R;
4598 %}
4599
4600 // Two integer ALU reg operations
4601 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4602 instruction_count(2); may_have_no_code;
4603 dst : E(write);
4604 src : R(read);
4605 A0 : R;
4606 A1 : R;
4607 %}
4608
4609 // Integer ALU imm operation
4610 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4611 single_instruction;
4612 dst : E(write);
4613 IALU : R;
4614 %}
4615
4616 // Integer ALU reg-reg with carry operation
4617 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4618 single_instruction;
4619 dst : E(write);
4620 src1 : R(read);
4621 src2 : R(read);
4622 IALU : R;
4623 %}
4624
4625 // Integer ALU cc operation
4626 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4627 single_instruction;
4628 dst : E(write);
4629 cc : R(read);
4630 IALU : R;
4631 %}
4632
4633 // Integer ALU cc / second IALU operation
4634 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4635 instruction_count(1); multiple_bundles;
4636 dst : E(write)+1;
4637 src : R(read);
4638 IALU : R;
4639 %}
4640
4641 // Integer ALU cc / second IALU operation
4642 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4643 instruction_count(1); multiple_bundles;
4644 dst : E(write)+1;
4645 p : R(read);
4646 q : R(read);
4647 IALU : R;
4648 %}
4649
4650 // Integer ALU hi-lo-reg operation
4651 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4652 instruction_count(1); multiple_bundles;
4653 dst : E(write)+1;
4654 IALU : R(2);
4655 %}
4656
4657 // Float ALU hi-lo-reg operation (with temp)
4658 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4659 instruction_count(1); multiple_bundles;
4660 dst : E(write)+1;
4661 IALU : R(2);
4662 %}
4663
4664 // Long Constant
4665 pipe_class loadConL( iRegL dst, immL src ) %{
4666 instruction_count(2); multiple_bundles;
4667 dst : E(write)+1;
4668 IALU : R(2);
4669 IALU : R(2);
4670 %}
4671
4672 // Pointer Constant
4673 pipe_class loadConP( iRegP dst, immP src ) %{
4674 instruction_count(0); multiple_bundles;
4675 fixed_latency(6);
4676 %}
4677
4678 // Polling Address
4679 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4680 #ifdef _LP64
4681 instruction_count(0); multiple_bundles;
4682 fixed_latency(6);
4683 #else
4684 dst : E(write);
4685 IALU : R;
4686 #endif
4687 %}
4688
4689 // Long Constant small
4690 pipe_class loadConLlo( iRegL dst, immL src ) %{
4691 instruction_count(2);
4692 dst : E(write);
4693 IALU : R;
4694 IALU : R;
4695 %}
4696
4697 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4698 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4699 instruction_count(1); multiple_bundles;
4700 src : R(read);
4701 dst : M(write)+1;
4702 IALU : R;
4703 MS : E;
4704 %}
4705
4706 // Integer ALU nop operation
4707 pipe_class ialu_nop() %{
4708 single_instruction;
4709 IALU : R;
4710 %}
4711
4712 // Integer ALU nop operation
4713 pipe_class ialu_nop_A0() %{
4714 single_instruction;
4715 A0 : R;
4716 %}
4717
4718 // Integer ALU nop operation
4719 pipe_class ialu_nop_A1() %{
4720 single_instruction;
4721 A1 : R;
4722 %}
4723
4724 // Integer Multiply reg-reg operation
4725 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4726 single_instruction;
4727 dst : E(write);
4728 src1 : R(read);
4729 src2 : R(read);
4730 MS : R(5);
4731 %}
4732
4733 // Integer Multiply reg-imm operation
4734 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4735 single_instruction;
4736 dst : E(write);
4737 src1 : R(read);
4738 MS : R(5);
4739 %}
4740
4741 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4742 single_instruction;
4743 dst : E(write)+4;
4744 src1 : R(read);
4745 src2 : R(read);
4746 MS : R(6);
4747 %}
4748
4749 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4750 single_instruction;
4751 dst : E(write)+4;
4752 src1 : R(read);
4753 MS : R(6);
4754 %}
4755
4756 // Integer Divide reg-reg
4757 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4758 instruction_count(1); multiple_bundles;
4759 dst : E(write);
4760 temp : E(write);
4761 src1 : R(read);
4762 src2 : R(read);
4763 temp : R(read);
4764 MS : R(38);
4765 %}
4766
4767 // Integer Divide reg-imm
4768 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4769 instruction_count(1); multiple_bundles;
4770 dst : E(write);
4771 temp : E(write);
4772 src1 : R(read);
4773 temp : R(read);
4774 MS : R(38);
4775 %}
4776
4777 // Long Divide
4778 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4779 dst : E(write)+71;
4780 src1 : R(read);
4781 src2 : R(read)+1;
4782 MS : R(70);
4783 %}
4784
4785 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4786 dst : E(write)+71;
4787 src1 : R(read);
4788 MS : R(70);
4789 %}
4790
4791 // Floating Point Add Float
4792 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4793 single_instruction;
4794 dst : X(write);
4795 src1 : E(read);
4796 src2 : E(read);
4797 FA : R;
4798 %}
4799
4800 // Floating Point Add Double
4801 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4802 single_instruction;
4803 dst : X(write);
4804 src1 : E(read);
4805 src2 : E(read);
4806 FA : R;
4807 %}
4808
4809 // Floating Point Conditional Move based on integer flags
4810 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4811 single_instruction;
4812 dst : X(write);
4813 src : E(read);
4814 cr : R(read);
4815 FA : R(2);
4816 BR : R(2);
4817 %}
4818
4819 // Floating Point Conditional Move based on integer flags
4820 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4821 single_instruction;
4822 dst : X(write);
4823 src : E(read);
4824 cr : R(read);
4825 FA : R(2);
4826 BR : R(2);
4827 %}
4828
4829 // Floating Point Multiply Float
4830 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4831 single_instruction;
4832 dst : X(write);
4833 src1 : E(read);
4834 src2 : E(read);
4835 FM : R;
4836 %}
4837
4838 // Floating Point Multiply Double
4839 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4840 single_instruction;
4841 dst : X(write);
4842 src1 : E(read);
4843 src2 : E(read);
4844 FM : R;
4845 %}
4846
4847 // Floating Point Divide Float
4848 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4849 single_instruction;
4850 dst : X(write);
4851 src1 : E(read);
4852 src2 : E(read);
4853 FM : R;
4854 FDIV : C(14);
4855 %}
4856
4857 // Floating Point Divide Double
4858 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4859 single_instruction;
4860 dst : X(write);
4861 src1 : E(read);
4862 src2 : E(read);
4863 FM : R;
4864 FDIV : C(17);
4865 %}
4866
4867 // Floating Point Move/Negate/Abs Float
4868 pipe_class faddF_reg(regF dst, regF src) %{
4869 single_instruction;
4870 dst : W(write);
4871 src : E(read);
4872 FA : R(1);
4873 %}
4874
4875 // Floating Point Move/Negate/Abs Double
4876 pipe_class faddD_reg(regD dst, regD src) %{
4877 single_instruction;
4878 dst : W(write);
4879 src : E(read);
4880 FA : R;
4881 %}
4882
4883 // Floating Point Convert F->D
4884 pipe_class fcvtF2D(regD dst, regF src) %{
4885 single_instruction;
4886 dst : X(write);
4887 src : E(read);
4888 FA : R;
4889 %}
4890
4891 // Floating Point Convert I->D
4892 pipe_class fcvtI2D(regD dst, regF src) %{
4893 single_instruction;
4894 dst : X(write);
4895 src : E(read);
4896 FA : R;
4897 %}
4898
4899 // Floating Point Convert LHi->D
4900 pipe_class fcvtLHi2D(regD dst, regD src) %{
4901 single_instruction;
4902 dst : X(write);
4903 src : E(read);
4904 FA : R;
4905 %}
4906
4907 // Floating Point Convert L->D
4908 pipe_class fcvtL2D(regD dst, regF src) %{
4909 single_instruction;
4910 dst : X(write);
4911 src : E(read);
4912 FA : R;
4913 %}
4914
4915 // Floating Point Convert L->F
4916 pipe_class fcvtL2F(regD dst, regF src) %{
4917 single_instruction;
4918 dst : X(write);
4919 src : E(read);
4920 FA : R;
4921 %}
4922
4923 // Floating Point Convert D->F
4924 pipe_class fcvtD2F(regD dst, regF src) %{
4925 single_instruction;
4926 dst : X(write);
4927 src : E(read);
4928 FA : R;
4929 %}
4930
4931 // Floating Point Convert I->L
4932 pipe_class fcvtI2L(regD dst, regF src) %{
4933 single_instruction;
4934 dst : X(write);
4935 src : E(read);
4936 FA : R;
4937 %}
4938
4939 // Floating Point Convert D->F
4940 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4941 instruction_count(1); multiple_bundles;
4942 dst : X(write)+6;
4943 src : E(read);
4944 FA : R;
4945 %}
4946
4947 // Floating Point Convert D->L
4948 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4949 instruction_count(1); multiple_bundles;
4950 dst : X(write)+6;
4951 src : E(read);
4952 FA : R;
4953 %}
4954
4955 // Floating Point Convert F->I
4956 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4957 instruction_count(1); multiple_bundles;
4958 dst : X(write)+6;
4959 src : E(read);
4960 FA : R;
4961 %}
4962
4963 // Floating Point Convert F->L
4964 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4965 instruction_count(1); multiple_bundles;
4966 dst : X(write)+6;
4967 src : E(read);
4968 FA : R;
4969 %}
4970
4971 // Floating Point Convert I->F
4972 pipe_class fcvtI2F(regF dst, regF src) %{
4973 single_instruction;
4974 dst : X(write);
4975 src : E(read);
4976 FA : R;
4977 %}
4978
4979 // Floating Point Compare
4980 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4981 single_instruction;
4982 cr : X(write);
4983 src1 : E(read);
4984 src2 : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Compare
4989 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4990 single_instruction;
4991 cr : X(write);
4992 src1 : E(read);
4993 src2 : E(read);
4994 FA : R;
4995 %}
4996
4997 // Floating Add Nop
4998 pipe_class fadd_nop() %{
4999 single_instruction;
5000 FA : R;
5001 %}
5002
5003 // Integer Store to Memory
5004 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5005 single_instruction;
5006 mem : R(read);
5007 src : C(read);
5008 MS : R;
5009 %}
5010
5011 // Integer Store to Memory
5012 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5013 single_instruction;
5014 mem : R(read);
5015 src : C(read);
5016 MS : R;
5017 %}
5018
5019 // Integer Store Zero to Memory
5020 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5021 single_instruction;
5022 mem : R(read);
5023 MS : R;
5024 %}
5025
5026 // Special Stack Slot Store
5027 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5028 single_instruction;
5029 stkSlot : R(read);
5030 src : C(read);
5031 MS : R;
5032 %}
5033
5034 // Special Stack Slot Store
5035 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5036 instruction_count(2); multiple_bundles;
5037 stkSlot : R(read);
5038 src : C(read);
5039 MS : R(2);
5040 %}
5041
5042 // Float Store
5043 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5044 single_instruction;
5045 mem : R(read);
5046 src : C(read);
5047 MS : R;
5048 %}
5049
5050 // Float Store
5051 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5052 single_instruction;
5053 mem : R(read);
5054 MS : R;
5055 %}
5056
5057 // Double Store
5058 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5059 instruction_count(1);
5060 mem : R(read);
5061 src : C(read);
5062 MS : R;
5063 %}
5064
5065 // Double Store
5066 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5067 single_instruction;
5068 mem : R(read);
5069 MS : R;
5070 %}
5071
5072 // Special Stack Slot Float Store
5073 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5074 single_instruction;
5075 stkSlot : R(read);
5076 src : C(read);
5077 MS : R;
5078 %}
5079
5080 // Special Stack Slot Double Store
5081 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5082 single_instruction;
5083 stkSlot : R(read);
5084 src : C(read);
5085 MS : R;
5086 %}
5087
5088 // Integer Load (when sign bit propagation not needed)
5089 pipe_class iload_mem(iRegI dst, memory mem) %{
5090 single_instruction;
5091 mem : R(read);
5092 dst : C(write);
5093 MS : R;
5094 %}
5095
5096 // Integer Load from stack operand
5097 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5098 single_instruction;
5099 mem : R(read);
5100 dst : C(write);
5101 MS : R;
5102 %}
5103
5104 // Integer Load (when sign bit propagation or masking is needed)
5105 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5106 single_instruction;
5107 mem : R(read);
5108 dst : M(write);
5109 MS : R;
5110 %}
5111
5112 // Float Load
5113 pipe_class floadF_mem(regF dst, memory mem) %{
5114 single_instruction;
5115 mem : R(read);
5116 dst : M(write);
5117 MS : R;
5118 %}
5119
5120 // Float Load
5121 pipe_class floadD_mem(regD dst, memory mem) %{
5122 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5123 mem : R(read);
5124 dst : M(write);
5125 MS : R;
5126 %}
5127
5128 // Float Load
5129 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5130 single_instruction;
5131 stkSlot : R(read);
5132 dst : M(write);
5133 MS : R;
5134 %}
5135
5136 // Float Load
5137 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5138 single_instruction;
5139 stkSlot : R(read);
5140 dst : M(write);
5141 MS : R;
5142 %}
5143
5144 // Memory Nop
5145 pipe_class mem_nop() %{
5146 single_instruction;
5147 MS : R;
5148 %}
5149
5150 pipe_class sethi(iRegP dst, immI src) %{
5151 single_instruction;
5152 dst : E(write);
5153 IALU : R;
5154 %}
5155
5156 pipe_class loadPollP(iRegP poll) %{
5157 single_instruction;
5158 poll : R(read);
5159 MS : R;
5160 %}
5161
5162 pipe_class br(Universe br, label labl) %{
5163 single_instruction_with_delay_slot;
5164 BR : R;
5165 %}
5166
5167 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5168 single_instruction_with_delay_slot;
5169 cr : E(read);
5170 BR : R;
5171 %}
5172
5173 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5174 single_instruction_with_delay_slot;
5175 op1 : E(read);
5176 BR : R;
5177 MS : R;
5178 %}
5179
5180 // Compare and branch
5181 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5182 instruction_count(2); has_delay_slot;
5183 cr : E(write);
5184 src1 : R(read);
5185 src2 : R(read);
5186 IALU : R;
5187 BR : R;
5188 %}
5189
5190 // Compare and branch
5191 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5192 instruction_count(2); has_delay_slot;
5193 cr : E(write);
5194 src1 : R(read);
5195 IALU : R;
5196 BR : R;
5197 %}
5198
5199 // Compare and branch using cbcond
5200 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5201 single_instruction;
5202 src1 : E(read);
5203 src2 : E(read);
5204 IALU : R;
5205 BR : R;
5206 %}
5207
5208 // Compare and branch using cbcond
5209 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5210 single_instruction;
5211 src1 : E(read);
5212 IALU : R;
5213 BR : R;
5214 %}
5215
5216 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5217 single_instruction_with_delay_slot;
5218 cr : E(read);
5219 BR : R;
5220 %}
5221
5222 pipe_class br_nop() %{
5223 single_instruction;
5224 BR : R;
5225 %}
5226
5227 pipe_class simple_call(method meth) %{
5228 instruction_count(2); multiple_bundles; force_serialization;
5229 fixed_latency(100);
5230 BR : R(1);
5231 MS : R(1);
5232 A0 : R(1);
5233 %}
5234
5235 pipe_class compiled_call(method meth) %{
5236 instruction_count(1); multiple_bundles; force_serialization;
5237 fixed_latency(100);
5238 MS : R(1);
5239 %}
5240
5241 pipe_class call(method meth) %{
5242 instruction_count(0); multiple_bundles; force_serialization;
5243 fixed_latency(100);
5244 %}
5245
5246 pipe_class tail_call(Universe ignore, label labl) %{
5247 single_instruction; has_delay_slot;
5248 fixed_latency(100);
5249 BR : R(1);
5250 MS : R(1);
5251 %}
5252
5253 pipe_class ret(Universe ignore) %{
5254 single_instruction; has_delay_slot;
5255 BR : R(1);
5256 MS : R(1);
5257 %}
5258
5259 pipe_class ret_poll(g3RegP poll) %{
5260 instruction_count(3); has_delay_slot;
5261 poll : E(read);
5262 MS : R;
5263 %}
5264
5265 // The real do-nothing guy
5266 pipe_class empty( ) %{
5267 instruction_count(0);
5268 %}
5269
5270 pipe_class long_memory_op() %{
5271 instruction_count(0); multiple_bundles; force_serialization;
5272 fixed_latency(25);
5273 MS : R(1);
5274 %}
5275
5276 // Check-cast
5277 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5278 array : R(read);
5279 match : R(read);
5280 IALU : R(2);
5281 BR : R(2);
5282 MS : R;
5283 %}
5284
5285 // Convert FPU flags into +1,0,-1
5286 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5287 src1 : E(read);
5288 src2 : E(read);
5289 dst : E(write);
5290 FA : R;
5291 MS : R(2);
5292 BR : R(2);
5293 %}
5294
5295 // Compare for p < q, and conditionally add y
5296 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5297 p : E(read);
5298 q : E(read);
5299 y : E(read);
5300 IALU : R(3)
5301 %}
5302
5303 // Perform a compare, then move conditionally in a branch delay slot.
5304 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5305 src2 : E(read);
5306 srcdst : E(read);
5307 IALU : R;
5308 BR : R;
5309 %}
5310
5311 // Define the class for the Nop node
5312 define %{
5313 MachNop = ialu_nop;
5314 %}
5315
5316 %}
5317
5318 //----------INSTRUCTIONS-------------------------------------------------------
5319
5320 //------------Special Stack Slot instructions - no match rules-----------------
5321 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5322 // No match rule to avoid chain rule match.
5323 effect(DEF dst, USE src);
5324 ins_cost(MEMORY_REF_COST);
5325 size(4);
5326 format %{ "LDF $src,$dst\t! stkI to regF" %}
5327 opcode(Assembler::ldf_op3);
5328 ins_encode(simple_form3_mem_reg(src, dst));
5329 ins_pipe(floadF_stk);
5330 %}
5331
5332 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5333 // No match rule to avoid chain rule match.
5334 effect(DEF dst, USE src);
5335 ins_cost(MEMORY_REF_COST);
5336 size(4);
5337 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5338 opcode(Assembler::lddf_op3);
5339 ins_encode(simple_form3_mem_reg(src, dst));
5340 ins_pipe(floadD_stk);
5341 %}
5342
5343 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5344 // No match rule to avoid chain rule match.
5345 effect(DEF dst, USE src);
5346 ins_cost(MEMORY_REF_COST);
5347 size(4);
5348 format %{ "STF $src,$dst\t! regF to stkI" %}
5349 opcode(Assembler::stf_op3);
5350 ins_encode(simple_form3_mem_reg(dst, src));
5351 ins_pipe(fstoreF_stk_reg);
5352 %}
5353
5354 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5355 // No match rule to avoid chain rule match.
5356 effect(DEF dst, USE src);
5357 ins_cost(MEMORY_REF_COST);
5358 size(4);
5359 format %{ "STDF $src,$dst\t! regD to stkL" %}
5360 opcode(Assembler::stdf_op3);
5361 ins_encode(simple_form3_mem_reg(dst, src));
5362 ins_pipe(fstoreD_stk_reg);
5363 %}
5364
5365 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5366 effect(DEF dst, USE src);
5367 ins_cost(MEMORY_REF_COST*2);
5368 size(8);
5369 format %{ "STW $src,$dst.hi\t! long\n\t"
5370 "STW R_G0,$dst.lo" %}
5371 opcode(Assembler::stw_op3);
5372 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5373 ins_pipe(lstoreI_stk_reg);
5374 %}
5375
5376 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5377 // No match rule to avoid chain rule match.
5378 effect(DEF dst, USE src);
5379 ins_cost(MEMORY_REF_COST);
5380 size(4);
5381 format %{ "STX $src,$dst\t! regL to stkD" %}
5382 opcode(Assembler::stx_op3);
5383 ins_encode(simple_form3_mem_reg( dst, src ) );
5384 ins_pipe(istore_stk_reg);
5385 %}
5386
5387 //---------- Chain stack slots between similar types --------
5388
5389 // Load integer from stack slot
5390 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5391 match(Set dst src);
5392 ins_cost(MEMORY_REF_COST);
5393
5394 size(4);
5395 format %{ "LDUW $src,$dst\t!stk" %}
5396 opcode(Assembler::lduw_op3);
5397 ins_encode(simple_form3_mem_reg( src, dst ) );
5398 ins_pipe(iload_mem);
5399 %}
5400
5401 // Store integer to stack slot
5402 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5403 match(Set dst src);
5404 ins_cost(MEMORY_REF_COST);
5405
5406 size(4);
5407 format %{ "STW $src,$dst\t!stk" %}
5408 opcode(Assembler::stw_op3);
5409 ins_encode(simple_form3_mem_reg( dst, src ) );
5410 ins_pipe(istore_mem_reg);
5411 %}
5412
5413 // Load long from stack slot
5414 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5415 match(Set dst src);
5416
5417 ins_cost(MEMORY_REF_COST);
5418 size(4);
5419 format %{ "LDX $src,$dst\t! long" %}
5420 opcode(Assembler::ldx_op3);
5421 ins_encode(simple_form3_mem_reg( src, dst ) );
5422 ins_pipe(iload_mem);
5423 %}
5424
5425 // Store long to stack slot
5426 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5427 match(Set dst src);
5428
5429 ins_cost(MEMORY_REF_COST);
5430 size(4);
5431 format %{ "STX $src,$dst\t! long" %}
5432 opcode(Assembler::stx_op3);
5433 ins_encode(simple_form3_mem_reg( dst, src ) );
5434 ins_pipe(istore_mem_reg);
5435 %}
5436
5437 #ifdef _LP64
5438 // Load pointer from stack slot, 64-bit encoding
5439 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5440 match(Set dst src);
5441 ins_cost(MEMORY_REF_COST);
5442 size(4);
5443 format %{ "LDX $src,$dst\t!ptr" %}
5444 opcode(Assembler::ldx_op3);
5445 ins_encode(simple_form3_mem_reg( src, dst ) );
5446 ins_pipe(iload_mem);
5447 %}
5448
5449 // Store pointer to stack slot
5450 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5451 match(Set dst src);
5452 ins_cost(MEMORY_REF_COST);
5453 size(4);
5454 format %{ "STX $src,$dst\t!ptr" %}
5455 opcode(Assembler::stx_op3);
5456 ins_encode(simple_form3_mem_reg( dst, src ) );
5457 ins_pipe(istore_mem_reg);
5458 %}
5459 #else // _LP64
5460 // Load pointer from stack slot, 32-bit encoding
5461 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5462 match(Set dst src);
5463 ins_cost(MEMORY_REF_COST);
5464 format %{ "LDUW $src,$dst\t!ptr" %}
5465 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5466 ins_encode(simple_form3_mem_reg( src, dst ) );
5467 ins_pipe(iload_mem);
5468 %}
5469
5470 // Store pointer to stack slot
5471 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5472 match(Set dst src);
5473 ins_cost(MEMORY_REF_COST);
5474 format %{ "STW $src,$dst\t!ptr" %}
5475 opcode(Assembler::stw_op3, Assembler::ldst_op);
5476 ins_encode(simple_form3_mem_reg( dst, src ) );
5477 ins_pipe(istore_mem_reg);
5478 %}
5479 #endif // _LP64
5480
5481 //------------Special Nop instructions for bundling - no match rules-----------
5482 // Nop using the A0 functional unit
5483 instruct Nop_A0() %{
5484 ins_cost(0);
5485
5486 format %{ "NOP ! Alu Pipeline" %}
5487 opcode(Assembler::or_op3, Assembler::arith_op);
5488 ins_encode( form2_nop() );
5489 ins_pipe(ialu_nop_A0);
5490 %}
5491
5492 // Nop using the A1 functional unit
5493 instruct Nop_A1( ) %{
5494 ins_cost(0);
5495
5496 format %{ "NOP ! Alu Pipeline" %}
5497 opcode(Assembler::or_op3, Assembler::arith_op);
5498 ins_encode( form2_nop() );
5499 ins_pipe(ialu_nop_A1);
5500 %}
5501
5502 // Nop using the memory functional unit
5503 instruct Nop_MS( ) %{
5504 ins_cost(0);
5505
5506 format %{ "NOP ! Memory Pipeline" %}
5507 ins_encode( emit_mem_nop );
5508 ins_pipe(mem_nop);
5509 %}
5510
5511 // Nop using the floating add functional unit
5512 instruct Nop_FA( ) %{
5513 ins_cost(0);
5514
5515 format %{ "NOP ! Floating Add Pipeline" %}
5516 ins_encode( emit_fadd_nop );
5517 ins_pipe(fadd_nop);
5518 %}
5519
5520 // Nop using the branch functional unit
5521 instruct Nop_BR( ) %{
5522 ins_cost(0);
5523
5524 format %{ "NOP ! Branch Pipeline" %}
5525 ins_encode( emit_br_nop );
5526 ins_pipe(br_nop);
5527 %}
5528
5529 //----------Load/Store/Move Instructions---------------------------------------
5530 //----------Load Instructions--------------------------------------------------
5531 // Load Byte (8bit signed)
5532 instruct loadB(iRegI dst, memory mem) %{
5533 match(Set dst (LoadB mem));
5534 ins_cost(MEMORY_REF_COST);
5535
5536 size(4);
5537 format %{ "LDSB $mem,$dst\t! byte" %}
5538 ins_encode %{
5539 __ ldsb($mem$$Address, $dst$$Register);
5540 %}
5541 ins_pipe(iload_mask_mem);
5542 %}
5543
5544 // Load Byte (8bit signed) into a Long Register
5545 instruct loadB2L(iRegL dst, memory mem) %{
5546 match(Set dst (ConvI2L (LoadB mem)));
5547 ins_cost(MEMORY_REF_COST);
5548
5549 size(4);
5550 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5551 ins_encode %{
5552 __ ldsb($mem$$Address, $dst$$Register);
5553 %}
5554 ins_pipe(iload_mask_mem);
5555 %}
5556
5557 // Load Unsigned Byte (8bit UNsigned) into an int reg
5558 instruct loadUB(iRegI dst, memory mem) %{
5559 match(Set dst (LoadUB mem));
5560 ins_cost(MEMORY_REF_COST);
5561
5562 size(4);
5563 format %{ "LDUB $mem,$dst\t! ubyte" %}
5564 ins_encode %{
5565 __ ldub($mem$$Address, $dst$$Register);
5566 %}
5567 ins_pipe(iload_mem);
5568 %}
5569
5570 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5571 instruct loadUB2L(iRegL dst, memory mem) %{
5572 match(Set dst (ConvI2L (LoadUB mem)));
5573 ins_cost(MEMORY_REF_COST);
5574
5575 size(4);
5576 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5577 ins_encode %{
5578 __ ldub($mem$$Address, $dst$$Register);
5579 %}
5580 ins_pipe(iload_mem);
5581 %}
5582
5583 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5584 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5585 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5586 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5587
5588 size(2*4);
5589 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5590 "AND $dst,$mask,$dst" %}
5591 ins_encode %{
5592 __ ldub($mem$$Address, $dst$$Register);
5593 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Short (16bit signed)
5599 instruct loadS(iRegI dst, memory mem) %{
5600 match(Set dst (LoadS mem));
5601 ins_cost(MEMORY_REF_COST);
5602
5603 size(4);
5604 format %{ "LDSH $mem,$dst\t! short" %}
5605 ins_encode %{
5606 __ ldsh($mem$$Address, $dst$$Register);
5607 %}
5608 ins_pipe(iload_mask_mem);
5609 %}
5610
5611 // Load Short (16 bit signed) to Byte (8 bit signed)
5612 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5613 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5614 ins_cost(MEMORY_REF_COST);
5615
5616 size(4);
5617
5618 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5619 ins_encode %{
5620 __ ldsb($mem$$Address, $dst$$Register, 1);
5621 %}
5622 ins_pipe(iload_mask_mem);
5623 %}
5624
5625 // Load Short (16bit signed) into a Long Register
5626 instruct loadS2L(iRegL dst, memory mem) %{
5627 match(Set dst (ConvI2L (LoadS mem)));
5628 ins_cost(MEMORY_REF_COST);
5629
5630 size(4);
5631 format %{ "LDSH $mem,$dst\t! short -> long" %}
5632 ins_encode %{
5633 __ ldsh($mem$$Address, $dst$$Register);
5634 %}
5635 ins_pipe(iload_mask_mem);
5636 %}
5637
5638 // Load Unsigned Short/Char (16bit UNsigned)
5639 instruct loadUS(iRegI dst, memory mem) %{
5640 match(Set dst (LoadUS mem));
5641 ins_cost(MEMORY_REF_COST);
5642
5643 size(4);
5644 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5645 ins_encode %{
5646 __ lduh($mem$$Address, $dst$$Register);
5647 %}
5648 ins_pipe(iload_mem);
5649 %}
5650
5651 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5652 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5653 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5654 ins_cost(MEMORY_REF_COST);
5655
5656 size(4);
5657 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5658 ins_encode %{
5659 __ ldsb($mem$$Address, $dst$$Register, 1);
5660 %}
5661 ins_pipe(iload_mask_mem);
5662 %}
5663
5664 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5665 instruct loadUS2L(iRegL dst, memory mem) %{
5666 match(Set dst (ConvI2L (LoadUS mem)));
5667 ins_cost(MEMORY_REF_COST);
5668
5669 size(4);
5670 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5671 ins_encode %{
5672 __ lduh($mem$$Address, $dst$$Register);
5673 %}
5674 ins_pipe(iload_mem);
5675 %}
5676
5677 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5678 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5679 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5680 ins_cost(MEMORY_REF_COST);
5681
5682 size(4);
5683 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5684 ins_encode %{
5685 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5686 %}
5687 ins_pipe(iload_mem);
5688 %}
5689
5690 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5691 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5692 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5693 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5694
5695 size(2*4);
5696 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5697 "AND $dst,$mask,$dst" %}
5698 ins_encode %{
5699 Register Rdst = $dst$$Register;
5700 __ lduh($mem$$Address, Rdst);
5701 __ and3(Rdst, $mask$$constant, Rdst);
5702 %}
5703 ins_pipe(iload_mem);
5704 %}
5705
5706 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5707 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5708 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5709 effect(TEMP dst, TEMP tmp);
5710 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5711
5712 size((3+1)*4); // set may use two instructions.
5713 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5714 "SET $mask,$tmp\n\t"
5715 "AND $dst,$tmp,$dst" %}
5716 ins_encode %{
5717 Register Rdst = $dst$$Register;
5718 Register Rtmp = $tmp$$Register;
5719 __ lduh($mem$$Address, Rdst);
5720 __ set($mask$$constant, Rtmp);
5721 __ and3(Rdst, Rtmp, Rdst);
5722 %}
5723 ins_pipe(iload_mem);
5724 %}
5725
5726 // Load Integer
5727 instruct loadI(iRegI dst, memory mem) %{
5728 match(Set dst (LoadI mem));
5729 ins_cost(MEMORY_REF_COST);
5730
5731 size(4);
5732 format %{ "LDUW $mem,$dst\t! int" %}
5733 ins_encode %{
5734 __ lduw($mem$$Address, $dst$$Register);
5735 %}
5736 ins_pipe(iload_mem);
5737 %}
5738
5739 // Load Integer to Byte (8 bit signed)
5740 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5741 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5742 ins_cost(MEMORY_REF_COST);
5743
5744 size(4);
5745
5746 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5747 ins_encode %{
5748 __ ldsb($mem$$Address, $dst$$Register, 3);
5749 %}
5750 ins_pipe(iload_mask_mem);
5751 %}
5752
5753 // Load Integer to Unsigned Byte (8 bit UNsigned)
5754 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5755 match(Set dst (AndI (LoadI mem) mask));
5756 ins_cost(MEMORY_REF_COST);
5757
5758 size(4);
5759
5760 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5761 ins_encode %{
5762 __ ldub($mem$$Address, $dst$$Register, 3);
5763 %}
5764 ins_pipe(iload_mask_mem);
5765 %}
5766
5767 // Load Integer to Short (16 bit signed)
5768 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5769 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5770 ins_cost(MEMORY_REF_COST);
5771
5772 size(4);
5773
5774 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5775 ins_encode %{
5776 __ ldsh($mem$$Address, $dst$$Register, 2);
5777 %}
5778 ins_pipe(iload_mask_mem);
5779 %}
5780
5781 // Load Integer to Unsigned Short (16 bit UNsigned)
5782 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5783 match(Set dst (AndI (LoadI mem) mask));
5784 ins_cost(MEMORY_REF_COST);
5785
5786 size(4);
5787
5788 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5789 ins_encode %{
5790 __ lduh($mem$$Address, $dst$$Register, 2);
5791 %}
5792 ins_pipe(iload_mask_mem);
5793 %}
5794
5795 // Load Integer into a Long Register
5796 instruct loadI2L(iRegL dst, memory mem) %{
5797 match(Set dst (ConvI2L (LoadI mem)));
5798 ins_cost(MEMORY_REF_COST);
5799
5800 size(4);
5801 format %{ "LDSW $mem,$dst\t! int -> long" %}
5802 ins_encode %{
5803 __ ldsw($mem$$Address, $dst$$Register);
5804 %}
5805 ins_pipe(iload_mask_mem);
5806 %}
5807
5808 // Load Integer with mask 0xFF into a Long Register
5809 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5810 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5811 ins_cost(MEMORY_REF_COST);
5812
5813 size(4);
5814 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5815 ins_encode %{
5816 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5817 %}
5818 ins_pipe(iload_mem);
5819 %}
5820
5821 // Load Integer with mask 0xFFFF into a Long Register
5822 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5823 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5824 ins_cost(MEMORY_REF_COST);
5825
5826 size(4);
5827 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5828 ins_encode %{
5829 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5830 %}
5831 ins_pipe(iload_mem);
5832 %}
5833
5834 // Load Integer with a 13-bit mask into a Long Register
5835 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5836 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5837 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5838
5839 size(2*4);
5840 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5841 "AND $dst,$mask,$dst" %}
5842 ins_encode %{
5843 Register Rdst = $dst$$Register;
5844 __ lduw($mem$$Address, Rdst);
5845 __ and3(Rdst, $mask$$constant, Rdst);
5846 %}
5847 ins_pipe(iload_mem);
5848 %}
5849
5850 // Load Integer with a 32-bit mask into a Long Register
5851 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5852 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5853 effect(TEMP dst, TEMP tmp);
5854 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5855
5856 size((3+1)*4); // set may use two instructions.
5857 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5858 "SET $mask,$tmp\n\t"
5859 "AND $dst,$tmp,$dst" %}
5860 ins_encode %{
5861 Register Rdst = $dst$$Register;
5862 Register Rtmp = $tmp$$Register;
5863 __ lduw($mem$$Address, Rdst);
5864 __ set($mask$$constant, Rtmp);
5865 __ and3(Rdst, Rtmp, Rdst);
5866 %}
5867 ins_pipe(iload_mem);
5868 %}
5869
5870 // Load Unsigned Integer into a Long Register
5871 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5872 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5873 ins_cost(MEMORY_REF_COST);
5874
5875 size(4);
5876 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5877 ins_encode %{
5878 __ lduw($mem$$Address, $dst$$Register);
5879 %}
5880 ins_pipe(iload_mem);
5881 %}
5882
5883 // Load Long - aligned
5884 instruct loadL(iRegL dst, memory mem ) %{
5885 match(Set dst (LoadL mem));
5886 ins_cost(MEMORY_REF_COST);
5887
5888 size(4);
5889 format %{ "LDX $mem,$dst\t! long" %}
5890 ins_encode %{
5891 __ ldx($mem$$Address, $dst$$Register);
5892 %}
5893 ins_pipe(iload_mem);
5894 %}
5895
5896 // Load Long - UNaligned
5897 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5898 match(Set dst (LoadL_unaligned mem));
5899 effect(KILL tmp);
5900 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5901 size(16);
5902 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5903 "\tLDUW $mem ,$dst\n"
5904 "\tSLLX #32, $dst, $dst\n"
5905 "\tOR $dst, R_O7, $dst" %}
5906 opcode(Assembler::lduw_op3);
5907 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5908 ins_pipe(iload_mem);
5909 %}
5910
5911 // Load Range
5912 instruct loadRange(iRegI dst, memory mem) %{
5913 match(Set dst (LoadRange mem));
5914 ins_cost(MEMORY_REF_COST);
5915
5916 size(4);
5917 format %{ "LDUW $mem,$dst\t! range" %}
5918 opcode(Assembler::lduw_op3);
5919 ins_encode(simple_form3_mem_reg( mem, dst ) );
5920 ins_pipe(iload_mem);
5921 %}
5922
5923 // Load Integer into %f register (for fitos/fitod)
5924 instruct loadI_freg(regF dst, memory mem) %{
5925 match(Set dst (LoadI mem));
5926 ins_cost(MEMORY_REF_COST);
5927 size(4);
5928
5929 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5930 opcode(Assembler::ldf_op3);
5931 ins_encode(simple_form3_mem_reg( mem, dst ) );
5932 ins_pipe(floadF_mem);
5933 %}
5934
5935 // Load Pointer
5936 instruct loadP(iRegP dst, memory mem) %{
5937 match(Set dst (LoadP mem));
5938 ins_cost(MEMORY_REF_COST);
5939 size(4);
5940
5941 #ifndef _LP64
5942 format %{ "LDUW $mem,$dst\t! ptr" %}
5943 ins_encode %{
5944 __ lduw($mem$$Address, $dst$$Register);
5945 %}
5946 #else
5947 format %{ "LDX $mem,$dst\t! ptr" %}
5948 ins_encode %{
5949 __ ldx($mem$$Address, $dst$$Register);
5950 %}
5951 #endif
5952 ins_pipe(iload_mem);
5953 %}
5954
5955 // Load Compressed Pointer
5956 instruct loadN(iRegN dst, memory mem) %{
5957 match(Set dst (LoadN mem));
5958 ins_cost(MEMORY_REF_COST);
5959 size(4);
5960
5961 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5962 ins_encode %{
5963 __ lduw($mem$$Address, $dst$$Register);
5964 %}
5965 ins_pipe(iload_mem);
5966 %}
5967
5968 // Load Klass Pointer
5969 instruct loadKlass(iRegP dst, memory mem) %{
5970 match(Set dst (LoadKlass mem));
5971 ins_cost(MEMORY_REF_COST);
5972 size(4);
5973
5974 #ifndef _LP64
5975 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5976 ins_encode %{
5977 __ lduw($mem$$Address, $dst$$Register);
5978 %}
5979 #else
5980 format %{ "LDX $mem,$dst\t! klass ptr" %}
5981 ins_encode %{
5982 __ ldx($mem$$Address, $dst$$Register);
5983 %}
5984 #endif
5985 ins_pipe(iload_mem);
5986 %}
5987
5988 // Load narrow Klass Pointer
5989 instruct loadNKlass(iRegN dst, memory mem) %{
5990 match(Set dst (LoadNKlass mem));
5991 ins_cost(MEMORY_REF_COST);
5992 size(4);
5993
5994 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5995 ins_encode %{
5996 __ lduw($mem$$Address, $dst$$Register);
5997 %}
5998 ins_pipe(iload_mem);
5999 %}
6000
6001 // Load Double
6002 instruct loadD(regD dst, memory mem) %{
6003 match(Set dst (LoadD mem));
6004 ins_cost(MEMORY_REF_COST);
6005
6006 size(4);
6007 format %{ "LDDF $mem,$dst" %}
6008 opcode(Assembler::lddf_op3);
6009 ins_encode(simple_form3_mem_reg( mem, dst ) );
6010 ins_pipe(floadD_mem);
6011 %}
6012
6013 // Load Double - UNaligned
6014 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6015 match(Set dst (LoadD_unaligned mem));
6016 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6017 size(8);
6018 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6019 "\tLDF $mem+4,$dst.lo\t!" %}
6020 opcode(Assembler::ldf_op3);
6021 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6022 ins_pipe(iload_mem);
6023 %}
6024
6025 // Load Float
6026 instruct loadF(regF dst, memory mem) %{
6027 match(Set dst (LoadF mem));
6028 ins_cost(MEMORY_REF_COST);
6029
6030 size(4);
6031 format %{ "LDF $mem,$dst" %}
6032 opcode(Assembler::ldf_op3);
6033 ins_encode(simple_form3_mem_reg( mem, dst ) );
6034 ins_pipe(floadF_mem);
6035 %}
6036
6037 // Load Constant
6038 instruct loadConI( iRegI dst, immI src ) %{
6039 match(Set dst src);
6040 ins_cost(DEFAULT_COST * 3/2);
6041 format %{ "SET $src,$dst" %}
6042 ins_encode( Set32(src, dst) );
6043 ins_pipe(ialu_hi_lo_reg);
6044 %}
6045
6046 instruct loadConI13( iRegI dst, immI13 src ) %{
6047 match(Set dst src);
6048
6049 size(4);
6050 format %{ "MOV $src,$dst" %}
6051 ins_encode( Set13( src, dst ) );
6052 ins_pipe(ialu_imm);
6053 %}
6054
6055 #ifndef _LP64
6056 instruct loadConP(iRegP dst, immP con) %{
6057 match(Set dst con);
6058 ins_cost(DEFAULT_COST * 3/2);
6059 format %{ "SET $con,$dst\t!ptr" %}
6060 ins_encode %{
6061 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6062 intptr_t val = $con$$constant;
6063 if (constant_reloc == relocInfo::oop_type) {
6064 __ set_oop_constant((jobject) val, $dst$$Register);
6065 } else if (constant_reloc == relocInfo::metadata_type) {
6066 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6067 } else { // non-oop pointers, e.g. card mark base, heap top
6068 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6069 __ set(val, $dst$$Register);
6070 }
6071 %}
6072 ins_pipe(loadConP);
6073 %}
6074 #else
6075 instruct loadConP_set(iRegP dst, immP_set con) %{
6076 match(Set dst con);
6077 ins_cost(DEFAULT_COST * 3/2);
6078 format %{ "SET $con,$dst\t! ptr" %}
6079 ins_encode %{
6080 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6081 intptr_t val = $con$$constant;
6082 if (constant_reloc == relocInfo::oop_type) {
6083 __ set_oop_constant((jobject) val, $dst$$Register);
6084 } else if (constant_reloc == relocInfo::metadata_type) {
6085 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6086 } else { // non-oop pointers, e.g. card mark base, heap top
6087 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6088 __ set(val, $dst$$Register);
6089 }
6090 %}
6091 ins_pipe(loadConP);
6092 %}
6093
6094 instruct loadConP_load(iRegP dst, immP_load con) %{
6095 match(Set dst con);
6096 ins_cost(MEMORY_REF_COST);
6097 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6098 ins_encode %{
6099 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6100 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6101 %}
6102 ins_pipe(loadConP);
6103 %}
6104
6105 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6106 match(Set dst con);
6107 ins_cost(DEFAULT_COST * 3/2);
6108 format %{ "SET $con,$dst\t! non-oop ptr" %}
6109 ins_encode %{
6110 __ set($con$$constant, $dst$$Register);
6111 %}
6112 ins_pipe(loadConP);
6113 %}
6114 #endif // _LP64
6115
6116 instruct loadConP0(iRegP dst, immP0 src) %{
6117 match(Set dst src);
6118
6119 size(4);
6120 format %{ "CLR $dst\t!ptr" %}
6121 ins_encode %{
6122 __ clr($dst$$Register);
6123 %}
6124 ins_pipe(ialu_imm);
6125 %}
6126
6127 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6128 match(Set dst src);
6129 ins_cost(DEFAULT_COST);
6130 format %{ "SET $src,$dst\t!ptr" %}
6131 ins_encode %{
6132 AddressLiteral polling_page(os::get_polling_page());
6133 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6134 %}
6135 ins_pipe(loadConP_poll);
6136 %}
6137
6138 instruct loadConN0(iRegN dst, immN0 src) %{
6139 match(Set dst src);
6140
6141 size(4);
6142 format %{ "CLR $dst\t! compressed NULL ptr" %}
6143 ins_encode %{
6144 __ clr($dst$$Register);
6145 %}
6146 ins_pipe(ialu_imm);
6147 %}
6148
6149 instruct loadConN(iRegN dst, immN src) %{
6150 match(Set dst src);
6151 ins_cost(DEFAULT_COST * 3/2);
6152 format %{ "SET $src,$dst\t! compressed ptr" %}
6153 ins_encode %{
6154 Register dst = $dst$$Register;
6155 __ set_narrow_oop((jobject)$src$$constant, dst);
6156 %}
6157 ins_pipe(ialu_hi_lo_reg);
6158 %}
6159
6160 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6161 match(Set dst src);
6162 ins_cost(DEFAULT_COST * 3/2);
6163 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6164 ins_encode %{
6165 Register dst = $dst$$Register;
6166 __ set_narrow_klass((Klass*)$src$$constant, dst);
6167 %}
6168 ins_pipe(ialu_hi_lo_reg);
6169 %}
6170
6171 // Materialize long value (predicated by immL_cheap).
6172 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6173 match(Set dst con);
6174 effect(KILL tmp);
6175 ins_cost(DEFAULT_COST * 3);
6176 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6177 ins_encode %{
6178 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6179 %}
6180 ins_pipe(loadConL);
6181 %}
6182
6183 // Load long value from constant table (predicated by immL_expensive).
6184 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6185 match(Set dst con);
6186 ins_cost(MEMORY_REF_COST);
6187 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6188 ins_encode %{
6189 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6190 __ ldx($constanttablebase, con_offset, $dst$$Register);
6191 %}
6192 ins_pipe(loadConL);
6193 %}
6194
6195 instruct loadConL0( iRegL dst, immL0 src ) %{
6196 match(Set dst src);
6197 ins_cost(DEFAULT_COST);
6198 size(4);
6199 format %{ "CLR $dst\t! long" %}
6200 ins_encode( Set13( src, dst ) );
6201 ins_pipe(ialu_imm);
6202 %}
6203
6204 instruct loadConL13( iRegL dst, immL13 src ) %{
6205 match(Set dst src);
6206 ins_cost(DEFAULT_COST * 2);
6207
6208 size(4);
6209 format %{ "MOV $src,$dst\t! long" %}
6210 ins_encode( Set13( src, dst ) );
6211 ins_pipe(ialu_imm);
6212 %}
6213
6214 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6215 match(Set dst con);
6216 effect(KILL tmp);
6217 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6218 ins_encode %{
6219 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6220 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6221 %}
6222 ins_pipe(loadConFD);
6223 %}
6224
6225 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6226 match(Set dst con);
6227 effect(KILL tmp);
6228 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6229 ins_encode %{
6230 // XXX This is a quick fix for 6833573.
6231 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6232 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6233 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6234 %}
6235 ins_pipe(loadConFD);
6236 %}
6237
6238 // Prefetch instructions.
6239 // Must be safe to execute with invalid address (cannot fault).
6240
6241 instruct prefetchr( memory mem ) %{
6242 match( PrefetchRead mem );
6243 ins_cost(MEMORY_REF_COST);
6244 size(4);
6245
6246 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6247 opcode(Assembler::prefetch_op3);
6248 ins_encode( form3_mem_prefetch_read( mem ) );
6249 ins_pipe(iload_mem);
6250 %}
6251
6252 instruct prefetchw( memory mem ) %{
6253 match( PrefetchWrite mem );
6254 ins_cost(MEMORY_REF_COST);
6255 size(4);
6256
6257 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6258 opcode(Assembler::prefetch_op3);
6259 ins_encode( form3_mem_prefetch_write( mem ) );
6260 ins_pipe(iload_mem);
6261 %}
6262
6263 // Prefetch instructions for allocation.
6264
6265 instruct prefetchAlloc( memory mem ) %{
6266 predicate(AllocatePrefetchInstr == 0);
6267 match( PrefetchAllocation mem );
6268 ins_cost(MEMORY_REF_COST);
6269 size(4);
6270
6271 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6272 opcode(Assembler::prefetch_op3);
6273 ins_encode( form3_mem_prefetch_write( mem ) );
6274 ins_pipe(iload_mem);
6275 %}
6276
6277 // Use BIS instruction to prefetch for allocation.
6278 // Could fault, need space at the end of TLAB.
6279 instruct prefetchAlloc_bis( iRegP dst ) %{
6280 predicate(AllocatePrefetchInstr == 1);
6281 match( PrefetchAllocation dst );
6282 ins_cost(MEMORY_REF_COST);
6283 size(4);
6284
6285 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6286 ins_encode %{
6287 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6288 %}
6289 ins_pipe(istore_mem_reg);
6290 %}
6291
6292 // Next code is used for finding next cache line address to prefetch.
6293 #ifndef _LP64
6294 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6295 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6296 ins_cost(DEFAULT_COST);
6297 size(4);
6298
6299 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6300 ins_encode %{
6301 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6302 %}
6303 ins_pipe(ialu_reg_imm);
6304 %}
6305 #else
6306 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6307 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6308 ins_cost(DEFAULT_COST);
6309 size(4);
6310
6311 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6312 ins_encode %{
6313 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6314 %}
6315 ins_pipe(ialu_reg_imm);
6316 %}
6317 #endif
6318
6319 //----------Store Instructions-------------------------------------------------
6320 // Store Byte
6321 instruct storeB(memory mem, iRegI src) %{
6322 match(Set mem (StoreB mem src));
6323 ins_cost(MEMORY_REF_COST);
6324
6325 size(4);
6326 format %{ "STB $src,$mem\t! byte" %}
6327 opcode(Assembler::stb_op3);
6328 ins_encode(simple_form3_mem_reg( mem, src ) );
6329 ins_pipe(istore_mem_reg);
6330 %}
6331
6332 instruct storeB0(memory mem, immI0 src) %{
6333 match(Set mem (StoreB mem src));
6334 ins_cost(MEMORY_REF_COST);
6335
6336 size(4);
6337 format %{ "STB $src,$mem\t! byte" %}
6338 opcode(Assembler::stb_op3);
6339 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6340 ins_pipe(istore_mem_zero);
6341 %}
6342
6343 instruct storeCM0(memory mem, immI0 src) %{
6344 match(Set mem (StoreCM mem src));
6345 ins_cost(MEMORY_REF_COST);
6346
6347 size(4);
6348 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6349 opcode(Assembler::stb_op3);
6350 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6351 ins_pipe(istore_mem_zero);
6352 %}
6353
6354 // Store Char/Short
6355 instruct storeC(memory mem, iRegI src) %{
6356 match(Set mem (StoreC mem src));
6357 ins_cost(MEMORY_REF_COST);
6358
6359 size(4);
6360 format %{ "STH $src,$mem\t! short" %}
6361 opcode(Assembler::sth_op3);
6362 ins_encode(simple_form3_mem_reg( mem, src ) );
6363 ins_pipe(istore_mem_reg);
6364 %}
6365
6366 instruct storeC0(memory mem, immI0 src) %{
6367 match(Set mem (StoreC mem src));
6368 ins_cost(MEMORY_REF_COST);
6369
6370 size(4);
6371 format %{ "STH $src,$mem\t! short" %}
6372 opcode(Assembler::sth_op3);
6373 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6374 ins_pipe(istore_mem_zero);
6375 %}
6376
6377 // Store Integer
6378 instruct storeI(memory mem, iRegI src) %{
6379 match(Set mem (StoreI mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STW $src,$mem" %}
6384 opcode(Assembler::stw_op3);
6385 ins_encode(simple_form3_mem_reg( mem, src ) );
6386 ins_pipe(istore_mem_reg);
6387 %}
6388
6389 // Store Long
6390 instruct storeL(memory mem, iRegL src) %{
6391 match(Set mem (StoreL mem src));
6392 ins_cost(MEMORY_REF_COST);
6393 size(4);
6394 format %{ "STX $src,$mem\t! long" %}
6395 opcode(Assembler::stx_op3);
6396 ins_encode(simple_form3_mem_reg( mem, src ) );
6397 ins_pipe(istore_mem_reg);
6398 %}
6399
6400 instruct storeI0(memory mem, immI0 src) %{
6401 match(Set mem (StoreI mem src));
6402 ins_cost(MEMORY_REF_COST);
6403
6404 size(4);
6405 format %{ "STW $src,$mem" %}
6406 opcode(Assembler::stw_op3);
6407 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6408 ins_pipe(istore_mem_zero);
6409 %}
6410
6411 instruct storeL0(memory mem, immL0 src) %{
6412 match(Set mem (StoreL mem src));
6413 ins_cost(MEMORY_REF_COST);
6414
6415 size(4);
6416 format %{ "STX $src,$mem" %}
6417 opcode(Assembler::stx_op3);
6418 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6419 ins_pipe(istore_mem_zero);
6420 %}
6421
6422 // Store Integer from float register (used after fstoi)
6423 instruct storeI_Freg(memory mem, regF src) %{
6424 match(Set mem (StoreI mem src));
6425 ins_cost(MEMORY_REF_COST);
6426
6427 size(4);
6428 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6429 opcode(Assembler::stf_op3);
6430 ins_encode(simple_form3_mem_reg( mem, src ) );
6431 ins_pipe(fstoreF_mem_reg);
6432 %}
6433
6434 // Store Pointer
6435 instruct storeP(memory dst, sp_ptr_RegP src) %{
6436 match(Set dst (StoreP dst src));
6437 ins_cost(MEMORY_REF_COST);
6438 size(4);
6439
6440 #ifndef _LP64
6441 format %{ "STW $src,$dst\t! ptr" %}
6442 opcode(Assembler::stw_op3, 0, REGP_OP);
6443 #else
6444 format %{ "STX $src,$dst\t! ptr" %}
6445 opcode(Assembler::stx_op3, 0, REGP_OP);
6446 #endif
6447 ins_encode( form3_mem_reg( dst, src ) );
6448 ins_pipe(istore_mem_spORreg);
6449 %}
6450
6451 instruct storeP0(memory dst, immP0 src) %{
6452 match(Set dst (StoreP dst src));
6453 ins_cost(MEMORY_REF_COST);
6454 size(4);
6455
6456 #ifndef _LP64
6457 format %{ "STW $src,$dst\t! ptr" %}
6458 opcode(Assembler::stw_op3, 0, REGP_OP);
6459 #else
6460 format %{ "STX $src,$dst\t! ptr" %}
6461 opcode(Assembler::stx_op3, 0, REGP_OP);
6462 #endif
6463 ins_encode( form3_mem_reg( dst, R_G0 ) );
6464 ins_pipe(istore_mem_zero);
6465 %}
6466
6467 // Store Compressed Pointer
6468 instruct storeN(memory dst, iRegN src) %{
6469 match(Set dst (StoreN dst src));
6470 ins_cost(MEMORY_REF_COST);
6471 size(4);
6472
6473 format %{ "STW $src,$dst\t! compressed ptr" %}
6474 ins_encode %{
6475 Register base = as_Register($dst$$base);
6476 Register index = as_Register($dst$$index);
6477 Register src = $src$$Register;
6478 if (index != G0) {
6479 __ stw(src, base, index);
6480 } else {
6481 __ stw(src, base, $dst$$disp);
6482 }
6483 %}
6484 ins_pipe(istore_mem_spORreg);
6485 %}
6486
6487 instruct storeNKlass(memory dst, iRegN src) %{
6488 match(Set dst (StoreNKlass dst src));
6489 ins_cost(MEMORY_REF_COST);
6490 size(4);
6491
6492 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6493 ins_encode %{
6494 Register base = as_Register($dst$$base);
6495 Register index = as_Register($dst$$index);
6496 Register src = $src$$Register;
6497 if (index != G0) {
6498 __ stw(src, base, index);
6499 } else {
6500 __ stw(src, base, $dst$$disp);
6501 }
6502 %}
6503 ins_pipe(istore_mem_spORreg);
6504 %}
6505
6506 instruct storeN0(memory dst, immN0 src) %{
6507 match(Set dst (StoreN dst src));
6508 ins_cost(MEMORY_REF_COST);
6509 size(4);
6510
6511 format %{ "STW $src,$dst\t! compressed ptr" %}
6512 ins_encode %{
6513 Register base = as_Register($dst$$base);
6514 Register index = as_Register($dst$$index);
6515 if (index != G0) {
6516 __ stw(0, base, index);
6517 } else {
6518 __ stw(0, base, $dst$$disp);
6519 }
6520 %}
6521 ins_pipe(istore_mem_zero);
6522 %}
6523
6524 // Store Double
6525 instruct storeD( memory mem, regD src) %{
6526 match(Set mem (StoreD mem src));
6527 ins_cost(MEMORY_REF_COST);
6528
6529 size(4);
6530 format %{ "STDF $src,$mem" %}
6531 opcode(Assembler::stdf_op3);
6532 ins_encode(simple_form3_mem_reg( mem, src ) );
6533 ins_pipe(fstoreD_mem_reg);
6534 %}
6535
6536 instruct storeD0( memory mem, immD0 src) %{
6537 match(Set mem (StoreD mem src));
6538 ins_cost(MEMORY_REF_COST);
6539
6540 size(4);
6541 format %{ "STX $src,$mem" %}
6542 opcode(Assembler::stx_op3);
6543 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6544 ins_pipe(fstoreD_mem_zero);
6545 %}
6546
6547 // Store Float
6548 instruct storeF( memory mem, regF src) %{
6549 match(Set mem (StoreF mem src));
6550 ins_cost(MEMORY_REF_COST);
6551
6552 size(4);
6553 format %{ "STF $src,$mem" %}
6554 opcode(Assembler::stf_op3);
6555 ins_encode(simple_form3_mem_reg( mem, src ) );
6556 ins_pipe(fstoreF_mem_reg);
6557 %}
6558
6559 instruct storeF0( memory mem, immF0 src) %{
6560 match(Set mem (StoreF mem src));
6561 ins_cost(MEMORY_REF_COST);
6562
6563 size(4);
6564 format %{ "STW $src,$mem\t! storeF0" %}
6565 opcode(Assembler::stw_op3);
6566 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6567 ins_pipe(fstoreF_mem_zero);
6568 %}
6569
6570 // Convert oop pointer into compressed form
6571 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6572 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6573 match(Set dst (EncodeP src));
6574 format %{ "encode_heap_oop $src, $dst" %}
6575 ins_encode %{
6576 __ encode_heap_oop($src$$Register, $dst$$Register);
6577 %}
6578 ins_pipe(ialu_reg);
6579 %}
6580
6581 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6582 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6583 match(Set dst (EncodeP src));
6584 format %{ "encode_heap_oop_not_null $src, $dst" %}
6585 ins_encode %{
6586 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6587 %}
6588 ins_pipe(ialu_reg);
6589 %}
6590
6591 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6592 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6593 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6594 match(Set dst (DecodeN src));
6595 format %{ "decode_heap_oop $src, $dst" %}
6596 ins_encode %{
6597 __ decode_heap_oop($src$$Register, $dst$$Register);
6598 %}
6599 ins_pipe(ialu_reg);
6600 %}
6601
6602 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6603 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6604 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6605 match(Set dst (DecodeN src));
6606 format %{ "decode_heap_oop_not_null $src, $dst" %}
6607 ins_encode %{
6608 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6609 %}
6610 ins_pipe(ialu_reg);
6611 %}
6612
6613 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6614 match(Set dst (EncodePKlass src));
6615 format %{ "encode_klass_not_null $src, $dst" %}
6616 ins_encode %{
6617 __ encode_klass_not_null($src$$Register, $dst$$Register);
6618 %}
6619 ins_pipe(ialu_reg);
6620 %}
6621
6622 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6623 match(Set dst (DecodeNKlass src));
6624 format %{ "decode_klass_not_null $src, $dst" %}
6625 ins_encode %{
6626 __ decode_klass_not_null($src$$Register, $dst$$Register);
6627 %}
6628 ins_pipe(ialu_reg);
6629 %}
6630
6631 //----------MemBar Instructions-----------------------------------------------
6632 // Memory barrier flavors
6633
6634 instruct membar_acquire() %{
6635 match(MemBarAcquire);
6636 ins_cost(4*MEMORY_REF_COST);
6637
6638 size(0);
6639 format %{ "MEMBAR-acquire" %}
6640 ins_encode( enc_membar_acquire );
6641 ins_pipe(long_memory_op);
6642 %}
6643
6644 instruct membar_acquire_lock() %{
6645 match(MemBarAcquireLock);
6646 ins_cost(0);
6647
6648 size(0);
6649 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6650 ins_encode( );
6651 ins_pipe(empty);
6652 %}
6653
6654 instruct membar_release() %{
6655 match(MemBarRelease);
6656 ins_cost(4*MEMORY_REF_COST);
6657
6658 size(0);
6659 format %{ "MEMBAR-release" %}
6660 ins_encode( enc_membar_release );
6661 ins_pipe(long_memory_op);
6662 %}
6663
6664 instruct membar_release_lock() %{
6665 match(MemBarReleaseLock);
6666 ins_cost(0);
6667
6668 size(0);
6669 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6670 ins_encode( );
6671 ins_pipe(empty);
6672 %}
6673
6674 instruct membar_volatile() %{
6675 match(MemBarVolatile);
6676 ins_cost(4*MEMORY_REF_COST);
6677
6678 size(4);
6679 format %{ "MEMBAR-volatile" %}
6680 ins_encode( enc_membar_volatile );
6681 ins_pipe(long_memory_op);
6682 %}
6683
6684 instruct unnecessary_membar_volatile() %{
6685 match(MemBarVolatile);
6686 predicate(Matcher::post_store_load_barrier(n));
6687 ins_cost(0);
6688
6689 size(0);
6690 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6691 ins_encode( );
6692 ins_pipe(empty);
6693 %}
6694
6695 instruct membar_storestore() %{
6696 match(MemBarStoreStore);
6697 ins_cost(0);
6698
6699 size(0);
6700 format %{ "!MEMBAR-storestore (empty encoding)" %}
6701 ins_encode( );
6702 ins_pipe(empty);
6703 %}
6704
6705 //----------Register Move Instructions-----------------------------------------
6706 instruct roundDouble_nop(regD dst) %{
6707 match(Set dst (RoundDouble dst));
6708 ins_cost(0);
6709 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6710 ins_encode( );
6711 ins_pipe(empty);
6712 %}
6713
6714
6715 instruct roundFloat_nop(regF dst) %{
6716 match(Set dst (RoundFloat dst));
6717 ins_cost(0);
6718 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6719 ins_encode( );
6720 ins_pipe(empty);
6721 %}
6722
6723
6724 // Cast Index to Pointer for unsafe natives
6725 instruct castX2P(iRegX src, iRegP dst) %{
6726 match(Set dst (CastX2P src));
6727
6728 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6729 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6730 ins_pipe(ialu_reg);
6731 %}
6732
6733 // Cast Pointer to Index for unsafe natives
6734 instruct castP2X(iRegP src, iRegX dst) %{
6735 match(Set dst (CastP2X src));
6736
6737 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6738 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6739 ins_pipe(ialu_reg);
6740 %}
6741
6742 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6743 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6744 match(Set stkSlot src); // chain rule
6745 ins_cost(MEMORY_REF_COST);
6746 format %{ "STDF $src,$stkSlot\t!stk" %}
6747 opcode(Assembler::stdf_op3);
6748 ins_encode(simple_form3_mem_reg(stkSlot, src));
6749 ins_pipe(fstoreD_stk_reg);
6750 %}
6751
6752 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6753 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6754 match(Set dst stkSlot); // chain rule
6755 ins_cost(MEMORY_REF_COST);
6756 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6757 opcode(Assembler::lddf_op3);
6758 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6759 ins_pipe(floadD_stk);
6760 %}
6761
6762 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6763 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6764 match(Set stkSlot src); // chain rule
6765 ins_cost(MEMORY_REF_COST);
6766 format %{ "STF $src,$stkSlot\t!stk" %}
6767 opcode(Assembler::stf_op3);
6768 ins_encode(simple_form3_mem_reg(stkSlot, src));
6769 ins_pipe(fstoreF_stk_reg);
6770 %}
6771
6772 //----------Conditional Move---------------------------------------------------
6773 // Conditional move
6774 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6775 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6776 ins_cost(150);
6777 format %{ "MOV$cmp $pcc,$src,$dst" %}
6778 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6779 ins_pipe(ialu_reg);
6780 %}
6781
6782 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6783 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6784 ins_cost(140);
6785 format %{ "MOV$cmp $pcc,$src,$dst" %}
6786 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6787 ins_pipe(ialu_imm);
6788 %}
6789
6790 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6791 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6792 ins_cost(150);
6793 size(4);
6794 format %{ "MOV$cmp $icc,$src,$dst" %}
6795 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6796 ins_pipe(ialu_reg);
6797 %}
6798
6799 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6800 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6801 ins_cost(140);
6802 size(4);
6803 format %{ "MOV$cmp $icc,$src,$dst" %}
6804 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6805 ins_pipe(ialu_imm);
6806 %}
6807
6808 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6809 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6810 ins_cost(150);
6811 size(4);
6812 format %{ "MOV$cmp $icc,$src,$dst" %}
6813 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6814 ins_pipe(ialu_reg);
6815 %}
6816
6817 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6818 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6819 ins_cost(140);
6820 size(4);
6821 format %{ "MOV$cmp $icc,$src,$dst" %}
6822 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6823 ins_pipe(ialu_imm);
6824 %}
6825
6826 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6827 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6828 ins_cost(150);
6829 size(4);
6830 format %{ "MOV$cmp $fcc,$src,$dst" %}
6831 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6832 ins_pipe(ialu_reg);
6833 %}
6834
6835 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6836 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6837 ins_cost(140);
6838 size(4);
6839 format %{ "MOV$cmp $fcc,$src,$dst" %}
6840 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6841 ins_pipe(ialu_imm);
6842 %}
6843
6844 // Conditional move for RegN. Only cmov(reg,reg).
6845 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6846 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6847 ins_cost(150);
6848 format %{ "MOV$cmp $pcc,$src,$dst" %}
6849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6850 ins_pipe(ialu_reg);
6851 %}
6852
6853 // This instruction also works with CmpN so we don't need cmovNN_reg.
6854 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6855 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6856 ins_cost(150);
6857 size(4);
6858 format %{ "MOV$cmp $icc,$src,$dst" %}
6859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6860 ins_pipe(ialu_reg);
6861 %}
6862
6863 // This instruction also works with CmpN so we don't need cmovNN_reg.
6864 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6865 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6866 ins_cost(150);
6867 size(4);
6868 format %{ "MOV$cmp $icc,$src,$dst" %}
6869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6870 ins_pipe(ialu_reg);
6871 %}
6872
6873 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6874 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6875 ins_cost(150);
6876 size(4);
6877 format %{ "MOV$cmp $fcc,$src,$dst" %}
6878 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6879 ins_pipe(ialu_reg);
6880 %}
6881
6882 // Conditional move
6883 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6884 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6885 ins_cost(150);
6886 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6887 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6888 ins_pipe(ialu_reg);
6889 %}
6890
6891 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6892 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6893 ins_cost(140);
6894 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6895 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6896 ins_pipe(ialu_imm);
6897 %}
6898
6899 // This instruction also works with CmpN so we don't need cmovPN_reg.
6900 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6901 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6902 ins_cost(150);
6903
6904 size(4);
6905 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6906 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6907 ins_pipe(ialu_reg);
6908 %}
6909
6910 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6911 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6912 ins_cost(150);
6913
6914 size(4);
6915 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6917 ins_pipe(ialu_reg);
6918 %}
6919
6920 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6921 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6922 ins_cost(140);
6923
6924 size(4);
6925 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6926 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6927 ins_pipe(ialu_imm);
6928 %}
6929
6930 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6931 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6932 ins_cost(140);
6933
6934 size(4);
6935 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6936 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6937 ins_pipe(ialu_imm);
6938 %}
6939
6940 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6941 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6942 ins_cost(150);
6943 size(4);
6944 format %{ "MOV$cmp $fcc,$src,$dst" %}
6945 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6946 ins_pipe(ialu_imm);
6947 %}
6948
6949 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6950 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6951 ins_cost(140);
6952 size(4);
6953 format %{ "MOV$cmp $fcc,$src,$dst" %}
6954 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6955 ins_pipe(ialu_imm);
6956 %}
6957
6958 // Conditional move
6959 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6960 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6961 ins_cost(150);
6962 opcode(0x101);
6963 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6964 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6965 ins_pipe(int_conditional_float_move);
6966 %}
6967
6968 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6969 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6970 ins_cost(150);
6971
6972 size(4);
6973 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6974 opcode(0x101);
6975 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6976 ins_pipe(int_conditional_float_move);
6977 %}
6978
6979 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6980 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6981 ins_cost(150);
6982
6983 size(4);
6984 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6985 opcode(0x101);
6986 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6987 ins_pipe(int_conditional_float_move);
6988 %}
6989
6990 // Conditional move,
6991 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6992 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6993 ins_cost(150);
6994 size(4);
6995 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6996 opcode(0x1);
6997 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6998 ins_pipe(int_conditional_double_move);
6999 %}
7000
7001 // Conditional move
7002 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7003 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7004 ins_cost(150);
7005 size(4);
7006 opcode(0x102);
7007 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7008 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7009 ins_pipe(int_conditional_double_move);
7010 %}
7011
7012 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7013 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7014 ins_cost(150);
7015
7016 size(4);
7017 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7018 opcode(0x102);
7019 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7020 ins_pipe(int_conditional_double_move);
7021 %}
7022
7023 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7024 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7025 ins_cost(150);
7026
7027 size(4);
7028 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7029 opcode(0x102);
7030 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7031 ins_pipe(int_conditional_double_move);
7032 %}
7033
7034 // Conditional move,
7035 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7036 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7037 ins_cost(150);
7038 size(4);
7039 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7040 opcode(0x2);
7041 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7042 ins_pipe(int_conditional_double_move);
7043 %}
7044
7045 // Conditional move
7046 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7047 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7048 ins_cost(150);
7049 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7050 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7051 ins_pipe(ialu_reg);
7052 %}
7053
7054 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7055 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7056 ins_cost(140);
7057 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7058 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7059 ins_pipe(ialu_imm);
7060 %}
7061
7062 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7063 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7064 ins_cost(150);
7065
7066 size(4);
7067 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7068 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7069 ins_pipe(ialu_reg);
7070 %}
7071
7072
7073 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7074 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7075 ins_cost(150);
7076
7077 size(4);
7078 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7079 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7080 ins_pipe(ialu_reg);
7081 %}
7082
7083
7084 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7085 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7086 ins_cost(150);
7087
7088 size(4);
7089 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7090 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7091 ins_pipe(ialu_reg);
7092 %}
7093
7094
7095
7096 //----------OS and Locking Instructions----------------------------------------
7097
7098 // This name is KNOWN by the ADLC and cannot be changed.
7099 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7100 // for this guy.
7101 instruct tlsLoadP(g2RegP dst) %{
7102 match(Set dst (ThreadLocal));
7103
7104 size(0);
7105 ins_cost(0);
7106 format %{ "# TLS is in G2" %}
7107 ins_encode( /*empty encoding*/ );
7108 ins_pipe(ialu_none);
7109 %}
7110
7111 instruct checkCastPP( iRegP dst ) %{
7112 match(Set dst (CheckCastPP dst));
7113
7114 size(0);
7115 format %{ "# checkcastPP of $dst" %}
7116 ins_encode( /*empty encoding*/ );
7117 ins_pipe(empty);
7118 %}
7119
7120
7121 instruct castPP( iRegP dst ) %{
7122 match(Set dst (CastPP dst));
7123 format %{ "# castPP of $dst" %}
7124 ins_encode( /*empty encoding*/ );
7125 ins_pipe(empty);
7126 %}
7127
7128 instruct castII( iRegI dst ) %{
7129 match(Set dst (CastII dst));
7130 format %{ "# castII of $dst" %}
7131 ins_encode( /*empty encoding*/ );
7132 ins_cost(0);
7133 ins_pipe(empty);
7134 %}
7135
7136 //----------Arithmetic Instructions--------------------------------------------
7137 // Addition Instructions
7138 // Register Addition
7139 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7140 match(Set dst (AddI src1 src2));
7141
7142 size(4);
7143 format %{ "ADD $src1,$src2,$dst" %}
7144 ins_encode %{
7145 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7146 %}
7147 ins_pipe(ialu_reg_reg);
7148 %}
7149
7150 // Immediate Addition
7151 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7152 match(Set dst (AddI src1 src2));
7153
7154 size(4);
7155 format %{ "ADD $src1,$src2,$dst" %}
7156 opcode(Assembler::add_op3, Assembler::arith_op);
7157 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7158 ins_pipe(ialu_reg_imm);
7159 %}
7160
7161 // Pointer Register Addition
7162 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7163 match(Set dst (AddP src1 src2));
7164
7165 size(4);
7166 format %{ "ADD $src1,$src2,$dst" %}
7167 opcode(Assembler::add_op3, Assembler::arith_op);
7168 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7169 ins_pipe(ialu_reg_reg);
7170 %}
7171
7172 // Pointer Immediate Addition
7173 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7174 match(Set dst (AddP src1 src2));
7175
7176 size(4);
7177 format %{ "ADD $src1,$src2,$dst" %}
7178 opcode(Assembler::add_op3, Assembler::arith_op);
7179 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7180 ins_pipe(ialu_reg_imm);
7181 %}
7182
7183 // Long Addition
7184 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7185 match(Set dst (AddL src1 src2));
7186
7187 size(4);
7188 format %{ "ADD $src1,$src2,$dst\t! long" %}
7189 opcode(Assembler::add_op3, Assembler::arith_op);
7190 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7191 ins_pipe(ialu_reg_reg);
7192 %}
7193
7194 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7195 match(Set dst (AddL src1 con));
7196
7197 size(4);
7198 format %{ "ADD $src1,$con,$dst" %}
7199 opcode(Assembler::add_op3, Assembler::arith_op);
7200 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7201 ins_pipe(ialu_reg_imm);
7202 %}
7203
7204 //----------Conditional_store--------------------------------------------------
7205 // Conditional-store of the updated heap-top.
7206 // Used during allocation of the shared heap.
7207 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7208
7209 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7210 instruct loadPLocked(iRegP dst, memory mem) %{
7211 match(Set dst (LoadPLocked mem));
7212 ins_cost(MEMORY_REF_COST);
7213
7214 #ifndef _LP64
7215 size(4);
7216 format %{ "LDUW $mem,$dst\t! ptr" %}
7217 opcode(Assembler::lduw_op3, 0, REGP_OP);
7218 #else
7219 format %{ "LDX $mem,$dst\t! ptr" %}
7220 opcode(Assembler::ldx_op3, 0, REGP_OP);
7221 #endif
7222 ins_encode( form3_mem_reg( mem, dst ) );
7223 ins_pipe(iload_mem);
7224 %}
7225
7226 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7227 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7228 effect( KILL newval );
7229 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7230 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7231 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7232 ins_pipe( long_memory_op );
7233 %}
7234
7235 // Conditional-store of an int value.
7236 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7237 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7238 effect( KILL newval );
7239 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7240 "CMP $oldval,$newval\t\t! See if we made progress" %}
7241 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7242 ins_pipe( long_memory_op );
7243 %}
7244
7245 // Conditional-store of a long value.
7246 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7247 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7248 effect( KILL newval );
7249 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7250 "CMP $oldval,$newval\t\t! See if we made progress" %}
7251 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7252 ins_pipe( long_memory_op );
7253 %}
7254
7255 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7256
7257 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7258 predicate(VM_Version::supports_cx8());
7259 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7260 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7261 format %{
7262 "MOV $newval,O7\n\t"
7263 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7264 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7265 "MOV 1,$res\n\t"
7266 "MOVne xcc,R_G0,$res"
7267 %}
7268 ins_encode( enc_casx(mem_ptr, oldval, newval),
7269 enc_lflags_ne_to_boolean(res) );
7270 ins_pipe( long_memory_op );
7271 %}
7272
7273
7274 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7275 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7276 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7277 format %{
7278 "MOV $newval,O7\n\t"
7279 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7280 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7281 "MOV 1,$res\n\t"
7282 "MOVne icc,R_G0,$res"
7283 %}
7284 ins_encode( enc_casi(mem_ptr, oldval, newval),
7285 enc_iflags_ne_to_boolean(res) );
7286 ins_pipe( long_memory_op );
7287 %}
7288
7289 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7290 #ifdef _LP64
7291 predicate(VM_Version::supports_cx8());
7292 #endif
7293 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7294 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7295 format %{
7296 "MOV $newval,O7\n\t"
7297 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7298 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7299 "MOV 1,$res\n\t"
7300 "MOVne xcc,R_G0,$res"
7301 %}
7302 #ifdef _LP64
7303 ins_encode( enc_casx(mem_ptr, oldval, newval),
7304 enc_lflags_ne_to_boolean(res) );
7305 #else
7306 ins_encode( enc_casi(mem_ptr, oldval, newval),
7307 enc_iflags_ne_to_boolean(res) );
7308 #endif
7309 ins_pipe( long_memory_op );
7310 %}
7311
7312 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7313 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7314 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7315 format %{
7316 "MOV $newval,O7\n\t"
7317 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7318 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7319 "MOV 1,$res\n\t"
7320 "MOVne icc,R_G0,$res"
7321 %}
7322 ins_encode( enc_casi(mem_ptr, oldval, newval),
7323 enc_iflags_ne_to_boolean(res) );
7324 ins_pipe( long_memory_op );
7325 %}
7326
7327 instruct xchgI( memory mem, iRegI newval) %{
7328 match(Set newval (GetAndSetI mem newval));
7329 format %{ "SWAP [$mem],$newval" %}
7330 size(4);
7331 ins_encode %{
7332 __ swap($mem$$Address, $newval$$Register);
7333 %}
7334 ins_pipe( long_memory_op );
7335 %}
7336
7337 #ifndef _LP64
7338 instruct xchgP( memory mem, iRegP newval) %{
7339 match(Set newval (GetAndSetP mem newval));
7340 format %{ "SWAP [$mem],$newval" %}
7341 size(4);
7342 ins_encode %{
7343 __ swap($mem$$Address, $newval$$Register);
7344 %}
7345 ins_pipe( long_memory_op );
7346 %}
7347 #endif
7348
7349 instruct xchgN( memory mem, iRegN newval) %{
7350 match(Set newval (GetAndSetN mem newval));
7351 format %{ "SWAP [$mem],$newval" %}
7352 size(4);
7353 ins_encode %{
7354 __ swap($mem$$Address, $newval$$Register);
7355 %}
7356 ins_pipe( long_memory_op );
7357 %}
7358
7359 //---------------------
7360 // Subtraction Instructions
7361 // Register Subtraction
7362 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7363 match(Set dst (SubI src1 src2));
7364
7365 size(4);
7366 format %{ "SUB $src1,$src2,$dst" %}
7367 opcode(Assembler::sub_op3, Assembler::arith_op);
7368 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7369 ins_pipe(ialu_reg_reg);
7370 %}
7371
7372 // Immediate Subtraction
7373 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7374 match(Set dst (SubI src1 src2));
7375
7376 size(4);
7377 format %{ "SUB $src1,$src2,$dst" %}
7378 opcode(Assembler::sub_op3, Assembler::arith_op);
7379 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7380 ins_pipe(ialu_reg_imm);
7381 %}
7382
7383 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7384 match(Set dst (SubI zero src2));
7385
7386 size(4);
7387 format %{ "NEG $src2,$dst" %}
7388 opcode(Assembler::sub_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7390 ins_pipe(ialu_zero_reg);
7391 %}
7392
7393 // Long subtraction
7394 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7395 match(Set dst (SubL src1 src2));
7396
7397 size(4);
7398 format %{ "SUB $src1,$src2,$dst\t! long" %}
7399 opcode(Assembler::sub_op3, Assembler::arith_op);
7400 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7401 ins_pipe(ialu_reg_reg);
7402 %}
7403
7404 // Immediate Subtraction
7405 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7406 match(Set dst (SubL src1 con));
7407
7408 size(4);
7409 format %{ "SUB $src1,$con,$dst\t! long" %}
7410 opcode(Assembler::sub_op3, Assembler::arith_op);
7411 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7412 ins_pipe(ialu_reg_imm);
7413 %}
7414
7415 // Long negation
7416 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7417 match(Set dst (SubL zero src2));
7418
7419 size(4);
7420 format %{ "NEG $src2,$dst\t! long" %}
7421 opcode(Assembler::sub_op3, Assembler::arith_op);
7422 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7423 ins_pipe(ialu_zero_reg);
7424 %}
7425
7426 // Multiplication Instructions
7427 // Integer Multiplication
7428 // Register Multiplication
7429 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7430 match(Set dst (MulI src1 src2));
7431
7432 size(4);
7433 format %{ "MULX $src1,$src2,$dst" %}
7434 opcode(Assembler::mulx_op3, Assembler::arith_op);
7435 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7436 ins_pipe(imul_reg_reg);
7437 %}
7438
7439 // Immediate Multiplication
7440 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7441 match(Set dst (MulI src1 src2));
7442
7443 size(4);
7444 format %{ "MULX $src1,$src2,$dst" %}
7445 opcode(Assembler::mulx_op3, Assembler::arith_op);
7446 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7447 ins_pipe(imul_reg_imm);
7448 %}
7449
7450 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7451 match(Set dst (MulL src1 src2));
7452 ins_cost(DEFAULT_COST * 5);
7453 size(4);
7454 format %{ "MULX $src1,$src2,$dst\t! long" %}
7455 opcode(Assembler::mulx_op3, Assembler::arith_op);
7456 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7457 ins_pipe(mulL_reg_reg);
7458 %}
7459
7460 // Immediate Multiplication
7461 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7462 match(Set dst (MulL src1 src2));
7463 ins_cost(DEFAULT_COST * 5);
7464 size(4);
7465 format %{ "MULX $src1,$src2,$dst" %}
7466 opcode(Assembler::mulx_op3, Assembler::arith_op);
7467 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7468 ins_pipe(mulL_reg_imm);
7469 %}
7470
7471 // Integer Division
7472 // Register Division
7473 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7474 match(Set dst (DivI src1 src2));
7475 ins_cost((2+71)*DEFAULT_COST);
7476
7477 format %{ "SRA $src2,0,$src2\n\t"
7478 "SRA $src1,0,$src1\n\t"
7479 "SDIVX $src1,$src2,$dst" %}
7480 ins_encode( idiv_reg( src1, src2, dst ) );
7481 ins_pipe(sdiv_reg_reg);
7482 %}
7483
7484 // Immediate Division
7485 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7486 match(Set dst (DivI src1 src2));
7487 ins_cost((2+71)*DEFAULT_COST);
7488
7489 format %{ "SRA $src1,0,$src1\n\t"
7490 "SDIVX $src1,$src2,$dst" %}
7491 ins_encode( idiv_imm( src1, src2, dst ) );
7492 ins_pipe(sdiv_reg_imm);
7493 %}
7494
7495 //----------Div-By-10-Expansion------------------------------------------------
7496 // Extract hi bits of a 32x32->64 bit multiply.
7497 // Expand rule only, not matched
7498 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7499 effect( DEF dst, USE src1, USE src2 );
7500 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7501 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7502 ins_encode( enc_mul_hi(dst,src1,src2));
7503 ins_pipe(sdiv_reg_reg);
7504 %}
7505
7506 // Magic constant, reciprocal of 10
7507 instruct loadConI_x66666667(iRegIsafe dst) %{
7508 effect( DEF dst );
7509
7510 size(8);
7511 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7512 ins_encode( Set32(0x66666667, dst) );
7513 ins_pipe(ialu_hi_lo_reg);
7514 %}
7515
7516 // Register Shift Right Arithmetic Long by 32-63
7517 instruct sra_31( iRegI dst, iRegI src ) %{
7518 effect( DEF dst, USE src );
7519 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7520 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7521 ins_pipe(ialu_reg_reg);
7522 %}
7523
7524 // Arithmetic Shift Right by 8-bit immediate
7525 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7526 effect( DEF dst, USE src );
7527 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7528 opcode(Assembler::sra_op3, Assembler::arith_op);
7529 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7530 ins_pipe(ialu_reg_imm);
7531 %}
7532
7533 // Integer DIV with 10
7534 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7535 match(Set dst (DivI src div));
7536 ins_cost((6+6)*DEFAULT_COST);
7537 expand %{
7538 iRegIsafe tmp1; // Killed temps;
7539 iRegIsafe tmp2; // Killed temps;
7540 iRegI tmp3; // Killed temps;
7541 iRegI tmp4; // Killed temps;
7542 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7543 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7544 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7545 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7546 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7547 %}
7548 %}
7549
7550 // Register Long Division
7551 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7552 match(Set dst (DivL src1 src2));
7553 ins_cost(DEFAULT_COST*71);
7554 size(4);
7555 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7556 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7557 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7558 ins_pipe(divL_reg_reg);
7559 %}
7560
7561 // Register Long Division
7562 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7563 match(Set dst (DivL src1 src2));
7564 ins_cost(DEFAULT_COST*71);
7565 size(4);
7566 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7567 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7568 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7569 ins_pipe(divL_reg_imm);
7570 %}
7571
7572 // Integer Remainder
7573 // Register Remainder
7574 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7575 match(Set dst (ModI src1 src2));
7576 effect( KILL ccr, KILL temp);
7577
7578 format %{ "SREM $src1,$src2,$dst" %}
7579 ins_encode( irem_reg(src1, src2, dst, temp) );
7580 ins_pipe(sdiv_reg_reg);
7581 %}
7582
7583 // Immediate Remainder
7584 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7585 match(Set dst (ModI src1 src2));
7586 effect( KILL ccr, KILL temp);
7587
7588 format %{ "SREM $src1,$src2,$dst" %}
7589 ins_encode( irem_imm(src1, src2, dst, temp) );
7590 ins_pipe(sdiv_reg_imm);
7591 %}
7592
7593 // Register Long Remainder
7594 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7595 effect(DEF dst, USE src1, USE src2);
7596 size(4);
7597 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7598 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7599 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7600 ins_pipe(divL_reg_reg);
7601 %}
7602
7603 // Register Long Division
7604 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7605 effect(DEF dst, USE src1, USE src2);
7606 size(4);
7607 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7608 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7609 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7610 ins_pipe(divL_reg_imm);
7611 %}
7612
7613 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7614 effect(DEF dst, USE src1, USE src2);
7615 size(4);
7616 format %{ "MULX $src1,$src2,$dst\t! long" %}
7617 opcode(Assembler::mulx_op3, Assembler::arith_op);
7618 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7619 ins_pipe(mulL_reg_reg);
7620 %}
7621
7622 // Immediate Multiplication
7623 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7624 effect(DEF dst, USE src1, USE src2);
7625 size(4);
7626 format %{ "MULX $src1,$src2,$dst" %}
7627 opcode(Assembler::mulx_op3, Assembler::arith_op);
7628 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7629 ins_pipe(mulL_reg_imm);
7630 %}
7631
7632 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7633 effect(DEF dst, USE src1, USE src2);
7634 size(4);
7635 format %{ "SUB $src1,$src2,$dst\t! long" %}
7636 opcode(Assembler::sub_op3, Assembler::arith_op);
7637 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7638 ins_pipe(ialu_reg_reg);
7639 %}
7640
7641 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7642 effect(DEF dst, USE src1, USE src2);
7643 size(4);
7644 format %{ "SUB $src1,$src2,$dst\t! long" %}
7645 opcode(Assembler::sub_op3, Assembler::arith_op);
7646 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7647 ins_pipe(ialu_reg_reg);
7648 %}
7649
7650 // Register Long Remainder
7651 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7652 match(Set dst (ModL src1 src2));
7653 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7654 expand %{
7655 iRegL tmp1;
7656 iRegL tmp2;
7657 divL_reg_reg_1(tmp1, src1, src2);
7658 mulL_reg_reg_1(tmp2, tmp1, src2);
7659 subL_reg_reg_1(dst, src1, tmp2);
7660 %}
7661 %}
7662
7663 // Register Long Remainder
7664 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7665 match(Set dst (ModL src1 src2));
7666 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7667 expand %{
7668 iRegL tmp1;
7669 iRegL tmp2;
7670 divL_reg_imm13_1(tmp1, src1, src2);
7671 mulL_reg_imm13_1(tmp2, tmp1, src2);
7672 subL_reg_reg_2 (dst, src1, tmp2);
7673 %}
7674 %}
7675
7676 // Integer Shift Instructions
7677 // Register Shift Left
7678 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7679 match(Set dst (LShiftI src1 src2));
7680
7681 size(4);
7682 format %{ "SLL $src1,$src2,$dst" %}
7683 opcode(Assembler::sll_op3, Assembler::arith_op);
7684 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7685 ins_pipe(ialu_reg_reg);
7686 %}
7687
7688 // Register Shift Left Immediate
7689 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7690 match(Set dst (LShiftI src1 src2));
7691
7692 size(4);
7693 format %{ "SLL $src1,$src2,$dst" %}
7694 opcode(Assembler::sll_op3, Assembler::arith_op);
7695 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7696 ins_pipe(ialu_reg_imm);
7697 %}
7698
7699 // Register Shift Left
7700 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7701 match(Set dst (LShiftL src1 src2));
7702
7703 size(4);
7704 format %{ "SLLX $src1,$src2,$dst" %}
7705 opcode(Assembler::sllx_op3, Assembler::arith_op);
7706 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7707 ins_pipe(ialu_reg_reg);
7708 %}
7709
7710 // Register Shift Left Immediate
7711 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7712 match(Set dst (LShiftL src1 src2));
7713
7714 size(4);
7715 format %{ "SLLX $src1,$src2,$dst" %}
7716 opcode(Assembler::sllx_op3, Assembler::arith_op);
7717 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7718 ins_pipe(ialu_reg_imm);
7719 %}
7720
7721 // Register Arithmetic Shift Right
7722 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7723 match(Set dst (RShiftI src1 src2));
7724 size(4);
7725 format %{ "SRA $src1,$src2,$dst" %}
7726 opcode(Assembler::sra_op3, Assembler::arith_op);
7727 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7728 ins_pipe(ialu_reg_reg);
7729 %}
7730
7731 // Register Arithmetic Shift Right Immediate
7732 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7733 match(Set dst (RShiftI src1 src2));
7734
7735 size(4);
7736 format %{ "SRA $src1,$src2,$dst" %}
7737 opcode(Assembler::sra_op3, Assembler::arith_op);
7738 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7739 ins_pipe(ialu_reg_imm);
7740 %}
7741
7742 // Register Shift Right Arithmatic Long
7743 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7744 match(Set dst (RShiftL src1 src2));
7745
7746 size(4);
7747 format %{ "SRAX $src1,$src2,$dst" %}
7748 opcode(Assembler::srax_op3, Assembler::arith_op);
7749 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7750 ins_pipe(ialu_reg_reg);
7751 %}
7752
7753 // Register Shift Left Immediate
7754 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7755 match(Set dst (RShiftL src1 src2));
7756
7757 size(4);
7758 format %{ "SRAX $src1,$src2,$dst" %}
7759 opcode(Assembler::srax_op3, Assembler::arith_op);
7760 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7761 ins_pipe(ialu_reg_imm);
7762 %}
7763
7764 // Register Shift Right
7765 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7766 match(Set dst (URShiftI src1 src2));
7767
7768 size(4);
7769 format %{ "SRL $src1,$src2,$dst" %}
7770 opcode(Assembler::srl_op3, Assembler::arith_op);
7771 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7772 ins_pipe(ialu_reg_reg);
7773 %}
7774
7775 // Register Shift Right Immediate
7776 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7777 match(Set dst (URShiftI src1 src2));
7778
7779 size(4);
7780 format %{ "SRL $src1,$src2,$dst" %}
7781 opcode(Assembler::srl_op3, Assembler::arith_op);
7782 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7783 ins_pipe(ialu_reg_imm);
7784 %}
7785
7786 // Register Shift Right
7787 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7788 match(Set dst (URShiftL src1 src2));
7789
7790 size(4);
7791 format %{ "SRLX $src1,$src2,$dst" %}
7792 opcode(Assembler::srlx_op3, Assembler::arith_op);
7793 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7794 ins_pipe(ialu_reg_reg);
7795 %}
7796
7797 // Register Shift Right Immediate
7798 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7799 match(Set dst (URShiftL src1 src2));
7800
7801 size(4);
7802 format %{ "SRLX $src1,$src2,$dst" %}
7803 opcode(Assembler::srlx_op3, Assembler::arith_op);
7804 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7805 ins_pipe(ialu_reg_imm);
7806 %}
7807
7808 // Register Shift Right Immediate with a CastP2X
7809 #ifdef _LP64
7810 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7811 match(Set dst (URShiftL (CastP2X src1) src2));
7812 size(4);
7813 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7814 opcode(Assembler::srlx_op3, Assembler::arith_op);
7815 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7816 ins_pipe(ialu_reg_imm);
7817 %}
7818 #else
7819 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7820 match(Set dst (URShiftI (CastP2X src1) src2));
7821 size(4);
7822 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7823 opcode(Assembler::srl_op3, Assembler::arith_op);
7824 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7825 ins_pipe(ialu_reg_imm);
7826 %}
7827 #endif
7828
7829
7830 //----------Floating Point Arithmetic Instructions-----------------------------
7831
7832 // Add float single precision
7833 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7834 match(Set dst (AddF src1 src2));
7835
7836 size(4);
7837 format %{ "FADDS $src1,$src2,$dst" %}
7838 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7839 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7840 ins_pipe(faddF_reg_reg);
7841 %}
7842
7843 // Add float double precision
7844 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7845 match(Set dst (AddD src1 src2));
7846
7847 size(4);
7848 format %{ "FADDD $src1,$src2,$dst" %}
7849 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7850 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7851 ins_pipe(faddD_reg_reg);
7852 %}
7853
7854 // Sub float single precision
7855 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7856 match(Set dst (SubF src1 src2));
7857
7858 size(4);
7859 format %{ "FSUBS $src1,$src2,$dst" %}
7860 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7861 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7862 ins_pipe(faddF_reg_reg);
7863 %}
7864
7865 // Sub float double precision
7866 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7867 match(Set dst (SubD src1 src2));
7868
7869 size(4);
7870 format %{ "FSUBD $src1,$src2,$dst" %}
7871 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7872 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7873 ins_pipe(faddD_reg_reg);
7874 %}
7875
7876 // Mul float single precision
7877 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7878 match(Set dst (MulF src1 src2));
7879
7880 size(4);
7881 format %{ "FMULS $src1,$src2,$dst" %}
7882 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7883 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7884 ins_pipe(fmulF_reg_reg);
7885 %}
7886
7887 // Mul float double precision
7888 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7889 match(Set dst (MulD src1 src2));
7890
7891 size(4);
7892 format %{ "FMULD $src1,$src2,$dst" %}
7893 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7894 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7895 ins_pipe(fmulD_reg_reg);
7896 %}
7897
7898 // Div float single precision
7899 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7900 match(Set dst (DivF src1 src2));
7901
7902 size(4);
7903 format %{ "FDIVS $src1,$src2,$dst" %}
7904 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7905 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7906 ins_pipe(fdivF_reg_reg);
7907 %}
7908
7909 // Div float double precision
7910 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7911 match(Set dst (DivD src1 src2));
7912
7913 size(4);
7914 format %{ "FDIVD $src1,$src2,$dst" %}
7915 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7916 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7917 ins_pipe(fdivD_reg_reg);
7918 %}
7919
7920 // Absolute float double precision
7921 instruct absD_reg(regD dst, regD src) %{
7922 match(Set dst (AbsD src));
7923
7924 format %{ "FABSd $src,$dst" %}
7925 ins_encode(fabsd(dst, src));
7926 ins_pipe(faddD_reg);
7927 %}
7928
7929 // Absolute float single precision
7930 instruct absF_reg(regF dst, regF src) %{
7931 match(Set dst (AbsF src));
7932
7933 format %{ "FABSs $src,$dst" %}
7934 ins_encode(fabss(dst, src));
7935 ins_pipe(faddF_reg);
7936 %}
7937
7938 instruct negF_reg(regF dst, regF src) %{
7939 match(Set dst (NegF src));
7940
7941 size(4);
7942 format %{ "FNEGs $src,$dst" %}
7943 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7944 ins_encode(form3_opf_rs2F_rdF(src, dst));
7945 ins_pipe(faddF_reg);
7946 %}
7947
7948 instruct negD_reg(regD dst, regD src) %{
7949 match(Set dst (NegD src));
7950
7951 format %{ "FNEGd $src,$dst" %}
7952 ins_encode(fnegd(dst, src));
7953 ins_pipe(faddD_reg);
7954 %}
7955
7956 // Sqrt float double precision
7957 instruct sqrtF_reg_reg(regF dst, regF src) %{
7958 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7959
7960 size(4);
7961 format %{ "FSQRTS $src,$dst" %}
7962 ins_encode(fsqrts(dst, src));
7963 ins_pipe(fdivF_reg_reg);
7964 %}
7965
7966 // Sqrt float double precision
7967 instruct sqrtD_reg_reg(regD dst, regD src) %{
7968 match(Set dst (SqrtD src));
7969
7970 size(4);
7971 format %{ "FSQRTD $src,$dst" %}
7972 ins_encode(fsqrtd(dst, src));
7973 ins_pipe(fdivD_reg_reg);
7974 %}
7975
7976 //----------Logical Instructions-----------------------------------------------
7977 // And Instructions
7978 // Register And
7979 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7980 match(Set dst (AndI src1 src2));
7981
7982 size(4);
7983 format %{ "AND $src1,$src2,$dst" %}
7984 opcode(Assembler::and_op3, Assembler::arith_op);
7985 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7986 ins_pipe(ialu_reg_reg);
7987 %}
7988
7989 // Immediate And
7990 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7991 match(Set dst (AndI src1 src2));
7992
7993 size(4);
7994 format %{ "AND $src1,$src2,$dst" %}
7995 opcode(Assembler::and_op3, Assembler::arith_op);
7996 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7997 ins_pipe(ialu_reg_imm);
7998 %}
7999
8000 // Register And Long
8001 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8002 match(Set dst (AndL src1 src2));
8003
8004 ins_cost(DEFAULT_COST);
8005 size(4);
8006 format %{ "AND $src1,$src2,$dst\t! long" %}
8007 opcode(Assembler::and_op3, Assembler::arith_op);
8008 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8009 ins_pipe(ialu_reg_reg);
8010 %}
8011
8012 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8013 match(Set dst (AndL src1 con));
8014
8015 ins_cost(DEFAULT_COST);
8016 size(4);
8017 format %{ "AND $src1,$con,$dst\t! long" %}
8018 opcode(Assembler::and_op3, Assembler::arith_op);
8019 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8020 ins_pipe(ialu_reg_imm);
8021 %}
8022
8023 // Or Instructions
8024 // Register Or
8025 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8026 match(Set dst (OrI src1 src2));
8027
8028 size(4);
8029 format %{ "OR $src1,$src2,$dst" %}
8030 opcode(Assembler::or_op3, Assembler::arith_op);
8031 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8032 ins_pipe(ialu_reg_reg);
8033 %}
8034
8035 // Immediate Or
8036 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8037 match(Set dst (OrI src1 src2));
8038
8039 size(4);
8040 format %{ "OR $src1,$src2,$dst" %}
8041 opcode(Assembler::or_op3, Assembler::arith_op);
8042 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8043 ins_pipe(ialu_reg_imm);
8044 %}
8045
8046 // Register Or Long
8047 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8048 match(Set dst (OrL src1 src2));
8049
8050 ins_cost(DEFAULT_COST);
8051 size(4);
8052 format %{ "OR $src1,$src2,$dst\t! long" %}
8053 opcode(Assembler::or_op3, Assembler::arith_op);
8054 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8055 ins_pipe(ialu_reg_reg);
8056 %}
8057
8058 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8059 match(Set dst (OrL src1 con));
8060 ins_cost(DEFAULT_COST*2);
8061
8062 ins_cost(DEFAULT_COST);
8063 size(4);
8064 format %{ "OR $src1,$con,$dst\t! long" %}
8065 opcode(Assembler::or_op3, Assembler::arith_op);
8066 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8067 ins_pipe(ialu_reg_imm);
8068 %}
8069
8070 #ifndef _LP64
8071
8072 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8073 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8074 match(Set dst (OrI src1 (CastP2X src2)));
8075
8076 size(4);
8077 format %{ "OR $src1,$src2,$dst" %}
8078 opcode(Assembler::or_op3, Assembler::arith_op);
8079 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8080 ins_pipe(ialu_reg_reg);
8081 %}
8082
8083 #else
8084
8085 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8086 match(Set dst (OrL src1 (CastP2X src2)));
8087
8088 ins_cost(DEFAULT_COST);
8089 size(4);
8090 format %{ "OR $src1,$src2,$dst\t! long" %}
8091 opcode(Assembler::or_op3, Assembler::arith_op);
8092 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8093 ins_pipe(ialu_reg_reg);
8094 %}
8095
8096 #endif
8097
8098 // Xor Instructions
8099 // Register Xor
8100 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8101 match(Set dst (XorI src1 src2));
8102
8103 size(4);
8104 format %{ "XOR $src1,$src2,$dst" %}
8105 opcode(Assembler::xor_op3, Assembler::arith_op);
8106 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8107 ins_pipe(ialu_reg_reg);
8108 %}
8109
8110 // Immediate Xor
8111 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8112 match(Set dst (XorI src1 src2));
8113
8114 size(4);
8115 format %{ "XOR $src1,$src2,$dst" %}
8116 opcode(Assembler::xor_op3, Assembler::arith_op);
8117 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8118 ins_pipe(ialu_reg_imm);
8119 %}
8120
8121 // Register Xor Long
8122 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8123 match(Set dst (XorL src1 src2));
8124
8125 ins_cost(DEFAULT_COST);
8126 size(4);
8127 format %{ "XOR $src1,$src2,$dst\t! long" %}
8128 opcode(Assembler::xor_op3, Assembler::arith_op);
8129 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8134 match(Set dst (XorL src1 con));
8135
8136 ins_cost(DEFAULT_COST);
8137 size(4);
8138 format %{ "XOR $src1,$con,$dst\t! long" %}
8139 opcode(Assembler::xor_op3, Assembler::arith_op);
8140 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8141 ins_pipe(ialu_reg_imm);
8142 %}
8143
8144 //----------Convert to Boolean-------------------------------------------------
8145 // Nice hack for 32-bit tests but doesn't work for
8146 // 64-bit pointers.
8147 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8148 match(Set dst (Conv2B src));
8149 effect( KILL ccr );
8150 ins_cost(DEFAULT_COST*2);
8151 format %{ "CMP R_G0,$src\n\t"
8152 "ADDX R_G0,0,$dst" %}
8153 ins_encode( enc_to_bool( src, dst ) );
8154 ins_pipe(ialu_reg_ialu);
8155 %}
8156
8157 #ifndef _LP64
8158 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8159 match(Set dst (Conv2B src));
8160 effect( KILL ccr );
8161 ins_cost(DEFAULT_COST*2);
8162 format %{ "CMP R_G0,$src\n\t"
8163 "ADDX R_G0,0,$dst" %}
8164 ins_encode( enc_to_bool( src, dst ) );
8165 ins_pipe(ialu_reg_ialu);
8166 %}
8167 #else
8168 instruct convP2B( iRegI dst, iRegP src ) %{
8169 match(Set dst (Conv2B src));
8170 ins_cost(DEFAULT_COST*2);
8171 format %{ "MOV $src,$dst\n\t"
8172 "MOVRNZ $src,1,$dst" %}
8173 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8174 ins_pipe(ialu_clr_and_mover);
8175 %}
8176 #endif
8177
8178 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8179 match(Set dst (CmpLTMask src zero));
8180 effect(KILL ccr);
8181 size(4);
8182 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8183 ins_encode %{
8184 __ sra($src$$Register, 31, $dst$$Register);
8185 %}
8186 ins_pipe(ialu_reg_imm);
8187 %}
8188
8189 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8190 match(Set dst (CmpLTMask p q));
8191 effect( KILL ccr );
8192 ins_cost(DEFAULT_COST*4);
8193 format %{ "CMP $p,$q\n\t"
8194 "MOV #0,$dst\n\t"
8195 "BLT,a .+8\n\t"
8196 "MOV #-1,$dst" %}
8197 ins_encode( enc_ltmask(p,q,dst) );
8198 ins_pipe(ialu_reg_reg_ialu);
8199 %}
8200
8201 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8202 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8203 effect(KILL ccr, TEMP tmp);
8204 ins_cost(DEFAULT_COST*3);
8205
8206 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8207 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8208 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8209 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8210 ins_pipe(cadd_cmpltmask);
8211 %}
8212
8213 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8214 match(Set p (AndI (CmpLTMask p q) y));
8215 effect(KILL ccr);
8216 ins_cost(DEFAULT_COST*3);
8217
8218 format %{ "CMP $p,$q\n\t"
8219 "MOV $y,$p\n\t"
8220 "MOVge G0,$p" %}
8221 ins_encode %{
8222 __ cmp($p$$Register, $q$$Register);
8223 __ mov($y$$Register, $p$$Register);
8224 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8225 %}
8226 ins_pipe(ialu_reg_reg_ialu);
8227 %}
8228
8229 //-----------------------------------------------------------------
8230 // Direct raw moves between float and general registers using VIS3.
8231
8232 // ins_pipe(faddF_reg);
8233 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8234 predicate(UseVIS >= 3);
8235 match(Set dst (MoveF2I src));
8236
8237 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8238 ins_encode %{
8239 __ movstouw($src$$FloatRegister, $dst$$Register);
8240 %}
8241 ins_pipe(ialu_reg_reg);
8242 %}
8243
8244 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8245 predicate(UseVIS >= 3);
8246 match(Set dst (MoveI2F src));
8247
8248 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8249 ins_encode %{
8250 __ movwtos($src$$Register, $dst$$FloatRegister);
8251 %}
8252 ins_pipe(ialu_reg_reg);
8253 %}
8254
8255 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8256 predicate(UseVIS >= 3);
8257 match(Set dst (MoveD2L src));
8258
8259 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8260 ins_encode %{
8261 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8262 %}
8263 ins_pipe(ialu_reg_reg);
8264 %}
8265
8266 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8267 predicate(UseVIS >= 3);
8268 match(Set dst (MoveL2D src));
8269
8270 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8271 ins_encode %{
8272 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8273 %}
8274 ins_pipe(ialu_reg_reg);
8275 %}
8276
8277
8278 // Raw moves between float and general registers using stack.
8279
8280 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8281 match(Set dst (MoveF2I src));
8282 effect(DEF dst, USE src);
8283 ins_cost(MEMORY_REF_COST);
8284
8285 size(4);
8286 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8287 opcode(Assembler::lduw_op3);
8288 ins_encode(simple_form3_mem_reg( src, dst ) );
8289 ins_pipe(iload_mem);
8290 %}
8291
8292 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8293 match(Set dst (MoveI2F src));
8294 effect(DEF dst, USE src);
8295 ins_cost(MEMORY_REF_COST);
8296
8297 size(4);
8298 format %{ "LDF $src,$dst\t! MoveI2F" %}
8299 opcode(Assembler::ldf_op3);
8300 ins_encode(simple_form3_mem_reg(src, dst));
8301 ins_pipe(floadF_stk);
8302 %}
8303
8304 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8305 match(Set dst (MoveD2L src));
8306 effect(DEF dst, USE src);
8307 ins_cost(MEMORY_REF_COST);
8308
8309 size(4);
8310 format %{ "LDX $src,$dst\t! MoveD2L" %}
8311 opcode(Assembler::ldx_op3);
8312 ins_encode(simple_form3_mem_reg( src, dst ) );
8313 ins_pipe(iload_mem);
8314 %}
8315
8316 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8317 match(Set dst (MoveL2D src));
8318 effect(DEF dst, USE src);
8319 ins_cost(MEMORY_REF_COST);
8320
8321 size(4);
8322 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8323 opcode(Assembler::lddf_op3);
8324 ins_encode(simple_form3_mem_reg(src, dst));
8325 ins_pipe(floadD_stk);
8326 %}
8327
8328 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8329 match(Set dst (MoveF2I src));
8330 effect(DEF dst, USE src);
8331 ins_cost(MEMORY_REF_COST);
8332
8333 size(4);
8334 format %{ "STF $src,$dst\t! MoveF2I" %}
8335 opcode(Assembler::stf_op3);
8336 ins_encode(simple_form3_mem_reg(dst, src));
8337 ins_pipe(fstoreF_stk_reg);
8338 %}
8339
8340 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8341 match(Set dst (MoveI2F src));
8342 effect(DEF dst, USE src);
8343 ins_cost(MEMORY_REF_COST);
8344
8345 size(4);
8346 format %{ "STW $src,$dst\t! MoveI2F" %}
8347 opcode(Assembler::stw_op3);
8348 ins_encode(simple_form3_mem_reg( dst, src ) );
8349 ins_pipe(istore_mem_reg);
8350 %}
8351
8352 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8353 match(Set dst (MoveD2L src));
8354 effect(DEF dst, USE src);
8355 ins_cost(MEMORY_REF_COST);
8356
8357 size(4);
8358 format %{ "STDF $src,$dst\t! MoveD2L" %}
8359 opcode(Assembler::stdf_op3);
8360 ins_encode(simple_form3_mem_reg(dst, src));
8361 ins_pipe(fstoreD_stk_reg);
8362 %}
8363
8364 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8365 match(Set dst (MoveL2D src));
8366 effect(DEF dst, USE src);
8367 ins_cost(MEMORY_REF_COST);
8368
8369 size(4);
8370 format %{ "STX $src,$dst\t! MoveL2D" %}
8371 opcode(Assembler::stx_op3);
8372 ins_encode(simple_form3_mem_reg( dst, src ) );
8373 ins_pipe(istore_mem_reg);
8374 %}
8375
8376
8377 //----------Arithmetic Conversion Instructions---------------------------------
8378 // The conversions operations are all Alpha sorted. Please keep it that way!
8379
8380 instruct convD2F_reg(regF dst, regD src) %{
8381 match(Set dst (ConvD2F src));
8382 size(4);
8383 format %{ "FDTOS $src,$dst" %}
8384 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8385 ins_encode(form3_opf_rs2D_rdF(src, dst));
8386 ins_pipe(fcvtD2F);
8387 %}
8388
8389
8390 // Convert a double to an int in a float register.
8391 // If the double is a NAN, stuff a zero in instead.
8392 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8393 effect(DEF dst, USE src, KILL fcc0);
8394 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8395 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8396 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8397 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8398 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8399 "skip:" %}
8400 ins_encode(form_d2i_helper(src,dst));
8401 ins_pipe(fcvtD2I);
8402 %}
8403
8404 instruct convD2I_stk(stackSlotI dst, regD src) %{
8405 match(Set dst (ConvD2I src));
8406 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8407 expand %{
8408 regF tmp;
8409 convD2I_helper(tmp, src);
8410 regF_to_stkI(dst, tmp);
8411 %}
8412 %}
8413
8414 instruct convD2I_reg(iRegI dst, regD src) %{
8415 predicate(UseVIS >= 3);
8416 match(Set dst (ConvD2I src));
8417 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8418 expand %{
8419 regF tmp;
8420 convD2I_helper(tmp, src);
8421 MoveF2I_reg_reg(dst, tmp);
8422 %}
8423 %}
8424
8425
8426 // Convert a double to a long in a double register.
8427 // If the double is a NAN, stuff a zero in instead.
8428 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8429 effect(DEF dst, USE src, KILL fcc0);
8430 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8431 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8432 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8433 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8434 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8435 "skip:" %}
8436 ins_encode(form_d2l_helper(src,dst));
8437 ins_pipe(fcvtD2L);
8438 %}
8439
8440 instruct convD2L_stk(stackSlotL dst, regD src) %{
8441 match(Set dst (ConvD2L src));
8442 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8443 expand %{
8444 regD tmp;
8445 convD2L_helper(tmp, src);
8446 regD_to_stkL(dst, tmp);
8447 %}
8448 %}
8449
8450 instruct convD2L_reg(iRegL dst, regD src) %{
8451 predicate(UseVIS >= 3);
8452 match(Set dst (ConvD2L src));
8453 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8454 expand %{
8455 regD tmp;
8456 convD2L_helper(tmp, src);
8457 MoveD2L_reg_reg(dst, tmp);
8458 %}
8459 %}
8460
8461
8462 instruct convF2D_reg(regD dst, regF src) %{
8463 match(Set dst (ConvF2D src));
8464 format %{ "FSTOD $src,$dst" %}
8465 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8466 ins_encode(form3_opf_rs2F_rdD(src, dst));
8467 ins_pipe(fcvtF2D);
8468 %}
8469
8470
8471 // Convert a float to an int in a float register.
8472 // If the float is a NAN, stuff a zero in instead.
8473 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8474 effect(DEF dst, USE src, KILL fcc0);
8475 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8476 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8477 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8478 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8479 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8480 "skip:" %}
8481 ins_encode(form_f2i_helper(src,dst));
8482 ins_pipe(fcvtF2I);
8483 %}
8484
8485 instruct convF2I_stk(stackSlotI dst, regF src) %{
8486 match(Set dst (ConvF2I src));
8487 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8488 expand %{
8489 regF tmp;
8490 convF2I_helper(tmp, src);
8491 regF_to_stkI(dst, tmp);
8492 %}
8493 %}
8494
8495 instruct convF2I_reg(iRegI dst, regF src) %{
8496 predicate(UseVIS >= 3);
8497 match(Set dst (ConvF2I src));
8498 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8499 expand %{
8500 regF tmp;
8501 convF2I_helper(tmp, src);
8502 MoveF2I_reg_reg(dst, tmp);
8503 %}
8504 %}
8505
8506
8507 // Convert a float to a long in a float register.
8508 // If the float is a NAN, stuff a zero in instead.
8509 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8510 effect(DEF dst, USE src, KILL fcc0);
8511 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8512 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8513 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8514 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8515 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8516 "skip:" %}
8517 ins_encode(form_f2l_helper(src,dst));
8518 ins_pipe(fcvtF2L);
8519 %}
8520
8521 instruct convF2L_stk(stackSlotL dst, regF src) %{
8522 match(Set dst (ConvF2L src));
8523 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8524 expand %{
8525 regD tmp;
8526 convF2L_helper(tmp, src);
8527 regD_to_stkL(dst, tmp);
8528 %}
8529 %}
8530
8531 instruct convF2L_reg(iRegL dst, regF src) %{
8532 predicate(UseVIS >= 3);
8533 match(Set dst (ConvF2L src));
8534 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8535 expand %{
8536 regD tmp;
8537 convF2L_helper(tmp, src);
8538 MoveD2L_reg_reg(dst, tmp);
8539 %}
8540 %}
8541
8542
8543 instruct convI2D_helper(regD dst, regF tmp) %{
8544 effect(USE tmp, DEF dst);
8545 format %{ "FITOD $tmp,$dst" %}
8546 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8547 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8548 ins_pipe(fcvtI2D);
8549 %}
8550
8551 instruct convI2D_stk(stackSlotI src, regD dst) %{
8552 match(Set dst (ConvI2D src));
8553 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8554 expand %{
8555 regF tmp;
8556 stkI_to_regF(tmp, src);
8557 convI2D_helper(dst, tmp);
8558 %}
8559 %}
8560
8561 instruct convI2D_reg(regD_low dst, iRegI src) %{
8562 predicate(UseVIS >= 3);
8563 match(Set dst (ConvI2D src));
8564 expand %{
8565 regF tmp;
8566 MoveI2F_reg_reg(tmp, src);
8567 convI2D_helper(dst, tmp);
8568 %}
8569 %}
8570
8571 instruct convI2D_mem(regD_low dst, memory mem) %{
8572 match(Set dst (ConvI2D (LoadI mem)));
8573 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8574 size(8);
8575 format %{ "LDF $mem,$dst\n\t"
8576 "FITOD $dst,$dst" %}
8577 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8578 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8579 ins_pipe(floadF_mem);
8580 %}
8581
8582
8583 instruct convI2F_helper(regF dst, regF tmp) %{
8584 effect(DEF dst, USE tmp);
8585 format %{ "FITOS $tmp,$dst" %}
8586 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8587 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8588 ins_pipe(fcvtI2F);
8589 %}
8590
8591 instruct convI2F_stk(regF dst, stackSlotI src) %{
8592 match(Set dst (ConvI2F src));
8593 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8594 expand %{
8595 regF tmp;
8596 stkI_to_regF(tmp,src);
8597 convI2F_helper(dst, tmp);
8598 %}
8599 %}
8600
8601 instruct convI2F_reg(regF dst, iRegI src) %{
8602 predicate(UseVIS >= 3);
8603 match(Set dst (ConvI2F src));
8604 ins_cost(DEFAULT_COST);
8605 expand %{
8606 regF tmp;
8607 MoveI2F_reg_reg(tmp, src);
8608 convI2F_helper(dst, tmp);
8609 %}
8610 %}
8611
8612 instruct convI2F_mem( regF dst, memory mem ) %{
8613 match(Set dst (ConvI2F (LoadI mem)));
8614 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8615 size(8);
8616 format %{ "LDF $mem,$dst\n\t"
8617 "FITOS $dst,$dst" %}
8618 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8619 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8620 ins_pipe(floadF_mem);
8621 %}
8622
8623
8624 instruct convI2L_reg(iRegL dst, iRegI src) %{
8625 match(Set dst (ConvI2L src));
8626 size(4);
8627 format %{ "SRA $src,0,$dst\t! int->long" %}
8628 opcode(Assembler::sra_op3, Assembler::arith_op);
8629 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8630 ins_pipe(ialu_reg_reg);
8631 %}
8632
8633 // Zero-extend convert int to long
8634 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8635 match(Set dst (AndL (ConvI2L src) mask) );
8636 size(4);
8637 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8638 opcode(Assembler::srl_op3, Assembler::arith_op);
8639 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8640 ins_pipe(ialu_reg_reg);
8641 %}
8642
8643 // Zero-extend long
8644 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8645 match(Set dst (AndL src mask) );
8646 size(4);
8647 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8648 opcode(Assembler::srl_op3, Assembler::arith_op);
8649 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8650 ins_pipe(ialu_reg_reg);
8651 %}
8652
8653
8654 //-----------
8655 // Long to Double conversion using V8 opcodes.
8656 // Still useful because cheetah traps and becomes
8657 // amazingly slow for some common numbers.
8658
8659 // Magic constant, 0x43300000
8660 instruct loadConI_x43300000(iRegI dst) %{
8661 effect(DEF dst);
8662 size(4);
8663 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8664 ins_encode(SetHi22(0x43300000, dst));
8665 ins_pipe(ialu_none);
8666 %}
8667
8668 // Magic constant, 0x41f00000
8669 instruct loadConI_x41f00000(iRegI dst) %{
8670 effect(DEF dst);
8671 size(4);
8672 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8673 ins_encode(SetHi22(0x41f00000, dst));
8674 ins_pipe(ialu_none);
8675 %}
8676
8677 // Construct a double from two float halves
8678 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8679 effect(DEF dst, USE src1, USE src2);
8680 size(8);
8681 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8682 "FMOVS $src2.lo,$dst.lo" %}
8683 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8684 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8685 ins_pipe(faddD_reg_reg);
8686 %}
8687
8688 // Convert integer in high half of a double register (in the lower half of
8689 // the double register file) to double
8690 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8691 effect(DEF dst, USE src);
8692 size(4);
8693 format %{ "FITOD $src,$dst" %}
8694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8695 ins_encode(form3_opf_rs2D_rdD(src, dst));
8696 ins_pipe(fcvtLHi2D);
8697 %}
8698
8699 // Add float double precision
8700 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8701 effect(DEF dst, USE src1, USE src2);
8702 size(4);
8703 format %{ "FADDD $src1,$src2,$dst" %}
8704 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8705 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8706 ins_pipe(faddD_reg_reg);
8707 %}
8708
8709 // Sub float double precision
8710 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8711 effect(DEF dst, USE src1, USE src2);
8712 size(4);
8713 format %{ "FSUBD $src1,$src2,$dst" %}
8714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8715 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8716 ins_pipe(faddD_reg_reg);
8717 %}
8718
8719 // Mul float double precision
8720 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8721 effect(DEF dst, USE src1, USE src2);
8722 size(4);
8723 format %{ "FMULD $src1,$src2,$dst" %}
8724 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8725 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8726 ins_pipe(fmulD_reg_reg);
8727 %}
8728
8729 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8730 match(Set dst (ConvL2D src));
8731 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8732
8733 expand %{
8734 regD_low tmpsrc;
8735 iRegI ix43300000;
8736 iRegI ix41f00000;
8737 stackSlotL lx43300000;
8738 stackSlotL lx41f00000;
8739 regD_low dx43300000;
8740 regD dx41f00000;
8741 regD tmp1;
8742 regD_low tmp2;
8743 regD tmp3;
8744 regD tmp4;
8745
8746 stkL_to_regD(tmpsrc, src);
8747
8748 loadConI_x43300000(ix43300000);
8749 loadConI_x41f00000(ix41f00000);
8750 regI_to_stkLHi(lx43300000, ix43300000);
8751 regI_to_stkLHi(lx41f00000, ix41f00000);
8752 stkL_to_regD(dx43300000, lx43300000);
8753 stkL_to_regD(dx41f00000, lx41f00000);
8754
8755 convI2D_regDHi_regD(tmp1, tmpsrc);
8756 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8757 subD_regD_regD(tmp3, tmp2, dx43300000);
8758 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8759 addD_regD_regD(dst, tmp3, tmp4);
8760 %}
8761 %}
8762
8763 // Long to Double conversion using fast fxtof
8764 instruct convL2D_helper(regD dst, regD tmp) %{
8765 effect(DEF dst, USE tmp);
8766 size(4);
8767 format %{ "FXTOD $tmp,$dst" %}
8768 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8769 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8770 ins_pipe(fcvtL2D);
8771 %}
8772
8773 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8774 predicate(VM_Version::has_fast_fxtof());
8775 match(Set dst (ConvL2D src));
8776 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8777 expand %{
8778 regD tmp;
8779 stkL_to_regD(tmp, src);
8780 convL2D_helper(dst, tmp);
8781 %}
8782 %}
8783
8784 instruct convL2D_reg(regD dst, iRegL src) %{
8785 predicate(UseVIS >= 3);
8786 match(Set dst (ConvL2D src));
8787 expand %{
8788 regD tmp;
8789 MoveL2D_reg_reg(tmp, src);
8790 convL2D_helper(dst, tmp);
8791 %}
8792 %}
8793
8794 // Long to Float conversion using fast fxtof
8795 instruct convL2F_helper(regF dst, regD tmp) %{
8796 effect(DEF dst, USE tmp);
8797 size(4);
8798 format %{ "FXTOS $tmp,$dst" %}
8799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8800 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8801 ins_pipe(fcvtL2F);
8802 %}
8803
8804 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8805 match(Set dst (ConvL2F src));
8806 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8807 expand %{
8808 regD tmp;
8809 stkL_to_regD(tmp, src);
8810 convL2F_helper(dst, tmp);
8811 %}
8812 %}
8813
8814 instruct convL2F_reg(regF dst, iRegL src) %{
8815 predicate(UseVIS >= 3);
8816 match(Set dst (ConvL2F src));
8817 ins_cost(DEFAULT_COST);
8818 expand %{
8819 regD tmp;
8820 MoveL2D_reg_reg(tmp, src);
8821 convL2F_helper(dst, tmp);
8822 %}
8823 %}
8824
8825 //-----------
8826
8827 instruct convL2I_reg(iRegI dst, iRegL src) %{
8828 match(Set dst (ConvL2I src));
8829 #ifndef _LP64
8830 format %{ "MOV $src.lo,$dst\t! long->int" %}
8831 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8832 ins_pipe(ialu_move_reg_I_to_L);
8833 #else
8834 size(4);
8835 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8836 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8837 ins_pipe(ialu_reg);
8838 #endif
8839 %}
8840
8841 // Register Shift Right Immediate
8842 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8843 match(Set dst (ConvL2I (RShiftL src cnt)));
8844
8845 size(4);
8846 format %{ "SRAX $src,$cnt,$dst" %}
8847 opcode(Assembler::srax_op3, Assembler::arith_op);
8848 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8849 ins_pipe(ialu_reg_imm);
8850 %}
8851
8852 //----------Control Flow Instructions------------------------------------------
8853 // Compare Instructions
8854 // Compare Integers
8855 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8856 match(Set icc (CmpI op1 op2));
8857 effect( DEF icc, USE op1, USE op2 );
8858
8859 size(4);
8860 format %{ "CMP $op1,$op2" %}
8861 opcode(Assembler::subcc_op3, Assembler::arith_op);
8862 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8863 ins_pipe(ialu_cconly_reg_reg);
8864 %}
8865
8866 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8867 match(Set icc (CmpU op1 op2));
8868
8869 size(4);
8870 format %{ "CMP $op1,$op2\t! unsigned" %}
8871 opcode(Assembler::subcc_op3, Assembler::arith_op);
8872 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8873 ins_pipe(ialu_cconly_reg_reg);
8874 %}
8875
8876 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8877 match(Set icc (CmpI op1 op2));
8878 effect( DEF icc, USE op1 );
8879
8880 size(4);
8881 format %{ "CMP $op1,$op2" %}
8882 opcode(Assembler::subcc_op3, Assembler::arith_op);
8883 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8884 ins_pipe(ialu_cconly_reg_imm);
8885 %}
8886
8887 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8888 match(Set icc (CmpI (AndI op1 op2) zero));
8889
8890 size(4);
8891 format %{ "BTST $op2,$op1" %}
8892 opcode(Assembler::andcc_op3, Assembler::arith_op);
8893 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8894 ins_pipe(ialu_cconly_reg_reg_zero);
8895 %}
8896
8897 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8898 match(Set icc (CmpI (AndI op1 op2) zero));
8899
8900 size(4);
8901 format %{ "BTST $op2,$op1" %}
8902 opcode(Assembler::andcc_op3, Assembler::arith_op);
8903 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8904 ins_pipe(ialu_cconly_reg_imm_zero);
8905 %}
8906
8907 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8908 match(Set xcc (CmpL op1 op2));
8909 effect( DEF xcc, USE op1, USE op2 );
8910
8911 size(4);
8912 format %{ "CMP $op1,$op2\t\t! long" %}
8913 opcode(Assembler::subcc_op3, Assembler::arith_op);
8914 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8915 ins_pipe(ialu_cconly_reg_reg);
8916 %}
8917
8918 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8919 match(Set xcc (CmpL op1 con));
8920 effect( DEF xcc, USE op1, USE con );
8921
8922 size(4);
8923 format %{ "CMP $op1,$con\t\t! long" %}
8924 opcode(Assembler::subcc_op3, Assembler::arith_op);
8925 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8926 ins_pipe(ialu_cconly_reg_reg);
8927 %}
8928
8929 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8930 match(Set xcc (CmpL (AndL op1 op2) zero));
8931 effect( DEF xcc, USE op1, USE op2 );
8932
8933 size(4);
8934 format %{ "BTST $op1,$op2\t\t! long" %}
8935 opcode(Assembler::andcc_op3, Assembler::arith_op);
8936 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8937 ins_pipe(ialu_cconly_reg_reg);
8938 %}
8939
8940 // useful for checking the alignment of a pointer:
8941 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8942 match(Set xcc (CmpL (AndL op1 con) zero));
8943 effect( DEF xcc, USE op1, USE con );
8944
8945 size(4);
8946 format %{ "BTST $op1,$con\t\t! long" %}
8947 opcode(Assembler::andcc_op3, Assembler::arith_op);
8948 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8949 ins_pipe(ialu_cconly_reg_reg);
8950 %}
8951
8952 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8953 match(Set icc (CmpU op1 op2));
8954
8955 size(4);
8956 format %{ "CMP $op1,$op2\t! unsigned" %}
8957 opcode(Assembler::subcc_op3, Assembler::arith_op);
8958 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8959 ins_pipe(ialu_cconly_reg_imm);
8960 %}
8961
8962 // Compare Pointers
8963 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8964 match(Set pcc (CmpP op1 op2));
8965
8966 size(4);
8967 format %{ "CMP $op1,$op2\t! ptr" %}
8968 opcode(Assembler::subcc_op3, Assembler::arith_op);
8969 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8970 ins_pipe(ialu_cconly_reg_reg);
8971 %}
8972
8973 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8974 match(Set pcc (CmpP op1 op2));
8975
8976 size(4);
8977 format %{ "CMP $op1,$op2\t! ptr" %}
8978 opcode(Assembler::subcc_op3, Assembler::arith_op);
8979 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8980 ins_pipe(ialu_cconly_reg_imm);
8981 %}
8982
8983 // Compare Narrow oops
8984 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8985 match(Set icc (CmpN op1 op2));
8986
8987 size(4);
8988 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8989 opcode(Assembler::subcc_op3, Assembler::arith_op);
8990 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8991 ins_pipe(ialu_cconly_reg_reg);
8992 %}
8993
8994 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8995 match(Set icc (CmpN op1 op2));
8996
8997 size(4);
8998 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8999 opcode(Assembler::subcc_op3, Assembler::arith_op);
9000 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9001 ins_pipe(ialu_cconly_reg_imm);
9002 %}
9003
9004 //----------Max and Min--------------------------------------------------------
9005 // Min Instructions
9006 // Conditional move for min
9007 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9008 effect( USE_DEF op2, USE op1, USE icc );
9009
9010 size(4);
9011 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9012 opcode(Assembler::less);
9013 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9014 ins_pipe(ialu_reg_flags);
9015 %}
9016
9017 // Min Register with Register.
9018 instruct minI_eReg(iRegI op1, iRegI op2) %{
9019 match(Set op2 (MinI op1 op2));
9020 ins_cost(DEFAULT_COST*2);
9021 expand %{
9022 flagsReg icc;
9023 compI_iReg(icc,op1,op2);
9024 cmovI_reg_lt(op2,op1,icc);
9025 %}
9026 %}
9027
9028 // Max Instructions
9029 // Conditional move for max
9030 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9031 effect( USE_DEF op2, USE op1, USE icc );
9032 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9033 opcode(Assembler::greater);
9034 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9035 ins_pipe(ialu_reg_flags);
9036 %}
9037
9038 // Max Register with Register
9039 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9040 match(Set op2 (MaxI op1 op2));
9041 ins_cost(DEFAULT_COST*2);
9042 expand %{
9043 flagsReg icc;
9044 compI_iReg(icc,op1,op2);
9045 cmovI_reg_gt(op2,op1,icc);
9046 %}
9047 %}
9048
9049
9050 //----------Float Compares----------------------------------------------------
9051 // Compare floating, generate condition code
9052 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9053 match(Set fcc (CmpF src1 src2));
9054
9055 size(4);
9056 format %{ "FCMPs $fcc,$src1,$src2" %}
9057 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9058 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9059 ins_pipe(faddF_fcc_reg_reg_zero);
9060 %}
9061
9062 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9063 match(Set fcc (CmpD src1 src2));
9064
9065 size(4);
9066 format %{ "FCMPd $fcc,$src1,$src2" %}
9067 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9068 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9069 ins_pipe(faddD_fcc_reg_reg_zero);
9070 %}
9071
9072
9073 // Compare floating, generate -1,0,1
9074 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9075 match(Set dst (CmpF3 src1 src2));
9076 effect(KILL fcc0);
9077 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9078 format %{ "fcmpl $dst,$src1,$src2" %}
9079 // Primary = float
9080 opcode( true );
9081 ins_encode( floating_cmp( dst, src1, src2 ) );
9082 ins_pipe( floating_cmp );
9083 %}
9084
9085 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9086 match(Set dst (CmpD3 src1 src2));
9087 effect(KILL fcc0);
9088 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9089 format %{ "dcmpl $dst,$src1,$src2" %}
9090 // Primary = double (not float)
9091 opcode( false );
9092 ins_encode( floating_cmp( dst, src1, src2 ) );
9093 ins_pipe( floating_cmp );
9094 %}
9095
9096 //----------Branches---------------------------------------------------------
9097 // Jump
9098 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9099 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9100 match(Jump switch_val);
9101 effect(TEMP table);
9102
9103 ins_cost(350);
9104
9105 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9106 "LD [O7 + $switch_val], O7\n\t"
9107 "JUMP O7" %}
9108 ins_encode %{
9109 // Calculate table address into a register.
9110 Register table_reg;
9111 Register label_reg = O7;
9112 // If we are calculating the size of this instruction don't trust
9113 // zero offsets because they might change when
9114 // MachConstantBaseNode decides to optimize the constant table
9115 // base.
9116 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9117 table_reg = $constanttablebase;
9118 } else {
9119 table_reg = O7;
9120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9121 __ add($constanttablebase, con_offset, table_reg);
9122 }
9123
9124 // Jump to base address + switch value
9125 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9126 __ jmp(label_reg, G0);
9127 __ delayed()->nop();
9128 %}
9129 ins_pipe(ialu_reg_reg);
9130 %}
9131
9132 // Direct Branch. Use V8 version with longer range.
9133 instruct branch(label labl) %{
9134 match(Goto);
9135 effect(USE labl);
9136
9137 size(8);
9138 ins_cost(BRANCH_COST);
9139 format %{ "BA $labl" %}
9140 ins_encode %{
9141 Label* L = $labl$$label;
9142 __ ba(*L);
9143 __ delayed()->nop();
9144 %}
9145 ins_pipe(br);
9146 %}
9147
9148 // Direct Branch, short with no delay slot
9149 instruct branch_short(label labl) %{
9150 match(Goto);
9151 predicate(UseCBCond);
9152 effect(USE labl);
9153
9154 size(4);
9155 ins_cost(BRANCH_COST);
9156 format %{ "BA $labl\t! short branch" %}
9157 ins_encode %{
9158 Label* L = $labl$$label;
9159 assert(__ use_cbcond(*L), "back to back cbcond");
9160 __ ba_short(*L);
9161 %}
9162 ins_short_branch(1);
9163 ins_avoid_back_to_back(1);
9164 ins_pipe(cbcond_reg_imm);
9165 %}
9166
9167 // Conditional Direct Branch
9168 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9169 match(If cmp icc);
9170 effect(USE labl);
9171
9172 size(8);
9173 ins_cost(BRANCH_COST);
9174 format %{ "BP$cmp $icc,$labl" %}
9175 // Prim = bits 24-22, Secnd = bits 31-30
9176 ins_encode( enc_bp( labl, cmp, icc ) );
9177 ins_pipe(br_cc);
9178 %}
9179
9180 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9181 match(If cmp icc);
9182 effect(USE labl);
9183
9184 ins_cost(BRANCH_COST);
9185 format %{ "BP$cmp $icc,$labl" %}
9186 // Prim = bits 24-22, Secnd = bits 31-30
9187 ins_encode( enc_bp( labl, cmp, icc ) );
9188 ins_pipe(br_cc);
9189 %}
9190
9191 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9192 match(If cmp pcc);
9193 effect(USE labl);
9194
9195 size(8);
9196 ins_cost(BRANCH_COST);
9197 format %{ "BP$cmp $pcc,$labl" %}
9198 ins_encode %{
9199 Label* L = $labl$$label;
9200 Assembler::Predict predict_taken =
9201 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9202
9203 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9204 __ delayed()->nop();
9205 %}
9206 ins_pipe(br_cc);
9207 %}
9208
9209 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9210 match(If cmp fcc);
9211 effect(USE labl);
9212
9213 size(8);
9214 ins_cost(BRANCH_COST);
9215 format %{ "FBP$cmp $fcc,$labl" %}
9216 ins_encode %{
9217 Label* L = $labl$$label;
9218 Assembler::Predict predict_taken =
9219 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9220
9221 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9222 __ delayed()->nop();
9223 %}
9224 ins_pipe(br_fcc);
9225 %}
9226
9227 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9228 match(CountedLoopEnd cmp icc);
9229 effect(USE labl);
9230
9231 size(8);
9232 ins_cost(BRANCH_COST);
9233 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9234 // Prim = bits 24-22, Secnd = bits 31-30
9235 ins_encode( enc_bp( labl, cmp, icc ) );
9236 ins_pipe(br_cc);
9237 %}
9238
9239 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9240 match(CountedLoopEnd cmp icc);
9241 effect(USE labl);
9242
9243 size(8);
9244 ins_cost(BRANCH_COST);
9245 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9246 // Prim = bits 24-22, Secnd = bits 31-30
9247 ins_encode( enc_bp( labl, cmp, icc ) );
9248 ins_pipe(br_cc);
9249 %}
9250
9251 // Compare and branch instructions
9252 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9253 match(If cmp (CmpI op1 op2));
9254 effect(USE labl, KILL icc);
9255
9256 size(12);
9257 ins_cost(BRANCH_COST);
9258 format %{ "CMP $op1,$op2\t! int\n\t"
9259 "BP$cmp $labl" %}
9260 ins_encode %{
9261 Label* L = $labl$$label;
9262 Assembler::Predict predict_taken =
9263 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9264 __ cmp($op1$$Register, $op2$$Register);
9265 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9266 __ delayed()->nop();
9267 %}
9268 ins_pipe(cmp_br_reg_reg);
9269 %}
9270
9271 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9272 match(If cmp (CmpI op1 op2));
9273 effect(USE labl, KILL icc);
9274
9275 size(12);
9276 ins_cost(BRANCH_COST);
9277 format %{ "CMP $op1,$op2\t! int\n\t"
9278 "BP$cmp $labl" %}
9279 ins_encode %{
9280 Label* L = $labl$$label;
9281 Assembler::Predict predict_taken =
9282 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9283 __ cmp($op1$$Register, $op2$$constant);
9284 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9285 __ delayed()->nop();
9286 %}
9287 ins_pipe(cmp_br_reg_imm);
9288 %}
9289
9290 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9291 match(If cmp (CmpU op1 op2));
9292 effect(USE labl, KILL icc);
9293
9294 size(12);
9295 ins_cost(BRANCH_COST);
9296 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9297 "BP$cmp $labl" %}
9298 ins_encode %{
9299 Label* L = $labl$$label;
9300 Assembler::Predict predict_taken =
9301 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9302 __ cmp($op1$$Register, $op2$$Register);
9303 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9304 __ delayed()->nop();
9305 %}
9306 ins_pipe(cmp_br_reg_reg);
9307 %}
9308
9309 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9310 match(If cmp (CmpU op1 op2));
9311 effect(USE labl, KILL icc);
9312
9313 size(12);
9314 ins_cost(BRANCH_COST);
9315 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9316 "BP$cmp $labl" %}
9317 ins_encode %{
9318 Label* L = $labl$$label;
9319 Assembler::Predict predict_taken =
9320 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9321 __ cmp($op1$$Register, $op2$$constant);
9322 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9323 __ delayed()->nop();
9324 %}
9325 ins_pipe(cmp_br_reg_imm);
9326 %}
9327
9328 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9329 match(If cmp (CmpL op1 op2));
9330 effect(USE labl, KILL xcc);
9331
9332 size(12);
9333 ins_cost(BRANCH_COST);
9334 format %{ "CMP $op1,$op2\t! long\n\t"
9335 "BP$cmp $labl" %}
9336 ins_encode %{
9337 Label* L = $labl$$label;
9338 Assembler::Predict predict_taken =
9339 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9340 __ cmp($op1$$Register, $op2$$Register);
9341 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9342 __ delayed()->nop();
9343 %}
9344 ins_pipe(cmp_br_reg_reg);
9345 %}
9346
9347 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9348 match(If cmp (CmpL op1 op2));
9349 effect(USE labl, KILL xcc);
9350
9351 size(12);
9352 ins_cost(BRANCH_COST);
9353 format %{ "CMP $op1,$op2\t! long\n\t"
9354 "BP$cmp $labl" %}
9355 ins_encode %{
9356 Label* L = $labl$$label;
9357 Assembler::Predict predict_taken =
9358 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9359 __ cmp($op1$$Register, $op2$$constant);
9360 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9361 __ delayed()->nop();
9362 %}
9363 ins_pipe(cmp_br_reg_imm);
9364 %}
9365
9366 // Compare Pointers and branch
9367 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9368 match(If cmp (CmpP op1 op2));
9369 effect(USE labl, KILL pcc);
9370
9371 size(12);
9372 ins_cost(BRANCH_COST);
9373 format %{ "CMP $op1,$op2\t! ptr\n\t"
9374 "B$cmp $labl" %}
9375 ins_encode %{
9376 Label* L = $labl$$label;
9377 Assembler::Predict predict_taken =
9378 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9379 __ cmp($op1$$Register, $op2$$Register);
9380 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9381 __ delayed()->nop();
9382 %}
9383 ins_pipe(cmp_br_reg_reg);
9384 %}
9385
9386 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9387 match(If cmp (CmpP op1 null));
9388 effect(USE labl, KILL pcc);
9389
9390 size(12);
9391 ins_cost(BRANCH_COST);
9392 format %{ "CMP $op1,0\t! ptr\n\t"
9393 "B$cmp $labl" %}
9394 ins_encode %{
9395 Label* L = $labl$$label;
9396 Assembler::Predict predict_taken =
9397 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9398 __ cmp($op1$$Register, G0);
9399 // bpr() is not used here since it has shorter distance.
9400 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9401 __ delayed()->nop();
9402 %}
9403 ins_pipe(cmp_br_reg_reg);
9404 %}
9405
9406 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9407 match(If cmp (CmpN op1 op2));
9408 effect(USE labl, KILL icc);
9409
9410 size(12);
9411 ins_cost(BRANCH_COST);
9412 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9413 "BP$cmp $labl" %}
9414 ins_encode %{
9415 Label* L = $labl$$label;
9416 Assembler::Predict predict_taken =
9417 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9418 __ cmp($op1$$Register, $op2$$Register);
9419 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9420 __ delayed()->nop();
9421 %}
9422 ins_pipe(cmp_br_reg_reg);
9423 %}
9424
9425 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9426 match(If cmp (CmpN op1 null));
9427 effect(USE labl, KILL icc);
9428
9429 size(12);
9430 ins_cost(BRANCH_COST);
9431 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9432 "BP$cmp $labl" %}
9433 ins_encode %{
9434 Label* L = $labl$$label;
9435 Assembler::Predict predict_taken =
9436 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9437 __ cmp($op1$$Register, G0);
9438 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9439 __ delayed()->nop();
9440 %}
9441 ins_pipe(cmp_br_reg_reg);
9442 %}
9443
9444 // Loop back branch
9445 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9446 match(CountedLoopEnd cmp (CmpI op1 op2));
9447 effect(USE labl, KILL icc);
9448
9449 size(12);
9450 ins_cost(BRANCH_COST);
9451 format %{ "CMP $op1,$op2\t! int\n\t"
9452 "BP$cmp $labl\t! Loop end" %}
9453 ins_encode %{
9454 Label* L = $labl$$label;
9455 Assembler::Predict predict_taken =
9456 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9457 __ cmp($op1$$Register, $op2$$Register);
9458 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9459 __ delayed()->nop();
9460 %}
9461 ins_pipe(cmp_br_reg_reg);
9462 %}
9463
9464 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9465 match(CountedLoopEnd cmp (CmpI op1 op2));
9466 effect(USE labl, KILL icc);
9467
9468 size(12);
9469 ins_cost(BRANCH_COST);
9470 format %{ "CMP $op1,$op2\t! int\n\t"
9471 "BP$cmp $labl\t! Loop end" %}
9472 ins_encode %{
9473 Label* L = $labl$$label;
9474 Assembler::Predict predict_taken =
9475 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9476 __ cmp($op1$$Register, $op2$$constant);
9477 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9478 __ delayed()->nop();
9479 %}
9480 ins_pipe(cmp_br_reg_imm);
9481 %}
9482
9483 // Short compare and branch instructions
9484 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9485 match(If cmp (CmpI op1 op2));
9486 predicate(UseCBCond);
9487 effect(USE labl, KILL icc);
9488
9489 size(4);
9490 ins_cost(BRANCH_COST);
9491 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9492 ins_encode %{
9493 Label* L = $labl$$label;
9494 assert(__ use_cbcond(*L), "back to back cbcond");
9495 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9496 %}
9497 ins_short_branch(1);
9498 ins_avoid_back_to_back(1);
9499 ins_pipe(cbcond_reg_reg);
9500 %}
9501
9502 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9503 match(If cmp (CmpI op1 op2));
9504 predicate(UseCBCond);
9505 effect(USE labl, KILL icc);
9506
9507 size(4);
9508 ins_cost(BRANCH_COST);
9509 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9510 ins_encode %{
9511 Label* L = $labl$$label;
9512 assert(__ use_cbcond(*L), "back to back cbcond");
9513 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9514 %}
9515 ins_short_branch(1);
9516 ins_avoid_back_to_back(1);
9517 ins_pipe(cbcond_reg_imm);
9518 %}
9519
9520 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9521 match(If cmp (CmpU op1 op2));
9522 predicate(UseCBCond);
9523 effect(USE labl, KILL icc);
9524
9525 size(4);
9526 ins_cost(BRANCH_COST);
9527 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9528 ins_encode %{
9529 Label* L = $labl$$label;
9530 assert(__ use_cbcond(*L), "back to back cbcond");
9531 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9532 %}
9533 ins_short_branch(1);
9534 ins_avoid_back_to_back(1);
9535 ins_pipe(cbcond_reg_reg);
9536 %}
9537
9538 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9539 match(If cmp (CmpU op1 op2));
9540 predicate(UseCBCond);
9541 effect(USE labl, KILL icc);
9542
9543 size(4);
9544 ins_cost(BRANCH_COST);
9545 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9546 ins_encode %{
9547 Label* L = $labl$$label;
9548 assert(__ use_cbcond(*L), "back to back cbcond");
9549 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9550 %}
9551 ins_short_branch(1);
9552 ins_avoid_back_to_back(1);
9553 ins_pipe(cbcond_reg_imm);
9554 %}
9555
9556 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9557 match(If cmp (CmpL op1 op2));
9558 predicate(UseCBCond);
9559 effect(USE labl, KILL xcc);
9560
9561 size(4);
9562 ins_cost(BRANCH_COST);
9563 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9564 ins_encode %{
9565 Label* L = $labl$$label;
9566 assert(__ use_cbcond(*L), "back to back cbcond");
9567 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9568 %}
9569 ins_short_branch(1);
9570 ins_avoid_back_to_back(1);
9571 ins_pipe(cbcond_reg_reg);
9572 %}
9573
9574 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9575 match(If cmp (CmpL op1 op2));
9576 predicate(UseCBCond);
9577 effect(USE labl, KILL xcc);
9578
9579 size(4);
9580 ins_cost(BRANCH_COST);
9581 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9582 ins_encode %{
9583 Label* L = $labl$$label;
9584 assert(__ use_cbcond(*L), "back to back cbcond");
9585 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9586 %}
9587 ins_short_branch(1);
9588 ins_avoid_back_to_back(1);
9589 ins_pipe(cbcond_reg_imm);
9590 %}
9591
9592 // Compare Pointers and branch
9593 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9594 match(If cmp (CmpP op1 op2));
9595 predicate(UseCBCond);
9596 effect(USE labl, KILL pcc);
9597
9598 size(4);
9599 ins_cost(BRANCH_COST);
9600 #ifdef _LP64
9601 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9602 #else
9603 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9604 #endif
9605 ins_encode %{
9606 Label* L = $labl$$label;
9607 assert(__ use_cbcond(*L), "back to back cbcond");
9608 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9609 %}
9610 ins_short_branch(1);
9611 ins_avoid_back_to_back(1);
9612 ins_pipe(cbcond_reg_reg);
9613 %}
9614
9615 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9616 match(If cmp (CmpP op1 null));
9617 predicate(UseCBCond);
9618 effect(USE labl, KILL pcc);
9619
9620 size(4);
9621 ins_cost(BRANCH_COST);
9622 #ifdef _LP64
9623 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9624 #else
9625 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9626 #endif
9627 ins_encode %{
9628 Label* L = $labl$$label;
9629 assert(__ use_cbcond(*L), "back to back cbcond");
9630 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9631 %}
9632 ins_short_branch(1);
9633 ins_avoid_back_to_back(1);
9634 ins_pipe(cbcond_reg_reg);
9635 %}
9636
9637 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9638 match(If cmp (CmpN op1 op2));
9639 predicate(UseCBCond);
9640 effect(USE labl, KILL icc);
9641
9642 size(4);
9643 ins_cost(BRANCH_COST);
9644 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9645 ins_encode %{
9646 Label* L = $labl$$label;
9647 assert(__ use_cbcond(*L), "back to back cbcond");
9648 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9649 %}
9650 ins_short_branch(1);
9651 ins_avoid_back_to_back(1);
9652 ins_pipe(cbcond_reg_reg);
9653 %}
9654
9655 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9656 match(If cmp (CmpN op1 null));
9657 predicate(UseCBCond);
9658 effect(USE labl, KILL icc);
9659
9660 size(4);
9661 ins_cost(BRANCH_COST);
9662 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9663 ins_encode %{
9664 Label* L = $labl$$label;
9665 assert(__ use_cbcond(*L), "back to back cbcond");
9666 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9667 %}
9668 ins_short_branch(1);
9669 ins_avoid_back_to_back(1);
9670 ins_pipe(cbcond_reg_reg);
9671 %}
9672
9673 // Loop back branch
9674 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9675 match(CountedLoopEnd cmp (CmpI op1 op2));
9676 predicate(UseCBCond);
9677 effect(USE labl, KILL icc);
9678
9679 size(4);
9680 ins_cost(BRANCH_COST);
9681 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9682 ins_encode %{
9683 Label* L = $labl$$label;
9684 assert(__ use_cbcond(*L), "back to back cbcond");
9685 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9686 %}
9687 ins_short_branch(1);
9688 ins_avoid_back_to_back(1);
9689 ins_pipe(cbcond_reg_reg);
9690 %}
9691
9692 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9693 match(CountedLoopEnd cmp (CmpI op1 op2));
9694 predicate(UseCBCond);
9695 effect(USE labl, KILL icc);
9696
9697 size(4);
9698 ins_cost(BRANCH_COST);
9699 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9700 ins_encode %{
9701 Label* L = $labl$$label;
9702 assert(__ use_cbcond(*L), "back to back cbcond");
9703 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9704 %}
9705 ins_short_branch(1);
9706 ins_avoid_back_to_back(1);
9707 ins_pipe(cbcond_reg_imm);
9708 %}
9709
9710 // Branch-on-register tests all 64 bits. We assume that values
9711 // in 64-bit registers always remains zero or sign extended
9712 // unless our code munges the high bits. Interrupts can chop
9713 // the high order bits to zero or sign at any time.
9714 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9715 match(If cmp (CmpI op1 zero));
9716 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9717 effect(USE labl);
9718
9719 size(8);
9720 ins_cost(BRANCH_COST);
9721 format %{ "BR$cmp $op1,$labl" %}
9722 ins_encode( enc_bpr( labl, cmp, op1 ) );
9723 ins_pipe(br_reg);
9724 %}
9725
9726 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9727 match(If cmp (CmpP op1 null));
9728 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9729 effect(USE labl);
9730
9731 size(8);
9732 ins_cost(BRANCH_COST);
9733 format %{ "BR$cmp $op1,$labl" %}
9734 ins_encode( enc_bpr( labl, cmp, op1 ) );
9735 ins_pipe(br_reg);
9736 %}
9737
9738 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9739 match(If cmp (CmpL op1 zero));
9740 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9741 effect(USE labl);
9742
9743 size(8);
9744 ins_cost(BRANCH_COST);
9745 format %{ "BR$cmp $op1,$labl" %}
9746 ins_encode( enc_bpr( labl, cmp, op1 ) );
9747 ins_pipe(br_reg);
9748 %}
9749
9750
9751 // ============================================================================
9752 // Long Compare
9753 //
9754 // Currently we hold longs in 2 registers. Comparing such values efficiently
9755 // is tricky. The flavor of compare used depends on whether we are testing
9756 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9757 // The GE test is the negated LT test. The LE test can be had by commuting
9758 // the operands (yielding a GE test) and then negating; negate again for the
9759 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9760 // NE test is negated from that.
9761
9762 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9763 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9764 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9765 // are collapsed internally in the ADLC's dfa-gen code. The match for
9766 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9767 // foo match ends up with the wrong leaf. One fix is to not match both
9768 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9769 // both forms beat the trinary form of long-compare and both are very useful
9770 // on Intel which has so few registers.
9771
9772 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9773 match(If cmp xcc);
9774 effect(USE labl);
9775
9776 size(8);
9777 ins_cost(BRANCH_COST);
9778 format %{ "BP$cmp $xcc,$labl" %}
9779 ins_encode %{
9780 Label* L = $labl$$label;
9781 Assembler::Predict predict_taken =
9782 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9783
9784 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9785 __ delayed()->nop();
9786 %}
9787 ins_pipe(br_cc);
9788 %}
9789
9790 // Manifest a CmpL3 result in an integer register. Very painful.
9791 // This is the test to avoid.
9792 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9793 match(Set dst (CmpL3 src1 src2) );
9794 effect( KILL ccr );
9795 ins_cost(6*DEFAULT_COST);
9796 size(24);
9797 format %{ "CMP $src1,$src2\t\t! long\n"
9798 "\tBLT,a,pn done\n"
9799 "\tMOV -1,$dst\t! delay slot\n"
9800 "\tBGT,a,pn done\n"
9801 "\tMOV 1,$dst\t! delay slot\n"
9802 "\tCLR $dst\n"
9803 "done:" %}
9804 ins_encode( cmpl_flag(src1,src2,dst) );
9805 ins_pipe(cmpL_reg);
9806 %}
9807
9808 // Conditional move
9809 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9810 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9811 ins_cost(150);
9812 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9813 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9814 ins_pipe(ialu_reg);
9815 %}
9816
9817 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9818 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9819 ins_cost(140);
9820 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9821 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9822 ins_pipe(ialu_imm);
9823 %}
9824
9825 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9826 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9827 ins_cost(150);
9828 format %{ "MOV$cmp $xcc,$src,$dst" %}
9829 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9830 ins_pipe(ialu_reg);
9831 %}
9832
9833 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9834 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9835 ins_cost(140);
9836 format %{ "MOV$cmp $xcc,$src,$dst" %}
9837 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9838 ins_pipe(ialu_imm);
9839 %}
9840
9841 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9842 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9843 ins_cost(150);
9844 format %{ "MOV$cmp $xcc,$src,$dst" %}
9845 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9846 ins_pipe(ialu_reg);
9847 %}
9848
9849 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9850 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9851 ins_cost(150);
9852 format %{ "MOV$cmp $xcc,$src,$dst" %}
9853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9854 ins_pipe(ialu_reg);
9855 %}
9856
9857 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9858 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9859 ins_cost(140);
9860 format %{ "MOV$cmp $xcc,$src,$dst" %}
9861 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9862 ins_pipe(ialu_imm);
9863 %}
9864
9865 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9866 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9867 ins_cost(150);
9868 opcode(0x101);
9869 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9870 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9871 ins_pipe(int_conditional_float_move);
9872 %}
9873
9874 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9875 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9876 ins_cost(150);
9877 opcode(0x102);
9878 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9879 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9880 ins_pipe(int_conditional_float_move);
9881 %}
9882
9883 // ============================================================================
9884 // Safepoint Instruction
9885 instruct safePoint_poll(iRegP poll) %{
9886 match(SafePoint poll);
9887 effect(USE poll);
9888
9889 size(4);
9890 #ifdef _LP64
9891 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9892 #else
9893 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9894 #endif
9895 ins_encode %{
9896 __ relocate(relocInfo::poll_type);
9897 __ ld_ptr($poll$$Register, 0, G0);
9898 %}
9899 ins_pipe(loadPollP);
9900 %}
9901
9902 // ============================================================================
9903 // Call Instructions
9904 // Call Java Static Instruction
9905 instruct CallStaticJavaDirect( method meth ) %{
9906 match(CallStaticJava);
9907 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9908 effect(USE meth);
9909
9910 size(8);
9911 ins_cost(CALL_COST);
9912 format %{ "CALL,static ; NOP ==> " %}
9913 ins_encode( Java_Static_Call( meth ), call_epilog );
9914 ins_pipe(simple_call);
9915 %}
9916
9917 // Call Java Static Instruction (method handle version)
9918 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9919 match(CallStaticJava);
9920 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9921 effect(USE meth, KILL l7_mh_SP_save);
9922
9923 size(16);
9924 ins_cost(CALL_COST);
9925 format %{ "CALL,static/MethodHandle" %}
9926 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9927 ins_pipe(simple_call);
9928 %}
9929
9930 // Call Java Dynamic Instruction
9931 instruct CallDynamicJavaDirect( method meth ) %{
9932 match(CallDynamicJava);
9933 effect(USE meth);
9934
9935 ins_cost(CALL_COST);
9936 format %{ "SET (empty),R_G5\n\t"
9937 "CALL,dynamic ; NOP ==> " %}
9938 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9939 ins_pipe(call);
9940 %}
9941
9942 // Call Runtime Instruction
9943 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9944 match(CallRuntime);
9945 effect(USE meth, KILL l7);
9946 ins_cost(CALL_COST);
9947 format %{ "CALL,runtime" %}
9948 ins_encode( Java_To_Runtime( meth ),
9949 call_epilog, adjust_long_from_native_call );
9950 ins_pipe(simple_call);
9951 %}
9952
9953 // Call runtime without safepoint - same as CallRuntime
9954 instruct CallLeafDirect(method meth, l7RegP l7) %{
9955 match(CallLeaf);
9956 effect(USE meth, KILL l7);
9957 ins_cost(CALL_COST);
9958 format %{ "CALL,runtime leaf" %}
9959 ins_encode( Java_To_Runtime( meth ),
9960 call_epilog,
9961 adjust_long_from_native_call );
9962 ins_pipe(simple_call);
9963 %}
9964
9965 // Call runtime without safepoint - same as CallLeaf
9966 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9967 match(CallLeafNoFP);
9968 effect(USE meth, KILL l7);
9969 ins_cost(CALL_COST);
9970 format %{ "CALL,runtime leaf nofp" %}
9971 ins_encode( Java_To_Runtime( meth ),
9972 call_epilog,
9973 adjust_long_from_native_call );
9974 ins_pipe(simple_call);
9975 %}
9976
9977 // Tail Call; Jump from runtime stub to Java code.
9978 // Also known as an 'interprocedural jump'.
9979 // Target of jump will eventually return to caller.
9980 // TailJump below removes the return address.
9981 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9982 match(TailCall jump_target method_oop );
9983
9984 ins_cost(CALL_COST);
9985 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9986 ins_encode(form_jmpl(jump_target));
9987 ins_pipe(tail_call);
9988 %}
9989
9990
9991 // Return Instruction
9992 instruct Ret() %{
9993 match(Return);
9994
9995 // The epilogue node did the ret already.
9996 size(0);
9997 format %{ "! return" %}
9998 ins_encode();
9999 ins_pipe(empty);
10000 %}
10001
10002
10003 // Tail Jump; remove the return address; jump to target.
10004 // TailCall above leaves the return address around.
10005 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10006 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10007 // "restore" before this instruction (in Epilogue), we need to materialize it
10008 // in %i0.
10009 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10010 match( TailJump jump_target ex_oop );
10011 ins_cost(CALL_COST);
10012 format %{ "! discard R_O7\n\t"
10013 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10014 ins_encode(form_jmpl_set_exception_pc(jump_target));
10015 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10016 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10017 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10018 ins_pipe(tail_call);
10019 %}
10020
10021 // Create exception oop: created by stack-crawling runtime code.
10022 // Created exception is now available to this handler, and is setup
10023 // just prior to jumping to this handler. No code emitted.
10024 instruct CreateException( o0RegP ex_oop )
10025 %{
10026 match(Set ex_oop (CreateEx));
10027 ins_cost(0);
10028
10029 size(0);
10030 // use the following format syntax
10031 format %{ "! exception oop is in R_O0; no code emitted" %}
10032 ins_encode();
10033 ins_pipe(empty);
10034 %}
10035
10036
10037 // Rethrow exception:
10038 // The exception oop will come in the first argument position.
10039 // Then JUMP (not call) to the rethrow stub code.
10040 instruct RethrowException()
10041 %{
10042 match(Rethrow);
10043 ins_cost(CALL_COST);
10044
10045 // use the following format syntax
10046 format %{ "Jmp rethrow_stub" %}
10047 ins_encode(enc_rethrow);
10048 ins_pipe(tail_call);
10049 %}
10050
10051
10052 // Die now
10053 instruct ShouldNotReachHere( )
10054 %{
10055 match(Halt);
10056 ins_cost(CALL_COST);
10057
10058 size(4);
10059 // Use the following format syntax
10060 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10061 ins_encode( form2_illtrap() );
10062 ins_pipe(tail_call);
10063 %}
10064
10065 // ============================================================================
10066 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10067 // array for an instance of the superklass. Set a hidden internal cache on a
10068 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10069 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10070 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10071 match(Set index (PartialSubtypeCheck sub super));
10072 effect( KILL pcc, KILL o7 );
10073 ins_cost(DEFAULT_COST*10);
10074 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10075 ins_encode( enc_PartialSubtypeCheck() );
10076 ins_pipe(partial_subtype_check_pipe);
10077 %}
10078
10079 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10080 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10081 effect( KILL idx, KILL o7 );
10082 ins_cost(DEFAULT_COST*10);
10083 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10084 ins_encode( enc_PartialSubtypeCheck() );
10085 ins_pipe(partial_subtype_check_pipe);
10086 %}
10087
10088
10089 // ============================================================================
10090 // inlined locking and unlocking
10091
10092 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10093 match(Set pcc (FastLock object box));
10094
10095 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10096 ins_cost(100);
10097
10098 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10099 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10100 ins_pipe(long_memory_op);
10101 %}
10102
10103
10104 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10105 match(Set pcc (FastUnlock object box));
10106 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10107 ins_cost(100);
10108
10109 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10110 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10111 ins_pipe(long_memory_op);
10112 %}
10113
10114 // The encodings are generic.
10115 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10116 predicate(!use_block_zeroing(n->in(2)) );
10117 match(Set dummy (ClearArray cnt base));
10118 effect(TEMP temp, KILL ccr);
10119 ins_cost(300);
10120 format %{ "MOV $cnt,$temp\n"
10121 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10122 " BRge loop\t\t! Clearing loop\n"
10123 " STX G0,[$base+$temp]\t! delay slot" %}
10124
10125 ins_encode %{
10126 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10127 Register nof_bytes_arg = $cnt$$Register;
10128 Register nof_bytes_tmp = $temp$$Register;
10129 Register base_pointer_arg = $base$$Register;
10130
10131 Label loop;
10132 __ mov(nof_bytes_arg, nof_bytes_tmp);
10133
10134 // Loop and clear, walking backwards through the array.
10135 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10136 __ bind(loop);
10137 __ deccc(nof_bytes_tmp, 8);
10138 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10139 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10140 // %%%% this mini-loop must not cross a cache boundary!
10141 %}
10142 ins_pipe(long_memory_op);
10143 %}
10144
10145 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10146 predicate(use_block_zeroing(n->in(2)));
10147 match(Set dummy (ClearArray cnt base));
10148 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10149 ins_cost(300);
10150 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10151
10152 ins_encode %{
10153
10154 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10155 Register to = $base$$Register;
10156 Register count = $cnt$$Register;
10157
10158 Label Ldone;
10159 __ nop(); // Separate short branches
10160 // Use BIS for zeroing (temp is not used).
10161 __ bis_zeroing(to, count, G0, Ldone);
10162 __ bind(Ldone);
10163
10164 %}
10165 ins_pipe(long_memory_op);
10166 %}
10167
10168 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10169 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10170 match(Set dummy (ClearArray cnt base));
10171 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10172 ins_cost(300);
10173 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10174
10175 ins_encode %{
10176
10177 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10178 Register to = $base$$Register;
10179 Register count = $cnt$$Register;
10180 Register temp = $tmp$$Register;
10181
10182 Label Ldone;
10183 __ nop(); // Separate short branches
10184 // Use BIS for zeroing
10185 __ bis_zeroing(to, count, temp, Ldone);
10186 __ bind(Ldone);
10187
10188 %}
10189 ins_pipe(long_memory_op);
10190 %}
10191
10192 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10193 o7RegI tmp, flagsReg ccr) %{
10194 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10195 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10196 ins_cost(300);
10197 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10198 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10199 ins_pipe(long_memory_op);
10200 %}
10201
10202 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10203 o7RegI tmp, flagsReg ccr) %{
10204 match(Set result (StrEquals (Binary str1 str2) cnt));
10205 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10206 ins_cost(300);
10207 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10208 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10209 ins_pipe(long_memory_op);
10210 %}
10211
10212 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10213 o7RegI tmp2, flagsReg ccr) %{
10214 match(Set result (AryEq ary1 ary2));
10215 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10216 ins_cost(300);
10217 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10218 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10219 ins_pipe(long_memory_op);
10220 %}
10221
10222
10223 //---------- Zeros Count Instructions ------------------------------------------
10224
10225 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10226 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10227 match(Set dst (CountLeadingZerosI src));
10228 effect(TEMP dst, TEMP tmp, KILL cr);
10229
10230 // x |= (x >> 1);
10231 // x |= (x >> 2);
10232 // x |= (x >> 4);
10233 // x |= (x >> 8);
10234 // x |= (x >> 16);
10235 // return (WORDBITS - popc(x));
10236 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10237 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10238 "OR $dst,$tmp,$dst\n\t"
10239 "SRL $dst,2,$tmp\n\t"
10240 "OR $dst,$tmp,$dst\n\t"
10241 "SRL $dst,4,$tmp\n\t"
10242 "OR $dst,$tmp,$dst\n\t"
10243 "SRL $dst,8,$tmp\n\t"
10244 "OR $dst,$tmp,$dst\n\t"
10245 "SRL $dst,16,$tmp\n\t"
10246 "OR $dst,$tmp,$dst\n\t"
10247 "POPC $dst,$dst\n\t"
10248 "MOV 32,$tmp\n\t"
10249 "SUB $tmp,$dst,$dst" %}
10250 ins_encode %{
10251 Register Rdst = $dst$$Register;
10252 Register Rsrc = $src$$Register;
10253 Register Rtmp = $tmp$$Register;
10254 __ srl(Rsrc, 1, Rtmp);
10255 __ srl(Rsrc, 0, Rdst);
10256 __ or3(Rdst, Rtmp, Rdst);
10257 __ srl(Rdst, 2, Rtmp);
10258 __ or3(Rdst, Rtmp, Rdst);
10259 __ srl(Rdst, 4, Rtmp);
10260 __ or3(Rdst, Rtmp, Rdst);
10261 __ srl(Rdst, 8, Rtmp);
10262 __ or3(Rdst, Rtmp, Rdst);
10263 __ srl(Rdst, 16, Rtmp);
10264 __ or3(Rdst, Rtmp, Rdst);
10265 __ popc(Rdst, Rdst);
10266 __ mov(BitsPerInt, Rtmp);
10267 __ sub(Rtmp, Rdst, Rdst);
10268 %}
10269 ins_pipe(ialu_reg);
10270 %}
10271
10272 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10273 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10274 match(Set dst (CountLeadingZerosL src));
10275 effect(TEMP dst, TEMP tmp, KILL cr);
10276
10277 // x |= (x >> 1);
10278 // x |= (x >> 2);
10279 // x |= (x >> 4);
10280 // x |= (x >> 8);
10281 // x |= (x >> 16);
10282 // x |= (x >> 32);
10283 // return (WORDBITS - popc(x));
10284 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10285 "OR $src,$tmp,$dst\n\t"
10286 "SRLX $dst,2,$tmp\n\t"
10287 "OR $dst,$tmp,$dst\n\t"
10288 "SRLX $dst,4,$tmp\n\t"
10289 "OR $dst,$tmp,$dst\n\t"
10290 "SRLX $dst,8,$tmp\n\t"
10291 "OR $dst,$tmp,$dst\n\t"
10292 "SRLX $dst,16,$tmp\n\t"
10293 "OR $dst,$tmp,$dst\n\t"
10294 "SRLX $dst,32,$tmp\n\t"
10295 "OR $dst,$tmp,$dst\n\t"
10296 "POPC $dst,$dst\n\t"
10297 "MOV 64,$tmp\n\t"
10298 "SUB $tmp,$dst,$dst" %}
10299 ins_encode %{
10300 Register Rdst = $dst$$Register;
10301 Register Rsrc = $src$$Register;
10302 Register Rtmp = $tmp$$Register;
10303 __ srlx(Rsrc, 1, Rtmp);
10304 __ or3( Rsrc, Rtmp, Rdst);
10305 __ srlx(Rdst, 2, Rtmp);
10306 __ or3( Rdst, Rtmp, Rdst);
10307 __ srlx(Rdst, 4, Rtmp);
10308 __ or3( Rdst, Rtmp, Rdst);
10309 __ srlx(Rdst, 8, Rtmp);
10310 __ or3( Rdst, Rtmp, Rdst);
10311 __ srlx(Rdst, 16, Rtmp);
10312 __ or3( Rdst, Rtmp, Rdst);
10313 __ srlx(Rdst, 32, Rtmp);
10314 __ or3( Rdst, Rtmp, Rdst);
10315 __ popc(Rdst, Rdst);
10316 __ mov(BitsPerLong, Rtmp);
10317 __ sub(Rtmp, Rdst, Rdst);
10318 %}
10319 ins_pipe(ialu_reg);
10320 %}
10321
10322 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10323 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10324 match(Set dst (CountTrailingZerosI src));
10325 effect(TEMP dst, KILL cr);
10326
10327 // return popc(~x & (x - 1));
10328 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10329 "ANDN $dst,$src,$dst\n\t"
10330 "SRL $dst,R_G0,$dst\n\t"
10331 "POPC $dst,$dst" %}
10332 ins_encode %{
10333 Register Rdst = $dst$$Register;
10334 Register Rsrc = $src$$Register;
10335 __ sub(Rsrc, 1, Rdst);
10336 __ andn(Rdst, Rsrc, Rdst);
10337 __ srl(Rdst, G0, Rdst);
10338 __ popc(Rdst, Rdst);
10339 %}
10340 ins_pipe(ialu_reg);
10341 %}
10342
10343 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10344 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10345 match(Set dst (CountTrailingZerosL src));
10346 effect(TEMP dst, KILL cr);
10347
10348 // return popc(~x & (x - 1));
10349 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10350 "ANDN $dst,$src,$dst\n\t"
10351 "POPC $dst,$dst" %}
10352 ins_encode %{
10353 Register Rdst = $dst$$Register;
10354 Register Rsrc = $src$$Register;
10355 __ sub(Rsrc, 1, Rdst);
10356 __ andn(Rdst, Rsrc, Rdst);
10357 __ popc(Rdst, Rdst);
10358 %}
10359 ins_pipe(ialu_reg);
10360 %}
10361
10362
10363 //---------- Population Count Instructions -------------------------------------
10364
10365 instruct popCountI(iRegIsafe dst, iRegI src) %{
10366 predicate(UsePopCountInstruction);
10367 match(Set dst (PopCountI src));
10368
10369 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10370 "POPC $dst, $dst" %}
10371 ins_encode %{
10372 __ srl($src$$Register, G0, $dst$$Register);
10373 __ popc($dst$$Register, $dst$$Register);
10374 %}
10375 ins_pipe(ialu_reg);
10376 %}
10377
10378 // Note: Long.bitCount(long) returns an int.
10379 instruct popCountL(iRegIsafe dst, iRegL src) %{
10380 predicate(UsePopCountInstruction);
10381 match(Set dst (PopCountL src));
10382
10383 format %{ "POPC $src, $dst" %}
10384 ins_encode %{
10385 __ popc($src$$Register, $dst$$Register);
10386 %}
10387 ins_pipe(ialu_reg);
10388 %}
10389
10390
10391 // ============================================================================
10392 //------------Bytes reverse--------------------------------------------------
10393
10394 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10395 match(Set dst (ReverseBytesI src));
10396
10397 // Op cost is artificially doubled to make sure that load or store
10398 // instructions are preferred over this one which requires a spill
10399 // onto a stack slot.
10400 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10401 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10402
10403 ins_encode %{
10404 __ set($src$$disp + STACK_BIAS, O7);
10405 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10406 %}
10407 ins_pipe( iload_mem );
10408 %}
10409
10410 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10411 match(Set dst (ReverseBytesL src));
10412
10413 // Op cost is artificially doubled to make sure that load or store
10414 // instructions are preferred over this one which requires a spill
10415 // onto a stack slot.
10416 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10417 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10418
10419 ins_encode %{
10420 __ set($src$$disp + STACK_BIAS, O7);
10421 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10422 %}
10423 ins_pipe( iload_mem );
10424 %}
10425
10426 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10427 match(Set dst (ReverseBytesUS src));
10428
10429 // Op cost is artificially doubled to make sure that load or store
10430 // instructions are preferred over this one which requires a spill
10431 // onto a stack slot.
10432 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10433 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10434
10435 ins_encode %{
10436 // the value was spilled as an int so bias the load
10437 __ set($src$$disp + STACK_BIAS + 2, O7);
10438 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10439 %}
10440 ins_pipe( iload_mem );
10441 %}
10442
10443 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10444 match(Set dst (ReverseBytesS src));
10445
10446 // Op cost is artificially doubled to make sure that load or store
10447 // instructions are preferred over this one which requires a spill
10448 // onto a stack slot.
10449 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10450 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10451
10452 ins_encode %{
10453 // the value was spilled as an int so bias the load
10454 __ set($src$$disp + STACK_BIAS + 2, O7);
10455 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10456 %}
10457 ins_pipe( iload_mem );
10458 %}
10459
10460 // Load Integer reversed byte order
10461 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10462 match(Set dst (ReverseBytesI (LoadI src)));
10463
10464 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10465 size(4);
10466 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10467
10468 ins_encode %{
10469 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10470 %}
10471 ins_pipe(iload_mem);
10472 %}
10473
10474 // Load Long - aligned and reversed
10475 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10476 match(Set dst (ReverseBytesL (LoadL src)));
10477
10478 ins_cost(MEMORY_REF_COST);
10479 size(4);
10480 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10481
10482 ins_encode %{
10483 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10484 %}
10485 ins_pipe(iload_mem);
10486 %}
10487
10488 // Load unsigned short / char reversed byte order
10489 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10490 match(Set dst (ReverseBytesUS (LoadUS src)));
10491
10492 ins_cost(MEMORY_REF_COST);
10493 size(4);
10494 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10495
10496 ins_encode %{
10497 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10498 %}
10499 ins_pipe(iload_mem);
10500 %}
10501
10502 // Load short reversed byte order
10503 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10504 match(Set dst (ReverseBytesS (LoadS src)));
10505
10506 ins_cost(MEMORY_REF_COST);
10507 size(4);
10508 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10509
10510 ins_encode %{
10511 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10512 %}
10513 ins_pipe(iload_mem);
10514 %}
10515
10516 // Store Integer reversed byte order
10517 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10518 match(Set dst (StoreI dst (ReverseBytesI src)));
10519
10520 ins_cost(MEMORY_REF_COST);
10521 size(4);
10522 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10523
10524 ins_encode %{
10525 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10526 %}
10527 ins_pipe(istore_mem_reg);
10528 %}
10529
10530 // Store Long reversed byte order
10531 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10532 match(Set dst (StoreL dst (ReverseBytesL src)));
10533
10534 ins_cost(MEMORY_REF_COST);
10535 size(4);
10536 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10537
10538 ins_encode %{
10539 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10540 %}
10541 ins_pipe(istore_mem_reg);
10542 %}
10543
10544 // Store unsighed short/char reversed byte order
10545 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10546 match(Set dst (StoreC dst (ReverseBytesUS src)));
10547
10548 ins_cost(MEMORY_REF_COST);
10549 size(4);
10550 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10551
10552 ins_encode %{
10553 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10554 %}
10555 ins_pipe(istore_mem_reg);
10556 %}
10557
10558 // Store short reversed byte order
10559 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10560 match(Set dst (StoreC dst (ReverseBytesS src)));
10561
10562 ins_cost(MEMORY_REF_COST);
10563 size(4);
10564 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10565
10566 ins_encode %{
10567 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10568 %}
10569 ins_pipe(istore_mem_reg);
10570 %}
10571
10572 // ====================VECTOR INSTRUCTIONS=====================================
10573
10574 // Load Aligned Packed values into a Double Register
10575 instruct loadV8(regD dst, memory mem) %{
10576 predicate(n->as_LoadVector()->memory_size() == 8);
10577 match(Set dst (LoadVector mem));
10578 ins_cost(MEMORY_REF_COST);
10579 size(4);
10580 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10581 ins_encode %{
10582 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10583 %}
10584 ins_pipe(floadD_mem);
10585 %}
10586
10587 // Store Vector in Double register to memory
10588 instruct storeV8(memory mem, regD src) %{
10589 predicate(n->as_StoreVector()->memory_size() == 8);
10590 match(Set mem (StoreVector mem src));
10591 ins_cost(MEMORY_REF_COST);
10592 size(4);
10593 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10594 ins_encode %{
10595 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10596 %}
10597 ins_pipe(fstoreD_mem_reg);
10598 %}
10599
10600 // Store Zero into vector in memory
10601 instruct storeV8B_zero(memory mem, immI0 zero) %{
10602 predicate(n->as_StoreVector()->memory_size() == 8);
10603 match(Set mem (StoreVector mem (ReplicateB zero)));
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10607 ins_encode %{
10608 __ stx(G0, $mem$$Address);
10609 %}
10610 ins_pipe(fstoreD_mem_zero);
10611 %}
10612
10613 instruct storeV4S_zero(memory mem, immI0 zero) %{
10614 predicate(n->as_StoreVector()->memory_size() == 8);
10615 match(Set mem (StoreVector mem (ReplicateS zero)));
10616 ins_cost(MEMORY_REF_COST);
10617 size(4);
10618 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10619 ins_encode %{
10620 __ stx(G0, $mem$$Address);
10621 %}
10622 ins_pipe(fstoreD_mem_zero);
10623 %}
10624
10625 instruct storeV2I_zero(memory mem, immI0 zero) %{
10626 predicate(n->as_StoreVector()->memory_size() == 8);
10627 match(Set mem (StoreVector mem (ReplicateI zero)));
10628 ins_cost(MEMORY_REF_COST);
10629 size(4);
10630 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10631 ins_encode %{
10632 __ stx(G0, $mem$$Address);
10633 %}
10634 ins_pipe(fstoreD_mem_zero);
10635 %}
10636
10637 instruct storeV2F_zero(memory mem, immF0 zero) %{
10638 predicate(n->as_StoreVector()->memory_size() == 8);
10639 match(Set mem (StoreVector mem (ReplicateF zero)));
10640 ins_cost(MEMORY_REF_COST);
10641 size(4);
10642 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10643 ins_encode %{
10644 __ stx(G0, $mem$$Address);
10645 %}
10646 ins_pipe(fstoreD_mem_zero);
10647 %}
10648
10649 // Replicate scalar to packed byte values into Double register
10650 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10651 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10652 match(Set dst (ReplicateB src));
10653 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10654 format %{ "SLLX $src,56,$tmp\n\t"
10655 "SRLX $tmp, 8,$tmp2\n\t"
10656 "OR $tmp,$tmp2,$tmp\n\t"
10657 "SRLX $tmp,16,$tmp2\n\t"
10658 "OR $tmp,$tmp2,$tmp\n\t"
10659 "SRLX $tmp,32,$tmp2\n\t"
10660 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10661 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10662 ins_encode %{
10663 Register Rsrc = $src$$Register;
10664 Register Rtmp = $tmp$$Register;
10665 Register Rtmp2 = $tmp2$$Register;
10666 __ sllx(Rsrc, 56, Rtmp);
10667 __ srlx(Rtmp, 8, Rtmp2);
10668 __ or3 (Rtmp, Rtmp2, Rtmp);
10669 __ srlx(Rtmp, 16, Rtmp2);
10670 __ or3 (Rtmp, Rtmp2, Rtmp);
10671 __ srlx(Rtmp, 32, Rtmp2);
10672 __ or3 (Rtmp, Rtmp2, Rtmp);
10673 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10674 %}
10675 ins_pipe(ialu_reg);
10676 %}
10677
10678 // Replicate scalar to packed byte values into Double stack
10679 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10680 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10681 match(Set dst (ReplicateB src));
10682 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10683 format %{ "SLLX $src,56,$tmp\n\t"
10684 "SRLX $tmp, 8,$tmp2\n\t"
10685 "OR $tmp,$tmp2,$tmp\n\t"
10686 "SRLX $tmp,16,$tmp2\n\t"
10687 "OR $tmp,$tmp2,$tmp\n\t"
10688 "SRLX $tmp,32,$tmp2\n\t"
10689 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10690 "STX $tmp,$dst\t! regL to stkD" %}
10691 ins_encode %{
10692 Register Rsrc = $src$$Register;
10693 Register Rtmp = $tmp$$Register;
10694 Register Rtmp2 = $tmp2$$Register;
10695 __ sllx(Rsrc, 56, Rtmp);
10696 __ srlx(Rtmp, 8, Rtmp2);
10697 __ or3 (Rtmp, Rtmp2, Rtmp);
10698 __ srlx(Rtmp, 16, Rtmp2);
10699 __ or3 (Rtmp, Rtmp2, Rtmp);
10700 __ srlx(Rtmp, 32, Rtmp2);
10701 __ or3 (Rtmp, Rtmp2, Rtmp);
10702 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10703 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10704 %}
10705 ins_pipe(ialu_reg);
10706 %}
10707
10708 // Replicate scalar constant to packed byte values in Double register
10709 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10710 predicate(n->as_Vector()->length() == 8);
10711 match(Set dst (ReplicateB con));
10712 effect(KILL tmp);
10713 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10714 ins_encode %{
10715 // XXX This is a quick fix for 6833573.
10716 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10717 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10718 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10719 %}
10720 ins_pipe(loadConFD);
10721 %}
10722
10723 // Replicate scalar to packed char/short values into Double register
10724 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10725 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10726 match(Set dst (ReplicateS src));
10727 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10728 format %{ "SLLX $src,48,$tmp\n\t"
10729 "SRLX $tmp,16,$tmp2\n\t"
10730 "OR $tmp,$tmp2,$tmp\n\t"
10731 "SRLX $tmp,32,$tmp2\n\t"
10732 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10733 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10734 ins_encode %{
10735 Register Rsrc = $src$$Register;
10736 Register Rtmp = $tmp$$Register;
10737 Register Rtmp2 = $tmp2$$Register;
10738 __ sllx(Rsrc, 48, Rtmp);
10739 __ srlx(Rtmp, 16, Rtmp2);
10740 __ or3 (Rtmp, Rtmp2, Rtmp);
10741 __ srlx(Rtmp, 32, Rtmp2);
10742 __ or3 (Rtmp, Rtmp2, Rtmp);
10743 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10744 %}
10745 ins_pipe(ialu_reg);
10746 %}
10747
10748 // Replicate scalar to packed char/short values into Double stack
10749 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10750 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10751 match(Set dst (ReplicateS src));
10752 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10753 format %{ "SLLX $src,48,$tmp\n\t"
10754 "SRLX $tmp,16,$tmp2\n\t"
10755 "OR $tmp,$tmp2,$tmp\n\t"
10756 "SRLX $tmp,32,$tmp2\n\t"
10757 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10758 "STX $tmp,$dst\t! regL to stkD" %}
10759 ins_encode %{
10760 Register Rsrc = $src$$Register;
10761 Register Rtmp = $tmp$$Register;
10762 Register Rtmp2 = $tmp2$$Register;
10763 __ sllx(Rsrc, 48, Rtmp);
10764 __ srlx(Rtmp, 16, Rtmp2);
10765 __ or3 (Rtmp, Rtmp2, Rtmp);
10766 __ srlx(Rtmp, 32, Rtmp2);
10767 __ or3 (Rtmp, Rtmp2, Rtmp);
10768 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10769 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10770 %}
10771 ins_pipe(ialu_reg);
10772 %}
10773
10774 // Replicate scalar constant to packed char/short values in Double register
10775 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10776 predicate(n->as_Vector()->length() == 4);
10777 match(Set dst (ReplicateS con));
10778 effect(KILL tmp);
10779 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10780 ins_encode %{
10781 // XXX This is a quick fix for 6833573.
10782 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10783 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10784 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10785 %}
10786 ins_pipe(loadConFD);
10787 %}
10788
10789 // Replicate scalar to packed int values into Double register
10790 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10791 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10792 match(Set dst (ReplicateI src));
10793 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10794 format %{ "SLLX $src,32,$tmp\n\t"
10795 "SRLX $tmp,32,$tmp2\n\t"
10796 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10797 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10798 ins_encode %{
10799 Register Rsrc = $src$$Register;
10800 Register Rtmp = $tmp$$Register;
10801 Register Rtmp2 = $tmp2$$Register;
10802 __ sllx(Rsrc, 32, Rtmp);
10803 __ srlx(Rtmp, 32, Rtmp2);
10804 __ or3 (Rtmp, Rtmp2, Rtmp);
10805 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10806 %}
10807 ins_pipe(ialu_reg);
10808 %}
10809
10810 // Replicate scalar to packed int values into Double stack
10811 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10812 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10813 match(Set dst (ReplicateI src));
10814 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10815 format %{ "SLLX $src,32,$tmp\n\t"
10816 "SRLX $tmp,32,$tmp2\n\t"
10817 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10818 "STX $tmp,$dst\t! regL to stkD" %}
10819 ins_encode %{
10820 Register Rsrc = $src$$Register;
10821 Register Rtmp = $tmp$$Register;
10822 Register Rtmp2 = $tmp2$$Register;
10823 __ sllx(Rsrc, 32, Rtmp);
10824 __ srlx(Rtmp, 32, Rtmp2);
10825 __ or3 (Rtmp, Rtmp2, Rtmp);
10826 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10827 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10828 %}
10829 ins_pipe(ialu_reg);
10830 %}
10831
10832 // Replicate scalar zero constant to packed int values in Double register
10833 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10834 predicate(n->as_Vector()->length() == 2);
10835 match(Set dst (ReplicateI con));
10836 effect(KILL tmp);
10837 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10838 ins_encode %{
10839 // XXX This is a quick fix for 6833573.
10840 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10841 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10842 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10843 %}
10844 ins_pipe(loadConFD);
10845 %}
10846
10847 // Replicate scalar to packed float values into Double stack
10848 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10849 predicate(n->as_Vector()->length() == 2);
10850 match(Set dst (ReplicateF src));
10851 ins_cost(MEMORY_REF_COST*2);
10852 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10853 "STF $src,$dst.lo" %}
10854 opcode(Assembler::stf_op3);
10855 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10856 ins_pipe(fstoreF_stk_reg);
10857 %}
10858
10859 // Replicate scalar zero constant to packed float values in Double register
10860 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10861 predicate(n->as_Vector()->length() == 2);
10862 match(Set dst (ReplicateF con));
10863 effect(KILL tmp);
10864 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10865 ins_encode %{
10866 // XXX This is a quick fix for 6833573.
10867 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10868 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10869 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10870 %}
10871 ins_pipe(loadConFD);
10872 %}
10873
10874 //----------PEEPHOLE RULES-----------------------------------------------------
10875 // These must follow all instruction definitions as they use the names
10876 // defined in the instructions definitions.
10877 //
10878 // peepmatch ( root_instr_name [preceding_instruction]* );
10879 //
10880 // peepconstraint %{
10881 // (instruction_number.operand_name relational_op instruction_number.operand_name
10882 // [, ...] );
10883 // // instruction numbers are zero-based using left to right order in peepmatch
10884 //
10885 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10886 // // provide an instruction_number.operand_name for each operand that appears
10887 // // in the replacement instruction's match rule
10888 //
10889 // ---------VM FLAGS---------------------------------------------------------
10890 //
10891 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10892 //
10893 // Each peephole rule is given an identifying number starting with zero and
10894 // increasing by one in the order seen by the parser. An individual peephole
10895 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10896 // on the command-line.
10897 //
10898 // ---------CURRENT LIMITATIONS----------------------------------------------
10899 //
10900 // Only match adjacent instructions in same basic block
10901 // Only equality constraints
10902 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10903 // Only one replacement instruction
10904 //
10905 // ---------EXAMPLE----------------------------------------------------------
10906 //
10907 // // pertinent parts of existing instructions in architecture description
10908 // instruct movI(eRegI dst, eRegI src) %{
10909 // match(Set dst (CopyI src));
10910 // %}
10911 //
10912 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10913 // match(Set dst (AddI dst src));
10914 // effect(KILL cr);
10915 // %}
10916 //
10917 // // Change (inc mov) to lea
10918 // peephole %{
10919 // // increment preceeded by register-register move
10920 // peepmatch ( incI_eReg movI );
10921 // // require that the destination register of the increment
10922 // // match the destination register of the move
10923 // peepconstraint ( 0.dst == 1.dst );
10924 // // construct a replacement instruction that sets
10925 // // the destination to ( move's source register + one )
10926 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10927 // %}
10928 //
10929
10930 // // Change load of spilled value to only a spill
10931 // instruct storeI(memory mem, eRegI src) %{
10932 // match(Set mem (StoreI mem src));
10933 // %}
10934 //
10935 // instruct loadI(eRegI dst, memory mem) %{
10936 // match(Set dst (LoadI mem));
10937 // %}
10938 //
10939 // peephole %{
10940 // peepmatch ( loadI storeI );
10941 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10942 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10943 // %}
10944
10945 //----------SMARTSPILL RULES---------------------------------------------------
10946 // These must follow all instruction definitions as they use the names
10947 // defined in the instructions definitions.
10948 //
10949 // SPARC will probably not have any of these rules due to RISC instruction set.
10950
10951 //----------PIPELINE-----------------------------------------------------------
10952 // Rules which define the behavior of the target architectures pipeline.