1636 }
1637
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1642
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1651
1652 const RegMask Matcher::mathExactI_result_proj_mask() {
1653 return INT_RAX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::mathExactI_flags_proj_mask() {
1657 return INT_FLAGS_mask();
1658 }
1659
1660 %}
1661
1662 //----------ENCODING BLOCK-----------------------------------------------------
1663 // This block specifies the encoding classes used by the compiler to
1664 // output byte streams. Encoding classes are parameterized macros
1665 // used by Machine Instruction Nodes in order to generate the bit
1666 // encoding of the instruction. Operands specify their base encoding
1667 // interface with the interface keyword. There are currently
1668 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1669 // COND_INTER. REG_INTER causes an operand to generate a function
1670 // which returns its register number when queried. CONST_INTER causes
1671 // an operand to generate a function which returns the value of the
1672 // constant when queried. MEMORY_INTER causes an operand to generate
1673 // four functions which return the Base Register, the Index Register,
1674 // the Scale Value, and the Offset Value of the operand when queried.
1675 // COND_INTER causes an operand to generate six functions which return
6945
6946 format %{ "addl $dst, $src\t# addExact int" %}
6947 ins_encode %{
6948 __ addl($dst$$Register, $src$$Register);
6949 %}
6950 ins_pipe(ialu_reg_reg);
6951 %}
6952
6953 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6954 %{
6955 match(AddExactI dst src);
6956 effect(DEF cr);
6957
6958 format %{ "addl $dst, $src\t# addExact int" %}
6959 ins_encode %{
6960 __ addl($dst$$Register, $src$$constant);
6961 %}
6962 ins_pipe(ialu_reg_reg);
6963 %}
6964
6965 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6966 %{
6967 match(Set dst (AddI dst src));
6968 effect(KILL cr);
6969
6970 format %{ "addl $dst, $src\t# int" %}
6971 opcode(0x03);
6972 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6973 ins_pipe(ialu_reg_reg);
6974 %}
6975
6976 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6977 %{
6978 match(Set dst (AddI dst src));
6979 effect(KILL cr);
6980
6981 format %{ "addl $dst, $src\t# int" %}
6982 opcode(0x81, 0x00); /* /0 id */
6983 ins_encode(OpcSErm(dst, src), Con8or32(src));
6984 ins_pipe( ialu_reg );
7557
7558 ins_cost(150);
7559 format %{ "subl $dst, $src\t# int" %}
7560 opcode(0x29); /* Opcode 29 /r */
7561 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7562 ins_pipe(ialu_mem_reg);
7563 %}
7564
7565 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7566 %{
7567 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7568 effect(KILL cr);
7569
7570 ins_cost(125); // XXX
7571 format %{ "subl $dst, $src\t# int" %}
7572 opcode(0x81); /* Opcode 81 /5 id */
7573 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7574 ins_pipe(ialu_mem_imm);
7575 %}
7576
7577 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7578 %{
7579 match(Set dst (SubL dst src));
7580 effect(KILL cr);
7581
7582 format %{ "subq $dst, $src\t# long" %}
7583 opcode(0x2B);
7584 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7585 ins_pipe(ialu_reg_reg);
7586 %}
7587
7588 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7589 %{
7590 match(Set dst (SubL dst src));
7591 effect(KILL cr);
7592
7593 format %{ "subq $dst, $src\t# long" %}
7594 opcode(0x81, 0x05); /* Opcode 81 /5 */
7595 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7596 ins_pipe(ialu_reg);
7673 match(Set dst (SubL zero dst));
7674 effect(KILL cr);
7675
7676 format %{ "negq $dst\t# long" %}
7677 opcode(0xF7, 0x03); // Opcode F7 /3
7678 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7679 ins_pipe(ialu_reg);
7680 %}
7681
7682 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7683 %{
7684 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7685 effect(KILL cr);
7686
7687 format %{ "negq $dst\t# long" %}
7688 opcode(0xF7, 0x03); // Opcode F7 /3
7689 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7690 ins_pipe(ialu_reg);
7691 %}
7692
7693
7694 //----------Multiplication/Division Instructions-------------------------------
7695 // Integer Multiplication Instructions
7696 // Multiply Register
7697
7698 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7699 %{
7700 match(Set dst (MulI dst src));
7701 effect(KILL cr);
7702
7703 ins_cost(300);
7704 format %{ "imull $dst, $src\t# int" %}
7705 opcode(0x0F, 0xAF);
7706 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7707 ins_pipe(ialu_reg_reg_alu0);
7708 %}
7709
7710 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7711 %{
7712 match(Set dst (MulI src imm));
7788 effect(KILL cr);
7789
7790 ins_cost(300);
7791 format %{ "imulq $dst, $src, $imm\t# long" %}
7792 opcode(0x69); /* 69 /r id */
7793 ins_encode(REX_reg_mem_wide(dst, src),
7794 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7795 ins_pipe(ialu_reg_mem_alu0);
7796 %}
7797
7798 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7799 %{
7800 match(Set dst (MulHiL src rax));
7801 effect(USE_KILL rax, KILL cr);
7802
7803 ins_cost(300);
7804 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7805 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7806 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7807 ins_pipe(ialu_reg_reg_alu0);
7808 %}
7809
7810 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7811 rFlagsReg cr)
7812 %{
7813 match(Set rax (DivI rax div));
7814 effect(KILL rdx, KILL cr);
7815
7816 ins_cost(30*100+10*100); // XXX
7817 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7818 "jne,s normal\n\t"
7819 "xorl rdx, rdx\n\t"
7820 "cmpl $div, -1\n\t"
7821 "je,s done\n"
7822 "normal: cdql\n\t"
7823 "idivl $div\n"
7824 "done:" %}
7825 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7826 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7827 ins_pipe(ialu_reg_reg_alu0);
|
1636 }
1637
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1642
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1651
1652 const RegMask Matcher::mathExactI_result_proj_mask() {
1653 return INT_RAX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::mathExactL_result_proj_mask() {
1657 return LONG_RAX_REG_mask();
1658 }
1659
1660 const RegMask Matcher::mathExactI_flags_proj_mask() {
1661 return INT_FLAGS_mask();
1662 }
1663
1664 %}
1665
1666 //----------ENCODING BLOCK-----------------------------------------------------
1667 // This block specifies the encoding classes used by the compiler to
1668 // output byte streams. Encoding classes are parameterized macros
1669 // used by Machine Instruction Nodes in order to generate the bit
1670 // encoding of the instruction. Operands specify their base encoding
1671 // interface with the interface keyword. There are currently
1672 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1673 // COND_INTER. REG_INTER causes an operand to generate a function
1674 // which returns its register number when queried. CONST_INTER causes
1675 // an operand to generate a function which returns the value of the
1676 // constant when queried. MEMORY_INTER causes an operand to generate
1677 // four functions which return the Base Register, the Index Register,
1678 // the Scale Value, and the Offset Value of the operand when queried.
1679 // COND_INTER causes an operand to generate six functions which return
6949
6950 format %{ "addl $dst, $src\t# addExact int" %}
6951 ins_encode %{
6952 __ addl($dst$$Register, $src$$Register);
6953 %}
6954 ins_pipe(ialu_reg_reg);
6955 %}
6956
6957 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6958 %{
6959 match(AddExactI dst src);
6960 effect(DEF cr);
6961
6962 format %{ "addl $dst, $src\t# addExact int" %}
6963 ins_encode %{
6964 __ addl($dst$$Register, $src$$constant);
6965 %}
6966 ins_pipe(ialu_reg_reg);
6967 %}
6968
6969 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6970 %{
6971 match(AddExactI dst (LoadI src));
6972 effect(DEF cr);
6973
6974 ins_cost(125); // XXX
6975 format %{ "addl $dst, $src\t# addExact int" %}
6976 ins_encode %{
6977 __ addl($dst$$Register, $src$$Address);
6978 %}
6979
6980 ins_pipe(ialu_reg_mem);
6981 %}
6982
6983 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
6984 %{
6985 match(AddExactL dst src);
6986 effect(DEF cr);
6987
6988 format %{ "addq $dst, $src\t# addExact long" %}
6989 ins_encode %{
6990 __ addq($dst$$Register, $src$$Register);
6991 %}
6992 ins_pipe(ialu_reg_reg);
6993 %}
6994
6995 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
6996 %{
6997 match(AddExactL dst src);
6998 effect(DEF cr);
6999
7000 format %{ "addq $dst, $src\t# addExact long" %}
7001 ins_encode %{
7002 __ addq($dst$$Register, $src$$constant);
7003 %}
7004 ins_pipe(ialu_reg_reg);
7005 %}
7006
7007 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7008 %{
7009 match(AddExactL dst (LoadL src));
7010 effect(DEF cr);
7011
7012 ins_cost(125); // XXX
7013 format %{ "addq $dst, $src\t# addExact long" %}
7014 ins_encode %{
7015 __ addq($dst$$Register, $src$$Address);
7016 %}
7017
7018 ins_pipe(ialu_reg_mem);
7019 %}
7020
7021 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7022 %{
7023 match(Set dst (AddI dst src));
7024 effect(KILL cr);
7025
7026 format %{ "addl $dst, $src\t# int" %}
7027 opcode(0x03);
7028 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7029 ins_pipe(ialu_reg_reg);
7030 %}
7031
7032 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7033 %{
7034 match(Set dst (AddI dst src));
7035 effect(KILL cr);
7036
7037 format %{ "addl $dst, $src\t# int" %}
7038 opcode(0x81, 0x00); /* /0 id */
7039 ins_encode(OpcSErm(dst, src), Con8or32(src));
7040 ins_pipe( ialu_reg );
7613
7614 ins_cost(150);
7615 format %{ "subl $dst, $src\t# int" %}
7616 opcode(0x29); /* Opcode 29 /r */
7617 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7618 ins_pipe(ialu_mem_reg);
7619 %}
7620
7621 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7622 %{
7623 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7624 effect(KILL cr);
7625
7626 ins_cost(125); // XXX
7627 format %{ "subl $dst, $src\t# int" %}
7628 opcode(0x81); /* Opcode 81 /5 id */
7629 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7630 ins_pipe(ialu_mem_imm);
7631 %}
7632
7633 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7634 %{
7635 match(SubExactI dst src);
7636 effect(DEF cr);
7637
7638 format %{ "subl $dst, $src\t# subExact int" %}
7639 ins_encode %{
7640 __ subl($dst$$Register, $src$$Register);
7641 %}
7642 ins_pipe(ialu_reg_reg);
7643 %}
7644
7645 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7646 %{
7647 match(SubExactI dst src);
7648 effect(DEF cr);
7649
7650 format %{ "subl $dst, $src\t# subExact int" %}
7651 ins_encode %{
7652 __ subl($dst$$Register, $src$$constant);
7653 %}
7654 ins_pipe(ialu_reg_reg);
7655 %}
7656
7657 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7658 %{
7659 match(SubExactI dst (LoadI src));
7660 effect(DEF cr);
7661
7662 ins_cost(125);
7663 format %{ "subl $dst, $src\t# subExact int" %}
7664 ins_encode %{
7665 __ subl($dst$$Register, $src$$Address);
7666 %}
7667 ins_pipe(ialu_reg_mem);
7668 %}
7669
7670 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7671 %{
7672 match(SubExactL dst src);
7673 effect(DEF cr);
7674
7675 format %{ "subq $dst, $src\t# subExact long" %}
7676 ins_encode %{
7677 __ subq($dst$$Register, $src$$Register);
7678 %}
7679 ins_pipe(ialu_reg_reg);
7680 %}
7681
7682 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7683 %{
7684 match(SubExactL dst (LoadL src));
7685 effect(DEF cr);
7686
7687 format %{ "subq $dst, $src\t# subExact long" %}
7688 ins_encode %{
7689 __ subq($dst$$Register, $src$$constant);
7690 %}
7691 ins_pipe(ialu_reg_reg);
7692 %}
7693
7694 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7695 %{
7696 match(SubExactI dst src);
7697 effect(DEF cr);
7698
7699 ins_cost(125);
7700 format %{ "subq $dst, $src\t# subExact long" %}
7701 ins_encode %{
7702 __ subq($dst$$Register, $src$$Address);
7703 %}
7704 ins_pipe(ialu_reg_mem);
7705 %}
7706
7707 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7708 %{
7709 match(Set dst (SubL dst src));
7710 effect(KILL cr);
7711
7712 format %{ "subq $dst, $src\t# long" %}
7713 opcode(0x2B);
7714 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7715 ins_pipe(ialu_reg_reg);
7716 %}
7717
7718 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7719 %{
7720 match(Set dst (SubL dst src));
7721 effect(KILL cr);
7722
7723 format %{ "subq $dst, $src\t# long" %}
7724 opcode(0x81, 0x05); /* Opcode 81 /5 */
7725 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7726 ins_pipe(ialu_reg);
7803 match(Set dst (SubL zero dst));
7804 effect(KILL cr);
7805
7806 format %{ "negq $dst\t# long" %}
7807 opcode(0xF7, 0x03); // Opcode F7 /3
7808 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7809 ins_pipe(ialu_reg);
7810 %}
7811
7812 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7813 %{
7814 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7815 effect(KILL cr);
7816
7817 format %{ "negq $dst\t# long" %}
7818 opcode(0xF7, 0x03); // Opcode F7 /3
7819 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7820 ins_pipe(ialu_reg);
7821 %}
7822
7823 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7824 %{
7825 match(NegExactI dst);
7826 effect(KILL cr);
7827
7828 format %{ "negl $dst\t# negExact int" %}
7829 ins_encode %{
7830 __ negl($dst$$Register);
7831 %}
7832 ins_pipe(ialu_reg);
7833 %}
7834
7835 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7836 %{
7837 match(NegExactL dst);
7838 effect(KILL cr);
7839
7840 format %{ "negq $dst\t# negExact long" %}
7841 ins_encode %{
7842 __ negq($dst$$Register);
7843 %}
7844 ins_pipe(ialu_reg);
7845 %}
7846
7847
7848 //----------Multiplication/Division Instructions-------------------------------
7849 // Integer Multiplication Instructions
7850 // Multiply Register
7851
7852 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7853 %{
7854 match(Set dst (MulI dst src));
7855 effect(KILL cr);
7856
7857 ins_cost(300);
7858 format %{ "imull $dst, $src\t# int" %}
7859 opcode(0x0F, 0xAF);
7860 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7861 ins_pipe(ialu_reg_reg_alu0);
7862 %}
7863
7864 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7865 %{
7866 match(Set dst (MulI src imm));
7942 effect(KILL cr);
7943
7944 ins_cost(300);
7945 format %{ "imulq $dst, $src, $imm\t# long" %}
7946 opcode(0x69); /* 69 /r id */
7947 ins_encode(REX_reg_mem_wide(dst, src),
7948 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7949 ins_pipe(ialu_reg_mem_alu0);
7950 %}
7951
7952 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7953 %{
7954 match(Set dst (MulHiL src rax));
7955 effect(USE_KILL rax, KILL cr);
7956
7957 ins_cost(300);
7958 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7959 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7960 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7961 ins_pipe(ialu_reg_reg_alu0);
7962 %}
7963
7964
7965 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7966 %{
7967 match(MulExactI dst src);
7968 effect(DEF cr);
7969
7970 ins_cost(300);
7971 format %{ "imull $dst, $src\t# mulExact int" %}
7972 ins_encode %{
7973 __ imull($dst$$Register, $src$$Register);
7974 %}
7975 ins_pipe(ialu_reg_reg_alu0);
7976 %}
7977
7978
7979 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
7980 %{
7981 match(MulExactI src imm);
7982 effect(DEF cr);
7983
7984 ins_cost(300);
7985 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
7986 ins_encode %{
7987 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7988 %}
7989 ins_pipe(ialu_reg_reg_alu0);
7990 %}
7991
7992 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7993 %{
7994 match(MulExactI dst (LoadI src));
7995 effect(DEF cr);
7996
7997 ins_cost(350);
7998 format %{ "imull $dst, $src\t# mulExact int" %}
7999 ins_encode %{
8000 __ imull($dst$$Register, $src$$Address);
8001 %}
8002 ins_pipe(ialu_reg_mem_alu0);
8003 %}
8004
8005 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
8006 %{
8007 match(MulExactL dst src);
8008 effect(DEF cr);
8009
8010 ins_cost(300);
8011 format %{ "imulq $dst, $src\t# mulExact long" %}
8012 ins_encode %{
8013 __ imulq($dst$$Register, $src$$Register);
8014 %}
8015 ins_pipe(ialu_reg_reg_alu0);
8016 %}
8017
8018 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8019 %{
8020 match(MulExactL src imm);
8021 effect(DEF cr);
8022
8023 ins_cost(300);
8024 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
8025 ins_encode %{
8026 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8027 %}
8028 ins_pipe(ialu_reg_reg_alu0);
8029 %}
8030
8031 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
8032 %{
8033 match(MulExactL dst (LoadL src));
8034 effect(DEF cr);
8035
8036 ins_cost(350);
8037 format %{ "imulq $dst, $src\t# mulExact long" %}
8038 ins_encode %{
8039 __ imulq($dst$$Register, $src$$Address);
8040 %}
8041 ins_pipe(ialu_reg_mem_alu0);
8042 %}
8043
8044 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8045 rFlagsReg cr)
8046 %{
8047 match(Set rax (DivI rax div));
8048 effect(KILL rdx, KILL cr);
8049
8050 ins_cost(30*100+10*100); // XXX
8051 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8052 "jne,s normal\n\t"
8053 "xorl rdx, rdx\n\t"
8054 "cmpl $div, -1\n\t"
8055 "je,s done\n"
8056 "normal: cdql\n\t"
8057 "idivl $div\n"
8058 "done:" %}
8059 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8060 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8061 ins_pipe(ialu_reg_reg_alu0);
|