1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 const RegMask Matcher::mathExactI_result_proj_mask() {
1546 return EAX_REG_mask();
1547 }
1548
1549 const RegMask Matcher::mathExactL_result_proj_mask() {
1550 ShouldNotReachHere();
1551 return RegMask();
1552 }
1553
1554 const RegMask Matcher::mathExactI_flags_proj_mask() {
1555 return INT_FLAGS_mask();
1556 }
1557
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560 int opc = n->Opcode();
1561 if (opc == Op_AndL) {
1562 Node* o2 = n->in(2);
1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1564 return true;
1565 }
1566 }
1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568 return true;
1569 }
1570 return false;
1571 }
1572
1573 %}
1574
1575 //----------ENCODING BLOCK-----------------------------------------------------
1576 // This block specifies the encoding classes used by the compiler to output
1577 // byte streams. Encoding classes generate functions which are called by
7528 ins_cost(200);
7529 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7530 "CMOV$cop $dst.hi,$src.hi" %}
7531 opcode(0x0F,0x40);
7532 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7533 ins_pipe( pipe_cmov_reg_long );
7534 %}
7535
7536 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7537 predicate(VM_Version::supports_cmov() );
7538 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7539 ins_cost(200);
7540 expand %{
7541 cmovL_regU(cop, cr, dst, src);
7542 %}
7543 %}
7544
7545 //----------Arithmetic Instructions--------------------------------------------
7546 //----------Addition Instructions----------------------------------------------
7547
7548 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7549 %{
7550 match(AddExactI dst src);
7551 effect(DEF cr);
7552
7553 format %{ "ADD $dst, $src\t# addExact int" %}
7554 ins_encode %{
7555 __ addl($dst$$Register, $src$$Register);
7556 %}
7557 ins_pipe(ialu_reg_reg);
7558 %}
7559
7560 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7561 %{
7562 match(AddExactI dst src);
7563 effect(DEF cr);
7564
7565 format %{ "ADD $dst, $src\t# addExact int" %}
7566 ins_encode %{
7567 __ addl($dst$$Register, $src$$constant);
7568 %}
7569 ins_pipe(ialu_reg_reg);
7570 %}
7571
7572 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7573 %{
7574 match(AddExactI dst (LoadI src));
7575 effect(DEF cr);
7576
7577 ins_cost(125);
7578 format %{ "ADD $dst,$src\t# addExact int" %}
7579 ins_encode %{
7580 __ addl($dst$$Register, $src$$Address);
7581 %}
7582 ins_pipe( ialu_reg_mem );
7583 %}
7584
7585
7586 // Integer Addition Instructions
7587 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7588 match(Set dst (AddI dst src));
7589 effect(KILL cr);
7590
7591 size(2);
7592 format %{ "ADD $dst,$src" %}
7593 opcode(0x03);
7594 ins_encode( OpcP, RegReg( dst, src) );
7595 ins_pipe( ialu_reg_reg );
7596 %}
7597
7598 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7599 match(Set dst (AddI dst src));
7600 effect(KILL cr);
7601
7602 format %{ "ADD $dst,$src" %}
7603 opcode(0x81, 0x00); /* /0 id */
7604 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7605 ins_pipe( ialu_reg );
7875 instruct xchgI( memory mem, rRegI newval) %{
7876 match(Set newval (GetAndSetI mem newval));
7877 format %{ "XCHGL $newval,[$mem]" %}
7878 ins_encode %{
7879 __ xchgl($newval$$Register, $mem$$Address);
7880 %}
7881 ins_pipe( pipe_cmpxchg );
7882 %}
7883
7884 instruct xchgP( memory mem, pRegP newval) %{
7885 match(Set newval (GetAndSetP mem newval));
7886 format %{ "XCHGL $newval,[$mem]" %}
7887 ins_encode %{
7888 __ xchgl($newval$$Register, $mem$$Address);
7889 %}
7890 ins_pipe( pipe_cmpxchg );
7891 %}
7892
7893 //----------Subtraction Instructions-------------------------------------------
7894
7895 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7896 %{
7897 match(SubExactI dst src);
7898 effect(DEF cr);
7899
7900 format %{ "SUB $dst, $src\t# subExact int" %}
7901 ins_encode %{
7902 __ subl($dst$$Register, $src$$Register);
7903 %}
7904 ins_pipe(ialu_reg_reg);
7905 %}
7906
7907 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7908 %{
7909 match(SubExactI dst src);
7910 effect(DEF cr);
7911
7912 format %{ "SUB $dst, $src\t# subExact int" %}
7913 ins_encode %{
7914 __ subl($dst$$Register, $src$$constant);
7915 %}
7916 ins_pipe(ialu_reg_reg);
7917 %}
7918
7919 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7920 %{
7921 match(SubExactI dst (LoadI src));
7922 effect(DEF cr);
7923
7924 ins_cost(125);
7925 format %{ "SUB $dst,$src\t# subExact int" %}
7926 ins_encode %{
7927 __ subl($dst$$Register, $src$$Address);
7928 %}
7929 ins_pipe( ialu_reg_mem );
7930 %}
7931
7932 // Integer Subtraction Instructions
7933 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7934 match(Set dst (SubI dst src));
7935 effect(KILL cr);
7936
7937 size(2);
7938 format %{ "SUB $dst,$src" %}
7939 opcode(0x2B);
7940 ins_encode( OpcP, RegReg( dst, src) );
7941 ins_pipe( ialu_reg_reg );
7942 %}
7943
7944 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7945 match(Set dst (SubI dst src));
7946 effect(KILL cr);
7947
7948 format %{ "SUB $dst,$src" %}
7949 opcode(0x81,0x05); /* Opcode 81 /5 */
7950 // ins_encode( RegImm( dst, src) );
7951 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7980 effect(KILL cr);
7981
7982 size(2);
7983 format %{ "SUB $dst,$src" %}
7984 opcode(0x2B);
7985 ins_encode( OpcP, RegReg( dst, src) );
7986 ins_pipe( ialu_reg_reg );
7987 %}
7988
7989 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7990 match(Set dst (SubI zero dst));
7991 effect(KILL cr);
7992
7993 size(2);
7994 format %{ "NEG $dst" %}
7995 opcode(0xF7,0x03); // Opcode F7 /3
7996 ins_encode( OpcP, RegOpc( dst ) );
7997 ins_pipe( ialu_reg );
7998 %}
7999
8000 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
8001 match(NegExactI dst);
8002 effect(DEF cr);
8003
8004 format %{ "NEG $dst\t# negExact int"%}
8005 ins_encode %{
8006 __ negl($dst$$Register);
8007 %}
8008 ins_pipe(ialu_reg);
8009 %}
8010
8011 //----------Multiplication/Division Instructions-------------------------------
8012 // Integer Multiplication Instructions
8013 // Multiply Register
8014 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8015 match(Set dst (MulI dst src));
8016 effect(KILL cr);
8017
8018 size(3);
8019 ins_cost(300);
8020 format %{ "IMUL $dst,$src" %}
8021 opcode(0xAF, 0x0F);
8022 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8023 ins_pipe( ialu_reg_reg_alu0 );
8024 %}
8025
8026 // Multiply 32-bit Immediate
8027 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8028 match(Set dst (MulI src imm));
8029 effect(KILL cr);
8030
8202 %}
8203 ins_pipe( pipe_slow );
8204 %}
8205
8206 // Multiply Register Long by small constant
8207 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8208 match(Set dst (MulL dst src));
8209 effect(KILL cr, TEMP tmp);
8210 ins_cost(2*100+2*400);
8211 size(12);
8212 // Basic idea: lo(result) = lo(src * EAX)
8213 // hi(result) = hi(src * EAX) + lo(src * EDX)
8214 format %{ "IMUL $tmp,EDX,$src\n\t"
8215 "MOV EDX,$src\n\t"
8216 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8217 "ADD EDX,$tmp" %}
8218 ins_encode( long_multiply_con( dst, src, tmp ) );
8219 ins_pipe( pipe_slow );
8220 %}
8221
8222 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8223 %{
8224 match(MulExactI dst src);
8225 effect(DEF cr);
8226
8227 ins_cost(300);
8228 format %{ "IMUL $dst, $src\t# mulExact int" %}
8229 ins_encode %{
8230 __ imull($dst$$Register, $src$$Register);
8231 %}
8232 ins_pipe(ialu_reg_reg_alu0);
8233 %}
8234
8235 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8236 %{
8237 match(MulExactI src imm);
8238 effect(DEF cr);
8239
8240 ins_cost(300);
8241 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8242 ins_encode %{
8243 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8244 %}
8245 ins_pipe(ialu_reg_reg_alu0);
8246 %}
8247
8248 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8249 %{
8250 match(MulExactI dst (LoadI src));
8251 effect(DEF cr);
8252
8253 ins_cost(350);
8254 format %{ "IMUL $dst, $src\t# mulExact int" %}
8255 ins_encode %{
8256 __ imull($dst$$Register, $src$$Address);
8257 %}
8258 ins_pipe(ialu_reg_mem_alu0);
8259 %}
8260
8261
8262 // Integer DIV with Register
8263 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8264 match(Set rax (DivI rax div));
8265 effect(KILL rdx, KILL cr);
8266 size(26);
8267 ins_cost(30*100+10*100);
8268 format %{ "CMP EAX,0x80000000\n\t"
8269 "JNE,s normal\n\t"
8270 "XOR EDX,EDX\n\t"
8271 "CMP ECX,-1\n\t"
8272 "JE,s done\n"
8273 "normal: CDQ\n\t"
8274 "IDIV $div\n\t"
8275 "done:" %}
8276 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8277 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8278 ins_pipe( ialu_reg_reg_alu0 );
8279 %}
8280
8281 // Divide Register Long
9107 "XORL $y, $y\n"
9108 "done: " %}
9109 ins_encode %{
9110 Register Rp = $p$$Register;
9111 Register Rq = $q$$Register;
9112 Register Ry = $y$$Register;
9113 Label done;
9114 __ cmpl(Rp, Rq);
9115 __ jccb(Assembler::less, done);
9116 __ xorl(Ry, Ry);
9117 __ bind(done);
9118 %}
9119
9120 ins_pipe(pipe_cmplt);
9121 %}
9122
9123 /* If I enable this, I encourage spilling in the inner loop of compress.
9124 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9125 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9126 */
9127
9128 //----------Long Instructions------------------------------------------------
9129 // Add Long Register with Register
9130 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9131 match(Set dst (AddL dst src));
9132 effect(KILL cr);
9133 ins_cost(200);
9134 format %{ "ADD $dst.lo,$src.lo\n\t"
9135 "ADC $dst.hi,$src.hi" %}
9136 opcode(0x03, 0x13);
9137 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9138 ins_pipe( ialu_reg_reg_long );
9139 %}
9140
9141 // Add Long Register with Immediate
9142 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9143 match(Set dst (AddL dst src));
9144 effect(KILL cr);
9145 format %{ "ADD $dst.lo,$src.lo\n\t"
9146 "ADC $dst.hi,$src.hi" %}
|
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 // Returns true if the high 32 bits of the value is known to be zero.
1546 bool is_operand_hi32_zero(Node* n) {
1547 int opc = n->Opcode();
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1559
1560 %}
1561
1562 //----------ENCODING BLOCK-----------------------------------------------------
1563 // This block specifies the encoding classes used by the compiler to output
1564 // byte streams. Encoding classes generate functions which are called by
7515 ins_cost(200);
7516 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7517 "CMOV$cop $dst.hi,$src.hi" %}
7518 opcode(0x0F,0x40);
7519 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7520 ins_pipe( pipe_cmov_reg_long );
7521 %}
7522
7523 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7524 predicate(VM_Version::supports_cmov() );
7525 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7526 ins_cost(200);
7527 expand %{
7528 cmovL_regU(cop, cr, dst, src);
7529 %}
7530 %}
7531
7532 //----------Arithmetic Instructions--------------------------------------------
7533 //----------Addition Instructions----------------------------------------------
7534
7535 // Integer Addition Instructions
7536 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7537 match(Set dst (AddI dst src));
7538 effect(KILL cr);
7539
7540 size(2);
7541 format %{ "ADD $dst,$src" %}
7542 opcode(0x03);
7543 ins_encode( OpcP, RegReg( dst, src) );
7544 ins_pipe( ialu_reg_reg );
7545 %}
7546
7547 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7548 match(Set dst (AddI dst src));
7549 effect(KILL cr);
7550
7551 format %{ "ADD $dst,$src" %}
7552 opcode(0x81, 0x00); /* /0 id */
7553 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7554 ins_pipe( ialu_reg );
7824 instruct xchgI( memory mem, rRegI newval) %{
7825 match(Set newval (GetAndSetI mem newval));
7826 format %{ "XCHGL $newval,[$mem]" %}
7827 ins_encode %{
7828 __ xchgl($newval$$Register, $mem$$Address);
7829 %}
7830 ins_pipe( pipe_cmpxchg );
7831 %}
7832
7833 instruct xchgP( memory mem, pRegP newval) %{
7834 match(Set newval (GetAndSetP mem newval));
7835 format %{ "XCHGL $newval,[$mem]" %}
7836 ins_encode %{
7837 __ xchgl($newval$$Register, $mem$$Address);
7838 %}
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 //----------Subtraction Instructions-------------------------------------------
7843
7844 // Integer Subtraction Instructions
7845 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7846 match(Set dst (SubI dst src));
7847 effect(KILL cr);
7848
7849 size(2);
7850 format %{ "SUB $dst,$src" %}
7851 opcode(0x2B);
7852 ins_encode( OpcP, RegReg( dst, src) );
7853 ins_pipe( ialu_reg_reg );
7854 %}
7855
7856 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7857 match(Set dst (SubI dst src));
7858 effect(KILL cr);
7859
7860 format %{ "SUB $dst,$src" %}
7861 opcode(0x81,0x05); /* Opcode 81 /5 */
7862 // ins_encode( RegImm( dst, src) );
7863 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7892 effect(KILL cr);
7893
7894 size(2);
7895 format %{ "SUB $dst,$src" %}
7896 opcode(0x2B);
7897 ins_encode( OpcP, RegReg( dst, src) );
7898 ins_pipe( ialu_reg_reg );
7899 %}
7900
7901 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7902 match(Set dst (SubI zero dst));
7903 effect(KILL cr);
7904
7905 size(2);
7906 format %{ "NEG $dst" %}
7907 opcode(0xF7,0x03); // Opcode F7 /3
7908 ins_encode( OpcP, RegOpc( dst ) );
7909 ins_pipe( ialu_reg );
7910 %}
7911
7912 //----------Multiplication/Division Instructions-------------------------------
7913 // Integer Multiplication Instructions
7914 // Multiply Register
7915 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7916 match(Set dst (MulI dst src));
7917 effect(KILL cr);
7918
7919 size(3);
7920 ins_cost(300);
7921 format %{ "IMUL $dst,$src" %}
7922 opcode(0xAF, 0x0F);
7923 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7924 ins_pipe( ialu_reg_reg_alu0 );
7925 %}
7926
7927 // Multiply 32-bit Immediate
7928 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7929 match(Set dst (MulI src imm));
7930 effect(KILL cr);
7931
8103 %}
8104 ins_pipe( pipe_slow );
8105 %}
8106
8107 // Multiply Register Long by small constant
8108 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8109 match(Set dst (MulL dst src));
8110 effect(KILL cr, TEMP tmp);
8111 ins_cost(2*100+2*400);
8112 size(12);
8113 // Basic idea: lo(result) = lo(src * EAX)
8114 // hi(result) = hi(src * EAX) + lo(src * EDX)
8115 format %{ "IMUL $tmp,EDX,$src\n\t"
8116 "MOV EDX,$src\n\t"
8117 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8118 "ADD EDX,$tmp" %}
8119 ins_encode( long_multiply_con( dst, src, tmp ) );
8120 ins_pipe( pipe_slow );
8121 %}
8122
8123 // Integer DIV with Register
8124 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8125 match(Set rax (DivI rax div));
8126 effect(KILL rdx, KILL cr);
8127 size(26);
8128 ins_cost(30*100+10*100);
8129 format %{ "CMP EAX,0x80000000\n\t"
8130 "JNE,s normal\n\t"
8131 "XOR EDX,EDX\n\t"
8132 "CMP ECX,-1\n\t"
8133 "JE,s done\n"
8134 "normal: CDQ\n\t"
8135 "IDIV $div\n\t"
8136 "done:" %}
8137 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8138 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8139 ins_pipe( ialu_reg_reg_alu0 );
8140 %}
8141
8142 // Divide Register Long
8968 "XORL $y, $y\n"
8969 "done: " %}
8970 ins_encode %{
8971 Register Rp = $p$$Register;
8972 Register Rq = $q$$Register;
8973 Register Ry = $y$$Register;
8974 Label done;
8975 __ cmpl(Rp, Rq);
8976 __ jccb(Assembler::less, done);
8977 __ xorl(Ry, Ry);
8978 __ bind(done);
8979 %}
8980
8981 ins_pipe(pipe_cmplt);
8982 %}
8983
8984 /* If I enable this, I encourage spilling in the inner loop of compress.
8985 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8986 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8987 */
8988 //----------Overflow Math Instructions-----------------------------------------
8989
8990 instruct addofI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8991 %{
8992 match(Set cr (OverflowAddI op1 op2));
8993 effect(DEF cr, USE_KILL op1, USE op2);
8994
8995 format %{ "ADD $op1, $op2 #overflow check int" %}
8996
8997 ins_encode %{
8998 __ addl($op1$$Register, $op2$$Register);
8999 %}
9000 ins_pipe(ialu_reg_reg);
9001 %}
9002
9003 instruct addofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
9004 %{
9005 match(Set cr (OverflowAddI op1 op2));
9006 effect(DEF cr, USE_KILL op1, USE op2);
9007
9008 format %{ "ADD $op1, $op2 #overflow check int" %}
9009
9010 ins_encode %{
9011 __ addl($op1$$Register, $op2$$constant);
9012 %}
9013 ins_pipe(ialu_reg_reg);
9014 %}
9015
9016 instruct subofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9017 %{
9018 match(Set cr (OverflowSubI op1 op2));
9019 effect(DEF cr, USE op1, USE op2);
9020
9021 format %{ "CMP $op1, $op2 #overflow check int" %}
9022 ins_encode %{
9023 __ cmpl($op1$$Register, $op2$$Register);
9024 %}
9025 ins_pipe(ialu_reg_reg);
9026 %}
9027
9028 instruct subofI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
9029 %{
9030 match(Set cr (OverflowSubI op1 op2));
9031 effect(DEF cr, USE op1, USE op2);
9032
9033 format %{ "CMP $op1, $op2 #overflow check int" %}
9034 ins_encode %{
9035 __ cmpl($op1$$Register, $op2$$constant);
9036 %}
9037 ins_pipe(ialu_reg_reg);
9038 %}
9039
9040 instruct negofI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
9041 %{
9042 match(Set cr (OverflowSubI zero op2));
9043 effect(DEF cr, USE_KILL op2);
9044
9045 format %{ "NEG $op2 #overflow check int" %}
9046 ins_encode %{
9047 __ negl($op2$$Register);
9048 %}
9049 ins_pipe(ialu_reg_reg);
9050 %}
9051
9052 instruct mulofI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
9053 %{
9054 match(Set cr (OverflowMulI op1 op2));
9055 effect(DEF cr, USE_KILL op1, USE op2);
9056
9057 format %{ "IMUL $op1, $op2 #overflow check int" %}
9058 ins_encode %{
9059 __ imull($op1$$Register, $op2$$Register);
9060 %}
9061 ins_pipe(ialu_reg_reg_alu0);
9062 %}
9063
9064 instruct mulofI_rReg_imm(eFlagsReg cr, eAXRegI op1, rRegI op2, immI op3)
9065 %{
9066 match(Set cr (OverflowMulI op2 op3));
9067 effect(DEF cr, KILL op1, USE op2, USE op3);
9068
9069 format %{ "IMUL $op1, $op2, $op3 #overflow check int" %}
9070 ins_encode %{
9071 __ imull($op1$$Register, $op2$$Register, $op3$$constant);
9072 %}
9073 ins_pipe(ialu_reg_reg_alu0);
9074 %}
9075
9076 //----------Long Instructions------------------------------------------------
9077 // Add Long Register with Register
9078 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9079 match(Set dst (AddL dst src));
9080 effect(KILL cr);
9081 ins_cost(200);
9082 format %{ "ADD $dst.lo,$src.lo\n\t"
9083 "ADC $dst.hi,$src.hi" %}
9084 opcode(0x03, 0x13);
9085 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9086 ins_pipe( ialu_reg_reg_long );
9087 %}
9088
9089 // Add Long Register with Immediate
9090 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9091 match(Set dst (AddL dst src));
9092 effect(KILL cr);
9093 format %{ "ADD $dst.lo,$src.lo\n\t"
9094 "ADC $dst.hi,$src.hi" %}
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