1640
1641 // Register for MODI projection of divmodI
1642 RegMask Matcher::modI_proj_mask() {
1643 return INT_RDX_REG_mask();
1644 }
1645
1646 // Register for DIVL projection of divmodL
1647 RegMask Matcher::divL_proj_mask() {
1648 return LONG_RAX_REG_mask();
1649 }
1650
1651 // Register for MODL projection of divmodL
1652 RegMask Matcher::modL_proj_mask() {
1653 return LONG_RDX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1657 return PTR_RBP_REG_mask();
1658 }
1659
1660 const RegMask Matcher::mathExactI_result_proj_mask() {
1661 return INT_RAX_REG_mask();
1662 }
1663
1664 const RegMask Matcher::mathExactL_result_proj_mask() {
1665 return LONG_RAX_REG_mask();
1666 }
1667
1668 const RegMask Matcher::mathExactI_flags_proj_mask() {
1669 return INT_FLAGS_mask();
1670 }
1671
1672 %}
1673
1674 //----------ENCODING BLOCK-----------------------------------------------------
1675 // This block specifies the encoding classes used by the compiler to
1676 // output byte streams. Encoding classes are parameterized macros
1677 // used by Machine Instruction Nodes in order to generate the bit
1678 // encoding of the instruction. Operands specify their base encoding
1679 // interface with the interface keyword. There are currently
1680 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1681 // COND_INTER. REG_INTER causes an operand to generate a function
1682 // which returns its register number when queried. CONST_INTER causes
1683 // an operand to generate a function which returns the value of the
1684 // constant when queried. MEMORY_INTER causes an operand to generate
1685 // four functions which return the Base Register, the Index Register,
1686 // the Scale Value, and the Offset Value of the operand when queried.
1687 // COND_INTER causes an operand to generate six functions which return
1688 // the encoding code (ie - encoding bits for the instruction)
1689 // associated with each basic boolean condition for a conditional
1690 // instruction.
1691 //
6946 Label Lskip;
6947 // Invert sense of branch from sense of CMOV
6948 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6949 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6950 __ bind(Lskip);
6951 %}
6952 ins_pipe(pipe_slow);
6953 %}
6954
6955 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6956 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6957 ins_cost(200);
6958 expand %{
6959 cmovD_regU(cop, cr, dst, src);
6960 %}
6961 %}
6962
6963 //----------Arithmetic Instructions--------------------------------------------
6964 //----------Addition Instructions----------------------------------------------
6965
6966 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
6967 %{
6968 match(AddExactI dst src);
6969 effect(DEF cr);
6970
6971 format %{ "addl $dst, $src\t# addExact int" %}
6972 ins_encode %{
6973 __ addl($dst$$Register, $src$$Register);
6974 %}
6975 ins_pipe(ialu_reg_reg);
6976 %}
6977
6978 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6979 %{
6980 match(AddExactI dst src);
6981 effect(DEF cr);
6982
6983 format %{ "addl $dst, $src\t# addExact int" %}
6984 ins_encode %{
6985 __ addl($dst$$Register, $src$$constant);
6986 %}
6987 ins_pipe(ialu_reg_reg);
6988 %}
6989
6990 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6991 %{
6992 match(AddExactI dst (LoadI src));
6993 effect(DEF cr);
6994
6995 ins_cost(125); // XXX
6996 format %{ "addl $dst, $src\t# addExact int" %}
6997 ins_encode %{
6998 __ addl($dst$$Register, $src$$Address);
6999 %}
7000
7001 ins_pipe(ialu_reg_mem);
7002 %}
7003
7004 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7005 %{
7006 match(AddExactL dst src);
7007 effect(DEF cr);
7008
7009 format %{ "addq $dst, $src\t# addExact long" %}
7010 ins_encode %{
7011 __ addq($dst$$Register, $src$$Register);
7012 %}
7013 ins_pipe(ialu_reg_reg);
7014 %}
7015
7016 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7017 %{
7018 match(AddExactL dst src);
7019 effect(DEF cr);
7020
7021 format %{ "addq $dst, $src\t# addExact long" %}
7022 ins_encode %{
7023 __ addq($dst$$Register, $src$$constant);
7024 %}
7025 ins_pipe(ialu_reg_reg);
7026 %}
7027
7028 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7029 %{
7030 match(AddExactL dst (LoadL src));
7031 effect(DEF cr);
7032
7033 ins_cost(125); // XXX
7034 format %{ "addq $dst, $src\t# addExact long" %}
7035 ins_encode %{
7036 __ addq($dst$$Register, $src$$Address);
7037 %}
7038
7039 ins_pipe(ialu_reg_mem);
7040 %}
7041
7042 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7043 %{
7044 match(Set dst (AddI dst src));
7045 effect(KILL cr);
7046
7047 format %{ "addl $dst, $src\t# int" %}
7048 opcode(0x03);
7049 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7050 ins_pipe(ialu_reg_reg);
7051 %}
7052
7053 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7054 %{
7055 match(Set dst (AddI dst src));
7056 effect(KILL cr);
7057
7058 format %{ "addl $dst, $src\t# int" %}
7059 opcode(0x81, 0x00); /* /0 id */
7060 ins_encode(OpcSErm(dst, src), Con8or32(src));
7061 ins_pipe( ialu_reg );
7634
7635 ins_cost(150);
7636 format %{ "subl $dst, $src\t# int" %}
7637 opcode(0x29); /* Opcode 29 /r */
7638 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7639 ins_pipe(ialu_mem_reg);
7640 %}
7641
7642 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7643 %{
7644 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7645 effect(KILL cr);
7646
7647 ins_cost(125); // XXX
7648 format %{ "subl $dst, $src\t# int" %}
7649 opcode(0x81); /* Opcode 81 /5 id */
7650 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7651 ins_pipe(ialu_mem_imm);
7652 %}
7653
7654 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7655 %{
7656 match(SubExactI dst src);
7657 effect(DEF cr);
7658
7659 format %{ "subl $dst, $src\t# subExact int" %}
7660 ins_encode %{
7661 __ subl($dst$$Register, $src$$Register);
7662 %}
7663 ins_pipe(ialu_reg_reg);
7664 %}
7665
7666 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7667 %{
7668 match(SubExactI dst src);
7669 effect(DEF cr);
7670
7671 format %{ "subl $dst, $src\t# subExact int" %}
7672 ins_encode %{
7673 __ subl($dst$$Register, $src$$constant);
7674 %}
7675 ins_pipe(ialu_reg_reg);
7676 %}
7677
7678 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7679 %{
7680 match(SubExactI dst (LoadI src));
7681 effect(DEF cr);
7682
7683 ins_cost(125);
7684 format %{ "subl $dst, $src\t# subExact int" %}
7685 ins_encode %{
7686 __ subl($dst$$Register, $src$$Address);
7687 %}
7688 ins_pipe(ialu_reg_mem);
7689 %}
7690
7691 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7692 %{
7693 match(SubExactL dst src);
7694 effect(DEF cr);
7695
7696 format %{ "subq $dst, $src\t# subExact long" %}
7697 ins_encode %{
7698 __ subq($dst$$Register, $src$$Register);
7699 %}
7700 ins_pipe(ialu_reg_reg);
7701 %}
7702
7703 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7704 %{
7705 match(SubExactL dst (LoadL src));
7706 effect(DEF cr);
7707
7708 format %{ "subq $dst, $src\t# subExact long" %}
7709 ins_encode %{
7710 __ subq($dst$$Register, $src$$constant);
7711 %}
7712 ins_pipe(ialu_reg_reg);
7713 %}
7714
7715 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7716 %{
7717 match(SubExactI dst src);
7718 effect(DEF cr);
7719
7720 ins_cost(125);
7721 format %{ "subq $dst, $src\t# subExact long" %}
7722 ins_encode %{
7723 __ subq($dst$$Register, $src$$Address);
7724 %}
7725 ins_pipe(ialu_reg_mem);
7726 %}
7727
7728 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7729 %{
7730 match(Set dst (SubL dst src));
7731 effect(KILL cr);
7732
7733 format %{ "subq $dst, $src\t# long" %}
7734 opcode(0x2B);
7735 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7736 ins_pipe(ialu_reg_reg);
7737 %}
7738
7739 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7740 %{
7741 match(Set dst (SubL dst src));
7742 effect(KILL cr);
7743
7744 format %{ "subq $dst, $src\t# long" %}
7745 opcode(0x81, 0x05); /* Opcode 81 /5 */
7746 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7747 ins_pipe(ialu_reg);
7824 match(Set dst (SubL zero dst));
7825 effect(KILL cr);
7826
7827 format %{ "negq $dst\t# long" %}
7828 opcode(0xF7, 0x03); // Opcode F7 /3
7829 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7830 ins_pipe(ialu_reg);
7831 %}
7832
7833 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7834 %{
7835 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7836 effect(KILL cr);
7837
7838 format %{ "negq $dst\t# long" %}
7839 opcode(0xF7, 0x03); // Opcode F7 /3
7840 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7841 ins_pipe(ialu_reg);
7842 %}
7843
7844 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7845 %{
7846 match(NegExactI dst);
7847 effect(KILL cr);
7848
7849 format %{ "negl $dst\t# negExact int" %}
7850 ins_encode %{
7851 __ negl($dst$$Register);
7852 %}
7853 ins_pipe(ialu_reg);
7854 %}
7855
7856 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7857 %{
7858 match(NegExactL dst);
7859 effect(KILL cr);
7860
7861 format %{ "negq $dst\t# negExact long" %}
7862 ins_encode %{
7863 __ negq($dst$$Register);
7864 %}
7865 ins_pipe(ialu_reg);
7866 %}
7867
7868
7869 //----------Multiplication/Division Instructions-------------------------------
7870 // Integer Multiplication Instructions
7871 // Multiply Register
7872
7873 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7874 %{
7875 match(Set dst (MulI dst src));
7876 effect(KILL cr);
7877
7878 ins_cost(300);
7879 format %{ "imull $dst, $src\t# int" %}
7880 opcode(0x0F, 0xAF);
7881 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7882 ins_pipe(ialu_reg_reg_alu0);
7883 %}
7884
7885 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7886 %{
7887 match(Set dst (MulI src imm));
7888 effect(KILL cr);
7965 ins_cost(300);
7966 format %{ "imulq $dst, $src, $imm\t# long" %}
7967 opcode(0x69); /* 69 /r id */
7968 ins_encode(REX_reg_mem_wide(dst, src),
7969 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7970 ins_pipe(ialu_reg_mem_alu0);
7971 %}
7972
7973 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7974 %{
7975 match(Set dst (MulHiL src rax));
7976 effect(USE_KILL rax, KILL cr);
7977
7978 ins_cost(300);
7979 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7980 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7981 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7982 ins_pipe(ialu_reg_reg_alu0);
7983 %}
7984
7985
7986 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7987 %{
7988 match(MulExactI dst src);
7989 effect(DEF cr);
7990
7991 ins_cost(300);
7992 format %{ "imull $dst, $src\t# mulExact int" %}
7993 ins_encode %{
7994 __ imull($dst$$Register, $src$$Register);
7995 %}
7996 ins_pipe(ialu_reg_reg_alu0);
7997 %}
7998
7999
8000 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
8001 %{
8002 match(MulExactI src imm);
8003 effect(DEF cr);
8004
8005 ins_cost(300);
8006 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
8007 ins_encode %{
8008 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8009 %}
8010 ins_pipe(ialu_reg_reg_alu0);
8011 %}
8012
8013 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
8014 %{
8015 match(MulExactI dst (LoadI src));
8016 effect(DEF cr);
8017
8018 ins_cost(350);
8019 format %{ "imull $dst, $src\t# mulExact int" %}
8020 ins_encode %{
8021 __ imull($dst$$Register, $src$$Address);
8022 %}
8023 ins_pipe(ialu_reg_mem_alu0);
8024 %}
8025
8026 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
8027 %{
8028 match(MulExactL dst src);
8029 effect(DEF cr);
8030
8031 ins_cost(300);
8032 format %{ "imulq $dst, $src\t# mulExact long" %}
8033 ins_encode %{
8034 __ imulq($dst$$Register, $src$$Register);
8035 %}
8036 ins_pipe(ialu_reg_reg_alu0);
8037 %}
8038
8039 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8040 %{
8041 match(MulExactL src imm);
8042 effect(DEF cr);
8043
8044 ins_cost(300);
8045 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
8046 ins_encode %{
8047 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8048 %}
8049 ins_pipe(ialu_reg_reg_alu0);
8050 %}
8051
8052 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
8053 %{
8054 match(MulExactL dst (LoadL src));
8055 effect(DEF cr);
8056
8057 ins_cost(350);
8058 format %{ "imulq $dst, $src\t# mulExact long" %}
8059 ins_encode %{
8060 __ imulq($dst$$Register, $src$$Address);
8061 %}
8062 ins_pipe(ialu_reg_mem_alu0);
8063 %}
8064
8065 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8066 rFlagsReg cr)
8067 %{
8068 match(Set rax (DivI rax div));
8069 effect(KILL rdx, KILL cr);
8070
8071 ins_cost(30*100+10*100); // XXX
8072 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8073 "jne,s normal\n\t"
8074 "xorl rdx, rdx\n\t"
8075 "cmpl $div, -1\n\t"
8076 "je,s done\n"
8077 "normal: cdql\n\t"
8078 "idivl $div\n"
8079 "done:" %}
8080 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8081 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8082 ins_pipe(ialu_reg_reg_alu0);
8083 %}
8084
10651 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10652 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10653 %}
10654 ins_pipe( pipe_slow );
10655 %}
10656
10657 // encode char[] to byte[] in ISO_8859_1
10658 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10659 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10660 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10661 match(Set result (EncodeISOArray src (Binary dst len)));
10662 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10663
10664 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10665 ins_encode %{
10666 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10667 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10668 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10669 %}
10670 ins_pipe( pipe_slow );
10671 %}
10672
10673
10674 //----------Control Flow Instructions------------------------------------------
10675 // Signed compare Instructions
10676
10677 // XXX more variants!!
10678 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10679 %{
10680 match(Set cr (CmpI op1 op2));
10681 effect(DEF cr, USE op1, USE op2);
10682
10683 format %{ "cmpl $op1, $op2" %}
10684 opcode(0x3B); /* Opcode 3B /r */
10685 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10686 ins_pipe(ialu_cr_reg_reg);
10687 %}
10688
10689 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10690 %{
|
1640
1641 // Register for MODI projection of divmodI
1642 RegMask Matcher::modI_proj_mask() {
1643 return INT_RDX_REG_mask();
1644 }
1645
1646 // Register for DIVL projection of divmodL
1647 RegMask Matcher::divL_proj_mask() {
1648 return LONG_RAX_REG_mask();
1649 }
1650
1651 // Register for MODL projection of divmodL
1652 RegMask Matcher::modL_proj_mask() {
1653 return LONG_RDX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1657 return PTR_RBP_REG_mask();
1658 }
1659
1660 %}
1661
1662 //----------ENCODING BLOCK-----------------------------------------------------
1663 // This block specifies the encoding classes used by the compiler to
1664 // output byte streams. Encoding classes are parameterized macros
1665 // used by Machine Instruction Nodes in order to generate the bit
1666 // encoding of the instruction. Operands specify their base encoding
1667 // interface with the interface keyword. There are currently
1668 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1669 // COND_INTER. REG_INTER causes an operand to generate a function
1670 // which returns its register number when queried. CONST_INTER causes
1671 // an operand to generate a function which returns the value of the
1672 // constant when queried. MEMORY_INTER causes an operand to generate
1673 // four functions which return the Base Register, the Index Register,
1674 // the Scale Value, and the Offset Value of the operand when queried.
1675 // COND_INTER causes an operand to generate six functions which return
1676 // the encoding code (ie - encoding bits for the instruction)
1677 // associated with each basic boolean condition for a conditional
1678 // instruction.
1679 //
6934 Label Lskip;
6935 // Invert sense of branch from sense of CMOV
6936 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6937 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6938 __ bind(Lskip);
6939 %}
6940 ins_pipe(pipe_slow);
6941 %}
6942
6943 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6944 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6945 ins_cost(200);
6946 expand %{
6947 cmovD_regU(cop, cr, dst, src);
6948 %}
6949 %}
6950
6951 //----------Arithmetic Instructions--------------------------------------------
6952 //----------Addition Instructions----------------------------------------------
6953
6954 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6955 %{
6956 match(Set dst (AddI dst src));
6957 effect(KILL cr);
6958
6959 format %{ "addl $dst, $src\t# int" %}
6960 opcode(0x03);
6961 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6962 ins_pipe(ialu_reg_reg);
6963 %}
6964
6965 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6966 %{
6967 match(Set dst (AddI dst src));
6968 effect(KILL cr);
6969
6970 format %{ "addl $dst, $src\t# int" %}
6971 opcode(0x81, 0x00); /* /0 id */
6972 ins_encode(OpcSErm(dst, src), Con8or32(src));
6973 ins_pipe( ialu_reg );
7546
7547 ins_cost(150);
7548 format %{ "subl $dst, $src\t# int" %}
7549 opcode(0x29); /* Opcode 29 /r */
7550 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7551 ins_pipe(ialu_mem_reg);
7552 %}
7553
7554 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7555 %{
7556 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7557 effect(KILL cr);
7558
7559 ins_cost(125); // XXX
7560 format %{ "subl $dst, $src\t# int" %}
7561 opcode(0x81); /* Opcode 81 /5 id */
7562 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7563 ins_pipe(ialu_mem_imm);
7564 %}
7565
7566 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7567 %{
7568 match(Set dst (SubL dst src));
7569 effect(KILL cr);
7570
7571 format %{ "subq $dst, $src\t# long" %}
7572 opcode(0x2B);
7573 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7574 ins_pipe(ialu_reg_reg);
7575 %}
7576
7577 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7578 %{
7579 match(Set dst (SubL dst src));
7580 effect(KILL cr);
7581
7582 format %{ "subq $dst, $src\t# long" %}
7583 opcode(0x81, 0x05); /* Opcode 81 /5 */
7584 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7585 ins_pipe(ialu_reg);
7662 match(Set dst (SubL zero dst));
7663 effect(KILL cr);
7664
7665 format %{ "negq $dst\t# long" %}
7666 opcode(0xF7, 0x03); // Opcode F7 /3
7667 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7668 ins_pipe(ialu_reg);
7669 %}
7670
7671 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7672 %{
7673 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7674 effect(KILL cr);
7675
7676 format %{ "negq $dst\t# long" %}
7677 opcode(0xF7, 0x03); // Opcode F7 /3
7678 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7679 ins_pipe(ialu_reg);
7680 %}
7681
7682 //----------Multiplication/Division Instructions-------------------------------
7683 // Integer Multiplication Instructions
7684 // Multiply Register
7685
7686 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7687 %{
7688 match(Set dst (MulI dst src));
7689 effect(KILL cr);
7690
7691 ins_cost(300);
7692 format %{ "imull $dst, $src\t# int" %}
7693 opcode(0x0F, 0xAF);
7694 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7695 ins_pipe(ialu_reg_reg_alu0);
7696 %}
7697
7698 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7699 %{
7700 match(Set dst (MulI src imm));
7701 effect(KILL cr);
7778 ins_cost(300);
7779 format %{ "imulq $dst, $src, $imm\t# long" %}
7780 opcode(0x69); /* 69 /r id */
7781 ins_encode(REX_reg_mem_wide(dst, src),
7782 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7783 ins_pipe(ialu_reg_mem_alu0);
7784 %}
7785
7786 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7787 %{
7788 match(Set dst (MulHiL src rax));
7789 effect(USE_KILL rax, KILL cr);
7790
7791 ins_cost(300);
7792 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7793 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7794 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7795 ins_pipe(ialu_reg_reg_alu0);
7796 %}
7797
7798 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7799 rFlagsReg cr)
7800 %{
7801 match(Set rax (DivI rax div));
7802 effect(KILL rdx, KILL cr);
7803
7804 ins_cost(30*100+10*100); // XXX
7805 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7806 "jne,s normal\n\t"
7807 "xorl rdx, rdx\n\t"
7808 "cmpl $div, -1\n\t"
7809 "je,s done\n"
7810 "normal: cdql\n\t"
7811 "idivl $div\n"
7812 "done:" %}
7813 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7814 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7815 ins_pipe(ialu_reg_reg_alu0);
7816 %}
7817
10384 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10385 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10386 %}
10387 ins_pipe( pipe_slow );
10388 %}
10389
10390 // encode char[] to byte[] in ISO_8859_1
10391 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10392 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10393 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10394 match(Set result (EncodeISOArray src (Binary dst len)));
10395 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10396
10397 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10398 ins_encode %{
10399 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10400 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10401 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10402 %}
10403 ins_pipe( pipe_slow );
10404 %}
10405
10406 //----------Overflow Math Instructions-----------------------------------------
10407
10408 instruct addofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10409 %{
10410 match(Set cr (OverflowAddI op1 op2));
10411 effect(DEF cr, USE_KILL op1, USE op2);
10412
10413 format %{ "addl $op1, $op2 #overflow check int" %}
10414
10415 ins_encode %{
10416 __ addl($op1$$Register, $op2$$Register);
10417 %}
10418 ins_pipe(ialu_reg_reg);
10419 %}
10420
10421 instruct addofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10422 %{
10423 match(Set cr (OverflowAddI op1 op2));
10424 effect(DEF cr, USE_KILL op1, USE op2);
10425
10426 format %{ "addl $op1, $op2 #overflow check int" %}
10427
10428 ins_encode %{
10429 __ addl($op1$$Register, $op2$$constant);
10430 %}
10431 ins_pipe(ialu_reg_reg);
10432 %}
10433
10434 instruct addofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10435 %{
10436 match(Set cr (OverflowAddL op1 op2));
10437 effect(DEF cr, USE_KILL op1, USE op2);
10438
10439 format %{ "addq $op1, $op2 #overflow check long" %}
10440 ins_encode %{
10441 __ addq($op1$$Register, $op2$$Register);
10442 %}
10443 ins_pipe(ialu_reg_reg);
10444 %}
10445
10446 instruct addofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10447 %{
10448 match(Set cr (OverflowAddL op1 op2));
10449 effect(DEF cr, USE_KILL op1, USE op2);
10450 ins_encode %{
10451 __ addq($op1$$Register, $op2$$constant);
10452 %}
10453 ins_pipe(ialu_reg_reg);
10454 %}
10455
10456 instruct subofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10457 %{
10458 match(Set cr (OverflowSubI op1 op2));
10459 effect(DEF cr, USE op1, USE op2);
10460
10461 format %{ "cmpl $op1, $op2 #overflow check int" %}
10462 ins_encode %{
10463 __ cmpl($op1$$Register, $op2$$Register);
10464 %}
10465 ins_pipe(ialu_reg_reg);
10466 %}
10467
10468 instruct subofI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10469 %{
10470 match(Set cr (OverflowSubI op1 op2));
10471 effect(DEF cr, USE op1, USE op2);
10472
10473 format %{ "cmpl $op1, $op2 #overflow check int" %}
10474 ins_encode %{
10475 __ cmpl($op1$$Register, $op2$$constant);
10476 %}
10477 ins_pipe(ialu_reg_reg);
10478 %}
10479
10480 instruct subofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10481 %{
10482 match(Set cr (OverflowSubL op1 op2));
10483 effect(DEF cr, USE op1, USE op2);
10484
10485 format %{ "cmpq $op1, $op2 #overflow check long" %}
10486 ins_encode %{
10487 __ cmpq($op1$$Register, $op2$$Register);
10488 %}
10489 ins_pipe(ialu_reg_reg);
10490 %}
10491
10492 instruct subofL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10493 %{
10494 match(Set cr (OverflowSubL op1 op2));
10495 effect(DEF cr, USE op1, USE op2);
10496
10497 format %{ "cmpq $op1, $op2 #overflow check long" %}
10498 ins_encode %{
10499 __ cmpq($op1$$Register, $op2$$constant);
10500 %}
10501 ins_pipe(ialu_reg_reg);
10502 %}
10503
10504 instruct negofI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10505 %{
10506 match(Set cr (OverflowSubI zero op2));
10507 effect(DEF cr, USE_KILL op2);
10508
10509 format %{ "negl $op2 #overflow check int" %}
10510 ins_encode %{
10511 __ negl($op2$$Register);
10512 %}
10513 ins_pipe(ialu_reg_reg);
10514 %}
10515
10516 instruct negofL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10517 %{
10518 match(Set cr (OverflowSubL zero op2));
10519 effect(DEF cr, USE_KILL op2);
10520
10521 format %{ "negq $op2 #overflow check long" %}
10522 ins_encode %{
10523 __ negq($op2$$Register);
10524 %}
10525 ins_pipe(ialu_reg_reg);
10526 %}
10527
10528 instruct mulofI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10529 %{
10530 match(Set cr (OverflowMulI op1 op2));
10531 effect(DEF cr, USE_KILL op1, USE op2);
10532
10533 format %{ "imull $op1, $op2 #overflow check int" %}
10534 ins_encode %{
10535 __ imull($op1$$Register, $op2$$Register);
10536 %}
10537 ins_pipe(ialu_reg_reg_alu0);
10538 %}
10539
10540 instruct mulofI_rReg_imm(rFlagsReg cr, rax_RegI op1, rRegI op2, immI op3)
10541 %{
10542 match(Set cr (OverflowMulI op2 op3));
10543 effect(DEF cr, KILL op1, USE op2, USE op3);
10544
10545 format %{ "imull $op1, $op2, $op3 #overflow check int" %}
10546 ins_encode %{
10547 __ imull($op1$$Register, $op2$$Register, $op3$$constant);
10548 %}
10549 ins_pipe(ialu_reg_reg_alu0);
10550 %}
10551
10552 instruct mulofL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10553 %{
10554 match(Set cr (OverflowMulL op1 op2));
10555 effect(DEF cr, USE_KILL op1, USE op2);
10556
10557 format %{ "imulq $op1, $op2 #overflow check long" %}
10558 ins_encode %{
10559 __ imulq($op1$$Register, $op2$$Register);
10560 %}
10561 ins_pipe(ialu_reg_reg_alu0);
10562 %}
10563
10564 instruct mulofL_rReg_imm(rFlagsReg cr, rax_RegL op1, rRegL op2, immL32 op3)
10565 %{
10566 match(Set cr (OverflowMulL op2 op3));
10567 effect(DEF cr, KILL op1, USE op2, USE op3);
10568
10569 format %{ "imulq $op1, $op2 #overflow check long" %}
10570 ins_encode %{
10571 __ imulq($op1$$Register, $op2$$Register, $op3$$constant);
10572 %}
10573 ins_pipe(ialu_reg_reg_alu0);
10574 %}
10575
10576
10577 //----------Control Flow Instructions------------------------------------------
10578 // Signed compare Instructions
10579
10580 // XXX more variants!!
10581 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10582 %{
10583 match(Set cr (CmpI op1 op2));
10584 effect(DEF cr, USE op1, USE op2);
10585
10586 format %{ "cmpl $op1, $op2" %}
10587 opcode(0x3B); /* Opcode 3B /r */
10588 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10589 ins_pipe(ialu_cr_reg_reg);
10590 %}
10591
10592 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10593 %{
|